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Fix attempt to inline recursive functions.
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
ee4e83ed 27#include "host-utils.h"
237c0af0 28
3fc6c082
FB		 29//#define PPC_DUMP_CPU
30//#define PPC_DEBUG_SPR
80d11f44
JM		 31//#define PPC_DUMP_SPR_ACCESSES
32#if defined(CONFIG_USER_ONLY)
33#define TODO_USER_ONLY 1
34#endif
3fc6c082
FB		 35
36struct ppc_def_t {
37 const unsigned char *name;
38 uint32_t pvr;
80d11f44 39 uint32_t svr;
0487d6a8 40 uint64_t insns_flags;
3fc6c082 41 uint64_t msr_mask;
7820dbf3
JM		 42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
d26bfc9a 45 uint32_t flags;
237c0af0 46 int bfd_mach;
a750fc0b 47 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 48 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 49};
50
e9df014c
JM		 51/* For user-mode emulation, we don't emulate any IRQ controller */
52#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 53#define PPC_IRQ_INIT_FN(name) \
54static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55{ \
e9df014c
JM		 56}
57#else
a750fc0b 58#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 59void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60#endif
a750fc0b 61
4e290a0b 62PPC_IRQ_INIT_FN(40x);
e9df014c 63PPC_IRQ_INIT_FN(6xx);
d0dfae6e 64PPC_IRQ_INIT_FN(970);
e9df014c 65
3fc6c082
FB		 66/* Generic callbacks:
67 * do nothing but store/retrieve spr value
68 */
04f20795 69#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 70static void spr_read_generic (void *opaque, int sprn)
71{
04f20795 72 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 73}
74
75static void spr_write_generic (void *opaque, int sprn)
76{
04f20795 77 gen_op_store_dump_spr(sprn);
3fc6c082 78}
04f20795
JM		 79#else
80static void spr_read_generic (void *opaque, int sprn)
a496775f 81{
04f20795 82 gen_op_load_spr(sprn);
a496775f
JM		 83}
84
04f20795 85static void spr_write_generic (void *opaque, int sprn)
a496775f 86{
04f20795 87 gen_op_store_spr(sprn);
a496775f 88}
04f20795 89#endif
a496775f
JM		 90
91#if !defined(CONFIG_USER_ONLY)
92static void spr_write_clear (void *opaque, int sprn)
93{
94 gen_op_mask_spr(sprn);
95}
96#endif
97
76a66253 98/* SPR common to all PowerPC */
3fc6c082
FB		 99/* XER */
100static void spr_read_xer (void *opaque, int sprn)
101{
102 gen_op_load_xer();
103}
104
105static void spr_write_xer (void *opaque, int sprn)
106{
107 gen_op_store_xer();
108}
109
110/* LR */
111static void spr_read_lr (void *opaque, int sprn)
112{
113 gen_op_load_lr();
114}
115
116static void spr_write_lr (void *opaque, int sprn)
117{
118 gen_op_store_lr();
119}
120
121/* CTR */
122static void spr_read_ctr (void *opaque, int sprn)
123{
124 gen_op_load_ctr();
125}
126
127static void spr_write_ctr (void *opaque, int sprn)
128{
129 gen_op_store_ctr();
130}
131
132/* User read access to SPR */
133/* USPRx */
134/* UMMCRx */
135/* UPMCx */
136/* USIA */
137/* UDECR */
138static void spr_read_ureg (void *opaque, int sprn)
139{
140 gen_op_load_spr(sprn + 0x10);
141}
142
76a66253 143/* SPR common to all non-embedded PowerPC */
3fc6c082 144/* DECR */
76a66253 145#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 146static void spr_read_decr (void *opaque, int sprn)
147{
148 gen_op_load_decr();
149}
150
151static void spr_write_decr (void *opaque, int sprn)
152{
153 gen_op_store_decr();
154}
76a66253 155#endif
3fc6c082 156
76a66253 157/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 158/* Time base */
159static void spr_read_tbl (void *opaque, int sprn)
160{
161 gen_op_load_tbl();
162}
163
76a66253 164static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 165{
76a66253 166 gen_op_load_tbu();
3fc6c082
FB		 167}
168
a062e36c
JM		 169__attribute__ (( unused ))
170static void spr_read_atbl (void *opaque, int sprn)
171{
172 gen_op_load_atbl();
173}
174
175__attribute__ (( unused ))
176static void spr_read_atbu (void *opaque, int sprn)
177{
178 gen_op_load_atbu();
179}
180
76a66253
JM		 181#if !defined(CONFIG_USER_ONLY)
182static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 183{
76a66253 184 gen_op_store_tbl();
3fc6c082
FB		 185}
186
187static void spr_write_tbu (void *opaque, int sprn)
188{
189 gen_op_store_tbu();
190}
a062e36c
JM		 191
192__attribute__ (( unused ))
193static void spr_write_atbl (void *opaque, int sprn)
194{
195 gen_op_store_atbl();
196}
197
198__attribute__ (( unused ))
199static void spr_write_atbu (void *opaque, int sprn)
200{
201 gen_op_store_atbu();
202}
76a66253 203#endif
3fc6c082 204
76a66253 205#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 206/* IBAT0U...IBAT0U */
207/* IBAT0L...IBAT7L */
208static void spr_read_ibat (void *opaque, int sprn)
209{
210 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
211}
212
213static void spr_read_ibat_h (void *opaque, int sprn)
214{
215 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
216}
217
218static void spr_write_ibatu (void *opaque, int sprn)
219{
3fc6c082 220 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 221}
222
223static void spr_write_ibatu_h (void *opaque, int sprn)
224{
3fc6c082 225 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 226}
227
228static void spr_write_ibatl (void *opaque, int sprn)
229{
3fc6c082 230 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 231}
232
233static void spr_write_ibatl_h (void *opaque, int sprn)
234{
3fc6c082 235 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 236}
237
238/* DBAT0U...DBAT7U */
239/* DBAT0L...DBAT7L */
240static void spr_read_dbat (void *opaque, int sprn)
241{
242 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
243}
244
245static void spr_read_dbat_h (void *opaque, int sprn)
246{
2e13d23a 247 gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
3fc6c082
FB		 248}
249
250static void spr_write_dbatu (void *opaque, int sprn)
251{
3fc6c082 252 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 253}
254
255static void spr_write_dbatu_h (void *opaque, int sprn)
256{
2e13d23a 257 gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
3fc6c082
FB		 258}
259
260static void spr_write_dbatl (void *opaque, int sprn)
261{
3fc6c082 262 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 263}
264
265static void spr_write_dbatl_h (void *opaque, int sprn)
266{
2e13d23a 267 gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
3fc6c082
FB		 268}
269
270/* SDR1 */
271static void spr_read_sdr1 (void *opaque, int sprn)
272{
273 gen_op_load_sdr1();
274}
275
276static void spr_write_sdr1 (void *opaque, int sprn)
277{
3fc6c082 278 gen_op_store_sdr1();
3fc6c082
FB		 279}
280
76a66253
JM		 281/* 64 bits PowerPC specific SPRs */
282/* ASR */
578bb252
JM		 283#if defined(TARGET_PPC64)
284__attribute__ (( unused ))
76a66253
JM		 285static void spr_read_asr (void *opaque, int sprn)
286{
287 gen_op_load_asr();
288}
289
578bb252 290__attribute__ (( unused ))
76a66253
JM		 291static void spr_write_asr (void *opaque, int sprn)
292{
76a66253 293 gen_op_store_asr();
76a66253
JM		 294}
295#endif
a750fc0b 296#endif
76a66253
JM		 297
298/* PowerPC 601 specific registers */
299/* RTC */
300static void spr_read_601_rtcl (void *opaque, int sprn)
301{
302 gen_op_load_601_rtcl();
303}
304
305static void spr_read_601_rtcu (void *opaque, int sprn)
306{
307 gen_op_load_601_rtcu();
308}
309
310#if !defined(CONFIG_USER_ONLY)
311static void spr_write_601_rtcu (void *opaque, int sprn)
312{
313 gen_op_store_601_rtcu();
314}
315
316static void spr_write_601_rtcl (void *opaque, int sprn)
317{
318 gen_op_store_601_rtcl();
319}
056401ea
JM		 320
321static void spr_write_hid0_601 (void *opaque, int sprn)
322{
323 DisasContext *ctx = opaque;
324
325 gen_op_store_hid0_601();
326 /* Must stop the translation as endianness may have changed */
327 GEN_STOP(ctx);
328}
76a66253
JM		 329#endif
330
331/* Unified bats */
332#if !defined(CONFIG_USER_ONLY)
333static void spr_read_601_ubat (void *opaque, int sprn)
334{
335 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
336}
337
338static void spr_write_601_ubatu (void *opaque, int sprn)
339{
76a66253 340 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 341}
342
343static void spr_write_601_ubatl (void *opaque, int sprn)
344{
76a66253 345 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 346}
347#endif
348
349/* PowerPC 40x specific registers */
350#if !defined(CONFIG_USER_ONLY)
351static void spr_read_40x_pit (void *opaque, int sprn)
352{
353 gen_op_load_40x_pit();
354}
355
356static void spr_write_40x_pit (void *opaque, int sprn)
357{
358 gen_op_store_40x_pit();
359}
360
8ecc7913
JM		 361static void spr_write_40x_dbcr0 (void *opaque, int sprn)
362{
363 DisasContext *ctx = opaque;
364
365 gen_op_store_40x_dbcr0();
366 /* We must stop translation as we may have rebooted */
e1833e1f 367 GEN_STOP(ctx);
8ecc7913
JM		 368}
369
c294fc58
JM		 370static void spr_write_40x_sler (void *opaque, int sprn)
371{
c294fc58 372 gen_op_store_40x_sler();
c294fc58
JM		 373}
374
76a66253
JM		 375static void spr_write_booke_tcr (void *opaque, int sprn)
376{
377 gen_op_store_booke_tcr();
378}
379
380static void spr_write_booke_tsr (void *opaque, int sprn)
381{
382 gen_op_store_booke_tsr();
383}
384#endif
385
386/* PowerPC 403 specific registers */
387/* PBL1 / PBU1 / PBL2 / PBU2 */
388#if !defined(CONFIG_USER_ONLY)
389static void spr_read_403_pbr (void *opaque, int sprn)
390{
391 gen_op_load_403_pb(sprn - SPR_403_PBL1);
392}
393
394static void spr_write_403_pbr (void *opaque, int sprn)
395{
76a66253 396 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 397}
398
3fc6c082
FB		 399static void spr_write_pir (void *opaque, int sprn)
400{
401 gen_op_store_pir();
402}
76a66253 403#endif
3fc6c082 404
6f5d427d
JM		 405#if !defined(CONFIG_USER_ONLY)
406/* Callback used to write the exception vector base */
407static void spr_write_excp_prefix (void *opaque, int sprn)
408{
409 gen_op_store_excp_prefix();
410 gen_op_store_spr(sprn);
411}
412
413static void spr_write_excp_vector (void *opaque, int sprn)
414{
415 DisasContext *ctx = opaque;
416
417 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
418 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
419 gen_op_store_spr(sprn);
420 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
421 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
422 gen_op_store_spr(sprn);
423 } else {
424 printf("Trying to write an unknown exception vector %d %03x\n",
425 sprn, sprn);
426 GEN_EXCP_PRIVREG(ctx);
427 }
428}
429#endif
430
76a66253
JM		 431#if defined(CONFIG_USER_ONLY)
432#define spr_register(env, num, name, uea_read, uea_write, \
433 oea_read, oea_write, initial_value) \
434do { \
435 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
436} while (0)
437static inline void _spr_register (CPUPPCState *env, int num,
438 const unsigned char *name,
439 void (*uea_read)(void *opaque, int sprn),
440 void (*uea_write)(void *opaque, int sprn),
441 target_ulong initial_value)
442#else
3fc6c082
FB		 443static inline void spr_register (CPUPPCState *env, int num,
444 const unsigned char *name,
445 void (*uea_read)(void *opaque, int sprn),
446 void (*uea_write)(void *opaque, int sprn),
447 void (*oea_read)(void *opaque, int sprn),
448 void (*oea_write)(void *opaque, int sprn),
449 target_ulong initial_value)
76a66253 450#endif
3fc6c082
FB		 451{
452 ppc_spr_t *spr;
453
454 spr = &env->spr_cb[num];
455 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 456#if !defined(CONFIG_USER_ONLY)
457 spr->oea_read != NULL || spr->oea_write != NULL ||
458#endif
459 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 460 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
461 exit(1);
462 }
463#if defined(PPC_DEBUG_SPR)
1b9eb036 464 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 465 initial_value);
3fc6c082
FB		 466#endif
467 spr->name = name;
468 spr->uea_read = uea_read;
469 spr->uea_write = uea_write;
76a66253 470#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 471 spr->oea_read = oea_read;
472 spr->oea_write = oea_write;
76a66253 473#endif
3fc6c082
FB		 474 env->spr[num] = initial_value;
475}
476
477/* Generic PowerPC SPRs */
478static void gen_spr_generic (CPUPPCState *env)
479{
480 /* Integer processing */
481 spr_register(env, SPR_XER, "XER",
482 &spr_read_xer, &spr_write_xer,
483 &spr_read_xer, &spr_write_xer,
484 0x00000000);
485 /* Branch contol */
486 spr_register(env, SPR_LR, "LR",
487 &spr_read_lr, &spr_write_lr,
488 &spr_read_lr, &spr_write_lr,
489 0x00000000);
490 spr_register(env, SPR_CTR, "CTR",
491 &spr_read_ctr, &spr_write_ctr,
492 &spr_read_ctr, &spr_write_ctr,
493 0x00000000);
494 /* Interrupt processing */
495 spr_register(env, SPR_SRR0, "SRR0",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 spr_register(env, SPR_SRR1, "SRR1",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 /* Processor control */
504 spr_register(env, SPR_SPRG0, "SPRG0",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508 spr_register(env, SPR_SPRG1, "SPRG1",
509 SPR_NOACCESS, SPR_NOACCESS,
510 &spr_read_generic, &spr_write_generic,
511 0x00000000);
512 spr_register(env, SPR_SPRG2, "SPRG2",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516 spr_register(env, SPR_SPRG3, "SPRG3",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520}
521
522/* SPR common to all non-embedded PowerPC, including 601 */
523static void gen_spr_ne_601 (CPUPPCState *env)
524{
525 /* Exception processing */
526 spr_register(env, SPR_DSISR, "DSISR",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530 spr_register(env, SPR_DAR, "DAR",
531 SPR_NOACCESS, SPR_NOACCESS,
532 &spr_read_generic, &spr_write_generic,
533 0x00000000);
534 /* Timer */
535 spr_register(env, SPR_DECR, "DECR",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_decr, &spr_write_decr,
538 0x00000000);
539 /* Memory management */
540 spr_register(env, SPR_SDR1, "SDR1",
541 SPR_NOACCESS, SPR_NOACCESS,
542 &spr_read_sdr1, &spr_write_sdr1,
543 0x00000000);
544}
545
546/* BATs 0-3 */
547static void gen_low_BATs (CPUPPCState *env)
548{
f2e63a42 549#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 550 spr_register(env, SPR_IBAT0U, "IBAT0U",
551 SPR_NOACCESS, SPR_NOACCESS,
552 &spr_read_ibat, &spr_write_ibatu,
553 0x00000000);
554 spr_register(env, SPR_IBAT0L, "IBAT0L",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_ibat, &spr_write_ibatl,
557 0x00000000);
558 spr_register(env, SPR_IBAT1U, "IBAT1U",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_ibat, &spr_write_ibatu,
561 0x00000000);
562 spr_register(env, SPR_IBAT1L, "IBAT1L",
563 SPR_NOACCESS, SPR_NOACCESS,
564 &spr_read_ibat, &spr_write_ibatl,
565 0x00000000);
566 spr_register(env, SPR_IBAT2U, "IBAT2U",
567 SPR_NOACCESS, SPR_NOACCESS,
568 &spr_read_ibat, &spr_write_ibatu,
569 0x00000000);
570 spr_register(env, SPR_IBAT2L, "IBAT2L",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_ibat, &spr_write_ibatl,
573 0x00000000);
574 spr_register(env, SPR_IBAT3U, "IBAT3U",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_ibat, &spr_write_ibatu,
577 0x00000000);
578 spr_register(env, SPR_IBAT3L, "IBAT3L",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_ibat, &spr_write_ibatl,
581 0x00000000);
582 spr_register(env, SPR_DBAT0U, "DBAT0U",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_dbat, &spr_write_dbatu,
585 0x00000000);
586 spr_register(env, SPR_DBAT0L, "DBAT0L",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_dbat, &spr_write_dbatl,
589 0x00000000);
590 spr_register(env, SPR_DBAT1U, "DBAT1U",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_dbat, &spr_write_dbatu,
593 0x00000000);
594 spr_register(env, SPR_DBAT1L, "DBAT1L",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_dbat, &spr_write_dbatl,
597 0x00000000);
598 spr_register(env, SPR_DBAT2U, "DBAT2U",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_dbat, &spr_write_dbatu,
601 0x00000000);
602 spr_register(env, SPR_DBAT2L, "DBAT2L",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_dbat, &spr_write_dbatl,
605 0x00000000);
606 spr_register(env, SPR_DBAT3U, "DBAT3U",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_dbat, &spr_write_dbatu,
609 0x00000000);
610 spr_register(env, SPR_DBAT3L, "DBAT3L",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_dbat, &spr_write_dbatl,
613 0x00000000);
a750fc0b 614 env->nb_BATs += 4;
f2e63a42 615#endif
3fc6c082
FB		 616}
617
618/* BATs 4-7 */
619static void gen_high_BATs (CPUPPCState *env)
620{
f2e63a42 621#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 622 spr_register(env, SPR_IBAT4U, "IBAT4U",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatu_h,
625 0x00000000);
626 spr_register(env, SPR_IBAT4L, "IBAT4L",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatl_h,
629 0x00000000);
630 spr_register(env, SPR_IBAT5U, "IBAT5U",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat_h, &spr_write_ibatu_h,
633 0x00000000);
634 spr_register(env, SPR_IBAT5L, "IBAT5L",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_ibat_h, &spr_write_ibatl_h,
637 0x00000000);
638 spr_register(env, SPR_IBAT6U, "IBAT6U",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_ibat_h, &spr_write_ibatu_h,
641 0x00000000);
642 spr_register(env, SPR_IBAT6L, "IBAT6L",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_ibat_h, &spr_write_ibatl_h,
645 0x00000000);
646 spr_register(env, SPR_IBAT7U, "IBAT7U",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_ibat_h, &spr_write_ibatu_h,
649 0x00000000);
650 spr_register(env, SPR_IBAT7L, "IBAT7L",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_ibat_h, &spr_write_ibatl_h,
653 0x00000000);
654 spr_register(env, SPR_DBAT4U, "DBAT4U",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatu_h,
657 0x00000000);
658 spr_register(env, SPR_DBAT4L, "DBAT4L",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatl_h,
661 0x00000000);
662 spr_register(env, SPR_DBAT5U, "DBAT5U",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat_h, &spr_write_dbatu_h,
665 0x00000000);
666 spr_register(env, SPR_DBAT5L, "DBAT5L",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_dbat_h, &spr_write_dbatl_h,
669 0x00000000);
670 spr_register(env, SPR_DBAT6U, "DBAT6U",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_dbat_h, &spr_write_dbatu_h,
673 0x00000000);
674 spr_register(env, SPR_DBAT6L, "DBAT6L",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_dbat_h, &spr_write_dbatl_h,
677 0x00000000);
678 spr_register(env, SPR_DBAT7U, "DBAT7U",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_dbat_h, &spr_write_dbatu_h,
681 0x00000000);
682 spr_register(env, SPR_DBAT7L, "DBAT7L",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_dbat_h, &spr_write_dbatl_h,
685 0x00000000);
a750fc0b 686 env->nb_BATs += 4;
f2e63a42 687#endif
3fc6c082
FB		 688}
689
690/* Generic PowerPC time base */
691static void gen_tbl (CPUPPCState *env)
692{
693 spr_register(env, SPR_VTBL, "TBL",
694 &spr_read_tbl, SPR_NOACCESS,
695 &spr_read_tbl, SPR_NOACCESS,
696 0x00000000);
697 spr_register(env, SPR_TBL, "TBL",
698 SPR_NOACCESS, SPR_NOACCESS,
699 SPR_NOACCESS, &spr_write_tbl,
700 0x00000000);
701 spr_register(env, SPR_VTBU, "TBU",
702 &spr_read_tbu, SPR_NOACCESS,
703 &spr_read_tbu, SPR_NOACCESS,
704 0x00000000);
705 spr_register(env, SPR_TBU, "TBU",
706 SPR_NOACCESS, SPR_NOACCESS,
707 SPR_NOACCESS, &spr_write_tbu,
708 0x00000000);
709}
710
76a66253
JM		 711/* Softare table search registers */
712static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
713{
f2e63a42 714#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 715 env->nb_tlb = nb_tlbs;
716 env->nb_ways = nb_ways;
717 env->id_tlbs = 1;
718 spr_register(env, SPR_DMISS, "DMISS",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, SPR_NOACCESS,
721 0x00000000);
722 spr_register(env, SPR_DCMP, "DCMP",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, SPR_NOACCESS,
725 0x00000000);
726 spr_register(env, SPR_HASH1, "HASH1",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, SPR_NOACCESS,
729 0x00000000);
730 spr_register(env, SPR_HASH2, "HASH2",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, SPR_NOACCESS,
733 0x00000000);
734 spr_register(env, SPR_IMISS, "IMISS",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, SPR_NOACCESS,
737 0x00000000);
738 spr_register(env, SPR_ICMP, "ICMP",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, SPR_NOACCESS,
741 0x00000000);
742 spr_register(env, SPR_RPA, "RPA",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 0x00000000);
f2e63a42 746#endif
76a66253
JM		 747}
748
749/* SPR common to MPC755 and G2 */
750static void gen_spr_G2_755 (CPUPPCState *env)
751{
752 /* SGPRs */
753 spr_register(env, SPR_SPRG4, "SPRG4",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 spr_register(env, SPR_SPRG5, "SPRG5",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_SPRG6, "SPRG6",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 spr_register(env, SPR_SPRG7, "SPRG7",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
768 0x00000000);
769 /* External access control */
770 /* XXX : not implemented */
771 spr_register(env, SPR_EAR, "EAR",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_generic, &spr_write_generic,
774 0x00000000);
775}
776
3fc6c082
FB		 777/* SPR common to all 7xx PowerPC implementations */
778static void gen_spr_7xx (CPUPPCState *env)
779{
780 /* Breakpoints */
781 /* XXX : not implemented */
782 spr_register(env, SPR_DABR, "DABR",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, &spr_write_generic,
785 0x00000000);
786 /* XXX : not implemented */
787 spr_register(env, SPR_IABR, "IABR",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_generic, &spr_write_generic,
790 0x00000000);
791 /* Cache management */
792 /* XXX : not implemented */
793 spr_register(env, SPR_ICTC, "ICTC",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_generic, &spr_write_generic,
796 0x00000000);
76a66253
JM		 797 /* XXX : not implemented */
798 spr_register(env, SPR_L2CR, "L2CR",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
3fc6c082
FB		 802 /* Performance monitors */
803 /* XXX : not implemented */
804 spr_register(env, SPR_MMCR0, "MMCR0",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 /* XXX : not implemented */
809 spr_register(env, SPR_MMCR1, "MMCR1",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_generic, &spr_write_generic,
812 0x00000000);
813 /* XXX : not implemented */
814 spr_register(env, SPR_PMC1, "PMC1",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, &spr_write_generic,
817 0x00000000);
818 /* XXX : not implemented */
819 spr_register(env, SPR_PMC2, "PMC2",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_generic, &spr_write_generic,
822 0x00000000);
823 /* XXX : not implemented */
824 spr_register(env, SPR_PMC3, "PMC3",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828 /* XXX : not implemented */
829 spr_register(env, SPR_PMC4, "PMC4",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_generic, &spr_write_generic,
832 0x00000000);
833 /* XXX : not implemented */
a750fc0b 834 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, SPR_NOACCESS,
837 0x00000000);
578bb252 838 /* XXX : not implemented */
3fc6c082
FB		 839 spr_register(env, SPR_UMMCR0, "UMMCR0",
840 &spr_read_ureg, SPR_NOACCESS,
841 &spr_read_ureg, SPR_NOACCESS,
842 0x00000000);
578bb252 843 /* XXX : not implemented */
3fc6c082
FB		 844 spr_register(env, SPR_UMMCR1, "UMMCR1",
845 &spr_read_ureg, SPR_NOACCESS,
846 &spr_read_ureg, SPR_NOACCESS,
847 0x00000000);
578bb252 848 /* XXX : not implemented */
3fc6c082
FB		 849 spr_register(env, SPR_UPMC1, "UPMC1",
850 &spr_read_ureg, SPR_NOACCESS,
851 &spr_read_ureg, SPR_NOACCESS,
852 0x00000000);
578bb252 853 /* XXX : not implemented */
3fc6c082
FB		 854 spr_register(env, SPR_UPMC2, "UPMC2",
855 &spr_read_ureg, SPR_NOACCESS,
856 &spr_read_ureg, SPR_NOACCESS,
857 0x00000000);
578bb252 858 /* XXX : not implemented */
3fc6c082
FB		 859 spr_register(env, SPR_UPMC3, "UPMC3",
860 &spr_read_ureg, SPR_NOACCESS,
861 &spr_read_ureg, SPR_NOACCESS,
862 0x00000000);
578bb252 863 /* XXX : not implemented */
3fc6c082
FB		 864 spr_register(env, SPR_UPMC4, "UPMC4",
865 &spr_read_ureg, SPR_NOACCESS,
866 &spr_read_ureg, SPR_NOACCESS,
867 0x00000000);
578bb252 868 /* XXX : not implemented */
a750fc0b 869 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 870 &spr_read_ureg, SPR_NOACCESS,
871 &spr_read_ureg, SPR_NOACCESS,
872 0x00000000);
a750fc0b 873 /* External access control */
3fc6c082 874 /* XXX : not implemented */
a750fc0b 875 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, &spr_write_generic,
878 0x00000000);
a750fc0b
JM		 879}
880
881static void gen_spr_thrm (CPUPPCState *env)
882{
883 /* Thermal management */
3fc6c082 884 /* XXX : not implemented */
a750fc0b 885 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 /* XXX : not implemented */
a750fc0b 890 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
3fc6c082 894 /* XXX : not implemented */
a750fc0b 895 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899}
900
901/* SPR specific to PowerPC 604 implementation */
902static void gen_spr_604 (CPUPPCState *env)
903{
904 /* Processor identification */
905 spr_register(env, SPR_PIR, "PIR",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_pir,
908 0x00000000);
909 /* Breakpoints */
910 /* XXX : not implemented */
911 spr_register(env, SPR_IABR, "IABR",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* XXX : not implemented */
916 spr_register(env, SPR_DABR, "DABR",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 /* Performance counters */
921 /* XXX : not implemented */
922 spr_register(env, SPR_MMCR0, "MMCR0",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 /* XXX : not implemented */
927 spr_register(env, SPR_MMCR1, "MMCR1",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_PMC1, "PMC1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* XXX : not implemented */
937 spr_register(env, SPR_PMC2, "PMC2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_PMC3, "PMC3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* XXX : not implemented */
947 spr_register(env, SPR_PMC4, "PMC4",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 /* XXX : not implemented */
a750fc0b 952 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, SPR_NOACCESS,
955 0x00000000);
956 /* XXX : not implemented */
957 spr_register(env, SPR_SDA, "SDA",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, SPR_NOACCESS,
960 0x00000000);
961 /* External access control */
962 /* XXX : not implemented */
963 spr_register(env, SPR_EAR, "EAR",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967}
968
76a66253
JM		 969/* SPR specific to PowerPC 603 implementation */
970static void gen_spr_603 (CPUPPCState *env)
3fc6c082 971{
76a66253
JM		 972 /* External access control */
973 /* XXX : not implemented */
974 spr_register(env, SPR_EAR, "EAR",
3fc6c082 975 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
3fc6c082
FB		 978}
979
76a66253
JM		 980/* SPR specific to PowerPC G2 implementation */
981static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 982{
76a66253
JM		 983 /* Memory base address */
984 /* MBAR */
578bb252 985 /* XXX : not implemented */
76a66253
JM		 986 spr_register(env, SPR_MBAR, "MBAR",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
76a66253 990 /* Exception processing */
363be49c 991 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
363be49c 995 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 /* Breakpoints */
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_DABR, "DABR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_DABR2, "DABR2",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_IABR, "IABR",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_IABR2, "IABR2",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_IBCR, "IBCR",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_DBCR, "DBCR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030}
1031
1032/* SPR specific to PowerPC 602 implementation */
1033static void gen_spr_602 (CPUPPCState *env)
1034{
1035 /* ESA registers */
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_SER, "SER",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_SEBR, "SEBR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
a750fc0b 1047 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* Floating point status */
1052 /* XXX : not implemented */
1053 spr_register(env, SPR_SP, "SP",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, &spr_write_generic,
1056 0x00000000);
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_LT, "LT",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* Watchdog timer */
1063 /* XXX : not implemented */
1064 spr_register(env, SPR_TCR, "TCR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 /* Interrupt base */
1069 spr_register(env, SPR_IBR, "IBR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
a750fc0b
JM		 1073 /* XXX : not implemented */
1074 spr_register(env, SPR_IABR, "IABR",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
76a66253
JM		 1078}
1079
1080/* SPR specific to PowerPC 601 implementation */
1081static void gen_spr_601 (CPUPPCState *env)
1082{
1083 /* Multiplication/division register */
1084 /* MQ */
1085 spr_register(env, SPR_MQ, "MQ",
1086 &spr_read_generic, &spr_write_generic,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 /* RTC registers */
1090 spr_register(env, SPR_601_RTCU, "RTCU",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 SPR_NOACCESS, &spr_write_601_rtcu,
1093 0x00000000);
1094 spr_register(env, SPR_601_VRTCU, "RTCU",
1095 &spr_read_601_rtcu, SPR_NOACCESS,
1096 &spr_read_601_rtcu, SPR_NOACCESS,
1097 0x00000000);
1098 spr_register(env, SPR_601_RTCL, "RTCL",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 SPR_NOACCESS, &spr_write_601_rtcl,
1101 0x00000000);
1102 spr_register(env, SPR_601_VRTCL, "RTCL",
1103 &spr_read_601_rtcl, SPR_NOACCESS,
1104 &spr_read_601_rtcl, SPR_NOACCESS,
1105 0x00000000);
1106 /* Timer */
1107#if 0 /* ? */
1108 spr_register(env, SPR_601_UDECR, "UDECR",
1109 &spr_read_decr, SPR_NOACCESS,
1110 &spr_read_decr, SPR_NOACCESS,
1111 0x00000000);
1112#endif
1113 /* External access control */
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_EAR, "EAR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* Memory management */
f2e63a42 1120#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1121 spr_register(env, SPR_IBAT0U, "IBAT0U",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_601_ubat, &spr_write_601_ubatu,
1124 0x00000000);
1125 spr_register(env, SPR_IBAT0L, "IBAT0L",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_601_ubat, &spr_write_601_ubatl,
1128 0x00000000);
1129 spr_register(env, SPR_IBAT1U, "IBAT1U",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_601_ubat, &spr_write_601_ubatu,
1132 0x00000000);
1133 spr_register(env, SPR_IBAT1L, "IBAT1L",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_601_ubat, &spr_write_601_ubatl,
1136 0x00000000);
1137 spr_register(env, SPR_IBAT2U, "IBAT2U",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_601_ubat, &spr_write_601_ubatu,
1140 0x00000000);
1141 spr_register(env, SPR_IBAT2L, "IBAT2L",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_601_ubat, &spr_write_601_ubatl,
1144 0x00000000);
1145 spr_register(env, SPR_IBAT3U, "IBAT3U",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_601_ubat, &spr_write_601_ubatu,
1148 0x00000000);
1149 spr_register(env, SPR_IBAT3L, "IBAT3L",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_601_ubat, &spr_write_601_ubatl,
1152 0x00000000);
a750fc0b 1153 env->nb_BATs = 4;
f2e63a42 1154#endif
a750fc0b
JM		 1155}
1156
1157static void gen_spr_74xx (CPUPPCState *env)
1158{
1159 /* Processor identification */
1160 spr_register(env, SPR_PIR, "PIR",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_pir,
1163 0x00000000);
1164 /* XXX : not implemented */
1165 spr_register(env, SPR_MMCR2, "MMCR2",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
578bb252 1169 /* XXX : not implemented */
a750fc0b
JM		 1170 spr_register(env, SPR_UMMCR2, "UMMCR2",
1171 &spr_read_ureg, SPR_NOACCESS,
1172 &spr_read_ureg, SPR_NOACCESS,
1173 0x00000000);
1174 /* XXX: not implemented */
1175 spr_register(env, SPR_BAMR, "BAMR",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
578bb252 1179 /* XXX : not implemented */
a750fc0b
JM		 1180 spr_register(env, SPR_UBAMR, "UBAMR",
1181 &spr_read_ureg, SPR_NOACCESS,
1182 &spr_read_ureg, SPR_NOACCESS,
1183 0x00000000);
578bb252 1184 /* XXX : not implemented */
a750fc0b
JM		 1185 spr_register(env, SPR_MSSCR0, "MSSCR0",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Hardware implementation registers */
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_HID0, "HID0",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_HID1, "HID1",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* Altivec */
1201 spr_register(env, SPR_VRSAVE, "VRSAVE",
1202 &spr_read_generic, &spr_write_generic,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205}
1206
a750fc0b
JM		 1207static void gen_l3_ctrl (CPUPPCState *env)
1208{
1209 /* L3CR */
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_L3CR, "L3CR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* L3ITCR0 */
578bb252 1216 /* XXX : not implemented */
a750fc0b
JM		 1217 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* L3ITCR1 */
578bb252 1222 /* XXX : not implemented */
a750fc0b
JM		 1223 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* L3ITCR2 */
578bb252 1228 /* XXX : not implemented */
a750fc0b
JM		 1229 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* L3ITCR3 */
578bb252 1234 /* XXX : not implemented */
a750fc0b
JM		 1235 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 /* L3OHCR */
578bb252 1240 /* XXX : not implemented */
a750fc0b
JM		 1241 spr_register(env, SPR_L3OHCR, "L3OHCR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* L3PM */
578bb252 1246 /* XXX : not implemented */
a750fc0b
JM		 1247 spr_register(env, SPR_L3PM, "L3PM",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251}
a750fc0b 1252
578bb252 1253static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1254{
f2e63a42 1255#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1256 env->nb_tlb = nb_tlbs;
1257 env->nb_ways = nb_ways;
1258 env->id_tlbs = 1;
1259 /* XXX : not implemented */
a750fc0b
JM		 1260 spr_register(env, SPR_PTEHI, "PTEHI",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
578bb252 1264 /* XXX : not implemented */
a750fc0b
JM		 1265 spr_register(env, SPR_PTELO, "PTELO",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
578bb252 1269 /* XXX : not implemented */
a750fc0b
JM		 1270 spr_register(env, SPR_TLBMISS, "TLBMISS",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
f2e63a42 1274#endif
76a66253
JM		 1275}
1276
80d11f44 1277static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1278{
80d11f44
JM		 1279 spr_register(env, SPR_USPRG4, "USPRG4",
1280 &spr_read_ureg, SPR_NOACCESS,
1281 &spr_read_ureg, SPR_NOACCESS,
1282 0x00000000);
1283 spr_register(env, SPR_USPRG5, "USPRG5",
1284 &spr_read_ureg, SPR_NOACCESS,
1285 &spr_read_ureg, SPR_NOACCESS,
1286 0x00000000);
1287 spr_register(env, SPR_USPRG6, "USPRG6",
1288 &spr_read_ureg, SPR_NOACCESS,
1289 &spr_read_ureg, SPR_NOACCESS,
1290 0x00000000);
1291 spr_register(env, SPR_USPRG7, "USPRG7",
1292 &spr_read_ureg, SPR_NOACCESS,
1293 &spr_read_ureg, SPR_NOACCESS,
76a66253 1294 0x00000000);
80d11f44
JM		 1295}
1296
1297/* PowerPC BookE SPR */
1298static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1299{
1300 const unsigned char *ivor_names[64] = {
1301 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1302 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1303 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1304 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1305 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1306 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1307 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1308 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1309 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1310 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1311 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1312 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1313 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1314 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1315 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1316 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1317 };
1318#define SPR_BOOKE_IVORxx (-1)
1319 int ivor_sprn[64] = {
1320 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1321 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1322 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1323 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1324 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1325 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1326 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1327 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1328 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1329 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1330 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1331 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1332 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1333 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1334 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1335 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1336 };
1337 int i;
1338
76a66253 1339 /* Interrupt processing */
363be49c 1340 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
363be49c
JM		 1344 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
76a66253
JM		 1348 /* Debug */
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
76a66253
JM		 1360 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
76a66253
JM		 1370 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* XXX : not implemented */
1380 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 /* XXX : not implemented */
1385 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1386 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1387 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1388 0x00000000);
1389 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_ESR, "ESR",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
363be49c
JM		 1397 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1398 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1399 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1400 0x00000000);
1401 /* Exception vectors */
80d11f44
JM		 1402 for (i = 0; i < 64; i++) {
1403 if (ivor_mask & (1ULL << i)) {
1404 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1405 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1406 exit(1);
1407 }
1408 spr_register(env, ivor_sprn[i], ivor_names[i],
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_excp_vector,
1411 0x00000000);
1412 }
1413 }
76a66253
JM		 1414 spr_register(env, SPR_BOOKE_PID, "PID",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418 spr_register(env, SPR_BOOKE_TCR, "TCR",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_booke_tcr,
1421 0x00000000);
1422 spr_register(env, SPR_BOOKE_TSR, "TSR",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_booke_tsr,
1425 0x00000000);
1426 /* Timer */
1427 spr_register(env, SPR_DECR, "DECR",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_decr, &spr_write_decr,
1430 0x00000000);
1431 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 SPR_NOACCESS, &spr_write_generic,
1434 0x00000000);
1435 /* SPRGs */
1436 spr_register(env, SPR_USPRG0, "USPRG0",
1437 &spr_read_generic, &spr_write_generic,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440 spr_register(env, SPR_SPRG4, "SPRG4",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
76a66253
JM		 1444 spr_register(env, SPR_SPRG5, "SPRG5",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
76a66253
JM		 1448 spr_register(env, SPR_SPRG6, "SPRG6",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
76a66253
JM		 1452 spr_register(env, SPR_SPRG7, "SPRG7",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
76a66253
JM		 1456}
1457
363be49c 1458/* FSL storage control registers */
80d11f44 1459static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1460{
f2e63a42 1461#if !defined(CONFIG_USER_ONLY)
80d11f44
JM		 1462 const unsigned char *mas_names[8] = {
1463 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1464 };
1465 int mas_sprn[8] = {
1466 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1467 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1468 };
1469 int i;
1470
363be49c 1471 /* TLB assist registers */
578bb252 1472 /* XXX : not implemented */
80d11f44
JM		 1473 for (i = 0; i < 8; i++) {
1474 if (mas_mask & (1 << i)) {
1475 spr_register(env, mas_sprn[i], mas_names[i],
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 }
1480 }
363be49c 1481 if (env->nb_pids > 1) {
578bb252 1482 /* XXX : not implemented */
363be49c
JM		 1483 spr_register(env, SPR_BOOKE_PID1, "PID1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 }
1488 if (env->nb_pids > 2) {
578bb252 1489 /* XXX : not implemented */
363be49c
JM		 1490 spr_register(env, SPR_BOOKE_PID2, "PID2",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 }
578bb252 1495 /* XXX : not implemented */
65f9ee8d 1496 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, SPR_NOACCESS,
1499 0x00000000); /* TOFIX */
578bb252 1500 /* XXX : not implemented */
65f9ee8d 1501 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000); /* TOFIX */
1505 switch (env->nb_ways) {
1506 case 4:
578bb252 1507 /* XXX : not implemented */
363be49c
JM		 1508 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, SPR_NOACCESS,
1511 0x00000000); /* TOFIX */
1512 /* Fallthru */
1513 case 3:
578bb252 1514 /* XXX : not implemented */
363be49c
JM		 1515 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, SPR_NOACCESS,
1518 0x00000000); /* TOFIX */
1519 /* Fallthru */
1520 case 2:
578bb252 1521 /* XXX : not implemented */
363be49c
JM		 1522 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, SPR_NOACCESS,
1525 0x00000000); /* TOFIX */
1526 /* Fallthru */
1527 case 1:
578bb252 1528 /* XXX : not implemented */
363be49c
JM		 1529 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, SPR_NOACCESS,
1532 0x00000000); /* TOFIX */
1533 /* Fallthru */
1534 case 0:
1535 default:
1536 break;
1537 }
f2e63a42 1538#endif
363be49c
JM		 1539}
1540
76a66253
JM		 1541/* SPR specific to PowerPC 440 implementation */
1542static void gen_spr_440 (CPUPPCState *env)
1543{
1544 /* Cache control */
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_440_DNV0, "DNV0",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* XXX : not implemented */
1551 spr_register(env, SPR_440_DNV1, "DNV1",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_440_DNV2, "DNV2",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 /* XXX : not implemented */
1561 spr_register(env, SPR_440_DNV3, "DNV3",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 /* XXX : not implemented */
2662a059 1566 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 /* XXX : not implemented */
2662a059 1571 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 /* XXX : not implemented */
2662a059 1576 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580 /* XXX : not implemented */
2662a059 1581 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585 /* XXX : not implemented */
1586 spr_register(env, SPR_440_DVLIM, "DVLIM",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590 /* XXX : not implemented */
1591 spr_register(env, SPR_440_INV0, "INV0",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_440_INV1, "INV1",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600 /* XXX : not implemented */
1601 spr_register(env, SPR_440_INV2, "INV2",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605 /* XXX : not implemented */
1606 spr_register(env, SPR_440_INV3, "INV3",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, &spr_write_generic,
1609 0x00000000);
1610 /* XXX : not implemented */
2662a059 1611 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_generic,
1614 0x00000000);
1615 /* XXX : not implemented */
2662a059 1616 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_generic,
1619 0x00000000);
1620 /* XXX : not implemented */
2662a059 1621 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625 /* XXX : not implemented */
2662a059 1626 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630 /* XXX : not implemented */
1631 spr_register(env, SPR_440_IVLIM, "IVLIM",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, &spr_write_generic,
1634 0x00000000);
1635 /* Cache debug */
1636 /* XXX : not implemented */
2662a059 1637 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, SPR_NOACCESS,
1640 0x00000000);
1641 /* XXX : not implemented */
2662a059 1642 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, SPR_NOACCESS,
1645 0x00000000);
1646 /* XXX : not implemented */
2662a059 1647 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, SPR_NOACCESS,
1650 0x00000000);
1651 /* XXX : not implemented */
2662a059 1652 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
1655 0x00000000);
1656 /* XXX : not implemented */
2662a059 1657 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, SPR_NOACCESS,
1660 0x00000000);
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_440_DBDR, "DBDR",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* Processor control */
1667 spr_register(env, SPR_4xx_CCR0, "CCR0",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, SPR_NOACCESS,
1674 0x00000000);
1675 /* Storage control */
1676 spr_register(env, SPR_440_MMUCR, "MMUCR",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680}
1681
1682/* SPR shared between PowerPC 40x implementations */
1683static void gen_spr_40x (CPUPPCState *env)
1684{
1685 /* Cache */
035feb88 1686 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1687 spr_register(env, SPR_40x_DCCR, "DCCR",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
035feb88 1691 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1692 spr_register(env, SPR_40x_ICCR, "ICCR",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
578bb252 1696 /* not emulated, as Qemu do not emulate caches */
2662a059 1697 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, SPR_NOACCESS,
1700 0x00000000);
76a66253
JM		 1701 /* Exception */
1702 spr_register(env, SPR_40x_DEAR, "DEAR",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 spr_register(env, SPR_40x_ESR, "ESR",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 spr_register(env, SPR_40x_EVPR, "EVPR",
1711 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1712 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1713 0x00000000);
1714 spr_register(env, SPR_40x_SRR2, "SRR2",
1715 &spr_read_generic, &spr_write_generic,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 spr_register(env, SPR_40x_SRR3, "SRR3",
1719 &spr_read_generic, &spr_write_generic,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* Timers */
1723 spr_register(env, SPR_40x_PIT, "PIT",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_40x_pit, &spr_write_40x_pit,
1726 0x00000000);
1727 spr_register(env, SPR_40x_TCR, "TCR",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_generic, &spr_write_booke_tcr,
1730 0x00000000);
1731 spr_register(env, SPR_40x_TSR, "TSR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_booke_tsr,
1734 0x00000000);
2662a059
JM		 1735}
1736
1737/* SPR specific to PowerPC 405 implementation */
1738static void gen_spr_405 (CPUPPCState *env)
1739{
1740 /* MMU */
1741 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
2662a059 1745 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1748 0x00700000);
1749 /* Debug interface */
76a66253
JM		 1750 /* XXX : not implemented */
1751 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1752 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1753 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1754 0x00000000);
1755 /* XXX : not implemented */
2662a059
JM		 1756 spr_register(env, SPR_405_DBCR1, "DBCR1",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 /* XXX : not implemented */
76a66253
JM		 1761 spr_register(env, SPR_40x_DBSR, "DBSR",
1762 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1763 &spr_read_generic, &spr_write_clear,
1764 /* Last reset was system reset */
76a66253
JM		 1765 0x00000300);
1766 /* XXX : not implemented */
2662a059 1767 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
2662a059 1771 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_generic,
1774 0x00000000);
2662a059
JM		 1775 /* XXX : not implemented */
1776 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1777 SPR_NOACCESS, SPR_NOACCESS,
1778 &spr_read_generic, &spr_write_generic,
2662a059 1779 0x00000000);
76a66253 1780 /* XXX : not implemented */
2662a059 1781 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, &spr_write_generic,
1784 0x00000000);
1785 /* XXX : not implemented */
2662a059 1786 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
2662a059 1790 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_405_IAC3, "IAC3",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_405_IAC4, "IAC4",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Storage control */
035feb88 1805 /* XXX: TODO: not implemented */
76a66253
JM		 1806 spr_register(env, SPR_405_SLER, "SLER",
1807 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1808 &spr_read_generic, &spr_write_40x_sler,
76a66253 1809 0x00000000);
2662a059
JM		 1810 spr_register(env, SPR_40x_ZPR, "ZPR",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
76a66253
JM		 1814 /* XXX : not implemented */
1815 spr_register(env, SPR_405_SU0R, "SU0R",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 /* SPRG */
1820 spr_register(env, SPR_USPRG0, "USPRG0",
1821 &spr_read_ureg, SPR_NOACCESS,
1822 &spr_read_ureg, SPR_NOACCESS,
1823 0x00000000);
1824 spr_register(env, SPR_SPRG4, "SPRG4",
1825 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1826 &spr_read_generic, &spr_write_generic,
76a66253 1827 0x00000000);
76a66253
JM		 1828 spr_register(env, SPR_SPRG5, "SPRG5",
1829 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1830 spr_read_generic, &spr_write_generic,
76a66253 1831 0x00000000);
76a66253
JM		 1832 spr_register(env, SPR_SPRG6, "SPRG6",
1833 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1834 spr_read_generic, &spr_write_generic,
76a66253 1835 0x00000000);
76a66253
JM		 1836 spr_register(env, SPR_SPRG7, "SPRG7",
1837 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1838 spr_read_generic, &spr_write_generic,
76a66253 1839 0x00000000);
80d11f44 1840 gen_spr_usprgh(env);
76a66253
JM		 1841}
1842
1843/* SPR shared between PowerPC 401 & 403 implementations */
1844static void gen_spr_401_403 (CPUPPCState *env)
1845{
1846 /* Time base */
1847 spr_register(env, SPR_403_VTBL, "TBL",
1848 &spr_read_tbl, SPR_NOACCESS,
1849 &spr_read_tbl, SPR_NOACCESS,
1850 0x00000000);
1851 spr_register(env, SPR_403_TBL, "TBL",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 SPR_NOACCESS, &spr_write_tbl,
1854 0x00000000);
1855 spr_register(env, SPR_403_VTBU, "TBU",
1856 &spr_read_tbu, SPR_NOACCESS,
1857 &spr_read_tbu, SPR_NOACCESS,
1858 0x00000000);
1859 spr_register(env, SPR_403_TBU, "TBU",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 SPR_NOACCESS, &spr_write_tbu,
1862 0x00000000);
1863 /* Debug */
578bb252 1864 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1865 spr_register(env, SPR_403_CDBCR, "CDBCR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, &spr_write_generic,
1868 0x00000000);
1869}
1870
2662a059
JM		 1871/* SPR specific to PowerPC 401 implementation */
1872static void gen_spr_401 (CPUPPCState *env)
1873{
1874 /* Debug interface */
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_40x_DBCR0, "DBCR",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_40x_dbcr0,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_40x_DBSR, "DBSR",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_clear,
1884 /* Last reset was system reset */
1885 0x00000300);
1886 /* XXX : not implemented */
1887 spr_register(env, SPR_40x_DAC1, "DAC",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_40x_IAC1, "IAC",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 /* Storage control */
035feb88 1897 /* XXX: TODO: not implemented */
2662a059
JM		 1898 spr_register(env, SPR_405_SLER, "SLER",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_40x_sler,
1901 0x00000000);
035feb88
JM		 1902 /* not emulated, as Qemu never does speculative access */
1903 spr_register(env, SPR_40x_SGR, "SGR",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0xFFFFFFFF);
1907 /* not emulated, as Qemu do not emulate caches */
1908 spr_register(env, SPR_40x_DCWR, "DCWR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
2662a059
JM		 1912}
1913
a750fc0b
JM		 1914static void gen_spr_401x2 (CPUPPCState *env)
1915{
1916 gen_spr_401(env);
1917 spr_register(env, SPR_40x_PID, "PID",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_40x_ZPR, "ZPR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925}
1926
76a66253
JM		 1927/* SPR specific to PowerPC 403 implementation */
1928static void gen_spr_403 (CPUPPCState *env)
1929{
2662a059
JM		 1930 /* Debug interface */
1931 /* XXX : not implemented */
1932 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_40x_dbcr0,
1935 0x00000000);
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_40x_DBSR, "DBSR",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_clear,
1940 /* Last reset was system reset */
1941 0x00000300);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_40x_DAC1, "DAC1",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
578bb252 1947 /* XXX : not implemented */
2662a059
JM		 1948 spr_register(env, SPR_40x_DAC2, "DAC2",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_IAC1, "IAC1",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
578bb252 1957 /* XXX : not implemented */
2662a059
JM		 1958 spr_register(env, SPR_40x_IAC2, "IAC2",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
a750fc0b
JM		 1962}
1963
1964static void gen_spr_403_real (CPUPPCState *env)
1965{
76a66253
JM		 1966 spr_register(env, SPR_403_PBL1, "PBL1",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_403_pbr, &spr_write_403_pbr,
1969 0x00000000);
1970 spr_register(env, SPR_403_PBU1, "PBU1",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_403_pbr, &spr_write_403_pbr,
1973 0x00000000);
1974 spr_register(env, SPR_403_PBL2, "PBL2",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_403_pbr, &spr_write_403_pbr,
1977 0x00000000);
1978 spr_register(env, SPR_403_PBU2, "PBU2",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_403_pbr, &spr_write_403_pbr,
1981 0x00000000);
a750fc0b
JM		 1982}
1983
1984static void gen_spr_403_mmu (CPUPPCState *env)
1985{
1986 /* MMU */
1987 spr_register(env, SPR_40x_PID, "PID",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
2662a059 1991 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_generic,
1994 0x00000000);
1995}
1996
1997/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 1998static void gen_spr_compress (CPUPPCState *env)
1999{
578bb252 2000 /* XXX : not implemented */
76a66253
JM		 2001 spr_register(env, SPR_401_SKR, "SKR",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005}
a750fc0b
JM		 2006
2007#if defined (TARGET_PPC64)
a750fc0b
JM		 2008/* SPR specific to PowerPC 620 */
2009static void gen_spr_620 (CPUPPCState *env)
2010{
578bb252 2011 /* XXX : not implemented */
a750fc0b
JM		 2012 spr_register(env, SPR_620_PMR0, "PMR0",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
578bb252 2016 /* XXX : not implemented */
a750fc0b
JM		 2017 spr_register(env, SPR_620_PMR1, "PMR1",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
578bb252 2021 /* XXX : not implemented */
a750fc0b
JM		 2022 spr_register(env, SPR_620_PMR2, "PMR2",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0x00000000);
578bb252 2026 /* XXX : not implemented */
a750fc0b
JM		 2027 spr_register(env, SPR_620_PMR3, "PMR3",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
578bb252 2031 /* XXX : not implemented */
a750fc0b
JM		 2032 spr_register(env, SPR_620_PMR4, "PMR4",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2035 0x00000000);
578bb252 2036 /* XXX : not implemented */
a750fc0b
JM		 2037 spr_register(env, SPR_620_PMR5, "PMR5",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_generic,
2040 0x00000000);
578bb252 2041 /* XXX : not implemented */
a750fc0b
JM		 2042 spr_register(env, SPR_620_PMR6, "PMR6",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
578bb252 2046 /* XXX : not implemented */
a750fc0b
JM		 2047 spr_register(env, SPR_620_PMR7, "PMR7",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_generic,
2050 0x00000000);
578bb252 2051 /* XXX : not implemented */
a750fc0b
JM		 2052 spr_register(env, SPR_620_PMR8, "PMR8",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2055 0x00000000);
578bb252 2056 /* XXX : not implemented */
a750fc0b
JM		 2057 spr_register(env, SPR_620_PMR9, "PMR9",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_generic,
2060 0x00000000);
578bb252 2061 /* XXX : not implemented */
a750fc0b
JM		 2062 spr_register(env, SPR_620_PMRA, "PMR10",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_generic,
2065 0x00000000);
578bb252 2066 /* XXX : not implemented */
a750fc0b
JM		 2067 spr_register(env, SPR_620_PMRB, "PMR11",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
578bb252 2071 /* XXX : not implemented */
a750fc0b
JM		 2072 spr_register(env, SPR_620_PMRC, "PMR12",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
578bb252 2076 /* XXX : not implemented */
a750fc0b
JM		 2077 spr_register(env, SPR_620_PMRD, "PMR13",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, &spr_write_generic,
2080 0x00000000);
578bb252 2081 /* XXX : not implemented */
a750fc0b
JM		 2082 spr_register(env, SPR_620_PMRE, "PMR14",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_generic,
2085 0x00000000);
578bb252 2086 /* XXX : not implemented */
a750fc0b
JM		 2087 spr_register(env, SPR_620_PMRF, "PMR15",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
578bb252 2091 /* XXX : not implemented */
a750fc0b
JM		 2092 spr_register(env, SPR_620_HID8, "HID8",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
578bb252 2096 /* XXX : not implemented */
a750fc0b
JM		 2097 spr_register(env, SPR_620_HID9, "HID9",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101}
a750fc0b 2102#endif /* defined (TARGET_PPC64) */
76a66253 2103
80d11f44 2104static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2105{
80d11f44
JM		 2106 /* Exception processing */
2107 spr_register(env, SPR_DSISR, "DSISR",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 spr_register(env, SPR_DAR, "DAR",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 /* Timer */
2116 spr_register(env, SPR_DECR, "DECR",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_decr, &spr_write_decr,
2119 0x00000000);
2120 /* XXX : not implemented */
2121 spr_register(env, SPR_MPC_EIE, "EIE",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, &spr_write_generic,
2124 0x00000000);
2125 /* XXX : not implemented */
2126 spr_register(env, SPR_MPC_EID, "EID",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, &spr_write_generic,
2129 0x00000000);
2130 /* XXX : not implemented */
2131 spr_register(env, SPR_MPC_NRI, "NRI",
2132 SPR_NOACCESS, SPR_NOACCESS,
2133 &spr_read_generic, &spr_write_generic,
2134 0x00000000);
2135 /* XXX : not implemented */
2136 spr_register(env, SPR_MPC_CMPA, "CMPA",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 /* XXX : not implemented */
2141 spr_register(env, SPR_MPC_CMPB, "CMPB",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
2145 /* XXX : not implemented */
2146 spr_register(env, SPR_MPC_CMPC, "CMPC",
2147 SPR_NOACCESS, SPR_NOACCESS,
2148 &spr_read_generic, &spr_write_generic,
2149 0x00000000);
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_MPC_CMPD, "CMPD",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
2155 /* XXX : not implemented */
2156 spr_register(env, SPR_MPC_ECR, "ECR",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_generic, &spr_write_generic,
2159 0x00000000);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_MPC_DER, "DER",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, &spr_write_generic,
2164 0x00000000);
2165 /* XXX : not implemented */
2166 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2167 SPR_NOACCESS, SPR_NOACCESS,
2168 &spr_read_generic, &spr_write_generic,
2169 0x00000000);
2170 /* XXX : not implemented */
2171 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 /* XXX : not implemented */
2176 spr_register(env, SPR_MPC_CMPE, "CMPE",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, &spr_write_generic,
2179 0x00000000);
2180 /* XXX : not implemented */
2181 spr_register(env, SPR_MPC_CMPF, "CMPF",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_generic, &spr_write_generic,
2184 0x00000000);
2185 /* XXX : not implemented */
2186 spr_register(env, SPR_MPC_CMPG, "CMPG",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
2190 /* XXX : not implemented */
2191 spr_register(env, SPR_MPC_CMPH, "CMPH",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, &spr_write_generic,
2194 0x00000000);
2195 /* XXX : not implemented */
2196 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 0x00000000);
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205 /* XXX : not implemented */
2206 spr_register(env, SPR_MPC_BAR, "BAR",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 /* XXX : not implemented */
2211 spr_register(env, SPR_MPC_DPDR, "DPDR",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_MPC_IMMR, "IMMR",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220}
2221
2222static void gen_spr_5xx (CPUPPCState *env)
2223{
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329}
2330
2331static void gen_spr_8xx (CPUPPCState *env)
2332{
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433 /* XXX : not implemented */
2434 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2435 SPR_NOACCESS, SPR_NOACCESS,
2436 &spr_read_generic, &spr_write_generic,
2437 0x00000000);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458}
2459
2460// XXX: TODO
2461/*
2462 * AMR => SPR 29 (Power 2.04)
2463 * CTRL => SPR 136 (Power 2.04)
2464 * CTRL => SPR 152 (Power 2.04)
2465 * SCOMC => SPR 276 (64 bits ?)
2466 * SCOMD => SPR 277 (64 bits ?)
2467 * TBU40 => SPR 286 (Power 2.04 hypv)
2468 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2469 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2470 * HDSISR => SPR 306 (Power 2.04 hypv)
2471 * HDAR => SPR 307 (Power 2.04 hypv)
2472 * PURR => SPR 309 (Power 2.04 hypv)
2473 * HDEC => SPR 310 (Power 2.04 hypv)
2474 * HIOR => SPR 311 (hypv)
2475 * RMOR => SPR 312 (970)
2476 * HRMOR => SPR 313 (Power 2.04 hypv)
2477 * HSRR0 => SPR 314 (Power 2.04 hypv)
2478 * HSRR1 => SPR 315 (Power 2.04 hypv)
2479 * LPCR => SPR 316 (970)
2480 * LPIDR => SPR 317 (970)
2481 * SPEFSCR => SPR 512 (Power 2.04 emb)
2482 * EPR => SPR 702 (Power 2.04 emb)
2483 * perf => 768-783 (Power 2.04)
2484 * perf => 784-799 (Power 2.04)
2485 * PPR => SPR 896 (Power 2.04)
2486 * EPLC => SPR 947 (Power 2.04 emb)
2487 * EPSC => SPR 948 (Power 2.04 emb)
2488 * DABRX => 1015 (Power 2.04 hypv)
2489 * FPECR => SPR 1022 (?)
2490 * ... and more (thermal management, performance counters, ...)
2491 */
2492
2493/*****************************************************************************/
2494/* Exception vectors models */
2495static void init_excp_4xx_real (CPUPPCState *env)
2496{
2497#if !defined(CONFIG_USER_ONLY)
2498 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2499 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2500 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2501 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2502 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2503 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2504 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2505 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2506 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2507 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
faadf50e 2508 env->excp_prefix = 0x00000000UL;
80d11f44 2509 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2510 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2511 /* Hardware reset vector */
2512 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2513#endif
2514}
2515
80d11f44
JM		 2516static void init_excp_4xx_softmmu (CPUPPCState *env)
2517{
2518#if !defined(CONFIG_USER_ONLY)
2519 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2520 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2521 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2522 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2523 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2524 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2525 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2526 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2527 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2528 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2529 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2530 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2531 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2532 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2533 env->excp_prefix = 0x00000000UL;
2534 env->ivor_mask = 0x0000FFF0UL;
2535 env->ivpr_mask = 0xFFFF0000UL;
2536 /* Hardware reset vector */
2537 env->hreset_vector = 0xFFFFFFFCUL;
2538#endif
2539}
2540
2541static void init_excp_MPC5xx (CPUPPCState *env)
2542{
2543#if !defined(CONFIG_USER_ONLY)
2544 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2545 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2546 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2547 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2548 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2549 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2550 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2551 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2552 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2553 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2554 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2555 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2556 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2557 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2558 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2559 env->excp_prefix = 0x00000000UL;
2560 env->ivor_mask = 0x0000FFF0UL;
2561 env->ivpr_mask = 0xFFFF0000UL;
2562 /* Hardware reset vector */
2563 env->hreset_vector = 0xFFFFFFFCUL;
2564#endif
2565}
2566
2567static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2568{
2569#if !defined(CONFIG_USER_ONLY)
2570 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2571 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2572 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2573 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2574 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2575 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2576 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2577 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2578 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2579 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2580 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2581 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2582 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2583 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2584 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2585 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2586 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2587 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2588 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2589 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2590 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2591 env->excp_prefix = 0x00000000UL;
2592 env->ivor_mask = 0x0000FFF0UL;
2593 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2594 /* Hardware reset vector */
80d11f44 2595 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2596#endif
2597}
2598
80d11f44 2599static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2600{
2601#if !defined(CONFIG_USER_ONLY)
2602 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2603 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2604 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2605 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2606 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2607 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2608 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2609 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2610 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2611 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2612 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2613 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2614 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2615 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2616 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2617 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2618 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2619 env->excp_prefix = 0x00000000UL;
2620 /* Hardware reset vector */
2621 env->hreset_vector = 0xFFFFFFFCUL;
2622#endif
2623}
2624
2625static void init_excp_e200 (CPUPPCState *env)
2626{
2627#if !defined(CONFIG_USER_ONLY)
2628 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2629 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2630 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2631 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2632 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2633 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2634 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2635 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2636 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2637 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2638 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2639 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2640 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2641 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2642 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2643 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2644 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2645 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2646 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2647 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2648 env->excp_prefix = 0x00000000UL;
2649 env->ivor_mask = 0x0000FFF7UL;
2650 env->ivpr_mask = 0xFFFF0000UL;
2651 /* Hardware reset vector */
2652 env->hreset_vector = 0xFFFFFFFCUL;
2653#endif
2654}
2655
2656static void init_excp_BookE (CPUPPCState *env)
2657{
2658#if !defined(CONFIG_USER_ONLY)
2659 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2660 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2661 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2662 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2663 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2664 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2665 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2666 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2667 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2668 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2669 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2670 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2671 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2672 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2673 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2674 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2675 env->excp_prefix = 0x00000000UL;
2676 env->ivor_mask = 0x0000FFE0UL;
2677 env->ivpr_mask = 0xFFFF0000UL;
2678 /* Hardware reset vector */
2679 env->hreset_vector = 0xFFFFFFFCUL;
2680#endif
2681}
2682
2683static void init_excp_601 (CPUPPCState *env)
2684{
2685#if !defined(CONFIG_USER_ONLY)
2686 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2688 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2689 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2690 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2691 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2692 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2693 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2694 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2695 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2696 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2697 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
faadf50e 2698 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2699 /* Hardware reset vector */
80d11f44 2700 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2701#endif
2702}
2703
80d11f44 2704static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2705{
2706#if !defined(CONFIG_USER_ONLY)
2707 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2708 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2709 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2710 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2711 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2712 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2713 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2714 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2715 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2716 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2717 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
80d11f44 2718 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
e1833e1f
JM		 2719 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2720 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2721 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2722 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2723 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2724 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2725 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2726 env->excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2727 /* Hardware reset vector */
2728 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2729#endif
2730}
2731
80d11f44 2732static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2733{
2734#if !defined(CONFIG_USER_ONLY)
2735 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2736 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2737 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2738 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2739 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2740 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2741 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2742 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2743 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2744 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2745 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2746 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2747 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2748 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2749 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2750 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2751 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2754#endif
2755}
2756
2757static void init_excp_604 (CPUPPCState *env)
2758{
2759#if !defined(CONFIG_USER_ONLY)
2760 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2761 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2762 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2763 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2764 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2765 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2766 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2767 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2768 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2769 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2770 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2771 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2772 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2773 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2774 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2775 /* Hardware reset vector */
2776 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2777#endif
2778}
2779
578bb252 2780#if defined(TARGET_PPC64)
e1833e1f
JM		 2781static void init_excp_620 (CPUPPCState *env)
2782{
2783#if !defined(CONFIG_USER_ONLY)
2784 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
faadf50e 2787 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
e1833e1f 2788 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
faadf50e 2789 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
e1833e1f
JM		 2790 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2791 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2792 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2793 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2795 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2796 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2797 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2798 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2799 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2800 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2801 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2802 /* Hardware reset vector */
faadf50e 2803 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2804#endif
2805}
578bb252 2806#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2807
2808static void init_excp_7x0 (CPUPPCState *env)
2809{
2810#if !defined(CONFIG_USER_ONLY)
2811 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2819 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2820 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2821 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2822 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2823 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2824 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2825 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2826 /* Hardware reset vector */
2827 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2828#endif
2829}
2830
2831static void init_excp_750FX (CPUPPCState *env)
2832{
2833#if !defined(CONFIG_USER_ONLY)
2834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2835 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2836 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2837 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2838 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2839 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2840 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2841 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2842 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2844 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2845 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2846 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2847 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2848 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2849 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2850 /* Hardware reset vector */
2851 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2852#endif
2853}
2854
7a3a6927
JM		 2855/* XXX: Check if this is correct */
2856static void init_excp_7x5 (CPUPPCState *env)
2857{
2858#if !defined(CONFIG_USER_ONLY)
2859 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2860 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2861 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2862 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2863 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2864 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2865 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2866 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2867 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2868 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2869 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2870 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2871 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2872 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2873 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2874 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2875 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2876 env->excp_prefix = 0x00000000UL;
7a3a6927
JM		 2877 /* Hardware reset vector */
2878 env->hreset_vector = 0xFFFFFFFCUL;
2879#endif
2880}
2881
e1833e1f
JM		 2882static void init_excp_7400 (CPUPPCState *env)
2883{
2884#if !defined(CONFIG_USER_ONLY)
2885 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2886 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2887 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2888 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2889 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2890 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2891 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2892 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2893 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2894 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2895 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2896 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2897 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2900 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2901 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2902 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2903 /* Hardware reset vector */
2904 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2905#endif
2906}
2907
e1833e1f
JM		 2908static void init_excp_7450 (CPUPPCState *env)
2909{
2910#if !defined(CONFIG_USER_ONLY)
2911 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2912 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2913 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2914 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2915 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2916 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2917 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2918 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2920 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2921 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2922 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2923 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2924 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2925 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2926 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2927 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2928 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2929 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
faadf50e 2930 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2931 /* Hardware reset vector */
2932 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2933#endif
2934}
e1833e1f
JM		 2935
2936#if defined (TARGET_PPC64)
2937static void init_excp_970 (CPUPPCState *env)
2938{
2939#if !defined(CONFIG_USER_ONLY)
2940 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2941 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2942 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2943 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2951 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2955 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2956 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2957 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2958 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2959 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
faadf50e 2960 env->excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 2961 /* Hardware reset vector */
2962 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2963#endif
2964}
2965#endif
2966
2f462816
JM		 2967/*****************************************************************************/
2968/* Power management enable checks */
2969static int check_pow_none (CPUPPCState *env)
2970{
2971 return 0;
2972}
2973
2974static int check_pow_nocheck (CPUPPCState *env)
2975{
2976 return 1;
2977}
2978
2979static int check_pow_hid0 (CPUPPCState *env)
2980{
2981 if (env->spr[SPR_HID0] & 0x00E00000)
2982 return 1;
2983
2984 return 0;
2985}
2986
a750fc0b
JM		 2987/*****************************************************************************/
2988/* PowerPC implementations definitions */
76a66253 2989
a750fc0b 2990/* PowerPC 40x instruction set */
05332d70 2991#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \
1b413d55 2992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
76a66253 2993
a750fc0b 2994/* PowerPC 401 */
05332d70 2995#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 2996 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2997 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2998#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 2999#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3000#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3001#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3002#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
25ba3a68 3003#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3004#define check_pow_401 check_pow_nocheck
76a66253 3005
a750fc0b
JM		 3006static void init_proc_401 (CPUPPCState *env)
3007{
3008 gen_spr_40x(env);
3009 gen_spr_401_403(env);
3010 gen_spr_401(env);
e1833e1f 3011 init_excp_4xx_real(env);
d63001d1
JM		 3012 env->dcache_line_size = 32;
3013 env->icache_line_size = 32;
4e290a0b
JM		 3014 /* Allocate hardware IRQ controller */
3015 ppc40x_irq_init(env);
a750fc0b 3016}
76a66253 3017
a750fc0b 3018/* PowerPC 401x2 */
05332d70 3019#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3020 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3021 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3022 PPC_CACHE_DCBA | PPC_MFTB | \
3023 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3024#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3025#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3026#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3027#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3028#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
25ba3a68 3029#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3030#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3031
3032static void init_proc_401x2 (CPUPPCState *env)
3033{
3034 gen_spr_40x(env);
3035 gen_spr_401_403(env);
3036 gen_spr_401x2(env);
3037 gen_spr_compress(env);
a750fc0b 3038 /* Memory management */
f2e63a42 3039#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3040 env->nb_tlb = 64;
3041 env->nb_ways = 1;
3042 env->id_tlbs = 0;
f2e63a42 3043#endif
e1833e1f 3044 init_excp_4xx_softmmu(env);
d63001d1
JM		 3045 env->dcache_line_size = 32;
3046 env->icache_line_size = 32;
4e290a0b
JM		 3047 /* Allocate hardware IRQ controller */
3048 ppc40x_irq_init(env);
76a66253
JM		 3049}
3050
a750fc0b 3051/* PowerPC 401x3 */
05332d70 3052#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3053 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3054 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3055 PPC_CACHE_DCBA | PPC_MFTB | \
3056 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3057#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3058#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3059#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3060#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3061#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
25ba3a68 3062#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3063#define check_pow_401x3 check_pow_nocheck
a750fc0b 3064
578bb252 3065__attribute__ (( unused ))
e1833e1f 3066static void init_proc_401x3 (CPUPPCState *env)
76a66253 3067{
4e290a0b
JM		 3068 gen_spr_40x(env);
3069 gen_spr_401_403(env);
3070 gen_spr_401(env);
3071 gen_spr_401x2(env);
3072 gen_spr_compress(env);
e1833e1f 3073 init_excp_4xx_softmmu(env);
d63001d1
JM		 3074 env->dcache_line_size = 32;
3075 env->icache_line_size = 32;
4e290a0b
JM		 3076 /* Allocate hardware IRQ controller */
3077 ppc40x_irq_init(env);
3fc6c082 3078}
a750fc0b
JM		 3079
3080/* IOP480 */
05332d70 3081#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3082 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3083 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3084 PPC_CACHE_DCBA | \
3085 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3086#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3087#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3088#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3089#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3090#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
25ba3a68 3091#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3092#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3093
3094static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3095{
a750fc0b
JM		 3096 gen_spr_40x(env);
3097 gen_spr_401_403(env);
3098 gen_spr_401x2(env);
3099 gen_spr_compress(env);
a750fc0b 3100 /* Memory management */
f2e63a42 3101#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3102 env->nb_tlb = 64;
3103 env->nb_ways = 1;
3104 env->id_tlbs = 0;
f2e63a42 3105#endif
e1833e1f 3106 init_excp_4xx_softmmu(env);
d63001d1
JM		 3107 env->dcache_line_size = 32;
3108 env->icache_line_size = 32;
4e290a0b
JM		 3109 /* Allocate hardware IRQ controller */
3110 ppc40x_irq_init(env);
3fc6c082
FB		 3111}
3112
a750fc0b 3113/* PowerPC 403 */
05332d70 3114#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b 3115 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
a750fc0b
JM		 3116 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3117#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3118#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3119#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3120#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3121#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
25ba3a68 3122#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2f462816 3123#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3124
3125static void init_proc_403 (CPUPPCState *env)
3fc6c082 3126{
a750fc0b
JM		 3127 gen_spr_40x(env);
3128 gen_spr_401_403(env);
3129 gen_spr_403(env);
3130 gen_spr_403_real(env);
e1833e1f 3131 init_excp_4xx_real(env);
d63001d1
JM		 3132 env->dcache_line_size = 32;
3133 env->icache_line_size = 32;
4e290a0b
JM		 3134 /* Allocate hardware IRQ controller */
3135 ppc40x_irq_init(env);
d63001d1
JM		 3136#if !defined(CONFIG_USER_ONLY)
3137 /* Hardware reset vector */
3138 env->hreset_vector = 0xFFFFFFFCUL;
3139#endif
3fc6c082
FB		 3140}
3141
a750fc0b 3142/* PowerPC 403 GCX */
05332d70 3143#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3144 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3145 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3146 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3147#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3148#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3149#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3150#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3151#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
25ba3a68 3152#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2f462816 3153#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3154
3155static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3156{
a750fc0b
JM		 3157 gen_spr_40x(env);
3158 gen_spr_401_403(env);
3159 gen_spr_403(env);
3160 gen_spr_403_real(env);
3161 gen_spr_403_mmu(env);
3162 /* Bus access control */
035feb88 3163 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3164 spr_register(env, SPR_40x_SGR, "SGR",
3165 SPR_NOACCESS, SPR_NOACCESS,
3166 &spr_read_generic, &spr_write_generic,
3167 0xFFFFFFFF);
035feb88 3168 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3169 spr_register(env, SPR_40x_DCWR, "DCWR",
3170 SPR_NOACCESS, SPR_NOACCESS,
3171 &spr_read_generic, &spr_write_generic,
3172 0x00000000);
3173 /* Memory management */
f2e63a42 3174#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3175 env->nb_tlb = 64;
3176 env->nb_ways = 1;
3177 env->id_tlbs = 0;
f2e63a42 3178#endif
80d11f44
JM		 3179 init_excp_4xx_softmmu(env);
3180 env->dcache_line_size = 32;
3181 env->icache_line_size = 32;
3182 /* Allocate hardware IRQ controller */
3183 ppc40x_irq_init(env);
3184}
3185
3186/* PowerPC 405 */
3187#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3188 PPC_MFTB | \
3189 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
3190 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3191 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
3192 PPC_405_MAC)
3193#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3194#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3195#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3196#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3197#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3198#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3199 POWERPC_FLAG_DE)
3200#define check_pow_405 check_pow_nocheck
3201
3202static void init_proc_405 (CPUPPCState *env)
3203{
3204 /* Time base */
3205 gen_tbl(env);
3206 gen_spr_40x(env);
3207 gen_spr_405(env);
3208 /* Bus access control */
3209 /* not emulated, as Qemu never does speculative access */
3210 spr_register(env, SPR_40x_SGR, "SGR",
3211 SPR_NOACCESS, SPR_NOACCESS,
3212 &spr_read_generic, &spr_write_generic,
3213 0xFFFFFFFF);
3214 /* not emulated, as Qemu do not emulate caches */
3215 spr_register(env, SPR_40x_DCWR, "DCWR",
3216 SPR_NOACCESS, SPR_NOACCESS,
3217 &spr_read_generic, &spr_write_generic,
3218 0x00000000);
3219 /* Memory management */
3220#if !defined(CONFIG_USER_ONLY)
3221 env->nb_tlb = 64;
3222 env->nb_ways = 1;
3223 env->id_tlbs = 0;
3224#endif
3225 init_excp_4xx_softmmu(env);
3226 env->dcache_line_size = 32;
3227 env->icache_line_size = 32;
3228 /* Allocate hardware IRQ controller */
3229 ppc40x_irq_init(env);
3230}
3231
3232/* PowerPC 440 EP */
3233#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3234 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3235 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3236 PPC_440_SPEC | PPC_RFMCI)
3237#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3238#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3239#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3240#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3241#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3242#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3243 POWERPC_FLAG_DE)
3244#define check_pow_440EP check_pow_nocheck
3245
3246__attribute__ (( unused ))
3247static void init_proc_440EP (CPUPPCState *env)
3248{
3249 /* Time base */
3250 gen_tbl(env);
3251 gen_spr_BookE(env, 0x000000000000FFFFULL);
3252 gen_spr_440(env);
3253 gen_spr_usprgh(env);
3254 /* Processor identification */
3255 spr_register(env, SPR_BOOKE_PIR, "PIR",
3256 SPR_NOACCESS, SPR_NOACCESS,
3257 &spr_read_generic, &spr_write_pir,
3258 0x00000000);
3259 /* XXX : not implemented */
3260 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3261 SPR_NOACCESS, SPR_NOACCESS,
3262 &spr_read_generic, &spr_write_generic,
3263 0x00000000);
3264 /* XXX : not implemented */
3265 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3266 SPR_NOACCESS, SPR_NOACCESS,
3267 &spr_read_generic, &spr_write_generic,
3268 0x00000000);
3269 /* XXX : not implemented */
3270 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3271 SPR_NOACCESS, SPR_NOACCESS,
3272 &spr_read_generic, &spr_write_generic,
3273 0x00000000);
3274 /* XXX : not implemented */
3275 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3276 SPR_NOACCESS, SPR_NOACCESS,
3277 &spr_read_generic, &spr_write_generic,
3278 0x00000000);
3279 /* XXX : not implemented */
3280 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3281 SPR_NOACCESS, SPR_NOACCESS,
3282 &spr_read_generic, &spr_write_generic,
3283 0x00000000);
3284 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3285 SPR_NOACCESS, SPR_NOACCESS,
3286 &spr_read_generic, &spr_write_generic,
3287 0x00000000);
3288 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3289 SPR_NOACCESS, SPR_NOACCESS,
3290 &spr_read_generic, &spr_write_generic,
3291 0x00000000);
3292 /* XXX : not implemented */
3293 spr_register(env, SPR_440_CCR1, "CCR1",
3294 SPR_NOACCESS, SPR_NOACCESS,
3295 &spr_read_generic, &spr_write_generic,
3296 0x00000000);
3297 /* Memory management */
3298#if !defined(CONFIG_USER_ONLY)
3299 env->nb_tlb = 64;
3300 env->nb_ways = 1;
3301 env->id_tlbs = 0;
3302#endif
3303 init_excp_BookE(env);
3304 env->dcache_line_size = 32;
3305 env->icache_line_size = 32;
3306 /* XXX: TODO: allocate internal IRQ controller */
3307}
3308
3309/* PowerPC 440 GP */
3310#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \
3311 PPC_DCR | PPC_DCRX | \
3312 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3313 PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3314 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3315#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3316#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3317#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3318#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3319#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3320#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3321 POWERPC_FLAG_DE)
3322#define check_pow_440GP check_pow_nocheck
3323
3324__attribute__ (( unused ))
3325static void init_proc_440GP (CPUPPCState *env)
3326{
3327 /* Time base */
3328 gen_tbl(env);
3329 gen_spr_BookE(env, 0x000000000000FFFFULL);
3330 gen_spr_440(env);
3331 gen_spr_usprgh(env);
3332 /* Processor identification */
3333 spr_register(env, SPR_BOOKE_PIR, "PIR",
3334 SPR_NOACCESS, SPR_NOACCESS,
3335 &spr_read_generic, &spr_write_pir,
3336 0x00000000);
3337 /* XXX : not implemented */
3338 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3339 SPR_NOACCESS, SPR_NOACCESS,
3340 &spr_read_generic, &spr_write_generic,
3341 0x00000000);
3342 /* XXX : not implemented */
3343 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3344 SPR_NOACCESS, SPR_NOACCESS,
3345 &spr_read_generic, &spr_write_generic,
3346 0x00000000);
3347 /* XXX : not implemented */
3348 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3349 SPR_NOACCESS, SPR_NOACCESS,
3350 &spr_read_generic, &spr_write_generic,
3351 0x00000000);
3352 /* XXX : not implemented */
3353 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3354 SPR_NOACCESS, SPR_NOACCESS,
3355 &spr_read_generic, &spr_write_generic,
3356 0x00000000);
3357 /* Memory management */
3358#if !defined(CONFIG_USER_ONLY)
3359 env->nb_tlb = 64;
3360 env->nb_ways = 1;
3361 env->id_tlbs = 0;
3362#endif
3363 init_excp_BookE(env);
3364 env->dcache_line_size = 32;
3365 env->icache_line_size = 32;
3366 /* XXX: TODO: allocate internal IRQ controller */
3367}
3368
3369/* PowerPC 440x4 */
3370#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3371 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3372 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3373 PPC_440_SPEC)
3374#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3375#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3376#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3377#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3378#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3379#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3380 POWERPC_FLAG_DE)
3381#define check_pow_440x4 check_pow_nocheck
3382
3383__attribute__ (( unused ))
3384static void init_proc_440x4 (CPUPPCState *env)
3385{
3386 /* Time base */
3387 gen_tbl(env);
3388 gen_spr_BookE(env, 0x000000000000FFFFULL);
3389 gen_spr_440(env);
3390 gen_spr_usprgh(env);
3391 /* Processor identification */
3392 spr_register(env, SPR_BOOKE_PIR, "PIR",
3393 SPR_NOACCESS, SPR_NOACCESS,
3394 &spr_read_generic, &spr_write_pir,
3395 0x00000000);
3396 /* XXX : not implemented */
3397 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3398 SPR_NOACCESS, SPR_NOACCESS,
3399 &spr_read_generic, &spr_write_generic,
3400 0x00000000);
3401 /* XXX : not implemented */
3402 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3403 SPR_NOACCESS, SPR_NOACCESS,
3404 &spr_read_generic, &spr_write_generic,
3405 0x00000000);
3406 /* XXX : not implemented */
3407 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3408 SPR_NOACCESS, SPR_NOACCESS,
3409 &spr_read_generic, &spr_write_generic,
3410 0x00000000);
3411 /* XXX : not implemented */
3412 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3413 SPR_NOACCESS, SPR_NOACCESS,
3414 &spr_read_generic, &spr_write_generic,
3415 0x00000000);
3416 /* Memory management */
3417#if !defined(CONFIG_USER_ONLY)
3418 env->nb_tlb = 64;
3419 env->nb_ways = 1;
3420 env->id_tlbs = 0;
3421#endif
3422 init_excp_BookE(env);
d63001d1
JM		 3423 env->dcache_line_size = 32;
3424 env->icache_line_size = 32;
80d11f44 3425 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3426}
3427
80d11f44
JM		 3428/* PowerPC 440x5 */
3429#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3430 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3431 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3432 PPC_440_SPEC | PPC_RFMCI)
3433#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3434#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3435#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3436#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3437#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3438#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
25ba3a68 3439 POWERPC_FLAG_DE)
80d11f44 3440#define check_pow_440x5 check_pow_nocheck
a750fc0b 3441
80d11f44
JM		 3442__attribute__ (( unused ))
3443static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3444{
a750fc0b
JM		 3445 /* Time base */
3446 gen_tbl(env);
80d11f44
JM		 3447 gen_spr_BookE(env, 0x000000000000FFFFULL);
3448 gen_spr_440(env);
3449 gen_spr_usprgh(env);
3450 /* Processor identification */
3451 spr_register(env, SPR_BOOKE_PIR, "PIR",
3452 SPR_NOACCESS, SPR_NOACCESS,
3453 &spr_read_generic, &spr_write_pir,
3454 0x00000000);
3455 /* XXX : not implemented */
3456 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3457 SPR_NOACCESS, SPR_NOACCESS,
3458 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3459 0x00000000);
3460 /* XXX : not implemented */
3461 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3462 SPR_NOACCESS, SPR_NOACCESS,
3463 &spr_read_generic, &spr_write_generic,
3464 0x00000000);
3465 /* XXX : not implemented */
3466 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3467 SPR_NOACCESS, SPR_NOACCESS,
3468 &spr_read_generic, &spr_write_generic,
3469 0x00000000);
3470 /* XXX : not implemented */
3471 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3472 SPR_NOACCESS, SPR_NOACCESS,
3473 &spr_read_generic, &spr_write_generic,
3474 0x00000000);
3475 /* XXX : not implemented */
3476 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3477 SPR_NOACCESS, SPR_NOACCESS,
3478 &spr_read_generic, &spr_write_generic,
3479 0x00000000);
3480 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3481 SPR_NOACCESS, SPR_NOACCESS,
3482 &spr_read_generic, &spr_write_generic,
3483 0x00000000);
3484 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3485 SPR_NOACCESS, SPR_NOACCESS,
3486 &spr_read_generic, &spr_write_generic,
3487 0x00000000);
3488 /* XXX : not implemented */
3489 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3490 SPR_NOACCESS, SPR_NOACCESS,
3491 &spr_read_generic, &spr_write_generic,
3492 0x00000000);
3493 /* Memory management */
f2e63a42 3494#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3495 env->nb_tlb = 64;
3496 env->nb_ways = 1;
3497 env->id_tlbs = 0;
f2e63a42 3498#endif
80d11f44 3499 init_excp_BookE(env);
d63001d1
JM		 3500 env->dcache_line_size = 32;
3501 env->icache_line_size = 32;
80d11f44 3502 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3503}
3504
80d11f44
JM		 3505/* PowerPC 460 (guessed) */
3506#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \
3507 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
a750fc0b 3508 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
80d11f44
JM		 3509 PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3510 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3511#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3512#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3513#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3514#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3515#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3516#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
25ba3a68 3517 POWERPC_FLAG_DE)
80d11f44 3518#define check_pow_460 check_pow_nocheck
a750fc0b 3519
80d11f44
JM		 3520__attribute__ (( unused ))
3521static void init_proc_460 (CPUPPCState *env)
3fc6c082 3522{
a750fc0b
JM		 3523 /* Time base */
3524 gen_tbl(env);
80d11f44 3525 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3526 gen_spr_440(env);
80d11f44
JM		 3527 gen_spr_usprgh(env);
3528 /* Processor identification */
3529 spr_register(env, SPR_BOOKE_PIR, "PIR",
3530 SPR_NOACCESS, SPR_NOACCESS,
3531 &spr_read_generic, &spr_write_pir,
3532 0x00000000);
3533 /* XXX : not implemented */
3534 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3535 SPR_NOACCESS, SPR_NOACCESS,
3536 &spr_read_generic, &spr_write_generic,
3537 0x00000000);
3538 /* XXX : not implemented */
3539 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3540 SPR_NOACCESS, SPR_NOACCESS,
3541 &spr_read_generic, &spr_write_generic,
3542 0x00000000);
3543 /* XXX : not implemented */
3544 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3545 SPR_NOACCESS, SPR_NOACCESS,
3546 &spr_read_generic, &spr_write_generic,
3547 0x00000000);
3548 /* XXX : not implemented */
3549 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, &spr_write_generic,
3552 0x00000000);
578bb252 3553 /* XXX : not implemented */
a750fc0b
JM		 3554 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_generic,
3557 0x00000000);
3558 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3559 SPR_NOACCESS, SPR_NOACCESS,
3560 &spr_read_generic, &spr_write_generic,
3561 0x00000000);
3562 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
578bb252 3566 /* XXX : not implemented */
a750fc0b
JM		 3567 spr_register(env, SPR_440_CCR1, "CCR1",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
80d11f44
JM		 3571 /* XXX : not implemented */
3572 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3573 &spr_read_generic, &spr_write_generic,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
a750fc0b 3576 /* Memory management */
f2e63a42 3577#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3578 env->nb_tlb = 64;
3579 env->nb_ways = 1;
3580 env->id_tlbs = 0;
f2e63a42 3581#endif
e1833e1f 3582 init_excp_BookE(env);
d63001d1
JM		 3583 env->dcache_line_size = 32;
3584 env->icache_line_size = 32;
a750fc0b 3585 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3586}
3587
80d11f44
JM		 3588/* PowerPC 460F (guessed) */
3589#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \
3590 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
a750fc0b 3591 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
80d11f44
JM		 3592 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3593 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3594 PPC_FLOAT_STFIWX | \
05332d70
JM		 3595 PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3596 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
80d11f44
JM		 3597#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3598#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3599#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3600#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3601#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3602#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
25ba3a68 3603 POWERPC_FLAG_DE)
80d11f44 3604#define check_pow_460F check_pow_nocheck
a750fc0b 3605
80d11f44
JM		 3606__attribute__ (( unused ))
3607static void init_proc_460F (CPUPPCState *env)
3fc6c082 3608{
a750fc0b
JM		 3609 /* Time base */
3610 gen_tbl(env);
80d11f44 3611 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3612 gen_spr_440(env);
80d11f44
JM		 3613 gen_spr_usprgh(env);
3614 /* Processor identification */
3615 spr_register(env, SPR_BOOKE_PIR, "PIR",
3616 SPR_NOACCESS, SPR_NOACCESS,
3617 &spr_read_generic, &spr_write_pir,
3618 0x00000000);
3619 /* XXX : not implemented */
3620 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3621 SPR_NOACCESS, SPR_NOACCESS,
3622 &spr_read_generic, &spr_write_generic,
3623 0x00000000);
3624 /* XXX : not implemented */
3625 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 /* XXX : not implemented */
3630 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
3648 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3649 SPR_NOACCESS, SPR_NOACCESS,
3650 &spr_read_generic, &spr_write_generic,
3651 0x00000000);
3652 /* XXX : not implemented */
3653 spr_register(env, SPR_440_CCR1, "CCR1",
3654 SPR_NOACCESS, SPR_NOACCESS,
3655 &spr_read_generic, &spr_write_generic,
3656 0x00000000);
3657 /* XXX : not implemented */
3658 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3659 &spr_read_generic, &spr_write_generic,
3660 &spr_read_generic, &spr_write_generic,
3661 0x00000000);
a750fc0b 3662 /* Memory management */
f2e63a42 3663#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3664 env->nb_tlb = 64;
3665 env->nb_ways = 1;
3666 env->id_tlbs = 0;
f2e63a42 3667#endif
e1833e1f 3668 init_excp_BookE(env);
d63001d1
JM		 3669 env->dcache_line_size = 32;
3670 env->icache_line_size = 32;
a750fc0b 3671 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3672}
3673
80d11f44
JM		 3674/* Freescale 5xx cores (aka RCPU) */
3675#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3676 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3677 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3678 PPC_MFTB)
3679#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3680#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3681#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3682#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3683#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
3684#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
3685#define check_pow_MPC5xx check_pow_none
3686
3687__attribute__ (( unused ))
3688static void init_proc_MPC5xx (CPUPPCState *env)
3689{
3690 /* Time base */
3691 gen_tbl(env);
3692 gen_spr_5xx_8xx(env);
3693 gen_spr_5xx(env);
3694 init_excp_MPC5xx(env);
3695 env->dcache_line_size = 32;
3696 env->icache_line_size = 32;
3697 /* XXX: TODO: allocate internal IRQ controller */
3698}
3699
3700/* Freescale 8xx cores (aka PowerQUICC) */
3701#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3702 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3703 PPC_CACHE_ICBI | PPC_MFTB)
3704#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3705#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3706#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3707#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3708#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
3709#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
3710#define check_pow_MPC8xx check_pow_none
3711
3712__attribute__ (( unused ))
3713static void init_proc_MPC8xx (CPUPPCState *env)
3714{
3715 /* Time base */
3716 gen_tbl(env);
3717 gen_spr_5xx_8xx(env);
3718 gen_spr_8xx(env);
3719 init_excp_MPC8xx(env);
3720 env->dcache_line_size = 32;
3721 env->icache_line_size = 32;
3722 /* XXX: TODO: allocate internal IRQ controller */
3723}
3724
3725/* Freescale 82xx cores (aka PowerQUICC-II) */
3726/* PowerPC G2 */
3727#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3728#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3729#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3730//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3731#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3732#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3733#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3734 POWERPC_FLAG_BE)
3735#define check_pow_G2 check_pow_hid0
a750fc0b 3736
80d11f44 3737static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3738{
80d11f44
JM		 3739 gen_spr_ne_601(env);
3740 gen_spr_G2_755(env);
3741 gen_spr_G2(env);
a750fc0b
JM		 3742 /* Time base */
3743 gen_tbl(env);
80d11f44
JM		 3744 /* Hardware implementation register */
3745 /* XXX : not implemented */
3746 spr_register(env, SPR_HID0, "HID0",
3747 SPR_NOACCESS, SPR_NOACCESS,
3748 &spr_read_generic, &spr_write_generic,
3749 0x00000000);
3750 /* XXX : not implemented */
3751 spr_register(env, SPR_HID1, "HID1",
3752 SPR_NOACCESS, SPR_NOACCESS,
3753 &spr_read_generic, &spr_write_generic,
3754 0x00000000);
3755 /* XXX : not implemented */
3756 spr_register(env, SPR_HID2, "HID2",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
a750fc0b 3760 /* Memory management */
80d11f44
JM		 3761 gen_low_BATs(env);
3762 gen_high_BATs(env);
3763 gen_6xx_7xx_soft_tlb(env, 64, 2);
3764 init_excp_G2(env);
d63001d1
JM		 3765 env->dcache_line_size = 32;
3766 env->icache_line_size = 32;
80d11f44
JM		 3767 /* Allocate hardware IRQ controller */
3768 ppc6xx_irq_init(env);
3fc6c082 3769}
a750fc0b 3770
80d11f44
JM		 3771/* PowerPC G2LE */
3772#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3773#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3774#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3775#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3776#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3777#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3778#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3779 POWERPC_FLAG_BE)
3780#define check_pow_G2LE check_pow_hid0
a750fc0b 3781
80d11f44 3782static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3783{
80d11f44
JM		 3784 gen_spr_ne_601(env);
3785 gen_spr_G2_755(env);
3786 gen_spr_G2(env);
a750fc0b
JM		 3787 /* Time base */
3788 gen_tbl(env);
80d11f44 3789 /* Hardware implementation register */
578bb252 3790 /* XXX : not implemented */
80d11f44 3791 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
80d11f44
JM		 3795 /* XXX : not implemented */
3796 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
578bb252 3800 /* XXX : not implemented */
80d11f44 3801 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* Memory management */
80d11f44
JM		 3806 gen_low_BATs(env);
3807 gen_high_BATs(env);
3808 gen_6xx_7xx_soft_tlb(env, 64, 2);
3809 init_excp_G2(env);
d63001d1
JM		 3810 env->dcache_line_size = 32;
3811 env->icache_line_size = 32;
80d11f44
JM		 3812 /* Allocate hardware IRQ controller */
3813 ppc6xx_irq_init(env);
3fc6c082
FB		 3814}
3815
80d11f44
JM		 3816/* e200 core */
3817/* XXX: unimplemented instructions:
3818 * dcblc
3819 * dcbtlst
3820 * dcbtstls
3821 * icblc
3822 * icbtls
3823 * tlbivax
3824 * all SPE multiply-accumulate instructions
3825 */
3826#define POWERPC_INSNS_e200 (POWERPC_INSNS_EMB | PPC_ISEL | \
3827 PPC_SPE | PPC_SPEFPU | \
3828 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3829 PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
3830 PPC_BOOKE | PPC_RFDI)
3831#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3832#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3833#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3834#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3835#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3836#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
3837 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
3838#define check_pow_e200 check_pow_hid0
3839
578bb252 3840__attribute__ (( unused ))
80d11f44 3841static void init_proc_e200 (CPUPPCState *env)
3fc6c082 3842{
e1833e1f
JM		 3843 /* Time base */
3844 gen_tbl(env);
80d11f44 3845 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 3846 /* XXX : not implemented */
80d11f44 3847 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
e1833e1f
JM		 3848 SPR_NOACCESS, SPR_NOACCESS,
3849 &spr_read_generic, &spr_write_generic,
3850 0x00000000);
80d11f44
JM		 3851 /* Memory management */
3852 gen_spr_BookE_FSL(env, 0x0000005D);
3853 /* XXX : not implemented */
3854 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 3855 SPR_NOACCESS, SPR_NOACCESS,
3856 &spr_read_generic, &spr_write_generic,
3857 0x00000000);
80d11f44
JM		 3858 /* XXX : not implemented */
3859 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 3860 SPR_NOACCESS, SPR_NOACCESS,
3861 &spr_read_generic, &spr_write_generic,
3862 0x00000000);
578bb252 3863 /* XXX : not implemented */
80d11f44 3864 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, &spr_write_generic,
3867 0x00000000);
578bb252 3868 /* XXX : not implemented */
80d11f44
JM		 3869 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3870 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 3871 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3872 0x00000000);
3873 /* XXX : not implemented */
3874 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3875 SPR_NOACCESS, SPR_NOACCESS,
3876 &spr_read_generic, &spr_write_generic,
3877 0x00000000);
3878 /* XXX : not implemented */
3879 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 /* XXX : not implemented */
3884 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3885 SPR_NOACCESS, SPR_NOACCESS,
3886 &spr_read_generic, &spr_write_generic,
3887 0x00000000);
3888 /* XXX : not implemented */
3889 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3890 SPR_NOACCESS, SPR_NOACCESS,
3891 &spr_read_generic, &spr_write_generic,
3892 0x00000000);
3893 /* XXX : not implemented */
3894 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3895 SPR_NOACCESS, SPR_NOACCESS,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
3898 /* XXX : not implemented */
3899 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 /* XXX : not implemented */
3904 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
3908 /* XXX : not implemented */
3909 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3910 SPR_NOACCESS, SPR_NOACCESS,
3911 &spr_read_generic, &spr_write_generic,
3912 0x00000000);
3913 /* XXX : not implemented */
3914 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3915 SPR_NOACCESS, SPR_NOACCESS,
3916 &spr_read_generic, &spr_write_generic,
3917 0x00000000);
3918 /* XXX : not implemented */
3919 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3920 SPR_NOACCESS, SPR_NOACCESS,
3921 &spr_read_generic, &spr_write_generic,
3922 0x00000000);
3923 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
3927 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3928 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 3929 &spr_read_generic, &spr_write_generic,
3930 0x00000000);
f2e63a42 3931#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 3932 env->nb_tlb = 64;
3933 env->nb_ways = 1;
3934 env->id_tlbs = 0;
f2e63a42 3935#endif
80d11f44 3936 init_excp_e200(env);
d63001d1
JM		 3937 env->dcache_line_size = 32;
3938 env->icache_line_size = 32;
e1833e1f 3939 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3940}
a750fc0b 3941
80d11f44
JM		 3942/* e300 core */
3943#define POWERPC_INSNS_e300 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3944#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
3945#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
3946#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
3947#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
3948#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
3949#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3950 POWERPC_FLAG_BE)
3951#define check_pow_e300 check_pow_hid0
a750fc0b 3952
578bb252 3953__attribute__ (( unused ))
80d11f44 3954static void init_proc_e300 (CPUPPCState *env)
3fc6c082 3955{
80d11f44
JM		 3956 gen_spr_ne_601(env);
3957 gen_spr_603(env);
a750fc0b
JM		 3958 /* Time base */
3959 gen_tbl(env);
80d11f44
JM		 3960 /* hardware implementation registers */
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_HID0, "HID0",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_HID1, "HID1",
3968 SPR_NOACCESS, SPR_NOACCESS,
3969 &spr_read_generic, &spr_write_generic,
3970 0x00000000);
3971 /* Memory management */
3972 gen_low_BATs(env);
3973 gen_6xx_7xx_soft_tlb(env, 64, 2);
3974 init_excp_603(env);
3975 env->dcache_line_size = 32;
3976 env->icache_line_size = 32;
3977 /* Allocate hardware IRQ controller */
3978 ppc6xx_irq_init(env);
3979}
3980
3981/* e500 core */
3982#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | PPC_ISEL | \
3983 PPC_SPE | PPC_SPEFPU | \
3984 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3985 PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
3986 PPC_BOOKE | PPC_RFDI)
3987#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
3988#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
3989#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
3990#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3991#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
3992#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
3993 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
3994#define check_pow_e500 check_pow_hid0
3995
3996__attribute__ (( unused ))
3997static void init_proc_e500 (CPUPPCState *env)
3998{
3999 /* Time base */
4000 gen_tbl(env);
4001 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4002 /* Processor identification */
4003 spr_register(env, SPR_BOOKE_PIR, "PIR",
4004 SPR_NOACCESS, SPR_NOACCESS,
4005 &spr_read_generic, &spr_write_pir,
4006 0x00000000);
4007 /* XXX : not implemented */
4008 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4009 SPR_NOACCESS, SPR_NOACCESS,
4010 &spr_read_generic, &spr_write_generic,
4011 0x00000000);
4012 /* Memory management */
4013#if !defined(CONFIG_USER_ONLY)
4014 env->nb_pids = 3;
4015#endif
4016 gen_spr_BookE_FSL(env, 0x0000005F);
4017 /* XXX : not implemented */
4018 spr_register(env, SPR_HID0, "HID0",
4019 SPR_NOACCESS, SPR_NOACCESS,
4020 &spr_read_generic, &spr_write_generic,
4021 0x00000000);
4022 /* XXX : not implemented */
4023 spr_register(env, SPR_HID1, "HID1",
4024 SPR_NOACCESS, SPR_NOACCESS,
4025 &spr_read_generic, &spr_write_generic,
4026 0x00000000);
4027 /* XXX : not implemented */
4028 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4029 SPR_NOACCESS, SPR_NOACCESS,
4030 &spr_read_generic, &spr_write_generic,
4031 0x00000000);
4032 /* XXX : not implemented */
4033 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4034 SPR_NOACCESS, SPR_NOACCESS,
4035 &spr_read_generic, &spr_write_generic,
4036 0x00000000);
4037 /* XXX : not implemented */
4038 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4039 SPR_NOACCESS, SPR_NOACCESS,
4040 &spr_read_generic, &spr_write_generic,
4041 0x00000000);
578bb252 4042 /* XXX : not implemented */
a750fc0b
JM		 4043 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4044 SPR_NOACCESS, SPR_NOACCESS,
4045 &spr_read_generic, &spr_write_generic,
4046 0x00000000);
80d11f44
JM		 4047 /* XXX : not implemented */
4048 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4049 SPR_NOACCESS, SPR_NOACCESS,
4050 &spr_read_generic, &spr_write_generic,
4051 0x00000000);
80d11f44
JM		 4052 /* XXX : not implemented */
4053 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4054 SPR_NOACCESS, SPR_NOACCESS,
4055 &spr_read_generic, &spr_write_generic,
4056 0x00000000);
578bb252 4057 /* XXX : not implemented */
80d11f44 4058 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4059 SPR_NOACCESS, SPR_NOACCESS,
4060 &spr_read_generic, &spr_write_generic,
4061 0x00000000);
578bb252 4062 /* XXX : not implemented */
80d11f44
JM		 4063 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4064 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4065 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4083 SPR_NOACCESS, SPR_NOACCESS,
4084 &spr_read_generic, &spr_write_generic,
4085 0x00000000);
4086 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4087 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
f2e63a42 4090#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4091 env->nb_tlb = 64;
4092 env->nb_ways = 1;
4093 env->id_tlbs = 0;
f2e63a42 4094#endif
80d11f44 4095 init_excp_e200(env);
d63001d1
JM		 4096 env->dcache_line_size = 32;
4097 env->icache_line_size = 32;
a750fc0b 4098 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4099}
a750fc0b 4100
a750fc0b
JM		 4101/* Non-embedded PowerPC */
4102/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
05332d70 4103#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | \
1b413d55
JM		 4104 PPC_CACHE | PPC_CACHE_ICBI | \
4105 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
a750fc0b
JM		 4106/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
4107#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4108 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4109 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
12de9a39
JM		 4110 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
4111 PPC_SEGMENT)
a750fc0b
JM		 4112
4113/* POWER : same as 601, without mfmsr, mfsr */
4114#if defined(TODO)
4115#define POWERPC_INSNS_POWER (XXX_TODO)
4116/* POWER RSC (from RAD6000) */
4117#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4118#endif /* TODO */
4119
4120/* PowerPC 601 */
d63001d1 4121#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
12de9a39 4122 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
25ba3a68 4123#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
faadf50e 4124//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4125//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4126#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4127#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
25ba3a68 4128#define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
2f462816 4129#define check_pow_601 check_pow_none
a750fc0b
JM		 4130
4131static void init_proc_601 (CPUPPCState *env)
3fc6c082 4132{
a750fc0b
JM		 4133 gen_spr_ne_601(env);
4134 gen_spr_601(env);
4135 /* Hardware implementation registers */
4136 /* XXX : not implemented */
4137 spr_register(env, SPR_HID0, "HID0",
4138 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4139 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4140 0x80010080);
a750fc0b
JM		 4141 /* XXX : not implemented */
4142 spr_register(env, SPR_HID1, "HID1",
4143 SPR_NOACCESS, SPR_NOACCESS,
4144 &spr_read_generic, &spr_write_generic,
4145 0x00000000);
4146 /* XXX : not implemented */
4147 spr_register(env, SPR_601_HID2, "HID2",
4148 SPR_NOACCESS, SPR_NOACCESS,
4149 &spr_read_generic, &spr_write_generic,
4150 0x00000000);
4151 /* XXX : not implemented */
4152 spr_register(env, SPR_601_HID5, "HID5",
4153 SPR_NOACCESS, SPR_NOACCESS,
4154 &spr_read_generic, &spr_write_generic,
4155 0x00000000);
4156 /* XXX : not implemented */
4157 spr_register(env, SPR_601_HID15, "HID15",
4158 SPR_NOACCESS, SPR_NOACCESS,
4159 &spr_read_generic, &spr_write_generic,
4160 0x00000000);
4161 /* Memory management */
f2e63a42 4162#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4163 env->nb_tlb = 64;
4164 env->nb_ways = 2;
4165 env->id_tlbs = 0;
f2e63a42 4166#endif
e1833e1f 4167 init_excp_601(env);
d63001d1
JM		 4168 env->dcache_line_size = 64;
4169 env->icache_line_size = 64;
faadf50e
JM		 4170 /* Allocate hardware IRQ controller */
4171 ppc6xx_irq_init(env);
3fc6c082
FB		 4172}
4173
a750fc0b
JM		 4174/* PowerPC 602 */
4175#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
4176 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4177 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
d63001d1 4178 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
12de9a39 4179 PPC_SEGMENT | PPC_602_SPEC)
a750fc0b
JM		 4180#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
4181#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4182//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4183#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4184#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68
JM		 4185#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4186 POWERPC_FLAG_BE)
2f462816 4187#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4188
4189static void init_proc_602 (CPUPPCState *env)
3fc6c082 4190{
a750fc0b
JM		 4191 gen_spr_ne_601(env);
4192 gen_spr_602(env);
4193 /* Time base */
4194 gen_tbl(env);
4195 /* hardware implementation registers */
4196 /* XXX : not implemented */
4197 spr_register(env, SPR_HID0, "HID0",
4198 SPR_NOACCESS, SPR_NOACCESS,
4199 &spr_read_generic, &spr_write_generic,
4200 0x00000000);
4201 /* XXX : not implemented */
4202 spr_register(env, SPR_HID1, "HID1",
4203 SPR_NOACCESS, SPR_NOACCESS,
4204 &spr_read_generic, &spr_write_generic,
4205 0x00000000);
4206 /* Memory management */
4207 gen_low_BATs(env);
4208 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4209 init_excp_602(env);
d63001d1
JM		 4210 env->dcache_line_size = 32;
4211 env->icache_line_size = 32;
a750fc0b
JM		 4212 /* Allocate hardware IRQ controller */
4213 ppc6xx_irq_init(env);
4214}
3fc6c082 4215
a750fc0b
JM		 4216/* PowerPC 603 */
4217#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
25ba3a68 4218#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4219#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4220//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4221#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4222#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68
JM		 4223#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4224 POWERPC_FLAG_BE)
2f462816 4225#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4226
4227static void init_proc_603 (CPUPPCState *env)
4228{
4229 gen_spr_ne_601(env);
4230 gen_spr_603(env);
4231 /* Time base */
4232 gen_tbl(env);
4233 /* hardware implementation registers */
4234 /* XXX : not implemented */
4235 spr_register(env, SPR_HID0, "HID0",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_generic, &spr_write_generic,
4238 0x00000000);
4239 /* XXX : not implemented */
4240 spr_register(env, SPR_HID1, "HID1",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 /* Memory management */
4245 gen_low_BATs(env);
4246 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4247 init_excp_603(env);
d63001d1
JM		 4248 env->dcache_line_size = 32;
4249 env->icache_line_size = 32;
a750fc0b
JM		 4250 /* Allocate hardware IRQ controller */
4251 ppc6xx_irq_init(env);
3fc6c082
FB		 4252}
4253
a750fc0b
JM		 4254/* PowerPC 603e */
4255#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
4256#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4257#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4258//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4259#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4260#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68
JM		 4261#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4262 POWERPC_FLAG_BE)
2f462816 4263#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4264
4265static void init_proc_603E (CPUPPCState *env)
4266{
4267 gen_spr_ne_601(env);
4268 gen_spr_603(env);
4269 /* Time base */
4270 gen_tbl(env);
4271 /* hardware implementation registers */
4272 /* XXX : not implemented */
4273 spr_register(env, SPR_HID0, "HID0",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277 /* XXX : not implemented */
4278 spr_register(env, SPR_HID1, "HID1",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_IABR, "IABR",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 /* Memory management */
4288 gen_low_BATs(env);
4289 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4290 init_excp_603(env);
d63001d1
JM		 4291 env->dcache_line_size = 32;
4292 env->icache_line_size = 32;
a750fc0b
JM		 4293 /* Allocate hardware IRQ controller */
4294 ppc6xx_irq_init(env);
4295}
4296
a750fc0b
JM		 4297/* PowerPC 604 */
4298#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
4299#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4300#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4301//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4302#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4303#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68
JM		 4304#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4305 POWERPC_FLAG_PMM)
2f462816 4306#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4307
4308static void init_proc_604 (CPUPPCState *env)
4309{
4310 gen_spr_ne_601(env);
4311 gen_spr_604(env);
4312 /* Time base */
4313 gen_tbl(env);
4314 /* Hardware implementation registers */
4315 /* XXX : not implemented */
4316 spr_register(env, SPR_HID0, "HID0",
4317 SPR_NOACCESS, SPR_NOACCESS,
4318 &spr_read_generic, &spr_write_generic,
4319 0x00000000);
4320 /* XXX : not implemented */
4321 spr_register(env, SPR_HID1, "HID1",
4322 SPR_NOACCESS, SPR_NOACCESS,
4323 &spr_read_generic, &spr_write_generic,
4324 0x00000000);
4325 /* Memory management */
4326 gen_low_BATs(env);
e1833e1f 4327 init_excp_604(env);
d63001d1
JM		 4328 env->dcache_line_size = 32;
4329 env->icache_line_size = 32;
a750fc0b
JM		 4330 /* Allocate hardware IRQ controller */
4331 ppc6xx_irq_init(env);
4332}
4333
4334/* PowerPC 740/750 (aka G3) */
4335#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
25ba3a68 4336#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
a750fc0b
JM		 4337#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
4338//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
4339#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 4340#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
25ba3a68
JM		 4341#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4342 POWERPC_FLAG_PMM)
2f462816 4343#define check_pow_7x0 check_pow_hid0
a750fc0b
JM		 4344
4345static void init_proc_7x0 (CPUPPCState *env)
4346{
4347 gen_spr_ne_601(env);
4348 gen_spr_7xx(env);
4349 /* Time base */
4350 gen_tbl(env);
4351 /* Thermal management */
4352 gen_spr_thrm(env);
4353 /* Hardware implementation registers */
4354 /* XXX : not implemented */
4355 spr_register(env, SPR_HID0, "HID0",
4356 SPR_NOACCESS, SPR_NOACCESS,
4357 &spr_read_generic, &spr_write_generic,
4358 0x00000000);
4359 /* XXX : not implemented */
4360 spr_register(env, SPR_HID1, "HID1",
4361 SPR_NOACCESS, SPR_NOACCESS,
4362 &spr_read_generic, &spr_write_generic,
4363 0x00000000);
4364 /* Memory management */
4365 gen_low_BATs(env);
e1833e1f 4366 init_excp_7x0(env);
d63001d1
JM		 4367 env->dcache_line_size = 32;
4368 env->icache_line_size = 32;
a750fc0b
JM		 4369 /* Allocate hardware IRQ controller */
4370 ppc6xx_irq_init(env);
4371}
4372
4373/* PowerPC 750FX/GX */
4374#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
25ba3a68 4375#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4376#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4377#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4378#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4379#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68
JM		 4380#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4381 POWERPC_FLAG_PMM)
2f462816 4382#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4383
4384static void init_proc_750fx (CPUPPCState *env)
4385{
4386 gen_spr_ne_601(env);
4387 gen_spr_7xx(env);
4388 /* Time base */
4389 gen_tbl(env);
4390 /* Thermal management */
4391 gen_spr_thrm(env);
4392 /* Hardware implementation registers */
4393 /* XXX : not implemented */
4394 spr_register(env, SPR_HID0, "HID0",
4395 SPR_NOACCESS, SPR_NOACCESS,
4396 &spr_read_generic, &spr_write_generic,
4397 0x00000000);
4398 /* XXX : not implemented */
4399 spr_register(env, SPR_HID1, "HID1",
4400 SPR_NOACCESS, SPR_NOACCESS,
4401 &spr_read_generic, &spr_write_generic,
4402 0x00000000);
4403 /* XXX : not implemented */
4404 spr_register(env, SPR_750_HID2, "HID2",
4405 SPR_NOACCESS, SPR_NOACCESS,
4406 &spr_read_generic, &spr_write_generic,
4407 0x00000000);
4408 /* Memory management */
4409 gen_low_BATs(env);
4410 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4411 gen_high_BATs(env);
e1833e1f 4412 init_excp_750FX(env);
d63001d1
JM		 4413 env->dcache_line_size = 32;
4414 env->icache_line_size = 32;
a750fc0b
JM		 4415 /* Allocate hardware IRQ controller */
4416 ppc6xx_irq_init(env);
4417}
4418
4419/* PowerPC 745/755 */
4420#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
25ba3a68 4421#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
a750fc0b
JM		 4422#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
4423//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
4424#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 4425#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
25ba3a68
JM		 4426#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4427 POWERPC_FLAG_PMM)
2f462816 4428#define check_pow_7x5 check_pow_hid0
a750fc0b
JM		 4429
4430static void init_proc_7x5 (CPUPPCState *env)
4431{
4432 gen_spr_ne_601(env);
4433 gen_spr_G2_755(env);
4434 /* Time base */
4435 gen_tbl(env);
4436 /* L2 cache control */
4437 /* XXX : not implemented */
4438 spr_register(env, SPR_ICTC, "ICTC",
4439 SPR_NOACCESS, SPR_NOACCESS,
4440 &spr_read_generic, &spr_write_generic,
4441 0x00000000);
4442 /* XXX : not implemented */
4443 spr_register(env, SPR_L2PMCR, "L2PMCR",
4444 SPR_NOACCESS, SPR_NOACCESS,
4445 &spr_read_generic, &spr_write_generic,
4446 0x00000000);
4447 /* Hardware implementation registers */
4448 /* XXX : not implemented */
4449 spr_register(env, SPR_HID0, "HID0",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* XXX : not implemented */
4454 spr_register(env, SPR_HID1, "HID1",
4455 SPR_NOACCESS, SPR_NOACCESS,
4456 &spr_read_generic, &spr_write_generic,
4457 0x00000000);
4458 /* XXX : not implemented */
4459 spr_register(env, SPR_HID2, "HID2",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_generic,
4462 0x00000000);
4463 /* Memory management */
4464 gen_low_BATs(env);
4465 gen_high_BATs(env);
4466 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 4467 init_excp_7x5(env);
d63001d1
JM		 4468 env->dcache_line_size = 32;
4469 env->icache_line_size = 32;
a750fc0b
JM		 4470 /* Allocate hardware IRQ controller */
4471 ppc6xx_irq_init(env);
d63001d1
JM		 4472#if !defined(CONFIG_USER_ONLY)
4473 /* Hardware reset vector */
4474 env->hreset_vector = 0xFFFFFFFCUL;
4475#endif
a750fc0b
JM		 4476}
4477
4478/* PowerPC 7400 (aka G4) */
4479#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4480 PPC_EXTERN | PPC_MEM_TLBIA | \
4481 PPC_ALTIVEC)
4482#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
4483#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
4484#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
4485#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 4486#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68
JM		 4487#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4488 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4489#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 4490
4491static void init_proc_7400 (CPUPPCState *env)
4492{
4493 gen_spr_ne_601(env);
4494 gen_spr_7xx(env);
4495 /* Time base */
4496 gen_tbl(env);
4497 /* 74xx specific SPR */
4498 gen_spr_74xx(env);
4499 /* Thermal management */
4500 gen_spr_thrm(env);
4501 /* Memory management */
4502 gen_low_BATs(env);
e1833e1f 4503 init_excp_7400(env);
d63001d1
JM		 4504 env->dcache_line_size = 32;
4505 env->icache_line_size = 32;
a750fc0b
JM		 4506 /* Allocate hardware IRQ controller */
4507 ppc6xx_irq_init(env);
4508}
4509
4510/* PowerPC 7410 (aka G4) */
4511#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4512 PPC_EXTERN | PPC_MEM_TLBIA | \
4513 PPC_ALTIVEC)
4514#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
4515#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
4516#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
4517#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 4518#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68
JM		 4519#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4520 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4521#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 4522
4523static void init_proc_7410 (CPUPPCState *env)
4524{
4525 gen_spr_ne_601(env);
4526 gen_spr_7xx(env);
4527 /* Time base */
4528 gen_tbl(env);
4529 /* 74xx specific SPR */
4530 gen_spr_74xx(env);
4531 /* Thermal management */
4532 gen_spr_thrm(env);
4533 /* L2PMCR */
4534 /* XXX : not implemented */
4535 spr_register(env, SPR_L2PMCR, "L2PMCR",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_generic,
4538 0x00000000);
4539 /* LDSTDB */
4540 /* XXX : not implemented */
4541 spr_register(env, SPR_LDSTDB, "LDSTDB",
4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_generic,
4544 0x00000000);
4545 /* Memory management */
4546 gen_low_BATs(env);
e1833e1f 4547 init_excp_7400(env);
d63001d1
JM		 4548 env->dcache_line_size = 32;
4549 env->icache_line_size = 32;
a750fc0b
JM		 4550 /* Allocate hardware IRQ controller */
4551 ppc6xx_irq_init(env);
4552}
4553
4554/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 4555#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4556 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4557 PPC_ALTIVEC)
4558#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
4559#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
4560#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
4561#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 4562#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68
JM		 4563#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4564 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4565#define check_pow_7440 check_pow_hid0
a750fc0b 4566
578bb252 4567__attribute__ (( unused ))
a750fc0b
JM		 4568static void init_proc_7440 (CPUPPCState *env)
4569{
4570 gen_spr_ne_601(env);
4571 gen_spr_7xx(env);
4572 /* Time base */
4573 gen_tbl(env);
4574 /* 74xx specific SPR */
4575 gen_spr_74xx(env);
4576 /* LDSTCR */
4577 /* XXX : not implemented */
4578 spr_register(env, SPR_LDSTCR, "LDSTCR",
4579 SPR_NOACCESS, SPR_NOACCESS,
4580 &spr_read_generic, &spr_write_generic,
4581 0x00000000);
4582 /* ICTRL */
4583 /* XXX : not implemented */
4584 spr_register(env, SPR_ICTRL, "ICTRL",
4585 SPR_NOACCESS, SPR_NOACCESS,
4586 &spr_read_generic, &spr_write_generic,
4587 0x00000000);
4588 /* MSSSR0 */
578bb252 4589 /* XXX : not implemented */
a750fc0b
JM		 4590 spr_register(env, SPR_MSSSR0, "MSSSR0",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, &spr_write_generic,
4593 0x00000000);
4594 /* PMC */
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_PMC5, "PMC5",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
578bb252 4600 /* XXX : not implemented */
a750fc0b
JM		 4601 spr_register(env, SPR_UPMC5, "UPMC5",
4602 &spr_read_ureg, SPR_NOACCESS,
4603 &spr_read_ureg, SPR_NOACCESS,
4604 0x00000000);
578bb252 4605 /* XXX : not implemented */
a750fc0b
JM		 4606 spr_register(env, SPR_PMC6, "PMC6",
4607 SPR_NOACCESS, SPR_NOACCESS,
4608 &spr_read_generic, &spr_write_generic,
4609 0x00000000);
578bb252 4610 /* XXX : not implemented */
a750fc0b
JM		 4611 spr_register(env, SPR_UPMC6, "UPMC6",
4612 &spr_read_ureg, SPR_NOACCESS,
4613 &spr_read_ureg, SPR_NOACCESS,
4614 0x00000000);
4615 /* Memory management */
4616 gen_low_BATs(env);
578bb252 4617 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 4618 init_excp_7450(env);
d63001d1
JM		 4619 env->dcache_line_size = 32;
4620 env->icache_line_size = 32;
a750fc0b
JM		 4621 /* Allocate hardware IRQ controller */
4622 ppc6xx_irq_init(env);
4623}
a750fc0b
JM		 4624
4625/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 4626#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4627 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4628 PPC_ALTIVEC)
4629#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
4630#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
4631#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
4632#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 4633#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68
JM		 4634#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4635 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4636#define check_pow_7450 check_pow_hid0
a750fc0b 4637
578bb252 4638__attribute__ (( unused ))
a750fc0b
JM		 4639static void init_proc_7450 (CPUPPCState *env)
4640{
4641 gen_spr_ne_601(env);
4642 gen_spr_7xx(env);
4643 /* Time base */
4644 gen_tbl(env);
4645 /* 74xx specific SPR */
4646 gen_spr_74xx(env);
4647 /* Level 3 cache control */
4648 gen_l3_ctrl(env);
4649 /* LDSTCR */
4650 /* XXX : not implemented */
4651 spr_register(env, SPR_LDSTCR, "LDSTCR",
4652 SPR_NOACCESS, SPR_NOACCESS,
4653 &spr_read_generic, &spr_write_generic,
4654 0x00000000);
4655 /* ICTRL */
4656 /* XXX : not implemented */
4657 spr_register(env, SPR_ICTRL, "ICTRL",
4658 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_read_generic, &spr_write_generic,
4660 0x00000000);
4661 /* MSSSR0 */
578bb252 4662 /* XXX : not implemented */
a750fc0b
JM		 4663 spr_register(env, SPR_MSSSR0, "MSSSR0",
4664 SPR_NOACCESS, SPR_NOACCESS,
4665 &spr_read_generic, &spr_write_generic,
4666 0x00000000);
4667 /* PMC */
4668 /* XXX : not implemented */
4669 spr_register(env, SPR_PMC5, "PMC5",
4670 SPR_NOACCESS, SPR_NOACCESS,
4671 &spr_read_generic, &spr_write_generic,
4672 0x00000000);
578bb252 4673 /* XXX : not implemented */
a750fc0b
JM		 4674 spr_register(env, SPR_UPMC5, "UPMC5",
4675 &spr_read_ureg, SPR_NOACCESS,
4676 &spr_read_ureg, SPR_NOACCESS,
4677 0x00000000);
578bb252 4678 /* XXX : not implemented */
a750fc0b
JM		 4679 spr_register(env, SPR_PMC6, "PMC6",
4680 SPR_NOACCESS, SPR_NOACCESS,
4681 &spr_read_generic, &spr_write_generic,
4682 0x00000000);
578bb252 4683 /* XXX : not implemented */
a750fc0b
JM		 4684 spr_register(env, SPR_UPMC6, "UPMC6",
4685 &spr_read_ureg, SPR_NOACCESS,
4686 &spr_read_ureg, SPR_NOACCESS,
4687 0x00000000);
4688 /* Memory management */
4689 gen_low_BATs(env);
578bb252 4690 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4691 init_excp_7450(env);
d63001d1
JM		 4692 env->dcache_line_size = 32;
4693 env->icache_line_size = 32;
a750fc0b
JM		 4694 /* Allocate hardware IRQ controller */
4695 ppc6xx_irq_init(env);
4696}
a750fc0b
JM		 4697
4698/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 4699#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4700 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4701 PPC_ALTIVEC)
4702#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
4703#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
4704#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
4705#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 4706#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68
JM		 4707#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4708 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4709#define check_pow_7445 check_pow_hid0
a750fc0b 4710
578bb252 4711__attribute__ (( unused ))
a750fc0b
JM		 4712static void init_proc_7445 (CPUPPCState *env)
4713{
4714 gen_spr_ne_601(env);
4715 gen_spr_7xx(env);
4716 /* Time base */
4717 gen_tbl(env);
4718 /* 74xx specific SPR */
4719 gen_spr_74xx(env);
4720 /* LDSTCR */
4721 /* XXX : not implemented */
4722 spr_register(env, SPR_LDSTCR, "LDSTCR",
4723 SPR_NOACCESS, SPR_NOACCESS,
4724 &spr_read_generic, &spr_write_generic,
4725 0x00000000);
4726 /* ICTRL */
4727 /* XXX : not implemented */
4728 spr_register(env, SPR_ICTRL, "ICTRL",
4729 SPR_NOACCESS, SPR_NOACCESS,
4730 &spr_read_generic, &spr_write_generic,
4731 0x00000000);
4732 /* MSSSR0 */
578bb252 4733 /* XXX : not implemented */
a750fc0b
JM		 4734 spr_register(env, SPR_MSSSR0, "MSSSR0",
4735 SPR_NOACCESS, SPR_NOACCESS,
4736 &spr_read_generic, &spr_write_generic,
4737 0x00000000);
4738 /* PMC */
4739 /* XXX : not implemented */
4740 spr_register(env, SPR_PMC5, "PMC5",
4741 SPR_NOACCESS, SPR_NOACCESS,
4742 &spr_read_generic, &spr_write_generic,
4743 0x00000000);
578bb252 4744 /* XXX : not implemented */
a750fc0b
JM		 4745 spr_register(env, SPR_UPMC5, "UPMC5",
4746 &spr_read_ureg, SPR_NOACCESS,
4747 &spr_read_ureg, SPR_NOACCESS,
4748 0x00000000);
578bb252 4749 /* XXX : not implemented */
a750fc0b
JM		 4750 spr_register(env, SPR_PMC6, "PMC6",
4751 SPR_NOACCESS, SPR_NOACCESS,
4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
578bb252 4754 /* XXX : not implemented */
a750fc0b
JM		 4755 spr_register(env, SPR_UPMC6, "UPMC6",
4756 &spr_read_ureg, SPR_NOACCESS,
4757 &spr_read_ureg, SPR_NOACCESS,
4758 0x00000000);
4759 /* SPRGs */
4760 spr_register(env, SPR_SPRG4, "SPRG4",
4761 SPR_NOACCESS, SPR_NOACCESS,
4762 &spr_read_generic, &spr_write_generic,
4763 0x00000000);
4764 spr_register(env, SPR_USPRG4, "USPRG4",
4765 &spr_read_ureg, SPR_NOACCESS,
4766 &spr_read_ureg, SPR_NOACCESS,
4767 0x00000000);
4768 spr_register(env, SPR_SPRG5, "SPRG5",
4769 SPR_NOACCESS, SPR_NOACCESS,
4770 &spr_read_generic, &spr_write_generic,
4771 0x00000000);
4772 spr_register(env, SPR_USPRG5, "USPRG5",
4773 &spr_read_ureg, SPR_NOACCESS,
4774 &spr_read_ureg, SPR_NOACCESS,
4775 0x00000000);
4776 spr_register(env, SPR_SPRG6, "SPRG6",
4777 SPR_NOACCESS, SPR_NOACCESS,
4778 &spr_read_generic, &spr_write_generic,
4779 0x00000000);
4780 spr_register(env, SPR_USPRG6, "USPRG6",
4781 &spr_read_ureg, SPR_NOACCESS,
4782 &spr_read_ureg, SPR_NOACCESS,
4783 0x00000000);
4784 spr_register(env, SPR_SPRG7, "SPRG7",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788 spr_register(env, SPR_USPRG7, "USPRG7",
4789 &spr_read_ureg, SPR_NOACCESS,
4790 &spr_read_ureg, SPR_NOACCESS,
4791 0x00000000);
4792 /* Memory management */
4793 gen_low_BATs(env);
4794 gen_high_BATs(env);
578bb252 4795 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4796 init_excp_7450(env);
d63001d1
JM		 4797 env->dcache_line_size = 32;
4798 env->icache_line_size = 32;
a750fc0b
JM		 4799 /* Allocate hardware IRQ controller */
4800 ppc6xx_irq_init(env);
4801}
a750fc0b
JM		 4802
4803/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 4804#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4805 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4806 PPC_ALTIVEC)
4807#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4808#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4809#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4810#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 4811#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68
JM		 4812#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4813 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4814#define check_pow_7455 check_pow_hid0
a750fc0b 4815
578bb252 4816__attribute__ (( unused ))
a750fc0b
JM		 4817static void init_proc_7455 (CPUPPCState *env)
4818{
4819 gen_spr_ne_601(env);
4820 gen_spr_7xx(env);
4821 /* Time base */
4822 gen_tbl(env);
4823 /* 74xx specific SPR */
4824 gen_spr_74xx(env);
4825 /* Level 3 cache control */
4826 gen_l3_ctrl(env);
4827 /* LDSTCR */
4828 /* XXX : not implemented */
4829 spr_register(env, SPR_LDSTCR, "LDSTCR",
4830 SPR_NOACCESS, SPR_NOACCESS,
4831 &spr_read_generic, &spr_write_generic,
4832 0x00000000);
4833 /* ICTRL */
4834 /* XXX : not implemented */
4835 spr_register(env, SPR_ICTRL, "ICTRL",
4836 SPR_NOACCESS, SPR_NOACCESS,
4837 &spr_read_generic, &spr_write_generic,
4838 0x00000000);
4839 /* MSSSR0 */
578bb252 4840 /* XXX : not implemented */
a750fc0b
JM		 4841 spr_register(env, SPR_MSSSR0, "MSSSR0",
4842 SPR_NOACCESS, SPR_NOACCESS,
4843 &spr_read_generic, &spr_write_generic,
4844 0x00000000);
4845 /* PMC */
4846 /* XXX : not implemented */
4847 spr_register(env, SPR_PMC5, "PMC5",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_generic,
4850 0x00000000);
578bb252 4851 /* XXX : not implemented */
a750fc0b
JM		 4852 spr_register(env, SPR_UPMC5, "UPMC5",
4853 &spr_read_ureg, SPR_NOACCESS,
4854 &spr_read_ureg, SPR_NOACCESS,
4855 0x00000000);
578bb252 4856 /* XXX : not implemented */
a750fc0b
JM		 4857 spr_register(env, SPR_PMC6, "PMC6",
4858 SPR_NOACCESS, SPR_NOACCESS,
4859 &spr_read_generic, &spr_write_generic,
4860 0x00000000);
578bb252 4861 /* XXX : not implemented */
a750fc0b
JM		 4862 spr_register(env, SPR_UPMC6, "UPMC6",
4863 &spr_read_ureg, SPR_NOACCESS,
4864 &spr_read_ureg, SPR_NOACCESS,
4865 0x00000000);
4866 /* SPRGs */
4867 spr_register(env, SPR_SPRG4, "SPRG4",
4868 SPR_NOACCESS, SPR_NOACCESS,
4869 &spr_read_generic, &spr_write_generic,
4870 0x00000000);
4871 spr_register(env, SPR_USPRG4, "USPRG4",
4872 &spr_read_ureg, SPR_NOACCESS,
4873 &spr_read_ureg, SPR_NOACCESS,
4874 0x00000000);
4875 spr_register(env, SPR_SPRG5, "SPRG5",
4876 SPR_NOACCESS, SPR_NOACCESS,
4877 &spr_read_generic, &spr_write_generic,
4878 0x00000000);
4879 spr_register(env, SPR_USPRG5, "USPRG5",
4880 &spr_read_ureg, SPR_NOACCESS,
4881 &spr_read_ureg, SPR_NOACCESS,
4882 0x00000000);
4883 spr_register(env, SPR_SPRG6, "SPRG6",
4884 SPR_NOACCESS, SPR_NOACCESS,
4885 &spr_read_generic, &spr_write_generic,
4886 0x00000000);
4887 spr_register(env, SPR_USPRG6, "USPRG6",
4888 &spr_read_ureg, SPR_NOACCESS,
4889 &spr_read_ureg, SPR_NOACCESS,
4890 0x00000000);
4891 spr_register(env, SPR_SPRG7, "SPRG7",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_generic,
4894 0x00000000);
4895 spr_register(env, SPR_USPRG7, "USPRG7",
4896 &spr_read_ureg, SPR_NOACCESS,
4897 &spr_read_ureg, SPR_NOACCESS,
4898 0x00000000);
4899 /* Memory management */
4900 gen_low_BATs(env);
4901 gen_high_BATs(env);
578bb252 4902 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4903 init_excp_7450(env);
d63001d1
JM		 4904 env->dcache_line_size = 32;
4905 env->icache_line_size = 32;
a750fc0b
JM		 4906 /* Allocate hardware IRQ controller */
4907 ppc6xx_irq_init(env);
4908}
a750fc0b
JM		 4909
4910#if defined (TARGET_PPC64)
d63001d1 4911#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
12de9a39
JM		 4912 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4913 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4914 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
a750fc0b 4915/* PowerPC 970 */
d63001d1 4916#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4917 PPC_64B | PPC_ALTIVEC | \
12de9a39 4918 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4919#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 4920#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 4921//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4922#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 4923#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68
JM		 4924#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4925 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 4926
417bf010
JM		 4927#if defined(CONFIG_USER_ONLY)
4928#define POWERPC970_HID5_INIT 0x00000080
4929#else
4930#define POWERPC970_HID5_INIT 0x00000000
4931#endif
4932
2f462816
JM		 4933static int check_pow_970 (CPUPPCState *env)
4934{
4935 if (env->spr[SPR_HID0] & 0x00600000)
4936 return 1;
4937
4938 return 0;
4939}
4940
a750fc0b
JM		 4941static void init_proc_970 (CPUPPCState *env)
4942{
4943 gen_spr_ne_601(env);
4944 gen_spr_7xx(env);
4945 /* Time base */
4946 gen_tbl(env);
4947 /* Hardware implementation registers */
4948 /* XXX : not implemented */
4949 spr_register(env, SPR_HID0, "HID0",
4950 SPR_NOACCESS, SPR_NOACCESS,
06403421 4951 &spr_read_generic, &spr_write_clear,
d63001d1 4952 0x60000000);
a750fc0b
JM		 4953 /* XXX : not implemented */
4954 spr_register(env, SPR_HID1, "HID1",
4955 SPR_NOACCESS, SPR_NOACCESS,
4956 &spr_read_generic, &spr_write_generic,
4957 0x00000000);
4958 /* XXX : not implemented */
4959 spr_register(env, SPR_750_HID2, "HID2",
4960 SPR_NOACCESS, SPR_NOACCESS,
4961 &spr_read_generic, &spr_write_generic,
4962 0x00000000);
e57448f1
JM		 4963 /* XXX : not implemented */
4964 spr_register(env, SPR_970_HID5, "HID5",
4965 SPR_NOACCESS, SPR_NOACCESS,
4966 &spr_read_generic, &spr_write_generic,
417bf010 4967 POWERPC970_HID5_INIT);
a750fc0b
JM		 4968 /* Memory management */
4969 /* XXX: not correct */
4970 gen_low_BATs(env);
12de9a39
JM		 4971 /* XXX : not implemented */
4972 spr_register(env, SPR_MMUCFG, "MMUCFG",
4973 SPR_NOACCESS, SPR_NOACCESS,
4974 &spr_read_generic, SPR_NOACCESS,
4975 0x00000000); /* TOFIX */
4976 /* XXX : not implemented */
4977 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4978 SPR_NOACCESS, SPR_NOACCESS,
4979 &spr_read_generic, &spr_write_generic,
4980 0x00000000); /* TOFIX */
4981 spr_register(env, SPR_HIOR, "SPR_HIOR",
4982 SPR_NOACCESS, SPR_NOACCESS,
4983 &spr_read_generic, &spr_write_generic,
4984 0xFFF00000); /* XXX: This is a hack */
f2e63a42 4985#if !defined(CONFIG_USER_ONLY)
12de9a39 4986 env->slb_nr = 32;
f2e63a42 4987#endif
e1833e1f 4988 init_excp_970(env);
d63001d1
JM		 4989 env->dcache_line_size = 128;
4990 env->icache_line_size = 128;
a750fc0b
JM		 4991 /* Allocate hardware IRQ controller */
4992 ppc970_irq_init(env);
4993}
a750fc0b
JM		 4994
4995/* PowerPC 970FX (aka G5) */
d63001d1 4996#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4997 PPC_64B | PPC_ALTIVEC | \
12de9a39 4998 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4999#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 5000#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 5001#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5002#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 5003#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68
JM		 5004#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5005 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 5006
2f462816
JM		 5007static int check_pow_970FX (CPUPPCState *env)
5008{
5009 if (env->spr[SPR_HID0] & 0x00600000)
5010 return 1;
5011
5012 return 0;
5013}
5014
a750fc0b
JM		 5015static void init_proc_970FX (CPUPPCState *env)
5016{
5017 gen_spr_ne_601(env);
5018 gen_spr_7xx(env);
5019 /* Time base */
5020 gen_tbl(env);
5021 /* Hardware implementation registers */
5022 /* XXX : not implemented */
5023 spr_register(env, SPR_HID0, "HID0",
5024 SPR_NOACCESS, SPR_NOACCESS,
06403421 5025 &spr_read_generic, &spr_write_clear,
d63001d1 5026 0x60000000);
a750fc0b
JM		 5027 /* XXX : not implemented */
5028 spr_register(env, SPR_HID1, "HID1",
5029 SPR_NOACCESS, SPR_NOACCESS,
5030 &spr_read_generic, &spr_write_generic,
5031 0x00000000);
5032 /* XXX : not implemented */
5033 spr_register(env, SPR_750_HID2, "HID2",
5034 SPR_NOACCESS, SPR_NOACCESS,
5035 &spr_read_generic, &spr_write_generic,
5036 0x00000000);
d63001d1
JM		 5037 /* XXX : not implemented */
5038 spr_register(env, SPR_970_HID5, "HID5",
5039 SPR_NOACCESS, SPR_NOACCESS,
5040 &spr_read_generic, &spr_write_generic,
417bf010 5041 POWERPC970_HID5_INIT);
a750fc0b
JM		 5042 /* Memory management */
5043 /* XXX: not correct */
5044 gen_low_BATs(env);
12de9a39
JM		 5045 /* XXX : not implemented */
5046 spr_register(env, SPR_MMUCFG, "MMUCFG",
5047 SPR_NOACCESS, SPR_NOACCESS,
5048 &spr_read_generic, SPR_NOACCESS,
5049 0x00000000); /* TOFIX */
5050 /* XXX : not implemented */
5051 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000); /* TOFIX */
5055 spr_register(env, SPR_HIOR, "SPR_HIOR",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5059#if !defined(CONFIG_USER_ONLY)
12de9a39 5060 env->slb_nr = 32;
f2e63a42 5061#endif
e1833e1f 5062 init_excp_970(env);
d63001d1
JM		 5063 env->dcache_line_size = 128;
5064 env->icache_line_size = 128;
a750fc0b
JM		 5065 /* Allocate hardware IRQ controller */
5066 ppc970_irq_init(env);
5067}
a750fc0b
JM		 5068
5069/* PowerPC 970 GX */
d63001d1 5070#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 5071 PPC_64B | PPC_ALTIVEC | \
12de9a39 5072 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5073#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 5074#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 5075#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
5076#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 5077#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68
JM		 5078#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5079 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 5080
2f462816
JM		 5081static int check_pow_970GX (CPUPPCState *env)
5082{
5083 if (env->spr[SPR_HID0] & 0x00600000)
5084 return 1;
5085
5086 return 0;
5087}
5088
a750fc0b
JM		 5089static void init_proc_970GX (CPUPPCState *env)
5090{
5091 gen_spr_ne_601(env);
5092 gen_spr_7xx(env);
5093 /* Time base */
5094 gen_tbl(env);
5095 /* Hardware implementation registers */
5096 /* XXX : not implemented */
5097 spr_register(env, SPR_HID0, "HID0",
5098 SPR_NOACCESS, SPR_NOACCESS,
06403421 5099 &spr_read_generic, &spr_write_clear,
d63001d1 5100 0x60000000);
a750fc0b
JM		 5101 /* XXX : not implemented */
5102 spr_register(env, SPR_HID1, "HID1",
5103 SPR_NOACCESS, SPR_NOACCESS,
5104 &spr_read_generic, &spr_write_generic,
5105 0x00000000);
5106 /* XXX : not implemented */
5107 spr_register(env, SPR_750_HID2, "HID2",
5108 SPR_NOACCESS, SPR_NOACCESS,
5109 &spr_read_generic, &spr_write_generic,
5110 0x00000000);
d63001d1
JM		 5111 /* XXX : not implemented */
5112 spr_register(env, SPR_970_HID5, "HID5",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
417bf010 5115 POWERPC970_HID5_INIT);
a750fc0b
JM		 5116 /* Memory management */
5117 /* XXX: not correct */
5118 gen_low_BATs(env);
12de9a39
JM		 5119 /* XXX : not implemented */
5120 spr_register(env, SPR_MMUCFG, "MMUCFG",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 &spr_read_generic, SPR_NOACCESS,
5123 0x00000000); /* TOFIX */
5124 /* XXX : not implemented */
5125 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5126 SPR_NOACCESS, SPR_NOACCESS,
5127 &spr_read_generic, &spr_write_generic,
5128 0x00000000); /* TOFIX */
5129 spr_register(env, SPR_HIOR, "SPR_HIOR",
5130 SPR_NOACCESS, SPR_NOACCESS,
5131 &spr_read_generic, &spr_write_generic,
5132 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5133#if !defined(CONFIG_USER_ONLY)
12de9a39 5134 env->slb_nr = 32;
f2e63a42 5135#endif
e1833e1f 5136 init_excp_970(env);
d63001d1
JM		 5137 env->dcache_line_size = 128;
5138 env->icache_line_size = 128;
a750fc0b
JM		 5139 /* Allocate hardware IRQ controller */
5140 ppc970_irq_init(env);
5141}
a750fc0b 5142
2f462816
JM		 5143/* PowerPC 970 MP */
5144#define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
5145 PPC_64B | PPC_ALTIVEC | \
5146 PPC_SEGMENT_64B | PPC_SLBI)
5147#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
5148#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
5149#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
5150#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
5151#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
5152#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5153 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
5154
5155static int check_pow_970MP (CPUPPCState *env)
5156{
5157 if (env->spr[SPR_HID0] & 0x01C00000)
5158 return 1;
5159
5160 return 0;
5161}
5162
5163static void init_proc_970MP (CPUPPCState *env)
5164{
5165 gen_spr_ne_601(env);
5166 gen_spr_7xx(env);
5167 /* Time base */
5168 gen_tbl(env);
5169 /* Hardware implementation registers */
5170 /* XXX : not implemented */
5171 spr_register(env, SPR_HID0, "HID0",
5172 SPR_NOACCESS, SPR_NOACCESS,
5173 &spr_read_generic, &spr_write_clear,
5174 0x60000000);
5175 /* XXX : not implemented */
5176 spr_register(env, SPR_HID1, "HID1",
5177 SPR_NOACCESS, SPR_NOACCESS,
5178 &spr_read_generic, &spr_write_generic,
5179 0x00000000);
5180 /* XXX : not implemented */
5181 spr_register(env, SPR_750_HID2, "HID2",
5182 SPR_NOACCESS, SPR_NOACCESS,
5183 &spr_read_generic, &spr_write_generic,
5184 0x00000000);
5185 /* XXX : not implemented */
5186 spr_register(env, SPR_970_HID5, "HID5",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_generic,
5189 POWERPC970_HID5_INIT);
5190 /* Memory management */
5191 /* XXX: not correct */
5192 gen_low_BATs(env);
5193 /* XXX : not implemented */
5194 spr_register(env, SPR_MMUCFG, "MMUCFG",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_generic, SPR_NOACCESS,
5197 0x00000000); /* TOFIX */
5198 /* XXX : not implemented */
5199 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5200 SPR_NOACCESS, SPR_NOACCESS,
5201 &spr_read_generic, &spr_write_generic,
5202 0x00000000); /* TOFIX */
5203 spr_register(env, SPR_HIOR, "SPR_HIOR",
5204 SPR_NOACCESS, SPR_NOACCESS,
5205 &spr_read_generic, &spr_write_generic,
5206 0xFFF00000); /* XXX: This is a hack */
2f462816
JM		 5207#if !defined(CONFIG_USER_ONLY)
5208 env->slb_nr = 32;
5209#endif
5210 init_excp_970(env);
5211 env->dcache_line_size = 128;
5212 env->icache_line_size = 128;
5213 /* Allocate hardware IRQ controller */
5214 ppc970_irq_init(env);
5215}
5216
a750fc0b 5217/* PowerPC 620 */
a750fc0b
JM		 5218#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
5219 PPC_64B | PPC_SLBI)
5220#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
5221#define POWERPC_MMU_620 (POWERPC_MMU_64B)
5222#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 5223#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 5224#define POWERPC_BFDM_620 (bfd_mach_ppc64)
25ba3a68 5225#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
2f462816 5226#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 5227
578bb252 5228__attribute__ (( unused ))
a750fc0b
JM		 5229static void init_proc_620 (CPUPPCState *env)
5230{
5231 gen_spr_ne_601(env);
5232 gen_spr_620(env);
5233 /* Time base */
5234 gen_tbl(env);
5235 /* Hardware implementation registers */
5236 /* XXX : not implemented */
5237 spr_register(env, SPR_HID0, "HID0",
5238 SPR_NOACCESS, SPR_NOACCESS,
5239 &spr_read_generic, &spr_write_generic,
5240 0x00000000);
5241 /* Memory management */
5242 gen_low_BATs(env);
5243 gen_high_BATs(env);
e1833e1f 5244 init_excp_620(env);
d63001d1
JM		 5245 env->dcache_line_size = 64;
5246 env->icache_line_size = 64;
faadf50e
JM		 5247 /* Allocate hardware IRQ controller */
5248 ppc6xx_irq_init(env);
a750fc0b 5249}
a750fc0b
JM		 5250#endif /* defined (TARGET_PPC64) */
5251
5252/* Default 32 bits PowerPC target will be 604 */
5253#define CPU_POWERPC_PPC32 CPU_POWERPC_604
5254#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
5255#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
5256#define POWERPC_MMU_PPC32 POWERPC_MMU_604
5257#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
5258#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 5259#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 5260#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 5261#define check_pow_PPC32 check_pow_604
5262#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 5263
5264/* Default 64 bits PowerPC target will be 970 FX */
5265#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
5266#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
5267#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
5268#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
5269#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
5270#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 5271#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 5272#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 5273#define check_pow_PPC64 check_pow_970FX
5274#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 5275
5276/* Default PowerPC target will be PowerPC 32 */
5277#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 5278#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
5279#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
5280#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
5281#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
5282#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
5283#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 5284#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 5285#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 5286#define check_pow_DEFAULT check_pow_PPC64
5287#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 5288#else
d12f4c38
JM		 5289#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
5290#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
5291#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
5292#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
5293#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
5294#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 5295#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 5296#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 5297#define check_pow_DEFAULT check_pow_PPC32
5298#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 5299#endif
5300
5301/*****************************************************************************/
5302/* PVR definitions for most known PowerPC */
5303enum {
5304 /* PowerPC 401 family */
5305 /* Generic PowerPC 401 */
80d11f44 5306#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 5307 /* PowerPC 401 cores */
80d11f44
JM		 5308 CPU_POWERPC_401A1 = 0x00210000,
5309 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 5310#if 0
80d11f44 5311 CPU_POWERPC_401B3 = xxx,
a750fc0b 5312#endif
80d11f44
JM		 5313 CPU_POWERPC_401C2 = 0x00230000,
5314 CPU_POWERPC_401D2 = 0x00240000,
5315 CPU_POWERPC_401E2 = 0x00250000,
5316 CPU_POWERPC_401F2 = 0x00260000,
5317 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 5318 /* PowerPC 401 microcontrolers */
5319#if 0
80d11f44 5320 CPU_POWERPC_401GF = xxx,
a750fc0b 5321#endif
80d11f44 5322#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 5323 /* IBM Processor for Network Resources */
80d11f44 5324 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 5325#if 0
80d11f44 5326 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 5327#endif
5328 /* PowerPC 403 family */
5329 /* Generic PowerPC 403 */
80d11f44 5330#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 5331 /* PowerPC 403 microcontrollers */
80d11f44
JM		 5332 CPU_POWERPC_403GA = 0x00200011,
5333 CPU_POWERPC_403GB = 0x00200100,
5334 CPU_POWERPC_403GC = 0x00200200,
5335 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 5336#if 0
80d11f44 5337 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 5338#endif
5339 /* PowerPC 405 family */
5340 /* Generic PowerPC 405 */
80d11f44 5341#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 5342 /* PowerPC 405 cores */
5343#if 0
80d11f44 5344 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 5345#endif
5346#if 0
80d11f44 5347 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 5348#endif
5349#if 0
80d11f44 5350 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 5351#endif
5352#if 0
80d11f44 5353 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 5354#endif
5355#if 0
80d11f44 5356 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 5357#endif
5358#if 0
80d11f44 5359 CPU_POWERPC_405C4 = xxx,
a750fc0b 5360#endif
80d11f44 5361 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 5362#if 0
80d11f44 5363 CPU_POWERPC_405D3 = xxx,
a750fc0b 5364#endif
80d11f44 5365 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 5366#if 0
80d11f44 5367 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 5368#endif
5369#if 0
80d11f44 5370 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 5371#endif
5372#if 0
80d11f44 5373 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 5374#endif
5375#if 0
80d11f44 5376 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 5377#endif
5378#if 0
80d11f44 5379 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 5380#endif
5381 /* PowerPC 405 microcontrolers */
5382 /* XXX: missing 0x200108a0 */
80d11f44
JM		 5383#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
5384 CPU_POWERPC_405CRa = 0x40110041,
5385 CPU_POWERPC_405CRb = 0x401100C5,
5386 CPU_POWERPC_405CRc = 0x40110145,
5387 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 5388#if 0
80d11f44 5389 CPU_POWERPC_405EXr = xxx,
a750fc0b 5390#endif
80d11f44 5391 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 5392#if 0
80d11f44
JM		 5393 CPU_POWERPC_405FX = xxx,
5394#endif
5395#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
5396 CPU_POWERPC_405GPa = 0x40110000,
5397 CPU_POWERPC_405GPb = 0x40110040,
5398 CPU_POWERPC_405GPc = 0x40110082,
5399 CPU_POWERPC_405GPd = 0x401100C4,
5400#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
5401 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 5402#if 0
80d11f44 5403 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 5404#endif
5405#if 0
80d11f44 5406 CPU_POWERPC_405L = xxx,
a750fc0b 5407#endif
80d11f44 5408 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 5409#if 0
80d11f44 5410 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 5411#endif
5412#if 0
80d11f44 5413 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 5414#endif
5415#if 0
80d11f44 5416 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 5417#endif
5418 /* IBM network processors */
80d11f44
JM		 5419 CPU_POWERPC_NPE405H = 0x414100C0,
5420 CPU_POWERPC_NPE405H2 = 0x41410140,
5421 CPU_POWERPC_NPE405L = 0x416100C0,
5422 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 5423#if 0
80d11f44 5424 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 5425#endif
5426#if 0
80d11f44 5427 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 5428#endif
5429#if 0
80d11f44 5430 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 5431#endif
5432 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
5433#if 0
80d11f44 5434 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 5435#endif
5436#if 0
80d11f44 5437 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 5438#endif
5439#if 0
80d11f44 5440 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 5441#endif
80d11f44 5442 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 5443#if 0
80d11f44 5444 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 5445#endif
5446#if 0
80d11f44 5447 CPU_POWERPC_STB045 = xxx,
a750fc0b 5448#endif
80d11f44
JM		 5449 CPU_POWERPC_STB04 = 0x41810000,
5450 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 5451#if 0
80d11f44 5452 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 5453#endif
5454 /* Xilinx cores */
80d11f44
JM		 5455 CPU_POWERPC_X2VP4 = 0x20010820,
5456#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
5457 CPU_POWERPC_X2VP20 = 0x20010860,
5458#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 5459#if 0
80d11f44 5460 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 5461#endif
5462#if 0
80d11f44 5463 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 5464#endif
5465#if 0
80d11f44 5466 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 5467#endif
5468#if 0
80d11f44 5469 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 5470#endif
5471 /* PowerPC 440 family */
5472 /* Generic PowerPC 440 */
80d11f44 5473#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 5474 /* PowerPC 440 cores */
5475#if 0
80d11f44 5476 CPU_POWERPC_440A4 = xxx,
a750fc0b
JM		 5477#endif
5478#if 0
80d11f44 5479 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 5480#endif
5481#if 0
80d11f44 5482 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 5483#endif
5484#if 0
80d11f44 5485 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 5486#endif
5487#if 0
80d11f44 5488 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 5489#endif
5490#if 0
80d11f44 5491 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 5492#endif
5493#if 0
80d11f44 5494 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 5495#endif
5496 /* PowerPC 440 microcontrolers */
80d11f44
JM		 5497#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
5498 CPU_POWERPC_440EPa = 0x42221850,
5499 CPU_POWERPC_440EPb = 0x422218D3,
5500#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
5501 CPU_POWERPC_440GPb = 0x40120440,
5502 CPU_POWERPC_440GPc = 0x40120481,
5503#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
5504#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
5505 CPU_POWERPC_440GRX = 0x200008D0,
5506#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
5507#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
5508 CPU_POWERPC_440GXa = 0x51B21850,
5509 CPU_POWERPC_440GXb = 0x51B21851,
5510 CPU_POWERPC_440GXc = 0x51B21892,
5511 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 5512#if 0
80d11f44 5513 CPU_POWERPC_440S = xxx,
a750fc0b 5514#endif
80d11f44
JM		 5515 CPU_POWERPC_440SP = 0x53221850,
5516 CPU_POWERPC_440SP2 = 0x53221891,
5517 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 5518 /* PowerPC 460 family */
5519#if 0
5520 /* Generic PowerPC 464 */
80d11f44 5521#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 5522#endif
5523 /* PowerPC 464 microcontrolers */
5524#if 0
80d11f44 5525 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 5526#endif
5527#if 0
80d11f44 5528 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 5529#endif
5530 /* Freescale embedded PowerPC cores */
c3e36823 5531 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 5532 CPU_POWERPC_MPC5xx = 0x00020020,
5533#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
5534#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
5535#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
5536#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
5537#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
5538#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
5539#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
5540#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
5541#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
5542#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
5543#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
5544#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
5545#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 5546 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 5547 CPU_POWERPC_MPC8xx = 0x00500000,
5548#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
5549#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
5550#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
5551#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
5552#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
5553#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
5554#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
5555#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
5556#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
5557#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
5558#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
5559#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
5560#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
5561#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
5562#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 5563 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 5564 CPU_POWERPC_G2 = 0x00810011,
5565 CPU_POWERPC_G2H4 = 0x80811010,
5566 CPU_POWERPC_G2gp = 0x80821010,
5567 CPU_POWERPC_G2ls = 0x90810010,
5568 CPU_POWERPC_MPC603 = 0x00810100,
5569 CPU_POWERPC_G2_HIP3 = 0x00810101,
5570 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 5571 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 5572 CPU_POWERPC_G2LE = 0x80820010,
5573 CPU_POWERPC_G2LEgp = 0x80822010,
5574 CPU_POWERPC_G2LEls = 0xA0822010,
5575 CPU_POWERPC_G2LEgp1 = 0x80822011,
5576 CPU_POWERPC_G2LEgp3 = 0x80822013,
5577 /* MPC52xx microcontrollers */
c3e36823 5578 /* XXX: MPC 5121 ? */
80d11f44
JM		 5579#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
5580#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
5581#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
5582#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
5583#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
5584#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
5585#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
5586#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
5587 /* MPC82xx microcontrollers */
5588#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
5589#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
5590#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
5591#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
5592#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
5593#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
5594#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
5595#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
5596#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
5597#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
5598#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
5599#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
5600#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
5601#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
5602#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
5603#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
5604#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
5605#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
5606#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
5607#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
5608#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
5609#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
5610#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
5611#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
5612#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
5613#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
5614#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
5615#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
5616#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 5617 /* e200 family */
80d11f44
JM		 5618 /* e200 cores */
5619#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 5620#if 0
80d11f44 5621 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 5622#endif
5623#if 0
80d11f44 5624 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 5625#endif
5626#if 0 /* ? */
80d11f44
JM		 5627 CPU_POWERPC_e200z3 = 0x81120000,
5628#endif
5629 CPU_POWERPC_e200z5 = 0x81000000,
5630 CPU_POWERPC_e200z6 = 0x81120000,
5631 /* MPC55xx microcontrollers */
5632#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
5633#if 0
5634#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
5635#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
5636#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
5637#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
5638#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
5639#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
5640#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
5641#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
5642#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
5643#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
5644#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
5645#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
5646#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
5647#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
5648#endif
5649#if 0
5650#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
5651#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
5652#endif
5653#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
5654#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
5655#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
5656#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
5657#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
5658#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 5659 /* e300 family */
80d11f44
JM		 5660 /* e300 cores */
5661#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
5662 CPU_POWERPC_e300c1 = 0x00830010,
5663 CPU_POWERPC_e300c2 = 0x00840010,
5664 CPU_POWERPC_e300c3 = 0x00850010,
5665 CPU_POWERPC_e300c4 = 0x00860010,
5666 /* MPC83xx microcontrollers */
5667#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
5668#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
5669#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
5670#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
5671#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
5672#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
5673#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
5674#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
5675#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
5676#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
5677#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
5678#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
5679#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
5680#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
5681#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
5682#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
5683#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
5684#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
5685#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
5686#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
5687#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
5688#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
5689#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
5690#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
5691#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
5692#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
5693#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
5694#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
5695#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
5696#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
a750fc0b 5697 /* e500 family */
80d11f44
JM		 5698 /* e500 cores */
5699#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
5700#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
5701 CPU_POWERPC_e500_v10 = 0x80200010,
5702 CPU_POWERPC_e500_v20 = 0x80200020,
5703 CPU_POWERPC_e500v2_v10 = 0x80210010,
5704 CPU_POWERPC_e500v2_v11 = 0x80210011,
5705 CPU_POWERPC_e500v2_v20 = 0x80210020,
5706 CPU_POWERPC_e500v2_v21 = 0x80210021,
5707 CPU_POWERPC_e500v2_v22 = 0x80210022,
5708 CPU_POWERPC_e500v2_v30 = 0x80210030,
5709 /* MPC85xx microcontrollers */
5710#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
5711#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
5712#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
5713#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
5714#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
5715#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
5716#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
5717#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
5718#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
5719#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
5720#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
5721#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
5722#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
5723#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
5724#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
5725#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
5726#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
5727#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
5728#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
5729#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
5730#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
5731#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
5732#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
5733#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
5734#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
5735#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
5736#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
5737#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
5738#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
5739#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
5740#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
5741#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
5742#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
5743#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
5744#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
5745#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
5746#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
5747#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
5748#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
5749#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
5750#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
5751#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
5752#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
5753#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
5754#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
5755#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
5756#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
5757#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
5758#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
5759#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
5760#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
5761#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
5762#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
5763#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
5764#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
5765#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
5766#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
5767#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
5768#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
5769#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
5770#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
5771#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
5772#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
5773#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
5774#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
5775#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
5776#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
5777#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
5778#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
5779#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 5780 /* e600 family */
80d11f44
JM		 5781 /* e600 cores */
5782 CPU_POWERPC_e600 = 0x80040010,
5783 /* MPC86xx microcontrollers */
5784#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
5785#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
5786#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 5787 /* PowerPC 6xx cores */
80d11f44
JM		 5788#define CPU_POWERPC_601 CPU_POWERPC_601_v2
5789 CPU_POWERPC_601_v0 = 0x00010001,
5790 CPU_POWERPC_601_v1 = 0x00010001,
5791 CPU_POWERPC_601_v2 = 0x00010002,
5792 CPU_POWERPC_602 = 0x00050100,
5793 CPU_POWERPC_603 = 0x00030100,
5794#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
5795 CPU_POWERPC_603E_v11 = 0x00060101,
5796 CPU_POWERPC_603E_v12 = 0x00060102,
5797 CPU_POWERPC_603E_v13 = 0x00060103,
5798 CPU_POWERPC_603E_v14 = 0x00060104,
5799 CPU_POWERPC_603E_v22 = 0x00060202,
5800 CPU_POWERPC_603E_v3 = 0x00060300,
5801 CPU_POWERPC_603E_v4 = 0x00060400,
5802 CPU_POWERPC_603E_v41 = 0x00060401,
5803 CPU_POWERPC_603E7t = 0x00071201,
5804 CPU_POWERPC_603E7v = 0x00070100,
5805 CPU_POWERPC_603E7v1 = 0x00070101,
5806 CPU_POWERPC_603E7v2 = 0x00070201,
5807 CPU_POWERPC_603E7 = 0x00070200,
5808 CPU_POWERPC_603P = 0x00070000,
5809#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 5810 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 5811 CPU_POWERPC_604 = 0x00040103,
5812#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 5813 /* XXX: missing 0x00091203 */
5814 /* XXX: missing 0x00092110 */
5815 /* XXX: missing 0x00092120 */
80d11f44
JM		 5816 CPU_POWERPC_604E_v10 = 0x00090100,
5817 CPU_POWERPC_604E_v22 = 0x00090202,
5818 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 5819 /* XXX: missing 0x000a0100 */
5820 /* XXX: missing 0x00093102 */
80d11f44 5821 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 5822#if 0
80d11f44 5823 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 5824#endif
5825 /* PowerPC 740/750 cores (aka G3) */
5826 /* XXX: missing 0x00084202 */
80d11f44
JM		 5827#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
5828 CPU_POWERPC_7x0_v20 = 0x00080200,
5829 CPU_POWERPC_7x0_v21 = 0x00080201,
5830 CPU_POWERPC_7x0_v22 = 0x00080202,
5831 CPU_POWERPC_7x0_v30 = 0x00080300,
5832 CPU_POWERPC_7x0_v31 = 0x00080301,
5833 CPU_POWERPC_740E = 0x00080100,
5834 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 5835 /* XXX: missing 0x00087010 (CL ?) */
80d11f44
JM		 5836 CPU_POWERPC_750CL = 0x00087200,
5837#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
5838 CPU_POWERPC_750CX_v21 = 0x00082201,
5839 CPU_POWERPC_750CX_v22 = 0x00082202,
5840#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
5841 CPU_POWERPC_750CXE_v21 = 0x00082211,
5842 CPU_POWERPC_750CXE_v22 = 0x00082212,
5843 CPU_POWERPC_750CXE_v23 = 0x00082213,
5844 CPU_POWERPC_750CXE_v24 = 0x00082214,
5845 CPU_POWERPC_750CXE_v24b = 0x00083214,
5846 CPU_POWERPC_750CXE_v31 = 0x00083211,
5847 CPU_POWERPC_750CXE_v31b = 0x00083311,
5848 CPU_POWERPC_750CXR = 0x00083410,
5849 CPU_POWERPC_750E = 0x00080200,
5850 CPU_POWERPC_750FL = 0x700A0203,
5851#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
5852 CPU_POWERPC_750FX_v10 = 0x70000100,
5853 CPU_POWERPC_750FX_v20 = 0x70000200,
5854 CPU_POWERPC_750FX_v21 = 0x70000201,
5855 CPU_POWERPC_750FX_v22 = 0x70000202,
5856 CPU_POWERPC_750FX_v23 = 0x70000203,
5857 CPU_POWERPC_750GL = 0x70020102,
5858#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
5859 CPU_POWERPC_750GX_v10 = 0x70020100,
5860 CPU_POWERPC_750GX_v11 = 0x70020101,
5861 CPU_POWERPC_750GX_v12 = 0x70020102,
5862#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
5863 CPU_POWERPC_750L_v22 = 0x00088202,
5864 CPU_POWERPC_750L_v30 = 0x00088300,
5865 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 5866 /* PowerPC 745/755 cores */
80d11f44
JM		 5867#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
5868 CPU_POWERPC_7x5_v10 = 0x00083100,
5869 CPU_POWERPC_7x5_v11 = 0x00083101,
5870 CPU_POWERPC_7x5_v20 = 0x00083200,
5871 CPU_POWERPC_7x5_v21 = 0x00083201,
5872 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
5873 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
5874 CPU_POWERPC_7x5_v24 = 0x00083204,
5875 CPU_POWERPC_7x5_v25 = 0x00083205,
5876 CPU_POWERPC_7x5_v26 = 0x00083206,
5877 CPU_POWERPC_7x5_v27 = 0x00083207,
5878 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 5879#if 0
80d11f44 5880 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 5881#endif
5882 /* PowerPC 74xx cores (aka G4) */
5883 /* XXX: missing 0x000C1101 */
80d11f44
JM		 5884#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
5885 CPU_POWERPC_7400_v10 = 0x000C0100,
5886 CPU_POWERPC_7400_v11 = 0x000C0101,
5887 CPU_POWERPC_7400_v20 = 0x000C0200,
5888 CPU_POWERPC_7400_v22 = 0x000C0202,
5889 CPU_POWERPC_7400_v26 = 0x000C0206,
5890 CPU_POWERPC_7400_v27 = 0x000C0207,
5891 CPU_POWERPC_7400_v28 = 0x000C0208,
5892 CPU_POWERPC_7400_v29 = 0x000C0209,
5893#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
5894 CPU_POWERPC_7410_v10 = 0x800C1100,
5895 CPU_POWERPC_7410_v11 = 0x800C1101,
5896 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
5897 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
5898 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
5899#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
5900 CPU_POWERPC_7448_v10 = 0x80040100,
5901 CPU_POWERPC_7448_v11 = 0x80040101,
5902 CPU_POWERPC_7448_v20 = 0x80040200,
5903 CPU_POWERPC_7448_v21 = 0x80040201,
5904#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
5905 CPU_POWERPC_7450_v10 = 0x80000100,
5906 CPU_POWERPC_7450_v11 = 0x80000101,
5907 CPU_POWERPC_7450_v12 = 0x80000102,
5908 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
5909 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
5910 CPU_POWERPC_74x1 = 0x80000203,
5911 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
5912#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
5913 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 5914 /* XXX: missing 0x80010200 */
80d11f44
JM		 5915 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
5916 CPU_POWERPC_74x5_v32 = 0x80010302,
5917 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
5918 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
5919#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
c3e36823
JM		 5920 /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
5921 /* XXX: missing 0x80030102 */
5922 /* XXX: missing 0x80020101 */
80d11f44
JM		 5923 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
5924 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
5925 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
a750fc0b 5926 /* 64 bits PowerPC */
00af685f 5927#if defined(TARGET_PPC64)
80d11f44
JM		 5928 CPU_POWERPC_620 = 0x00140000,
5929 CPU_POWERPC_630 = 0x00400000,
5930 CPU_POWERPC_631 = 0x00410104,
5931 CPU_POWERPC_POWER4 = 0x00350000,
5932 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 5933 /* XXX: missing 0x003A0201 */
80d11f44
JM		 5934 CPU_POWERPC_POWER5 = 0x003A0203,
5935#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
5936 CPU_POWERPC_POWER5P = 0x003B0000,
5937#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
5938 CPU_POWERPC_POWER6 = 0x003E0000,
5939 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
5940 CPU_POWERPC_POWER6A = 0x0F000002,
5941 CPU_POWERPC_970 = 0x00390202,
5942#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
5943 CPU_POWERPC_970FX_v10 = 0x00391100,
5944 CPU_POWERPC_970FX_v20 = 0x003C0200,
5945 CPU_POWERPC_970FX_v21 = 0x003C0201,
5946 CPU_POWERPC_970FX_v30 = 0x003C0300,
5947 CPU_POWERPC_970FX_v31 = 0x003C0301,
5948 CPU_POWERPC_970GX = 0x00450000,
5949#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
5950 CPU_POWERPC_970MP_v10 = 0x00440100,
5951 CPU_POWERPC_970MP_v11 = 0x00440101,
5952#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
5953 CPU_POWERPC_CELL_v10 = 0x00700100,
5954 CPU_POWERPC_CELL_v20 = 0x00700400,
5955 CPU_POWERPC_CELL_v30 = 0x00700500,
5956 CPU_POWERPC_CELL_v31 = 0x00700501,
5957#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
5958 CPU_POWERPC_RS64 = 0x00330000,
5959 CPU_POWERPC_RS64II = 0x00340000,
5960 CPU_POWERPC_RS64III = 0x00360000,
5961 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 5962#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 5963 /* Original POWER */
5964 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
5965 * POWER2 (RIOS2) & RSC2 (P2SC) here
5966 */
5967#if 0
80d11f44 5968 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 5969#endif
5970#if 0
80d11f44 5971 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 5972#endif
5973 /* PA Semi core */
80d11f44 5974 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 5975};
5976
5977/* System version register (used on MPC 8xxx) */
5978enum {
80d11f44
JM		 5979 POWERPC_SVR_NONE = 0x00000000,
5980#define POWERPC_SVR_52xx POWERPC_SVR_5200
5981#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
5982 POWERPC_SVR_5200_v10 = 0x80110010,
5983 POWERPC_SVR_5200_v11 = 0x80110011,
5984 POWERPC_SVR_5200_v12 = 0x80110012,
5985#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
5986 POWERPC_SVR_5200B_v20 = 0x80110020,
5987 POWERPC_SVR_5200B_v21 = 0x80110021,
5988#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 5989#if 0
80d11f44 5990 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 5991#endif
5992#if 0
80d11f44 5993 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 5994#endif
5995#if 0
80d11f44 5996 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 5997#endif
5998#if 0
80d11f44 5999 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 6000#endif
6001#if 0
80d11f44 6002 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 6003#endif
6004#if 0
80d11f44 6005 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 6006#endif
6007#if 0
80d11f44 6008 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 6009#endif
6010#if 0
80d11f44 6011 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 6012#endif
6013#if 0
80d11f44 6014 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 6015#endif
6016#if 0
80d11f44 6017 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 6018#endif
6019#if 0
80d11f44 6020 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 6021#endif
6022#if 0
80d11f44 6023 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 6024#endif
6025#if 0
80d11f44 6026 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 6027#endif
6028#if 0
80d11f44 6029 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 6030#endif
6031#if 0
80d11f44 6032 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 6033#endif
6034#if 0
80d11f44 6035 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 6036#endif
6037#if 0
80d11f44 6038 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 6039#endif
6040#if 0
80d11f44
JM		 6041 POWERPC_SVR_8323E = xxx,
6042#endif
6043 POWERPC_SVR_8343A = 0x80570030,
6044 POWERPC_SVR_8343EA = 0x80560030,
6045#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
6046 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
6047 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
6048#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
6049 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
6050 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
6051 POWERPC_SVR_8349 = 0x80510010,
6052 POWERPC_SVR_8349A = 0x80510030,
6053 POWERPC_SVR_8349E = 0x80500010,
6054 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 6055#if 0
80d11f44 6056 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 6057#endif
6058#if 0
80d11f44
JM		 6059 POWERPC_SVR_8360E = xxx,
6060#endif
6061#define POWERPC_SVR_E500 0x40000000
6062 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
6063 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
6064 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
6065 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
6066 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
6067 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
6068#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
6069 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
6070 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
6071#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
6072 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
6073 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
6074#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
6075 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
6076 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
6077 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
6078#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
6079 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
6080 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
6081#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
6082 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
6083 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
6084#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
6085 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
6086 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
6087 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
6088 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
6089#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
6090 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
6091 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
6092 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
6093 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
6094#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
6095 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
6096 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
6097#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
6098 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
6099 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
6100#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
6101 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
6102 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
6103#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
6104 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
6105 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
6106#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
6107 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
6108 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
6109#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
6110 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
6111 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
6112 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
6113 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
6114#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
6115 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
6116 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
6117 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
6118 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
6119#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
6120 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
6121 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
6122#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
6123 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
6124 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
6125#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
6126 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
6127 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
6128 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
6129 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
6130 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
6131 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
6132 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
6133 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
6134 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 6135#if 0
80d11f44 6136 POWERPC_SVR_8610 = xxx,
c3e36823 6137#endif
80d11f44
JM		 6138 POWERPC_SVR_8641 = 0x80900021,
6139 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 6140};
6141
3fc6c082 6142/*****************************************************************************/
a750fc0b 6143/* PowerPC CPU definitions */
80d11f44 6144#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 6145 { \
6146 .name = _name, \
6147 .pvr = _pvr, \
80d11f44 6148 .svr = _svr, \
a750fc0b
JM		 6149 .insns_flags = glue(POWERPC_INSNS_,_type), \
6150 .msr_mask = glue(POWERPC_MSRM_,_type), \
6151 .mmu_model = glue(POWERPC_MMU_,_type), \
6152 .excp_model = glue(POWERPC_EXCP_,_type), \
6153 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 6154 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 6155 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 6156 .init_proc = &glue(init_proc_,_type), \
2f462816 6157 .check_pow = &glue(check_pow_,_type), \
a750fc0b 6158 }
80d11f44
JM		 6159#define POWERPC_DEF(_name, _pvr, _type) \
6160POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 6161
ee4e83ed 6162static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 6163 /* Embedded PowerPC */
6164 /* PowerPC 401 family */
2662a059 6165 /* Generic PowerPC 401 */
80d11f44 6166 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 6167 /* PowerPC 401 cores */
2662a059 6168 /* PowerPC 401A1 */
80d11f44 6169 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 6170 /* PowerPC 401B2 */
80d11f44 6171 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 6172#if defined (TODO)
a750fc0b 6173 /* PowerPC 401B3 */
80d11f44 6174 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 6175#endif
6176 /* PowerPC 401C2 */
80d11f44 6177 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 6178 /* PowerPC 401D2 */
80d11f44 6179 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 6180 /* PowerPC 401E2 */
80d11f44 6181 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 6182 /* PowerPC 401F2 */
80d11f44 6183 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 6184 /* PowerPC 401G2 */
6185 /* XXX: to be checked */
80d11f44 6186 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 6187 /* PowerPC 401 microcontrolers */
2662a059 6188#if defined (TODO)
a750fc0b 6189 /* PowerPC 401GF */
80d11f44 6190 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 6191#endif
a750fc0b 6192 /* IOP480 (401 microcontroler) */
80d11f44 6193 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 6194 /* IBM Processor for Network Resources */
80d11f44 6195 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 6196#if defined (TODO)
80d11f44 6197 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 6198#endif
a750fc0b
JM		 6199 /* PowerPC 403 family */
6200 /* Generic PowerPC 403 */
80d11f44 6201 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 6202 /* PowerPC 403 microcontrolers */
6203 /* PowerPC 403 GA */
80d11f44 6204 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 6205 /* PowerPC 403 GB */
80d11f44 6206 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 6207 /* PowerPC 403 GC */
80d11f44 6208 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 6209 /* PowerPC 403 GCX */
80d11f44 6210 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 6211#if defined (TODO)
a750fc0b 6212 /* PowerPC 403 GP */
80d11f44 6213 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 6214#endif
a750fc0b
JM		 6215 /* PowerPC 405 family */
6216 /* Generic PowerPC 405 */
80d11f44 6217 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 6218 /* PowerPC 405 cores */
2662a059 6219#if defined (TODO)
a750fc0b 6220 /* PowerPC 405 A3 */
80d11f44 6221 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 6222#endif
3a607854 6223#if defined (TODO)
a750fc0b 6224 /* PowerPC 405 A4 */
80d11f44 6225 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 6226#endif
3a607854 6227#if defined (TODO)
a750fc0b 6228 /* PowerPC 405 B3 */
80d11f44 6229 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 6230#endif
6231#if defined (TODO)
a750fc0b 6232 /* PowerPC 405 B4 */
80d11f44 6233 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 6234#endif
6235#if defined (TODO)
6236 /* PowerPC 405 C3 */
80d11f44 6237 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 6238#endif
6239#if defined (TODO)
6240 /* PowerPC 405 C4 */
80d11f44 6241 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 6242#endif
6243 /* PowerPC 405 D2 */
80d11f44 6244 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 6245#if defined (TODO)
6246 /* PowerPC 405 D3 */
80d11f44 6247 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 6248#endif
6249 /* PowerPC 405 D4 */
80d11f44 6250 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 6251#if defined (TODO)
6252 /* PowerPC 405 D5 */
80d11f44 6253 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 6254#endif
6255#if defined (TODO)
6256 /* PowerPC 405 E4 */
80d11f44 6257 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 6258#endif
6259#if defined (TODO)
6260 /* PowerPC 405 F4 */
80d11f44 6261 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 6262#endif
6263#if defined (TODO)
6264 /* PowerPC 405 F5 */
80d11f44 6265 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 6266#endif
6267#if defined (TODO)
6268 /* PowerPC 405 F6 */
80d11f44 6269 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 6270#endif
6271 /* PowerPC 405 microcontrolers */
6272 /* PowerPC 405 CR */
80d11f44 6273 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 6274 /* PowerPC 405 CRa */
80d11f44 6275 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 6276 /* PowerPC 405 CRb */
80d11f44 6277 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 6278 /* PowerPC 405 CRc */
80d11f44 6279 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 6280 /* PowerPC 405 EP */
80d11f44 6281 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 6282#if defined(TODO)
6283 /* PowerPC 405 EXr */
80d11f44 6284 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 6285#endif
6286 /* PowerPC 405 EZ */
80d11f44 6287 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 6288#if defined(TODO)
6289 /* PowerPC 405 FX */
80d11f44 6290 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 6291#endif
6292 /* PowerPC 405 GP */
80d11f44 6293 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 6294 /* PowerPC 405 GPa */
80d11f44 6295 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 6296 /* PowerPC 405 GPb */
80d11f44 6297 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 6298 /* PowerPC 405 GPc */
80d11f44 6299 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 6300 /* PowerPC 405 GPd */
80d11f44 6301 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 6302 /* PowerPC 405 GPe */
80d11f44 6303 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 6304 /* PowerPC 405 GPR */
80d11f44 6305 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 6306#if defined(TODO)
6307 /* PowerPC 405 H */
80d11f44 6308 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 6309#endif
6310#if defined(TODO)
6311 /* PowerPC 405 L */
80d11f44 6312 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 6313#endif
6314 /* PowerPC 405 LP */
80d11f44 6315 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 6316#if defined(TODO)
6317 /* PowerPC 405 PM */
80d11f44 6318 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 6319#endif
6320#if defined(TODO)
6321 /* PowerPC 405 PS */
80d11f44 6322 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 6323#endif
6324#if defined(TODO)
6325 /* PowerPC 405 S */
80d11f44 6326 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 6327#endif
6328 /* Npe405 H */
80d11f44 6329 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 6330 /* Npe405 H2 */
80d11f44 6331 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 6332 /* Npe405 L */
80d11f44 6333 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 6334 /* Npe4GS3 */
80d11f44 6335 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 6336#if defined (TODO)
80d11f44 6337 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 6338#endif
6339#if defined (TODO)
80d11f44 6340 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 6341#endif
6342#if defined (TODO)
6343 /* PowerPC LC77700 (Sanyo) */
80d11f44 6344 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 6345#endif
6346 /* PowerPC 401/403/405 based set-top-box microcontrolers */
6347#if defined (TODO)
6348 /* STB010000 */
80d11f44 6349 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 6350#endif
6351#if defined (TODO)
6352 /* STB01010 */
80d11f44 6353 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 6354#endif
6355#if defined (TODO)
6356 /* STB0210 */
80d11f44 6357 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 6358#endif
6359 /* STB03xx */
80d11f44 6360 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 6361#if defined (TODO)
6362 /* STB043x */
80d11f44 6363 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 6364#endif
6365#if defined (TODO)
6366 /* STB045x */
80d11f44 6367 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 6368#endif
6369 /* STB04xx */
80d11f44 6370 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 6371 /* STB25xx */
80d11f44 6372 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 6373#if defined (TODO)
6374 /* STB130 */
80d11f44 6375 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 6376#endif
6377 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 6378 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
6379 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
6380 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
6381 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 6382#if defined (TODO)
6383 /* Zarlink ZL10310 */
80d11f44 6384 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 6385#endif
6386#if defined (TODO)
6387 /* Zarlink ZL10311 */
80d11f44 6388 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 6389#endif
6390#if defined (TODO)
6391 /* Zarlink ZL10320 */
80d11f44 6392 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 6393#endif
6394#if defined (TODO)
6395 /* Zarlink ZL10321 */
80d11f44 6396 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 6397#endif
6398 /* PowerPC 440 family */
80d11f44 6399#if defined(TODO_USER_ONLY)
a750fc0b 6400 /* Generic PowerPC 440 */
80d11f44
JM		 6401 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
6402#endif
a750fc0b
JM		 6403 /* PowerPC 440 cores */
6404#if defined (TODO)
6405 /* PowerPC 440 A4 */
80d11f44 6406 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b
JM		 6407#endif
6408#if defined (TODO)
6409 /* PowerPC 440 A5 */
80d11f44 6410 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 6411#endif
6412#if defined (TODO)
6413 /* PowerPC 440 B4 */
80d11f44 6414 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 6415#endif
6416#if defined (TODO)
6417 /* PowerPC 440 G4 */
80d11f44 6418 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 6419#endif
6420#if defined (TODO)
6421 /* PowerPC 440 F5 */
80d11f44 6422 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 6423#endif
6424#if defined (TODO)
6425 /* PowerPC 440 G5 */
80d11f44 6426 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 6427#endif
6428#if defined (TODO)
6429 /* PowerPC 440H4 */
80d11f44 6430 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 6431#endif
6432#if defined (TODO)
6433 /* PowerPC 440H6 */
80d11f44 6434 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 6435#endif
6436 /* PowerPC 440 microcontrolers */
80d11f44 6437#if defined(TODO_USER_ONLY)
a750fc0b 6438 /* PowerPC 440 EP */
80d11f44
JM		 6439 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
6440#endif
6441#if defined(TODO_USER_ONLY)
a750fc0b 6442 /* PowerPC 440 EPa */
80d11f44
JM		 6443 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
6444#endif
6445#if defined(TODO_USER_ONLY)
a750fc0b 6446 /* PowerPC 440 EPb */
80d11f44
JM		 6447 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
6448#endif
6449#if defined(TODO_USER_ONLY)
a750fc0b 6450 /* PowerPC 440 EPX */
80d11f44
JM		 6451 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
6452#endif
6453#if defined(TODO_USER_ONLY)
a750fc0b 6454 /* PowerPC 440 GP */
80d11f44
JM		 6455 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
6456#endif
6457#if defined(TODO_USER_ONLY)
a750fc0b 6458 /* PowerPC 440 GPb */
80d11f44
JM		 6459 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
6460#endif
6461#if defined(TODO_USER_ONLY)
a750fc0b 6462 /* PowerPC 440 GPc */
80d11f44
JM		 6463 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
6464#endif
6465#if defined(TODO_USER_ONLY)
a750fc0b 6466 /* PowerPC 440 GR */
80d11f44
JM		 6467 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
6468#endif
6469#if defined(TODO_USER_ONLY)
a750fc0b 6470 /* PowerPC 440 GRa */
80d11f44
JM		 6471 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
6472#endif
6473#if defined(TODO_USER_ONLY)
a750fc0b 6474 /* PowerPC 440 GRX */
80d11f44
JM		 6475 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
6476#endif
6477#if defined(TODO_USER_ONLY)
a750fc0b 6478 /* PowerPC 440 GX */
80d11f44
JM		 6479 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
6480#endif
6481#if defined(TODO_USER_ONLY)
a750fc0b 6482 /* PowerPC 440 GXa */
80d11f44
JM		 6483 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
6484#endif
6485#if defined(TODO_USER_ONLY)
a750fc0b 6486 /* PowerPC 440 GXb */
80d11f44
JM		 6487 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
6488#endif
6489#if defined(TODO_USER_ONLY)
a750fc0b 6490 /* PowerPC 440 GXc */
80d11f44
JM		 6491 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
6492#endif
6493#if defined(TODO_USER_ONLY)
a750fc0b 6494 /* PowerPC 440 GXf */
80d11f44
JM		 6495 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
6496#endif
a750fc0b
JM		 6497#if defined(TODO)
6498 /* PowerPC 440 S */
80d11f44 6499 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 6500#endif
80d11f44 6501#if defined(TODO_USER_ONLY)
a750fc0b 6502 /* PowerPC 440 SP */
80d11f44
JM		 6503 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
6504#endif
6505#if defined(TODO_USER_ONLY)
a750fc0b 6506 /* PowerPC 440 SP2 */
80d11f44
JM		 6507 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
6508#endif
6509#if defined(TODO_USER_ONLY)
a750fc0b 6510 /* PowerPC 440 SPE */
80d11f44
JM		 6511 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
6512#endif
a750fc0b
JM		 6513 /* PowerPC 460 family */
6514#if defined (TODO)
6515 /* Generic PowerPC 464 */
80d11f44 6516 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 6517#endif
6518 /* PowerPC 464 microcontrolers */
6519#if defined (TODO)
6520 /* PowerPC 464H90 */
80d11f44 6521 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 6522#endif
6523#if defined (TODO)
6524 /* PowerPC 464H90F */
80d11f44 6525 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 6526#endif
6527 /* Freescale embedded PowerPC cores */
80d11f44
JM		 6528 /* MPC5xx family (aka RCPU) */
6529#if defined(TODO_USER_ONLY)
6530 /* Generic MPC5xx core */
6531 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
6532#endif
6533#if defined(TODO_USER_ONLY)
6534 /* Codename for MPC5xx core */
6535 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
6536#endif
6537 /* MPC5xx microcontrollers */
6538#if defined(TODO_USER_ONLY)
6539 /* MGT560 */
6540 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
6541#endif
6542#if defined(TODO_USER_ONLY)
6543 /* MPC509 */
6544 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
6545#endif
6546#if defined(TODO_USER_ONLY)
6547 /* MPC533 */
6548 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
6549#endif
6550#if defined(TODO_USER_ONLY)
6551 /* MPC534 */
6552 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
6553#endif
6554#if defined(TODO_USER_ONLY)
6555 /* MPC555 */
6556 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
6557#endif
6558#if defined(TODO_USER_ONLY)
6559 /* MPC556 */
6560 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
6561#endif
6562#if defined(TODO_USER_ONLY)
6563 /* MPC560 */
6564 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
6565#endif
6566#if defined(TODO_USER_ONLY)
6567 /* MPC561 */
6568 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
6569#endif
6570#if defined(TODO_USER_ONLY)
6571 /* MPC562 */
6572 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
6573#endif
6574#if defined(TODO_USER_ONLY)
6575 /* MPC563 */
6576 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
6577#endif
6578#if defined(TODO_USER_ONLY)
6579 /* MPC564 */
6580 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
6581#endif
6582#if defined(TODO_USER_ONLY)
6583 /* MPC565 */
6584 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
6585#endif
6586#if defined(TODO_USER_ONLY)
6587 /* MPC566 */
6588 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
6589#endif
6590 /* MPC8xx family (aka PowerQUICC) */
6591#if defined(TODO_USER_ONLY)
6592 /* Generic MPC8xx core */
6593 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
6594#endif
6595#if defined(TODO_USER_ONLY)
6596 /* Codename for MPC8xx core */
6597 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
6598#endif
6599 /* MPC8xx microcontrollers */
6600#if defined(TODO_USER_ONLY)
6601 /* MGT823 */
6602 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
6603#endif
6604#if defined(TODO_USER_ONLY)
6605 /* MPC821 */
6606 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
6607#endif
6608#if defined(TODO_USER_ONLY)
6609 /* MPC823 */
6610 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
6611#endif
6612#if defined(TODO_USER_ONLY)
6613 /* MPC850 */
6614 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
6615#endif
6616#if defined(TODO_USER_ONLY)
6617 /* MPC852T */
6618 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
6619#endif
6620#if defined(TODO_USER_ONLY)
6621 /* MPC855T */
6622 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
6623#endif
6624#if defined(TODO_USER_ONLY)
6625 /* MPC857 */
6626 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
6627#endif
6628#if defined(TODO_USER_ONLY)
6629 /* MPC859 */
6630 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
6631#endif
6632#if defined(TODO_USER_ONLY)
6633 /* MPC860 */
6634 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
6635#endif
6636#if defined(TODO_USER_ONLY)
6637 /* MPC862 */
6638 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
6639#endif
6640#if defined(TODO_USER_ONLY)
6641 /* MPC866 */
6642 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
6643#endif
6644#if defined(TODO_USER_ONLY)
6645 /* MPC870 */
6646 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
6647#endif
6648#if defined(TODO_USER_ONLY)
6649 /* MPC875 */
6650 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
6651#endif
6652#if defined(TODO_USER_ONLY)
6653 /* MPC880 */
6654 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
6655#endif
6656#if defined(TODO_USER_ONLY)
6657 /* MPC885 */
6658 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
6659#endif
6660 /* MPC82xx family (aka PowerQUICC-II) */
6661 /* Generic MPC52xx core */
6662 POWERPC_DEF_SVR("MPC52xx",
6663 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
6664 /* Generic MPC82xx core */
6665 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
6666 /* Codename for MPC82xx */
6667 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
6668 /* PowerPC G2 core */
6669 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
6670 /* PowerPC G2 H4 core */
6671 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
6672 /* PowerPC G2 GP core */
6673 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
6674 /* PowerPC G2 LS core */
6675 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
6676 /* PowerPC G2 HiP3 core */
6677 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
6678 /* PowerPC G2 HiP4 core */
6679 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
6680 /* PowerPC MPC603 core */
6681 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
6682 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
6683 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
6684 /* PowerPC G2LE GP core */
6685 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
6686 /* PowerPC G2LE LS core */
6687 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
6688 /* PowerPC G2LE GP1 core */
6689 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
6690 /* PowerPC G2LE GP3 core */
6691 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
6692 /* PowerPC MPC603 microcontrollers */
6693 /* MPC8240 */
6694 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
6695 /* PowerPC G2 microcontrollers */
6696#if 0
6697 /* MPC5121 */
6698 POWERPC_DEF_SVR("MPC5121",
6699 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
6700#endif
6701 /* MPC5200 */
6702 POWERPC_DEF_SVR("MPC5200",
6703 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
6704 /* MPC5200 v1.0 */
6705 POWERPC_DEF_SVR("MPC5200_v10",
6706 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
6707 /* MPC5200 v1.1 */
6708 POWERPC_DEF_SVR("MPC5200_v11",
6709 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
6710 /* MPC5200 v1.2 */
6711 POWERPC_DEF_SVR("MPC5200_v12",
6712 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
6713 /* MPC5200B */
6714 POWERPC_DEF_SVR("MPC5200B",
6715 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
6716 /* MPC5200B v2.0 */
6717 POWERPC_DEF_SVR("MPC5200B_v20",
6718 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
6719 /* MPC5200B v2.1 */
6720 POWERPC_DEF_SVR("MPC5200B_v21",
6721 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
6722 /* MPC8241 */
6723 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
6724 /* MPC8245 */
6725 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
6726 /* MPC8247 */
6727 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
6728 /* MPC8248 */
6729 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
6730 /* MPC8250 */
6731 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
6732 /* MPC8250 HiP3 */
6733 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
6734 /* MPC8250 HiP4 */
6735 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
6736 /* MPC8255 */
6737 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
6738 /* MPC8255 HiP3 */
6739 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
6740 /* MPC8255 HiP4 */
6741 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
6742 /* MPC8260 */
6743 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
6744 /* MPC8260 HiP3 */
6745 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
6746 /* MPC8260 HiP4 */
6747 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
6748 /* MPC8264 */
6749 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
6750 /* MPC8264 HiP3 */
6751 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
6752 /* MPC8264 HiP4 */
6753 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
6754 /* MPC8265 */
6755 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
6756 /* MPC8265 HiP3 */
6757 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
6758 /* MPC8265 HiP4 */
6759 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
6760 /* MPC8266 */
6761 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
6762 /* MPC8266 HiP3 */
6763 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
6764 /* MPC8266 HiP4 */
6765 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
6766 /* MPC8270 */
6767 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
6768 /* MPC8271 */
6769 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
6770 /* MPC8272 */
6771 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
6772 /* MPC8275 */
6773 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
6774 /* MPC8280 */
6775 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 6776 /* e200 family */
a750fc0b 6777 /* Generic PowerPC e200 core */
80d11f44
JM		 6778 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
6779 /* Generic MPC55xx core */
6780#if defined (TODO)
6781 POWERPC_DEF_SVR("MPC55xx",
6782 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 6783#endif
6784#if defined (TODO)
80d11f44
JM		 6785 /* PowerPC e200z0 core */
6786 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 6787#endif
6788#if defined (TODO)
80d11f44
JM		 6789 /* PowerPC e200z1 core */
6790 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
6791#endif
6792#if defined (TODO)
6793 /* PowerPC e200z3 core */
6794 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
6795#endif
6796 /* PowerPC e200z5 core */
6797 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 6798 /* PowerPC e200z6 core */
80d11f44
JM		 6799 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
6800 /* PowerPC e200 microcontrollers */
6801#if defined (TODO)
6802 /* MPC5514E */
6803 POWERPC_DEF_SVR("MPC5514E",
6804 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 6805#endif
a750fc0b 6806#if defined (TODO)
80d11f44
JM		 6807 /* MPC5514E v0 */
6808 POWERPC_DEF_SVR("MPC5514E_v0",
6809 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 6810#endif
6811#if defined (TODO)
80d11f44
JM		 6812 /* MPC5514E v1 */
6813 POWERPC_DEF_SVR("MPC5514E_v1",
6814 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 6815#endif
6816#if defined (TODO)
80d11f44
JM		 6817 /* MPC5514G */
6818 POWERPC_DEF_SVR("MPC5514G",
6819 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 6820#endif
6821#if defined (TODO)
80d11f44
JM		 6822 /* MPC5514G v0 */
6823 POWERPC_DEF_SVR("MPC5514G_v0",
6824 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 6825#endif
a750fc0b 6826#if defined (TODO)
80d11f44
JM		 6827 /* MPC5514G v1 */
6828 POWERPC_DEF_SVR("MPC5514G_v1",
6829 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 6830#endif
6831#if defined (TODO)
80d11f44
JM		 6832 /* MPC5515S */
6833 POWERPC_DEF_SVR("MPC5515S",
6834 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 6835#endif
6836#if defined (TODO)
80d11f44
JM		 6837 /* MPC5516E */
6838 POWERPC_DEF_SVR("MPC5516E",
6839 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 6840#endif
6841#if defined (TODO)
80d11f44
JM		 6842 /* MPC5516E v0 */
6843 POWERPC_DEF_SVR("MPC5516E_v0",
6844 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 6845#endif
6846#if defined (TODO)
80d11f44
JM		 6847 /* MPC5516E v1 */
6848 POWERPC_DEF_SVR("MPC5516E_v1",
6849 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 6850#endif
a750fc0b 6851#if defined (TODO)
80d11f44
JM		 6852 /* MPC5516G */
6853 POWERPC_DEF_SVR("MPC5516G",
6854 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 6855#endif
a750fc0b 6856#if defined (TODO)
80d11f44
JM		 6857 /* MPC5516G v0 */
6858 POWERPC_DEF_SVR("MPC5516G_v0",
6859 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 6860#endif
a750fc0b 6861#if defined (TODO)
80d11f44
JM		 6862 /* MPC5516G v1 */
6863 POWERPC_DEF_SVR("MPC5516G_v1",
6864 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 6865#endif
a750fc0b 6866#if defined (TODO)
80d11f44
JM		 6867 /* MPC5516S */
6868 POWERPC_DEF_SVR("MPC5516S",
6869 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 6870#endif
6871#if defined (TODO)
80d11f44
JM		 6872 /* MPC5533 */
6873 POWERPC_DEF_SVR("MPC5533",
6874 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 6875#endif
6876#if defined (TODO)
80d11f44
JM		 6877 /* MPC5534 */
6878 POWERPC_DEF_SVR("MPC5534",
6879 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 6880#endif
80d11f44
JM		 6881#if defined (TODO)
6882 /* MPC5553 */
6883 POWERPC_DEF_SVR("MPC5553",
6884 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
6885#endif
6886#if defined (TODO)
6887 /* MPC5554 */
6888 POWERPC_DEF_SVR("MPC5554",
6889 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
6890#endif
6891#if defined (TODO)
6892 /* MPC5561 */
6893 POWERPC_DEF_SVR("MPC5561",
6894 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
6895#endif
6896#if defined (TODO)
6897 /* MPC5565 */
6898 POWERPC_DEF_SVR("MPC5565",
6899 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
6900#endif
6901#if defined (TODO)
6902 /* MPC5566 */
6903 POWERPC_DEF_SVR("MPC5566",
6904 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
6905#endif
6906#if defined (TODO)
6907 /* MPC5567 */
6908 POWERPC_DEF_SVR("MPC5567",
6909 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
6910#endif
6911 /* e300 family */
6912 /* Generic PowerPC e300 core */
6913 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
6914 /* PowerPC e300c1 core */
6915 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
6916 /* PowerPC e300c2 core */
6917 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
6918 /* PowerPC e300c3 core */
6919 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
6920 /* PowerPC e300c4 core */
6921 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
6922 /* PowerPC e300 microcontrollers */
6923#if defined (TODO)
6924 /* MPC8313 */
6925 POWERPC_DEF_SVR("MPC8313",
6926 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
6927#endif
6928#if defined (TODO)
6929 /* MPC8313E */
6930 POWERPC_DEF_SVR("MPC8313E",
6931 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
6932#endif
6933#if defined (TODO)
6934 /* MPC8314 */
6935 POWERPC_DEF_SVR("MPC8314",
6936 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
6937#endif
6938#if defined (TODO)
6939 /* MPC8314E */
6940 POWERPC_DEF_SVR("MPC8314E",
6941 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
6942#endif
6943#if defined (TODO)
6944 /* MPC8315 */
6945 POWERPC_DEF_SVR("MPC8315",
6946 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
6947#endif
6948#if defined (TODO)
6949 /* MPC8315E */
6950 POWERPC_DEF_SVR("MPC8315E",
6951 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
6952#endif
6953#if defined (TODO)
6954 /* MPC8321 */
6955 POWERPC_DEF_SVR("MPC8321",
6956 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
6957#endif
6958#if defined (TODO)
6959 /* MPC8321E */
6960 POWERPC_DEF_SVR("MPC8321E",
6961 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
6962#endif
6963#if defined (TODO)
6964 /* MPC8323 */
6965 POWERPC_DEF_SVR("MPC8323",
6966 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
6967#endif
6968#if defined (TODO)
6969 /* MPC8323E */
6970 POWERPC_DEF_SVR("MPC8323E",
6971 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
6972#endif
6973 /* MPC8343A */
6974 POWERPC_DEF_SVR("MPC8343A",
6975 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
6976 /* MPC8343EA */
6977 POWERPC_DEF_SVR("MPC8343EA",
6978 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
6979 /* MPC8347A */
6980 POWERPC_DEF_SVR("MPC8347A",
6981 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
6982 /* MPC8347AT */
6983 POWERPC_DEF_SVR("MPC8347AT",
6984 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
6985 /* MPC8347AP */
6986 POWERPC_DEF_SVR("MPC8347AP",
6987 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
6988 /* MPC8347EA */
6989 POWERPC_DEF_SVR("MPC8347EA",
6990 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
6991 /* MPC8347EAT */
6992 POWERPC_DEF_SVR("MPC8347EAT",
6993 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
6994 /* MPC8343EAP */
6995 POWERPC_DEF_SVR("MPC8347EAP",
6996 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
6997 /* MPC8349 */
6998 POWERPC_DEF_SVR("MPC8349",
6999 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
7000 /* MPC8349A */
7001 POWERPC_DEF_SVR("MPC8349A",
7002 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
7003 /* MPC8349E */
7004 POWERPC_DEF_SVR("MPC8349E",
7005 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
7006 /* MPC8349EA */
7007 POWERPC_DEF_SVR("MPC8349EA",
7008 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
7009#if defined (TODO)
7010 /* MPC8358E */
7011 POWERPC_DEF_SVR("MPC8358E",
7012 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
7013#endif
7014#if defined (TODO)
7015 /* MPC8360E */
7016 POWERPC_DEF_SVR("MPC8360E",
7017 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
7018#endif
7019 /* MPC8377 */
7020 POWERPC_DEF_SVR("MPC8377",
7021 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
7022 /* MPC8377E */
7023 POWERPC_DEF_SVR("MPC8377E",
7024 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
7025 /* MPC8378 */
7026 POWERPC_DEF_SVR("MPC8378",
7027 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
7028 /* MPC8378E */
7029 POWERPC_DEF_SVR("MPC8378E",
7030 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
7031 /* MPC8379 */
7032 POWERPC_DEF_SVR("MPC8379",
7033 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
7034 /* MPC8379E */
7035 POWERPC_DEF_SVR("MPC8379E",
7036 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
7037 /* e500 family */
7038 /* PowerPC e500 core */
7039 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
7040 /* PowerPC e500 v1.0 core */
7041 POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
7042 /* PowerPC e500 v2.0 core */
7043 POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
7044 /* PowerPC e500v2 core */
7045 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
7046 /* PowerPC e500v2 v1.0 core */
7047 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
7048 /* PowerPC e500v2 v2.0 core */
7049 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
7050 /* PowerPC e500v2 v2.1 core */
7051 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
7052 /* PowerPC e500v2 v2.2 core */
7053 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
7054 /* PowerPC e500v2 v3.0 core */
7055 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
7056 /* PowerPC e500 microcontrollers */
7057 /* MPC8533 */
7058 POWERPC_DEF_SVR("MPC8533",
7059 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
7060 /* MPC8533 v1.0 */
7061 POWERPC_DEF_SVR("MPC8533_v10",
7062 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
7063 /* MPC8533 v1.1 */
7064 POWERPC_DEF_SVR("MPC8533_v11",
7065 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
7066 /* MPC8533E */
7067 POWERPC_DEF_SVR("MPC8533E",
7068 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
7069 /* MPC8533E v1.0 */
7070 POWERPC_DEF_SVR("MPC8533E_v10",
7071 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
7072 POWERPC_DEF_SVR("MPC8533E_v11",
7073 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
7074 /* MPC8540 */
7075 POWERPC_DEF_SVR("MPC8540",
7076 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
7077 /* MPC8540 v1.0 */
7078 POWERPC_DEF_SVR("MPC8540_v10",
7079 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
7080 /* MPC8540 v2.0 */
7081 POWERPC_DEF_SVR("MPC8540_v20",
7082 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
7083 /* MPC8540 v2.1 */
7084 POWERPC_DEF_SVR("MPC8540_v21",
7085 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
7086 /* MPC8541 */
7087 POWERPC_DEF_SVR("MPC8541",
7088 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
7089 /* MPC8541 v1.0 */
7090 POWERPC_DEF_SVR("MPC8541_v10",
7091 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
7092 /* MPC8541 v1.1 */
7093 POWERPC_DEF_SVR("MPC8541_v11",
7094 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
7095 /* MPC8541E */
7096 POWERPC_DEF_SVR("MPC8541E",
7097 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
7098 /* MPC8541E v1.0 */
7099 POWERPC_DEF_SVR("MPC8541E_v10",
7100 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
7101 /* MPC8541E v1.1 */
7102 POWERPC_DEF_SVR("MPC8541E_v11",
7103 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
7104 /* MPC8543 */
7105 POWERPC_DEF_SVR("MPC8543",
7106 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
7107 /* MPC8543 v1.0 */
7108 POWERPC_DEF_SVR("MPC8543_v10",
7109 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
7110 /* MPC8543 v1.1 */
7111 POWERPC_DEF_SVR("MPC8543_v11",
7112 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
7113 /* MPC8543 v2.0 */
7114 POWERPC_DEF_SVR("MPC8543_v20",
7115 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
7116 /* MPC8543 v2.1 */
7117 POWERPC_DEF_SVR("MPC8543_v21",
7118 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
7119 /* MPC8543E */
7120 POWERPC_DEF_SVR("MPC8543E",
7121 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
7122 /* MPC8543E v1.0 */
7123 POWERPC_DEF_SVR("MPC8543E_v10",
7124 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
7125 /* MPC8543E v1.1 */
7126 POWERPC_DEF_SVR("MPC8543E_v11",
7127 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
7128 /* MPC8543E v2.0 */
7129 POWERPC_DEF_SVR("MPC8543E_v20",
7130 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
7131 /* MPC8543E v2.1 */
7132 POWERPC_DEF_SVR("MPC8543E_v21",
7133 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
7134 /* MPC8544 */
7135 POWERPC_DEF_SVR("MPC8544",
7136 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
7137 /* MPC8544 v1.0 */
7138 POWERPC_DEF_SVR("MPC8544_v10",
7139 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
7140 /* MPC8544 v1.1 */
7141 POWERPC_DEF_SVR("MPC8544_v11",
7142 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
7143 /* MPC8544E */
7144 POWERPC_DEF_SVR("MPC8544E",
7145 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
7146 /* MPC8544E v1.0 */
7147 POWERPC_DEF_SVR("MPC8544E_v10",
7148 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
7149 /* MPC8544E v1.1 */
7150 POWERPC_DEF_SVR("MPC8544E_v11",
7151 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
7152 /* MPC8545 */
7153 POWERPC_DEF_SVR("MPC8545",
7154 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
7155 /* MPC8545 v2.0 */
7156 POWERPC_DEF_SVR("MPC8545_v20",
7157 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
7158 /* MPC8545 v2.1 */
7159 POWERPC_DEF_SVR("MPC8545_v21",
7160 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
7161 /* MPC8545E */
7162 POWERPC_DEF_SVR("MPC8545E",
7163 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
7164 /* MPC8545E v2.0 */
7165 POWERPC_DEF_SVR("MPC8545E_v20",
7166 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
7167 /* MPC8545E v2.1 */
7168 POWERPC_DEF_SVR("MPC8545E_v21",
7169 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
7170 /* MPC8547E */
7171 POWERPC_DEF_SVR("MPC8547E",
7172 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
7173 /* MPC8547E v2.0 */
7174 POWERPC_DEF_SVR("MPC8547E_v20",
7175 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
7176 /* MPC8547E v2.1 */
7177 POWERPC_DEF_SVR("MPC8547E_v21",
7178 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
7179 /* MPC8548 */
7180 POWERPC_DEF_SVR("MPC8548",
7181 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
7182 /* MPC8548 v1.0 */
7183 POWERPC_DEF_SVR("MPC8548_v10",
7184 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
7185 /* MPC8548 v1.1 */
7186 POWERPC_DEF_SVR("MPC8548_v11",
7187 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
7188 /* MPC8548 v2.0 */
7189 POWERPC_DEF_SVR("MPC8548_v20",
7190 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
7191 /* MPC8548 v2.1 */
7192 POWERPC_DEF_SVR("MPC8548_v21",
7193 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
7194 /* MPC8548E */
7195 POWERPC_DEF_SVR("MPC8548E",
7196 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
7197 /* MPC8548E v1.0 */
7198 POWERPC_DEF_SVR("MPC8548E_v10",
7199 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
7200 /* MPC8548E v1.1 */
7201 POWERPC_DEF_SVR("MPC8548E_v11",
7202 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
7203 /* MPC8548E v2.0 */
7204 POWERPC_DEF_SVR("MPC8548E_v20",
7205 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
7206 /* MPC8548E v2.1 */
7207 POWERPC_DEF_SVR("MPC8548E_v21",
7208 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
7209 /* MPC8555 */
7210 POWERPC_DEF_SVR("MPC8555",
7211 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
7212 /* MPC8555 v1.0 */
7213 POWERPC_DEF_SVR("MPC8555_v10",
7214 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
7215 /* MPC8555 v1.1 */
7216 POWERPC_DEF_SVR("MPC8555_v11",
7217 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
7218 /* MPC8555E */
7219 POWERPC_DEF_SVR("MPC8555E",
7220 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
7221 /* MPC8555E v1.0 */
7222 POWERPC_DEF_SVR("MPC8555E_v10",
7223 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
7224 /* MPC8555E v1.1 */
7225 POWERPC_DEF_SVR("MPC8555E_v11",
7226 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
7227 /* MPC8560 */
7228 POWERPC_DEF_SVR("MPC8560",
7229 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
7230 /* MPC8560 v1.0 */
7231 POWERPC_DEF_SVR("MPC8560_v10",
7232 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
7233 /* MPC8560 v2.0 */
7234 POWERPC_DEF_SVR("MPC8560_v20",
7235 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
7236 /* MPC8560 v2.1 */
7237 POWERPC_DEF_SVR("MPC8560_v21",
7238 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
7239 /* MPC8567 */
7240 POWERPC_DEF_SVR("MPC8567",
7241 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
7242 /* MPC8567E */
7243 POWERPC_DEF_SVR("MPC8567E",
7244 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
7245 /* MPC8568 */
7246 POWERPC_DEF_SVR("MPC8568",
7247 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
7248 /* MPC8568E */
7249 POWERPC_DEF_SVR("MPC8568E",
7250 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
7251 /* MPC8572 */
7252 POWERPC_DEF_SVR("MPC8572",
7253 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
7254 /* MPC8572E */
7255 POWERPC_DEF_SVR("MPC8572E",
7256 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
7257 /* e600 family */
7258 /* PowerPC e600 core */
7259 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
7260 /* PowerPC e600 microcontrollers */
7261#if defined (TODO)
7262 /* MPC8610 */
7263 POWERPC_DEF_SVR("MPC8610",
7264 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
7265#endif
7266 /* MPC8641 */
7267 POWERPC_DEF_SVR("MPC8641",
7268 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
7269 /* MPC8641D */
7270 POWERPC_DEF_SVR("MPC8641D",
7271 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 7272 /* 32 bits "classic" PowerPC */
7273 /* PowerPC 6xx family */
7274 /* PowerPC 601 */
80d11f44 7275 POWERPC_DEF("601", CPU_POWERPC_601, 601),
c3e36823 7276 /* PowerPC 601v0 */
80d11f44 7277 POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
c3e36823 7278 /* PowerPC 601v1 */
80d11f44 7279 POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
a750fc0b 7280 /* PowerPC 601v2 */
80d11f44 7281 POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
a750fc0b 7282 /* PowerPC 602 */
80d11f44 7283 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 7284 /* PowerPC 603 */
80d11f44 7285 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 7286 /* Code name for PowerPC 603 */
80d11f44 7287 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
a750fc0b 7288 /* PowerPC 603e */
80d11f44 7289 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 7290 /* Code name for PowerPC 603e */
80d11f44 7291 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 7292 /* PowerPC 603e v1.1 */
80d11f44 7293 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 7294 /* PowerPC 603e v1.2 */
80d11f44 7295 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 7296 /* PowerPC 603e v1.3 */
80d11f44 7297 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 7298 /* PowerPC 603e v1.4 */
80d11f44 7299 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 7300 /* PowerPC 603e v2.2 */
80d11f44 7301 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 7302 /* PowerPC 603e v3 */
80d11f44 7303 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 7304 /* PowerPC 603e v4 */
80d11f44 7305 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 7306 /* PowerPC 603e v4.1 */
80d11f44 7307 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
a750fc0b 7308 /* PowerPC 603e */
80d11f44 7309 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 7310 /* PowerPC 603e7t */
80d11f44 7311 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 7312 /* PowerPC 603e7v */
80d11f44 7313 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 7314 /* Code name for PowerPC 603ev */
80d11f44 7315 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 7316 /* PowerPC 603e7v1 */
80d11f44 7317 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 7318 /* PowerPC 603e7v2 */
80d11f44 7319 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
a750fc0b
JM		 7320 /* PowerPC 603p */
7321 /* to be checked */
80d11f44 7322 POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
a750fc0b 7323 /* PowerPC 603r */
80d11f44 7324 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 7325 /* Code name for PowerPC 603r */
80d11f44 7326 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 7327 /* PowerPC 604 */
80d11f44 7328 POWERPC_DEF("604", CPU_POWERPC_604, 604),
a750fc0b 7329 /* PowerPC 604e */
ee4e83ed 7330 /* XXX: code names "Sirocco" "Mach 5" */
80d11f44 7331 POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
a750fc0b 7332 /* PowerPC 604e v1.0 */
80d11f44 7333 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604),
a750fc0b 7334 /* PowerPC 604e v2.2 */
80d11f44 7335 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604),
a750fc0b 7336 /* PowerPC 604e v2.4 */
80d11f44 7337 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604),
a750fc0b 7338 /* PowerPC 604r */
80d11f44 7339 POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
a750fc0b
JM		 7340#if defined(TODO)
7341 /* PowerPC 604ev */
80d11f44 7342 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
a750fc0b
JM		 7343#endif
7344 /* PowerPC 7xx family */
7345 /* Generic PowerPC 740 (G3) */
80d11f44 7346 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
a750fc0b 7347 /* Generic PowerPC 750 (G3) */
80d11f44 7348 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
a750fc0b 7349 /* Code name for generic PowerPC 740/750 (G3) */
80d11f44 7350 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
ee4e83ed 7351 /* XXX: 750 codename "Typhoon" */
a750fc0b 7352 /* PowerPC 740/750 is also known as G3 */
80d11f44 7353 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
a750fc0b 7354 /* PowerPC 740 v2.0 (G3) */
80d11f44 7355 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0),
a750fc0b 7356 /* PowerPC 750 v2.0 (G3) */
80d11f44 7357 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0),
a750fc0b 7358 /* PowerPC 740 v2.1 (G3) */
80d11f44 7359 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0),
a750fc0b 7360 /* PowerPC 750 v2.1 (G3) */
80d11f44 7361 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0),
a750fc0b 7362 /* PowerPC 740 v2.2 (G3) */
80d11f44 7363 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0),
a750fc0b 7364 /* PowerPC 750 v2.2 (G3) */
80d11f44 7365 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0),
a750fc0b 7366 /* PowerPC 740 v3.0 (G3) */
80d11f44 7367 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0),
a750fc0b 7368 /* PowerPC 750 v3.0 (G3) */
80d11f44 7369 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0),
a750fc0b 7370 /* PowerPC 740 v3.1 (G3) */
80d11f44 7371 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0),
a750fc0b 7372 /* PowerPC 750 v3.1 (G3) */
80d11f44 7373 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0),
a750fc0b 7374 /* PowerPC 740E (G3) */
80d11f44 7375 POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
a750fc0b 7376 /* PowerPC 740P (G3) */
80d11f44 7377 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7378 /* PowerPC 750P (G3) */
80d11f44 7379 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7380 /* Code name for PowerPC 740P/750P (G3) */
80d11f44 7381 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7382 /* PowerPC 750CL (G3 embedded) */
80d11f44 7383 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
a750fc0b 7384 /* PowerPC 750CX (G3 embedded) */
80d11f44 7385 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
a750fc0b 7386 /* PowerPC 750CX v2.1 (G3 embedded) */
80d11f44 7387 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0),
a750fc0b 7388 /* PowerPC 750CX v2.2 (G3 embedded) */
80d11f44 7389 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0),
a750fc0b 7390 /* PowerPC 750CXe (G3 embedded) */
80d11f44 7391 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
a750fc0b 7392 /* PowerPC 750CXe v2.1 (G3 embedded) */
80d11f44 7393 POWERPC_DEF("750cxe_v21", CPU_POWERPC_750CXE_v21, 7x0),
a750fc0b 7394 /* PowerPC 750CXe v2.2 (G3 embedded) */
80d11f44 7395 POWERPC_DEF("750cxe_v22", CPU_POWERPC_750CXE_v22, 7x0),
a750fc0b 7396 /* PowerPC 750CXe v2.3 (G3 embedded) */
80d11f44 7397 POWERPC_DEF("750cxe_v23", CPU_POWERPC_750CXE_v23, 7x0),
a750fc0b 7398 /* PowerPC 750CXe v2.4 (G3 embedded) */
80d11f44 7399 POWERPC_DEF("750cxe_v24", CPU_POWERPC_750CXE_v24, 7x0),
a750fc0b 7400 /* PowerPC 750CXe v2.4b (G3 embedded) */
80d11f44 7401 POWERPC_DEF("750cxe_v24b", CPU_POWERPC_750CXE_v24b, 7x0),
a750fc0b 7402 /* PowerPC 750CXe v3.1 (G3 embedded) */
80d11f44 7403 POWERPC_DEF("750cxe_v31", CPU_POWERPC_750CXE_v31, 7x0),
a750fc0b 7404 /* PowerPC 750CXe v3.1b (G3 embedded) */
80d11f44 7405 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
a750fc0b 7406 /* PowerPC 750CXr (G3 embedded) */
80d11f44 7407 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
a750fc0b 7408 /* PowerPC 750E (G3) */
80d11f44 7409 POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
a750fc0b 7410 /* PowerPC 750FL (G3 embedded) */
80d11f44 7411 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 7412 /* PowerPC 750FX (G3 embedded) */
80d11f44 7413 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 7414 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 7415 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 7416 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 7417 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 7418 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 7419 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 7420 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 7421 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 7422 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 7423 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 7424 /* PowerPC 750GL (G3 embedded) */
80d11f44 7425 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
a750fc0b 7426 /* PowerPC 750GX (G3 embedded) */
80d11f44 7427 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
a750fc0b 7428 /* PowerPC 750GX v1.0 (G3 embedded) */
80d11f44 7429 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx),
a750fc0b 7430 /* PowerPC 750GX v1.1 (G3 embedded) */
80d11f44 7431 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx),
a750fc0b 7432 /* PowerPC 750GX v1.2 (G3 embedded) */
80d11f44 7433 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx),
a750fc0b 7434 /* PowerPC 750L (G3 embedded) */
80d11f44 7435 POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
a750fc0b 7436 /* Code name for PowerPC 750L (G3 embedded) */
80d11f44 7437 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
a750fc0b 7438 /* PowerPC 750L v2.2 (G3 embedded) */
80d11f44 7439 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0),
a750fc0b 7440 /* PowerPC 750L v3.0 (G3 embedded) */
80d11f44 7441 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0),
a750fc0b 7442 /* PowerPC 750L v3.2 (G3 embedded) */
80d11f44 7443 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0),
a750fc0b 7444 /* Generic PowerPC 745 */
80d11f44 7445 POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
a750fc0b 7446 /* Generic PowerPC 755 */
80d11f44 7447 POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
a750fc0b 7448 /* Code name for PowerPC 745/755 */
80d11f44 7449 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
a750fc0b 7450 /* PowerPC 745 v1.0 */
80d11f44 7451 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5),
a750fc0b 7452 /* PowerPC 755 v1.0 */
80d11f44 7453 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5),
a750fc0b 7454 /* PowerPC 745 v1.1 */
80d11f44 7455 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5),
a750fc0b 7456 /* PowerPC 755 v1.1 */
80d11f44 7457 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5),
a750fc0b 7458 /* PowerPC 745 v2.0 */
80d11f44 7459 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5),
a750fc0b 7460 /* PowerPC 755 v2.0 */
80d11f44 7461 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5),
a750fc0b 7462 /* PowerPC 745 v2.1 */
80d11f44 7463 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5),
a750fc0b 7464 /* PowerPC 755 v2.1 */
80d11f44 7465 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5),
a750fc0b 7466 /* PowerPC 745 v2.2 */
80d11f44 7467 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5),
a750fc0b 7468 /* PowerPC 755 v2.2 */
80d11f44 7469 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5),
a750fc0b 7470 /* PowerPC 745 v2.3 */
80d11f44 7471 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5),
a750fc0b 7472 /* PowerPC 755 v2.3 */
80d11f44 7473 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5),
a750fc0b 7474 /* PowerPC 745 v2.4 */
80d11f44 7475 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5),
a750fc0b 7476 /* PowerPC 755 v2.4 */
80d11f44 7477 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5),
a750fc0b 7478 /* PowerPC 745 v2.5 */
80d11f44 7479 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5),
a750fc0b 7480 /* PowerPC 755 v2.5 */
80d11f44 7481 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5),
a750fc0b 7482 /* PowerPC 745 v2.6 */
80d11f44 7483 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5),
a750fc0b 7484 /* PowerPC 755 v2.6 */
80d11f44 7485 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5),
a750fc0b 7486 /* PowerPC 745 v2.7 */
80d11f44 7487 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5),
a750fc0b 7488 /* PowerPC 755 v2.7 */
80d11f44 7489 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5),
a750fc0b 7490 /* PowerPC 745 v2.8 */
80d11f44 7491 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5),
a750fc0b 7492 /* PowerPC 755 v2.8 */
80d11f44 7493 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5),
a750fc0b
JM		 7494#if defined (TODO)
7495 /* PowerPC 745P (G3) */
80d11f44 7496 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
a750fc0b 7497 /* PowerPC 755P (G3) */
80d11f44 7498 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
a750fc0b
JM		 7499#endif
7500 /* PowerPC 74xx family */
7501 /* PowerPC 7400 (G4) */
80d11f44 7502 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 7503 /* Code name for PowerPC 7400 */
80d11f44 7504 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 7505 /* PowerPC 74xx is also well known as G4 */
80d11f44 7506 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 7507 /* PowerPC 7400 v1.0 (G4) */
80d11f44 7508 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 7509 /* PowerPC 7400 v1.1 (G4) */
80d11f44 7510 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 7511 /* PowerPC 7400 v2.0 (G4) */
80d11f44 7512 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
a750fc0b 7513 /* PowerPC 7400 v2.2 (G4) */
80d11f44 7514 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 7515 /* PowerPC 7400 v2.6 (G4) */
80d11f44 7516 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 7517 /* PowerPC 7400 v2.7 (G4) */
80d11f44 7518 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 7519 /* PowerPC 7400 v2.8 (G4) */
80d11f44 7520 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 7521 /* PowerPC 7400 v2.9 (G4) */
80d11f44 7522 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 7523 /* PowerPC 7410 (G4) */
80d11f44 7524 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 7525 /* Code name for PowerPC 7410 */
80d11f44 7526 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 7527 /* PowerPC 7410 v1.0 (G4) */
80d11f44 7528 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 7529 /* PowerPC 7410 v1.1 (G4) */
80d11f44 7530 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 7531 /* PowerPC 7410 v1.2 (G4) */
80d11f44 7532 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 7533 /* PowerPC 7410 v1.3 (G4) */
80d11f44 7534 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 7535 /* PowerPC 7410 v1.4 (G4) */
80d11f44 7536 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 7537 /* PowerPC 7448 (G4) */
80d11f44 7538 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 7539 /* PowerPC 7448 v1.0 (G4) */
80d11f44 7540 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 7541 /* PowerPC 7448 v1.1 (G4) */
80d11f44 7542 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 7543 /* PowerPC 7448 v2.0 (G4) */
80d11f44 7544 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 7545 /* PowerPC 7448 v2.1 (G4) */
80d11f44 7546 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 7547 /* PowerPC 7450 (G4) */
80d11f44 7548 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 7549 /* Code name for PowerPC 7450 */
80d11f44 7550 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 7551 /* PowerPC 7450 v1.0 (G4) */
80d11f44 7552 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 7553 /* PowerPC 7450 v1.1 (G4) */
80d11f44 7554 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 7555 /* PowerPC 7450 v1.2 (G4) */
80d11f44 7556 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 7557 /* PowerPC 7450 v2.0 (G4) */
80d11f44 7558 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 7559 /* PowerPC 7450 v2.1 (G4) */
80d11f44 7560 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 7561 /* PowerPC 7441 (G4) */
80d11f44 7562 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 7563 /* PowerPC 7451 (G4) */
80d11f44 7564 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
a750fc0b 7565 /* PowerPC 7441g (G4) */
80d11f44 7566 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
a750fc0b 7567 /* PowerPC 7451g (G4) */
80d11f44 7568 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
a750fc0b 7569 /* PowerPC 7445 (G4) */
80d11f44 7570 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 7571 /* PowerPC 7455 (G4) */
80d11f44 7572 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 7573 /* Code name for PowerPC 7445/7455 */
80d11f44 7574 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 7575 /* PowerPC 7445 v1.0 (G4) */
80d11f44 7576 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 7577 /* PowerPC 7455 v1.0 (G4) */
80d11f44 7578 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 7579 /* PowerPC 7445 v2.1 (G4) */
80d11f44 7580 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 7581 /* PowerPC 7455 v2.1 (G4) */
80d11f44 7582 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 7583 /* PowerPC 7445 v3.2 (G4) */
80d11f44 7584 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 7585 /* PowerPC 7455 v3.2 (G4) */
80d11f44 7586 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 7587 /* PowerPC 7445 v3.3 (G4) */
80d11f44 7588 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 7589 /* PowerPC 7455 v3.3 (G4) */
80d11f44 7590 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 7591 /* PowerPC 7445 v3.4 (G4) */
80d11f44 7592 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 7593 /* PowerPC 7455 v3.4 (G4) */
80d11f44 7594 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 7595 /* PowerPC 7447 (G4) */
80d11f44 7596 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 7597 /* PowerPC 7457 (G4) */
80d11f44 7598 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 7599 /* Code name for PowerPC 7447/7457 */
80d11f44 7600 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 7601 /* PowerPC 7447 v1.0 (G4) */
80d11f44 7602 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 7603 /* PowerPC 7457 v1.0 (G4) */
80d11f44 7604 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 7605 /* Code name for PowerPC 7447A/7457A */
80d11f44 7606 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 7607 /* PowerPC 7447 v1.1 (G4) */
80d11f44 7608 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 7609 /* PowerPC 7457 v1.1 (G4) */
80d11f44 7610 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 7611 /* PowerPC 7447 v1.2 (G4) */
80d11f44 7612 POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
a750fc0b 7613 /* PowerPC 7457 v1.2 (G4) */
80d11f44 7614 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
a750fc0b
JM		 7615 /* 64 bits PowerPC */
7616#if defined (TARGET_PPC64)
a750fc0b 7617 /* PowerPC 620 */
ee4e83ed 7618 /* XXX: code name "Trident" */
80d11f44 7619 POWERPC_DEF("620", CPU_POWERPC_620, 620),
3fc6c082 7620#if defined (TODO)
a750fc0b 7621 /* PowerPC 630 (POWER3) */
ee4e83ed 7622 /* XXX: code names: "Boxer" "Dino" */
80d11f44
JM		 7623 POWERPC_DEF("630", CPU_POWERPC_630, 630),
7624 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
a750fc0b 7625#endif
3a607854 7626#if defined (TODO)
a750fc0b 7627 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 7628 POWERPC_DEF("631", CPU_POWERPC_631, 631),
7629 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 7630#endif
7631#if defined (TODO)
a750fc0b 7632 /* POWER4 */
80d11f44 7633 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 7634#endif
3a607854 7635#if defined (TODO)
a750fc0b 7636 /* POWER4p */
80d11f44 7637 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 7638#endif
2662a059 7639#if defined (TODO)
a750fc0b 7640 /* POWER5 */
80d11f44 7641 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 7642 /* POWER5GR */
80d11f44 7643 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 7644#endif
3a607854 7645#if defined (TODO)
a750fc0b 7646 /* POWER5+ */
80d11f44 7647 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 7648 /* POWER5GS */
80d11f44 7649 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 7650#endif
2662a059 7651#if defined (TODO)
a750fc0b 7652 /* POWER6 */
80d11f44 7653 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 7654 /* POWER6 running in POWER5 mode */
80d11f44 7655 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 7656 /* POWER6A */
80d11f44 7657 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 7658#endif
a750fc0b 7659 /* PowerPC 970 */
80d11f44 7660 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 7661 /* PowerPC 970FX (G5) */
80d11f44 7662 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 7663 /* PowerPC 970FX v1.0 (G5) */
80d11f44 7664 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 7665 /* PowerPC 970FX v2.0 (G5) */
80d11f44 7666 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 7667 /* PowerPC 970FX v2.1 (G5) */
80d11f44 7668 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 7669 /* PowerPC 970FX v3.0 (G5) */
80d11f44 7670 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 7671 /* PowerPC 970FX v3.1 (G5) */
80d11f44 7672 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 7673 /* PowerPC 970GX (G5) */
80d11f44 7674 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 7675 /* PowerPC 970MP */
80d11f44 7676 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 7677 /* PowerPC 970MP v1.0 */
80d11f44 7678 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 7679 /* PowerPC 970MP v1.1 */
80d11f44 7680 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 7681#if defined (TODO)
a750fc0b 7682 /* PowerPC Cell */
80d11f44 7683 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 7684#endif
7685#if defined (TODO)
a750fc0b 7686 /* PowerPC Cell v1.0 */
80d11f44 7687 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 7688#endif
7689#if defined (TODO)
a750fc0b 7690 /* PowerPC Cell v2.0 */
80d11f44 7691 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 7692#endif
7693#if defined (TODO)
a750fc0b 7694 /* PowerPC Cell v3.0 */
80d11f44 7695 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 7696#endif
3a607854 7697#if defined (TODO)
a750fc0b 7698 /* PowerPC Cell v3.1 */
80d11f44 7699 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 7700#endif
7701#if defined (TODO)
a750fc0b 7702 /* PowerPC Cell v3.2 */
80d11f44 7703 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 7704#endif
7705#if defined (TODO)
a750fc0b
JM		 7706 /* RS64 (Apache/A35) */
7707 /* This one seems to support the whole POWER2 instruction set
7708 * and the PowerPC 64 one.
7709 */
7710 /* What about A10 & A30 ? */
80d11f44
JM		 7711 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
7712 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
7713 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 7714#endif
7715#if defined (TODO)
a750fc0b 7716 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 7717 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
7718 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
7719 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 7720#endif
7721#if defined (TODO)
a750fc0b 7722 /* RS64-III (Pulsar) */
80d11f44
JM		 7723 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
7724 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 7725#endif
7726#if defined (TODO)
a750fc0b 7727 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 7728 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
7729 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
7730 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
7731 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 7732#endif
a750fc0b
JM		 7733#endif /* defined (TARGET_PPC64) */
7734 /* POWER */
3fc6c082 7735#if defined (TODO)
a750fc0b 7736 /* Original POWER */
80d11f44
JM		 7737 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
7738 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
7739 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
7740 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
7741 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 7742#endif
7743#if defined (TODO)
a750fc0b 7744 /* POWER2 */
80d11f44
JM		 7745 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
7746 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
7747 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 7748#endif
7749 /* PA semi cores */
7750#if defined (TODO)
7751 /* PA PA6T */
80d11f44 7752 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 7753#endif
7754 /* Generic PowerPCs */
7755#if defined (TARGET_PPC64)
80d11f44 7756 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 7757#endif
80d11f44
JM		 7758 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
7759 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 7760 /* Fallback */
80d11f44 7761 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 7762};
7763
7764/*****************************************************************************/
7765/* Generic CPU instanciation routine */
aaed909a 7766static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 7767{
7768#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 7769 int i;
7770
a750fc0b 7771 env->irq_inputs = NULL;
e1833e1f
JM		 7772 /* Set all exception vectors to an invalid address */
7773 for (i = 0; i < POWERPC_EXCP_NB; i++)
7774 env->excp_vectors[i] = (target_ulong)(-1ULL);
7775 env->excp_prefix = 0x00000000;
7776 env->ivor_mask = 0x00000000;
7777 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 7778 /* Default MMU definitions */
7779 env->nb_BATs = 0;
7780 env->nb_tlb = 0;
7781 env->nb_ways = 0;
f2e63a42 7782#endif
a750fc0b
JM		 7783 /* Register SPR common to all PowerPC implementations */
7784 gen_spr_generic(env);
7785 spr_register(env, SPR_PVR, "PVR",
7786 SPR_NOACCESS, SPR_NOACCESS,
7787 &spr_read_generic, SPR_NOACCESS,
7788 def->pvr);
80d11f44
JM		 7789 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7790 if (def->svr != POWERPC_SVR_NONE) {
7791 if (def->svr & POWERPC_SVR_E500) {
7792 spr_register(env, SPR_E500_SVR, "SVR",
7793 SPR_NOACCESS, SPR_NOACCESS,
7794 &spr_read_generic, SPR_NOACCESS,
7795 def->svr & ~POWERPC_SVR_E500);
7796 } else {
7797 spr_register(env, SPR_SVR, "SVR",
7798 SPR_NOACCESS, SPR_NOACCESS,
7799 &spr_read_generic, SPR_NOACCESS,
7800 def->svr);
7801 }
7802 }
a750fc0b
JM		 7803 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7804 (*def->init_proc)(env);
25ba3a68
JM		 7805 /* MSR bits & flags consistency checks */
7806 if (env->msr_mask & (1 << 25)) {
7807 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7808 case POWERPC_FLAG_SPE:
7809 case POWERPC_FLAG_VRE:
7810 break;
7811 default:
7812 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7813 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7814 exit(1);
7815 }
7816 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7817 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7818 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7819 exit(1);
7820 }
7821 if (env->msr_mask & (1 << 17)) {
7822 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7823 case POWERPC_FLAG_TGPR:
7824 case POWERPC_FLAG_CE:
7825 break;
7826 default:
7827 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7828 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7829 exit(1);
7830 }
7831 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7832 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7833 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7834 exit(1);
7835 }
7836 if (env->msr_mask & (1 << 10)) {
7837 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7838 POWERPC_FLAG_UBLE)) {
7839 case POWERPC_FLAG_SE:
7840 case POWERPC_FLAG_DWE:
7841 case POWERPC_FLAG_UBLE:
7842 break;
7843 default:
7844 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7845 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7846 "POWERPC_FLAG_UBLE\n");
7847 exit(1);
7848 }
7849 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7850 POWERPC_FLAG_UBLE)) {
7851 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7852 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7853 "POWERPC_FLAG_UBLE\n");
7854 exit(1);
7855 }
7856 if (env->msr_mask & (1 << 9)) {
7857 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7858 case POWERPC_FLAG_BE:
7859 case POWERPC_FLAG_DE:
7860 break;
7861 default:
7862 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7863 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7864 exit(1);
7865 }
7866 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7867 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7868 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7869 exit(1);
7870 }
7871 if (env->msr_mask & (1 << 2)) {
7872 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7873 case POWERPC_FLAG_PX:
7874 case POWERPC_FLAG_PMM:
7875 break;
7876 default:
7877 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7878 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7879 exit(1);
7880 }
7881 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7882 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7883 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7884 exit(1);
7885 }
a750fc0b 7886 /* Allocate TLBs buffer when needed */
f2e63a42 7887#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 7888 if (env->nb_tlb != 0) {
7889 int nb_tlb = env->nb_tlb;
7890 if (env->id_tlbs != 0)
7891 nb_tlb *= 2;
7892 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
7893 /* Pre-compute some useful values */
7894 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7895 }
a750fc0b
JM		 7896 if (env->irq_inputs == NULL) {
7897 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7898 " Attempt Qemu to crash very soon !\n");
7899 }
7900#endif
2f462816
JM		 7901 if (env->check_pow == NULL) {
7902 fprintf(stderr, "WARNING: no power management check handler "
7903 "registered.\n"
7904 " Attempt Qemu to crash very soon !\n");
7905 }
a750fc0b
JM		 7906}
7907
7908#if defined(PPC_DUMP_CPU)
7909static void dump_ppc_sprs (CPUPPCState *env)
7910{
7911 ppc_spr_t *spr;
7912#if !defined(CONFIG_USER_ONLY)
7913 uint32_t sr, sw;
7914#endif
7915 uint32_t ur, uw;
7916 int i, j, n;
7917
7918 printf("Special purpose registers:\n");
7919 for (i = 0; i < 32; i++) {
7920 for (j = 0; j < 32; j++) {
7921 n = (i << 5) | j;
7922 spr = &env->spr_cb[n];
7923 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7924 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7925#if !defined(CONFIG_USER_ONLY)
7926 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7927 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7928 if (sw || sr || uw || ur) {
7929 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7930 (i << 5) | j, (i << 5) | j, spr->name,
7931 sw ? 'w' : '-', sr ? 'r' : '-',
7932 uw ? 'w' : '-', ur ? 'r' : '-');
7933 }
7934#else
7935 if (uw || ur) {
7936 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7937 (i << 5) | j, (i << 5) | j, spr->name,
7938 uw ? 'w' : '-', ur ? 'r' : '-');
7939 }
7940#endif
7941 }
7942 }
7943 fflush(stdout);
7944 fflush(stderr);
7945}
7946#endif
7947
7948/*****************************************************************************/
7949#include <stdlib.h>
7950#include <string.h>
7951
7952int fflush (FILE *stream);
7953
7954/* Opcode types */
7955enum {
7956 PPC_DIRECT = 0, /* Opcode routine */
7957 PPC_INDIRECT = 1, /* Indirect opcode table */
7958};
7959
7960static inline int is_indirect_opcode (void *handler)
7961{
7962 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
7963}
7964
7965static inline opc_handler_t **ind_table(void *handler)
7966{
7967 return (opc_handler_t **)((unsigned long)handler & ~3);
7968}
7969
7970/* Instruction table creation */
7971/* Opcodes tables creation */
7972static void fill_new_table (opc_handler_t **table, int len)
7973{
7974 int i;
7975
7976 for (i = 0; i < len; i++)
7977 table[i] = &invalid_handler;
7978}
7979
7980static int create_new_table (opc_handler_t **table, unsigned char idx)
7981{
7982 opc_handler_t **tmp;
7983
7984 tmp = malloc(0x20 * sizeof(opc_handler_t));
7985 if (tmp == NULL)
7986 return -1;
7987 fill_new_table(tmp, 0x20);
7988 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
7989
7990 return 0;
7991}
7992
7993static int insert_in_table (opc_handler_t **table, unsigned char idx,
7994 opc_handler_t *handler)
7995{
7996 if (table[idx] != &invalid_handler)
7997 return -1;
7998 table[idx] = handler;
7999
8000 return 0;
8001}
8002
8003static int register_direct_insn (opc_handler_t **ppc_opcodes,
8004 unsigned char idx, opc_handler_t *handler)
8005{
8006 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8007 printf("*** ERROR: opcode %02x already assigned in main "
8008 "opcode table\n", idx);
4c1b1bfe
JM		 8009#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8010 printf(" Registered handler '%s' - new handler '%s'\n",
8011 ppc_opcodes[idx]->oname, handler->oname);
8012#endif
a750fc0b
JM		 8013 return -1;
8014 }
8015
8016 return 0;
8017}
8018
8019static int register_ind_in_table (opc_handler_t **table,
8020 unsigned char idx1, unsigned char idx2,
8021 opc_handler_t *handler)
8022{
8023 if (table[idx1] == &invalid_handler) {
8024 if (create_new_table(table, idx1) < 0) {
8025 printf("*** ERROR: unable to create indirect table "
8026 "idx=%02x\n", idx1);
8027 return -1;
8028 }
8029 } else {
8030 if (!is_indirect_opcode(table[idx1])) {
8031 printf("*** ERROR: idx %02x already assigned to a direct "
8032 "opcode\n", idx1);
4c1b1bfe
JM		 8033#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8034 printf(" Registered handler '%s' - new handler '%s'\n",
8035 ind_table(table[idx1])[idx2]->oname, handler->oname);
8036#endif
a750fc0b
JM		 8037 return -1;
8038 }
3a607854 8039 }
a750fc0b
JM		 8040 if (handler != NULL &&
8041 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8042 printf("*** ERROR: opcode %02x already assigned in "
8043 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 8044#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8045 printf(" Registered handler '%s' - new handler '%s'\n",
8046 ind_table(table[idx1])[idx2]->oname, handler->oname);
8047#endif
a750fc0b 8048 return -1;
3a607854 8049 }
a750fc0b
JM		 8050
8051 return 0;
8052}
8053
8054static int register_ind_insn (opc_handler_t **ppc_opcodes,
8055 unsigned char idx1, unsigned char idx2,
8056 opc_handler_t *handler)
8057{
8058 int ret;
8059
8060 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8061
8062 return ret;
8063}
8064
8065static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8066 unsigned char idx1, unsigned char idx2,
8067 unsigned char idx3, opc_handler_t *handler)
8068{
8069 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8070 printf("*** ERROR: unable to join indirect table idx "
8071 "[%02x-%02x]\n", idx1, idx2);
8072 return -1;
8073 }
8074 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8075 handler) < 0) {
8076 printf("*** ERROR: unable to insert opcode "
8077 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8078 return -1;
8079 }
8080
8081 return 0;
8082}
8083
8084static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8085{
8086 if (insn->opc2 != 0xFF) {
8087 if (insn->opc3 != 0xFF) {
8088 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8089 insn->opc3, &insn->handler) < 0)
8090 return -1;
8091 } else {
8092 if (register_ind_insn(ppc_opcodes, insn->opc1,
8093 insn->opc2, &insn->handler) < 0)
8094 return -1;
8095 }
8096 } else {
8097 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8098 return -1;
8099 }
8100
8101 return 0;
8102}
8103
8104static int test_opcode_table (opc_handler_t **table, int len)
8105{
8106 int i, count, tmp;
8107
8108 for (i = 0, count = 0; i < len; i++) {
8109 /* Consistency fixup */
8110 if (table[i] == NULL)
8111 table[i] = &invalid_handler;
8112 if (table[i] != &invalid_handler) {
8113 if (is_indirect_opcode(table[i])) {
8114 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8115 if (tmp == 0) {
8116 free(table[i]);
8117 table[i] = &invalid_handler;
8118 } else {
8119 count++;
8120 }
8121 } else {
8122 count++;
8123 }
8124 }
8125 }
8126
8127 return count;
8128}
8129
8130static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8131{
8132 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8133 printf("*** WARNING: no opcode defined !\n");
8134}
8135
8136/*****************************************************************************/
aaed909a 8137static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8138{
8139 opcode_t *opc, *start, *end;
8140
8141 fill_new_table(env->opcodes, 0x40);
8142 if (&opc_start < &opc_end) {
8143 start = &opc_start;
8144 end = &opc_end;
8145 } else {
8146 start = &opc_end;
8147 end = &opc_start;
8148 }
8149 for (opc = start + 1; opc != end; opc++) {
8150 if ((opc->handler.type & def->insns_flags) != 0) {
8151 if (register_insn(env->opcodes, opc) < 0) {
8152 printf("*** ERROR initializing PowerPC instruction "
8153 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
8154 opc->opc3);
8155 return -1;
8156 }
8157 }
8158 }
8159 fix_opcode_tables(env->opcodes);
8160 fflush(stdout);
8161 fflush(stderr);
8162
8163 return 0;
8164}
8165
8166#if defined(PPC_DUMP_CPU)
25ba3a68 8167static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 8168{
8169 opc_handler_t **table, *handler;
4c1b1bfe 8170 const unsigned char *p, *q;
a750fc0b
JM		 8171 uint8_t opc1, opc2, opc3;
8172
8173 printf("Instructions set:\n");
8174 /* opc1 is 6 bits long */
8175 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8176 table = env->opcodes;
8177 handler = table[opc1];
8178 if (is_indirect_opcode(handler)) {
8179 /* opc2 is 5 bits long */
8180 for (opc2 = 0; opc2 < 0x20; opc2++) {
8181 table = env->opcodes;
8182 handler = env->opcodes[opc1];
8183 table = ind_table(handler);
8184 handler = table[opc2];
8185 if (is_indirect_opcode(handler)) {
8186 table = ind_table(handler);
8187 /* opc3 is 5 bits long */
8188 for (opc3 = 0; opc3 < 0x20; opc3++) {
8189 handler = table[opc3];
8190 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 8191 /* Special hack to properly dump SPE insns */
8192 p = strchr(handler->oname, '_');
8193 if (p == NULL) {
8194 printf("INSN: %02x %02x %02x (%02d %04d) : "
8195 "%s\n",
8196 opc1, opc2, opc3, opc1,
8197 (opc3 << 5) | opc2,
8198 handler->oname);
8199 } else {
8200 q = "speundef";
8201 if ((p - handler->oname) != strlen(q) ||
8202 memcmp(handler->oname, q, strlen(q)) != 0) {
8203 /* First instruction */
8204 printf("INSN: %02x %02x %02x (%02d %04d) : "
8205 "%.*s\n",
8206 opc1, opc2 << 1, opc3, opc1,
8207 (opc3 << 6) | (opc2 << 1),
8208 (int)(p - handler->oname),
8209 handler->oname);
8210 }
8211 if (strcmp(p + 1, q) != 0) {
8212 /* Second instruction */
8213 printf("INSN: %02x %02x %02x (%02d %04d) : "
8214 "%s\n",
8215 opc1, (opc2 << 1) | 1, opc3, opc1,
8216 (opc3 << 6) | (opc2 << 1) | 1,
8217 p + 1);
8218 }
8219 }
a750fc0b
JM		 8220 }
8221 }
8222 } else {
8223 if (handler->handler != &gen_invalid) {
8224 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8225 opc1, opc2, opc1, opc2, handler->oname);
8226 }
8227 }
8228 }
8229 } else {
8230 if (handler->handler != &gen_invalid) {
8231 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8232 opc1, opc1, handler->oname);
8233 }
8234 }
8235 }
8236}
3a607854 8237#endif
a750fc0b 8238
aaed909a 8239int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8240{
8241 env->msr_mask = def->msr_mask;
8242 env->mmu_model = def->mmu_model;
8243 env->excp_model = def->excp_model;
8244 env->bus_model = def->bus_model;
d26bfc9a 8245 env->flags = def->flags;
237c0af0 8246 env->bfd_mach = def->bfd_mach;
2f462816 8247 env->check_pow = def->check_pow;
a750fc0b
JM		 8248 if (create_ppc_opcodes(env, def) < 0)
8249 return -1;
8250 init_ppc_proc(env, def);
8251#if defined(PPC_DUMP_CPU)
3a607854 8252 {
a750fc0b
JM		 8253 const unsigned char *mmu_model, *excp_model, *bus_model;
8254 switch (env->mmu_model) {
8255 case POWERPC_MMU_32B:
8256 mmu_model = "PowerPC 32";
8257 break;
a750fc0b
JM		 8258 case POWERPC_MMU_SOFT_6xx:
8259 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8260 break;
8261 case POWERPC_MMU_SOFT_74xx:
8262 mmu_model = "PowerPC 74xx with software driven TLBs";
8263 break;
8264 case POWERPC_MMU_SOFT_4xx:
8265 mmu_model = "PowerPC 4xx with software driven TLBs";
8266 break;
8267 case POWERPC_MMU_SOFT_4xx_Z:
8268 mmu_model = "PowerPC 4xx with software driven TLBs "
8269 "and zones protections";
8270 break;
b4095fed
JM		 8271 case POWERPC_MMU_REAL:
8272 mmu_model = "PowerPC real mode only";
8273 break;
8274 case POWERPC_MMU_MPC8xx:
8275 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 8276 break;
8277 case POWERPC_MMU_BOOKE:
8278 mmu_model = "PowerPC BookE";
8279 break;
8280 case POWERPC_MMU_BOOKE_FSL:
8281 mmu_model = "PowerPC BookE FSL";
8282 break;
b4095fed
JM		 8283 case POWERPC_MMU_601:
8284 mmu_model = "PowerPC 601";
8285 break;
00af685f
JM		 8286#if defined (TARGET_PPC64)
8287 case POWERPC_MMU_64B:
8288 mmu_model = "PowerPC 64";
8289 break;
00af685f 8290#endif
a750fc0b
JM		 8291 default:
8292 mmu_model = "Unknown or invalid";
8293 break;
8294 }
8295 switch (env->excp_model) {
8296 case POWERPC_EXCP_STD:
8297 excp_model = "PowerPC";
8298 break;
8299 case POWERPC_EXCP_40x:
8300 excp_model = "PowerPC 40x";
8301 break;
8302 case POWERPC_EXCP_601:
8303 excp_model = "PowerPC 601";
8304 break;
8305 case POWERPC_EXCP_602:
8306 excp_model = "PowerPC 602";
8307 break;
8308 case POWERPC_EXCP_603:
8309 excp_model = "PowerPC 603";
8310 break;
8311 case POWERPC_EXCP_603E:
8312 excp_model = "PowerPC 603e";
8313 break;
8314 case POWERPC_EXCP_604:
8315 excp_model = "PowerPC 604";
8316 break;
8317 case POWERPC_EXCP_7x0:
8318 excp_model = "PowerPC 740/750";
8319 break;
8320 case POWERPC_EXCP_7x5:
8321 excp_model = "PowerPC 745/755";
8322 break;
8323 case POWERPC_EXCP_74xx:
8324 excp_model = "PowerPC 74xx";
8325 break;
a750fc0b
JM		 8326 case POWERPC_EXCP_BOOKE:
8327 excp_model = "PowerPC BookE";
8328 break;
00af685f
JM		 8329#if defined (TARGET_PPC64)
8330 case POWERPC_EXCP_970:
8331 excp_model = "PowerPC 970";
8332 break;
8333#endif
a750fc0b
JM		 8334 default:
8335 excp_model = "Unknown or invalid";
8336 break;
8337 }
8338 switch (env->bus_model) {
8339 case PPC_FLAGS_INPUT_6xx:
8340 bus_model = "PowerPC 6xx";
8341 break;
8342 case PPC_FLAGS_INPUT_BookE:
8343 bus_model = "PowerPC BookE";
8344 break;
8345 case PPC_FLAGS_INPUT_405:
8346 bus_model = "PowerPC 405";
8347 break;
a750fc0b
JM		 8348 case PPC_FLAGS_INPUT_401:
8349 bus_model = "PowerPC 401/403";
8350 break;
b4095fed
JM		 8351 case PPC_FLAGS_INPUT_RCPU:
8352 bus_model = "RCPU / MPC8xx";
8353 break;
00af685f
JM		 8354#if defined (TARGET_PPC64)
8355 case PPC_FLAGS_INPUT_970:
8356 bus_model = "PowerPC 970";
8357 break;
8358#endif
a750fc0b
JM		 8359 default:
8360 bus_model = "Unknown or invalid";
8361 break;
8362 }
8363 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8364 " MMU model : %s\n",
8365 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 8366#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8367 if (env->tlb != NULL) {
8368 printf(" %d %s TLB in %d ways\n",
8369 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8370 env->nb_ways);
8371 }
f2e63a42 8372#endif
a750fc0b
JM		 8373 printf(" Exceptions model : %s\n"
8374 " Bus model : %s\n",
8375 excp_model, bus_model);
25ba3a68
JM		 8376 printf(" MSR features :\n");
8377 if (env->flags & POWERPC_FLAG_SPE)
8378 printf(" signal processing engine enable"
8379 "\n");
8380 else if (env->flags & POWERPC_FLAG_VRE)
8381 printf(" vector processor enable\n");
8382 if (env->flags & POWERPC_FLAG_TGPR)
8383 printf(" temporary GPRs\n");
8384 else if (env->flags & POWERPC_FLAG_CE)
8385 printf(" critical input enable\n");
8386 if (env->flags & POWERPC_FLAG_SE)
8387 printf(" single-step trace mode\n");
8388 else if (env->flags & POWERPC_FLAG_DWE)
8389 printf(" debug wait enable\n");
8390 else if (env->flags & POWERPC_FLAG_UBLE)
8391 printf(" user BTB lock enable\n");
8392 if (env->flags & POWERPC_FLAG_BE)
8393 printf(" branch-step trace mode\n");
8394 else if (env->flags & POWERPC_FLAG_DE)
8395 printf(" debug interrupt enable\n");
8396 if (env->flags & POWERPC_FLAG_PX)
8397 printf(" inclusive protection\n");
8398 else if (env->flags & POWERPC_FLAG_PMM)
8399 printf(" performance monitor mark\n");
8400 if (env->flags == POWERPC_FLAG_NONE)
8401 printf(" none\n");
a750fc0b
JM		 8402 }
8403 dump_ppc_insns(env);
8404 dump_ppc_sprs(env);
8405 fflush(stdout);
3a607854 8406#endif
a750fc0b
JM		 8407
8408 return 0;
8409}
3fc6c082 8410
ee4e83ed 8411static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 8412{
ee4e83ed
JM		 8413 const ppc_def_t *ret;
8414 uint32_t pvr_rev;
8415 int i, best, match, best_match, max;
3fc6c082 8416
ee4e83ed 8417 ret = NULL;
068abdc8 8418 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
ee4e83ed
JM		 8419 best = -1;
8420 pvr_rev = pvr & 0xFFFF;
8421 /* We want all specified bits to match */
8422 best_match = 32 - ctz32(pvr_rev);
068abdc8 8423 for (i = 0; i < max; i++) {
ee4e83ed
JM		 8424 /* We check that the 16 higher bits are the same to ensure the CPU
8425 * model will be the choosen one.
8426 */
8427 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
8428 /* We want as much as possible of the low-level 16 bits
8429 * to be the same but we allow inexact matches.
8430 */
8431 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
8432 /* We check '>=' instead of '>' because the PPC_defs table
8433 * is ordered by increasing revision.
4c1b1bfe 8434 * Then, we will match the higher revision compatible
ee4e83ed
JM		 8435 * with the requested PVR
8436 */
8437 if (match >= best_match) {
8438 best = i;
8439 best_match = match;
8440 }
3fc6c082
FB		 8441 }
8442 }
ee4e83ed
JM		 8443 if (best != -1)
8444 ret = &ppc_defs[best];
8445
8446 return ret;
3fc6c082
FB		 8447}
8448
ee4e83ed 8449#include <ctype.h>
3fc6c082 8450
ee4e83ed
JM		 8451const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
8452{
8453 const ppc_def_t *ret;
8454 const unsigned char *p;
8455 int i, max, len;
8456
8457 /* Check if the given name is a PVR */
8458 len = strlen(name);
8459 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8460 p = name + 2;
8461 goto check_pvr;
8462 } else if (len == 8) {
8463 p = name;
8464 check_pvr:
8465 for (i = 0; i < 8; i++) {
8466 if (!isxdigit(*p++))
8467 break;
8468 }
8469 if (i == 8)
8470 return ppc_find_by_pvr(strtoul(name, NULL, 16));
8471 }
8472 ret = NULL;
068abdc8
JM		 8473 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
8474 for (i = 0; i < max; i++) {
ee4e83ed
JM		 8475 if (strcasecmp(name, ppc_defs[i].name) == 0) {
8476 ret = &ppc_defs[i];
8477 break;
3fc6c082
FB		 8478 }
8479 }
ee4e83ed
JM		 8480
8481 return ret;
3fc6c082
FB		 8482}
8483
8484void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
8485{
068abdc8 8486 int i, max;
3fc6c082 8487
068abdc8
JM		 8488 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
8489 for (i = 0; i < max; i++) {
a750fc0b
JM		 8490 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
8491 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 8492 }
8493}
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