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spapr_vscsi: Fix REPORT_LUNS handling
[mirror_qemu.git] / target-ppc / translate_init.c
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3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
76cad711 21#include "disas/bfd.h"
022c62cb 22#include "exec/gdbstub.h"
9c17d615 23#include <sysemu/kvm.h>
a1e98583 24#include "kvm_ppc.h"
9c17d615 25#include "sysemu/arch_init.h"
fe828a4d 26#include "sysemu/cpus.h"
953af181 27#include "cpu-models.h"
b632a148
DG		 28#include "mmu-hash32.h"
29#include "mmu-hash64.h"
4a44d85e 30#include "qemu/error-report.h"
237c0af0 31
3fc6c082
FB		 32//#define PPC_DUMP_CPU
33//#define PPC_DEBUG_SPR
80d11f44 34//#define PPC_DUMP_SPR_ACCESSES
3fc6c082 35
e9df014c
JM		 36/* For user-mode emulation, we don't emulate any IRQ controller */
37#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 38#define PPC_IRQ_INIT_FN(name) \
39static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
40{ \
e9df014c
JM		 41}
42#else
a750fc0b 43#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 44void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
45#endif
a750fc0b 46
4e290a0b 47PPC_IRQ_INIT_FN(40x);
e9df014c 48PPC_IRQ_INIT_FN(6xx);
d0dfae6e 49PPC_IRQ_INIT_FN(970);
9d52e907 50PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 51PPC_IRQ_INIT_FN(e500);
e9df014c 52
3fc6c082
FB		 53/* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
91f477fd
AG		 56static void spr_load_dump_spr(int sprn)
57{
58#ifdef PPC_DUMP_SPR_ACCESSES
59 TCGv_i32 t0 = tcg_const_i32(sprn);
edbe35e0 60 gen_helper_load_dump_spr(cpu_env, t0);
91f477fd
AG		 61 tcg_temp_free_i32(t0);
62#endif
63}
64
45d827d2 65static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 66{
45d827d2 67 gen_load_spr(cpu_gpr[gprn], sprn);
91f477fd
AG		 68 spr_load_dump_spr(sprn);
69}
70
71static void spr_store_dump_spr(int sprn)
72{
45d827d2 73#ifdef PPC_DUMP_SPR_ACCESSES
91f477fd 74 TCGv_i32 t0 = tcg_const_i32(sprn);
edbe35e0 75 gen_helper_store_dump_spr(cpu_env, t0);
91f477fd 76 tcg_temp_free_i32(t0);
45d827d2 77#endif
a496775f
JM		 78}
79
45d827d2 80static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 81{
45d827d2 82 gen_store_spr(sprn, cpu_gpr[gprn]);
91f477fd 83 spr_store_dump_spr(sprn);
45d827d2 84}
a496775f
JM		 85
86#if !defined(CONFIG_USER_ONLY)
ba38ab8d
AG		 87static void spr_write_generic32(void *opaque, int sprn, int gprn)
88{
89#ifdef TARGET_PPC64
90 TCGv t0 = tcg_temp_new();
91 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
92 gen_store_spr(sprn, t0);
93 tcg_temp_free(t0);
94 spr_store_dump_spr(sprn);
95#else
96 spr_write_generic(opaque, sprn, gprn);
97#endif
98}
99
45d827d2 100static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 101{
45d827d2
AJ		 102 TCGv t0 = tcg_temp_new();
103 TCGv t1 = tcg_temp_new();
104 gen_load_spr(t0, sprn);
105 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
106 tcg_gen_and_tl(t0, t0, t1);
107 gen_store_spr(sprn, t0);
108 tcg_temp_free(t0);
109 tcg_temp_free(t1);
a496775f 110}
9633fcc6
AG		 111
112static void spr_access_nop(void *opaque, int sprn, int gprn)
113{
114}
115
a496775f
JM		 116#endif
117
76a66253 118/* SPR common to all PowerPC */
3fc6c082 119/* XER */
45d827d2 120static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 121{
da91a00f 122 gen_read_xer(cpu_gpr[gprn]);
3fc6c082
FB		 123}
124
45d827d2 125static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 126{
da91a00f 127 gen_write_xer(cpu_gpr[gprn]);
3fc6c082
FB		 128}
129
130/* LR */
45d827d2 131static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 132{
45d827d2 133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 134}
135
45d827d2 136static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 137{
45d827d2 138 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 139}
140
697ab892
DG		 141/* CFAR */
142#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
143static void spr_read_cfar (void *opaque, int gprn, int sprn)
144{
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
146}
147
148static void spr_write_cfar (void *opaque, int sprn, int gprn)
149{
150 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
151}
152#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
153
3fc6c082 154/* CTR */
45d827d2 155static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 156{
45d827d2 157 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 158}
159
45d827d2 160static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 161{
45d827d2 162 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 163}
164
165/* User read access to SPR */
166/* USPRx */
167/* UMMCRx */
168/* UPMCx */
169/* USIA */
170/* UDECR */
45d827d2 171static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 172{
45d827d2 173 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 174}
175
76a66253 176/* SPR common to all non-embedded PowerPC */
3fc6c082 177/* DECR */
76a66253 178#if !defined(CONFIG_USER_ONLY)
45d827d2 179static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 180{
630ecca0
TG		 181 if (use_icount) {
182 gen_io_start();
183 }
d0f1562d 184 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 185 if (use_icount) {
186 gen_io_end();
187 gen_stop_exception(opaque);
188 }
3fc6c082
FB		 189}
190
45d827d2 191static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 192{
630ecca0
TG		 193 if (use_icount) {
194 gen_io_start();
195 }
d0f1562d 196 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 197 if (use_icount) {
198 gen_io_end();
199 gen_stop_exception(opaque);
200 }
3fc6c082 201}
76a66253 202#endif
3fc6c082 203
76a66253 204/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 205/* Time base */
45d827d2 206static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 207{
630ecca0
TG		 208 if (use_icount) {
209 gen_io_start();
210 }
d0f1562d 211 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 212 if (use_icount) {
213 gen_io_end();
214 gen_stop_exception(opaque);
215 }
3fc6c082
FB		 216}
217
45d827d2 218static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 219{
630ecca0
TG		 220 if (use_icount) {
221 gen_io_start();
222 }
d0f1562d 223 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 224 if (use_icount) {
225 gen_io_end();
226 gen_stop_exception(opaque);
227 }
3fc6c082
FB		 228}
229
a062e36c 230__attribute__ (( unused ))
45d827d2 231static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 232{
d0f1562d 233 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 234}
235
236__attribute__ (( unused ))
45d827d2 237static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 238{
d0f1562d 239 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 240}
241
76a66253 242#if !defined(CONFIG_USER_ONLY)
45d827d2 243static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 244{
630ecca0
TG		 245 if (use_icount) {
246 gen_io_start();
247 }
d0f1562d 248 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 249 if (use_icount) {
250 gen_io_end();
251 gen_stop_exception(opaque);
252 }
3fc6c082
FB		 253}
254
45d827d2 255static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 256{
630ecca0
TG		 257 if (use_icount) {
258 gen_io_start();
259 }
d0f1562d 260 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 261 if (use_icount) {
262 gen_io_end();
263 gen_stop_exception(opaque);
264 }
3fc6c082 265}
a062e36c
JM		 266
267__attribute__ (( unused ))
45d827d2 268static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 269{
d0f1562d 270 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
a062e36c
JM		 271}
272
273__attribute__ (( unused ))
45d827d2 274static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 275{
d0f1562d 276 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
a062e36c 277}
3a7f009a
DG		 278
279#if defined(TARGET_PPC64)
280__attribute__ (( unused ))
281static void spr_read_purr (void *opaque, int gprn, int sprn)
282{
d0f1562d 283 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
3a7f009a
DG		 284}
285#endif
76a66253 286#endif
3fc6c082 287
76a66253 288#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 289/* IBAT0U...IBAT0U */
290/* IBAT0L...IBAT7L */
45d827d2 291static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 292{
1328c2bf 293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 294}
295
45d827d2 296static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 297{
1328c2bf 298 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 299}
300
45d827d2 301static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 302{
45d827d2 303 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 304 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 305 tcg_temp_free_i32(t0);
3fc6c082
FB		 306}
307
45d827d2 308static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 309{
8daf1781 310 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
c6c7cf05 311 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 312 tcg_temp_free_i32(t0);
3fc6c082
FB		 313}
314
45d827d2 315static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 316{
45d827d2 317 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
c6c7cf05 318 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 319 tcg_temp_free_i32(t0);
3fc6c082
FB		 320}
321
45d827d2 322static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 323{
8daf1781 324 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
c6c7cf05 325 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 326 tcg_temp_free_i32(t0);
3fc6c082
FB		 327}
328
329/* DBAT0U...DBAT7U */
330/* DBAT0L...DBAT7L */
45d827d2 331static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 332{
1328c2bf 333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 334}
335
45d827d2 336static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 337{
1328c2bf 338 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 339}
340
45d827d2 341static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 342{
45d827d2 343 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
c6c7cf05 344 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 345 tcg_temp_free_i32(t0);
3fc6c082
FB		 346}
347
45d827d2 348static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 349{
45d827d2 350 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
c6c7cf05 351 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 352 tcg_temp_free_i32(t0);
3fc6c082
FB		 353}
354
45d827d2 355static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 356{
45d827d2 357 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
c6c7cf05 358 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 359 tcg_temp_free_i32(t0);
3fc6c082
FB		 360}
361
45d827d2 362static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 363{
45d827d2 364 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
c6c7cf05 365 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 366 tcg_temp_free_i32(t0);
3fc6c082
FB		 367}
368
369/* SDR1 */
45d827d2 370static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 371{
d523dd00 372 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
3fc6c082
FB		 373}
374
76a66253 375/* 64 bits PowerPC specific SPRs */
578bb252 376#if defined(TARGET_PPC64)
2adab7d6
BS		 377static void spr_read_hior (void *opaque, int gprn, int sprn)
378{
1328c2bf 379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 380}
381
382static void spr_write_hior (void *opaque, int sprn, int gprn)
383{
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
1328c2bf 386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 387 tcg_temp_free(t0);
388}
76a66253 389#endif
a750fc0b 390#endif
76a66253
JM		 391
392/* PowerPC 601 specific registers */
393/* RTC */
45d827d2 394static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 395{
d0f1562d 396 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
76a66253
JM		 397}
398
45d827d2 399static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 400{
d0f1562d 401 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
76a66253
JM		 402}
403
404#if !defined(CONFIG_USER_ONLY)
45d827d2 405static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 406{
d0f1562d 407 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 408}
409
45d827d2 410static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 411{
d0f1562d 412 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
76a66253 413}
056401ea 414
45d827d2 415static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 416{
417 DisasContext *ctx = opaque;
418
d523dd00 419 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
056401ea 420 /* Must stop the translation as endianness may have changed */
e06fcd75 421 gen_stop_exception(ctx);
056401ea 422}
76a66253
JM		 423#endif
424
425/* Unified bats */
426#if !defined(CONFIG_USER_ONLY)
45d827d2 427static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 428{
1328c2bf 429 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 430}
431
45d827d2 432static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 433{
45d827d2 434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 435 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 436 tcg_temp_free_i32(t0);
76a66253
JM		 437}
438
45d827d2 439static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 440{
45d827d2 441 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 442 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 443 tcg_temp_free_i32(t0);
76a66253
JM		 444}
445#endif
446
447/* PowerPC 40x specific registers */
448#if !defined(CONFIG_USER_ONLY)
45d827d2 449static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 450{
d0f1562d 451 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
76a66253
JM		 452}
453
45d827d2 454static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 455{
d0f1562d 456 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 457}
458
45d827d2 459static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 460{
461 DisasContext *ctx = opaque;
462
d523dd00 463 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
8ecc7913 464 /* We must stop translation as we may have rebooted */
e06fcd75 465 gen_stop_exception(ctx);
8ecc7913
JM		 466}
467
45d827d2 468static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 469{
d523dd00 470 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
c294fc58
JM		 471}
472
45d827d2 473static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 474{
d0f1562d 475 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 476}
477
45d827d2 478static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 479{
d0f1562d 480 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 481}
482#endif
483
484/* PowerPC 403 specific registers */
485/* PBL1 / PBU1 / PBL2 / PBU2 */
486#if !defined(CONFIG_USER_ONLY)
45d827d2 487static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 488{
1328c2bf 489 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 490}
491
45d827d2 492static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 493{
45d827d2 494 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
d523dd00 495 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 496 tcg_temp_free_i32(t0);
76a66253
JM		 497}
498
45d827d2 499static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 500{
45d827d2
AJ		 501 TCGv t0 = tcg_temp_new();
502 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
503 gen_store_spr(SPR_PIR, t0);
504 tcg_temp_free(t0);
3fc6c082 505}
76a66253 506#endif
3fc6c082 507
d34defbc
AJ		 508/* SPE specific registers */
509static void spr_read_spefscr (void *opaque, int gprn, int sprn)
510{
511 TCGv_i32 t0 = tcg_temp_new_i32();
1328c2bf 512 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 513 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
514 tcg_temp_free_i32(t0);
515}
516
517static void spr_write_spefscr (void *opaque, int sprn, int gprn)
518{
519 TCGv_i32 t0 = tcg_temp_new_i32();
520 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1328c2bf 521 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 522 tcg_temp_free_i32(t0);
523}
524
6f5d427d
JM		 525#if !defined(CONFIG_USER_ONLY)
526/* Callback used to write the exception vector base */
45d827d2 527static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 528{
45d827d2 529 TCGv t0 = tcg_temp_new();
1328c2bf 530 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
45d827d2 531 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 532 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
45d827d2 533 gen_store_spr(sprn, t0);
69bd5820 534 tcg_temp_free(t0);
6f5d427d
JM		 535}
536
45d827d2 537static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 538{
539 DisasContext *ctx = opaque;
e9205258 540 int sprn_offs;
6f5d427d
JM		 541
542 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
e9205258 543 sprn_offs = sprn - SPR_BOOKE_IVOR0;
6f5d427d 544 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
e9205258
AG		 545 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
546 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
547 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
6f5d427d
JM		 548 } else {
549 printf("Trying to write an unknown exception vector %d %03x\n",
550 sprn, sprn);
e06fcd75 551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
e9205258 552 return;
6f5d427d 553 }
e9205258
AG		 554
555 TCGv t0 = tcg_temp_new();
1328c2bf 556 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
e9205258 557 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 558 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
e9205258
AG		 559 gen_store_spr(sprn, t0);
560 tcg_temp_free(t0);
6f5d427d
JM		 561}
562#endif
563
cf8358c8
AJ		 564static inline void vscr_init (CPUPPCState *env, uint32_t val)
565{
566 env->vscr = val;
567 /* Altivec always uses round-to-nearest */
568 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
569 set_flush_to_zero(vscr_nj, &env->vec_status);
570}
571
d67d40ea
DG		 572#ifdef CONFIG_USER_ONLY
573#define spr_register_kvm(env, num, name, uea_read, uea_write, \
574 oea_read, oea_write, one_reg_id, initial_value) \
575 _spr_register(env, num, name, uea_read, uea_write, initial_value)
576#else
577#if !defined(CONFIG_KVM)
578#define spr_register_kvm(env, num, name, uea_read, uea_write, \
579 oea_read, oea_write, one_reg_id, initial_value) \
580 _spr_register(env, num, name, uea_read, uea_write, \
581 oea_read, oea_write, initial_value)
76a66253 582#else
d67d40ea
DG		 583#define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, \
586 oea_read, oea_write, one_reg_id, initial_value)
587#endif
588#endif
589
590#define spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value) \
592 spr_register_kvm(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, 0, initial_value)
594
595static inline void _spr_register(CPUPPCState *env, int num,
b55266b5 596 const char *name,
45d827d2
AJ		 597 void (*uea_read)(void *opaque, int gprn, int sprn),
598 void (*uea_write)(void *opaque, int sprn, int gprn),
d67d40ea
DG		 599#if !defined(CONFIG_USER_ONLY)
600
45d827d2
AJ		 601 void (*oea_read)(void *opaque, int gprn, int sprn),
602 void (*oea_write)(void *opaque, int sprn, int gprn),
76a66253 603#endif
d67d40ea
DG		 604#if defined(CONFIG_KVM)
605 uint64_t one_reg_id,
606#endif
607 target_ulong initial_value)
3fc6c082 608{
c227f099 609 ppc_spr_t *spr;
3fc6c082
FB		 610
611 spr = &env->spr_cb[num];
612 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 613#if !defined(CONFIG_USER_ONLY)
614 spr->oea_read != NULL || spr->oea_write != NULL ||
615#endif
616 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 617 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
618 exit(1);
619 }
620#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 621 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
622 name, initial_value);
3fc6c082
FB		 623#endif
624 spr->name = name;
625 spr->uea_read = uea_read;
626 spr->uea_write = uea_write;
76a66253 627#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 628 spr->oea_read = oea_read;
629 spr->oea_write = oea_write;
7a7c05d7
AK		 630#endif
631#if defined(CONFIG_KVM)
632 spr->one_reg_id = one_reg_id,
76a66253 633#endif
3fc6c082
FB		 634 env->spr[num] = initial_value;
635}
636
637/* Generic PowerPC SPRs */
638static void gen_spr_generic (CPUPPCState *env)
639{
640 /* Integer processing */
641 spr_register(env, SPR_XER, "XER",
642 &spr_read_xer, &spr_write_xer,
643 &spr_read_xer, &spr_write_xer,
644 0x00000000);
645 /* Branch contol */
646 spr_register(env, SPR_LR, "LR",
647 &spr_read_lr, &spr_write_lr,
648 &spr_read_lr, &spr_write_lr,
649 0x00000000);
650 spr_register(env, SPR_CTR, "CTR",
651 &spr_read_ctr, &spr_write_ctr,
652 &spr_read_ctr, &spr_write_ctr,
653 0x00000000);
654 /* Interrupt processing */
655 spr_register(env, SPR_SRR0, "SRR0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SRR1, "SRR1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Processor control */
664 spr_register(env, SPR_SPRG0, "SPRG0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SPRG1, "SPRG1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_SPRG2, "SPRG2",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SPRG3, "SPRG3",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680}
681
682/* SPR common to all non-embedded PowerPC, including 601 */
683static void gen_spr_ne_601 (CPUPPCState *env)
684{
685 /* Exception processing */
d67d40ea
DG		 686 spr_register_kvm(env, SPR_DSISR, "DSISR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 KVM_REG_PPC_DSISR, 0x00000000);
690 spr_register_kvm(env, SPR_DAR, "DAR",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_generic,
693 KVM_REG_PPC_DAR, 0x00000000);
3fc6c082
FB		 694 /* Timer */
695 spr_register(env, SPR_DECR, "DECR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_decr, &spr_write_decr,
698 0x00000000);
699 /* Memory management */
700 spr_register(env, SPR_SDR1, "SDR1",
701 SPR_NOACCESS, SPR_NOACCESS,
bb593904 702 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 703 0x00000000);
704}
705
706/* BATs 0-3 */
707static void gen_low_BATs (CPUPPCState *env)
708{
f2e63a42 709#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 710 spr_register(env, SPR_IBAT0U, "IBAT0U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT0L, "IBAT0L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT1U, "IBAT1U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT1L, "IBAT1L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_IBAT2U, "IBAT2U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_ibat, &spr_write_ibatu,
729 0x00000000);
730 spr_register(env, SPR_IBAT2L, "IBAT2L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_ibat, &spr_write_ibatl,
733 0x00000000);
734 spr_register(env, SPR_IBAT3U, "IBAT3U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_ibat, &spr_write_ibatu,
737 0x00000000);
738 spr_register(env, SPR_IBAT3L, "IBAT3L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_ibat, &spr_write_ibatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT0U, "DBAT0U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT0L, "DBAT0L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT1U, "DBAT1U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT1L, "DBAT1L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 spr_register(env, SPR_DBAT2U, "DBAT2U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_dbat, &spr_write_dbatu,
761 0x00000000);
762 spr_register(env, SPR_DBAT2L, "DBAT2L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_dbat, &spr_write_dbatl,
765 0x00000000);
766 spr_register(env, SPR_DBAT3U, "DBAT3U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_dbat, &spr_write_dbatu,
769 0x00000000);
770 spr_register(env, SPR_DBAT3L, "DBAT3L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_dbat, &spr_write_dbatl,
773 0x00000000);
a750fc0b 774 env->nb_BATs += 4;
f2e63a42 775#endif
3fc6c082
FB		 776}
777
778/* BATs 4-7 */
779static void gen_high_BATs (CPUPPCState *env)
780{
f2e63a42 781#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 782 spr_register(env, SPR_IBAT4U, "IBAT4U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT4L, "IBAT4L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT5U, "IBAT5U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT5L, "IBAT5L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_IBAT6U, "IBAT6U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat_h, &spr_write_ibatu_h,
801 0x00000000);
802 spr_register(env, SPR_IBAT6L, "IBAT6L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat_h, &spr_write_ibatl_h,
805 0x00000000);
806 spr_register(env, SPR_IBAT7U, "IBAT7U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat_h, &spr_write_ibatu_h,
809 0x00000000);
810 spr_register(env, SPR_IBAT7L, "IBAT7L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat_h, &spr_write_ibatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT4U, "DBAT4U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT4L, "DBAT4L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT5U, "DBAT5U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT5L, "DBAT5L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 spr_register(env, SPR_DBAT6U, "DBAT6U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat_h, &spr_write_dbatu_h,
833 0x00000000);
834 spr_register(env, SPR_DBAT6L, "DBAT6L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat_h, &spr_write_dbatl_h,
837 0x00000000);
838 spr_register(env, SPR_DBAT7U, "DBAT7U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat_h, &spr_write_dbatu_h,
841 0x00000000);
842 spr_register(env, SPR_DBAT7L, "DBAT7L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat_h, &spr_write_dbatl_h,
845 0x00000000);
a750fc0b 846 env->nb_BATs += 4;
f2e63a42 847#endif
3fc6c082
FB		 848}
849
850/* Generic PowerPC time base */
851static void gen_tbl (CPUPPCState *env)
852{
853 spr_register(env, SPR_VTBL, "TBL",
854 &spr_read_tbl, SPR_NOACCESS,
855 &spr_read_tbl, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 858 &spr_read_tbl, SPR_NOACCESS,
859 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 860 0x00000000);
861 spr_register(env, SPR_VTBU, "TBU",
862 &spr_read_tbu, SPR_NOACCESS,
863 &spr_read_tbu, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 866 &spr_read_tbu, SPR_NOACCESS,
867 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 868 0x00000000);
869}
870
76a66253
JM		 871/* Softare table search registers */
872static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
873{
f2e63a42 874#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 875 env->nb_tlb = nb_tlbs;
876 env->nb_ways = nb_ways;
877 env->id_tlbs = 1;
1c53accc 878 env->tlb_type = TLB_6XX;
76a66253
JM		 879 spr_register(env, SPR_DMISS, "DMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_DCMP, "DCMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_HASH1, "HASH1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 0x00000000);
891 spr_register(env, SPR_HASH2, "HASH2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, SPR_NOACCESS,
894 0x00000000);
895 spr_register(env, SPR_IMISS, "IMISS",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 spr_register(env, SPR_ICMP, "ICMP",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 0x00000000);
903 spr_register(env, SPR_RPA, "RPA",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
f2e63a42 907#endif
76a66253
JM		 908}
909
910/* SPR common to MPC755 and G2 */
911static void gen_spr_G2_755 (CPUPPCState *env)
912{
913 /* SGPRs */
914 spr_register(env, SPR_SPRG4, "SPRG4",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 spr_register(env, SPR_SPRG5, "SPRG5",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 spr_register(env, SPR_SPRG6, "SPRG6",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 spr_register(env, SPR_SPRG7, "SPRG7",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
76a66253
JM		 930}
931
3fc6c082
FB		 932/* SPR common to all 7xx PowerPC implementations */
933static void gen_spr_7xx (CPUPPCState *env)
934{
935 /* Breakpoints */
936 /* XXX : not implemented */
d67d40ea
DG		 937 spr_register_kvm(env, SPR_DABR, "DABR",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082
FB		 941 /* XXX : not implemented */
942 spr_register(env, SPR_IABR, "IABR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* Cache management */
947 /* XXX : not implemented */
948 spr_register(env, SPR_ICTC, "ICTC",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Performance monitors */
953 /* XXX : not implemented */
954 spr_register(env, SPR_MMCR0, "MMCR0",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_MMCR1, "MMCR1",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC1, "PMC1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC2, "PMC2",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_PMC3, "PMC3",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_PMC4, "PMC4",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
a750fc0b 984 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, SPR_NOACCESS,
987 0x00000000);
578bb252 988 /* XXX : not implemented */
3fc6c082
FB		 989 spr_register(env, SPR_UMMCR0, "UMMCR0",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
578bb252 993 /* XXX : not implemented */
3fc6c082
FB		 994 spr_register(env, SPR_UMMCR1, "UMMCR1",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
578bb252 998 /* XXX : not implemented */
3fc6c082
FB		 999 spr_register(env, SPR_UPMC1, "UPMC1",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
578bb252 1003 /* XXX : not implemented */
3fc6c082
FB		 1004 spr_register(env, SPR_UPMC2, "UPMC2",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
578bb252 1008 /* XXX : not implemented */
3fc6c082
FB		 1009 spr_register(env, SPR_UPMC3, "UPMC3",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
578bb252 1013 /* XXX : not implemented */
3fc6c082
FB		 1014 spr_register(env, SPR_UPMC4, "UPMC4",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
578bb252 1018 /* XXX : not implemented */
a750fc0b 1019 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
a750fc0b 1023 /* External access control */
3fc6c082 1024 /* XXX : not implemented */
a750fc0b 1025 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
a750fc0b
JM		 1029}
1030
f80872e2
DG		 1031#ifdef TARGET_PPC64
1032#ifndef CONFIG_USER_ONLY
1033static void spr_read_uamr (void *opaque, int gprn, int sprn)
1034{
1035 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1036 spr_load_dump_spr(SPR_AMR);
1037}
1038
1039static void spr_write_uamr (void *opaque, int sprn, int gprn)
1040{
1041 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1042 spr_store_dump_spr(SPR_AMR);
1043}
1044
1045static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1046{
1047 TCGv t0 = tcg_temp_new();
1048
1049 gen_load_spr(t0, SPR_UAMOR);
1050 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1051 gen_store_spr(SPR_AMR, t0);
1052 spr_store_dump_spr(SPR_AMR);
1053}
1054#endif /* CONFIG_USER_ONLY */
1055
1056static void gen_spr_amr (CPUPPCState *env)
1057{
1058#ifndef CONFIG_USER_ONLY
1059 /* Virtual Page Class Key protection */
1060 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1061 * userspace accessible, 29 is privileged. So we only need to set
1062 * the kvm ONE_REG id on one of them, we use 29 */
1063 spr_register(env, SPR_UAMR, "UAMR",
1064 &spr_read_uamr, &spr_write_uamr_pr,
1065 &spr_read_uamr, &spr_write_uamr,
1066 0);
1067 spr_register_kvm(env, SPR_AMR, "AMR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
0dc083fe 1070 KVM_REG_PPC_AMR, 0);
f80872e2
DG		 1071 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 KVM_REG_PPC_UAMOR, 0);
1075#endif /* !CONFIG_USER_ONLY */
1076}
1077#endif /* TARGET_PPC64 */
1078
a750fc0b
JM		 1079static void gen_spr_thrm (CPUPPCState *env)
1080{
1081 /* Thermal management */
3fc6c082 1082 /* XXX : not implemented */
a750fc0b 1083 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, &spr_write_generic,
1086 0x00000000);
1087 /* XXX : not implemented */
a750fc0b 1088 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
3fc6c082 1092 /* XXX : not implemented */
a750fc0b 1093 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097}
1098
1099/* SPR specific to PowerPC 604 implementation */
1100static void gen_spr_604 (CPUPPCState *env)
1101{
1102 /* Processor identification */
1103 spr_register(env, SPR_PIR, "PIR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_pir,
1106 0x00000000);
1107 /* Breakpoints */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_IABR, "IABR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
d67d40ea
DG		 1114 spr_register_kvm(env, SPR_DABR, "DABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082
FB		 1118 /* Performance counters */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_MMCR0, "MMCR0",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
3fc6c082
FB		 1125 spr_register(env, SPR_PMC1, "PMC1",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_PMC2, "PMC2",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
a750fc0b 1135 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, SPR_NOACCESS,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SDA, "SDA",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, SPR_NOACCESS,
1143 0x00000000);
1144 /* External access control */
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_EAR, "EAR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150}
1151
76a66253
JM		 1152/* SPR specific to PowerPC 603 implementation */
1153static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1154{
76a66253
JM		 1155 /* External access control */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1158 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
2bc17322
FC		 1161 /* Breakpoints */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_IABR, "IABR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167
3fc6c082
FB		 1168}
1169
76a66253
JM		 1170/* SPR specific to PowerPC G2 implementation */
1171static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1172{
76a66253
JM		 1173 /* Memory base address */
1174 /* MBAR */
578bb252 1175 /* XXX : not implemented */
76a66253
JM		 1176 spr_register(env, SPR_MBAR, "MBAR",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
76a66253 1180 /* Exception processing */
363be49c 1181 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
363be49c 1185 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Breakpoints */
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_DABR, "DABR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_DABR2, "DABR2",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* XXX : not implemented */
1201 spr_register(env, SPR_IABR, "IABR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_IABR2, "IABR2",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_IBCR, "IBCR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_DBCR, "DBCR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220}
1221
1222/* SPR specific to PowerPC 602 implementation */
1223static void gen_spr_602 (CPUPPCState *env)
1224{
1225 /* ESA registers */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_SER, "SER",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_SEBR, "SEBR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* XXX : not implemented */
a750fc0b 1237 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* Floating point status */
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_SP, "SP",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_LT, "LT",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 /* Watchdog timer */
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_TCR, "TCR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* Interrupt base */
1259 spr_register(env, SPR_IBR, "IBR",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
a750fc0b
JM		 1263 /* XXX : not implemented */
1264 spr_register(env, SPR_IABR, "IABR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
76a66253
JM		 1268}
1269
1270/* SPR specific to PowerPC 601 implementation */
1271static void gen_spr_601 (CPUPPCState *env)
1272{
1273 /* Multiplication/division register */
1274 /* MQ */
1275 spr_register(env, SPR_MQ, "MQ",
1276 &spr_read_generic, &spr_write_generic,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
1279 /* RTC registers */
1280 spr_register(env, SPR_601_RTCU, "RTCU",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 SPR_NOACCESS, &spr_write_601_rtcu,
1283 0x00000000);
1284 spr_register(env, SPR_601_VRTCU, "RTCU",
1285 &spr_read_601_rtcu, SPR_NOACCESS,
1286 &spr_read_601_rtcu, SPR_NOACCESS,
1287 0x00000000);
1288 spr_register(env, SPR_601_RTCL, "RTCL",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 SPR_NOACCESS, &spr_write_601_rtcl,
1291 0x00000000);
1292 spr_register(env, SPR_601_VRTCL, "RTCL",
1293 &spr_read_601_rtcl, SPR_NOACCESS,
1294 &spr_read_601_rtcl, SPR_NOACCESS,
1295 0x00000000);
1296 /* Timer */
1297#if 0 /* ? */
1298 spr_register(env, SPR_601_UDECR, "UDECR",
1299 &spr_read_decr, SPR_NOACCESS,
1300 &spr_read_decr, SPR_NOACCESS,
1301 0x00000000);
1302#endif
1303 /* External access control */
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_EAR, "EAR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Memory management */
f2e63a42 1310#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1311 spr_register(env, SPR_IBAT0U, "IBAT0U",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_601_ubat, &spr_write_601_ubatu,
1314 0x00000000);
1315 spr_register(env, SPR_IBAT0L, "IBAT0L",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_601_ubat, &spr_write_601_ubatl,
1318 0x00000000);
1319 spr_register(env, SPR_IBAT1U, "IBAT1U",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_601_ubat, &spr_write_601_ubatu,
1322 0x00000000);
1323 spr_register(env, SPR_IBAT1L, "IBAT1L",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_601_ubat, &spr_write_601_ubatl,
1326 0x00000000);
1327 spr_register(env, SPR_IBAT2U, "IBAT2U",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_601_ubat, &spr_write_601_ubatu,
1330 0x00000000);
1331 spr_register(env, SPR_IBAT2L, "IBAT2L",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_601_ubat, &spr_write_601_ubatl,
1334 0x00000000);
1335 spr_register(env, SPR_IBAT3U, "IBAT3U",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_601_ubat, &spr_write_601_ubatu,
1338 0x00000000);
1339 spr_register(env, SPR_IBAT3L, "IBAT3L",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_601_ubat, &spr_write_601_ubatl,
1342 0x00000000);
a750fc0b 1343 env->nb_BATs = 4;
f2e63a42 1344#endif
a750fc0b
JM		 1345}
1346
1347static void gen_spr_74xx (CPUPPCState *env)
1348{
1349 /* Processor identification */
1350 spr_register(env, SPR_PIR, "PIR",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_pir,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_MMCR2, "MMCR2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
578bb252 1359 /* XXX : not implemented */
a750fc0b
JM		 1360 spr_register(env, SPR_UMMCR2, "UMMCR2",
1361 &spr_read_ureg, SPR_NOACCESS,
1362 &spr_read_ureg, SPR_NOACCESS,
1363 0x00000000);
1364 /* XXX: not implemented */
1365 spr_register(env, SPR_BAMR, "BAMR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
578bb252 1369 /* XXX : not implemented */
a750fc0b
JM		 1370 spr_register(env, SPR_MSSCR0, "MSSCR0",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* Hardware implementation registers */
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_HID0, "HID0",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_HID1, "HID1",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 /* Altivec */
1386 spr_register(env, SPR_VRSAVE, "VRSAVE",
1387 &spr_read_generic, &spr_write_generic,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
bd928eba
JM		 1390 /* XXX : not implemented */
1391 spr_register(env, SPR_L2CR, "L2CR",
1392 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 1393 &spr_read_generic, spr_access_nop,
bd928eba 1394 0x00000000);
cf8358c8
AJ		 1395 /* Not strictly an SPR */
1396 vscr_init(env, 0x00010000);
a750fc0b
JM		 1397}
1398
a750fc0b
JM		 1399static void gen_l3_ctrl (CPUPPCState *env)
1400{
1401 /* L3CR */
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_L3CR, "L3CR",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 /* L3ITCR0 */
578bb252 1408 /* XXX : not implemented */
a750fc0b
JM		 1409 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
a750fc0b 1413 /* L3PM */
578bb252 1414 /* XXX : not implemented */
a750fc0b
JM		 1415 spr_register(env, SPR_L3PM, "L3PM",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419}
a750fc0b 1420
578bb252 1421static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1422{
f2e63a42 1423#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1424 env->nb_tlb = nb_tlbs;
1425 env->nb_ways = nb_ways;
1426 env->id_tlbs = 1;
1c53accc 1427 env->tlb_type = TLB_6XX;
578bb252 1428 /* XXX : not implemented */
a750fc0b
JM		 1429 spr_register(env, SPR_PTEHI, "PTEHI",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
578bb252 1433 /* XXX : not implemented */
a750fc0b
JM		 1434 spr_register(env, SPR_PTELO, "PTELO",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
578bb252 1438 /* XXX : not implemented */
a750fc0b
JM		 1439 spr_register(env, SPR_TLBMISS, "TLBMISS",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
f2e63a42 1443#endif
76a66253
JM		 1444}
1445
01662f3e
AG		 1446#if !defined(CONFIG_USER_ONLY)
1447static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1448{
1449 TCGv t0 = tcg_temp_new();
1450
1451 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1452 gen_store_spr(sprn, t0);
1453 tcg_temp_free(t0);
1454}
1455
1456static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1457{
1ff7854e 1458 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1459 gen_helper_booke206_tlbflush(cpu_env, t0);
1ff7854e 1460 tcg_temp_free_i32(t0);
01662f3e
AG		 1461}
1462
1463static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1464{
1ff7854e 1465 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1466 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1ff7854e 1467 tcg_temp_free_i32(t0);
01662f3e
AG		 1468}
1469#endif
1470
80d11f44 1471static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1472{
80d11f44
JM		 1473 spr_register(env, SPR_USPRG4, "USPRG4",
1474 &spr_read_ureg, SPR_NOACCESS,
1475 &spr_read_ureg, SPR_NOACCESS,
1476 0x00000000);
1477 spr_register(env, SPR_USPRG5, "USPRG5",
1478 &spr_read_ureg, SPR_NOACCESS,
1479 &spr_read_ureg, SPR_NOACCESS,
1480 0x00000000);
1481 spr_register(env, SPR_USPRG6, "USPRG6",
1482 &spr_read_ureg, SPR_NOACCESS,
1483 &spr_read_ureg, SPR_NOACCESS,
1484 0x00000000);
1485 spr_register(env, SPR_USPRG7, "USPRG7",
1486 &spr_read_ureg, SPR_NOACCESS,
1487 &spr_read_ureg, SPR_NOACCESS,
76a66253 1488 0x00000000);
80d11f44
JM		 1489}
1490
1491/* PowerPC BookE SPR */
1492static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1493{
b55266b5 1494 const char *ivor_names[64] = {
80d11f44
JM		 1495 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1496 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1497 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1498 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1499 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1500 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1501 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1502 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1503 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1504 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1505 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1506 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1507 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1508 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1509 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1510 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1511 };
1512#define SPR_BOOKE_IVORxx (-1)
1513 int ivor_sprn[64] = {
1514 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1515 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1516 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1517 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1518 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1519 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1520 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1521 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1522 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 1523 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1524 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 1525 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1526 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1527 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1528 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1529 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1530 };
1531 int i;
1532
76a66253 1533 /* Interrupt processing */
363be49c 1534 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
363be49c
JM		 1538 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
76a66253
JM		 1542 /* Debug */
1543 /* XXX : not implemented */
1544 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 /* XXX : not implemented */
1549 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 /* XXX : not implemented */
76a66253
JM		 1554 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* XXX : not implemented */
1559 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 /* XXX : not implemented */
76a66253
JM		 1564 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1565 SPR_NOACCESS, SPR_NOACCESS,
e598a9c5 1566 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1567 0x00000000);
1568 /* XXX : not implemented */
1569 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1580 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1581 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1582 0x00000000);
1583 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 spr_register(env, SPR_BOOKE_ESR, "ESR",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
363be49c
JM		 1591 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1592 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1593 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1594 0x00000000);
1595 /* Exception vectors */
80d11f44
JM		 1596 for (i = 0; i < 64; i++) {
1597 if (ivor_mask & (1ULL << i)) {
1598 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1599 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1600 exit(1);
1601 }
1602 spr_register(env, ivor_sprn[i], ivor_names[i],
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_excp_vector,
1605 0x00000000);
1606 }
1607 }
76a66253
JM		 1608 spr_register(env, SPR_BOOKE_PID, "PID",
1609 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1610 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1611 0x00000000);
1612 spr_register(env, SPR_BOOKE_TCR, "TCR",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, &spr_write_booke_tcr,
1615 0x00000000);
1616 spr_register(env, SPR_BOOKE_TSR, "TSR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_booke_tsr,
1619 0x00000000);
1620 /* Timer */
1621 spr_register(env, SPR_DECR, "DECR",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_decr, &spr_write_decr,
1624 0x00000000);
1625 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 SPR_NOACCESS, &spr_write_generic,
1628 0x00000000);
1629 /* SPRGs */
1630 spr_register(env, SPR_USPRG0, "USPRG0",
1631 &spr_read_generic, &spr_write_generic,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 spr_register(env, SPR_SPRG4, "SPRG4",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
76a66253
JM		 1638 spr_register(env, SPR_SPRG5, "SPRG5",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
76a66253
JM		 1642 spr_register(env, SPR_SPRG6, "SPRG6",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
76a66253
JM		 1646 spr_register(env, SPR_SPRG7, "SPRG7",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
76a66253
JM		 1650}
1651
01662f3e
AG		 1652static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1653 uint32_t maxsize, uint32_t flags,
1654 uint32_t nentries)
1655{
1656 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1657 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1658 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1659 flags | nentries;
1660}
1661
1662/* BookE 2.06 storage control registers */
1663static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1664 uint32_t *tlbncfg)
363be49c 1665{
f2e63a42 1666#if !defined(CONFIG_USER_ONLY)
b55266b5 1667 const char *mas_names[8] = {
80d11f44
JM		 1668 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1669 };
1670 int mas_sprn[8] = {
1671 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1672 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1673 };
1674 int i;
1675
363be49c 1676 /* TLB assist registers */
578bb252 1677 /* XXX : not implemented */
80d11f44 1678 for (i = 0; i < 8; i++) {
ba38ab8d
AG		 1679 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1680 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1681 uea_write = &spr_write_generic;
1682 }
80d11f44
JM		 1683 if (mas_mask & (1 << i)) {
1684 spr_register(env, mas_sprn[i], mas_names[i],
1685 SPR_NOACCESS, SPR_NOACCESS,
ba38ab8d 1686 &spr_read_generic, uea_write,
80d11f44
JM		 1687 0x00000000);
1688 }
1689 }
363be49c 1690 if (env->nb_pids > 1) {
578bb252 1691 /* XXX : not implemented */
363be49c
JM		 1692 spr_register(env, SPR_BOOKE_PID1, "PID1",
1693 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1694 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1695 0x00000000);
1696 }
1697 if (env->nb_pids > 2) {
578bb252 1698 /* XXX : not implemented */
363be49c
JM		 1699 spr_register(env, SPR_BOOKE_PID2, "PID2",
1700 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1701 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1702 0x00000000);
1703 }
578bb252 1704 /* XXX : not implemented */
65f9ee8d 1705 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, SPR_NOACCESS,
1708 0x00000000); /* TOFIX */
363be49c
JM		 1709 switch (env->nb_ways) {
1710 case 4:
1711 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, SPR_NOACCESS,
01662f3e 1714 tlbncfg[3]);
363be49c
JM		 1715 /* Fallthru */
1716 case 3:
1717 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_generic, SPR_NOACCESS,
01662f3e 1720 tlbncfg[2]);
363be49c
JM		 1721 /* Fallthru */
1722 case 2:
1723 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
01662f3e 1726 tlbncfg[1]);
363be49c
JM		 1727 /* Fallthru */
1728 case 1:
1729 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, SPR_NOACCESS,
01662f3e 1732 tlbncfg[0]);
363be49c
JM		 1733 /* Fallthru */
1734 case 0:
1735 default:
1736 break;
1737 }
f2e63a42 1738#endif
01662f3e
AG		 1739
1740 gen_spr_usprgh(env);
363be49c
JM		 1741}
1742
76a66253
JM		 1743/* SPR specific to PowerPC 440 implementation */
1744static void gen_spr_440 (CPUPPCState *env)
1745{
1746 /* Cache control */
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_DNV0, "DNV0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_DNV1, "DNV1",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_440_DNV2, "DNV2",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_440_DNV3, "DNV3",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
2662a059 1768 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
2662a059 1773 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
2662a059 1778 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* XXX : not implemented */
2662a059 1783 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 /* XXX : not implemented */
1788 spr_register(env, SPR_440_DVLIM, "DVLIM",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 /* XXX : not implemented */
1793 spr_register(env, SPR_440_INV0, "INV0",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797 /* XXX : not implemented */
1798 spr_register(env, SPR_440_INV1, "INV1",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 /* XXX : not implemented */
1803 spr_register(env, SPR_440_INV2, "INV2",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807 /* XXX : not implemented */
1808 spr_register(env, SPR_440_INV3, "INV3",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812 /* XXX : not implemented */
2662a059 1813 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 /* XXX : not implemented */
2662a059 1818 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* XXX : not implemented */
2662a059 1823 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 /* XXX : not implemented */
2662a059 1828 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_440_IVLIM, "IVLIM",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 /* Cache debug */
1838 /* XXX : not implemented */
2662a059 1839 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, SPR_NOACCESS,
1842 0x00000000);
1843 /* XXX : not implemented */
2662a059 1844 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, SPR_NOACCESS,
1847 0x00000000);
1848 /* XXX : not implemented */
2662a059 1849 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, SPR_NOACCESS,
1852 0x00000000);
1853 /* XXX : not implemented */
2662a059 1854 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, SPR_NOACCESS,
1857 0x00000000);
1858 /* XXX : not implemented */
2662a059 1859 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1860 SPR_NOACCESS, SPR_NOACCESS,
1861 &spr_read_generic, SPR_NOACCESS,
1862 0x00000000);
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_440_DBDR, "DBDR",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_generic,
1867 0x00000000);
1868 /* Processor control */
1869 spr_register(env, SPR_4xx_CCR0, "CCR0",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, SPR_NOACCESS,
1876 0x00000000);
1877 /* Storage control */
1878 spr_register(env, SPR_440_MMUCR, "MMUCR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882}
1883
1884/* SPR shared between PowerPC 40x implementations */
1885static void gen_spr_40x (CPUPPCState *env)
1886{
1887 /* Cache */
5cbdb3a3 1888 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1889 spr_register(env, SPR_40x_DCCR, "DCCR",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
1892 0x00000000);
5cbdb3a3 1893 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1894 spr_register(env, SPR_40x_ICCR, "ICCR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
5cbdb3a3 1898 /* not emulated, as QEMU do not emulate caches */
2662a059 1899 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, SPR_NOACCESS,
1902 0x00000000);
76a66253
JM		 1903 /* Exception */
1904 spr_register(env, SPR_40x_DEAR, "DEAR",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 spr_register(env, SPR_40x_ESR, "ESR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 spr_register(env, SPR_40x_EVPR, "EVPR",
1913 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1914 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1915 0x00000000);
1916 spr_register(env, SPR_40x_SRR2, "SRR2",
1917 &spr_read_generic, &spr_write_generic,
1918 &spr_read_generic, &spr_write_generic,
1919 0x00000000);
1920 spr_register(env, SPR_40x_SRR3, "SRR3",
1921 &spr_read_generic, &spr_write_generic,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* Timers */
1925 spr_register(env, SPR_40x_PIT, "PIT",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_40x_pit, &spr_write_40x_pit,
1928 0x00000000);
1929 spr_register(env, SPR_40x_TCR, "TCR",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_booke_tcr,
1932 0x00000000);
1933 spr_register(env, SPR_40x_TSR, "TSR",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_booke_tsr,
1936 0x00000000);
2662a059
JM		 1937}
1938
1939/* SPR specific to PowerPC 405 implementation */
1940static void gen_spr_405 (CPUPPCState *env)
1941{
1942 /* MMU */
1943 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
2662a059 1947 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1950 0x00700000);
1951 /* Debug interface */
76a66253
JM		 1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1954 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1955 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1956 0x00000000);
1957 /* XXX : not implemented */
2662a059
JM		 1958 spr_register(env, SPR_405_DBCR1, "DBCR1",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
1962 /* XXX : not implemented */
76a66253
JM		 1963 spr_register(env, SPR_40x_DBSR, "DBSR",
1964 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1965 &spr_read_generic, &spr_write_clear,
1966 /* Last reset was system reset */
76a66253
JM		 1967 0x00000300);
1968 /* XXX : not implemented */
2662a059 1969 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, &spr_write_generic,
1972 0x00000000);
2662a059 1973 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_generic,
1976 0x00000000);
2662a059
JM		 1977 /* XXX : not implemented */
1978 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
2662a059 1981 0x00000000);
76a66253 1982 /* XXX : not implemented */
2662a059 1983 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
2662a059 1988 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
2662a059 1992 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_405_IAC3, "IAC3",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_405_IAC4, "IAC4",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* Storage control */
035feb88 2007 /* XXX: TODO: not implemented */
76a66253
JM		 2008 spr_register(env, SPR_405_SLER, "SLER",
2009 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 2010 &spr_read_generic, &spr_write_40x_sler,
76a66253 2011 0x00000000);
2662a059
JM		 2012 spr_register(env, SPR_40x_ZPR, "ZPR",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
76a66253
JM		 2016 /* XXX : not implemented */
2017 spr_register(env, SPR_405_SU0R, "SU0R",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* SPRG */
2022 spr_register(env, SPR_USPRG0, "USPRG0",
2023 &spr_read_ureg, SPR_NOACCESS,
2024 &spr_read_ureg, SPR_NOACCESS,
2025 0x00000000);
2026 spr_register(env, SPR_SPRG4, "SPRG4",
2027 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2028 &spr_read_generic, &spr_write_generic,
76a66253 2029 0x00000000);
76a66253
JM		 2030 spr_register(env, SPR_SPRG5, "SPRG5",
2031 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2032 spr_read_generic, &spr_write_generic,
76a66253 2033 0x00000000);
76a66253
JM		 2034 spr_register(env, SPR_SPRG6, "SPRG6",
2035 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2036 spr_read_generic, &spr_write_generic,
76a66253 2037 0x00000000);
76a66253
JM		 2038 spr_register(env, SPR_SPRG7, "SPRG7",
2039 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2040 spr_read_generic, &spr_write_generic,
76a66253 2041 0x00000000);
80d11f44 2042 gen_spr_usprgh(env);
76a66253
JM		 2043}
2044
2045/* SPR shared between PowerPC 401 & 403 implementations */
2046static void gen_spr_401_403 (CPUPPCState *env)
2047{
2048 /* Time base */
2049 spr_register(env, SPR_403_VTBL, "TBL",
2050 &spr_read_tbl, SPR_NOACCESS,
2051 &spr_read_tbl, SPR_NOACCESS,
2052 0x00000000);
2053 spr_register(env, SPR_403_TBL, "TBL",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 SPR_NOACCESS, &spr_write_tbl,
2056 0x00000000);
2057 spr_register(env, SPR_403_VTBU, "TBU",
2058 &spr_read_tbu, SPR_NOACCESS,
2059 &spr_read_tbu, SPR_NOACCESS,
2060 0x00000000);
2061 spr_register(env, SPR_403_TBU, "TBU",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 SPR_NOACCESS, &spr_write_tbu,
2064 0x00000000);
2065 /* Debug */
5cbdb3a3 2066 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2067 spr_register(env, SPR_403_CDBCR, "CDBCR",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
2071}
2072
2662a059
JM		 2073/* SPR specific to PowerPC 401 implementation */
2074static void gen_spr_401 (CPUPPCState *env)
2075{
2076 /* Debug interface */
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_DBCR0, "DBCR",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_40x_dbcr0,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_40x_DBSR, "DBSR",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_clear,
2086 /* Last reset was system reset */
2087 0x00000300);
2088 /* XXX : not implemented */
2089 spr_register(env, SPR_40x_DAC1, "DAC",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0x00000000);
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_40x_IAC1, "IAC",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 /* Storage control */
035feb88 2099 /* XXX: TODO: not implemented */
2662a059
JM		 2100 spr_register(env, SPR_405_SLER, "SLER",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_40x_sler,
2103 0x00000000);
5cbdb3a3 2104 /* not emulated, as QEMU never does speculative access */
035feb88
JM		 2105 spr_register(env, SPR_40x_SGR, "SGR",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0xFFFFFFFF);
5cbdb3a3 2109 /* not emulated, as QEMU do not emulate caches */
035feb88
JM		 2110 spr_register(env, SPR_40x_DCWR, "DCWR",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2662a059
JM		 2114}
2115
a750fc0b
JM		 2116static void gen_spr_401x2 (CPUPPCState *env)
2117{
2118 gen_spr_401(env);
2119 spr_register(env, SPR_40x_PID, "PID",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 spr_register(env, SPR_40x_ZPR, "ZPR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127}
2128
76a66253
JM		 2129/* SPR specific to PowerPC 403 implementation */
2130static void gen_spr_403 (CPUPPCState *env)
2131{
2662a059
JM		 2132 /* Debug interface */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_40x_dbcr0,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_40x_DBSR, "DBSR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_clear,
2142 /* Last reset was system reset */
2143 0x00000300);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_40x_DAC1, "DAC1",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
578bb252 2149 /* XXX : not implemented */
2662a059
JM		 2150 spr_register(env, SPR_40x_DAC2, "DAC2",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_40x_IAC1, "IAC1",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
578bb252 2159 /* XXX : not implemented */
2662a059
JM		 2160 spr_register(env, SPR_40x_IAC2, "IAC2",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
a750fc0b
JM		 2164}
2165
2166static void gen_spr_403_real (CPUPPCState *env)
2167{
76a66253
JM		 2168 spr_register(env, SPR_403_PBL1, "PBL1",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_403_pbr, &spr_write_403_pbr,
2171 0x00000000);
2172 spr_register(env, SPR_403_PBU1, "PBU1",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_403_pbr, &spr_write_403_pbr,
2175 0x00000000);
2176 spr_register(env, SPR_403_PBL2, "PBL2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_403_pbr, &spr_write_403_pbr,
2179 0x00000000);
2180 spr_register(env, SPR_403_PBU2, "PBU2",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_403_pbr, &spr_write_403_pbr,
2183 0x00000000);
a750fc0b
JM		 2184}
2185
2186static void gen_spr_403_mmu (CPUPPCState *env)
2187{
2188 /* MMU */
2189 spr_register(env, SPR_40x_PID, "PID",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2662a059 2193 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197}
2198
2199/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2200static void gen_spr_compress (CPUPPCState *env)
2201{
578bb252 2202 /* XXX : not implemented */
76a66253
JM		 2203 spr_register(env, SPR_401_SKR, "SKR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207}
a750fc0b 2208
80d11f44 2209static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2210{
80d11f44 2211 /* Exception processing */
d67d40ea
DG		 2212 spr_register_kvm(env, SPR_DSISR, "DSISR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 KVM_REG_PPC_DSISR, 0x00000000);
2216 spr_register_kvm(env, SPR_DAR, "DAR",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 KVM_REG_PPC_DAR, 0x00000000);
80d11f44
JM		 2220 /* Timer */
2221 spr_register(env, SPR_DECR, "DECR",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_decr, &spr_write_decr,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_MPC_EIE, "EIE",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
2230 /* XXX : not implemented */
2231 spr_register(env, SPR_MPC_EID, "EID",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_MPC_NRI, "NRI",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_MPC_CMPA, "CMPA",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_MPC_CMPB, "CMPB",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_MPC_CMPC, "CMPC",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_MPC_CMPD, "CMPD",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_MPC_ECR, "ECR",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_MPC_DER, "DER",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* XXX : not implemented */
2281 spr_register(env, SPR_MPC_CMPE, "CMPE",
2282 SPR_NOACCESS, SPR_NOACCESS,
2283 &spr_read_generic, &spr_write_generic,
2284 0x00000000);
2285 /* XXX : not implemented */
2286 spr_register(env, SPR_MPC_CMPF, "CMPF",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 /* XXX : not implemented */
2291 spr_register(env, SPR_MPC_CMPG, "CMPG",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* XXX : not implemented */
2296 spr_register(env, SPR_MPC_CMPH, "CMPH",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0x00000000);
2300 /* XXX : not implemented */
2301 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 /* XXX : not implemented */
2306 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_MPC_BAR, "BAR",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_generic,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_DPDR, "DPDR",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_IMMR, "IMMR",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325}
2326
2327static void gen_spr_5xx (CPUPPCState *env)
2328{
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* XXX : not implemented */
2335 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0x00000000);
2339 /* XXX : not implemented */
2340 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* XXX : not implemented */
2360 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_generic, &spr_write_generic,
2363 0x00000000);
2364 /* XXX : not implemented */
2365 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369 /* XXX : not implemented */
2370 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374 /* XXX : not implemented */
2375 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2393 0x00000000);
2394 /* XXX : not implemented */
2395 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2396 SPR_NOACCESS, SPR_NOACCESS,
2397 &spr_read_generic, &spr_write_generic,
2398 0x00000000);
2399 /* XXX : not implemented */
2400 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2401 SPR_NOACCESS, SPR_NOACCESS,
2402 &spr_read_generic, &spr_write_generic,
2403 0x00000000);
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 /* XXX : not implemented */
2410 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 0x00000000);
2414 /* XXX : not implemented */
2415 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_generic, &spr_write_generic,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434}
2435
2436static void gen_spr_8xx (CPUPPCState *env)
2437{
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 /* XXX : not implemented */
2459 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463 /* XXX : not implemented */
2464 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* XXX : not implemented */
2469 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 /* XXX : not implemented */
2474 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_generic, &spr_write_generic,
2477 0x00000000);
2478 /* XXX : not implemented */
2479 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 0x00000000);
2483 /* XXX : not implemented */
2484 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2485 SPR_NOACCESS, SPR_NOACCESS,
2486 &spr_read_generic, &spr_write_generic,
2487 0x00000000);
2488 /* XXX : not implemented */
2489 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2490 SPR_NOACCESS, SPR_NOACCESS,
2491 &spr_read_generic, &spr_write_generic,
2492 0x00000000);
2493 /* XXX : not implemented */
2494 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2495 SPR_NOACCESS, SPR_NOACCESS,
2496 &spr_read_generic, &spr_write_generic,
2497 0x00000000);
2498 /* XXX : not implemented */
2499 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2500 SPR_NOACCESS, SPR_NOACCESS,
2501 &spr_read_generic, &spr_write_generic,
2502 0x00000000);
2503 /* XXX : not implemented */
2504 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2505 SPR_NOACCESS, SPR_NOACCESS,
2506 &spr_read_generic, &spr_write_generic,
2507 0x00000000);
2508 /* XXX : not implemented */
2509 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2510 SPR_NOACCESS, SPR_NOACCESS,
2511 &spr_read_generic, &spr_write_generic,
2512 0x00000000);
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563}
2564
2565// XXX: TODO
2566/*
2567 * AMR => SPR 29 (Power 2.04)
2568 * CTRL => SPR 136 (Power 2.04)
2569 * CTRL => SPR 152 (Power 2.04)
2570 * SCOMC => SPR 276 (64 bits ?)
2571 * SCOMD => SPR 277 (64 bits ?)
2572 * TBU40 => SPR 286 (Power 2.04 hypv)
2573 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2574 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2575 * HDSISR => SPR 306 (Power 2.04 hypv)
2576 * HDAR => SPR 307 (Power 2.04 hypv)
2577 * PURR => SPR 309 (Power 2.04 hypv)
2578 * HDEC => SPR 310 (Power 2.04 hypv)
2579 * HIOR => SPR 311 (hypv)
2580 * RMOR => SPR 312 (970)
2581 * HRMOR => SPR 313 (Power 2.04 hypv)
2582 * HSRR0 => SPR 314 (Power 2.04 hypv)
2583 * HSRR1 => SPR 315 (Power 2.04 hypv)
80d11f44 2584 * LPIDR => SPR 317 (970)
80d11f44
JM		 2585 * EPR => SPR 702 (Power 2.04 emb)
2586 * perf => 768-783 (Power 2.04)
2587 * perf => 784-799 (Power 2.04)
2588 * PPR => SPR 896 (Power 2.04)
2589 * EPLC => SPR 947 (Power 2.04 emb)
2590 * EPSC => SPR 948 (Power 2.04 emb)
2591 * DABRX => 1015 (Power 2.04 hypv)
2592 * FPECR => SPR 1022 (?)
2593 * ... and more (thermal management, performance counters, ...)
2594 */
2595
2596/*****************************************************************************/
2597/* Exception vectors models */
2598static void init_excp_4xx_real (CPUPPCState *env)
2599{
2600#if !defined(CONFIG_USER_ONLY)
2601 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2602 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2603 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2604 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2605 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2606 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2607 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2608 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2609 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2610 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
80d11f44 2611 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2612 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2613 /* Hardware reset vector */
2614 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2615#endif
2616}
2617
80d11f44
JM		 2618static void init_excp_4xx_softmmu (CPUPPCState *env)
2619{
2620#if !defined(CONFIG_USER_ONLY)
2621 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2622 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2623 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2624 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2625 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2626 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2627 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2628 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2629 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2630 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2631 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2632 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2633 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2634 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
80d11f44
JM		 2635 env->ivor_mask = 0x0000FFF0UL;
2636 env->ivpr_mask = 0xFFFF0000UL;
2637 /* Hardware reset vector */
2638 env->hreset_vector = 0xFFFFFFFCUL;
2639#endif
2640}
2641
2642static void init_excp_MPC5xx (CPUPPCState *env)
2643{
2644#if !defined(CONFIG_USER_ONLY)
2645 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2646 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2647 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2648 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2649 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2650 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2651 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2652 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2653 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2654 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2655 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2656 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2657 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2658 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2659 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
80d11f44
JM		 2660 env->ivor_mask = 0x0000FFF0UL;
2661 env->ivpr_mask = 0xFFFF0000UL;
2662 /* Hardware reset vector */
09d9828a 2663 env->hreset_vector = 0x00000100UL;
80d11f44
JM		 2664#endif
2665}
2666
2667static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2668{
2669#if !defined(CONFIG_USER_ONLY)
2670 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2671 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2672 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2673 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2674 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2675 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2676 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2677 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2678 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2680 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2681 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2682 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2683 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2684 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2685 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2686 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2687 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2688 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2689 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2690 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
80d11f44
JM		 2691 env->ivor_mask = 0x0000FFF0UL;
2692 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2693 /* Hardware reset vector */
09d9828a 2694 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2695#endif
2696}
2697
80d11f44 2698static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2699{
2700#if !defined(CONFIG_USER_ONLY)
2701 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2702 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2703 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2704 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2705 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2706 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2707 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2708 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2709 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2710 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2711 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2712 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2713 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2714 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2715 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2716 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2717 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44 2718 /* Hardware reset vector */
09d9828a 2719 env->hreset_vector = 0x00000100UL;
80d11f44
JM		 2720#endif
2721}
2722
e9cd84b9 2723static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
80d11f44
JM		 2724{
2725#if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2727 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
80d11f44 2746 env->ivor_mask = 0x0000FFF7UL;
e9cd84b9 2747 env->ivpr_mask = ivpr_mask;
80d11f44
JM		 2748 /* Hardware reset vector */
2749 env->hreset_vector = 0xFFFFFFFCUL;
2750#endif
2751}
2752
2753static void init_excp_BookE (CPUPPCState *env)
2754{
2755#if !defined(CONFIG_USER_ONLY)
2756 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2763 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2765 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
80d11f44
JM		 2772 env->ivor_mask = 0x0000FFE0UL;
2773 env->ivpr_mask = 0xFFFF0000UL;
2774 /* Hardware reset vector */
2775 env->hreset_vector = 0xFFFFFFFCUL;
2776#endif
2777}
2778
2779static void init_excp_601 (CPUPPCState *env)
2780{
2781#if !defined(CONFIG_USER_ONLY)
2782 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2783 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2784 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2785 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2786 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2787 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2788 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2789 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2790 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2791 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2792 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2793 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
1c27f8fb 2794 /* Hardware reset vector */
80d11f44 2795 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2796#endif
2797}
2798
80d11f44 2799static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2800{
2801#if !defined(CONFIG_USER_ONLY)
082c6681 2802 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2803 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2804 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2805 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2806 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2807 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2808 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2809 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2810 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2811 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2812 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2813 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2814 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2815 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2816 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2817 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2818 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2819 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2820 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
1c27f8fb 2821 /* Hardware reset vector */
09d9828a 2822 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2823#endif
2824}
2825
80d11f44 2826static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2827{
2828#if !defined(CONFIG_USER_ONLY)
2829 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2831 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2832 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2833 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2834 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2835 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2836 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2837 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2838 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2839 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2840 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2841 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2842 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2843 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2844 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb 2845 /* Hardware reset vector */
09d9828a 2846 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2847#endif
2848}
2849
2850static void init_excp_604 (CPUPPCState *env)
2851{
2852#if !defined(CONFIG_USER_ONLY)
2853 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2861 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2862 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2863 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2864 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2865 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2866 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb 2867 /* Hardware reset vector */
2d3eb7bf 2868 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2869#endif
2870}
2871
e1833e1f
JM		 2872static void init_excp_7x0 (CPUPPCState *env)
2873{
2874#if !defined(CONFIG_USER_ONLY)
2875 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2883 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2884 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2885 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2886 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2887 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 2888 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 2889 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 2890 /* Hardware reset vector */
09d9828a 2891 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2892#endif
2893}
2894
bd928eba 2895static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 2896{
2897#if !defined(CONFIG_USER_ONLY)
2898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2899 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2900 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2901 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2902 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2903 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2904 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2905 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2906 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2908 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2909 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 2912 /* Hardware reset vector */
09d9828a 2913 env->hreset_vector = 0x00000100UL;
bd928eba
JM		 2914#endif
2915}
2916
2917static void init_excp_750cx (CPUPPCState *env)
2918{
2919#if !defined(CONFIG_USER_ONLY)
2920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2921 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2922 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2923 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2924 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2925 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2926 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2927 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2930 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2931 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2932 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 2933 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 2934 /* Hardware reset vector */
09d9828a 2935 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2936#endif
2937}
2938
7a3a6927
JM		 2939/* XXX: Check if this is correct */
2940static void init_excp_7x5 (CPUPPCState *env)
2941{
2942#if !defined(CONFIG_USER_ONLY)
2943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 2955 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2956 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2957 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 2958 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2959 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 2960 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
7a3a6927 2961 /* Hardware reset vector */
09d9828a 2962 env->hreset_vector = 0x00000100UL;
7a3a6927
JM		 2963#endif
2964}
2965
e1833e1f
JM		 2966static void init_excp_7400 (CPUPPCState *env)
2967{
2968#if !defined(CONFIG_USER_ONLY)
2969 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2970 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2971 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2972 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2980 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2981 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2984 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2985 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 2986 /* Hardware reset vector */
09d9828a 2987 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2988#endif
2989}
2990
e1833e1f
JM		 2991static void init_excp_7450 (CPUPPCState *env)
2992{
2993#if !defined(CONFIG_USER_ONLY)
2994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3006 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3007 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3008 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3009 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3010 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3011 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3012 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb 3013 /* Hardware reset vector */
09d9828a 3014 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3015#endif
3016}
e1833e1f
JM		 3017
3018#if defined (TARGET_PPC64)
3019static void init_excp_970 (CPUPPCState *env)
3020{
3021#if !defined(CONFIG_USER_ONLY)
3022 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3023 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3024 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3025 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3026 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3027 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3033 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3034 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3035 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3036 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3037 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3038 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3039 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3040 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3041 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 3042 /* Hardware reset vector */
3043 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3044#endif
3045}
9d52e907
DG		 3046
3047static void init_excp_POWER7 (CPUPPCState *env)
3048{
3049#if !defined(CONFIG_USER_ONLY)
3050 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3051 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3052 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3053 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3054 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3055 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3056 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3057 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3058 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3059 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3060 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3061 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3062 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3063 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3064 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3065 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1f29871c 3066 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
9d52e907
DG		 3067 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3068 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3069 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3070 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
9d52e907
DG		 3071 /* Hardware reset vector */
3072 env->hreset_vector = 0x0000000000000100ULL;
3073#endif
3074}
e1833e1f
JM		 3075#endif
3076
2f462816
JM		 3077/*****************************************************************************/
3078/* Power management enable checks */
3079static int check_pow_none (CPUPPCState *env)
3080{
3081 return 0;
3082}
3083
3084static int check_pow_nocheck (CPUPPCState *env)
3085{
3086 return 1;
3087}
3088
3089static int check_pow_hid0 (CPUPPCState *env)
3090{
3091 if (env->spr[SPR_HID0] & 0x00E00000)
3092 return 1;
3093
3094 return 0;
3095}
3096
4e777442
JM		 3097static int check_pow_hid0_74xx (CPUPPCState *env)
3098{
3099 if (env->spr[SPR_HID0] & 0x00600000)
3100 return 1;
3101
3102 return 0;
3103}
3104
a750fc0b
JM		 3105/*****************************************************************************/
3106/* PowerPC implementations definitions */
76a66253 3107
7856e3a4
AF		 3108#define POWERPC_FAMILY(_name) \
3109 static void \
3110 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3111 \
3112 static const TypeInfo \
3113 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3114 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3115 .parent = TYPE_POWERPC_CPU, \
3116 .abstract = true, \
3117 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3118 }; \
3119 \
3120 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3121 { \
3122 type_register_static( \
3123 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3124 } \
3125 \
3126 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3127 \
3128 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3129
a750fc0b
JM		 3130static void init_proc_401 (CPUPPCState *env)
3131{
3132 gen_spr_40x(env);
3133 gen_spr_401_403(env);
3134 gen_spr_401(env);
e1833e1f 3135 init_excp_4xx_real(env);
d63001d1
JM		 3136 env->dcache_line_size = 32;
3137 env->icache_line_size = 32;
4e290a0b
JM		 3138 /* Allocate hardware IRQ controller */
3139 ppc40x_irq_init(env);
ddd1055b
FC		 3140
3141 SET_FIT_PERIOD(12, 16, 20, 24);
3142 SET_WDT_PERIOD(16, 20, 24, 28);
a750fc0b 3143}
76a66253 3144
7856e3a4
AF		 3145POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3146{
ca5dff0a 3147 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3149
ca5dff0a 3150 dc->desc = "PowerPC 401";
7856e3a4
AF		 3151 pcc->init_proc = init_proc_401;
3152 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3153 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3154 PPC_WRTEE | PPC_DCR |
3155 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3156 PPC_CACHE_DCBZ |
3157 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3158 PPC_4xx_COMMON | PPC_40x_EXCP;
ba9fd9f1
AF		 3159 pcc->msr_mask = 0x00000000000FD201ULL;
3160 pcc->mmu_model = POWERPC_MMU_REAL;
3161 pcc->excp_model = POWERPC_EXCP_40x;
3162 pcc->bus_model = PPC_FLAGS_INPUT_401;
3163 pcc->bfd_mach = bfd_mach_ppc_403;
3164 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3165 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3166}
3167
a750fc0b
JM		 3168static void init_proc_401x2 (CPUPPCState *env)
3169{
3170 gen_spr_40x(env);
3171 gen_spr_401_403(env);
3172 gen_spr_401x2(env);
3173 gen_spr_compress(env);
a750fc0b 3174 /* Memory management */
f2e63a42 3175#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3176 env->nb_tlb = 64;
3177 env->nb_ways = 1;
3178 env->id_tlbs = 0;
1c53accc 3179 env->tlb_type = TLB_EMB;
f2e63a42 3180#endif
e1833e1f 3181 init_excp_4xx_softmmu(env);
d63001d1
JM		 3182 env->dcache_line_size = 32;
3183 env->icache_line_size = 32;
4e290a0b
JM		 3184 /* Allocate hardware IRQ controller */
3185 ppc40x_irq_init(env);
ddd1055b
FC		 3186
3187 SET_FIT_PERIOD(12, 16, 20, 24);
3188 SET_WDT_PERIOD(16, 20, 24, 28);
76a66253
JM		 3189}
3190
7856e3a4
AF		 3191POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3192{
ca5dff0a 3193 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3194 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3195
ca5dff0a 3196 dc->desc = "PowerPC 401x2";
7856e3a4
AF		 3197 pcc->init_proc = init_proc_401x2;
3198 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3199 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3200 PPC_DCR | PPC_WRTEE |
3201 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3202 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3203 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3204 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3205 PPC_4xx_COMMON | PPC_40x_EXCP;
ba9fd9f1
AF		 3206 pcc->msr_mask = 0x00000000001FD231ULL;
3207 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3208 pcc->excp_model = POWERPC_EXCP_40x;
3209 pcc->bus_model = PPC_FLAGS_INPUT_401;
3210 pcc->bfd_mach = bfd_mach_ppc_403;
3211 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3212 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3213}
3214
e1833e1f 3215static void init_proc_401x3 (CPUPPCState *env)
76a66253 3216{
4e290a0b
JM		 3217 gen_spr_40x(env);
3218 gen_spr_401_403(env);
3219 gen_spr_401(env);
3220 gen_spr_401x2(env);
3221 gen_spr_compress(env);
e1833e1f 3222 init_excp_4xx_softmmu(env);
d63001d1
JM		 3223 env->dcache_line_size = 32;
3224 env->icache_line_size = 32;
4e290a0b
JM		 3225 /* Allocate hardware IRQ controller */
3226 ppc40x_irq_init(env);
ddd1055b
FC		 3227
3228 SET_FIT_PERIOD(12, 16, 20, 24);
3229 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082 3230}
a750fc0b 3231
7856e3a4
AF		 3232POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3233{
ca5dff0a 3234 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3235 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3236
ca5dff0a 3237 dc->desc = "PowerPC 401x3";
7856e3a4
AF		 3238 pcc->init_proc = init_proc_401x3;
3239 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3240 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3241 PPC_DCR | PPC_WRTEE |
3242 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3243 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3244 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3245 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3246 PPC_4xx_COMMON | PPC_40x_EXCP;
ba9fd9f1
AF		 3247 pcc->msr_mask = 0x00000000001FD631ULL;
3248 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3249 pcc->excp_model = POWERPC_EXCP_40x;
3250 pcc->bus_model = PPC_FLAGS_INPUT_401;
3251 pcc->bfd_mach = bfd_mach_ppc_403;
3252 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3253 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3254}
3255
a750fc0b 3256static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3257{
a750fc0b
JM		 3258 gen_spr_40x(env);
3259 gen_spr_401_403(env);
3260 gen_spr_401x2(env);
3261 gen_spr_compress(env);
a750fc0b 3262 /* Memory management */
f2e63a42 3263#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3264 env->nb_tlb = 64;
3265 env->nb_ways = 1;
3266 env->id_tlbs = 0;
1c53accc 3267 env->tlb_type = TLB_EMB;
f2e63a42 3268#endif
e1833e1f 3269 init_excp_4xx_softmmu(env);
d63001d1
JM		 3270 env->dcache_line_size = 32;
3271 env->icache_line_size = 32;
4e290a0b
JM		 3272 /* Allocate hardware IRQ controller */
3273 ppc40x_irq_init(env);
ddd1055b
FC		 3274
3275 SET_FIT_PERIOD(8, 12, 16, 20);
3276 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3277}
3278
7856e3a4
AF		 3279POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3280{
ca5dff0a 3281 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3282 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3283
ca5dff0a 3284 dc->desc = "IOP480";
7856e3a4
AF		 3285 pcc->init_proc = init_proc_IOP480;
3286 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3287 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3288 PPC_DCR | PPC_WRTEE |
3289 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3290 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3291 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3292 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3293 PPC_4xx_COMMON | PPC_40x_EXCP;
ba9fd9f1
AF		 3294 pcc->msr_mask = 0x00000000001FD231ULL;
3295 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3296 pcc->excp_model = POWERPC_EXCP_40x;
3297 pcc->bus_model = PPC_FLAGS_INPUT_401;
3298 pcc->bfd_mach = bfd_mach_ppc_403;
3299 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3300 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3301}
3302
a750fc0b 3303static void init_proc_403 (CPUPPCState *env)
3fc6c082 3304{
a750fc0b
JM		 3305 gen_spr_40x(env);
3306 gen_spr_401_403(env);
3307 gen_spr_403(env);
3308 gen_spr_403_real(env);
e1833e1f 3309 init_excp_4xx_real(env);
d63001d1
JM		 3310 env->dcache_line_size = 32;
3311 env->icache_line_size = 32;
4e290a0b
JM		 3312 /* Allocate hardware IRQ controller */
3313 ppc40x_irq_init(env);
ddd1055b
FC		 3314
3315 SET_FIT_PERIOD(8, 12, 16, 20);
3316 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3317}
3318
7856e3a4
AF		 3319POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3320{
ca5dff0a 3321 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3322 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3323
ca5dff0a 3324 dc->desc = "PowerPC 403";
7856e3a4
AF		 3325 pcc->init_proc = init_proc_403;
3326 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3327 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3328 PPC_DCR | PPC_WRTEE |
3329 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3330 PPC_CACHE_DCBZ |
3331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3332 PPC_4xx_COMMON | PPC_40x_EXCP;
ba9fd9f1
AF		 3333 pcc->msr_mask = 0x000000000007D00DULL;
3334 pcc->mmu_model = POWERPC_MMU_REAL;
3335 pcc->excp_model = POWERPC_EXCP_40x;
3336 pcc->bus_model = PPC_FLAGS_INPUT_401;
3337 pcc->bfd_mach = bfd_mach_ppc_403;
3338 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3339 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3340}
3341
a750fc0b 3342static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3343{
a750fc0b
JM		 3344 gen_spr_40x(env);
3345 gen_spr_401_403(env);
3346 gen_spr_403(env);
3347 gen_spr_403_real(env);
3348 gen_spr_403_mmu(env);
3349 /* Bus access control */
5cbdb3a3 3350 /* not emulated, as QEMU never does speculative access */
a750fc0b
JM		 3351 spr_register(env, SPR_40x_SGR, "SGR",
3352 SPR_NOACCESS, SPR_NOACCESS,
3353 &spr_read_generic, &spr_write_generic,
3354 0xFFFFFFFF);
5cbdb3a3 3355 /* not emulated, as QEMU do not emulate caches */
a750fc0b
JM		 3356 spr_register(env, SPR_40x_DCWR, "DCWR",
3357 SPR_NOACCESS, SPR_NOACCESS,
3358 &spr_read_generic, &spr_write_generic,
3359 0x00000000);
3360 /* Memory management */
f2e63a42 3361#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3362 env->nb_tlb = 64;
3363 env->nb_ways = 1;
3364 env->id_tlbs = 0;
1c53accc 3365 env->tlb_type = TLB_EMB;
f2e63a42 3366#endif
80d11f44
JM		 3367 init_excp_4xx_softmmu(env);
3368 env->dcache_line_size = 32;
3369 env->icache_line_size = 32;
3370 /* Allocate hardware IRQ controller */
3371 ppc40x_irq_init(env);
ddd1055b
FC		 3372
3373 SET_FIT_PERIOD(8, 12, 16, 20);
3374 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3375}
3376
7856e3a4
AF		 3377POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3378{
ca5dff0a 3379 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3381
ca5dff0a 3382 dc->desc = "PowerPC 403 GCX";
7856e3a4
AF		 3383 pcc->init_proc = init_proc_403GCX;
3384 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3386 PPC_DCR | PPC_WRTEE |
3387 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3388 PPC_CACHE_DCBZ |
3389 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3390 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3391 PPC_4xx_COMMON | PPC_40x_EXCP;
ba9fd9f1
AF		 3392 pcc->msr_mask = 0x000000000007D00DULL;
3393 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3394 pcc->excp_model = POWERPC_EXCP_40x;
3395 pcc->bus_model = PPC_FLAGS_INPUT_401;
3396 pcc->bfd_mach = bfd_mach_ppc_403;
3397 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3398 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3399}
3400
80d11f44
JM		 3401static void init_proc_405 (CPUPPCState *env)
3402{
3403 /* Time base */
3404 gen_tbl(env);
3405 gen_spr_40x(env);
3406 gen_spr_405(env);
3407 /* Bus access control */
5cbdb3a3 3408 /* not emulated, as QEMU never does speculative access */
80d11f44
JM		 3409 spr_register(env, SPR_40x_SGR, "SGR",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0xFFFFFFFF);
5cbdb3a3 3413 /* not emulated, as QEMU do not emulate caches */
80d11f44
JM		 3414 spr_register(env, SPR_40x_DCWR, "DCWR",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 /* Memory management */
3419#if !defined(CONFIG_USER_ONLY)
3420 env->nb_tlb = 64;
3421 env->nb_ways = 1;
3422 env->id_tlbs = 0;
1c53accc 3423 env->tlb_type = TLB_EMB;
80d11f44
JM		 3424#endif
3425 init_excp_4xx_softmmu(env);
3426 env->dcache_line_size = 32;
3427 env->icache_line_size = 32;
3428 /* Allocate hardware IRQ controller */
3429 ppc40x_irq_init(env);
ddd1055b
FC		 3430
3431 SET_FIT_PERIOD(8, 12, 16, 20);
3432 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3433}
3434
7856e3a4
AF		 3435POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3436{
ca5dff0a 3437 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3438 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3439
ca5dff0a 3440 dc->desc = "PowerPC 405";
7856e3a4
AF		 3441 pcc->init_proc = init_proc_405;
3442 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3443 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3444 PPC_DCR | PPC_WRTEE |
3445 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3446 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3447 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3448 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3449 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
ba9fd9f1
AF		 3450 pcc->msr_mask = 0x000000000006E630ULL;
3451 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3452 pcc->excp_model = POWERPC_EXCP_40x;
3453 pcc->bus_model = PPC_FLAGS_INPUT_405;
3454 pcc->bfd_mach = bfd_mach_ppc_403;
3455 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3456 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3457}
3458
80d11f44
JM		 3459static void init_proc_440EP (CPUPPCState *env)
3460{
3461 /* Time base */
3462 gen_tbl(env);
3463 gen_spr_BookE(env, 0x000000000000FFFFULL);
3464 gen_spr_440(env);
3465 gen_spr_usprgh(env);
3466 /* Processor identification */
3467 spr_register(env, SPR_BOOKE_PIR, "PIR",
3468 SPR_NOACCESS, SPR_NOACCESS,
3469 &spr_read_generic, &spr_write_pir,
3470 0x00000000);
3471 /* XXX : not implemented */
3472 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3473 SPR_NOACCESS, SPR_NOACCESS,
3474 &spr_read_generic, &spr_write_generic,
3475 0x00000000);
3476 /* XXX : not implemented */
3477 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3478 SPR_NOACCESS, SPR_NOACCESS,
3479 &spr_read_generic, &spr_write_generic,
3480 0x00000000);
3481 /* XXX : not implemented */
3482 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3483 SPR_NOACCESS, SPR_NOACCESS,
3484 &spr_read_generic, &spr_write_generic,
3485 0x00000000);
3486 /* XXX : not implemented */
3487 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, &spr_write_generic,
3490 0x00000000);
3491 /* XXX : not implemented */
3492 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0x00000000);
3496 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0x00000000);
3500 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3501 SPR_NOACCESS, SPR_NOACCESS,
3502 &spr_read_generic, &spr_write_generic,
3503 0x00000000);
3504 /* XXX : not implemented */
3505 spr_register(env, SPR_440_CCR1, "CCR1",
3506 SPR_NOACCESS, SPR_NOACCESS,
3507 &spr_read_generic, &spr_write_generic,
3508 0x00000000);
3509 /* Memory management */
3510#if !defined(CONFIG_USER_ONLY)
3511 env->nb_tlb = 64;
3512 env->nb_ways = 1;
3513 env->id_tlbs = 0;
1c53accc 3514 env->tlb_type = TLB_EMB;
80d11f44
JM		 3515#endif
3516 init_excp_BookE(env);
3517 env->dcache_line_size = 32;
3518 env->icache_line_size = 32;
c0a7e81a 3519 ppc40x_irq_init(env);
ddd1055b
FC		 3520
3521 SET_FIT_PERIOD(12, 16, 20, 24);
3522 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3523}
3524
7856e3a4
AF		 3525POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3526{
ca5dff0a 3527 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3528 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3529
ca5dff0a 3530 dc->desc = "PowerPC 440 EP";
7856e3a4
AF		 3531 pcc->init_proc = init_proc_440EP;
3532 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3533 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3534 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3535 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3536 PPC_FLOAT_STFIWX |
3537 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3538 PPC_CACHE | PPC_CACHE_ICBI |
3539 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3540 PPC_MEM_TLBSYNC | PPC_MFTB |
3541 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3542 PPC_440_SPEC;
ba9fd9f1
AF		 3543 pcc->msr_mask = 0x000000000006FF30ULL;
3544 pcc->mmu_model = POWERPC_MMU_BOOKE;
3545 pcc->excp_model = POWERPC_EXCP_BOOKE;
3546 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3547 pcc->bfd_mach = bfd_mach_ppc_403;
3548 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3549 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3550}
3551
80d11f44
JM		 3552static void init_proc_440GP (CPUPPCState *env)
3553{
3554 /* Time base */
3555 gen_tbl(env);
3556 gen_spr_BookE(env, 0x000000000000FFFFULL);
3557 gen_spr_440(env);
3558 gen_spr_usprgh(env);
3559 /* Processor identification */
3560 spr_register(env, SPR_BOOKE_PIR, "PIR",
3561 SPR_NOACCESS, SPR_NOACCESS,
3562 &spr_read_generic, &spr_write_pir,
3563 0x00000000);
3564 /* XXX : not implemented */
3565 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3566 SPR_NOACCESS, SPR_NOACCESS,
3567 &spr_read_generic, &spr_write_generic,
3568 0x00000000);
3569 /* XXX : not implemented */
3570 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3571 SPR_NOACCESS, SPR_NOACCESS,
3572 &spr_read_generic, &spr_write_generic,
3573 0x00000000);
3574 /* XXX : not implemented */
3575 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3576 SPR_NOACCESS, SPR_NOACCESS,
3577 &spr_read_generic, &spr_write_generic,
3578 0x00000000);
3579 /* XXX : not implemented */
3580 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3581 SPR_NOACCESS, SPR_NOACCESS,
3582 &spr_read_generic, &spr_write_generic,
3583 0x00000000);
3584 /* Memory management */
3585#if !defined(CONFIG_USER_ONLY)
3586 env->nb_tlb = 64;
3587 env->nb_ways = 1;
3588 env->id_tlbs = 0;
1c53accc 3589 env->tlb_type = TLB_EMB;
80d11f44
JM		 3590#endif
3591 init_excp_BookE(env);
3592 env->dcache_line_size = 32;
3593 env->icache_line_size = 32;
3594 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3595
3596 SET_FIT_PERIOD(12, 16, 20, 24);
3597 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3598}
3599
7856e3a4
AF		 3600POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3601{
ca5dff0a 3602 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3604
ca5dff0a 3605 dc->desc = "PowerPC 440 GP";
7856e3a4
AF		 3606 pcc->init_proc = init_proc_440GP;
3607 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3609 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3610 PPC_CACHE | PPC_CACHE_ICBI |
3611 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3612 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3613 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3614 PPC_440_SPEC;
ba9fd9f1
AF		 3615 pcc->msr_mask = 0x000000000006FF30ULL;
3616 pcc->mmu_model = POWERPC_MMU_BOOKE;
3617 pcc->excp_model = POWERPC_EXCP_BOOKE;
3618 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3619 pcc->bfd_mach = bfd_mach_ppc_403;
3620 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3621 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3622}
3623
80d11f44
JM		 3624static void init_proc_440x4 (CPUPPCState *env)
3625{
3626 /* Time base */
3627 gen_tbl(env);
3628 gen_spr_BookE(env, 0x000000000000FFFFULL);
3629 gen_spr_440(env);
3630 gen_spr_usprgh(env);
3631 /* Processor identification */
3632 spr_register(env, SPR_BOOKE_PIR, "PIR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_pir,
3635 0x00000000);
3636 /* XXX : not implemented */
3637 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657#if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
1c53accc 3661 env->tlb_type = TLB_EMB;
80d11f44
JM		 3662#endif
3663 init_excp_BookE(env);
d63001d1
JM		 3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
80d11f44 3666 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3670}
3671
7856e3a4
AF		 3672POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3673{
ca5dff0a 3674 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3675 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3676
ca5dff0a 3677 dc->desc = "PowerPC 440x4";
7856e3a4
AF		 3678 pcc->init_proc = init_proc_440x4;
3679 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3680 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3681 PPC_DCR | PPC_WRTEE |
3682 PPC_CACHE | PPC_CACHE_ICBI |
3683 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3684 PPC_MEM_TLBSYNC | PPC_MFTB |
3685 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3686 PPC_440_SPEC;
ba9fd9f1
AF		 3687 pcc->msr_mask = 0x000000000006FF30ULL;
3688 pcc->mmu_model = POWERPC_MMU_BOOKE;
3689 pcc->excp_model = POWERPC_EXCP_BOOKE;
3690 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3691 pcc->bfd_mach = bfd_mach_ppc_403;
3692 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3693 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3694}
3695
80d11f44 3696static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3697{
a750fc0b
JM		 3698 /* Time base */
3699 gen_tbl(env);
80d11f44
JM		 3700 gen_spr_BookE(env, 0x000000000000FFFFULL);
3701 gen_spr_440(env);
3702 gen_spr_usprgh(env);
3703 /* Processor identification */
3704 spr_register(env, SPR_BOOKE_PIR, "PIR",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_pir,
3707 0x00000000);
3708 /* XXX : not implemented */
3709 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3712 0x00000000);
3713 /* XXX : not implemented */
3714 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* XXX : not implemented */
3724 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3738 SPR_NOACCESS, SPR_NOACCESS,
3739 &spr_read_generic, &spr_write_generic,
3740 0x00000000);
3741 /* XXX : not implemented */
3742 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3743 SPR_NOACCESS, SPR_NOACCESS,
3744 &spr_read_generic, &spr_write_generic,
3745 0x00000000);
3746 /* Memory management */
f2e63a42 3747#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3748 env->nb_tlb = 64;
3749 env->nb_ways = 1;
3750 env->id_tlbs = 0;
1c53accc 3751 env->tlb_type = TLB_EMB;
f2e63a42 3752#endif
80d11f44 3753 init_excp_BookE(env);
d63001d1
JM		 3754 env->dcache_line_size = 32;
3755 env->icache_line_size = 32;
95070372 3756 ppc40x_irq_init(env);
ddd1055b
FC		 3757
3758 SET_FIT_PERIOD(12, 16, 20, 24);
3759 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3760}
3761
7856e3a4
AF		 3762POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3763{
ca5dff0a 3764 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3765 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3766
ca5dff0a 3767 dc->desc = "PowerPC 440x5";
7856e3a4
AF		 3768 pcc->init_proc = init_proc_440x5;
3769 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3770 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3771 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3772 PPC_CACHE | PPC_CACHE_ICBI |
3773 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3774 PPC_MEM_TLBSYNC | PPC_MFTB |
3775 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3776 PPC_440_SPEC;
ba9fd9f1
AF		 3777 pcc->msr_mask = 0x000000000006FF30ULL;
3778 pcc->mmu_model = POWERPC_MMU_BOOKE;
3779 pcc->excp_model = POWERPC_EXCP_BOOKE;
3780 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3781 pcc->bfd_mach = bfd_mach_ppc_403;
3782 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3783 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3784}
3785
80d11f44 3786static void init_proc_460 (CPUPPCState *env)
3fc6c082 3787{
a750fc0b
JM		 3788 /* Time base */
3789 gen_tbl(env);
80d11f44 3790 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3791 gen_spr_440(env);
80d11f44
JM		 3792 gen_spr_usprgh(env);
3793 /* Processor identification */
3794 spr_register(env, SPR_BOOKE_PIR, "PIR",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_pir,
3797 0x00000000);
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
3803 /* XXX : not implemented */
3804 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* XXX : not implemented */
3814 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3815 SPR_NOACCESS, SPR_NOACCESS,
3816 &spr_read_generic, &spr_write_generic,
3817 0x00000000);
578bb252 3818 /* XXX : not implemented */
a750fc0b
JM		 3819 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3820 SPR_NOACCESS, SPR_NOACCESS,
3821 &spr_read_generic, &spr_write_generic,
3822 0x00000000);
3823 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, &spr_write_generic,
3826 0x00000000);
3827 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
578bb252 3831 /* XXX : not implemented */
a750fc0b
JM		 3832 spr_register(env, SPR_440_CCR1, "CCR1",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
80d11f44
JM		 3836 /* XXX : not implemented */
3837 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3838 &spr_read_generic, &spr_write_generic,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
a750fc0b 3841 /* Memory management */
f2e63a42 3842#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3843 env->nb_tlb = 64;
3844 env->nb_ways = 1;
3845 env->id_tlbs = 0;
1c53accc 3846 env->tlb_type = TLB_EMB;
f2e63a42 3847#endif
e1833e1f 3848 init_excp_BookE(env);
d63001d1
JM		 3849 env->dcache_line_size = 32;
3850 env->icache_line_size = 32;
a750fc0b 3851 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3852
3853 SET_FIT_PERIOD(12, 16, 20, 24);
3854 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3855}
3856
7856e3a4
AF		 3857POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3858{
ca5dff0a 3859 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3860 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3861
ca5dff0a 3862 dc->desc = "PowerPC 460 (guessed)";
7856e3a4
AF		 3863 pcc->init_proc = init_proc_460;
3864 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3865 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3866 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3867 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3868 PPC_CACHE | PPC_CACHE_ICBI |
3869 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3870 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3871 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3872 PPC_440_SPEC;
ba9fd9f1
AF		 3873 pcc->msr_mask = 0x000000000006FF30ULL;
3874 pcc->mmu_model = POWERPC_MMU_BOOKE;
3875 pcc->excp_model = POWERPC_EXCP_BOOKE;
3876 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3877 pcc->bfd_mach = bfd_mach_ppc_403;
3878 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3879 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3880}
3881
80d11f44 3882static void init_proc_460F (CPUPPCState *env)
3fc6c082 3883{
a750fc0b
JM		 3884 /* Time base */
3885 gen_tbl(env);
80d11f44 3886 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3887 gen_spr_440(env);
80d11f44
JM		 3888 gen_spr_usprgh(env);
3889 /* Processor identification */
3890 spr_register(env, SPR_BOOKE_PIR, "PIR",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_pir,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* XXX : not implemented */
3905 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 /* XXX : not implemented */
3910 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* XXX : not implemented */
3915 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3916 SPR_NOACCESS, SPR_NOACCESS,
3917 &spr_read_generic, &spr_write_generic,
3918 0x00000000);
3919 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3920 SPR_NOACCESS, SPR_NOACCESS,
3921 &spr_read_generic, &spr_write_generic,
3922 0x00000000);
3923 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
3927 /* XXX : not implemented */
3928 spr_register(env, SPR_440_CCR1, "CCR1",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 /* XXX : not implemented */
3933 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3934 &spr_read_generic, &spr_write_generic,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
a750fc0b 3937 /* Memory management */
f2e63a42 3938#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3939 env->nb_tlb = 64;
3940 env->nb_ways = 1;
3941 env->id_tlbs = 0;
1c53accc 3942 env->tlb_type = TLB_EMB;
f2e63a42 3943#endif
e1833e1f 3944 init_excp_BookE(env);
d63001d1
JM		 3945 env->dcache_line_size = 32;
3946 env->icache_line_size = 32;
a750fc0b 3947 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3948
3949 SET_FIT_PERIOD(12, 16, 20, 24);
3950 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3951}
3952
7856e3a4
AF		 3953POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3954{
ca5dff0a 3955 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3956 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3957
ca5dff0a 3958 dc->desc = "PowerPC 460F (guessed)";
7856e3a4
AF		 3959 pcc->init_proc = init_proc_460F;
3960 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3961 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3962 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3963 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3964 PPC_FLOAT_STFIWX | PPC_MFTB |
3965 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3966 PPC_WRTEE | PPC_MFAPIDI |
3967 PPC_CACHE | PPC_CACHE_ICBI |
3968 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3969 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3970 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3971 PPC_440_SPEC;
ba9fd9f1
AF		 3972 pcc->msr_mask = 0x000000000006FF30ULL;
3973 pcc->mmu_model = POWERPC_MMU_BOOKE;
3974 pcc->excp_model = POWERPC_EXCP_BOOKE;
3975 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3976 pcc->bfd_mach = bfd_mach_ppc_403;
3977 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3978 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3979}
3980
80d11f44
JM		 3981static void init_proc_MPC5xx (CPUPPCState *env)
3982{
3983 /* Time base */
3984 gen_tbl(env);
3985 gen_spr_5xx_8xx(env);
3986 gen_spr_5xx(env);
3987 init_excp_MPC5xx(env);
3988 env->dcache_line_size = 32;
3989 env->icache_line_size = 32;
3990 /* XXX: TODO: allocate internal IRQ controller */
3991}
3992
7856e3a4
AF		 3993POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3994{
ca5dff0a 3995 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3997
ca5dff0a 3998 dc->desc = "Freescale 5xx cores (aka RCPU)";
7856e3a4
AF		 3999 pcc->init_proc = init_proc_MPC5xx;
4000 pcc->check_pow = check_pow_none;
53116ebf
AF		 4001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4002 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4003 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4004 PPC_MFTB;
ba9fd9f1
AF		 4005 pcc->msr_mask = 0x000000000001FF43ULL;
4006 pcc->mmu_model = POWERPC_MMU_REAL;
4007 pcc->excp_model = POWERPC_EXCP_603;
4008 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4009 pcc->bfd_mach = bfd_mach_ppc_505;
4010 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4011 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4012}
4013
80d11f44
JM		 4014static void init_proc_MPC8xx (CPUPPCState *env)
4015{
4016 /* Time base */
4017 gen_tbl(env);
4018 gen_spr_5xx_8xx(env);
4019 gen_spr_8xx(env);
4020 init_excp_MPC8xx(env);
4021 env->dcache_line_size = 32;
4022 env->icache_line_size = 32;
4023 /* XXX: TODO: allocate internal IRQ controller */
4024}
4025
7856e3a4
AF		 4026POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4027{
ca5dff0a 4028 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4029 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4030
ca5dff0a 4031 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
7856e3a4
AF		 4032 pcc->init_proc = init_proc_MPC8xx;
4033 pcc->check_pow = check_pow_none;
53116ebf
AF		 4034 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4035 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4036 PPC_CACHE_ICBI | PPC_MFTB;
ba9fd9f1
AF		 4037 pcc->msr_mask = 0x000000000001F673ULL;
4038 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4039 pcc->excp_model = POWERPC_EXCP_603;
4040 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4041 pcc->bfd_mach = bfd_mach_ppc_860;
4042 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4043 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4044}
4045
80d11f44 4046/* Freescale 82xx cores (aka PowerQUICC-II) */
ca5dff0a 4047
80d11f44 4048static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4049{
80d11f44
JM		 4050 gen_spr_ne_601(env);
4051 gen_spr_G2_755(env);
4052 gen_spr_G2(env);
a750fc0b
JM		 4053 /* Time base */
4054 gen_tbl(env);
bd928eba
JM		 4055 /* External access control */
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_EAR, "EAR",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
80d11f44
JM		 4061 /* Hardware implementation register */
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_HID0, "HID0",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_HID1, "HID1",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_HID2, "HID2",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
a750fc0b 4077 /* Memory management */
80d11f44
JM		 4078 gen_low_BATs(env);
4079 gen_high_BATs(env);
4080 gen_6xx_7xx_soft_tlb(env, 64, 2);
4081 init_excp_G2(env);
d63001d1
JM		 4082 env->dcache_line_size = 32;
4083 env->icache_line_size = 32;
80d11f44
JM		 4084 /* Allocate hardware IRQ controller */
4085 ppc6xx_irq_init(env);
3fc6c082 4086}
a750fc0b 4087
7856e3a4
AF		 4088POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4089{
ca5dff0a 4090 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4092
ca5dff0a 4093 dc->desc = "PowerPC G2";
7856e3a4
AF		 4094 pcc->init_proc = init_proc_G2;
4095 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4096 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4098 PPC_FLOAT_STFIWX |
4099 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4100 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4102 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4103 pcc->msr_mask = 0x000000000006FFF2ULL;
4104 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4105 pcc->excp_model = POWERPC_EXCP_G2;
4106 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4107 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4108 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4109 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4110}
4111
80d11f44 4112static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4113{
80d11f44
JM		 4114 gen_spr_ne_601(env);
4115 gen_spr_G2_755(env);
4116 gen_spr_G2(env);
a750fc0b
JM		 4117 /* Time base */
4118 gen_tbl(env);
bd928eba
JM		 4119 /* External access control */
4120 /* XXX : not implemented */
4121 spr_register(env, SPR_EAR, "EAR",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
80d11f44 4125 /* Hardware implementation register */
578bb252 4126 /* XXX : not implemented */
80d11f44 4127 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4128 SPR_NOACCESS, SPR_NOACCESS,
4129 &spr_read_generic, &spr_write_generic,
4130 0x00000000);
80d11f44
JM		 4131 /* XXX : not implemented */
4132 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4133 SPR_NOACCESS, SPR_NOACCESS,
4134 &spr_read_generic, &spr_write_generic,
4135 0x00000000);
578bb252 4136 /* XXX : not implemented */
80d11f44 4137 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4138 SPR_NOACCESS, SPR_NOACCESS,
4139 &spr_read_generic, &spr_write_generic,
4140 0x00000000);
2bc17322
FC		 4141 /* Breakpoints */
4142 /* XXX : not implemented */
4143 spr_register(env, SPR_DABR, "DABR",
4144 SPR_NOACCESS, SPR_NOACCESS,
4145 &spr_read_generic, &spr_write_generic,
4146 0x00000000);
4147 /* XXX : not implemented */
4148 spr_register(env, SPR_DABR2, "DABR2",
4149 SPR_NOACCESS, SPR_NOACCESS,
4150 &spr_read_generic, &spr_write_generic,
4151 0x00000000);
4152 /* XXX : not implemented */
4153 spr_register(env, SPR_IABR2, "IABR2",
4154 SPR_NOACCESS, SPR_NOACCESS,
4155 &spr_read_generic, &spr_write_generic,
4156 0x00000000);
4157 /* XXX : not implemented */
4158 spr_register(env, SPR_IBCR, "IBCR",
4159 SPR_NOACCESS, SPR_NOACCESS,
4160 &spr_read_generic, &spr_write_generic,
4161 0x00000000);
4162 /* XXX : not implemented */
4163 spr_register(env, SPR_DBCR, "DBCR",
4164 SPR_NOACCESS, SPR_NOACCESS,
4165 &spr_read_generic, &spr_write_generic,
4166 0x00000000);
4167
a750fc0b 4168 /* Memory management */
80d11f44
JM		 4169 gen_low_BATs(env);
4170 gen_high_BATs(env);
4171 gen_6xx_7xx_soft_tlb(env, 64, 2);
4172 init_excp_G2(env);
d63001d1
JM		 4173 env->dcache_line_size = 32;
4174 env->icache_line_size = 32;
80d11f44
JM		 4175 /* Allocate hardware IRQ controller */
4176 ppc6xx_irq_init(env);
3fc6c082
FB		 4177}
4178
7856e3a4
AF		 4179POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4180{
ca5dff0a 4181 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4183
ca5dff0a 4184 dc->desc = "PowerPC G2LE";
7856e3a4
AF		 4185 pcc->init_proc = init_proc_G2LE;
4186 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4187 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4188 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4189 PPC_FLOAT_STFIWX |
4190 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4191 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4192 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4193 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4194 pcc->msr_mask = 0x000000000007FFF3ULL;
4195 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4196 pcc->excp_model = POWERPC_EXCP_G2;
4197 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4198 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4199 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4200 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4201}
4202
80d11f44 4203static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4204{
e1833e1f
JM		 4205 /* Time base */
4206 gen_tbl(env);
80d11f44 4207 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4208 /* XXX : not implemented */
80d11f44 4209 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4210 &spr_read_spefscr, &spr_write_spefscr,
4211 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4212 0x00000000);
80d11f44 4213 /* Memory management */
01662f3e 4214 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4215 /* XXX : not implemented */
4216 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4217 SPR_NOACCESS, SPR_NOACCESS,
4218 &spr_read_generic, &spr_write_generic,
4219 0x00000000);
80d11f44
JM		 4220 /* XXX : not implemented */
4221 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4222 SPR_NOACCESS, SPR_NOACCESS,
4223 &spr_read_generic, &spr_write_generic,
4224 0x00000000);
578bb252 4225 /* XXX : not implemented */
80d11f44 4226 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
578bb252 4230 /* XXX : not implemented */
80d11f44
JM		 4231 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4232 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4233 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4234 0x00000000);
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_generic,
4239 0x00000000);
4240 /* XXX : not implemented */
4241 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4242 SPR_NOACCESS, SPR_NOACCESS,
4243 &spr_read_generic, &spr_write_generic,
4244 0x00000000);
4245 /* XXX : not implemented */
4246 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
4255 /* XXX : not implemented */
4256 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
4260 /* XXX : not implemented */
4261 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, &spr_write_generic,
4264 0x00000000);
4265 /* XXX : not implemented */
4266 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4267 SPR_NOACCESS, SPR_NOACCESS,
4268 &spr_read_generic, &spr_write_generic,
4269 0x00000000);
4270 /* XXX : not implemented */
4271 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 /* XXX : not implemented */
4276 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4277 SPR_NOACCESS, SPR_NOACCESS,
4278 &spr_read_generic, &spr_write_generic,
4279 0x00000000);
4280 /* XXX : not implemented */
4281 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
01662f3e
AG		 4285 /* XXX : not implemented */
4286 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4287 SPR_NOACCESS, SPR_NOACCESS,
4288 &spr_read_generic, &spr_write_generic,
4289 0x00000000); /* TOFIX */
80d11f44
JM		 4290 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4291 SPR_NOACCESS, SPR_NOACCESS,
4292 &spr_read_generic, &spr_write_generic,
4293 0x00000000);
4294 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4295 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4296 &spr_read_generic, &spr_write_generic,
4297 0x00000000);
f2e63a42 4298#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4299 env->nb_tlb = 64;
4300 env->nb_ways = 1;
4301 env->id_tlbs = 0;
1c53accc 4302 env->tlb_type = TLB_EMB;
f2e63a42 4303#endif
e9cd84b9 4304 init_excp_e200(env, 0xFFFF0000UL);
d63001d1
JM		 4305 env->dcache_line_size = 32;
4306 env->icache_line_size = 32;
e1833e1f 4307 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4308}
a750fc0b 4309
7856e3a4
AF		 4310POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4311{
ca5dff0a 4312 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4314
ca5dff0a 4315 dc->desc = "e200 core";
7856e3a4
AF		 4316 pcc->init_proc = init_proc_e200;
4317 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4318 /* XXX: unimplemented instructions:
4319 * dcblc
4320 * dcbtlst
4321 * dcbtstls
4322 * icblc
4323 * icbtls
4324 * tlbivax
4325 * all SPE multiply-accumulate instructions
4326 */
4327 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4328 PPC_SPE | PPC_SPE_SINGLE |
4329 PPC_WRTEE | PPC_RFDI |
4330 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4332 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4333 PPC_BOOKE;
ba9fd9f1
AF		 4334 pcc->msr_mask = 0x000000000606FF30ULL;
4335 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4336 pcc->excp_model = POWERPC_EXCP_BOOKE;
4337 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4338 pcc->bfd_mach = bfd_mach_ppc_860;
4339 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4340 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4341 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4342}
4343
80d11f44 4344static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4345{
80d11f44
JM		 4346 gen_spr_ne_601(env);
4347 gen_spr_603(env);
a750fc0b
JM		 4348 /* Time base */
4349 gen_tbl(env);
80d11f44
JM		 4350 /* hardware implementation registers */
4351 /* XXX : not implemented */
4352 spr_register(env, SPR_HID0, "HID0",
4353 SPR_NOACCESS, SPR_NOACCESS,
4354 &spr_read_generic, &spr_write_generic,
4355 0x00000000);
4356 /* XXX : not implemented */
4357 spr_register(env, SPR_HID1, "HID1",
4358 SPR_NOACCESS, SPR_NOACCESS,
4359 &spr_read_generic, &spr_write_generic,
4360 0x00000000);
8daf1781
TM		 4361 /* XXX : not implemented */
4362 spr_register(env, SPR_HID2, "HID2",
4363 SPR_NOACCESS, SPR_NOACCESS,
4364 &spr_read_generic, &spr_write_generic,
4365 0x00000000);
80d11f44
JM		 4366 /* Memory management */
4367 gen_low_BATs(env);
8daf1781 4368 gen_high_BATs(env);
80d11f44
JM		 4369 gen_6xx_7xx_soft_tlb(env, 64, 2);
4370 init_excp_603(env);
4371 env->dcache_line_size = 32;
4372 env->icache_line_size = 32;
4373 /* Allocate hardware IRQ controller */
4374 ppc6xx_irq_init(env);
4375}
4376
7856e3a4
AF		 4377POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4378{
ca5dff0a 4379 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4381
ca5dff0a 4382 dc->desc = "e300 core";
7856e3a4
AF		 4383 pcc->init_proc = init_proc_e300;
4384 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4386 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4387 PPC_FLOAT_STFIWX |
4388 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4389 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4390 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4391 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4392 pcc->msr_mask = 0x000000000007FFF3ULL;
4393 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4394 pcc->excp_model = POWERPC_EXCP_603;
4395 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4396 pcc->bfd_mach = bfd_mach_ppc_603;
4397 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4398 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4399}
4400
b81ccf8a
AG		 4401#if !defined(CONFIG_USER_ONLY)
4402static void spr_write_mas73(void *opaque, int sprn, int gprn)
4403{
4404 TCGv val = tcg_temp_new();
4405 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4406 gen_store_spr(SPR_BOOKE_MAS3, val);
cfee0218 4407 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
b81ccf8a
AG		 4408 gen_store_spr(SPR_BOOKE_MAS7, val);
4409 tcg_temp_free(val);
4410}
4411
4412static void spr_read_mas73(void *opaque, int gprn, int sprn)
4413{
4414 TCGv mas7 = tcg_temp_new();
4415 TCGv mas3 = tcg_temp_new();
4416 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4417 tcg_gen_shli_tl(mas7, mas7, 32);
4418 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4419 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4420 tcg_temp_free(mas3);
4421 tcg_temp_free(mas7);
4422}
4423
b81ccf8a
AG		 4424#endif
4425
f7aa5583
VS		 4426enum fsl_e500_version {
4427 fsl_e500v1,
4428 fsl_e500v2,
4429 fsl_e500mc,
b81ccf8a 4430 fsl_e5500,
f7aa5583
VS		 4431};
4432
01662f3e 4433static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4434{
01662f3e 4435 uint32_t tlbncfg[2];
b81ccf8a 4436 uint64_t ivor_mask;
e9cd84b9 4437 uint64_t ivpr_mask = 0xFFFF0000ULL;
a496e8ee
AG		 4438 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4439 | 0x0020; /* 32 kb */
01662f3e
AG		 4440#if !defined(CONFIG_USER_ONLY)
4441 int i;
4442#endif
4443
80d11f44
JM		 4444 /* Time base */
4445 gen_tbl(env);
01662f3e
AG		 4446 /*
4447 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4448 * complain when accessing them.
4449 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4450 */
b81ccf8a
AG		 4451 switch (version) {
4452 case fsl_e500v1:
4453 case fsl_e500v2:
4454 default:
4455 ivor_mask = 0x0000000F0000FFFFULL;
4456 break;
4457 case fsl_e500mc:
4458 case fsl_e5500:
4459 ivor_mask = 0x000003FE0000FFFFULL;
4460 break;
2c9732db
AG		 4461 }
4462 gen_spr_BookE(env, ivor_mask);
80d11f44
JM		 4463 /* Processor identification */
4464 spr_register(env, SPR_BOOKE_PIR, "PIR",
4465 SPR_NOACCESS, SPR_NOACCESS,
4466 &spr_read_generic, &spr_write_pir,
4467 0x00000000);
4468 /* XXX : not implemented */
4469 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4470 &spr_read_spefscr, &spr_write_spefscr,
4471 &spr_read_spefscr, &spr_write_spefscr,
80d11f44 4472 0x00000000);
892c587f 4473#if !defined(CONFIG_USER_ONLY)
80d11f44 4474 /* Memory management */
80d11f44 4475 env->nb_pids = 3;
01662f3e
AG		 4476 env->nb_ways = 2;
4477 env->id_tlbs = 0;
4478 switch (version) {
f7aa5583 4479 case fsl_e500v1:
01662f3e
AG		 4480 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4481 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4482 break;
f7aa5583 4483 case fsl_e500v2:
01662f3e
AG		 4484 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4485 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4486 break;
4487 case fsl_e500mc:
b81ccf8a 4488 case fsl_e5500:
f7aa5583
VS		 4489 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4490 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
892c587f
AG		 4491 break;
4492 default:
4493 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4494 }
4495#endif
4496 /* Cache sizes */
4497 switch (version) {
4498 case fsl_e500v1:
4499 case fsl_e500v2:
4500 env->dcache_line_size = 32;
4501 env->icache_line_size = 32;
4502 break;
4503 case fsl_e500mc:
b81ccf8a 4504 case fsl_e5500:
f7aa5583
VS		 4505 env->dcache_line_size = 64;
4506 env->icache_line_size = 64;
a496e8ee 4507 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
01662f3e
AG		 4508 break;
4509 default:
4510 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4511 }
01662f3e 4512 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4513 /* XXX : not implemented */
4514 spr_register(env, SPR_HID0, "HID0",
4515 SPR_NOACCESS, SPR_NOACCESS,
4516 &spr_read_generic, &spr_write_generic,
4517 0x00000000);
4518 /* XXX : not implemented */
4519 spr_register(env, SPR_HID1, "HID1",
4520 SPR_NOACCESS, SPR_NOACCESS,
4521 &spr_read_generic, &spr_write_generic,
4522 0x00000000);
4523 /* XXX : not implemented */
4524 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4525 SPR_NOACCESS, SPR_NOACCESS,
4526 &spr_read_generic, &spr_write_generic,
4527 0x00000000);
4528 /* XXX : not implemented */
4529 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4530 SPR_NOACCESS, SPR_NOACCESS,
4531 &spr_read_generic, &spr_write_generic,
4532 0x00000000);
4533 /* XXX : not implemented */
4534 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4535 SPR_NOACCESS, SPR_NOACCESS,
4536 &spr_read_generic, &spr_write_generic,
4537 0x00000000);
578bb252 4538 /* XXX : not implemented */
a750fc0b
JM		 4539 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4540 SPR_NOACCESS, SPR_NOACCESS,
4541 &spr_read_generic, &spr_write_generic,
4542 0x00000000);
80d11f44
JM		 4543 /* XXX : not implemented */
4544 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
80d11f44
JM		 4548 /* XXX : not implemented */
4549 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
578bb252 4553 /* XXX : not implemented */
80d11f44 4554 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4555 SPR_NOACCESS, SPR_NOACCESS,
4556 &spr_read_generic, &spr_write_generic,
a496e8ee 4557 l1cfg0);
578bb252 4558 /* XXX : not implemented */
80d11f44
JM		 4559 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4560 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4561 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4562 0x00000000);
4563 /* XXX : not implemented */
4564 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4565 SPR_NOACCESS, SPR_NOACCESS,
4566 &spr_read_generic, &spr_write_generic,
4567 0x00000000);
80d11f44
JM		 4568 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4569 SPR_NOACCESS, SPR_NOACCESS,
4570 &spr_read_generic, &spr_write_generic,
4571 0x00000000);
4572 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4573 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4574 &spr_read_generic, &spr_write_generic,
4575 0x00000000);
01662f3e
AG		 4576 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4577 SPR_NOACCESS, SPR_NOACCESS,
4578 &spr_read_generic, &spr_write_booke206_mmucsr0,
4579 0x00000000);
b81ccf8a
AG		 4580 spr_register(env, SPR_BOOKE_EPR, "EPR",
4581 SPR_NOACCESS, SPR_NOACCESS,
68c2dd70 4582 &spr_read_generic, SPR_NOACCESS,
b81ccf8a
AG		 4583 0x00000000);
4584 /* XXX better abstract into Emb.xxx features */
4585 if (version == fsl_e5500) {
4586 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4587 SPR_NOACCESS, SPR_NOACCESS,
4588 &spr_read_generic, &spr_write_generic,
4589 0x00000000);
4590 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_mas73, &spr_write_mas73,
4593 0x00000000);
4594 ivpr_mask = (target_ulong)~0xFFFFULL;
4595 }
01662f3e 4596
f2e63a42 4597#if !defined(CONFIG_USER_ONLY)
01662f3e 4598 env->nb_tlb = 0;
1c53accc 4599 env->tlb_type = TLB_MAS;
01662f3e
AG		 4600 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4601 env->nb_tlb += booke206_tlb_size(env, i);
4602 }
f2e63a42 4603#endif
01662f3e 4604
e9cd84b9 4605 init_excp_e200(env, ivpr_mask);
9fdc60bf
AJ		 4606 /* Allocate hardware IRQ controller */
4607 ppce500_irq_init(env);
3fc6c082 4608}
a750fc0b 4609
01662f3e
AG		 4610static void init_proc_e500v1(CPUPPCState *env)
4611{
f7aa5583 4612 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 4613}
4614
7856e3a4
AF		 4615POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4616{
ca5dff0a 4617 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4618 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4619
ca5dff0a 4620 dc->desc = "e500v1 core";
7856e3a4
AF		 4621 pcc->init_proc = init_proc_e500v1;
4622 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4623 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4624 PPC_SPE | PPC_SPE_SINGLE |
4625 PPC_WRTEE | PPC_RFDI |
4626 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4627 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4628 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4629 pcc->insns_flags2 = PPC2_BOOKE206;
ba9fd9f1
AF		 4630 pcc->msr_mask = 0x000000000606FF30ULL;
4631 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4632 pcc->excp_model = POWERPC_EXCP_BOOKE;
4633 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4634 pcc->bfd_mach = bfd_mach_ppc_860;
4635 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4636 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4637 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4638}
4639
01662f3e
AG		 4640static void init_proc_e500v2(CPUPPCState *env)
4641{
f7aa5583
VS		 4642 init_proc_e500(env, fsl_e500v2);
4643}
4644
7856e3a4
AF		 4645POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4646{
ca5dff0a 4647 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4648 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4649
ca5dff0a 4650 dc->desc = "e500v2 core";
7856e3a4
AF		 4651 pcc->init_proc = init_proc_e500v2;
4652 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4653 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4654 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4655 PPC_WRTEE | PPC_RFDI |
4656 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4657 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4658 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4659 pcc->insns_flags2 = PPC2_BOOKE206;
ba9fd9f1
AF		 4660 pcc->msr_mask = 0x000000000606FF30ULL;
4661 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4662 pcc->excp_model = POWERPC_EXCP_BOOKE;
4663 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4664 pcc->bfd_mach = bfd_mach_ppc_860;
4665 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4666 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4667 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4668}
4669
f7aa5583
VS		 4670static void init_proc_e500mc(CPUPPCState *env)
4671{
4672 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 4673}
4674
7856e3a4
AF		 4675POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4676{
ca5dff0a 4677 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4678 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4679
ca5dff0a 4680 dc->desc = "e500mc core";
7856e3a4
AF		 4681 pcc->init_proc = init_proc_e500mc;
4682 pcc->check_pow = check_pow_none;
53116ebf
AF		 4683 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4684 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4685 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4686 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4687 PPC_FLOAT | PPC_FLOAT_FRES |
4688 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4689 PPC_FLOAT_STFIWX | PPC_WAIT |
4690 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4691 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
ba9fd9f1
AF		 4692 pcc->msr_mask = 0x000000001402FB36ULL;
4693 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4694 pcc->excp_model = POWERPC_EXCP_BOOKE;
4695 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4696 /* FIXME: figure out the correct flag for e500mc */
4697 pcc->bfd_mach = bfd_mach_ppc_e500;
4698 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4699 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4700}
4701
b81ccf8a
AG		 4702#ifdef TARGET_PPC64
4703static void init_proc_e5500(CPUPPCState *env)
4704{
4705 init_proc_e500(env, fsl_e5500);
4706}
7856e3a4
AF		 4707
4708POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4709{
ca5dff0a 4710 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4712
ca5dff0a 4713 dc->desc = "e5500 core";
7856e3a4
AF		 4714 pcc->init_proc = init_proc_e5500;
4715 pcc->check_pow = check_pow_none;
53116ebf
AF		 4716 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4717 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4718 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4719 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4720 PPC_FLOAT | PPC_FLOAT_FRES |
4721 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4722 PPC_FLOAT_STFIWX | PPC_WAIT |
4723 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4724 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4725 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
ba9fd9f1
AF		 4726 pcc->msr_mask = 0x000000009402FB36ULL;
4727 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4728 pcc->excp_model = POWERPC_EXCP_BOOKE;
4729 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4730 /* FIXME: figure out the correct flag for e5500 */
4731 pcc->bfd_mach = bfd_mach_ppc_e500;
4732 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4733 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4 4734}
b81ccf8a
AG		 4735#endif
4736
a750fc0b 4737/* Non-embedded PowerPC */
a750fc0b
JM		 4738
4739/* POWER : same as 601, without mfmsr, mfsr */
53116ebf
AF		 4740POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4741{
ca5dff0a 4742 DeviceClass *dc = DEVICE_CLASS(oc);
53116ebf
AF		 4743 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4744
ca5dff0a 4745 dc->desc = "POWER";
953af181 4746 /* pcc->insns_flags = XXX_TODO; */
ba9fd9f1
AF		 4747 /* POWER RSC (from RAD6000) */
4748 pcc->msr_mask = 0x00000000FEF0ULL;
53116ebf 4749}
a750fc0b 4750
082c6681 4751#define POWERPC_MSRR_601 (0x0000000000001040ULL)
a750fc0b
JM		 4752
4753static void init_proc_601 (CPUPPCState *env)
3fc6c082 4754{
a750fc0b
JM		 4755 gen_spr_ne_601(env);
4756 gen_spr_601(env);
4757 /* Hardware implementation registers */
4758 /* XXX : not implemented */
4759 spr_register(env, SPR_HID0, "HID0",
4760 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4761 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4762 0x80010080);
a750fc0b
JM		 4763 /* XXX : not implemented */
4764 spr_register(env, SPR_HID1, "HID1",
4765 SPR_NOACCESS, SPR_NOACCESS,
4766 &spr_read_generic, &spr_write_generic,
4767 0x00000000);
4768 /* XXX : not implemented */
4769 spr_register(env, SPR_601_HID2, "HID2",
4770 SPR_NOACCESS, SPR_NOACCESS,
4771 &spr_read_generic, &spr_write_generic,
4772 0x00000000);
4773 /* XXX : not implemented */
4774 spr_register(env, SPR_601_HID5, "HID5",
4775 SPR_NOACCESS, SPR_NOACCESS,
4776 &spr_read_generic, &spr_write_generic,
4777 0x00000000);
a750fc0b 4778 /* Memory management */
e1833e1f 4779 init_excp_601(env);
082c6681
JM		 4780 /* XXX: beware that dcache line size is 64
4781 * but dcbz uses 32 bytes "sectors"
4782 * XXX: this breaks clcs instruction !
4783 */
4784 env->dcache_line_size = 32;
d63001d1 4785 env->icache_line_size = 64;
faadf50e
JM		 4786 /* Allocate hardware IRQ controller */
4787 ppc6xx_irq_init(env);
3fc6c082
FB		 4788}
4789
7856e3a4
AF		 4790POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4791{
ca5dff0a 4792 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4793 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4794
ca5dff0a 4795 dc->desc = "PowerPC 601";
7856e3a4
AF		 4796 pcc->init_proc = init_proc_601;
4797 pcc->check_pow = check_pow_none;
53116ebf
AF		 4798 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4799 PPC_FLOAT |
4800 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4801 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4802 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4803 pcc->msr_mask = 0x000000000000FD70ULL;
4804 pcc->mmu_model = POWERPC_MMU_601;
b632a148
DG		 4805#if defined(CONFIG_SOFTMMU)
4806 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4807#endif
ba9fd9f1
AF		 4808 pcc->excp_model = POWERPC_EXCP_601;
4809 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4810 pcc->bfd_mach = bfd_mach_ppc_601;
4811 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
7856e3a4
AF		 4812}
4813
082c6681 4814#define POWERPC_MSRR_601v (0x0000000000001040ULL)
082c6681
JM		 4815
4816static void init_proc_601v (CPUPPCState *env)
4817{
4818 init_proc_601(env);
4819 /* XXX : not implemented */
4820 spr_register(env, SPR_601_HID15, "HID15",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, &spr_write_generic,
4823 0x00000000);
4824}
4825
7856e3a4
AF		 4826POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4827{
ca5dff0a 4828 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4829 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4830
ca5dff0a 4831 dc->desc = "PowerPC 601v";
7856e3a4
AF		 4832 pcc->init_proc = init_proc_601v;
4833 pcc->check_pow = check_pow_none;
53116ebf
AF		 4834 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4835 PPC_FLOAT |
4836 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4837 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4838 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4839 pcc->msr_mask = 0x000000000000FD70ULL;
4840 pcc->mmu_model = POWERPC_MMU_601;
b632a148
DG		 4841#if defined(CONFIG_SOFTMMU)
4842 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4843#endif
ba9fd9f1
AF		 4844 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4845 pcc->bfd_mach = bfd_mach_ppc_601;
4846 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
7856e3a4
AF		 4847}
4848
a750fc0b 4849static void init_proc_602 (CPUPPCState *env)
3fc6c082 4850{
a750fc0b
JM		 4851 gen_spr_ne_601(env);
4852 gen_spr_602(env);
4853 /* Time base */
4854 gen_tbl(env);
4855 /* hardware implementation registers */
4856 /* XXX : not implemented */
4857 spr_register(env, SPR_HID0, "HID0",
4858 SPR_NOACCESS, SPR_NOACCESS,
4859 &spr_read_generic, &spr_write_generic,
4860 0x00000000);
4861 /* XXX : not implemented */
4862 spr_register(env, SPR_HID1, "HID1",
4863 SPR_NOACCESS, SPR_NOACCESS,
4864 &spr_read_generic, &spr_write_generic,
4865 0x00000000);
4866 /* Memory management */
4867 gen_low_BATs(env);
4868 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4869 init_excp_602(env);
d63001d1
JM		 4870 env->dcache_line_size = 32;
4871 env->icache_line_size = 32;
a750fc0b
JM		 4872 /* Allocate hardware IRQ controller */
4873 ppc6xx_irq_init(env);
4874}
3fc6c082 4875
7856e3a4
AF		 4876POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4877{
ca5dff0a 4878 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4879 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4880
ca5dff0a 4881 dc->desc = "PowerPC 602";
7856e3a4
AF		 4882 pcc->init_proc = init_proc_602;
4883 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4884 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4885 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4886 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4887 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4888 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4889 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4890 PPC_SEGMENT | PPC_602_SPEC;
ba9fd9f1
AF		 4891 pcc->msr_mask = 0x0000000000C7FF73ULL;
4892 /* XXX: 602 MMU is quite specific. Should add a special case */
4893 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4894 pcc->excp_model = POWERPC_EXCP_602;
4895 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4896 pcc->bfd_mach = bfd_mach_ppc_602;
4897 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4898 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4899}
4900
a750fc0b
JM		 4901static void init_proc_603 (CPUPPCState *env)
4902{
4903 gen_spr_ne_601(env);
4904 gen_spr_603(env);
4905 /* Time base */
4906 gen_tbl(env);
4907 /* hardware implementation registers */
4908 /* XXX : not implemented */
4909 spr_register(env, SPR_HID0, "HID0",
4910 SPR_NOACCESS, SPR_NOACCESS,
4911 &spr_read_generic, &spr_write_generic,
4912 0x00000000);
4913 /* XXX : not implemented */
4914 spr_register(env, SPR_HID1, "HID1",
4915 SPR_NOACCESS, SPR_NOACCESS,
4916 &spr_read_generic, &spr_write_generic,
4917 0x00000000);
4918 /* Memory management */
4919 gen_low_BATs(env);
4920 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4921 init_excp_603(env);
d63001d1
JM		 4922 env->dcache_line_size = 32;
4923 env->icache_line_size = 32;
a750fc0b
JM		 4924 /* Allocate hardware IRQ controller */
4925 ppc6xx_irq_init(env);
3fc6c082
FB		 4926}
4927
7856e3a4
AF		 4928POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4929{
ca5dff0a 4930 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4931 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4932
ca5dff0a 4933 dc->desc = "PowerPC 603";
7856e3a4
AF		 4934 pcc->init_proc = init_proc_603;
4935 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4936 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4937 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4938 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4939 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4940 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4941 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4942 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4943 pcc->msr_mask = 0x000000000007FF73ULL;
4944 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4945 pcc->excp_model = POWERPC_EXCP_603;
4946 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4947 pcc->bfd_mach = bfd_mach_ppc_603;
4948 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4949 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4950}
4951
a750fc0b
JM		 4952static void init_proc_603E (CPUPPCState *env)
4953{
4954 gen_spr_ne_601(env);
4955 gen_spr_603(env);
4956 /* Time base */
4957 gen_tbl(env);
4958 /* hardware implementation registers */
4959 /* XXX : not implemented */
4960 spr_register(env, SPR_HID0, "HID0",
4961 SPR_NOACCESS, SPR_NOACCESS,
4962 &spr_read_generic, &spr_write_generic,
4963 0x00000000);
4964 /* XXX : not implemented */
4965 spr_register(env, SPR_HID1, "HID1",
4966 SPR_NOACCESS, SPR_NOACCESS,
4967 &spr_read_generic, &spr_write_generic,
4968 0x00000000);
a750fc0b
JM		 4969 /* Memory management */
4970 gen_low_BATs(env);
4971 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4972 init_excp_603(env);
d63001d1
JM		 4973 env->dcache_line_size = 32;
4974 env->icache_line_size = 32;
a750fc0b
JM		 4975 /* Allocate hardware IRQ controller */
4976 ppc6xx_irq_init(env);
4977}
4978
7856e3a4
AF		 4979POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4980{
ca5dff0a 4981 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4982 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4983
ca5dff0a 4984 dc->desc = "PowerPC 603e";
7856e3a4
AF		 4985 pcc->init_proc = init_proc_603E;
4986 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4987 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4988 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4989 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4990 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4991 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4992 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4993 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 4994 pcc->msr_mask = 0x000000000007FF73ULL;
4995 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4996 pcc->excp_model = POWERPC_EXCP_603E;
4997 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4998 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4999 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5000 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5001}
5002
a750fc0b
JM		 5003static void init_proc_604 (CPUPPCState *env)
5004{
5005 gen_spr_ne_601(env);
5006 gen_spr_604(env);
5007 /* Time base */
5008 gen_tbl(env);
5009 /* Hardware implementation registers */
5010 /* XXX : not implemented */
082c6681
JM		 5011 spr_register(env, SPR_HID0, "HID0",
5012 SPR_NOACCESS, SPR_NOACCESS,
5013 &spr_read_generic, &spr_write_generic,
5014 0x00000000);
5015 /* Memory management */
5016 gen_low_BATs(env);
5017 init_excp_604(env);
5018 env->dcache_line_size = 32;
5019 env->icache_line_size = 32;
5020 /* Allocate hardware IRQ controller */
5021 ppc6xx_irq_init(env);
5022}
5023
7856e3a4
AF		 5024POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5025{
ca5dff0a 5026 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5028
ca5dff0a 5029 dc->desc = "PowerPC 604";
7856e3a4
AF		 5030 pcc->init_proc = init_proc_604;
5031 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5032 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5033 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5034 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5035 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5036 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5037 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5038 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5039 pcc->msr_mask = 0x000000000005FF77ULL;
5040 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5041#if defined(CONFIG_SOFTMMU)
5042 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5043#endif
ba9fd9f1
AF		 5044 pcc->excp_model = POWERPC_EXCP_604;
5045 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5046 pcc->bfd_mach = bfd_mach_ppc_604;
5047 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5048 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5049}
5050
082c6681
JM		 5051static void init_proc_604E (CPUPPCState *env)
5052{
5053 gen_spr_ne_601(env);
5054 gen_spr_604(env);
5055 /* XXX : not implemented */
5056 spr_register(env, SPR_MMCR1, "MMCR1",
5057 SPR_NOACCESS, SPR_NOACCESS,
5058 &spr_read_generic, &spr_write_generic,
5059 0x00000000);
5060 /* XXX : not implemented */
5061 spr_register(env, SPR_PMC3, "PMC3",
5062 SPR_NOACCESS, SPR_NOACCESS,
5063 &spr_read_generic, &spr_write_generic,
5064 0x00000000);
5065 /* XXX : not implemented */
5066 spr_register(env, SPR_PMC4, "PMC4",
5067 SPR_NOACCESS, SPR_NOACCESS,
5068 &spr_read_generic, &spr_write_generic,
5069 0x00000000);
5070 /* Time base */
5071 gen_tbl(env);
5072 /* Hardware implementation registers */
5073 /* XXX : not implemented */
a750fc0b
JM		 5074 spr_register(env, SPR_HID0, "HID0",
5075 SPR_NOACCESS, SPR_NOACCESS,
5076 &spr_read_generic, &spr_write_generic,
5077 0x00000000);
5078 /* XXX : not implemented */
5079 spr_register(env, SPR_HID1, "HID1",
5080 SPR_NOACCESS, SPR_NOACCESS,
5081 &spr_read_generic, &spr_write_generic,
5082 0x00000000);
5083 /* Memory management */
5084 gen_low_BATs(env);
e1833e1f 5085 init_excp_604(env);
d63001d1
JM		 5086 env->dcache_line_size = 32;
5087 env->icache_line_size = 32;
a750fc0b
JM		 5088 /* Allocate hardware IRQ controller */
5089 ppc6xx_irq_init(env);
5090}
5091
7856e3a4
AF		 5092POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5093{
ca5dff0a 5094 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5095 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5096
ca5dff0a 5097 dc->desc = "PowerPC 604E";
7856e3a4
AF		 5098 pcc->init_proc = init_proc_604E;
5099 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5100 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5101 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5102 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5103 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5104 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5105 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5106 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5107 pcc->msr_mask = 0x000000000005FF77ULL;
5108 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5109#if defined(CONFIG_SOFTMMU)
5110 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5111#endif
ba9fd9f1
AF		 5112 pcc->excp_model = POWERPC_EXCP_604;
5113 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5114 pcc->bfd_mach = bfd_mach_ppc_604;
5115 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5116 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5117}
5118
bd928eba 5119static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 5120{
5121 gen_spr_ne_601(env);
5122 gen_spr_7xx(env);
5123 /* Time base */
5124 gen_tbl(env);
5125 /* Thermal management */
5126 gen_spr_thrm(env);
5127 /* Hardware implementation registers */
5128 /* XXX : not implemented */
5129 spr_register(env, SPR_HID0, "HID0",
5130 SPR_NOACCESS, SPR_NOACCESS,
5131 &spr_read_generic, &spr_write_generic,
5132 0x00000000);
5133 /* XXX : not implemented */
5134 spr_register(env, SPR_HID1, "HID1",
5135 SPR_NOACCESS, SPR_NOACCESS,
5136 &spr_read_generic, &spr_write_generic,
5137 0x00000000);
5138 /* Memory management */
5139 gen_low_BATs(env);
e1833e1f 5140 init_excp_7x0(env);
d63001d1
JM		 5141 env->dcache_line_size = 32;
5142 env->icache_line_size = 32;
a750fc0b
JM		 5143 /* Allocate hardware IRQ controller */
5144 ppc6xx_irq_init(env);
5145}
5146
7856e3a4
AF		 5147POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5148{
ca5dff0a 5149 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5150 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5151
ca5dff0a 5152 dc->desc = "PowerPC 740";
7856e3a4
AF		 5153 pcc->init_proc = init_proc_740;
5154 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5155 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5156 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5157 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5158 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5159 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5160 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5161 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5162 pcc->msr_mask = 0x000000000005FF77ULL;
5163 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5164#if defined(CONFIG_SOFTMMU)
5165 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5166#endif
ba9fd9f1
AF		 5167 pcc->excp_model = POWERPC_EXCP_7x0;
5168 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5169 pcc->bfd_mach = bfd_mach_ppc_750;
5170 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5171 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5172}
5173
bd928eba
JM		 5174static void init_proc_750 (CPUPPCState *env)
5175{
5176 gen_spr_ne_601(env);
5177 gen_spr_7xx(env);
5178 /* XXX : not implemented */
5179 spr_register(env, SPR_L2CR, "L2CR",
5180 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5181 &spr_read_generic, spr_access_nop,
bd928eba
JM		 5182 0x00000000);
5183 /* Time base */
5184 gen_tbl(env);
5185 /* Thermal management */
5186 gen_spr_thrm(env);
5187 /* Hardware implementation registers */
5188 /* XXX : not implemented */
5189 spr_register(env, SPR_HID0, "HID0",
5190 SPR_NOACCESS, SPR_NOACCESS,
5191 &spr_read_generic, &spr_write_generic,
5192 0x00000000);
5193 /* XXX : not implemented */
5194 spr_register(env, SPR_HID1, "HID1",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_generic, &spr_write_generic,
5197 0x00000000);
5198 /* Memory management */
5199 gen_low_BATs(env);
5200 /* XXX: high BATs are also present but are known to be bugged on
5201 * die version 1.x
5202 */
5203 init_excp_7x0(env);
5204 env->dcache_line_size = 32;
5205 env->icache_line_size = 32;
5206 /* Allocate hardware IRQ controller */
5207 ppc6xx_irq_init(env);
5208}
5209
7856e3a4
AF		 5210POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5211{
ca5dff0a 5212 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5213 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5214
ca5dff0a 5215 dc->desc = "PowerPC 750";
7856e3a4
AF		 5216 pcc->init_proc = init_proc_750;
5217 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5218 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5219 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5220 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5221 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5222 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5223 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5224 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5225 pcc->msr_mask = 0x000000000005FF77ULL;
5226 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5227#if defined(CONFIG_SOFTMMU)
5228 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5229#endif
ba9fd9f1
AF		 5230 pcc->excp_model = POWERPC_EXCP_7x0;
5231 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5232 pcc->bfd_mach = bfd_mach_ppc_750;
5233 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5234 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5235}
5236
bd928eba
JM		 5237static void init_proc_750cl (CPUPPCState *env)
5238{
5239 gen_spr_ne_601(env);
5240 gen_spr_7xx(env);
5241 /* XXX : not implemented */
5242 spr_register(env, SPR_L2CR, "L2CR",
5243 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5244 &spr_read_generic, spr_access_nop,
bd928eba
JM		 5245 0x00000000);
5246 /* Time base */
5247 gen_tbl(env);
5248 /* Thermal management */
5249 /* Those registers are fake on 750CL */
5250 spr_register(env, SPR_THRM1, "THRM1",
5251 SPR_NOACCESS, SPR_NOACCESS,
5252 &spr_read_generic, &spr_write_generic,
5253 0x00000000);
5254 spr_register(env, SPR_THRM2, "THRM2",
5255 SPR_NOACCESS, SPR_NOACCESS,
5256 &spr_read_generic, &spr_write_generic,
5257 0x00000000);
5258 spr_register(env, SPR_THRM3, "THRM3",
5259 SPR_NOACCESS, SPR_NOACCESS,
5260 &spr_read_generic, &spr_write_generic,
5261 0x00000000);
5262 /* XXX: not implemented */
5263 spr_register(env, SPR_750_TDCL, "TDCL",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 spr_register(env, SPR_750_TDCH, "TDCH",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 0x00000000);
5271 /* DMA */
5272 /* XXX : not implemented */
5273 spr_register(env, SPR_750_WPAR, "WPAR",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 spr_register(env, SPR_750_DMAL, "DMAL",
5278 SPR_NOACCESS, SPR_NOACCESS,
5279 &spr_read_generic, &spr_write_generic,
5280 0x00000000);
5281 spr_register(env, SPR_750_DMAU, "DMAU",
5282 SPR_NOACCESS, SPR_NOACCESS,
5283 &spr_read_generic, &spr_write_generic,
5284 0x00000000);
5285 /* Hardware implementation registers */
5286 /* XXX : not implemented */
5287 spr_register(env, SPR_HID0, "HID0",
5288 SPR_NOACCESS, SPR_NOACCESS,
5289 &spr_read_generic, &spr_write_generic,
5290 0x00000000);
5291 /* XXX : not implemented */
5292 spr_register(env, SPR_HID1, "HID1",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 0x00000000);
5296 /* XXX : not implemented */
5297 spr_register(env, SPR_750CL_HID2, "HID2",
5298 SPR_NOACCESS, SPR_NOACCESS,
5299 &spr_read_generic, &spr_write_generic,
5300 0x00000000);
5301 /* XXX : not implemented */
5302 spr_register(env, SPR_750CL_HID4, "HID4",
5303 SPR_NOACCESS, SPR_NOACCESS,
5304 &spr_read_generic, &spr_write_generic,
5305 0x00000000);
5306 /* Quantization registers */
5307 /* XXX : not implemented */
5308 spr_register(env, SPR_750_GQR0, "GQR0",
5309 SPR_NOACCESS, SPR_NOACCESS,
5310 &spr_read_generic, &spr_write_generic,
5311 0x00000000);
5312 /* XXX : not implemented */
5313 spr_register(env, SPR_750_GQR1, "GQR1",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317 /* XXX : not implemented */
5318 spr_register(env, SPR_750_GQR2, "GQR2",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 0x00000000);
5322 /* XXX : not implemented */
5323 spr_register(env, SPR_750_GQR3, "GQR3",
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 &spr_read_generic, &spr_write_generic,
5326 0x00000000);
5327 /* XXX : not implemented */
5328 spr_register(env, SPR_750_GQR4, "GQR4",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_750_GQR5, "GQR5",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* XXX : not implemented */
5338 spr_register(env, SPR_750_GQR6, "GQR6",
5339 SPR_NOACCESS, SPR_NOACCESS,
5340 &spr_read_generic, &spr_write_generic,
5341 0x00000000);
5342 /* XXX : not implemented */
5343 spr_register(env, SPR_750_GQR7, "GQR7",
5344 SPR_NOACCESS, SPR_NOACCESS,
5345 &spr_read_generic, &spr_write_generic,
5346 0x00000000);
5347 /* Memory management */
5348 gen_low_BATs(env);
5349 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5350 gen_high_BATs(env);
5351 init_excp_750cl(env);
5352 env->dcache_line_size = 32;
5353 env->icache_line_size = 32;
5354 /* Allocate hardware IRQ controller */
5355 ppc6xx_irq_init(env);
5356}
5357
7856e3a4
AF		 5358POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5359{
ca5dff0a 5360 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5361 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5362
ca5dff0a 5363 dc->desc = "PowerPC 750 CL";
7856e3a4
AF		 5364 pcc->init_proc = init_proc_750cl;
5365 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5366 /* XXX: not implemented:
5367 * cache lock instructions:
5368 * dcbz_l
5369 * floating point paired instructions
5370 * psq_lux
5371 * psq_lx
5372 * psq_stux
5373 * psq_stx
5374 * ps_abs
5375 * ps_add
5376 * ps_cmpo0
5377 * ps_cmpo1
5378 * ps_cmpu0
5379 * ps_cmpu1
5380 * ps_div
5381 * ps_madd
5382 * ps_madds0
5383 * ps_madds1
5384 * ps_merge00
5385 * ps_merge01
5386 * ps_merge10
5387 * ps_merge11
5388 * ps_mr
5389 * ps_msub
5390 * ps_mul
5391 * ps_muls0
5392 * ps_muls1
5393 * ps_nabs
5394 * ps_neg
5395 * ps_nmadd
5396 * ps_nmsub
5397 * ps_res
5398 * ps_rsqrte
5399 * ps_sel
5400 * ps_sub
5401 * ps_sum0
5402 * ps_sum1
5403 */
5404 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5405 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5406 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5407 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5408 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5409 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5410 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5411 pcc->msr_mask = 0x000000000005FF77ULL;
5412 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5413#if defined(CONFIG_SOFTMMU)
5414 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5415#endif
ba9fd9f1
AF		 5416 pcc->excp_model = POWERPC_EXCP_7x0;
5417 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5418 pcc->bfd_mach = bfd_mach_ppc_750;
5419 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5420 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5421}
5422
bd928eba
JM		 5423static void init_proc_750cx (CPUPPCState *env)
5424{
5425 gen_spr_ne_601(env);
5426 gen_spr_7xx(env);
5427 /* XXX : not implemented */
5428 spr_register(env, SPR_L2CR, "L2CR",
5429 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5430 &spr_read_generic, spr_access_nop,
bd928eba
JM		 5431 0x00000000);
5432 /* Time base */
5433 gen_tbl(env);
5434 /* Thermal management */
5435 gen_spr_thrm(env);
5436 /* This register is not implemented but is present for compatibility */
5437 spr_register(env, SPR_SDA, "SDA",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* Hardware implementation registers */
5442 /* XXX : not implemented */
5443 spr_register(env, SPR_HID0, "HID0",
5444 SPR_NOACCESS, SPR_NOACCESS,
5445 &spr_read_generic, &spr_write_generic,
5446 0x00000000);
5447 /* XXX : not implemented */
5448 spr_register(env, SPR_HID1, "HID1",
5449 SPR_NOACCESS, SPR_NOACCESS,
5450 &spr_read_generic, &spr_write_generic,
5451 0x00000000);
5452 /* Memory management */
5453 gen_low_BATs(env);
4e777442
JM		 5454 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5455 gen_high_BATs(env);
bd928eba
JM		 5456 init_excp_750cx(env);
5457 env->dcache_line_size = 32;
5458 env->icache_line_size = 32;
5459 /* Allocate hardware IRQ controller */
5460 ppc6xx_irq_init(env);
5461}
5462
7856e3a4
AF		 5463POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5464{
ca5dff0a 5465 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5467
ca5dff0a 5468 dc->desc = "PowerPC 750CX";
7856e3a4
AF		 5469 pcc->init_proc = init_proc_750cx;
5470 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5473 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5474 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5475 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5476 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5477 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5478 pcc->msr_mask = 0x000000000005FF77ULL;
5479 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5480#if defined(CONFIG_SOFTMMU)
5481 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5482#endif
ba9fd9f1
AF		 5483 pcc->excp_model = POWERPC_EXCP_7x0;
5484 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5485 pcc->bfd_mach = bfd_mach_ppc_750;
5486 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5487 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5488}
5489
a750fc0b
JM		 5490static void init_proc_750fx (CPUPPCState *env)
5491{
5492 gen_spr_ne_601(env);
5493 gen_spr_7xx(env);
bd928eba
JM		 5494 /* XXX : not implemented */
5495 spr_register(env, SPR_L2CR, "L2CR",
5496 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5497 &spr_read_generic, spr_access_nop,
bd928eba 5498 0x00000000);
a750fc0b
JM		 5499 /* Time base */
5500 gen_tbl(env);
5501 /* Thermal management */
5502 gen_spr_thrm(env);
bd928eba
JM		 5503 /* XXX : not implemented */
5504 spr_register(env, SPR_750_THRM4, "THRM4",
5505 SPR_NOACCESS, SPR_NOACCESS,
5506 &spr_read_generic, &spr_write_generic,
5507 0x00000000);
a750fc0b
JM		 5508 /* Hardware implementation registers */
5509 /* XXX : not implemented */
5510 spr_register(env, SPR_HID0, "HID0",
5511 SPR_NOACCESS, SPR_NOACCESS,
5512 &spr_read_generic, &spr_write_generic,
5513 0x00000000);
5514 /* XXX : not implemented */
5515 spr_register(env, SPR_HID1, "HID1",
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 &spr_read_generic, &spr_write_generic,
5518 0x00000000);
5519 /* XXX : not implemented */
bd928eba 5520 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5521 SPR_NOACCESS, SPR_NOACCESS,
5522 &spr_read_generic, &spr_write_generic,
5523 0x00000000);
5524 /* Memory management */
5525 gen_low_BATs(env);
5526 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5527 gen_high_BATs(env);
bd928eba 5528 init_excp_7x0(env);
d63001d1
JM		 5529 env->dcache_line_size = 32;
5530 env->icache_line_size = 32;
a750fc0b
JM		 5531 /* Allocate hardware IRQ controller */
5532 ppc6xx_irq_init(env);
5533}
5534
7856e3a4
AF		 5535POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5536{
ca5dff0a 5537 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5538 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5539
ca5dff0a 5540 dc->desc = "PowerPC 750FX";
7856e3a4
AF		 5541 pcc->init_proc = init_proc_750fx;
5542 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5543 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5544 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5545 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5546 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5547 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5548 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5549 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5550 pcc->msr_mask = 0x000000000005FF77ULL;
5551 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5552#if defined(CONFIG_SOFTMMU)
5553 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5554#endif
ba9fd9f1
AF		 5555 pcc->excp_model = POWERPC_EXCP_7x0;
5556 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5557 pcc->bfd_mach = bfd_mach_ppc_750;
5558 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5559 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5560}
5561
bd928eba
JM		 5562static void init_proc_750gx (CPUPPCState *env)
5563{
5564 gen_spr_ne_601(env);
5565 gen_spr_7xx(env);
5566 /* XXX : not implemented (XXX: different from 750fx) */
5567 spr_register(env, SPR_L2CR, "L2CR",
5568 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5569 &spr_read_generic, spr_access_nop,
bd928eba
JM		 5570 0x00000000);
5571 /* Time base */
5572 gen_tbl(env);
5573 /* Thermal management */
5574 gen_spr_thrm(env);
5575 /* XXX : not implemented */
5576 spr_register(env, SPR_750_THRM4, "THRM4",
5577 SPR_NOACCESS, SPR_NOACCESS,
5578 &spr_read_generic, &spr_write_generic,
5579 0x00000000);
5580 /* Hardware implementation registers */
5581 /* XXX : not implemented (XXX: different from 750fx) */
5582 spr_register(env, SPR_HID0, "HID0",
5583 SPR_NOACCESS, SPR_NOACCESS,
5584 &spr_read_generic, &spr_write_generic,
5585 0x00000000);
5586 /* XXX : not implemented */
5587 spr_register(env, SPR_HID1, "HID1",
5588 SPR_NOACCESS, SPR_NOACCESS,
5589 &spr_read_generic, &spr_write_generic,
5590 0x00000000);
5591 /* XXX : not implemented (XXX: different from 750fx) */
5592 spr_register(env, SPR_750FX_HID2, "HID2",
5593 SPR_NOACCESS, SPR_NOACCESS,
5594 &spr_read_generic, &spr_write_generic,
5595 0x00000000);
5596 /* Memory management */
5597 gen_low_BATs(env);
5598 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5599 gen_high_BATs(env);
5600 init_excp_7x0(env);
5601 env->dcache_line_size = 32;
5602 env->icache_line_size = 32;
5603 /* Allocate hardware IRQ controller */
5604 ppc6xx_irq_init(env);
5605}
5606
7856e3a4
AF		 5607POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5608{
ca5dff0a 5609 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5610 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5611
ca5dff0a 5612 dc->desc = "PowerPC 750GX";
7856e3a4
AF		 5613 pcc->init_proc = init_proc_750gx;
5614 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5615 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5616 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5617 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5618 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5619 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5620 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5621 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5622 pcc->msr_mask = 0x000000000005FF77ULL;
5623 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5624#if defined(CONFIG_SOFTMMU)
5625 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5626#endif
ba9fd9f1
AF		 5627 pcc->excp_model = POWERPC_EXCP_7x0;
5628 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5629 pcc->bfd_mach = bfd_mach_ppc_750;
5630 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5631 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5632}
5633
bd928eba
JM		 5634static void init_proc_745 (CPUPPCState *env)
5635{
5636 gen_spr_ne_601(env);
5637 gen_spr_7xx(env);
5638 gen_spr_G2_755(env);
5639 /* Time base */
5640 gen_tbl(env);
5641 /* Thermal management */
5642 gen_spr_thrm(env);
5643 /* Hardware implementation registers */
5644 /* XXX : not implemented */
5645 spr_register(env, SPR_HID0, "HID0",
5646 SPR_NOACCESS, SPR_NOACCESS,
5647 &spr_read_generic, &spr_write_generic,
5648 0x00000000);
5649 /* XXX : not implemented */
5650 spr_register(env, SPR_HID1, "HID1",
5651 SPR_NOACCESS, SPR_NOACCESS,
5652 &spr_read_generic, &spr_write_generic,
5653 0x00000000);
5654 /* XXX : not implemented */
5655 spr_register(env, SPR_HID2, "HID2",
5656 SPR_NOACCESS, SPR_NOACCESS,
5657 &spr_read_generic, &spr_write_generic,
5658 0x00000000);
5659 /* Memory management */
5660 gen_low_BATs(env);
5661 gen_high_BATs(env);
5662 gen_6xx_7xx_soft_tlb(env, 64, 2);
5663 init_excp_7x5(env);
5664 env->dcache_line_size = 32;
5665 env->icache_line_size = 32;
5666 /* Allocate hardware IRQ controller */
5667 ppc6xx_irq_init(env);
5668}
5669
7856e3a4
AF		 5670POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5671{
ca5dff0a 5672 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5673 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5674
ca5dff0a 5675 dc->desc = "PowerPC 745";
7856e3a4
AF		 5676 pcc->init_proc = init_proc_745;
5677 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5678 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5679 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5680 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5681 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5682 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5683 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5684 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5685 pcc->msr_mask = 0x000000000005FF77ULL;
5686 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5687 pcc->excp_model = POWERPC_EXCP_7x5;
5688 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5689 pcc->bfd_mach = bfd_mach_ppc_750;
5690 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5691 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5692}
5693
bd928eba 5694static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5695{
5696 gen_spr_ne_601(env);
bd928eba 5697 gen_spr_7xx(env);
a750fc0b
JM		 5698 gen_spr_G2_755(env);
5699 /* Time base */
5700 gen_tbl(env);
5701 /* L2 cache control */
5702 /* XXX : not implemented */
bd928eba 5703 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b 5704 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5705 &spr_read_generic, spr_access_nop,
a750fc0b
JM		 5706 0x00000000);
5707 /* XXX : not implemented */
5708 spr_register(env, SPR_L2PMCR, "L2PMCR",
5709 SPR_NOACCESS, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic,
5711 0x00000000);
bd928eba
JM		 5712 /* Thermal management */
5713 gen_spr_thrm(env);
a750fc0b
JM		 5714 /* Hardware implementation registers */
5715 /* XXX : not implemented */
5716 spr_register(env, SPR_HID0, "HID0",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 &spr_read_generic, &spr_write_generic,
5719 0x00000000);
5720 /* XXX : not implemented */
5721 spr_register(env, SPR_HID1, "HID1",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_generic, &spr_write_generic,
5724 0x00000000);
5725 /* XXX : not implemented */
5726 spr_register(env, SPR_HID2, "HID2",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 /* Memory management */
5731 gen_low_BATs(env);
5732 gen_high_BATs(env);
5733 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5734 init_excp_7x5(env);
d63001d1
JM		 5735 env->dcache_line_size = 32;
5736 env->icache_line_size = 32;
a750fc0b
JM		 5737 /* Allocate hardware IRQ controller */
5738 ppc6xx_irq_init(env);
5739}
5740
7856e3a4
AF		 5741POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5742{
ca5dff0a 5743 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5744 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5745
ca5dff0a 5746 dc->desc = "PowerPC 755";
7856e3a4
AF		 5747 pcc->init_proc = init_proc_755;
5748 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5749 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5750 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5751 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5752 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5753 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5754 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5755 PPC_SEGMENT | PPC_EXTERN;
ba9fd9f1
AF		 5756 pcc->msr_mask = 0x000000000005FF77ULL;
5757 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5758 pcc->excp_model = POWERPC_EXCP_7x5;
5759 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5760 pcc->bfd_mach = bfd_mach_ppc_750;
5761 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5762 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5763}
5764
a750fc0b
JM		 5765static void init_proc_7400 (CPUPPCState *env)
5766{
5767 gen_spr_ne_601(env);
5768 gen_spr_7xx(env);
5769 /* Time base */
5770 gen_tbl(env);
5771 /* 74xx specific SPR */
5772 gen_spr_74xx(env);
4e777442
JM		 5773 /* XXX : not implemented */
5774 spr_register(env, SPR_UBAMR, "UBAMR",
5775 &spr_read_ureg, SPR_NOACCESS,
5776 &spr_read_ureg, SPR_NOACCESS,
5777 0x00000000);
5778 /* XXX: this seems not implemented on all revisions. */
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_MSSCR1, "MSSCR1",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
a750fc0b
JM		 5784 /* Thermal management */
5785 gen_spr_thrm(env);
5786 /* Memory management */
5787 gen_low_BATs(env);
e1833e1f 5788 init_excp_7400(env);
d63001d1
JM		 5789 env->dcache_line_size = 32;
5790 env->icache_line_size = 32;
a750fc0b
JM		 5791 /* Allocate hardware IRQ controller */
5792 ppc6xx_irq_init(env);
5793}
5794
7856e3a4
AF		 5795POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5796{
ca5dff0a 5797 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5798 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5799
ca5dff0a 5800 dc->desc = "PowerPC 7400 (aka G4)";
7856e3a4
AF		 5801 pcc->init_proc = init_proc_7400;
5802 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5803 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5804 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5805 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5806 PPC_FLOAT_STFIWX |
5807 PPC_CACHE | PPC_CACHE_ICBI |
5808 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5809 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5810 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5811 PPC_MEM_TLBIA |
5812 PPC_SEGMENT | PPC_EXTERN |
5813 PPC_ALTIVEC;
ba9fd9f1
AF		 5814 pcc->msr_mask = 0x000000000205FF77ULL;
5815 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5816#if defined(CONFIG_SOFTMMU)
5817 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5818#endif
ba9fd9f1
AF		 5819 pcc->excp_model = POWERPC_EXCP_74xx;
5820 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5821 pcc->bfd_mach = bfd_mach_ppc_7400;
5822 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5823 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5824 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5825}
5826
a750fc0b
JM		 5827static void init_proc_7410 (CPUPPCState *env)
5828{
5829 gen_spr_ne_601(env);
5830 gen_spr_7xx(env);
5831 /* Time base */
5832 gen_tbl(env);
5833 /* 74xx specific SPR */
5834 gen_spr_74xx(env);
4e777442
JM		 5835 /* XXX : not implemented */
5836 spr_register(env, SPR_UBAMR, "UBAMR",
5837 &spr_read_ureg, SPR_NOACCESS,
5838 &spr_read_ureg, SPR_NOACCESS,
5839 0x00000000);
a750fc0b
JM		 5840 /* Thermal management */
5841 gen_spr_thrm(env);
5842 /* L2PMCR */
5843 /* XXX : not implemented */
5844 spr_register(env, SPR_L2PMCR, "L2PMCR",
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_generic,
5847 0x00000000);
5848 /* LDSTDB */
5849 /* XXX : not implemented */
5850 spr_register(env, SPR_LDSTDB, "LDSTDB",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* Memory management */
5855 gen_low_BATs(env);
e1833e1f 5856 init_excp_7400(env);
d63001d1
JM		 5857 env->dcache_line_size = 32;
5858 env->icache_line_size = 32;
a750fc0b
JM		 5859 /* Allocate hardware IRQ controller */
5860 ppc6xx_irq_init(env);
5861}
5862
7856e3a4
AF		 5863POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5864{
ca5dff0a 5865 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5866 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5867
ca5dff0a 5868 dc->desc = "PowerPC 7410 (aka G4)";
7856e3a4
AF		 5869 pcc->init_proc = init_proc_7410;
5870 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5871 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5872 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5873 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5874 PPC_FLOAT_STFIWX |
5875 PPC_CACHE | PPC_CACHE_ICBI |
5876 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5877 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5878 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5879 PPC_MEM_TLBIA |
5880 PPC_SEGMENT | PPC_EXTERN |
5881 PPC_ALTIVEC;
ba9fd9f1
AF		 5882 pcc->msr_mask = 0x000000000205FF77ULL;
5883 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5884#if defined(CONFIG_SOFTMMU)
5885 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5886#endif
ba9fd9f1
AF		 5887 pcc->excp_model = POWERPC_EXCP_74xx;
5888 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5889 pcc->bfd_mach = bfd_mach_ppc_7400;
5890 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5891 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5892 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5893}
5894
a750fc0b
JM		 5895static void init_proc_7440 (CPUPPCState *env)
5896{
5897 gen_spr_ne_601(env);
5898 gen_spr_7xx(env);
5899 /* Time base */
5900 gen_tbl(env);
5901 /* 74xx specific SPR */
5902 gen_spr_74xx(env);
4e777442
JM		 5903 /* XXX : not implemented */
5904 spr_register(env, SPR_UBAMR, "UBAMR",
5905 &spr_read_ureg, SPR_NOACCESS,
5906 &spr_read_ureg, SPR_NOACCESS,
5907 0x00000000);
a750fc0b
JM		 5908 /* LDSTCR */
5909 /* XXX : not implemented */
5910 spr_register(env, SPR_LDSTCR, "LDSTCR",
5911 SPR_NOACCESS, SPR_NOACCESS,
5912 &spr_read_generic, &spr_write_generic,
5913 0x00000000);
5914 /* ICTRL */
5915 /* XXX : not implemented */
5916 spr_register(env, SPR_ICTRL, "ICTRL",
5917 SPR_NOACCESS, SPR_NOACCESS,
5918 &spr_read_generic, &spr_write_generic,
5919 0x00000000);
5920 /* MSSSR0 */
578bb252 5921 /* XXX : not implemented */
a750fc0b
JM		 5922 spr_register(env, SPR_MSSSR0, "MSSSR0",
5923 SPR_NOACCESS, SPR_NOACCESS,
5924 &spr_read_generic, &spr_write_generic,
5925 0x00000000);
5926 /* PMC */
5927 /* XXX : not implemented */
5928 spr_register(env, SPR_PMC5, "PMC5",
5929 SPR_NOACCESS, SPR_NOACCESS,
5930 &spr_read_generic, &spr_write_generic,
5931 0x00000000);
578bb252 5932 /* XXX : not implemented */
a750fc0b
JM		 5933 spr_register(env, SPR_UPMC5, "UPMC5",
5934 &spr_read_ureg, SPR_NOACCESS,
5935 &spr_read_ureg, SPR_NOACCESS,
5936 0x00000000);
578bb252 5937 /* XXX : not implemented */
a750fc0b
JM		 5938 spr_register(env, SPR_PMC6, "PMC6",
5939 SPR_NOACCESS, SPR_NOACCESS,
5940 &spr_read_generic, &spr_write_generic,
5941 0x00000000);
578bb252 5942 /* XXX : not implemented */
a750fc0b
JM		 5943 spr_register(env, SPR_UPMC6, "UPMC6",
5944 &spr_read_ureg, SPR_NOACCESS,
5945 &spr_read_ureg, SPR_NOACCESS,
5946 0x00000000);
5947 /* Memory management */
5948 gen_low_BATs(env);
578bb252 5949 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5950 init_excp_7450(env);
d63001d1
JM		 5951 env->dcache_line_size = 32;
5952 env->icache_line_size = 32;
a750fc0b
JM		 5953 /* Allocate hardware IRQ controller */
5954 ppc6xx_irq_init(env);
5955}
a750fc0b 5956
7856e3a4
AF		 5957POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5958{
ca5dff0a 5959 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5960 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5961
ca5dff0a 5962 dc->desc = "PowerPC 7440 (aka G4)";
7856e3a4
AF		 5963 pcc->init_proc = init_proc_7440;
5964 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 5965 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5966 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5967 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5968 PPC_FLOAT_STFIWX |
5969 PPC_CACHE | PPC_CACHE_ICBI |
5970 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5971 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5972 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5973 PPC_MEM_TLBIA | PPC_74xx_TLB |
5974 PPC_SEGMENT | PPC_EXTERN |
5975 PPC_ALTIVEC;
ba9fd9f1
AF		 5976 pcc->msr_mask = 0x000000000205FF77ULL;
5977 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5978 pcc->excp_model = POWERPC_EXCP_74xx;
5979 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5980 pcc->bfd_mach = bfd_mach_ppc_7400;
5981 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5982 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5983 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5984}
5985
a750fc0b
JM		 5986static void init_proc_7450 (CPUPPCState *env)
5987{
5988 gen_spr_ne_601(env);
5989 gen_spr_7xx(env);
5990 /* Time base */
5991 gen_tbl(env);
5992 /* 74xx specific SPR */
5993 gen_spr_74xx(env);
5994 /* Level 3 cache control */
5995 gen_l3_ctrl(env);
4e777442
JM		 5996 /* L3ITCR1 */
5997 /* XXX : not implemented */
5998 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5999 SPR_NOACCESS, SPR_NOACCESS,
6000 &spr_read_generic, &spr_write_generic,
6001 0x00000000);
6002 /* L3ITCR2 */
6003 /* XXX : not implemented */
6004 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6005 SPR_NOACCESS, SPR_NOACCESS,
6006 &spr_read_generic, &spr_write_generic,
6007 0x00000000);
6008 /* L3ITCR3 */
6009 /* XXX : not implemented */
6010 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6011 SPR_NOACCESS, SPR_NOACCESS,
6012 &spr_read_generic, &spr_write_generic,
6013 0x00000000);
6014 /* L3OHCR */
6015 /* XXX : not implemented */
6016 spr_register(env, SPR_L3OHCR, "L3OHCR",
6017 SPR_NOACCESS, SPR_NOACCESS,
6018 &spr_read_generic, &spr_write_generic,
6019 0x00000000);
6020 /* XXX : not implemented */
6021 spr_register(env, SPR_UBAMR, "UBAMR",
6022 &spr_read_ureg, SPR_NOACCESS,
6023 &spr_read_ureg, SPR_NOACCESS,
6024 0x00000000);
a750fc0b
JM		 6025 /* LDSTCR */
6026 /* XXX : not implemented */
6027 spr_register(env, SPR_LDSTCR, "LDSTCR",
6028 SPR_NOACCESS, SPR_NOACCESS,
6029 &spr_read_generic, &spr_write_generic,
6030 0x00000000);
6031 /* ICTRL */
6032 /* XXX : not implemented */
6033 spr_register(env, SPR_ICTRL, "ICTRL",
6034 SPR_NOACCESS, SPR_NOACCESS,
6035 &spr_read_generic, &spr_write_generic,
6036 0x00000000);
6037 /* MSSSR0 */
578bb252 6038 /* XXX : not implemented */
a750fc0b
JM		 6039 spr_register(env, SPR_MSSSR0, "MSSSR0",
6040 SPR_NOACCESS, SPR_NOACCESS,
6041 &spr_read_generic, &spr_write_generic,
6042 0x00000000);
6043 /* PMC */
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_PMC5, "PMC5",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 &spr_read_generic, &spr_write_generic,
6048 0x00000000);
578bb252 6049 /* XXX : not implemented */
a750fc0b
JM		 6050 spr_register(env, SPR_UPMC5, "UPMC5",
6051 &spr_read_ureg, SPR_NOACCESS,
6052 &spr_read_ureg, SPR_NOACCESS,
6053 0x00000000);
578bb252 6054 /* XXX : not implemented */
a750fc0b
JM		 6055 spr_register(env, SPR_PMC6, "PMC6",
6056 SPR_NOACCESS, SPR_NOACCESS,
6057 &spr_read_generic, &spr_write_generic,
6058 0x00000000);
578bb252 6059 /* XXX : not implemented */
a750fc0b
JM		 6060 spr_register(env, SPR_UPMC6, "UPMC6",
6061 &spr_read_ureg, SPR_NOACCESS,
6062 &spr_read_ureg, SPR_NOACCESS,
6063 0x00000000);
6064 /* Memory management */
6065 gen_low_BATs(env);
578bb252 6066 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6067 init_excp_7450(env);
d63001d1
JM		 6068 env->dcache_line_size = 32;
6069 env->icache_line_size = 32;
a750fc0b
JM		 6070 /* Allocate hardware IRQ controller */
6071 ppc6xx_irq_init(env);
6072}
a750fc0b 6073
7856e3a4
AF		 6074POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6075{
ca5dff0a 6076 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6078
ca5dff0a 6079 dc->desc = "PowerPC 7450 (aka G4)";
7856e3a4
AF		 6080 pcc->init_proc = init_proc_7450;
6081 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6084 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6085 PPC_FLOAT_STFIWX |
6086 PPC_CACHE | PPC_CACHE_ICBI |
6087 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6088 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6089 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6090 PPC_MEM_TLBIA | PPC_74xx_TLB |
6091 PPC_SEGMENT | PPC_EXTERN |
6092 PPC_ALTIVEC;
ba9fd9f1
AF		 6093 pcc->msr_mask = 0x000000000205FF77ULL;
6094 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6095 pcc->excp_model = POWERPC_EXCP_74xx;
6096 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6097 pcc->bfd_mach = bfd_mach_ppc_7400;
6098 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6099 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6100 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6101}
6102
a750fc0b
JM		 6103static void init_proc_7445 (CPUPPCState *env)
6104{
6105 gen_spr_ne_601(env);
6106 gen_spr_7xx(env);
6107 /* Time base */
6108 gen_tbl(env);
6109 /* 74xx specific SPR */
6110 gen_spr_74xx(env);
6111 /* LDSTCR */
6112 /* XXX : not implemented */
6113 spr_register(env, SPR_LDSTCR, "LDSTCR",
6114 SPR_NOACCESS, SPR_NOACCESS,
6115 &spr_read_generic, &spr_write_generic,
6116 0x00000000);
6117 /* ICTRL */
6118 /* XXX : not implemented */
6119 spr_register(env, SPR_ICTRL, "ICTRL",
6120 SPR_NOACCESS, SPR_NOACCESS,
6121 &spr_read_generic, &spr_write_generic,
6122 0x00000000);
6123 /* MSSSR0 */
578bb252 6124 /* XXX : not implemented */
a750fc0b
JM		 6125 spr_register(env, SPR_MSSSR0, "MSSSR0",
6126 SPR_NOACCESS, SPR_NOACCESS,
6127 &spr_read_generic, &spr_write_generic,
6128 0x00000000);
6129 /* PMC */
6130 /* XXX : not implemented */
6131 spr_register(env, SPR_PMC5, "PMC5",
6132 SPR_NOACCESS, SPR_NOACCESS,
6133 &spr_read_generic, &spr_write_generic,
6134 0x00000000);
578bb252 6135 /* XXX : not implemented */
a750fc0b
JM		 6136 spr_register(env, SPR_UPMC5, "UPMC5",
6137 &spr_read_ureg, SPR_NOACCESS,
6138 &spr_read_ureg, SPR_NOACCESS,
6139 0x00000000);
578bb252 6140 /* XXX : not implemented */
a750fc0b
JM		 6141 spr_register(env, SPR_PMC6, "PMC6",
6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
578bb252 6145 /* XXX : not implemented */
a750fc0b
JM		 6146 spr_register(env, SPR_UPMC6, "UPMC6",
6147 &spr_read_ureg, SPR_NOACCESS,
6148 &spr_read_ureg, SPR_NOACCESS,
6149 0x00000000);
6150 /* SPRGs */
6151 spr_register(env, SPR_SPRG4, "SPRG4",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
6154 0x00000000);
6155 spr_register(env, SPR_USPRG4, "USPRG4",
6156 &spr_read_ureg, SPR_NOACCESS,
6157 &spr_read_ureg, SPR_NOACCESS,
6158 0x00000000);
6159 spr_register(env, SPR_SPRG5, "SPRG5",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, &spr_write_generic,
6162 0x00000000);
6163 spr_register(env, SPR_USPRG5, "USPRG5",
6164 &spr_read_ureg, SPR_NOACCESS,
6165 &spr_read_ureg, SPR_NOACCESS,
6166 0x00000000);
6167 spr_register(env, SPR_SPRG6, "SPRG6",
6168 SPR_NOACCESS, SPR_NOACCESS,
6169 &spr_read_generic, &spr_write_generic,
6170 0x00000000);
6171 spr_register(env, SPR_USPRG6, "USPRG6",
6172 &spr_read_ureg, SPR_NOACCESS,
6173 &spr_read_ureg, SPR_NOACCESS,
6174 0x00000000);
6175 spr_register(env, SPR_SPRG7, "SPRG7",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 spr_register(env, SPR_USPRG7, "USPRG7",
6180 &spr_read_ureg, SPR_NOACCESS,
6181 &spr_read_ureg, SPR_NOACCESS,
6182 0x00000000);
6183 /* Memory management */
6184 gen_low_BATs(env);
6185 gen_high_BATs(env);
578bb252 6186 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6187 init_excp_7450(env);
d63001d1
JM		 6188 env->dcache_line_size = 32;
6189 env->icache_line_size = 32;
a750fc0b
JM		 6190 /* Allocate hardware IRQ controller */
6191 ppc6xx_irq_init(env);
6192}
a750fc0b 6193
7856e3a4
AF		 6194POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6195{
ca5dff0a 6196 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6197 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6198
ca5dff0a 6199 dc->desc = "PowerPC 7445 (aka G4)";
7856e3a4
AF		 6200 pcc->init_proc = init_proc_7445;
6201 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6202 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6203 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6204 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6205 PPC_FLOAT_STFIWX |
6206 PPC_CACHE | PPC_CACHE_ICBI |
6207 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6208 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6209 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6210 PPC_MEM_TLBIA | PPC_74xx_TLB |
6211 PPC_SEGMENT | PPC_EXTERN |
6212 PPC_ALTIVEC;
ba9fd9f1
AF		 6213 pcc->msr_mask = 0x000000000205FF77ULL;
6214 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6215 pcc->excp_model = POWERPC_EXCP_74xx;
6216 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6217 pcc->bfd_mach = bfd_mach_ppc_7400;
6218 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6219 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6220 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6221}
6222
a750fc0b
JM		 6223static void init_proc_7455 (CPUPPCState *env)
6224{
6225 gen_spr_ne_601(env);
6226 gen_spr_7xx(env);
6227 /* Time base */
6228 gen_tbl(env);
6229 /* 74xx specific SPR */
6230 gen_spr_74xx(env);
6231 /* Level 3 cache control */
6232 gen_l3_ctrl(env);
6233 /* LDSTCR */
6234 /* XXX : not implemented */
6235 spr_register(env, SPR_LDSTCR, "LDSTCR",
6236 SPR_NOACCESS, SPR_NOACCESS,
6237 &spr_read_generic, &spr_write_generic,
6238 0x00000000);
6239 /* ICTRL */
6240 /* XXX : not implemented */
6241 spr_register(env, SPR_ICTRL, "ICTRL",
6242 SPR_NOACCESS, SPR_NOACCESS,
6243 &spr_read_generic, &spr_write_generic,
6244 0x00000000);
6245 /* MSSSR0 */
578bb252 6246 /* XXX : not implemented */
a750fc0b
JM		 6247 spr_register(env, SPR_MSSSR0, "MSSSR0",
6248 SPR_NOACCESS, SPR_NOACCESS,
6249 &spr_read_generic, &spr_write_generic,
6250 0x00000000);
6251 /* PMC */
6252 /* XXX : not implemented */
6253 spr_register(env, SPR_PMC5, "PMC5",
6254 SPR_NOACCESS, SPR_NOACCESS,
6255 &spr_read_generic, &spr_write_generic,
6256 0x00000000);
578bb252 6257 /* XXX : not implemented */
a750fc0b
JM		 6258 spr_register(env, SPR_UPMC5, "UPMC5",
6259 &spr_read_ureg, SPR_NOACCESS,
6260 &spr_read_ureg, SPR_NOACCESS,
6261 0x00000000);
578bb252 6262 /* XXX : not implemented */
a750fc0b
JM		 6263 spr_register(env, SPR_PMC6, "PMC6",
6264 SPR_NOACCESS, SPR_NOACCESS,
6265 &spr_read_generic, &spr_write_generic,
6266 0x00000000);
578bb252 6267 /* XXX : not implemented */
a750fc0b
JM		 6268 spr_register(env, SPR_UPMC6, "UPMC6",
6269 &spr_read_ureg, SPR_NOACCESS,
6270 &spr_read_ureg, SPR_NOACCESS,
6271 0x00000000);
6272 /* SPRGs */
6273 spr_register(env, SPR_SPRG4, "SPRG4",
6274 SPR_NOACCESS, SPR_NOACCESS,
6275 &spr_read_generic, &spr_write_generic,
6276 0x00000000);
6277 spr_register(env, SPR_USPRG4, "USPRG4",
6278 &spr_read_ureg, SPR_NOACCESS,
6279 &spr_read_ureg, SPR_NOACCESS,
6280 0x00000000);
6281 spr_register(env, SPR_SPRG5, "SPRG5",
6282 SPR_NOACCESS, SPR_NOACCESS,
6283 &spr_read_generic, &spr_write_generic,
6284 0x00000000);
6285 spr_register(env, SPR_USPRG5, "USPRG5",
6286 &spr_read_ureg, SPR_NOACCESS,
6287 &spr_read_ureg, SPR_NOACCESS,
6288 0x00000000);
6289 spr_register(env, SPR_SPRG6, "SPRG6",
6290 SPR_NOACCESS, SPR_NOACCESS,
6291 &spr_read_generic, &spr_write_generic,
6292 0x00000000);
6293 spr_register(env, SPR_USPRG6, "USPRG6",
6294 &spr_read_ureg, SPR_NOACCESS,
6295 &spr_read_ureg, SPR_NOACCESS,
6296 0x00000000);
6297 spr_register(env, SPR_SPRG7, "SPRG7",
6298 SPR_NOACCESS, SPR_NOACCESS,
6299 &spr_read_generic, &spr_write_generic,
6300 0x00000000);
6301 spr_register(env, SPR_USPRG7, "USPRG7",
6302 &spr_read_ureg, SPR_NOACCESS,
6303 &spr_read_ureg, SPR_NOACCESS,
6304 0x00000000);
6305 /* Memory management */
6306 gen_low_BATs(env);
6307 gen_high_BATs(env);
578bb252 6308 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6309 init_excp_7450(env);
d63001d1
JM		 6310 env->dcache_line_size = 32;
6311 env->icache_line_size = 32;
a750fc0b
JM		 6312 /* Allocate hardware IRQ controller */
6313 ppc6xx_irq_init(env);
6314}
a750fc0b 6315
7856e3a4
AF		 6316POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6317{
ca5dff0a 6318 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6319 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6320
ca5dff0a 6321 dc->desc = "PowerPC 7455 (aka G4)";
7856e3a4
AF		 6322 pcc->init_proc = init_proc_7455;
6323 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6324 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6325 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6326 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6327 PPC_FLOAT_STFIWX |
6328 PPC_CACHE | PPC_CACHE_ICBI |
6329 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6330 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6331 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6332 PPC_MEM_TLBIA | PPC_74xx_TLB |
6333 PPC_SEGMENT | PPC_EXTERN |
6334 PPC_ALTIVEC;
ba9fd9f1
AF		 6335 pcc->msr_mask = 0x000000000205FF77ULL;
6336 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6337 pcc->excp_model = POWERPC_EXCP_74xx;
6338 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6339 pcc->bfd_mach = bfd_mach_ppc_7400;
6340 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6341 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6342 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6343}
6344
4e777442
JM		 6345static void init_proc_7457 (CPUPPCState *env)
6346{
6347 gen_spr_ne_601(env);
6348 gen_spr_7xx(env);
6349 /* Time base */
6350 gen_tbl(env);
6351 /* 74xx specific SPR */
6352 gen_spr_74xx(env);
6353 /* Level 3 cache control */
6354 gen_l3_ctrl(env);
6355 /* L3ITCR1 */
6356 /* XXX : not implemented */
6357 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6358 SPR_NOACCESS, SPR_NOACCESS,
6359 &spr_read_generic, &spr_write_generic,
6360 0x00000000);
6361 /* L3ITCR2 */
6362 /* XXX : not implemented */
6363 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6364 SPR_NOACCESS, SPR_NOACCESS,
6365 &spr_read_generic, &spr_write_generic,
6366 0x00000000);
6367 /* L3ITCR3 */
6368 /* XXX : not implemented */
6369 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6370 SPR_NOACCESS, SPR_NOACCESS,
6371 &spr_read_generic, &spr_write_generic,
6372 0x00000000);
6373 /* L3OHCR */
6374 /* XXX : not implemented */
6375 spr_register(env, SPR_L3OHCR, "L3OHCR",
6376 SPR_NOACCESS, SPR_NOACCESS,
6377 &spr_read_generic, &spr_write_generic,
6378 0x00000000);
6379 /* LDSTCR */
6380 /* XXX : not implemented */
6381 spr_register(env, SPR_LDSTCR, "LDSTCR",
6382 SPR_NOACCESS, SPR_NOACCESS,
6383 &spr_read_generic, &spr_write_generic,
6384 0x00000000);
6385 /* ICTRL */
6386 /* XXX : not implemented */
6387 spr_register(env, SPR_ICTRL, "ICTRL",
6388 SPR_NOACCESS, SPR_NOACCESS,
6389 &spr_read_generic, &spr_write_generic,
6390 0x00000000);
6391 /* MSSSR0 */
6392 /* XXX : not implemented */
6393 spr_register(env, SPR_MSSSR0, "MSSSR0",
6394 SPR_NOACCESS, SPR_NOACCESS,
6395 &spr_read_generic, &spr_write_generic,
6396 0x00000000);
6397 /* PMC */
6398 /* XXX : not implemented */
6399 spr_register(env, SPR_PMC5, "PMC5",
6400 SPR_NOACCESS, SPR_NOACCESS,
6401 &spr_read_generic, &spr_write_generic,
6402 0x00000000);
6403 /* XXX : not implemented */
6404 spr_register(env, SPR_UPMC5, "UPMC5",
6405 &spr_read_ureg, SPR_NOACCESS,
6406 &spr_read_ureg, SPR_NOACCESS,
6407 0x00000000);
6408 /* XXX : not implemented */
6409 spr_register(env, SPR_PMC6, "PMC6",
6410 SPR_NOACCESS, SPR_NOACCESS,
6411 &spr_read_generic, &spr_write_generic,
6412 0x00000000);
6413 /* XXX : not implemented */
6414 spr_register(env, SPR_UPMC6, "UPMC6",
6415 &spr_read_ureg, SPR_NOACCESS,
6416 &spr_read_ureg, SPR_NOACCESS,
6417 0x00000000);
6418 /* SPRGs */
6419 spr_register(env, SPR_SPRG4, "SPRG4",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 0x00000000);
6423 spr_register(env, SPR_USPRG4, "USPRG4",
6424 &spr_read_ureg, SPR_NOACCESS,
6425 &spr_read_ureg, SPR_NOACCESS,
6426 0x00000000);
6427 spr_register(env, SPR_SPRG5, "SPRG5",
6428 SPR_NOACCESS, SPR_NOACCESS,
6429 &spr_read_generic, &spr_write_generic,
6430 0x00000000);
6431 spr_register(env, SPR_USPRG5, "USPRG5",
6432 &spr_read_ureg, SPR_NOACCESS,
6433 &spr_read_ureg, SPR_NOACCESS,
6434 0x00000000);
6435 spr_register(env, SPR_SPRG6, "SPRG6",
6436 SPR_NOACCESS, SPR_NOACCESS,
6437 &spr_read_generic, &spr_write_generic,
6438 0x00000000);
6439 spr_register(env, SPR_USPRG6, "USPRG6",
6440 &spr_read_ureg, SPR_NOACCESS,
6441 &spr_read_ureg, SPR_NOACCESS,
6442 0x00000000);
6443 spr_register(env, SPR_SPRG7, "SPRG7",
6444 SPR_NOACCESS, SPR_NOACCESS,
6445 &spr_read_generic, &spr_write_generic,
6446 0x00000000);
6447 spr_register(env, SPR_USPRG7, "USPRG7",
6448 &spr_read_ureg, SPR_NOACCESS,
6449 &spr_read_ureg, SPR_NOACCESS,
6450 0x00000000);
6451 /* Memory management */
6452 gen_low_BATs(env);
6453 gen_high_BATs(env);
6454 gen_74xx_soft_tlb(env, 128, 2);
6455 init_excp_7450(env);
6456 env->dcache_line_size = 32;
6457 env->icache_line_size = 32;
6458 /* Allocate hardware IRQ controller */
6459 ppc6xx_irq_init(env);
6460}
6461
7856e3a4
AF		 6462POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6463{
ca5dff0a 6464 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6465 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6466
ca5dff0a 6467 dc->desc = "PowerPC 7457 (aka G4)";
7856e3a4
AF		 6468 pcc->init_proc = init_proc_7457;
6469 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6470 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6471 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6472 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6473 PPC_FLOAT_STFIWX |
6474 PPC_CACHE | PPC_CACHE_ICBI |
6475 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6476 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6477 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6478 PPC_MEM_TLBIA | PPC_74xx_TLB |
6479 PPC_SEGMENT | PPC_EXTERN |
6480 PPC_ALTIVEC;
ba9fd9f1
AF		 6481 pcc->msr_mask = 0x000000000205FF77ULL;
6482 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6483 pcc->excp_model = POWERPC_EXCP_74xx;
6484 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6485 pcc->bfd_mach = bfd_mach_ppc_7400;
6486 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6487 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6488 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6489}
6490
7162bdea
JG		 6491static void init_proc_e600 (CPUPPCState *env)
6492{
6493 gen_spr_ne_601(env);
6494 gen_spr_7xx(env);
6495 /* Time base */
6496 gen_tbl(env);
6497 /* 74xx specific SPR */
6498 gen_spr_74xx(env);
6499 /* XXX : not implemented */
6500 spr_register(env, SPR_UBAMR, "UBAMR",
6501 &spr_read_ureg, SPR_NOACCESS,
6502 &spr_read_ureg, SPR_NOACCESS,
6503 0x00000000);
6504 /* XXX : not implemented */
6505 spr_register(env, SPR_LDSTCR, "LDSTCR",
6506 SPR_NOACCESS, SPR_NOACCESS,
6507 &spr_read_generic, &spr_write_generic,
6508 0x00000000);
6509 /* XXX : not implemented */
6510 spr_register(env, SPR_ICTRL, "ICTRL",
6511 SPR_NOACCESS, SPR_NOACCESS,
6512 &spr_read_generic, &spr_write_generic,
6513 0x00000000);
6514 /* XXX : not implemented */
6515 spr_register(env, SPR_MSSSR0, "MSSSR0",
6516 SPR_NOACCESS, SPR_NOACCESS,
6517 &spr_read_generic, &spr_write_generic,
6518 0x00000000);
6519 /* XXX : not implemented */
6520 spr_register(env, SPR_PMC5, "PMC5",
6521 SPR_NOACCESS, SPR_NOACCESS,
6522 &spr_read_generic, &spr_write_generic,
6523 0x00000000);
6524 /* XXX : not implemented */
6525 spr_register(env, SPR_UPMC5, "UPMC5",
6526 &spr_read_ureg, SPR_NOACCESS,
6527 &spr_read_ureg, SPR_NOACCESS,
6528 0x00000000);
6529 /* XXX : not implemented */
6530 spr_register(env, SPR_PMC6, "PMC6",
6531 SPR_NOACCESS, SPR_NOACCESS,
6532 &spr_read_generic, &spr_write_generic,
6533 0x00000000);
6534 /* XXX : not implemented */
6535 spr_register(env, SPR_UPMC6, "UPMC6",
6536 &spr_read_ureg, SPR_NOACCESS,
6537 &spr_read_ureg, SPR_NOACCESS,
6538 0x00000000);
6539 /* SPRGs */
6540 spr_register(env, SPR_SPRG4, "SPRG4",
6541 SPR_NOACCESS, SPR_NOACCESS,
6542 &spr_read_generic, &spr_write_generic,
6543 0x00000000);
6544 spr_register(env, SPR_USPRG4, "USPRG4",
6545 &spr_read_ureg, SPR_NOACCESS,
6546 &spr_read_ureg, SPR_NOACCESS,
6547 0x00000000);
6548 spr_register(env, SPR_SPRG5, "SPRG5",
6549 SPR_NOACCESS, SPR_NOACCESS,
6550 &spr_read_generic, &spr_write_generic,
6551 0x00000000);
6552 spr_register(env, SPR_USPRG5, "USPRG5",
6553 &spr_read_ureg, SPR_NOACCESS,
6554 &spr_read_ureg, SPR_NOACCESS,
6555 0x00000000);
6556 spr_register(env, SPR_SPRG6, "SPRG6",
6557 SPR_NOACCESS, SPR_NOACCESS,
6558 &spr_read_generic, &spr_write_generic,
6559 0x00000000);
6560 spr_register(env, SPR_USPRG6, "USPRG6",
6561 &spr_read_ureg, SPR_NOACCESS,
6562 &spr_read_ureg, SPR_NOACCESS,
6563 0x00000000);
6564 spr_register(env, SPR_SPRG7, "SPRG7",
6565 SPR_NOACCESS, SPR_NOACCESS,
6566 &spr_read_generic, &spr_write_generic,
6567 0x00000000);
6568 spr_register(env, SPR_USPRG7, "USPRG7",
6569 &spr_read_ureg, SPR_NOACCESS,
6570 &spr_read_ureg, SPR_NOACCESS,
6571 0x00000000);
6572 /* Memory management */
6573 gen_low_BATs(env);
6574 gen_high_BATs(env);
6575 gen_74xx_soft_tlb(env, 128, 2);
6576 init_excp_7450(env);
6577 env->dcache_line_size = 32;
6578 env->icache_line_size = 32;
6579 /* Allocate hardware IRQ controller */
6580 ppc6xx_irq_init(env);
6581}
6582
6583POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6584{
6585 DeviceClass *dc = DEVICE_CLASS(oc);
6586 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6587
6588 dc->desc = "PowerPC e600";
6589 pcc->init_proc = init_proc_e600;
6590 pcc->check_pow = check_pow_hid0_74xx;
6591 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6592 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6593 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6594 PPC_FLOAT_STFIWX |
6595 PPC_CACHE | PPC_CACHE_ICBI |
6596 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6597 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6598 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6599 PPC_MEM_TLBIA | PPC_74xx_TLB |
6600 PPC_SEGMENT | PPC_EXTERN |
6601 PPC_ALTIVEC;
6602 pcc->insns_flags2 = PPC_NONE;
6603 pcc->msr_mask = 0x000000000205FF77ULL;
6604 pcc->mmu_model = POWERPC_MMU_32B;
6605#if defined(CONFIG_SOFTMMU)
6606 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6607#endif
6608 pcc->excp_model = POWERPC_EXCP_74xx;
6609 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6610 pcc->bfd_mach = bfd_mach_ppc_7400;
6611 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6612 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6613 POWERPC_FLAG_BUS_CLK;
6614}
6615
a750fc0b 6616#if defined (TARGET_PPC64)
417bf010
JM		 6617#if defined(CONFIG_USER_ONLY)
6618#define POWERPC970_HID5_INIT 0x00000080
6619#else
6620#define POWERPC970_HID5_INIT 0x00000000
6621#endif
6622
2f462816
JM		 6623static int check_pow_970 (CPUPPCState *env)
6624{
6625 if (env->spr[SPR_HID0] & 0x00600000)
6626 return 1;
6627
6628 return 0;
6629}
6630
a750fc0b
JM		 6631static void init_proc_970 (CPUPPCState *env)
6632{
6633 gen_spr_ne_601(env);
6634 gen_spr_7xx(env);
6635 /* Time base */
6636 gen_tbl(env);
6637 /* Hardware implementation registers */
6638 /* XXX : not implemented */
6639 spr_register(env, SPR_HID0, "HID0",
6640 SPR_NOACCESS, SPR_NOACCESS,
06403421 6641 &spr_read_generic, &spr_write_clear,
d63001d1 6642 0x60000000);
a750fc0b
JM		 6643 /* XXX : not implemented */
6644 spr_register(env, SPR_HID1, "HID1",
6645 SPR_NOACCESS, SPR_NOACCESS,
6646 &spr_read_generic, &spr_write_generic,
6647 0x00000000);
6648 /* XXX : not implemented */
e57448f1
JM		 6649 spr_register(env, SPR_970_HID5, "HID5",
6650 SPR_NOACCESS, SPR_NOACCESS,
6651 &spr_read_generic, &spr_write_generic,
417bf010 6652 POWERPC970_HID5_INIT);
a750fc0b
JM		 6653 /* Memory management */
6654 /* XXX: not correct */
6655 gen_low_BATs(env);
12de9a39
JM		 6656 spr_register(env, SPR_HIOR, "SPR_HIOR",
6657 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6658 &spr_read_hior, &spr_write_hior,
6659 0x00000000);
f2e63a42 6660#if !defined(CONFIG_USER_ONLY)
12de9a39 6661 env->slb_nr = 32;
f2e63a42 6662#endif
e1833e1f 6663 init_excp_970(env);
d63001d1
JM		 6664 env->dcache_line_size = 128;
6665 env->icache_line_size = 128;
a750fc0b
JM		 6666 /* Allocate hardware IRQ controller */
6667 ppc970_irq_init(env);
cf8358c8
AJ		 6668 /* Can't find information on what this should be on reset. This
6669 * value is the one used by 74xx processors. */
6670 vscr_init(env, 0x00010000);
a750fc0b 6671}
a750fc0b 6672
7856e3a4
AF		 6673POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6674{
ca5dff0a 6675 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6676 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6677
ca5dff0a 6678 dc->desc = "PowerPC 970";
7856e3a4
AF		 6679 pcc->init_proc = init_proc_970;
6680 pcc->check_pow = check_pow_970;
53116ebf
AF		 6681 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6682 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6683 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6684 PPC_FLOAT_STFIWX |
6685 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6686 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6687 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6688 PPC_64B | PPC_ALTIVEC |
6689 PPC_SEGMENT_64B | PPC_SLBI;
ba9fd9f1
AF		 6690 pcc->msr_mask = 0x900000000204FF36ULL;
6691 pcc->mmu_model = POWERPC_MMU_64B;
b632a148
DG		 6692#if defined(CONFIG_SOFTMMU)
6693 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6694#endif
ba9fd9f1
AF		 6695 pcc->excp_model = POWERPC_EXCP_970;
6696 pcc->bus_model = PPC_FLAGS_INPUT_970;
6697 pcc->bfd_mach = bfd_mach_ppc64;
6698 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6699 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6700 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6701}
6702
2f462816
JM		 6703static int check_pow_970FX (CPUPPCState *env)
6704{
6705 if (env->spr[SPR_HID0] & 0x00600000)
6706 return 1;
6707
6708 return 0;
6709}
6710
a750fc0b
JM		 6711static void init_proc_970FX (CPUPPCState *env)
6712{
6713 gen_spr_ne_601(env);
6714 gen_spr_7xx(env);
6715 /* Time base */
6716 gen_tbl(env);
6717 /* Hardware implementation registers */
6718 /* XXX : not implemented */
6719 spr_register(env, SPR_HID0, "HID0",
6720 SPR_NOACCESS, SPR_NOACCESS,
06403421 6721 &spr_read_generic, &spr_write_clear,
d63001d1 6722 0x60000000);
a750fc0b
JM		 6723 /* XXX : not implemented */
6724 spr_register(env, SPR_HID1, "HID1",
6725 SPR_NOACCESS, SPR_NOACCESS,
6726 &spr_read_generic, &spr_write_generic,
6727 0x00000000);
6728 /* XXX : not implemented */
d63001d1
JM		 6729 spr_register(env, SPR_970_HID5, "HID5",
6730 SPR_NOACCESS, SPR_NOACCESS,
6731 &spr_read_generic, &spr_write_generic,
417bf010 6732 POWERPC970_HID5_INIT);
a750fc0b
JM		 6733 /* Memory management */
6734 /* XXX: not correct */
6735 gen_low_BATs(env);
12de9a39
JM		 6736 spr_register(env, SPR_HIOR, "SPR_HIOR",
6737 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6738 &spr_read_hior, &spr_write_hior,
6739 0x00000000);
4e98d8cf
BS		 6740 spr_register(env, SPR_CTRL, "SPR_CTRL",
6741 SPR_NOACCESS, SPR_NOACCESS,
6742 &spr_read_generic, &spr_write_generic,
6743 0x00000000);
6744 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6745 SPR_NOACCESS, SPR_NOACCESS,
6746 &spr_read_generic, &spr_write_generic,
6747 0x00000000);
6748 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6749 &spr_read_generic, &spr_write_generic,
6750 &spr_read_generic, &spr_write_generic,
6751 0x00000000);
f2e63a42 6752#if !defined(CONFIG_USER_ONLY)
8eee0af9 6753 env->slb_nr = 64;
f2e63a42 6754#endif
e1833e1f 6755 init_excp_970(env);
d63001d1
JM		 6756 env->dcache_line_size = 128;
6757 env->icache_line_size = 128;
a750fc0b
JM		 6758 /* Allocate hardware IRQ controller */
6759 ppc970_irq_init(env);
cf8358c8
AJ		 6760 /* Can't find information on what this should be on reset. This
6761 * value is the one used by 74xx processors. */
6762 vscr_init(env, 0x00010000);
a750fc0b 6763}
a750fc0b 6764
7856e3a4
AF		 6765POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6766{
ca5dff0a 6767 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6768 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6769
ca5dff0a 6770 dc->desc = "PowerPC 970FX (aka G5)";
7856e3a4
AF		 6771 pcc->init_proc = init_proc_970FX;
6772 pcc->check_pow = check_pow_970FX;
53116ebf
AF		 6773 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6774 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6775 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6776 PPC_FLOAT_STFIWX |
6777 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6778 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6779 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6780 PPC_64B | PPC_ALTIVEC |
6781 PPC_SEGMENT_64B | PPC_SLBI;
ba9fd9f1
AF		 6782 pcc->msr_mask = 0x800000000204FF36ULL;
6783 pcc->mmu_model = POWERPC_MMU_64B;
b632a148
DG		 6784#if defined(CONFIG_SOFTMMU)
6785 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6786#endif
ba9fd9f1
AF		 6787 pcc->excp_model = POWERPC_EXCP_970;
6788 pcc->bus_model = PPC_FLAGS_INPUT_970;
6789 pcc->bfd_mach = bfd_mach_ppc64;
6790 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6791 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6792 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6793}
6794
2f462816
JM		 6795static int check_pow_970MP (CPUPPCState *env)
6796{
6797 if (env->spr[SPR_HID0] & 0x01C00000)
6798 return 1;
6799
6800 return 0;
6801}
6802
6803static void init_proc_970MP (CPUPPCState *env)
6804{
6805 gen_spr_ne_601(env);
6806 gen_spr_7xx(env);
6807 /* Time base */
6808 gen_tbl(env);
6809 /* Hardware implementation registers */
6810 /* XXX : not implemented */
6811 spr_register(env, SPR_HID0, "HID0",
6812 SPR_NOACCESS, SPR_NOACCESS,
6813 &spr_read_generic, &spr_write_clear,
6814 0x60000000);
6815 /* XXX : not implemented */
6816 spr_register(env, SPR_HID1, "HID1",
6817 SPR_NOACCESS, SPR_NOACCESS,
6818 &spr_read_generic, &spr_write_generic,
6819 0x00000000);
6820 /* XXX : not implemented */
2f462816
JM		 6821 spr_register(env, SPR_970_HID5, "HID5",
6822 SPR_NOACCESS, SPR_NOACCESS,
6823 &spr_read_generic, &spr_write_generic,
6824 POWERPC970_HID5_INIT);
bd928eba 6825 /* XXX : not implemented */
2f462816
JM		 6826 /* Memory management */
6827 /* XXX: not correct */
6828 gen_low_BATs(env);
2f462816
JM		 6829 spr_register(env, SPR_HIOR, "SPR_HIOR",
6830 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6831 &spr_read_hior, &spr_write_hior,
6832 0x00000000);
6cd8712c
GK		 6833 /* Logical partitionning */
6834 spr_register_kvm(env, SPR_LPCR, "LPCR",
6835 SPR_NOACCESS, SPR_NOACCESS,
6836 &spr_read_generic, &spr_write_generic,
6837 KVM_REG_PPC_LPCR, 0x00000000);
2f462816
JM		 6838#if !defined(CONFIG_USER_ONLY)
6839 env->slb_nr = 32;
6840#endif
6841 init_excp_970(env);
6842 env->dcache_line_size = 128;
6843 env->icache_line_size = 128;
6844 /* Allocate hardware IRQ controller */
6845 ppc970_irq_init(env);
cf8358c8
AJ		 6846 /* Can't find information on what this should be on reset. This
6847 * value is the one used by 74xx processors. */
6848 vscr_init(env, 0x00010000);
2f462816
JM		 6849}
6850
7856e3a4
AF		 6851POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6852{
ca5dff0a 6853 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6854 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6855
ca5dff0a 6856 dc->desc = "PowerPC 970 MP";
7856e3a4
AF		 6857 pcc->init_proc = init_proc_970MP;
6858 pcc->check_pow = check_pow_970MP;
53116ebf
AF		 6859 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6860 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6861 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6862 PPC_FLOAT_STFIWX |
6863 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6864 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6865 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6866 PPC_64B | PPC_ALTIVEC |
6867 PPC_SEGMENT_64B | PPC_SLBI;
ba9fd9f1
AF		 6868 pcc->msr_mask = 0x900000000204FF36ULL;
6869 pcc->mmu_model = POWERPC_MMU_64B;
b632a148
DG		 6870#if defined(CONFIG_SOFTMMU)
6871 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6872#endif
ba9fd9f1
AF		 6873 pcc->excp_model = POWERPC_EXCP_970;
6874 pcc->bus_model = PPC_FLAGS_INPUT_970;
6875 pcc->bfd_mach = bfd_mach_ppc64;
6876 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6877 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6878 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6879}
6880
35ebcb2b
AF		 6881static void init_proc_power5plus(CPUPPCState *env)
6882{
6883 gen_spr_ne_601(env);
6884 gen_spr_7xx(env);
6885 /* Time base */
6886 gen_tbl(env);
6887 /* Hardware implementation registers */
6888 /* XXX : not implemented */
6889 spr_register(env, SPR_HID0, "HID0",
6890 SPR_NOACCESS, SPR_NOACCESS,
6891 &spr_read_generic, &spr_write_clear,
6892 0x60000000);
6893 /* XXX : not implemented */
6894 spr_register(env, SPR_HID1, "HID1",
6895 SPR_NOACCESS, SPR_NOACCESS,
6896 &spr_read_generic, &spr_write_generic,
6897 0x00000000);
6898 /* XXX : not implemented */
35ebcb2b
AF		 6899 spr_register(env, SPR_970_HID5, "HID5",
6900 SPR_NOACCESS, SPR_NOACCESS,
6901 &spr_read_generic, &spr_write_generic,
6902 POWERPC970_HID5_INIT);
35ebcb2b
AF		 6903 /* Memory management */
6904 /* XXX: not correct */
6905 gen_low_BATs(env);
35ebcb2b
AF		 6906 spr_register(env, SPR_HIOR, "SPR_HIOR",
6907 SPR_NOACCESS, SPR_NOACCESS,
6908 &spr_read_hior, &spr_write_hior,
6909 0x00000000);
6910 spr_register(env, SPR_CTRL, "SPR_CTRL",
6911 SPR_NOACCESS, SPR_NOACCESS,
6912 &spr_read_generic, &spr_write_generic,
6913 0x00000000);
6914 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6915 SPR_NOACCESS, SPR_NOACCESS,
6916 &spr_read_generic, &spr_write_generic,
6917 0x00000000);
6918 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6919 &spr_read_generic, &spr_write_generic,
6920 &spr_read_generic, &spr_write_generic,
6921 0x00000000);
6cd8712c
GK		 6922 /* Logical partitionning */
6923 spr_register_kvm(env, SPR_LPCR, "LPCR",
6924 SPR_NOACCESS, SPR_NOACCESS,
6925 &spr_read_generic, &spr_write_generic,
6926 KVM_REG_PPC_LPCR, 0x00000000);
35ebcb2b
AF		 6927#if !defined(CONFIG_USER_ONLY)
6928 env->slb_nr = 64;
6929#endif
6930 init_excp_970(env);
6931 env->dcache_line_size = 128;
6932 env->icache_line_size = 128;
6933 /* Allocate hardware IRQ controller */
6934 ppc970_irq_init(env);
6935 /* Can't find information on what this should be on reset. This
6936 * value is the one used by 74xx processors. */
6937 vscr_init(env, 0x00010000);
6938}
6939
6940POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6941{
6942 DeviceClass *dc = DEVICE_CLASS(oc);
6943 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6944
793826cd 6945 dc->fw_name = "PowerPC,POWER5";
35ebcb2b
AF		 6946 dc->desc = "POWER5+";
6947 pcc->init_proc = init_proc_power5plus;
6948 pcc->check_pow = check_pow_970FX;
6949 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6950 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6951 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6952 PPC_FLOAT_STFIWX |
6953 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6954 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6955 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6956 PPC_64B |
6957 PPC_SEGMENT_64B | PPC_SLBI;
6958 pcc->msr_mask = 0x800000000204FF36ULL;
6959 pcc->mmu_model = POWERPC_MMU_64B;
6960#if defined(CONFIG_SOFTMMU)
6961 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6962#endif
6963 pcc->excp_model = POWERPC_EXCP_970;
6964 pcc->bus_model = PPC_FLAGS_INPUT_970;
6965 pcc->bfd_mach = bfd_mach_ppc64;
6966 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6967 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6968 POWERPC_FLAG_BUS_CLK;
6969}
6970
9d52e907
DG		 6971static void init_proc_POWER7 (CPUPPCState *env)
6972{
6973 gen_spr_ne_601(env);
6974 gen_spr_7xx(env);
6975 /* Time base */
6976 gen_tbl(env);
2e06214f
NW		 6977 /* Processor identification */
6978 spr_register(env, SPR_PIR, "PIR",
6979 SPR_NOACCESS, SPR_NOACCESS,
6980 &spr_read_generic, &spr_write_pir,
6981 0x00000000);
9d52e907
DG		 6982#if !defined(CONFIG_USER_ONLY)
6983 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
d67d40ea
DG		 6984 spr_register_kvm(env, SPR_PURR, "PURR",
6985 &spr_read_purr, SPR_NOACCESS,
6986 &spr_read_purr, SPR_NOACCESS,
6987 KVM_REG_PPC_PURR, 0x00000000);
6988 spr_register_kvm(env, SPR_SPURR, "SPURR",
6989 &spr_read_purr, SPR_NOACCESS,
6990 &spr_read_purr, SPR_NOACCESS,
6991 KVM_REG_PPC_SPURR, 0x00000000);
697ab892
DG		 6992 spr_register(env, SPR_CFAR, "SPR_CFAR",
6993 SPR_NOACCESS, SPR_NOACCESS,
6994 &spr_read_cfar, &spr_write_cfar,
6995 0x00000000);
d67d40ea
DG		 6996 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6997 SPR_NOACCESS, SPR_NOACCESS,
6998 &spr_read_generic, &spr_write_generic,
6999 KVM_REG_PPC_DSCR, 0x00000000);
702763fa
DG		 7000 spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
7001 SPR_NOACCESS, SPR_NOACCESS,
7002 &spr_read_generic, &spr_write_generic,
7003 KVM_REG_PPC_MMCRA, 0x00000000);
7004 spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
7005 SPR_NOACCESS, SPR_NOACCESS,
7006 &spr_read_generic, &spr_write_generic,
7007 KVM_REG_PPC_PMC5, 0x00000000);
7008 spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
7009 SPR_NOACCESS, SPR_NOACCESS,
7010 &spr_read_generic, &spr_write_generic,
7011 KVM_REG_PPC_PMC6, 0x00000000);
9d52e907 7012#endif /* !CONFIG_USER_ONLY */
f80872e2 7013 gen_spr_amr(env);
9d52e907
DG		 7014 /* XXX : not implemented */
7015 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7016 SPR_NOACCESS, SPR_NOACCESS,
7017 &spr_read_generic, &spr_write_generic,
7018 0x80800000);
7019 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7020 SPR_NOACCESS, SPR_NOACCESS,
7021 &spr_read_generic, &spr_write_generic,
7022 0x80800000);
7023 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7024 &spr_read_generic, &spr_write_generic,
7025 &spr_read_generic, &spr_write_generic,
7026 0x00000000);
04559d52
AB		 7027 spr_register(env, SPR_PPR, "PPR",
7028 &spr_read_generic, &spr_write_generic,
7029 &spr_read_generic, &spr_write_generic,
7030 0x00000000);
6cd8712c
GK		 7031 /* Logical partitionning */
7032 spr_register_kvm(env, SPR_LPCR, "LPCR",
7033 SPR_NOACCESS, SPR_NOACCESS,
7034 &spr_read_generic, &spr_write_generic,
7035 KVM_REG_PPC_LPCR, 0x00000000);
9d52e907
DG		 7036#if !defined(CONFIG_USER_ONLY)
7037 env->slb_nr = 32;
7038#endif
7039 init_excp_POWER7(env);
7040 env->dcache_line_size = 128;
7041 env->icache_line_size = 128;
0cbad81f 7042
9d52e907
DG		 7043 /* Allocate hardware IRQ controller */
7044 ppcPOWER7_irq_init(env);
7045 /* Can't find information on what this should be on reset. This
7046 * value is the one used by 74xx processors. */
7047 vscr_init(env, 0x00010000);
7048}
9d52e907 7049
7856e3a4
AF		 7050POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7051{
ca5dff0a 7052 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 7053 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7054
793826cd 7055 dc->fw_name = "PowerPC,POWER7";
ca5dff0a 7056 dc->desc = "POWER7";
3bc9ccc0
AK		 7057 pcc->pvr = CPU_POWERPC_POWER7_BASE;
7058 pcc->pvr_mask = CPU_POWERPC_POWER7_MASK;
7856e3a4
AF		 7059 pcc->init_proc = init_proc_POWER7;
7060 pcc->check_pow = check_pow_nocheck;
e71ec2e9 7061 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
53116ebf
AF		 7062 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7063 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7064 PPC_FLOAT_STFIWX |
7065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7066 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7068 PPC_64B | PPC_ALTIVEC |
7069 PPC_SEGMENT_64B | PPC_SLBI |
7070 PPC_POPCNTB | PPC_POPCNTWD;
9c2627b0 7071 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
1f29871c 7072 pcc->msr_mask = 0x800000000284FF37ULL;
ba9fd9f1 7073 pcc->mmu_model = POWERPC_MMU_2_06;
b632a148
DG		 7074#if defined(CONFIG_SOFTMMU)
7075 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
b650d6a2
AK		 7076#endif
7077 pcc->excp_model = POWERPC_EXCP_POWER7;
7078 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7079 pcc->bfd_mach = bfd_mach_ppc64;
7080 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7081 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7082 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7083 POWERPC_FLAG_VSX;
7084 pcc->l1_dcache_size = 0x8000;
7085 pcc->l1_icache_size = 0x8000;
7086}
7087
7088POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
7089{
7090 DeviceClass *dc = DEVICE_CLASS(oc);
7091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7092
7093 dc->fw_name = "PowerPC,POWER7+";
7094 dc->desc = "POWER7+";
7095 pcc->pvr = CPU_POWERPC_POWER7P_BASE;
7096 pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
7097 pcc->init_proc = init_proc_POWER7;
7098 pcc->check_pow = check_pow_nocheck;
7099 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7100 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7101 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7102 PPC_FLOAT_STFIWX |
7103 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7104 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7105 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7106 PPC_64B | PPC_ALTIVEC |
7107 PPC_SEGMENT_64B | PPC_SLBI |
7108 PPC_POPCNTB | PPC_POPCNTWD;
7109 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
7110 pcc->msr_mask = 0x800000000204FF37ULL;
7111 pcc->mmu_model = POWERPC_MMU_2_06;
7112#if defined(CONFIG_SOFTMMU)
7113 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
b632a148 7114#endif
ba9fd9f1
AF		 7115 pcc->excp_model = POWERPC_EXCP_POWER7;
7116 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7117 pcc->bfd_mach = bfd_mach_ppc64;
7118 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7119 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
74f23997
TM		 7120 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7121 POWERPC_FLAG_VSX;
0cbad81f
DG		 7122 pcc->l1_dcache_size = 0x8000;
7123 pcc->l1_icache_size = 0x8000;
7856e3a4 7124}
8d43ea1c
PS		 7125
7126POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7127{
7128 DeviceClass *dc = DEVICE_CLASS(oc);
7129 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7130
793826cd 7131 dc->fw_name = "PowerPC,POWER8";
8d43ea1c 7132 dc->desc = "POWER8";
3bc9ccc0
AK		 7133 pcc->pvr = CPU_POWERPC_POWER8_BASE;
7134 pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
8d43ea1c
PS		 7135 pcc->init_proc = init_proc_POWER7;
7136 pcc->check_pow = check_pow_nocheck;
7137 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7138 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7139 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7140 PPC_FLOAT_STFIWX |
7141 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7142 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7143 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7144 PPC_64B | PPC_ALTIVEC |
7145 PPC_SEGMENT_64B | PPC_SLBI |
7146 PPC_POPCNTB | PPC_POPCNTWD;
7147 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
1f29871c 7148 pcc->msr_mask = 0x800000000284FF36ULL;
8d43ea1c
PS		 7149 pcc->mmu_model = POWERPC_MMU_2_06;
7150#if defined(CONFIG_SOFTMMU)
7151 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7152#endif
7153 pcc->excp_model = POWERPC_EXCP_POWER7;
7154 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7155 pcc->bfd_mach = bfd_mach_ppc64;
7156 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7157 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
74f23997
TM		 7158 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7159 POWERPC_FLAG_VSX;
8d43ea1c
PS		 7160 pcc->l1_dcache_size = 0x8000;
7161 pcc->l1_icache_size = 0x8000;
7162}
a750fc0b
JM		 7163#endif /* defined (TARGET_PPC64) */
7164
fd5ed418 7165
a750fc0b 7166/*****************************************************************************/
60b14d95 7167/* Generic CPU instantiation routine */
cfe34f44 7168static void init_ppc_proc(PowerPCCPU *cpu)
a750fc0b 7169{
cfe34f44
AF		 7170 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7171 CPUPPCState *env = &cpu->env;
a750fc0b 7172#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 7173 int i;
7174
a750fc0b 7175 env->irq_inputs = NULL;
e1833e1f
JM		 7176 /* Set all exception vectors to an invalid address */
7177 for (i = 0; i < POWERPC_EXCP_NB; i++)
7178 env->excp_vectors[i] = (target_ulong)(-1ULL);
e1833e1f
JM		 7179 env->ivor_mask = 0x00000000;
7180 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 7181 /* Default MMU definitions */
7182 env->nb_BATs = 0;
7183 env->nb_tlb = 0;
7184 env->nb_ways = 0;
1c53accc 7185 env->tlb_type = TLB_NONE;
f2e63a42 7186#endif
a750fc0b
JM		 7187 /* Register SPR common to all PowerPC implementations */
7188 gen_spr_generic(env);
7189 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 7190 /* Linux permits userspace to read PVR */
7191#if defined(CONFIG_LINUX_USER)
7192 &spr_read_generic,
7193#else
7194 SPR_NOACCESS,
7195#endif
7196 SPR_NOACCESS,
a750fc0b 7197 &spr_read_generic, SPR_NOACCESS,
cfe34f44 7198 pcc->pvr);
80d11f44 7199 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
cfe34f44
AF		 7200 if (pcc->svr != POWERPC_SVR_NONE) {
7201 if (pcc->svr & POWERPC_SVR_E500) {
80d11f44
JM		 7202 spr_register(env, SPR_E500_SVR, "SVR",
7203 SPR_NOACCESS, SPR_NOACCESS,
7204 &spr_read_generic, SPR_NOACCESS,
cfe34f44 7205 pcc->svr & ~POWERPC_SVR_E500);
80d11f44
JM		 7206 } else {
7207 spr_register(env, SPR_SVR, "SVR",
7208 SPR_NOACCESS, SPR_NOACCESS,
7209 &spr_read_generic, SPR_NOACCESS,
cfe34f44 7210 pcc->svr);
80d11f44
JM		 7211 }
7212 }
a750fc0b 7213 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
cfe34f44 7214 (*pcc->init_proc)(env);
2cf3eb6d 7215
25ba3a68
JM		 7216 /* MSR bits & flags consistency checks */
7217 if (env->msr_mask & (1 << 25)) {
7218 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7219 case POWERPC_FLAG_SPE:
7220 case POWERPC_FLAG_VRE:
7221 break;
7222 default:
7223 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7224 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7225 exit(1);
7226 }
7227 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7228 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7229 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7230 exit(1);
7231 }
7232 if (env->msr_mask & (1 << 17)) {
7233 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7234 case POWERPC_FLAG_TGPR:
7235 case POWERPC_FLAG_CE:
7236 break;
7237 default:
7238 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7239 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7240 exit(1);
7241 }
7242 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7243 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7244 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7245 exit(1);
7246 }
7247 if (env->msr_mask & (1 << 10)) {
7248 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7249 POWERPC_FLAG_UBLE)) {
7250 case POWERPC_FLAG_SE:
7251 case POWERPC_FLAG_DWE:
7252 case POWERPC_FLAG_UBLE:
7253 break;
7254 default:
7255 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7256 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7257 "POWERPC_FLAG_UBLE\n");
7258 exit(1);
7259 }
7260 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7261 POWERPC_FLAG_UBLE)) {
7262 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7263 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7264 "POWERPC_FLAG_UBLE\n");
7265 exit(1);
7266 }
7267 if (env->msr_mask & (1 << 9)) {
7268 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7269 case POWERPC_FLAG_BE:
7270 case POWERPC_FLAG_DE:
7271 break;
7272 default:
7273 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7274 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7275 exit(1);
7276 }
7277 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7278 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7279 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7280 exit(1);
7281 }
7282 if (env->msr_mask & (1 << 2)) {
7283 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7284 case POWERPC_FLAG_PX:
7285 case POWERPC_FLAG_PMM:
7286 break;
7287 default:
7288 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7289 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7290 exit(1);
7291 }
7292 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7293 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7294 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7295 exit(1);
7296 }
4018bae9
JM		 7297 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7298 fprintf(stderr, "PowerPC flags inconsistency\n"
7299 "Should define the time-base and decrementer clock source\n");
7300 exit(1);
7301 }
a750fc0b 7302 /* Allocate TLBs buffer when needed */
f2e63a42 7303#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 7304 if (env->nb_tlb != 0) {
7305 int nb_tlb = env->nb_tlb;
7306 if (env->id_tlbs != 0)
7307 nb_tlb *= 2;
1c53accc
AG		 7308 switch (env->tlb_type) {
7309 case TLB_6XX:
7267c094 7310 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 7311 break;
7312 case TLB_EMB:
7267c094 7313 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 7314 break;
7315 case TLB_MAS:
7267c094 7316 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 7317 break;
7318 }
a750fc0b
JM		 7319 /* Pre-compute some useful values */
7320 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7321 }
a750fc0b
JM		 7322 if (env->irq_inputs == NULL) {
7323 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5cbdb3a3 7324 " Attempt QEMU to crash very soon !\n");
a750fc0b
JM		 7325 }
7326#endif
2f462816
JM		 7327 if (env->check_pow == NULL) {
7328 fprintf(stderr, "WARNING: no power management check handler "
7329 "registered.\n"
5cbdb3a3 7330 " Attempt QEMU to crash very soon !\n");
2f462816 7331 }
a750fc0b
JM		 7332}
7333
7334#if defined(PPC_DUMP_CPU)
7335static void dump_ppc_sprs (CPUPPCState *env)
7336{
7337 ppc_spr_t *spr;
7338#if !defined(CONFIG_USER_ONLY)
7339 uint32_t sr, sw;
7340#endif
7341 uint32_t ur, uw;
7342 int i, j, n;
7343
7344 printf("Special purpose registers:\n");
7345 for (i = 0; i < 32; i++) {
7346 for (j = 0; j < 32; j++) {
7347 n = (i << 5) | j;
7348 spr = &env->spr_cb[n];
7349 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7350 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7351#if !defined(CONFIG_USER_ONLY)
7352 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7353 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7354 if (sw || sr || uw || ur) {
7355 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7356 (i << 5) | j, (i << 5) | j, spr->name,
7357 sw ? 'w' : '-', sr ? 'r' : '-',
7358 uw ? 'w' : '-', ur ? 'r' : '-');
7359 }
7360#else
7361 if (uw || ur) {
7362 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7363 (i << 5) | j, (i << 5) | j, spr->name,
7364 uw ? 'w' : '-', ur ? 'r' : '-');
7365 }
7366#endif
7367 }
7368 }
7369 fflush(stdout);
7370 fflush(stderr);
7371}
7372#endif
7373
7374/*****************************************************************************/
7375#include <stdlib.h>
7376#include <string.h>
7377
a750fc0b
JM		 7378/* Opcode types */
7379enum {
7380 PPC_DIRECT = 0, /* Opcode routine */
7381 PPC_INDIRECT = 1, /* Indirect opcode table */
7382};
7383
7384static inline int is_indirect_opcode (void *handler)
7385{
5724753e 7386 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
a750fc0b
JM		 7387}
7388
c227f099 7389static inline opc_handler_t **ind_table(void *handler)
a750fc0b 7390{
5724753e 7391 return (opc_handler_t **)((uintptr_t)handler & ~3);
a750fc0b
JM		 7392}
7393
7394/* Instruction table creation */
7395/* Opcodes tables creation */
c227f099 7396static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 7397{
7398 int i;
7399
7400 for (i = 0; i < len; i++)
7401 table[i] = &invalid_handler;
7402}
7403
c227f099 7404static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 7405{
c227f099 7406 opc_handler_t **tmp;
a750fc0b 7407
b048960f 7408 tmp = g_malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 7409 fill_new_table(tmp, 0x20);
5724753e 7410 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
a750fc0b
JM		 7411
7412 return 0;
7413}
7414
c227f099
AL		 7415static int insert_in_table (opc_handler_t **table, unsigned char idx,
7416 opc_handler_t *handler)
a750fc0b
JM		 7417{
7418 if (table[idx] != &invalid_handler)
7419 return -1;
7420 table[idx] = handler;
7421
7422 return 0;
7423}
7424
c227f099
AL		 7425static int register_direct_insn (opc_handler_t **ppc_opcodes,
7426 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 7427{
7428 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7429 printf("*** ERROR: opcode %02x already assigned in main "
7430 "opcode table\n", idx);
4c1b1bfe
JM		 7431#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7432 printf(" Registered handler '%s' - new handler '%s'\n",
7433 ppc_opcodes[idx]->oname, handler->oname);
7434#endif
a750fc0b
JM		 7435 return -1;
7436 }
7437
7438 return 0;
7439}
7440
c227f099 7441static int register_ind_in_table (opc_handler_t **table,
a750fc0b 7442 unsigned char idx1, unsigned char idx2,
c227f099 7443 opc_handler_t *handler)
a750fc0b
JM		 7444{
7445 if (table[idx1] == &invalid_handler) {
7446 if (create_new_table(table, idx1) < 0) {
7447 printf("*** ERROR: unable to create indirect table "
7448 "idx=%02x\n", idx1);
7449 return -1;
7450 }
7451 } else {
7452 if (!is_indirect_opcode(table[idx1])) {
7453 printf("*** ERROR: idx %02x already assigned to a direct "
7454 "opcode\n", idx1);
4c1b1bfe
JM		 7455#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7456 printf(" Registered handler '%s' - new handler '%s'\n",
7457 ind_table(table[idx1])[idx2]->oname, handler->oname);
7458#endif
a750fc0b
JM		 7459 return -1;
7460 }
3a607854 7461 }
a750fc0b
JM		 7462 if (handler != NULL &&
7463 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7464 printf("*** ERROR: opcode %02x already assigned in "
7465 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 7466#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7467 printf(" Registered handler '%s' - new handler '%s'\n",
7468 ind_table(table[idx1])[idx2]->oname, handler->oname);
7469#endif
a750fc0b 7470 return -1;
3a607854 7471 }
a750fc0b
JM		 7472
7473 return 0;
7474}
7475
c227f099 7476static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 7477 unsigned char idx1, unsigned char idx2,
c227f099 7478 opc_handler_t *handler)
a750fc0b
JM		 7479{
7480 int ret;
7481
7482 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7483
7484 return ret;
7485}
7486
c227f099 7487static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 7488 unsigned char idx1, unsigned char idx2,
c227f099 7489 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 7490{
7491 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7492 printf("*** ERROR: unable to join indirect table idx "
7493 "[%02x-%02x]\n", idx1, idx2);
7494 return -1;
7495 }
7496 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7497 handler) < 0) {
7498 printf("*** ERROR: unable to insert opcode "
7499 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7500 return -1;
7501 }
7502
7503 return 0;
7504}
7505
c227f099 7506static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 7507{
7508 if (insn->opc2 != 0xFF) {
7509 if (insn->opc3 != 0xFF) {
7510 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7511 insn->opc3, &insn->handler) < 0)
7512 return -1;
7513 } else {
7514 if (register_ind_insn(ppc_opcodes, insn->opc1,
7515 insn->opc2, &insn->handler) < 0)
7516 return -1;
7517 }
7518 } else {
7519 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7520 return -1;
7521 }
7522
7523 return 0;
7524}
7525
c227f099 7526static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 7527{
7528 int i, count, tmp;
7529
7530 for (i = 0, count = 0; i < len; i++) {
7531 /* Consistency fixup */
7532 if (table[i] == NULL)
7533 table[i] = &invalid_handler;
7534 if (table[i] != &invalid_handler) {
7535 if (is_indirect_opcode(table[i])) {
c227f099 7536 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 7537 if (tmp == 0) {
7538 free(table[i]);
7539 table[i] = &invalid_handler;
7540 } else {
7541 count++;
7542 }
7543 } else {
7544 count++;
7545 }
7546 }
7547 }
7548
7549 return count;
7550}
7551
c227f099 7552static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 7553{
c227f099 7554 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 7555 printf("*** WARNING: no opcode defined !\n");
7556}
7557
7558/*****************************************************************************/
2985b86b 7559static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
a750fc0b 7560{
2985b86b
AF		 7561 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7562 CPUPPCState *env = &cpu->env;
c227f099 7563 opcode_t *opc;
a750fc0b
JM		 7564
7565 fill_new_table(env->opcodes, 0x40);
5c55ff99 7566 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
cfe34f44
AF		 7567 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7568 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
a750fc0b 7569 if (register_insn(env->opcodes, opc) < 0) {
2985b86b 7570 error_setg(errp, "ERROR initializing PowerPC instruction "
312fd5f2 7571 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
2985b86b
AF		 7572 opc->opc3);
7573 return;
a750fc0b
JM		 7574 }
7575 }
7576 }
c227f099 7577 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 7578 fflush(stdout);
7579 fflush(stderr);
a750fc0b
JM		 7580}
7581
7582#if defined(PPC_DUMP_CPU)
25ba3a68 7583static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 7584{
c227f099 7585 opc_handler_t **table, *handler;
b55266b5 7586 const char *p, *q;
a750fc0b
JM		 7587 uint8_t opc1, opc2, opc3;
7588
7589 printf("Instructions set:\n");
7590 /* opc1 is 6 bits long */
7591 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7592 table = env->opcodes;
7593 handler = table[opc1];
7594 if (is_indirect_opcode(handler)) {
7595 /* opc2 is 5 bits long */
7596 for (opc2 = 0; opc2 < 0x20; opc2++) {
7597 table = env->opcodes;
7598 handler = env->opcodes[opc1];
7599 table = ind_table(handler);
7600 handler = table[opc2];
7601 if (is_indirect_opcode(handler)) {
7602 table = ind_table(handler);
7603 /* opc3 is 5 bits long */
7604 for (opc3 = 0; opc3 < 0x20; opc3++) {
7605 handler = table[opc3];
7606 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 7607 /* Special hack to properly dump SPE insns */
7608 p = strchr(handler->oname, '_');
7609 if (p == NULL) {
7610 printf("INSN: %02x %02x %02x (%02d %04d) : "
7611 "%s\n",
7612 opc1, opc2, opc3, opc1,
7613 (opc3 << 5) | opc2,
7614 handler->oname);
7615 } else {
7616 q = "speundef";
7617 if ((p - handler->oname) != strlen(q) ||
7618 memcmp(handler->oname, q, strlen(q)) != 0) {
7619 /* First instruction */
7620 printf("INSN: %02x %02x %02x (%02d %04d) : "
7621 "%.*s\n",
7622 opc1, opc2 << 1, opc3, opc1,
7623 (opc3 << 6) | (opc2 << 1),
7624 (int)(p - handler->oname),
7625 handler->oname);
7626 }
7627 if (strcmp(p + 1, q) != 0) {
7628 /* Second instruction */
7629 printf("INSN: %02x %02x %02x (%02d %04d) : "
7630 "%s\n",
7631 opc1, (opc2 << 1) | 1, opc3, opc1,
7632 (opc3 << 6) | (opc2 << 1) | 1,
7633 p + 1);
7634 }
7635 }
a750fc0b
JM		 7636 }
7637 }
7638 } else {
7639 if (handler->handler != &gen_invalid) {
7640 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7641 opc1, opc2, opc1, opc2, handler->oname);
7642 }
7643 }
7644 }
7645 } else {
7646 if (handler->handler != &gen_invalid) {
7647 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7648 opc1, opc1, handler->oname);
7649 }
7650 }
7651 }
7652}
3a607854 7653#endif
a750fc0b 7654
1328c2bf 7655static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 7656{
7657 if (n < 32) {
7658 stfq_p(mem_buf, env->fpr[n]);
7659 return 8;
7660 }
7661 if (n == 32) {
5a576fb3 7662 stl_p(mem_buf, env->fpscr);
24951522
AJ		 7663 return 4;
7664 }
7665 return 0;
7666}
7667
1328c2bf 7668static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 7669{
7670 if (n < 32) {
7671 env->fpr[n] = ldfq_p(mem_buf);
7672 return 8;
7673 }
7674 if (n == 32) {
d6478bc7 7675 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
24951522
AJ		 7676 return 4;
7677 }
7678 return 0;
7679}
7680
1328c2bf 7681static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 7682{
7683 if (n < 32) {
e2542fe2 7684#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 7685 stq_p(mem_buf, env->avr[n].u64[0]);
7686 stq_p(mem_buf+8, env->avr[n].u64[1]);
7687#else
7688 stq_p(mem_buf, env->avr[n].u64[1]);
7689 stq_p(mem_buf+8, env->avr[n].u64[0]);
7690#endif
7691 return 16;
7692 }
70976a79 7693 if (n == 32) {
b4f8d821
AJ		 7694 stl_p(mem_buf, env->vscr);
7695 return 4;
7696 }
70976a79 7697 if (n == 33) {
b4f8d821
AJ		 7698 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7699 return 4;
7700 }
7701 return 0;
7702}
7703
1328c2bf 7704static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 7705{
7706 if (n < 32) {
e2542fe2 7707#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 7708 env->avr[n].u64[0] = ldq_p(mem_buf);
7709 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7710#else
7711 env->avr[n].u64[1] = ldq_p(mem_buf);
7712 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7713#endif
7714 return 16;
7715 }
70976a79 7716 if (n == 32) {
b4f8d821
AJ		 7717 env->vscr = ldl_p(mem_buf);
7718 return 4;
7719 }
70976a79 7720 if (n == 33) {
b4f8d821
AJ		 7721 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7722 return 4;
7723 }
7724 return 0;
7725}
7726
1328c2bf 7727static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 7728{
7729 if (n < 32) {
7730#if defined(TARGET_PPC64)
7731 stl_p(mem_buf, env->gpr[n] >> 32);
7732#else
7733 stl_p(mem_buf, env->gprh[n]);
7734#endif
7735 return 4;
7736 }
70976a79 7737 if (n == 32) {
688890f7
AJ		 7738 stq_p(mem_buf, env->spe_acc);
7739 return 8;
7740 }
70976a79 7741 if (n == 33) {
d34defbc 7742 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 7743 return 4;
7744 }
7745 return 0;
7746}
7747
1328c2bf 7748static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 7749{
7750 if (n < 32) {
7751#if defined(TARGET_PPC64)
7752 target_ulong lo = (uint32_t)env->gpr[n];
7753 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7754 env->gpr[n] = lo | hi;
7755#else
7756 env->gprh[n] = ldl_p(mem_buf);
7757#endif
7758 return 4;
7759 }
70976a79 7760 if (n == 32) {
688890f7
AJ		 7761 env->spe_acc = ldq_p(mem_buf);
7762 return 8;
7763 }
70976a79 7764 if (n == 33) {
d34defbc 7765 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 7766 return 4;
7767 }
7768 return 0;
7769}
7770
55e5c285 7771static int ppc_fixup_cpu(PowerPCCPU *cpu)
12b1143b 7772{
55e5c285
AF		 7773 CPUPPCState *env = &cpu->env;
7774
12b1143b
DG		 7775 /* TCG doesn't (yet) emulate some groups of instructions that
7776 * are implemented on some otherwise supported CPUs (e.g. VSX
7777 * and decimal floating point instructions on POWER7). We
7778 * remove unsupported instruction groups from the cpu state's
7779 * instruction masks and hope the guest can cope. For at
7780 * least the pseries machine, the unavailability of these
7781 * instructions can be advertised to the guest via the device
7782 * tree. */
7783 if ((env->insns_flags & ~PPC_TCG_INSNS)
7784 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7785 fprintf(stderr, "Warning: Disabling some instructions which are not "
7786 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7787 env->insns_flags & ~PPC_TCG_INSNS,
7788 env->insns_flags2 & ~PPC_TCG_INSNS2);
7789 }
7790 env->insns_flags &= PPC_TCG_INSNS;
7791 env->insns_flags2 &= PPC_TCG_INSNS2;
7792 return 0;
7793}
7794
292363e1
AF		 7795static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
7796{
7797#ifdef TARGET_PPCEMB
7798 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
7799 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
7800 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
7801#else
7802 return true;
7803#endif
7804}
7805
4776ce60 7806static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
a750fc0b 7807{
22169d41 7808 CPUState *cs = CPU(dev);
4776ce60 7809 PowerPCCPU *cpu = POWERPC_CPU(dev);
2985b86b 7810 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2985b86b 7811 Error *local_err = NULL;
fe828a4d
MQ		 7812#if !defined(CONFIG_USER_ONLY)
7813 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7814#endif
7815
7816#if !defined(CONFIG_USER_ONLY)
7817 if (smp_threads > max_smt) {
5e95acc8
AF		 7818 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7819 max_smt, kvm_enabled() ? "KVM" : "TCG");
7820 return;
fe828a4d
MQ		 7821 }
7822#endif
4656e1f0 7823
12b1143b 7824 if (kvm_enabled()) {
55e5c285 7825 if (kvmppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 7826 error_setg(errp, "Unable to virtualize selected CPU with KVM");
7827 return;
12b1143b 7828 }
96b3bfa0 7829 } else if (tcg_enabled()) {
55e5c285 7830 if (ppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 7831 error_setg(errp, "Unable to emulate selected CPU with TCG");
7832 return;
12b1143b
DG		 7833 }
7834 }
7835
4d7fb187 7836#if defined(TARGET_PPCEMB)
292363e1
AF		 7837 if (!ppc_cpu_is_valid(pcc)) {
7838 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
4d7fb187
AF		 7839 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7840 "or choose another CPU model.");
7841 return;
7842 }
7843#endif
7844
2985b86b
AF		 7845 create_ppc_opcodes(cpu, &local_err);
7846 if (local_err != NULL) {
7847 error_propagate(errp, local_err);
7848 return;
7849 }
cfe34f44 7850 init_ppc_proc(cpu);
24951522 7851
cfe34f44 7852 if (pcc->insns_flags & PPC_FLOAT) {
22169d41 7853 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
24951522
AJ		 7854 33, "power-fpu.xml", 0);
7855 }
cfe34f44 7856 if (pcc->insns_flags & PPC_ALTIVEC) {
22169d41 7857 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
b4f8d821
AJ		 7858 34, "power-altivec.xml", 0);
7859 }
cfe34f44 7860 if (pcc->insns_flags & PPC_SPE) {
22169d41 7861 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
688890f7
AJ		 7862 34, "power-spe.xml", 0);
7863 }
7864
14a10fc3
AF		 7865 qemu_init_vcpu(cs);
7866
4776ce60
AF		 7867 pcc->parent_realize(dev, errp);
7868
a750fc0b 7869#if defined(PPC_DUMP_CPU)
3a607854 7870 {
22169d41 7871 CPUPPCState *env = &cpu->env;
b55266b5 7872 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 7873 switch (env->mmu_model) {
7874 case POWERPC_MMU_32B:
7875 mmu_model = "PowerPC 32";
7876 break;
a750fc0b
JM		 7877 case POWERPC_MMU_SOFT_6xx:
7878 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7879 break;
7880 case POWERPC_MMU_SOFT_74xx:
7881 mmu_model = "PowerPC 74xx with software driven TLBs";
7882 break;
7883 case POWERPC_MMU_SOFT_4xx:
7884 mmu_model = "PowerPC 4xx with software driven TLBs";
7885 break;
7886 case POWERPC_MMU_SOFT_4xx_Z:
7887 mmu_model = "PowerPC 4xx with software driven TLBs "
7888 "and zones protections";
7889 break;
b4095fed
JM		 7890 case POWERPC_MMU_REAL:
7891 mmu_model = "PowerPC real mode only";
7892 break;
7893 case POWERPC_MMU_MPC8xx:
7894 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 7895 break;
7896 case POWERPC_MMU_BOOKE:
7897 mmu_model = "PowerPC BookE";
7898 break;
01662f3e
AG		 7899 case POWERPC_MMU_BOOKE206:
7900 mmu_model = "PowerPC BookE 2.06";
a750fc0b 7901 break;
b4095fed
JM		 7902 case POWERPC_MMU_601:
7903 mmu_model = "PowerPC 601";
7904 break;
00af685f
JM		 7905#if defined (TARGET_PPC64)
7906 case POWERPC_MMU_64B:
7907 mmu_model = "PowerPC 64";
7908 break;
00af685f 7909#endif
a750fc0b
JM		 7910 default:
7911 mmu_model = "Unknown or invalid";
7912 break;
7913 }
7914 switch (env->excp_model) {
7915 case POWERPC_EXCP_STD:
7916 excp_model = "PowerPC";
7917 break;
7918 case POWERPC_EXCP_40x:
7919 excp_model = "PowerPC 40x";
7920 break;
7921 case POWERPC_EXCP_601:
7922 excp_model = "PowerPC 601";
7923 break;
7924 case POWERPC_EXCP_602:
7925 excp_model = "PowerPC 602";
7926 break;
7927 case POWERPC_EXCP_603:
7928 excp_model = "PowerPC 603";
7929 break;
7930 case POWERPC_EXCP_603E:
7931 excp_model = "PowerPC 603e";
7932 break;
7933 case POWERPC_EXCP_604:
7934 excp_model = "PowerPC 604";
7935 break;
7936 case POWERPC_EXCP_7x0:
7937 excp_model = "PowerPC 740/750";
7938 break;
7939 case POWERPC_EXCP_7x5:
7940 excp_model = "PowerPC 745/755";
7941 break;
7942 case POWERPC_EXCP_74xx:
7943 excp_model = "PowerPC 74xx";
7944 break;
a750fc0b
JM		 7945 case POWERPC_EXCP_BOOKE:
7946 excp_model = "PowerPC BookE";
7947 break;
00af685f
JM		 7948#if defined (TARGET_PPC64)
7949 case POWERPC_EXCP_970:
7950 excp_model = "PowerPC 970";
7951 break;
7952#endif
a750fc0b
JM		 7953 default:
7954 excp_model = "Unknown or invalid";
7955 break;
7956 }
7957 switch (env->bus_model) {
7958 case PPC_FLAGS_INPUT_6xx:
7959 bus_model = "PowerPC 6xx";
7960 break;
7961 case PPC_FLAGS_INPUT_BookE:
7962 bus_model = "PowerPC BookE";
7963 break;
7964 case PPC_FLAGS_INPUT_405:
7965 bus_model = "PowerPC 405";
7966 break;
a750fc0b
JM		 7967 case PPC_FLAGS_INPUT_401:
7968 bus_model = "PowerPC 401/403";
7969 break;
b4095fed
JM		 7970 case PPC_FLAGS_INPUT_RCPU:
7971 bus_model = "RCPU / MPC8xx";
7972 break;
00af685f
JM		 7973#if defined (TARGET_PPC64)
7974 case PPC_FLAGS_INPUT_970:
7975 bus_model = "PowerPC 970";
7976 break;
7977#endif
a750fc0b
JM		 7978 default:
7979 bus_model = "Unknown or invalid";
7980 break;
7981 }
7982 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
7983 " MMU model : %s\n",
a5100e75
AK		 7984 object_class_get_name(OBJECT_CLASS(pcc)),
7985 pcc->pvr, pcc->msr_mask, mmu_model);
f2e63a42 7986#if !defined(CONFIG_USER_ONLY)
a5100e75 7987 if (env->tlb.tlb6) {
a750fc0b
JM		 7988 printf(" %d %s TLB in %d ways\n",
7989 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
7990 env->nb_ways);
7991 }
f2e63a42 7992#endif
a750fc0b
JM		 7993 printf(" Exceptions model : %s\n"
7994 " Bus model : %s\n",
7995 excp_model, bus_model);
25ba3a68
JM		 7996 printf(" MSR features :\n");
7997 if (env->flags & POWERPC_FLAG_SPE)
7998 printf(" signal processing engine enable"
7999 "\n");
8000 else if (env->flags & POWERPC_FLAG_VRE)
8001 printf(" vector processor enable\n");
8002 if (env->flags & POWERPC_FLAG_TGPR)
8003 printf(" temporary GPRs\n");
8004 else if (env->flags & POWERPC_FLAG_CE)
8005 printf(" critical input enable\n");
8006 if (env->flags & POWERPC_FLAG_SE)
8007 printf(" single-step trace mode\n");
8008 else if (env->flags & POWERPC_FLAG_DWE)
8009 printf(" debug wait enable\n");
8010 else if (env->flags & POWERPC_FLAG_UBLE)
8011 printf(" user BTB lock enable\n");
8012 if (env->flags & POWERPC_FLAG_BE)
8013 printf(" branch-step trace mode\n");
8014 else if (env->flags & POWERPC_FLAG_DE)
8015 printf(" debug interrupt enable\n");
8016 if (env->flags & POWERPC_FLAG_PX)
8017 printf(" inclusive protection\n");
8018 else if (env->flags & POWERPC_FLAG_PMM)
8019 printf(" performance monitor mark\n");
8020 if (env->flags == POWERPC_FLAG_NONE)
8021 printf(" none\n");
4018bae9
JM		 8022 printf(" Time-base/decrementer clock source: %s\n",
8023 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
22169d41
AF		 8024 dump_ppc_insns(env);
8025 dump_ppc_sprs(env);
8026 fflush(stdout);
a750fc0b 8027 }
3a607854 8028#endif
a750fc0b 8029}
3fc6c082 8030
b048960f
AF		 8031static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
8032{
8033 PowerPCCPU *cpu = POWERPC_CPU(dev);
8034 CPUPPCState *env = &cpu->env;
8035 int i;
8036
8037 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8038 if (env->opcodes[i] != &invalid_handler) {
8039 g_free(env->opcodes[i]);
8040 }
8041 }
8042}
8043
2985b86b 8044static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
f0ad8c34 8045{
2985b86b
AF		 8046 ObjectClass *oc = (ObjectClass *)a;
8047 uint32_t pvr = *(uint32_t *)b;
8048 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8049
8050 /* -cpu host does a PVR lookup during construction */
8051 if (unlikely(strcmp(object_class_get_name(oc),
8052 TYPE_HOST_POWERPC_CPU) == 0)) {
8053 return -1;
f0ad8c34 8054 }
f0ad8c34 8055
292363e1 8056 if (!ppc_cpu_is_valid(pcc)) {
4d7fb187
AF		 8057 return -1;
8058 }
4d7fb187 8059
cfe34f44 8060 return pcc->pvr == pvr ? 0 : -1;
f0ad8c34
AG		 8061}
8062
2985b86b 8063PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
3fc6c082 8064{
2985b86b
AF		 8065 GSList *list, *item;
8066 PowerPCCPUClass *pcc = NULL;
be40edcd 8067
2985b86b
AF		 8068 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8069 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8070 if (item != NULL) {
8071 pcc = POWERPC_CPU_CLASS(item->data);
3fc6c082 8072 }
2985b86b
AF		 8073 g_slist_free(list);
8074
8075 return pcc;
8076}
8077
3bc9ccc0
AK		 8078static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8079{
8080 ObjectClass *oc = (ObjectClass *)a;
8081 uint32_t pvr = *(uint32_t *)b;
8082 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8083 gint ret;
8084
8085 /* -cpu host does a PVR lookup during construction */
8086 if (unlikely(strcmp(object_class_get_name(oc),
8087 TYPE_HOST_POWERPC_CPU) == 0)) {
8088 return -1;
8089 }
8090
292363e1 8091 if (!ppc_cpu_is_valid(pcc)) {
3bc9ccc0
AK		 8092 return -1;
8093 }
292363e1 8094
3bc9ccc0
AK		 8095 ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1);
8096
8097 return ret;
8098}
8099
8100PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8101{
8102 GSList *list, *item;
8103 PowerPCCPUClass *pcc = NULL;
8104
8105 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8106 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8107 if (item != NULL) {
8108 pcc = POWERPC_CPU_CLASS(item->data);
8109 }
8110 g_slist_free(list);
8111
8112 return pcc;
8113}
8114
2985b86b
AF		 8115static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8116{
8117 ObjectClass *oc = (ObjectClass *)a;
8118 const char *name = b;
4d7fb187 8119 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
ee4e83ed 8120
2985b86b 8121 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
292363e1 8122 ppc_cpu_is_valid(pcc) &&
2985b86b
AF		 8123 strcmp(object_class_get_name(oc) + strlen(name),
8124 "-" TYPE_POWERPC_CPU) == 0) {
8125 return 0;
8126 }
8127 return -1;
3fc6c082
FB		 8128}
8129
ee4e83ed 8130#include <ctype.h>
3fc6c082 8131
9761ad75
AG		 8132static ObjectClass *ppc_cpu_class_by_name(const char *name);
8133
8134static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
8135{
8136 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
8137
8138 /* Cache target class lookups in the alias table */
8139 if (!alias->oc) {
8140 alias->oc = ppc_cpu_class_by_name(alias->model);
8141 if (!alias->oc) {
8142 /* Fast check for non-existing aliases */
8143 alias->oc = invalid_class;
8144 }
8145 }
8146
8147 if (alias->oc == invalid_class) {
8148 return NULL;
8149 } else {
8150 return alias->oc;
8151 }
8152}
8153
2985b86b 8154static ObjectClass *ppc_cpu_class_by_name(const char *name)
ee4e83ed 8155{
2985b86b
AF		 8156 GSList *list, *item;
8157 ObjectClass *ret = NULL;
b55266b5 8158 const char *p;
2985b86b 8159 int i, len;
ee4e83ed
JM		 8160
8161 /* Check if the given name is a PVR */
8162 len = strlen(name);
8163 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8164 p = name + 2;
8165 goto check_pvr;
8166 } else if (len == 8) {
8167 p = name;
8168 check_pvr:
8169 for (i = 0; i < 8; i++) {
cd390083 8170 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 8171 break;
8172 }
2985b86b
AF		 8173 if (i == 8) {
8174 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8175 return ret;
f0ad8c34 8176 }
2985b86b 8177 }
f0ad8c34 8178
e9a96075 8179 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
fd5ed418 8180 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9761ad75 8181 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
fd5ed418
AF		 8182 }
8183 }
8184
2985b86b
AF		 8185 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8186 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8187 if (item != NULL) {
8188 ret = OBJECT_CLASS(item->data);
3fc6c082 8189 }
2985b86b 8190 g_slist_free(list);
ee4e83ed
JM		 8191
8192 return ret;
3fc6c082
FB		 8193}
8194
2985b86b 8195PowerPCCPU *cpu_ppc_init(const char *cpu_model)
3fc6c082 8196{
2985b86b 8197 PowerPCCPU *cpu;
2985b86b
AF		 8198 ObjectClass *oc;
8199 Error *err = NULL;
3fc6c082 8200
2985b86b
AF		 8201 oc = ppc_cpu_class_by_name(cpu_model);
8202 if (oc == NULL) {
8203 return NULL;
8204 }
f0ad8c34 8205
2985b86b 8206 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
2985b86b 8207
4776ce60 8208 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
2985b86b 8209 if (err != NULL) {
4a44d85e 8210 error_report("%s", error_get_pretty(err));
2985b86b 8211 error_free(err);
5c099537 8212 object_unref(OBJECT(cpu));
2985b86b
AF		 8213 return NULL;
8214 }
8215
8216 return cpu;
8217}
8218
8219/* Sort by PVR, ordering special case "host" last. */
8220static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8221{
8222 ObjectClass *oc_a = (ObjectClass *)a;
8223 ObjectClass *oc_b = (ObjectClass *)b;
8224 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8225 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8226 const char *name_a = object_class_get_name(oc_a);
8227 const char *name_b = object_class_get_name(oc_b);
8228
8229 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8230 return 1;
8231 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8232 return -1;
8233 } else {
8234 /* Avoid an integer overflow during subtraction */
cfe34f44 8235 if (pcc_a->pvr < pcc_b->pvr) {
2985b86b 8236 return -1;
cfe34f44 8237 } else if (pcc_a->pvr > pcc_b->pvr) {
2985b86b
AF		 8238 return 1;
8239 } else {
8240 return 0;
8241 }
8242 }
8243}
8244
8245static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8246{
8247 ObjectClass *oc = data;
8248 CPUListState *s = user_data;
8249 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
de400129
AF		 8250 const char *typename = object_class_get_name(oc);
8251 char *name;
55d3d1a4 8252 int i;
2985b86b 8253
292363e1 8254 if (!ppc_cpu_is_valid(pcc)) {
4d7fb187
AF		 8255 return;
8256 }
5ba4576b
AF		 8257 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8258 return;
8259 }
4d7fb187 8260
de400129
AF		 8261 name = g_strndup(typename,
8262 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b 8263 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
cfe34f44 8264 name, pcc->pvr);
e9a96075 8265 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9761ad75
AG		 8266 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8267 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
55d3d1a4
AF		 8268
8269 if (alias_oc != oc) {
8270 continue;
8271 }
8272 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8273 alias->alias, name);
8274 }
de400129 8275 g_free(name);
2985b86b
AF		 8276}
8277
8278void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8279{
8280 CPUListState s = {
8281 .file = f,
8282 .cpu_fprintf = cpu_fprintf,
8283 };
8284 GSList *list;
8285
8286 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8287 list = g_slist_sort(list, ppc_cpu_list_compare);
8288 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8289 g_slist_free(list);
fd5ed418 8290
5ba4576b
AF		 8291#ifdef CONFIG_KVM
8292 cpu_fprintf(f, "\n");
8293 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8294#endif
2985b86b
AF		 8295}
8296
8297static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8298{
8299 ObjectClass *oc = data;
8300 CpuDefinitionInfoList **first = user_data;
de400129 8301 const char *typename;
2985b86b
AF		 8302 CpuDefinitionInfoList *entry;
8303 CpuDefinitionInfo *info;
4d7fb187
AF		 8304 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8305
292363e1 8306 if (!ppc_cpu_is_valid(pcc)) {
4d7fb187
AF		 8307 return;
8308 }
2985b86b 8309
de400129 8310 typename = object_class_get_name(oc);
2985b86b 8311 info = g_malloc0(sizeof(*info));
de400129
AF		 8312 info->name = g_strndup(typename,
8313 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b
AF		 8314
8315 entry = g_malloc0(sizeof(*entry));
8316 entry->value = info;
8317 entry->next = *first;
8318 *first = entry;
3fc6c082 8319}
1d0cb67d 8320
76b64a7a 8321CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
70b7660a
AL		 8322{
8323 CpuDefinitionInfoList *cpu_list = NULL;
2985b86b 8324 GSList *list;
35e21d3f 8325 int i;
70b7660a 8326
2985b86b
AF		 8327 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8328 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8329 g_slist_free(list);
70b7660a 8330
e9a96075 8331 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9761ad75 8332 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
35e21d3f
AF		 8333 ObjectClass *oc;
8334 CpuDefinitionInfoList *entry;
8335 CpuDefinitionInfo *info;
8336
9761ad75 8337 oc = ppc_cpu_class_by_alias(alias);
35e21d3f
AF		 8338 if (oc == NULL) {
8339 continue;
8340 }
8341
8342 info = g_malloc0(sizeof(*info));
8343 info->name = g_strdup(alias->alias);
8344
8345 entry = g_malloc0(sizeof(*entry));
8346 entry->value = info;
8347 entry->next = cpu_list;
8348 cpu_list = entry;
8349 }
8350
2985b86b
AF		 8351 return cpu_list;
8352}
70b7660a 8353
f45748f1
AF		 8354static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
8355{
8356 PowerPCCPU *cpu = POWERPC_CPU(cs);
8357
8358 cpu->env.nip = value;
8359}
8360
1d0cb67d
AF		 8361/* CPUClass::reset() */
8362static void ppc_cpu_reset(CPUState *s)
8363{
8364 PowerPCCPU *cpu = POWERPC_CPU(s);
8365 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8366 CPUPPCState *env = &cpu->env;
a1389542
AF		 8367 target_ulong msr;
8368
1d0cb67d
AF		 8369 pcc->parent_reset(s);
8370
a1389542
AF		 8371 msr = (target_ulong)0;
8372 if (0) {
8373 /* XXX: find a suitable condition to enable the hypervisor mode */
8374 msr |= (target_ulong)MSR_HVB;
8375 }
8376 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8377 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8378 msr |= (target_ulong)1 << MSR_EP;
8379#if defined(DO_SINGLE_STEP) && 0
8380 /* Single step trace mode */
8381 msr |= (target_ulong)1 << MSR_SE;
8382 msr |= (target_ulong)1 << MSR_BE;
8383#endif
8384#if defined(CONFIG_USER_ONLY)
8385 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8386 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8387 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8388 msr |= (target_ulong)1 << MSR_PR;
a1389542 8389#endif
2cf3eb6d 8390
a1389542
AF		 8391#if defined(TARGET_PPC64)
8392 if (env->mmu_model & POWERPC_MMU_64) {
8393 env->msr |= (1ULL << MSR_SF);
8394 }
8395#endif
2cf3eb6d
FC		 8396
8397 hreg_store_msr(env, msr, 1);
8398
8399#if !defined(CONFIG_USER_ONLY)
8400 env->nip = env->hreset_vector | env->excp_prefix;
8401 if (env->mmu_model != POWERPC_MMU_REAL) {
8402 ppc_tlb_invalidate_all(env);
8403 }
8404#endif
8405
a1389542
AF		 8406 hreg_compute_hflags(env);
8407 env->reserve_addr = (target_ulong)-1ULL;
8408 /* Be sure no exception or interrupt is pending */
8409 env->pending_interrupts = 0;
8410 env->exception_index = POWERPC_EXCP_NONE;
8411 env->error_code = 0;
2b15811c
DG		 8412
8413#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1bfb37d1
DG		 8414 env->vpa_addr = 0;
8415 env->slb_shadow_addr = 0;
8416 env->slb_shadow_size = 0;
8417 env->dtl_addr = 0;
2b15811c
DG		 8418 env->dtl_size = 0;
8419#endif /* TARGET_PPC64 */
8420
a1389542
AF		 8421 /* Flush all TLBs */
8422 tlb_flush(env, 1);
1d0cb67d
AF		 8423}
8424
6cca7ad6
AF		 8425static void ppc_cpu_initfn(Object *obj)
8426{
c05efcb1 8427 CPUState *cs = CPU(obj);
6cca7ad6 8428 PowerPCCPU *cpu = POWERPC_CPU(obj);
2985b86b 8429 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6cca7ad6
AF		 8430 CPUPPCState *env = &cpu->env;
8431
c05efcb1 8432 cs->env_ptr = env;
6cca7ad6 8433 cpu_exec_init(env);
2985b86b 8434
cfe34f44
AF		 8435 env->msr_mask = pcc->msr_mask;
8436 env->mmu_model = pcc->mmu_model;
8437 env->excp_model = pcc->excp_model;
8438 env->bus_model = pcc->bus_model;
8439 env->insns_flags = pcc->insns_flags;
8440 env->insns_flags2 = pcc->insns_flags2;
8441 env->flags = pcc->flags;
8442 env->bfd_mach = pcc->bfd_mach;
8443 env->check_pow = pcc->check_pow;
2985b86b
AF		 8444
8445#if defined(TARGET_PPC64)
cfe34f44
AF		 8446 if (pcc->sps) {
8447 env->sps = *pcc->sps;
2985b86b
AF		 8448 } else if (env->mmu_model & POWERPC_MMU_64) {
8449 /* Use default sets of page sizes */
8450 static const struct ppc_segment_page_sizes defsps = {
8451 .sps = {
8452 { .page_shift = 12, /* 4K */
8453 .slb_enc = 0,
8454 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8455 },
8456 { .page_shift = 24, /* 16M */
8457 .slb_enc = 0x100,
8458 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8459 },
8460 },
8461 };
8462 env->sps = defsps;
8463 }
8464#endif /* defined(TARGET_PPC64) */
60925d26
AF		 8465
8466 if (tcg_enabled()) {
8467 ppc_translate_init();
8468 }
6cca7ad6
AF		 8469}
8470
1d0cb67d
AF		 8471static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8472{
8473 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8474 CPUClass *cc = CPU_CLASS(oc);
4776ce60
AF		 8475 DeviceClass *dc = DEVICE_CLASS(oc);
8476
8477 pcc->parent_realize = dc->realize;
3bc9ccc0
AK		 8478 pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
8479 pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
4776ce60 8480 dc->realize = ppc_cpu_realizefn;
b048960f 8481 dc->unrealize = ppc_cpu_unrealizefn;
1d0cb67d
AF		 8482
8483 pcc->parent_reset = cc->reset;
8484 cc->reset = ppc_cpu_reset;
2b8c2754
AF		 8485
8486 cc->class_by_name = ppc_cpu_class_by_name;
97a8ea5a 8487 cc->do_interrupt = ppc_cpu_do_interrupt;
878096ee
AF		 8488 cc->dump_state = ppc_cpu_dump_state;
8489 cc->dump_statistics = ppc_cpu_dump_statistics;
f45748f1 8490 cc->set_pc = ppc_cpu_set_pc;
5b50e790
AF		 8491 cc->gdb_read_register = ppc_cpu_gdb_read_register;
8492 cc->gdb_write_register = ppc_cpu_gdb_write_register;
00b941e5
AF		 8493#ifndef CONFIG_USER_ONLY
8494 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
a90db158 8495 cc->vmsd = &vmstate_ppc_cpu;
e62fbc54
AK		 8496#if defined(TARGET_PPC64)
8497 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
8498 cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote;
8499#endif
00b941e5 8500#endif
a0e372f0
AF		 8501
8502 cc->gdb_num_core_regs = 71;
5b24c641
AF		 8503#if defined(TARGET_PPC64)
8504 cc->gdb_core_xml_file = "power64-core.xml";
8505#else
8506 cc->gdb_core_xml_file = "power-core.xml";
8507#endif
3bbf37f2
AF		 8508
8509 dc->fw_name = "PowerPC,UNKNOWN";
1d0cb67d
AF		 8510}
8511
8512static const TypeInfo ppc_cpu_type_info = {
8513 .name = TYPE_POWERPC_CPU,
8514 .parent = TYPE_CPU,
8515 .instance_size = sizeof(PowerPCCPU),
6cca7ad6 8516 .instance_init = ppc_cpu_initfn,
2985b86b 8517 .abstract = true,
1d0cb67d
AF		 8518 .class_size = sizeof(PowerPCCPUClass),
8519 .class_init = ppc_cpu_class_init,
8520};
8521
8522static void ppc_cpu_register_types(void)
8523{
8524 type_register_static(&ppc_cpu_type_info);
8525}
8526
8527type_init(ppc_cpu_register_types)
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