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Fix PowerPC 64 stat and statfs structures definitions.
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
ee4e83ed 27#include "host-utils.h"
237c0af0 28
3fc6c082
FB		 29//#define PPC_DUMP_CPU
30//#define PPC_DEBUG_SPR
80d11f44
JM		 31//#define PPC_DUMP_SPR_ACCESSES
32#if defined(CONFIG_USER_ONLY)
33#define TODO_USER_ONLY 1
34#endif
3fc6c082
FB		 35
36struct ppc_def_t {
37 const unsigned char *name;
38 uint32_t pvr;
80d11f44 39 uint32_t svr;
0487d6a8 40 uint64_t insns_flags;
3fc6c082 41 uint64_t msr_mask;
7820dbf3
JM		 42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
d26bfc9a 45 uint32_t flags;
237c0af0 46 int bfd_mach;
a750fc0b 47 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 48 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 49};
50
e9df014c
JM		 51/* For user-mode emulation, we don't emulate any IRQ controller */
52#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 53#define PPC_IRQ_INIT_FN(name) \
54static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55{ \
e9df014c
JM		 56}
57#else
a750fc0b 58#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 59void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60#endif
a750fc0b 61
4e290a0b 62PPC_IRQ_INIT_FN(40x);
e9df014c 63PPC_IRQ_INIT_FN(6xx);
d0dfae6e 64PPC_IRQ_INIT_FN(970);
e9df014c 65
3fc6c082
FB		 66/* Generic callbacks:
67 * do nothing but store/retrieve spr value
68 */
04f20795 69#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 70static void spr_read_generic (void *opaque, int sprn)
71{
04f20795 72 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 73}
74
75static void spr_write_generic (void *opaque, int sprn)
76{
04f20795 77 gen_op_store_dump_spr(sprn);
3fc6c082 78}
04f20795
JM		 79#else
80static void spr_read_generic (void *opaque, int sprn)
a496775f 81{
04f20795 82 gen_op_load_spr(sprn);
a496775f
JM		 83}
84
04f20795 85static void spr_write_generic (void *opaque, int sprn)
a496775f 86{
04f20795 87 gen_op_store_spr(sprn);
a496775f 88}
04f20795 89#endif
a496775f
JM		 90
91#if !defined(CONFIG_USER_ONLY)
92static void spr_write_clear (void *opaque, int sprn)
93{
94 gen_op_mask_spr(sprn);
95}
96#endif
97
76a66253 98/* SPR common to all PowerPC */
3fc6c082
FB		 99/* XER */
100static void spr_read_xer (void *opaque, int sprn)
101{
102 gen_op_load_xer();
103}
104
105static void spr_write_xer (void *opaque, int sprn)
106{
107 gen_op_store_xer();
108}
109
110/* LR */
111static void spr_read_lr (void *opaque, int sprn)
112{
113 gen_op_load_lr();
114}
115
116static void spr_write_lr (void *opaque, int sprn)
117{
118 gen_op_store_lr();
119}
120
121/* CTR */
122static void spr_read_ctr (void *opaque, int sprn)
123{
124 gen_op_load_ctr();
125}
126
127static void spr_write_ctr (void *opaque, int sprn)
128{
129 gen_op_store_ctr();
130}
131
132/* User read access to SPR */
133/* USPRx */
134/* UMMCRx */
135/* UPMCx */
136/* USIA */
137/* UDECR */
138static void spr_read_ureg (void *opaque, int sprn)
139{
140 gen_op_load_spr(sprn + 0x10);
141}
142
76a66253 143/* SPR common to all non-embedded PowerPC */
3fc6c082 144/* DECR */
76a66253 145#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 146static void spr_read_decr (void *opaque, int sprn)
147{
148 gen_op_load_decr();
149}
150
151static void spr_write_decr (void *opaque, int sprn)
152{
153 gen_op_store_decr();
154}
76a66253 155#endif
3fc6c082 156
76a66253 157/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 158/* Time base */
159static void spr_read_tbl (void *opaque, int sprn)
160{
161 gen_op_load_tbl();
162}
163
76a66253 164static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 165{
76a66253 166 gen_op_load_tbu();
3fc6c082
FB		 167}
168
a062e36c
JM		 169__attribute__ (( unused ))
170static void spr_read_atbl (void *opaque, int sprn)
171{
172 gen_op_load_atbl();
173}
174
175__attribute__ (( unused ))
176static void spr_read_atbu (void *opaque, int sprn)
177{
178 gen_op_load_atbu();
179}
180
76a66253
JM		 181#if !defined(CONFIG_USER_ONLY)
182static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 183{
76a66253 184 gen_op_store_tbl();
3fc6c082
FB		 185}
186
187static void spr_write_tbu (void *opaque, int sprn)
188{
189 gen_op_store_tbu();
190}
a062e36c
JM		 191
192__attribute__ (( unused ))
193static void spr_write_atbl (void *opaque, int sprn)
194{
195 gen_op_store_atbl();
196}
197
198__attribute__ (( unused ))
199static void spr_write_atbu (void *opaque, int sprn)
200{
201 gen_op_store_atbu();
202}
76a66253 203#endif
3fc6c082 204
76a66253 205#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 206/* IBAT0U...IBAT0U */
207/* IBAT0L...IBAT7L */
208static void spr_read_ibat (void *opaque, int sprn)
209{
210 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
211}
212
213static void spr_read_ibat_h (void *opaque, int sprn)
214{
215 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
216}
217
218static void spr_write_ibatu (void *opaque, int sprn)
219{
3fc6c082 220 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 221}
222
223static void spr_write_ibatu_h (void *opaque, int sprn)
224{
3fc6c082 225 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 226}
227
228static void spr_write_ibatl (void *opaque, int sprn)
229{
3fc6c082 230 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 231}
232
233static void spr_write_ibatl_h (void *opaque, int sprn)
234{
3fc6c082 235 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 236}
237
238/* DBAT0U...DBAT7U */
239/* DBAT0L...DBAT7L */
240static void spr_read_dbat (void *opaque, int sprn)
241{
242 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
243}
244
245static void spr_read_dbat_h (void *opaque, int sprn)
246{
2e13d23a 247 gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
3fc6c082
FB		 248}
249
250static void spr_write_dbatu (void *opaque, int sprn)
251{
3fc6c082 252 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 253}
254
255static void spr_write_dbatu_h (void *opaque, int sprn)
256{
2e13d23a 257 gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
3fc6c082
FB		 258}
259
260static void spr_write_dbatl (void *opaque, int sprn)
261{
3fc6c082 262 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 263}
264
265static void spr_write_dbatl_h (void *opaque, int sprn)
266{
2e13d23a 267 gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
3fc6c082
FB		 268}
269
270/* SDR1 */
271static void spr_read_sdr1 (void *opaque, int sprn)
272{
273 gen_op_load_sdr1();
274}
275
276static void spr_write_sdr1 (void *opaque, int sprn)
277{
3fc6c082 278 gen_op_store_sdr1();
3fc6c082
FB		 279}
280
76a66253
JM		 281/* 64 bits PowerPC specific SPRs */
282/* ASR */
578bb252 283#if defined(TARGET_PPC64)
76a66253
JM		 284static void spr_read_asr (void *opaque, int sprn)
285{
286 gen_op_load_asr();
287}
288
289static void spr_write_asr (void *opaque, int sprn)
290{
76a66253 291 gen_op_store_asr();
76a66253
JM		 292}
293#endif
a750fc0b 294#endif
76a66253
JM		 295
296/* PowerPC 601 specific registers */
297/* RTC */
298static void spr_read_601_rtcl (void *opaque, int sprn)
299{
300 gen_op_load_601_rtcl();
301}
302
303static void spr_read_601_rtcu (void *opaque, int sprn)
304{
305 gen_op_load_601_rtcu();
306}
307
308#if !defined(CONFIG_USER_ONLY)
309static void spr_write_601_rtcu (void *opaque, int sprn)
310{
311 gen_op_store_601_rtcu();
312}
313
314static void spr_write_601_rtcl (void *opaque, int sprn)
315{
316 gen_op_store_601_rtcl();
317}
056401ea
JM		 318
319static void spr_write_hid0_601 (void *opaque, int sprn)
320{
321 DisasContext *ctx = opaque;
322
323 gen_op_store_hid0_601();
324 /* Must stop the translation as endianness may have changed */
325 GEN_STOP(ctx);
326}
76a66253
JM		 327#endif
328
329/* Unified bats */
330#if !defined(CONFIG_USER_ONLY)
331static void spr_read_601_ubat (void *opaque, int sprn)
332{
333 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
334}
335
336static void spr_write_601_ubatu (void *opaque, int sprn)
337{
76a66253 338 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 339}
340
341static void spr_write_601_ubatl (void *opaque, int sprn)
342{
76a66253 343 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 344}
345#endif
346
347/* PowerPC 40x specific registers */
348#if !defined(CONFIG_USER_ONLY)
349static void spr_read_40x_pit (void *opaque, int sprn)
350{
351 gen_op_load_40x_pit();
352}
353
354static void spr_write_40x_pit (void *opaque, int sprn)
355{
356 gen_op_store_40x_pit();
357}
358
8ecc7913
JM		 359static void spr_write_40x_dbcr0 (void *opaque, int sprn)
360{
361 DisasContext *ctx = opaque;
362
363 gen_op_store_40x_dbcr0();
364 /* We must stop translation as we may have rebooted */
e1833e1f 365 GEN_STOP(ctx);
8ecc7913
JM		 366}
367
c294fc58
JM		 368static void spr_write_40x_sler (void *opaque, int sprn)
369{
c294fc58 370 gen_op_store_40x_sler();
c294fc58
JM		 371}
372
76a66253
JM		 373static void spr_write_booke_tcr (void *opaque, int sprn)
374{
375 gen_op_store_booke_tcr();
376}
377
378static void spr_write_booke_tsr (void *opaque, int sprn)
379{
380 gen_op_store_booke_tsr();
381}
382#endif
383
384/* PowerPC 403 specific registers */
385/* PBL1 / PBU1 / PBL2 / PBU2 */
386#if !defined(CONFIG_USER_ONLY)
387static void spr_read_403_pbr (void *opaque, int sprn)
388{
389 gen_op_load_403_pb(sprn - SPR_403_PBL1);
390}
391
392static void spr_write_403_pbr (void *opaque, int sprn)
393{
76a66253 394 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 395}
396
3fc6c082
FB		 397static void spr_write_pir (void *opaque, int sprn)
398{
399 gen_op_store_pir();
400}
76a66253 401#endif
3fc6c082 402
6f5d427d
JM		 403#if !defined(CONFIG_USER_ONLY)
404/* Callback used to write the exception vector base */
405static void spr_write_excp_prefix (void *opaque, int sprn)
406{
407 gen_op_store_excp_prefix();
408 gen_op_store_spr(sprn);
409}
410
411static void spr_write_excp_vector (void *opaque, int sprn)
412{
413 DisasContext *ctx = opaque;
414
415 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
416 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
417 gen_op_store_spr(sprn);
418 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
419 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
420 gen_op_store_spr(sprn);
421 } else {
422 printf("Trying to write an unknown exception vector %d %03x\n",
423 sprn, sprn);
424 GEN_EXCP_PRIVREG(ctx);
425 }
426}
427#endif
428
76a66253
JM		 429#if defined(CONFIG_USER_ONLY)
430#define spr_register(env, num, name, uea_read, uea_write, \
431 oea_read, oea_write, initial_value) \
432do { \
433 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
434} while (0)
435static inline void _spr_register (CPUPPCState *env, int num,
436 const unsigned char *name,
437 void (*uea_read)(void *opaque, int sprn),
438 void (*uea_write)(void *opaque, int sprn),
439 target_ulong initial_value)
440#else
3fc6c082
FB		 441static inline void spr_register (CPUPPCState *env, int num,
442 const unsigned char *name,
443 void (*uea_read)(void *opaque, int sprn),
444 void (*uea_write)(void *opaque, int sprn),
445 void (*oea_read)(void *opaque, int sprn),
446 void (*oea_write)(void *opaque, int sprn),
447 target_ulong initial_value)
76a66253 448#endif
3fc6c082
FB		 449{
450 ppc_spr_t *spr;
451
452 spr = &env->spr_cb[num];
453 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 454#if !defined(CONFIG_USER_ONLY)
455 spr->oea_read != NULL || spr->oea_write != NULL ||
456#endif
457 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 458 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
459 exit(1);
460 }
461#if defined(PPC_DEBUG_SPR)
1b9eb036 462 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 463 initial_value);
3fc6c082
FB		 464#endif
465 spr->name = name;
466 spr->uea_read = uea_read;
467 spr->uea_write = uea_write;
76a66253 468#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 469 spr->oea_read = oea_read;
470 spr->oea_write = oea_write;
76a66253 471#endif
3fc6c082
FB		 472 env->spr[num] = initial_value;
473}
474
475/* Generic PowerPC SPRs */
476static void gen_spr_generic (CPUPPCState *env)
477{
478 /* Integer processing */
479 spr_register(env, SPR_XER, "XER",
480 &spr_read_xer, &spr_write_xer,
481 &spr_read_xer, &spr_write_xer,
482 0x00000000);
483 /* Branch contol */
484 spr_register(env, SPR_LR, "LR",
485 &spr_read_lr, &spr_write_lr,
486 &spr_read_lr, &spr_write_lr,
487 0x00000000);
488 spr_register(env, SPR_CTR, "CTR",
489 &spr_read_ctr, &spr_write_ctr,
490 &spr_read_ctr, &spr_write_ctr,
491 0x00000000);
492 /* Interrupt processing */
493 spr_register(env, SPR_SRR0, "SRR0",
494 SPR_NOACCESS, SPR_NOACCESS,
495 &spr_read_generic, &spr_write_generic,
496 0x00000000);
497 spr_register(env, SPR_SRR1, "SRR1",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 0x00000000);
501 /* Processor control */
502 spr_register(env, SPR_SPRG0, "SPRG0",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 spr_register(env, SPR_SPRG1, "SPRG1",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 spr_register(env, SPR_SPRG2, "SPRG2",
511 SPR_NOACCESS, SPR_NOACCESS,
512 &spr_read_generic, &spr_write_generic,
513 0x00000000);
514 spr_register(env, SPR_SPRG3, "SPRG3",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518}
519
520/* SPR common to all non-embedded PowerPC, including 601 */
521static void gen_spr_ne_601 (CPUPPCState *env)
522{
523 /* Exception processing */
524 spr_register(env, SPR_DSISR, "DSISR",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_generic, &spr_write_generic,
527 0x00000000);
528 spr_register(env, SPR_DAR, "DAR",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_generic, &spr_write_generic,
531 0x00000000);
532 /* Timer */
533 spr_register(env, SPR_DECR, "DECR",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_decr, &spr_write_decr,
536 0x00000000);
537 /* Memory management */
538 spr_register(env, SPR_SDR1, "SDR1",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_sdr1, &spr_write_sdr1,
541 0x00000000);
542}
543
544/* BATs 0-3 */
545static void gen_low_BATs (CPUPPCState *env)
546{
f2e63a42 547#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 548 spr_register(env, SPR_IBAT0U, "IBAT0U",
549 SPR_NOACCESS, SPR_NOACCESS,
550 &spr_read_ibat, &spr_write_ibatu,
551 0x00000000);
552 spr_register(env, SPR_IBAT0L, "IBAT0L",
553 SPR_NOACCESS, SPR_NOACCESS,
554 &spr_read_ibat, &spr_write_ibatl,
555 0x00000000);
556 spr_register(env, SPR_IBAT1U, "IBAT1U",
557 SPR_NOACCESS, SPR_NOACCESS,
558 &spr_read_ibat, &spr_write_ibatu,
559 0x00000000);
560 spr_register(env, SPR_IBAT1L, "IBAT1L",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_ibat, &spr_write_ibatl,
563 0x00000000);
564 spr_register(env, SPR_IBAT2U, "IBAT2U",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_ibat, &spr_write_ibatu,
567 0x00000000);
568 spr_register(env, SPR_IBAT2L, "IBAT2L",
569 SPR_NOACCESS, SPR_NOACCESS,
570 &spr_read_ibat, &spr_write_ibatl,
571 0x00000000);
572 spr_register(env, SPR_IBAT3U, "IBAT3U",
573 SPR_NOACCESS, SPR_NOACCESS,
574 &spr_read_ibat, &spr_write_ibatu,
575 0x00000000);
576 spr_register(env, SPR_IBAT3L, "IBAT3L",
577 SPR_NOACCESS, SPR_NOACCESS,
578 &spr_read_ibat, &spr_write_ibatl,
579 0x00000000);
580 spr_register(env, SPR_DBAT0U, "DBAT0U",
581 SPR_NOACCESS, SPR_NOACCESS,
582 &spr_read_dbat, &spr_write_dbatu,
583 0x00000000);
584 spr_register(env, SPR_DBAT0L, "DBAT0L",
585 SPR_NOACCESS, SPR_NOACCESS,
586 &spr_read_dbat, &spr_write_dbatl,
587 0x00000000);
588 spr_register(env, SPR_DBAT1U, "DBAT1U",
589 SPR_NOACCESS, SPR_NOACCESS,
590 &spr_read_dbat, &spr_write_dbatu,
591 0x00000000);
592 spr_register(env, SPR_DBAT1L, "DBAT1L",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_dbat, &spr_write_dbatl,
595 0x00000000);
596 spr_register(env, SPR_DBAT2U, "DBAT2U",
597 SPR_NOACCESS, SPR_NOACCESS,
598 &spr_read_dbat, &spr_write_dbatu,
599 0x00000000);
600 spr_register(env, SPR_DBAT2L, "DBAT2L",
601 SPR_NOACCESS, SPR_NOACCESS,
602 &spr_read_dbat, &spr_write_dbatl,
603 0x00000000);
604 spr_register(env, SPR_DBAT3U, "DBAT3U",
605 SPR_NOACCESS, SPR_NOACCESS,
606 &spr_read_dbat, &spr_write_dbatu,
607 0x00000000);
608 spr_register(env, SPR_DBAT3L, "DBAT3L",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_dbat, &spr_write_dbatl,
611 0x00000000);
a750fc0b 612 env->nb_BATs += 4;
f2e63a42 613#endif
3fc6c082
FB		 614}
615
616/* BATs 4-7 */
617static void gen_high_BATs (CPUPPCState *env)
618{
f2e63a42 619#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 620 spr_register(env, SPR_IBAT4U, "IBAT4U",
621 SPR_NOACCESS, SPR_NOACCESS,
622 &spr_read_ibat_h, &spr_write_ibatu_h,
623 0x00000000);
624 spr_register(env, SPR_IBAT4L, "IBAT4L",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_ibat_h, &spr_write_ibatl_h,
627 0x00000000);
628 spr_register(env, SPR_IBAT5U, "IBAT5U",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_ibat_h, &spr_write_ibatu_h,
631 0x00000000);
632 spr_register(env, SPR_IBAT5L, "IBAT5L",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_ibat_h, &spr_write_ibatl_h,
635 0x00000000);
636 spr_register(env, SPR_IBAT6U, "IBAT6U",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_ibat_h, &spr_write_ibatu_h,
639 0x00000000);
640 spr_register(env, SPR_IBAT6L, "IBAT6L",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_ibat_h, &spr_write_ibatl_h,
643 0x00000000);
644 spr_register(env, SPR_IBAT7U, "IBAT7U",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_ibat_h, &spr_write_ibatu_h,
647 0x00000000);
648 spr_register(env, SPR_IBAT7L, "IBAT7L",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_ibat_h, &spr_write_ibatl_h,
651 0x00000000);
652 spr_register(env, SPR_DBAT4U, "DBAT4U",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_dbat_h, &spr_write_dbatu_h,
655 0x00000000);
656 spr_register(env, SPR_DBAT4L, "DBAT4L",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_dbat_h, &spr_write_dbatl_h,
659 0x00000000);
660 spr_register(env, SPR_DBAT5U, "DBAT5U",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_dbat_h, &spr_write_dbatu_h,
663 0x00000000);
664 spr_register(env, SPR_DBAT5L, "DBAT5L",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_dbat_h, &spr_write_dbatl_h,
667 0x00000000);
668 spr_register(env, SPR_DBAT6U, "DBAT6U",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_dbat_h, &spr_write_dbatu_h,
671 0x00000000);
672 spr_register(env, SPR_DBAT6L, "DBAT6L",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_dbat_h, &spr_write_dbatl_h,
675 0x00000000);
676 spr_register(env, SPR_DBAT7U, "DBAT7U",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_dbat_h, &spr_write_dbatu_h,
679 0x00000000);
680 spr_register(env, SPR_DBAT7L, "DBAT7L",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_dbat_h, &spr_write_dbatl_h,
683 0x00000000);
a750fc0b 684 env->nb_BATs += 4;
f2e63a42 685#endif
3fc6c082
FB		 686}
687
688/* Generic PowerPC time base */
689static void gen_tbl (CPUPPCState *env)
690{
691 spr_register(env, SPR_VTBL, "TBL",
692 &spr_read_tbl, SPR_NOACCESS,
693 &spr_read_tbl, SPR_NOACCESS,
694 0x00000000);
695 spr_register(env, SPR_TBL, "TBL",
696 SPR_NOACCESS, SPR_NOACCESS,
697 SPR_NOACCESS, &spr_write_tbl,
698 0x00000000);
699 spr_register(env, SPR_VTBU, "TBU",
700 &spr_read_tbu, SPR_NOACCESS,
701 &spr_read_tbu, SPR_NOACCESS,
702 0x00000000);
703 spr_register(env, SPR_TBU, "TBU",
704 SPR_NOACCESS, SPR_NOACCESS,
705 SPR_NOACCESS, &spr_write_tbu,
706 0x00000000);
707}
708
76a66253
JM		 709/* Softare table search registers */
710static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
711{
f2e63a42 712#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 713 env->nb_tlb = nb_tlbs;
714 env->nb_ways = nb_ways;
715 env->id_tlbs = 1;
716 spr_register(env, SPR_DMISS, "DMISS",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, SPR_NOACCESS,
719 0x00000000);
720 spr_register(env, SPR_DCMP, "DCMP",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, SPR_NOACCESS,
723 0x00000000);
724 spr_register(env, SPR_HASH1, "HASH1",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, SPR_NOACCESS,
727 0x00000000);
728 spr_register(env, SPR_HASH2, "HASH2",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_generic, SPR_NOACCESS,
731 0x00000000);
732 spr_register(env, SPR_IMISS, "IMISS",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_generic, SPR_NOACCESS,
735 0x00000000);
736 spr_register(env, SPR_ICMP, "ICMP",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, SPR_NOACCESS,
739 0x00000000);
740 spr_register(env, SPR_RPA, "RPA",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
f2e63a42 744#endif
76a66253
JM		 745}
746
747/* SPR common to MPC755 and G2 */
748static void gen_spr_G2_755 (CPUPPCState *env)
749{
750 /* SGPRs */
751 spr_register(env, SPR_SPRG4, "SPRG4",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755 spr_register(env, SPR_SPRG5, "SPRG5",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 0x00000000);
759 spr_register(env, SPR_SPRG6, "SPRG6",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763 spr_register(env, SPR_SPRG7, "SPRG7",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
767 /* External access control */
768 /* XXX : not implemented */
769 spr_register(env, SPR_EAR, "EAR",
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_generic, &spr_write_generic,
772 0x00000000);
773}
774
3fc6c082
FB		 775/* SPR common to all 7xx PowerPC implementations */
776static void gen_spr_7xx (CPUPPCState *env)
777{
778 /* Breakpoints */
779 /* XXX : not implemented */
780 spr_register(env, SPR_DABR, "DABR",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
783 0x00000000);
784 /* XXX : not implemented */
785 spr_register(env, SPR_IABR, "IABR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
789 /* Cache management */
790 /* XXX : not implemented */
791 spr_register(env, SPR_ICTC, "ICTC",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
76a66253
JM		 795 /* XXX : not implemented */
796 spr_register(env, SPR_L2CR, "L2CR",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
3fc6c082
FB		 800 /* Performance monitors */
801 /* XXX : not implemented */
802 spr_register(env, SPR_MMCR0, "MMCR0",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 /* XXX : not implemented */
807 spr_register(env, SPR_MMCR1, "MMCR1",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811 /* XXX : not implemented */
812 spr_register(env, SPR_PMC1, "PMC1",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 /* XXX : not implemented */
817 spr_register(env, SPR_PMC2, "PMC2",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
821 /* XXX : not implemented */
822 spr_register(env, SPR_PMC3, "PMC3",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826 /* XXX : not implemented */
827 spr_register(env, SPR_PMC4, "PMC4",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_generic, &spr_write_generic,
830 0x00000000);
831 /* XXX : not implemented */
a750fc0b 832 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_generic, SPR_NOACCESS,
835 0x00000000);
578bb252 836 /* XXX : not implemented */
3fc6c082
FB		 837 spr_register(env, SPR_UMMCR0, "UMMCR0",
838 &spr_read_ureg, SPR_NOACCESS,
839 &spr_read_ureg, SPR_NOACCESS,
840 0x00000000);
578bb252 841 /* XXX : not implemented */
3fc6c082
FB		 842 spr_register(env, SPR_UMMCR1, "UMMCR1",
843 &spr_read_ureg, SPR_NOACCESS,
844 &spr_read_ureg, SPR_NOACCESS,
845 0x00000000);
578bb252 846 /* XXX : not implemented */
3fc6c082
FB		 847 spr_register(env, SPR_UPMC1, "UPMC1",
848 &spr_read_ureg, SPR_NOACCESS,
849 &spr_read_ureg, SPR_NOACCESS,
850 0x00000000);
578bb252 851 /* XXX : not implemented */
3fc6c082
FB		 852 spr_register(env, SPR_UPMC2, "UPMC2",
853 &spr_read_ureg, SPR_NOACCESS,
854 &spr_read_ureg, SPR_NOACCESS,
855 0x00000000);
578bb252 856 /* XXX : not implemented */
3fc6c082
FB		 857 spr_register(env, SPR_UPMC3, "UPMC3",
858 &spr_read_ureg, SPR_NOACCESS,
859 &spr_read_ureg, SPR_NOACCESS,
860 0x00000000);
578bb252 861 /* XXX : not implemented */
3fc6c082
FB		 862 spr_register(env, SPR_UPMC4, "UPMC4",
863 &spr_read_ureg, SPR_NOACCESS,
864 &spr_read_ureg, SPR_NOACCESS,
865 0x00000000);
578bb252 866 /* XXX : not implemented */
a750fc0b 867 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 868 &spr_read_ureg, SPR_NOACCESS,
869 &spr_read_ureg, SPR_NOACCESS,
870 0x00000000);
a750fc0b 871 /* External access control */
3fc6c082 872 /* XXX : not implemented */
a750fc0b 873 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
a750fc0b
JM		 877}
878
879static void gen_spr_thrm (CPUPPCState *env)
880{
881 /* Thermal management */
3fc6c082 882 /* XXX : not implemented */
a750fc0b 883 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 /* XXX : not implemented */
a750fc0b 888 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
3fc6c082 892 /* XXX : not implemented */
a750fc0b 893 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_generic,
896 0x00000000);
897}
898
899/* SPR specific to PowerPC 604 implementation */
900static void gen_spr_604 (CPUPPCState *env)
901{
902 /* Processor identification */
903 spr_register(env, SPR_PIR, "PIR",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_pir,
906 0x00000000);
907 /* Breakpoints */
908 /* XXX : not implemented */
909 spr_register(env, SPR_IABR, "IABR",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 /* XXX : not implemented */
914 spr_register(env, SPR_DABR, "DABR",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 /* Performance counters */
919 /* XXX : not implemented */
920 spr_register(env, SPR_MMCR0, "MMCR0",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 /* XXX : not implemented */
3fc6c082
FB		 925 spr_register(env, SPR_PMC1, "PMC1",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_generic,
928 0x00000000);
929 /* XXX : not implemented */
930 spr_register(env, SPR_PMC2, "PMC2",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* XXX : not implemented */
a750fc0b 935 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, SPR_NOACCESS,
938 0x00000000);
939 /* XXX : not implemented */
940 spr_register(env, SPR_SDA, "SDA",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, SPR_NOACCESS,
943 0x00000000);
944 /* External access control */
945 /* XXX : not implemented */
946 spr_register(env, SPR_EAR, "EAR",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950}
951
76a66253
JM		 952/* SPR specific to PowerPC 603 implementation */
953static void gen_spr_603 (CPUPPCState *env)
3fc6c082 954{
76a66253
JM		 955 /* External access control */
956 /* XXX : not implemented */
957 spr_register(env, SPR_EAR, "EAR",
3fc6c082 958 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
3fc6c082
FB		 961}
962
76a66253
JM		 963/* SPR specific to PowerPC G2 implementation */
964static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 965{
76a66253
JM		 966 /* Memory base address */
967 /* MBAR */
578bb252 968 /* XXX : not implemented */
76a66253
JM		 969 spr_register(env, SPR_MBAR, "MBAR",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
76a66253 973 /* Exception processing */
363be49c 974 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
363be49c 978 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 979 SPR_NOACCESS, SPR_NOACCESS,
980 &spr_read_generic, &spr_write_generic,
981 0x00000000);
982 /* Breakpoints */
983 /* XXX : not implemented */
984 spr_register(env, SPR_DABR, "DABR",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_DABR2, "DABR2",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_IABR, "IABR",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_IABR2, "IABR2",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_IBCR, "IBCR",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_DBCR, "DBCR",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013}
1014
1015/* SPR specific to PowerPC 602 implementation */
1016static void gen_spr_602 (CPUPPCState *env)
1017{
1018 /* ESA registers */
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_SER, "SER",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_SEBR, "SEBR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
a750fc0b 1030 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* Floating point status */
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_SP, "SP",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_LT, "LT",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Watchdog timer */
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_TCR, "TCR",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* Interrupt base */
1052 spr_register(env, SPR_IBR, "IBR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
a750fc0b
JM		 1056 /* XXX : not implemented */
1057 spr_register(env, SPR_IABR, "IABR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
76a66253
JM		 1061}
1062
1063/* SPR specific to PowerPC 601 implementation */
1064static void gen_spr_601 (CPUPPCState *env)
1065{
1066 /* Multiplication/division register */
1067 /* MQ */
1068 spr_register(env, SPR_MQ, "MQ",
1069 &spr_read_generic, &spr_write_generic,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 /* RTC registers */
1073 spr_register(env, SPR_601_RTCU, "RTCU",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 SPR_NOACCESS, &spr_write_601_rtcu,
1076 0x00000000);
1077 spr_register(env, SPR_601_VRTCU, "RTCU",
1078 &spr_read_601_rtcu, SPR_NOACCESS,
1079 &spr_read_601_rtcu, SPR_NOACCESS,
1080 0x00000000);
1081 spr_register(env, SPR_601_RTCL, "RTCL",
1082 SPR_NOACCESS, SPR_NOACCESS,
1083 SPR_NOACCESS, &spr_write_601_rtcl,
1084 0x00000000);
1085 spr_register(env, SPR_601_VRTCL, "RTCL",
1086 &spr_read_601_rtcl, SPR_NOACCESS,
1087 &spr_read_601_rtcl, SPR_NOACCESS,
1088 0x00000000);
1089 /* Timer */
1090#if 0 /* ? */
1091 spr_register(env, SPR_601_UDECR, "UDECR",
1092 &spr_read_decr, SPR_NOACCESS,
1093 &spr_read_decr, SPR_NOACCESS,
1094 0x00000000);
1095#endif
1096 /* External access control */
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_EAR, "EAR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* Memory management */
f2e63a42 1103#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1104 spr_register(env, SPR_IBAT0U, "IBAT0U",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_601_ubat, &spr_write_601_ubatu,
1107 0x00000000);
1108 spr_register(env, SPR_IBAT0L, "IBAT0L",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_601_ubat, &spr_write_601_ubatl,
1111 0x00000000);
1112 spr_register(env, SPR_IBAT1U, "IBAT1U",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_601_ubat, &spr_write_601_ubatu,
1115 0x00000000);
1116 spr_register(env, SPR_IBAT1L, "IBAT1L",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_601_ubat, &spr_write_601_ubatl,
1119 0x00000000);
1120 spr_register(env, SPR_IBAT2U, "IBAT2U",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_601_ubat, &spr_write_601_ubatu,
1123 0x00000000);
1124 spr_register(env, SPR_IBAT2L, "IBAT2L",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_601_ubat, &spr_write_601_ubatl,
1127 0x00000000);
1128 spr_register(env, SPR_IBAT3U, "IBAT3U",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_601_ubat, &spr_write_601_ubatu,
1131 0x00000000);
1132 spr_register(env, SPR_IBAT3L, "IBAT3L",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_601_ubat, &spr_write_601_ubatl,
1135 0x00000000);
a750fc0b 1136 env->nb_BATs = 4;
f2e63a42 1137#endif
a750fc0b
JM		 1138}
1139
1140static void gen_spr_74xx (CPUPPCState *env)
1141{
1142 /* Processor identification */
1143 spr_register(env, SPR_PIR, "PIR",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_pir,
1146 0x00000000);
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_MMCR2, "MMCR2",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
578bb252 1152 /* XXX : not implemented */
a750fc0b
JM		 1153 spr_register(env, SPR_UMMCR2, "UMMCR2",
1154 &spr_read_ureg, SPR_NOACCESS,
1155 &spr_read_ureg, SPR_NOACCESS,
1156 0x00000000);
1157 /* XXX: not implemented */
1158 spr_register(env, SPR_BAMR, "BAMR",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
578bb252 1162 /* XXX : not implemented */
a750fc0b
JM		 1163 spr_register(env, SPR_UBAMR, "UBAMR",
1164 &spr_read_ureg, SPR_NOACCESS,
1165 &spr_read_ureg, SPR_NOACCESS,
1166 0x00000000);
578bb252 1167 /* XXX : not implemented */
a750fc0b
JM		 1168 spr_register(env, SPR_MSSCR0, "MSSCR0",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* Hardware implementation registers */
1173 /* XXX : not implemented */
1174 spr_register(env, SPR_HID0, "HID0",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_HID1, "HID1",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* Altivec */
1184 spr_register(env, SPR_VRSAVE, "VRSAVE",
1185 &spr_read_generic, &spr_write_generic,
1186 &spr_read_generic, &spr_write_generic,
1187 0x00000000);
1188}
1189
a750fc0b
JM		 1190static void gen_l3_ctrl (CPUPPCState *env)
1191{
1192 /* L3CR */
1193 /* XXX : not implemented */
1194 spr_register(env, SPR_L3CR, "L3CR",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 /* L3ITCR0 */
578bb252 1199 /* XXX : not implemented */
a750fc0b
JM		 1200 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 /* L3ITCR1 */
578bb252 1205 /* XXX : not implemented */
a750fc0b
JM		 1206 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* L3ITCR2 */
578bb252 1211 /* XXX : not implemented */
a750fc0b
JM		 1212 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* L3ITCR3 */
578bb252 1217 /* XXX : not implemented */
a750fc0b
JM		 1218 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* L3OHCR */
578bb252 1223 /* XXX : not implemented */
a750fc0b
JM		 1224 spr_register(env, SPR_L3OHCR, "L3OHCR",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 /* L3PM */
578bb252 1229 /* XXX : not implemented */
a750fc0b
JM		 1230 spr_register(env, SPR_L3PM, "L3PM",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234}
a750fc0b 1235
578bb252 1236static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1237{
f2e63a42 1238#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1239 env->nb_tlb = nb_tlbs;
1240 env->nb_ways = nb_ways;
1241 env->id_tlbs = 1;
1242 /* XXX : not implemented */
a750fc0b
JM		 1243 spr_register(env, SPR_PTEHI, "PTEHI",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
578bb252 1247 /* XXX : not implemented */
a750fc0b
JM		 1248 spr_register(env, SPR_PTELO, "PTELO",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
578bb252 1252 /* XXX : not implemented */
a750fc0b
JM		 1253 spr_register(env, SPR_TLBMISS, "TLBMISS",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_generic, &spr_write_generic,
1256 0x00000000);
f2e63a42 1257#endif
76a66253
JM		 1258}
1259
80d11f44 1260static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1261{
80d11f44
JM		 1262 spr_register(env, SPR_USPRG4, "USPRG4",
1263 &spr_read_ureg, SPR_NOACCESS,
1264 &spr_read_ureg, SPR_NOACCESS,
1265 0x00000000);
1266 spr_register(env, SPR_USPRG5, "USPRG5",
1267 &spr_read_ureg, SPR_NOACCESS,
1268 &spr_read_ureg, SPR_NOACCESS,
1269 0x00000000);
1270 spr_register(env, SPR_USPRG6, "USPRG6",
1271 &spr_read_ureg, SPR_NOACCESS,
1272 &spr_read_ureg, SPR_NOACCESS,
1273 0x00000000);
1274 spr_register(env, SPR_USPRG7, "USPRG7",
1275 &spr_read_ureg, SPR_NOACCESS,
1276 &spr_read_ureg, SPR_NOACCESS,
76a66253 1277 0x00000000);
80d11f44
JM		 1278}
1279
1280/* PowerPC BookE SPR */
1281static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1282{
1283 const unsigned char *ivor_names[64] = {
1284 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1285 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1286 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1287 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1288 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1289 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1290 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1291 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1292 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1293 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1294 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1295 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1296 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1297 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1298 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1299 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1300 };
1301#define SPR_BOOKE_IVORxx (-1)
1302 int ivor_sprn[64] = {
1303 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1304 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1305 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1306 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1307 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1308 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1309 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1310 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1311 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1312 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1313 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1314 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1315 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1316 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1317 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1318 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1319 };
1320 int i;
1321
76a66253 1322 /* Interrupt processing */
363be49c 1323 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
363be49c
JM		 1327 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_generic, &spr_write_generic,
1330 0x00000000);
76a66253
JM		 1331 /* Debug */
1332 /* XXX : not implemented */
1333 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_generic, &spr_write_generic,
1336 0x00000000);
1337 /* XXX : not implemented */
1338 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 /* XXX : not implemented */
76a66253
JM		 1343 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347 /* XXX : not implemented */
1348 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 /* XXX : not implemented */
76a66253
JM		 1353 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357 /* XXX : not implemented */
1358 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 /* XXX : not implemented */
1363 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 /* XXX : not implemented */
1368 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1369 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1370 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1371 0x00000000);
1372 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_ESR, "ESR",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
363be49c
JM		 1380 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1381 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1382 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1383 0x00000000);
1384 /* Exception vectors */
80d11f44
JM		 1385 for (i = 0; i < 64; i++) {
1386 if (ivor_mask & (1ULL << i)) {
1387 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1388 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1389 exit(1);
1390 }
1391 spr_register(env, ivor_sprn[i], ivor_names[i],
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_excp_vector,
1394 0x00000000);
1395 }
1396 }
76a66253
JM		 1397 spr_register(env, SPR_BOOKE_PID, "PID",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 spr_register(env, SPR_BOOKE_TCR, "TCR",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_booke_tcr,
1404 0x00000000);
1405 spr_register(env, SPR_BOOKE_TSR, "TSR",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_booke_tsr,
1408 0x00000000);
1409 /* Timer */
1410 spr_register(env, SPR_DECR, "DECR",
1411 SPR_NOACCESS, SPR_NOACCESS,
1412 &spr_read_decr, &spr_write_decr,
1413 0x00000000);
1414 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 SPR_NOACCESS, &spr_write_generic,
1417 0x00000000);
1418 /* SPRGs */
1419 spr_register(env, SPR_USPRG0, "USPRG0",
1420 &spr_read_generic, &spr_write_generic,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 spr_register(env, SPR_SPRG4, "SPRG4",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
76a66253
JM		 1427 spr_register(env, SPR_SPRG5, "SPRG5",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
76a66253
JM		 1431 spr_register(env, SPR_SPRG6, "SPRG6",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
76a66253
JM		 1435 spr_register(env, SPR_SPRG7, "SPRG7",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, &spr_write_generic,
1438 0x00000000);
76a66253
JM		 1439}
1440
363be49c 1441/* FSL storage control registers */
80d11f44 1442static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1443{
f2e63a42 1444#if !defined(CONFIG_USER_ONLY)
80d11f44
JM		 1445 const unsigned char *mas_names[8] = {
1446 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1447 };
1448 int mas_sprn[8] = {
1449 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1450 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1451 };
1452 int i;
1453
363be49c 1454 /* TLB assist registers */
578bb252 1455 /* XXX : not implemented */
80d11f44
JM		 1456 for (i = 0; i < 8; i++) {
1457 if (mas_mask & (1 << i)) {
1458 spr_register(env, mas_sprn[i], mas_names[i],
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 }
1463 }
363be49c 1464 if (env->nb_pids > 1) {
578bb252 1465 /* XXX : not implemented */
363be49c
JM		 1466 spr_register(env, SPR_BOOKE_PID1, "PID1",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 }
1471 if (env->nb_pids > 2) {
578bb252 1472 /* XXX : not implemented */
363be49c
JM		 1473 spr_register(env, SPR_BOOKE_PID2, "PID2",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 }
578bb252 1478 /* XXX : not implemented */
65f9ee8d 1479 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, SPR_NOACCESS,
1482 0x00000000); /* TOFIX */
578bb252 1483 /* XXX : not implemented */
65f9ee8d 1484 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000); /* TOFIX */
1488 switch (env->nb_ways) {
1489 case 4:
578bb252 1490 /* XXX : not implemented */
363be49c
JM		 1491 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, SPR_NOACCESS,
1494 0x00000000); /* TOFIX */
1495 /* Fallthru */
1496 case 3:
578bb252 1497 /* XXX : not implemented */
363be49c
JM		 1498 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, SPR_NOACCESS,
1501 0x00000000); /* TOFIX */
1502 /* Fallthru */
1503 case 2:
578bb252 1504 /* XXX : not implemented */
363be49c
JM		 1505 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, SPR_NOACCESS,
1508 0x00000000); /* TOFIX */
1509 /* Fallthru */
1510 case 1:
578bb252 1511 /* XXX : not implemented */
363be49c
JM		 1512 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, SPR_NOACCESS,
1515 0x00000000); /* TOFIX */
1516 /* Fallthru */
1517 case 0:
1518 default:
1519 break;
1520 }
f2e63a42 1521#endif
363be49c
JM		 1522}
1523
76a66253
JM		 1524/* SPR specific to PowerPC 440 implementation */
1525static void gen_spr_440 (CPUPPCState *env)
1526{
1527 /* Cache control */
1528 /* XXX : not implemented */
1529 spr_register(env, SPR_440_DNV0, "DNV0",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533 /* XXX : not implemented */
1534 spr_register(env, SPR_440_DNV1, "DNV1",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 /* XXX : not implemented */
1539 spr_register(env, SPR_440_DNV2, "DNV2",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, &spr_write_generic,
1542 0x00000000);
1543 /* XXX : not implemented */
1544 spr_register(env, SPR_440_DNV3, "DNV3",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 /* XXX : not implemented */
2662a059 1549 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 /* XXX : not implemented */
2662a059 1554 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* XXX : not implemented */
2662a059 1559 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 /* XXX : not implemented */
2662a059 1564 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 /* XXX : not implemented */
1569 spr_register(env, SPR_440_DVLIM, "DVLIM",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_440_INV0, "INV0",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_440_INV1, "INV1",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* XXX : not implemented */
1584 spr_register(env, SPR_440_INV2, "INV2",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_440_INV3, "INV3",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 /* XXX : not implemented */
2662a059 1594 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 /* XXX : not implemented */
2662a059 1599 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 /* XXX : not implemented */
2662a059 1604 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 /* XXX : not implemented */
2662a059 1609 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_440_IVLIM, "IVLIM",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* Cache debug */
1619 /* XXX : not implemented */
2662a059 1620 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, SPR_NOACCESS,
1623 0x00000000);
1624 /* XXX : not implemented */
2662a059 1625 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, SPR_NOACCESS,
1628 0x00000000);
1629 /* XXX : not implemented */
2662a059 1630 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, SPR_NOACCESS,
1633 0x00000000);
1634 /* XXX : not implemented */
2662a059 1635 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, SPR_NOACCESS,
1638 0x00000000);
1639 /* XXX : not implemented */
2662a059 1640 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 0x00000000);
1644 /* XXX : not implemented */
1645 spr_register(env, SPR_440_DBDR, "DBDR",
1646 SPR_NOACCESS, SPR_NOACCESS,
1647 &spr_read_generic, &spr_write_generic,
1648 0x00000000);
1649 /* Processor control */
1650 spr_register(env, SPR_4xx_CCR0, "CCR0",
1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, &spr_write_generic,
1653 0x00000000);
1654 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, SPR_NOACCESS,
1657 0x00000000);
1658 /* Storage control */
1659 spr_register(env, SPR_440_MMUCR, "MMUCR",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663}
1664
1665/* SPR shared between PowerPC 40x implementations */
1666static void gen_spr_40x (CPUPPCState *env)
1667{
1668 /* Cache */
035feb88 1669 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1670 spr_register(env, SPR_40x_DCCR, "DCCR",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
035feb88 1674 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1675 spr_register(env, SPR_40x_ICCR, "ICCR",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, &spr_write_generic,
1678 0x00000000);
578bb252 1679 /* not emulated, as Qemu do not emulate caches */
2662a059 1680 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, SPR_NOACCESS,
1683 0x00000000);
76a66253
JM		 1684 /* Exception */
1685 spr_register(env, SPR_40x_DEAR, "DEAR",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689 spr_register(env, SPR_40x_ESR, "ESR",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 spr_register(env, SPR_40x_EVPR, "EVPR",
1694 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1695 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1696 0x00000000);
1697 spr_register(env, SPR_40x_SRR2, "SRR2",
1698 &spr_read_generic, &spr_write_generic,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 spr_register(env, SPR_40x_SRR3, "SRR3",
1702 &spr_read_generic, &spr_write_generic,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* Timers */
1706 spr_register(env, SPR_40x_PIT, "PIT",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_40x_pit, &spr_write_40x_pit,
1709 0x00000000);
1710 spr_register(env, SPR_40x_TCR, "TCR",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_booke_tcr,
1713 0x00000000);
1714 spr_register(env, SPR_40x_TSR, "TSR",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_booke_tsr,
1717 0x00000000);
2662a059
JM		 1718}
1719
1720/* SPR specific to PowerPC 405 implementation */
1721static void gen_spr_405 (CPUPPCState *env)
1722{
1723 /* MMU */
1724 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
2662a059 1728 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1731 0x00700000);
1732 /* Debug interface */
76a66253
JM		 1733 /* XXX : not implemented */
1734 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1735 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1736 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1737 0x00000000);
1738 /* XXX : not implemented */
2662a059
JM		 1739 spr_register(env, SPR_405_DBCR1, "DBCR1",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
76a66253
JM		 1744 spr_register(env, SPR_40x_DBSR, "DBSR",
1745 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1746 &spr_read_generic, &spr_write_clear,
1747 /* Last reset was system reset */
76a66253
JM		 1748 0x00000300);
1749 /* XXX : not implemented */
2662a059 1750 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
2662a059 1754 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, &spr_write_generic,
1757 0x00000000);
2662a059
JM		 1758 /* XXX : not implemented */
1759 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
2662a059 1762 0x00000000);
76a66253 1763 /* XXX : not implemented */
2662a059 1764 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
2662a059 1769 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
2662a059 1773 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_405_IAC3, "IAC3",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* XXX : not implemented */
1783 spr_register(env, SPR_405_IAC4, "IAC4",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 /* Storage control */
035feb88 1788 /* XXX: TODO: not implemented */
76a66253
JM		 1789 spr_register(env, SPR_405_SLER, "SLER",
1790 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1791 &spr_read_generic, &spr_write_40x_sler,
76a66253 1792 0x00000000);
2662a059
JM		 1793 spr_register(env, SPR_40x_ZPR, "ZPR",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
76a66253
JM		 1797 /* XXX : not implemented */
1798 spr_register(env, SPR_405_SU0R, "SU0R",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 /* SPRG */
1803 spr_register(env, SPR_USPRG0, "USPRG0",
1804 &spr_read_ureg, SPR_NOACCESS,
1805 &spr_read_ureg, SPR_NOACCESS,
1806 0x00000000);
1807 spr_register(env, SPR_SPRG4, "SPRG4",
1808 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1809 &spr_read_generic, &spr_write_generic,
76a66253 1810 0x00000000);
76a66253
JM		 1811 spr_register(env, SPR_SPRG5, "SPRG5",
1812 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1813 spr_read_generic, &spr_write_generic,
76a66253 1814 0x00000000);
76a66253
JM		 1815 spr_register(env, SPR_SPRG6, "SPRG6",
1816 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1817 spr_read_generic, &spr_write_generic,
76a66253 1818 0x00000000);
76a66253
JM		 1819 spr_register(env, SPR_SPRG7, "SPRG7",
1820 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1821 spr_read_generic, &spr_write_generic,
76a66253 1822 0x00000000);
80d11f44 1823 gen_spr_usprgh(env);
76a66253
JM		 1824}
1825
1826/* SPR shared between PowerPC 401 & 403 implementations */
1827static void gen_spr_401_403 (CPUPPCState *env)
1828{
1829 /* Time base */
1830 spr_register(env, SPR_403_VTBL, "TBL",
1831 &spr_read_tbl, SPR_NOACCESS,
1832 &spr_read_tbl, SPR_NOACCESS,
1833 0x00000000);
1834 spr_register(env, SPR_403_TBL, "TBL",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 SPR_NOACCESS, &spr_write_tbl,
1837 0x00000000);
1838 spr_register(env, SPR_403_VTBU, "TBU",
1839 &spr_read_tbu, SPR_NOACCESS,
1840 &spr_read_tbu, SPR_NOACCESS,
1841 0x00000000);
1842 spr_register(env, SPR_403_TBU, "TBU",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 SPR_NOACCESS, &spr_write_tbu,
1845 0x00000000);
1846 /* Debug */
578bb252 1847 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1848 spr_register(env, SPR_403_CDBCR, "CDBCR",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852}
1853
2662a059
JM		 1854/* SPR specific to PowerPC 401 implementation */
1855static void gen_spr_401 (CPUPPCState *env)
1856{
1857 /* Debug interface */
1858 /* XXX : not implemented */
1859 spr_register(env, SPR_40x_DBCR0, "DBCR",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 &spr_read_generic, &spr_write_40x_dbcr0,
1862 0x00000000);
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_40x_DBSR, "DBSR",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_clear,
1867 /* Last reset was system reset */
1868 0x00000300);
1869 /* XXX : not implemented */
1870 spr_register(env, SPR_40x_DAC1, "DAC",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, &spr_write_generic,
1873 0x00000000);
1874 /* XXX : not implemented */
1875 spr_register(env, SPR_40x_IAC1, "IAC",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, &spr_write_generic,
1878 0x00000000);
1879 /* Storage control */
035feb88 1880 /* XXX: TODO: not implemented */
2662a059
JM		 1881 spr_register(env, SPR_405_SLER, "SLER",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_40x_sler,
1884 0x00000000);
035feb88
JM		 1885 /* not emulated, as Qemu never does speculative access */
1886 spr_register(env, SPR_40x_SGR, "SGR",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0xFFFFFFFF);
1890 /* not emulated, as Qemu do not emulate caches */
1891 spr_register(env, SPR_40x_DCWR, "DCWR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
2662a059
JM		 1895}
1896
a750fc0b
JM		 1897static void gen_spr_401x2 (CPUPPCState *env)
1898{
1899 gen_spr_401(env);
1900 spr_register(env, SPR_40x_PID, "PID",
1901 SPR_NOACCESS, SPR_NOACCESS,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 spr_register(env, SPR_40x_ZPR, "ZPR",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908}
1909
76a66253
JM		 1910/* SPR specific to PowerPC 403 implementation */
1911static void gen_spr_403 (CPUPPCState *env)
1912{
2662a059
JM		 1913 /* Debug interface */
1914 /* XXX : not implemented */
1915 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_40x_dbcr0,
1918 0x00000000);
1919 /* XXX : not implemented */
1920 spr_register(env, SPR_40x_DBSR, "DBSR",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_clear,
1923 /* Last reset was system reset */
1924 0x00000300);
1925 /* XXX : not implemented */
1926 spr_register(env, SPR_40x_DAC1, "DAC1",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
578bb252 1930 /* XXX : not implemented */
2662a059
JM		 1931 spr_register(env, SPR_40x_DAC2, "DAC2",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00000000);
1935 /* XXX : not implemented */
1936 spr_register(env, SPR_40x_IAC1, "IAC1",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_generic,
1939 0x00000000);
578bb252 1940 /* XXX : not implemented */
2662a059
JM		 1941 spr_register(env, SPR_40x_IAC2, "IAC2",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 &spr_read_generic, &spr_write_generic,
1944 0x00000000);
a750fc0b
JM		 1945}
1946
1947static void gen_spr_403_real (CPUPPCState *env)
1948{
76a66253
JM		 1949 spr_register(env, SPR_403_PBL1, "PBL1",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_403_pbr, &spr_write_403_pbr,
1952 0x00000000);
1953 spr_register(env, SPR_403_PBU1, "PBU1",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_403_pbr, &spr_write_403_pbr,
1956 0x00000000);
1957 spr_register(env, SPR_403_PBL2, "PBL2",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_403_pbr, &spr_write_403_pbr,
1960 0x00000000);
1961 spr_register(env, SPR_403_PBU2, "PBU2",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_403_pbr, &spr_write_403_pbr,
1964 0x00000000);
a750fc0b
JM		 1965}
1966
1967static void gen_spr_403_mmu (CPUPPCState *env)
1968{
1969 /* MMU */
1970 spr_register(env, SPR_40x_PID, "PID",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
2662a059 1974 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978}
1979
1980/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 1981static void gen_spr_compress (CPUPPCState *env)
1982{
578bb252 1983 /* XXX : not implemented */
76a66253
JM		 1984 spr_register(env, SPR_401_SKR, "SKR",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0x00000000);
1988}
a750fc0b
JM		 1989
1990#if defined (TARGET_PPC64)
a750fc0b
JM		 1991/* SPR specific to PowerPC 620 */
1992static void gen_spr_620 (CPUPPCState *env)
1993{
082c6681
JM		 1994 /* Processor identification */
1995 spr_register(env, SPR_PIR, "PIR",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_pir,
1998 0x00000000);
1999 spr_register(env, SPR_ASR, "ASR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_asr, &spr_write_asr,
2002 0x00000000);
2003 /* Breakpoints */
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_IABR, "IABR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* XXX : not implemented */
2010 spr_register(env, SPR_DABR, "DABR",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014 /* XXX : not implemented */
2015 spr_register(env, SPR_SIAR, "SIAR",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, SPR_NOACCESS,
2018 0x00000000);
2019 /* XXX : not implemented */
2020 spr_register(env, SPR_SDA, "SDA",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, SPR_NOACCESS,
2023 0x00000000);
2024 /* XXX : not implemented */
2025 spr_register(env, SPR_620_PMC1R, "PMC1",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, SPR_NOACCESS,
2028 0x00000000);
2029 spr_register(env, SPR_620_PMC1W, "PMC1",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 SPR_NOACCESS, &spr_write_generic,
2032 0x00000000);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_620_PMC2R, "PMC2",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, SPR_NOACCESS,
2037 0x00000000);
2038 spr_register(env, SPR_620_PMC2W, "PMC2",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 SPR_NOACCESS, &spr_write_generic,
2041 0x00000000);
2042 /* XXX : not implemented */
2043 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, SPR_NOACCESS,
2046 0x00000000);
2047 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 SPR_NOACCESS, &spr_write_generic,
2050 0x00000000);
2051 /* External access control */
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_EAR, "EAR",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057#if 0 // XXX: check this
578bb252 2058 /* XXX : not implemented */
a750fc0b
JM		 2059 spr_register(env, SPR_620_PMR0, "PMR0",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
578bb252 2063 /* XXX : not implemented */
a750fc0b
JM		 2064 spr_register(env, SPR_620_PMR1, "PMR1",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
578bb252 2068 /* XXX : not implemented */
a750fc0b
JM		 2069 spr_register(env, SPR_620_PMR2, "PMR2",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_generic,
2072 0x00000000);
578bb252 2073 /* XXX : not implemented */
a750fc0b
JM		 2074 spr_register(env, SPR_620_PMR3, "PMR3",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_generic,
2077 0x00000000);
578bb252 2078 /* XXX : not implemented */
a750fc0b
JM		 2079 spr_register(env, SPR_620_PMR4, "PMR4",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_generic,
2082 0x00000000);
578bb252 2083 /* XXX : not implemented */
a750fc0b
JM		 2084 spr_register(env, SPR_620_PMR5, "PMR5",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
578bb252 2088 /* XXX : not implemented */
a750fc0b
JM		 2089 spr_register(env, SPR_620_PMR6, "PMR6",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0x00000000);
578bb252 2093 /* XXX : not implemented */
a750fc0b
JM		 2094 spr_register(env, SPR_620_PMR7, "PMR7",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
578bb252 2098 /* XXX : not implemented */
a750fc0b
JM		 2099 spr_register(env, SPR_620_PMR8, "PMR8",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
578bb252 2103 /* XXX : not implemented */
a750fc0b
JM		 2104 spr_register(env, SPR_620_PMR9, "PMR9",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
578bb252 2108 /* XXX : not implemented */
a750fc0b
JM		 2109 spr_register(env, SPR_620_PMRA, "PMR10",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_generic,
2112 0x00000000);
578bb252 2113 /* XXX : not implemented */
a750fc0b
JM		 2114 spr_register(env, SPR_620_PMRB, "PMR11",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
578bb252 2118 /* XXX : not implemented */
a750fc0b
JM		 2119 spr_register(env, SPR_620_PMRC, "PMR12",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
578bb252 2123 /* XXX : not implemented */
a750fc0b
JM		 2124 spr_register(env, SPR_620_PMRD, "PMR13",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
578bb252 2128 /* XXX : not implemented */
a750fc0b
JM		 2129 spr_register(env, SPR_620_PMRE, "PMR14",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
578bb252 2133 /* XXX : not implemented */
a750fc0b
JM		 2134 spr_register(env, SPR_620_PMRF, "PMR15",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
082c6681 2138#endif
578bb252 2139 /* XXX : not implemented */
082c6681 2140 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
578bb252 2144 /* XXX : not implemented */
082c6681
JM		 2145 spr_register(env, SPR_620_L2CR, "L2CR",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
2154}
a750fc0b 2155#endif /* defined (TARGET_PPC64) */
76a66253 2156
80d11f44 2157static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2158{
80d11f44
JM		 2159 /* Exception processing */
2160 spr_register(env, SPR_DSISR, "DSISR",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 spr_register(env, SPR_DAR, "DAR",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* Timer */
2169 spr_register(env, SPR_DECR, "DECR",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_decr, &spr_write_decr,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_MPC_EIE, "EIE",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_MPC_EID, "EID",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 /* XXX : not implemented */
2184 spr_register(env, SPR_MPC_NRI, "NRI",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_MPC_CMPA, "CMPA",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 /* XXX : not implemented */
2194 spr_register(env, SPR_MPC_CMPB, "CMPB",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_MPC_CMPC, "CMPC",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_MPC_CMPD, "CMPD",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
2208 /* XXX : not implemented */
2209 spr_register(env, SPR_MPC_ECR, "ECR",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
2213 /* XXX : not implemented */
2214 spr_register(env, SPR_MPC_DER, "DER",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_MPC_CMPE, "CMPE",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_MPC_CMPF, "CMPF",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_MPC_CMPG, "CMPG",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_MPC_CMPH, "CMPH",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_MPC_BAR, "BAR",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_MPC_DPDR, "DPDR",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_MPC_IMMR, "IMMR",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273}
2274
2275static void gen_spr_5xx (CPUPPCState *env)
2276{
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382}
2383
2384static void gen_spr_8xx (CPUPPCState *env)
2385{
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511}
2512
2513// XXX: TODO
2514/*
2515 * AMR => SPR 29 (Power 2.04)
2516 * CTRL => SPR 136 (Power 2.04)
2517 * CTRL => SPR 152 (Power 2.04)
2518 * SCOMC => SPR 276 (64 bits ?)
2519 * SCOMD => SPR 277 (64 bits ?)
2520 * TBU40 => SPR 286 (Power 2.04 hypv)
2521 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2522 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2523 * HDSISR => SPR 306 (Power 2.04 hypv)
2524 * HDAR => SPR 307 (Power 2.04 hypv)
2525 * PURR => SPR 309 (Power 2.04 hypv)
2526 * HDEC => SPR 310 (Power 2.04 hypv)
2527 * HIOR => SPR 311 (hypv)
2528 * RMOR => SPR 312 (970)
2529 * HRMOR => SPR 313 (Power 2.04 hypv)
2530 * HSRR0 => SPR 314 (Power 2.04 hypv)
2531 * HSRR1 => SPR 315 (Power 2.04 hypv)
2532 * LPCR => SPR 316 (970)
2533 * LPIDR => SPR 317 (970)
2534 * SPEFSCR => SPR 512 (Power 2.04 emb)
2535 * EPR => SPR 702 (Power 2.04 emb)
2536 * perf => 768-783 (Power 2.04)
2537 * perf => 784-799 (Power 2.04)
2538 * PPR => SPR 896 (Power 2.04)
2539 * EPLC => SPR 947 (Power 2.04 emb)
2540 * EPSC => SPR 948 (Power 2.04 emb)
2541 * DABRX => 1015 (Power 2.04 hypv)
2542 * FPECR => SPR 1022 (?)
2543 * ... and more (thermal management, performance counters, ...)
2544 */
2545
2546/*****************************************************************************/
2547/* Exception vectors models */
2548static void init_excp_4xx_real (CPUPPCState *env)
2549{
2550#if !defined(CONFIG_USER_ONLY)
2551 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2552 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2553 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2554 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2555 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2556 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2557 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2558 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2559 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2560 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
faadf50e 2561 env->excp_prefix = 0x00000000UL;
80d11f44 2562 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2563 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2564 /* Hardware reset vector */
2565 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2566#endif
2567}
2568
80d11f44
JM		 2569static void init_excp_4xx_softmmu (CPUPPCState *env)
2570{
2571#if !defined(CONFIG_USER_ONLY)
2572 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2573 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2574 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2575 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2576 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2577 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2578 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2579 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2580 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2581 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2582 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2583 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2584 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2585 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2586 env->excp_prefix = 0x00000000UL;
2587 env->ivor_mask = 0x0000FFF0UL;
2588 env->ivpr_mask = 0xFFFF0000UL;
2589 /* Hardware reset vector */
2590 env->hreset_vector = 0xFFFFFFFCUL;
2591#endif
2592}
2593
2594static void init_excp_MPC5xx (CPUPPCState *env)
2595{
2596#if !defined(CONFIG_USER_ONLY)
2597 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2598 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2599 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2600 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2601 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2602 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2603 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2604 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2605 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2606 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2607 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2608 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2609 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2610 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2611 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2612 env->excp_prefix = 0x00000000UL;
2613 env->ivor_mask = 0x0000FFF0UL;
2614 env->ivpr_mask = 0xFFFF0000UL;
2615 /* Hardware reset vector */
2616 env->hreset_vector = 0xFFFFFFFCUL;
2617#endif
2618}
2619
2620static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2621{
2622#if !defined(CONFIG_USER_ONLY)
2623 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2624 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2625 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2626 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2627 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2628 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2629 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2630 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2631 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2632 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2633 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2634 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2635 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2636 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2637 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2638 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2639 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2640 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2641 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2642 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2643 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2644 env->excp_prefix = 0x00000000UL;
2645 env->ivor_mask = 0x0000FFF0UL;
2646 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2647 /* Hardware reset vector */
80d11f44 2648 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2649#endif
2650}
2651
80d11f44 2652static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2653{
2654#if !defined(CONFIG_USER_ONLY)
2655 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2656 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2657 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2658 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2659 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2660 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2661 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2662 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2663 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2664 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2665 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2666 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2667 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2668 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2669 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2670 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2671 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2672 env->excp_prefix = 0x00000000UL;
2673 /* Hardware reset vector */
2674 env->hreset_vector = 0xFFFFFFFCUL;
2675#endif
2676}
2677
2678static void init_excp_e200 (CPUPPCState *env)
2679{
2680#if !defined(CONFIG_USER_ONLY)
2681 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2682 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2683 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2684 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2685 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2686 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2687 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2688 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2689 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2690 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2691 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2692 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2693 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2694 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2695 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2696 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2697 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2698 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2699 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2700 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2701 env->excp_prefix = 0x00000000UL;
2702 env->ivor_mask = 0x0000FFF7UL;
2703 env->ivpr_mask = 0xFFFF0000UL;
2704 /* Hardware reset vector */
2705 env->hreset_vector = 0xFFFFFFFCUL;
2706#endif
2707}
2708
2709static void init_excp_BookE (CPUPPCState *env)
2710{
2711#if !defined(CONFIG_USER_ONLY)
2712 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2713 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2714 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2715 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2716 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2717 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2728 env->excp_prefix = 0x00000000UL;
2729 env->ivor_mask = 0x0000FFE0UL;
2730 env->ivpr_mask = 0xFFFF0000UL;
2731 /* Hardware reset vector */
2732 env->hreset_vector = 0xFFFFFFFCUL;
2733#endif
2734}
2735
2736static void init_excp_601 (CPUPPCState *env)
2737{
2738#if !defined(CONFIG_USER_ONLY)
2739 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2740 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2741 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2742 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2743 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2744 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2745 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2746 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2747 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2748 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2749 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2750 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
faadf50e 2751 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2752 /* Hardware reset vector */
80d11f44 2753 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2754#endif
2755}
2756
80d11f44 2757static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2758{
2759#if !defined(CONFIG_USER_ONLY)
082c6681 2760 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2761 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2762 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2763 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2764 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2765 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2766 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2767 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2768 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2769 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2770 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2771 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2772 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2773 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2774 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2775 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2776 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2777 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2778 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2779 env->excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2780 /* Hardware reset vector */
2781 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2782#endif
2783}
2784
80d11f44 2785static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2786{
2787#if !defined(CONFIG_USER_ONLY)
2788 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2789 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2790 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2791 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2792 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2793 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2794 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2795 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2796 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2798 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2799 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2800 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2801 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2802 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2803 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2804 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2805 /* Hardware reset vector */
2806 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2807#endif
2808}
2809
2810static void init_excp_604 (CPUPPCState *env)
2811{
2812#if !defined(CONFIG_USER_ONLY)
2813 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2814 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2815 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2816 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2817 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2818 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2819 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2820 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2821 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2822 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2823 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2824 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2825 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2826 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2827 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2828 /* Hardware reset vector */
2829 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2830#endif
2831}
2832
578bb252 2833#if defined(TARGET_PPC64)
e1833e1f
JM		 2834static void init_excp_620 (CPUPPCState *env)
2835{
2836#if !defined(CONFIG_USER_ONLY)
2837 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2838 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2839 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2840 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2841 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2842 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2843 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2844 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2845 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2847 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2848 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2849 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2850 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2851 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2852 /* Hardware reset vector */
faadf50e 2853 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2854#endif
2855}
578bb252 2856#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2857
2858static void init_excp_7x0 (CPUPPCState *env)
2859{
2860#if !defined(CONFIG_USER_ONLY)
2861 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2863 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2864 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2865 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2866 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2867 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2868 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2870 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2872 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2873 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2874 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2875 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2876 /* Hardware reset vector */
2877 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2878#endif
2879}
2880
2881static void init_excp_750FX (CPUPPCState *env)
2882{
2883#if !defined(CONFIG_USER_ONLY)
2884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2898 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2899 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2900 /* Hardware reset vector */
2901 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2902#endif
2903}
2904
7a3a6927
JM		 2905/* XXX: Check if this is correct */
2906static void init_excp_7x5 (CPUPPCState *env)
2907{
2908#if !defined(CONFIG_USER_ONLY)
2909 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2910 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2911 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2912 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2913 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2914 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2915 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2916 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2917 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2918 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2919 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2920 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2921 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2922 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2923 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2924 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2925 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2926 env->excp_prefix = 0x00000000UL;
7a3a6927
JM		 2927 /* Hardware reset vector */
2928 env->hreset_vector = 0xFFFFFFFCUL;
2929#endif
2930}
2931
e1833e1f
JM		 2932static void init_excp_7400 (CPUPPCState *env)
2933{
2934#if !defined(CONFIG_USER_ONLY)
2935 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2936 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2937 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2938 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2939 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2940 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2941 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2942 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2943 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2944 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2945 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2946 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2947 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2948 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2949 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2950 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2951 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2952 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2953 /* Hardware reset vector */
2954 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2955#endif
2956}
2957
e1833e1f
JM		 2958static void init_excp_7450 (CPUPPCState *env)
2959{
2960#if !defined(CONFIG_USER_ONLY)
2961 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2962 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2963 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2964 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2965 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2967 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2968 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2969 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2970 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2971 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2972 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2973 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2974 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2975 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2976 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2979 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
faadf50e 2980 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2981 /* Hardware reset vector */
2982 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2983#endif
2984}
e1833e1f
JM		 2985
2986#if defined (TARGET_PPC64)
2987static void init_excp_970 (CPUPPCState *env)
2988{
2989#if !defined(CONFIG_USER_ONLY)
2990 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2991 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2992 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2993 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2994 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2995 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2996 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2997 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2998 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2999 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3000 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3001 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3002 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3003 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3004 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3005 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3006 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3007 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3008 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3009 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
faadf50e 3010 env->excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3011 /* Hardware reset vector */
3012 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3013#endif
3014}
3015#endif
3016
2f462816
JM		 3017/*****************************************************************************/
3018/* Power management enable checks */
3019static int check_pow_none (CPUPPCState *env)
3020{
3021 return 0;
3022}
3023
3024static int check_pow_nocheck (CPUPPCState *env)
3025{
3026 return 1;
3027}
3028
3029static int check_pow_hid0 (CPUPPCState *env)
3030{
3031 if (env->spr[SPR_HID0] & 0x00E00000)
3032 return 1;
3033
3034 return 0;
3035}
3036
a750fc0b
JM		 3037/*****************************************************************************/
3038/* PowerPC implementations definitions */
76a66253 3039
a750fc0b 3040/* PowerPC 401 */
082c6681
JM		 3041#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3042 PPC_WRTEE | PPC_DCR | \
3043 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3044 PPC_CACHE_DCBZ | \
a750fc0b 3045 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3046 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3047#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3048#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3049#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3050#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3051#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3052#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3053 POWERPC_FLAG_BUS_CLK)
2f462816 3054#define check_pow_401 check_pow_nocheck
76a66253 3055
a750fc0b
JM		 3056static void init_proc_401 (CPUPPCState *env)
3057{
3058 gen_spr_40x(env);
3059 gen_spr_401_403(env);
3060 gen_spr_401(env);
e1833e1f 3061 init_excp_4xx_real(env);
d63001d1
JM		 3062 env->dcache_line_size = 32;
3063 env->icache_line_size = 32;
4e290a0b
JM		 3064 /* Allocate hardware IRQ controller */
3065 ppc40x_irq_init(env);
a750fc0b 3066}
76a66253 3067
a750fc0b 3068/* PowerPC 401x2 */
082c6681
JM		 3069#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3070 PPC_DCR | PPC_WRTEE | \
3071 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3072 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3073 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3074 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3075 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3076#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3077#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3078#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3079#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3080#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3081#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3082 POWERPC_FLAG_BUS_CLK)
2f462816 3083#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3084
3085static void init_proc_401x2 (CPUPPCState *env)
3086{
3087 gen_spr_40x(env);
3088 gen_spr_401_403(env);
3089 gen_spr_401x2(env);
3090 gen_spr_compress(env);
a750fc0b 3091 /* Memory management */
f2e63a42 3092#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3093 env->nb_tlb = 64;
3094 env->nb_ways = 1;
3095 env->id_tlbs = 0;
f2e63a42 3096#endif
e1833e1f 3097 init_excp_4xx_softmmu(env);
d63001d1
JM		 3098 env->dcache_line_size = 32;
3099 env->icache_line_size = 32;
4e290a0b
JM		 3100 /* Allocate hardware IRQ controller */
3101 ppc40x_irq_init(env);
76a66253
JM		 3102}
3103
a750fc0b 3104/* PowerPC 401x3 */
082c6681
JM		 3105#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3106 PPC_DCR | PPC_WRTEE | \
3107 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3108 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3109 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3110 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3111 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3112#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3113#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3114#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3115#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3116#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3117#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3118 POWERPC_FLAG_BUS_CLK)
2f462816 3119#define check_pow_401x3 check_pow_nocheck
a750fc0b 3120
578bb252 3121__attribute__ (( unused ))
e1833e1f 3122static void init_proc_401x3 (CPUPPCState *env)
76a66253 3123{
4e290a0b
JM		 3124 gen_spr_40x(env);
3125 gen_spr_401_403(env);
3126 gen_spr_401(env);
3127 gen_spr_401x2(env);
3128 gen_spr_compress(env);
e1833e1f 3129 init_excp_4xx_softmmu(env);
d63001d1
JM		 3130 env->dcache_line_size = 32;
3131 env->icache_line_size = 32;
4e290a0b
JM		 3132 /* Allocate hardware IRQ controller */
3133 ppc40x_irq_init(env);
3fc6c082 3134}
a750fc0b
JM		 3135
3136/* IOP480 */
082c6681
JM		 3137#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3138 PPC_DCR | PPC_WRTEE | \
3139 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3140 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3141 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3142 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3143 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3144#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3145#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3146#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3147#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3148#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3149#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3150 POWERPC_FLAG_BUS_CLK)
2f462816 3151#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3152
3153static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3154{
a750fc0b
JM		 3155 gen_spr_40x(env);
3156 gen_spr_401_403(env);
3157 gen_spr_401x2(env);
3158 gen_spr_compress(env);
a750fc0b 3159 /* Memory management */
f2e63a42 3160#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3161 env->nb_tlb = 64;
3162 env->nb_ways = 1;
3163 env->id_tlbs = 0;
f2e63a42 3164#endif
e1833e1f 3165 init_excp_4xx_softmmu(env);
d63001d1
JM		 3166 env->dcache_line_size = 32;
3167 env->icache_line_size = 32;
4e290a0b
JM		 3168 /* Allocate hardware IRQ controller */
3169 ppc40x_irq_init(env);
3fc6c082
FB		 3170}
3171
a750fc0b 3172/* PowerPC 403 */
082c6681
JM		 3173#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3174 PPC_DCR | PPC_WRTEE | \
3175 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3176 PPC_CACHE_DCBZ | \
a750fc0b 3177 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3178 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3179#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3180#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3181#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3182#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3183#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3184#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3185 POWERPC_FLAG_BUS_CLK)
2f462816 3186#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3187
3188static void init_proc_403 (CPUPPCState *env)
3fc6c082 3189{
a750fc0b
JM		 3190 gen_spr_40x(env);
3191 gen_spr_401_403(env);
3192 gen_spr_403(env);
3193 gen_spr_403_real(env);
e1833e1f 3194 init_excp_4xx_real(env);
d63001d1
JM		 3195 env->dcache_line_size = 32;
3196 env->icache_line_size = 32;
4e290a0b
JM		 3197 /* Allocate hardware IRQ controller */
3198 ppc40x_irq_init(env);
d63001d1
JM		 3199#if !defined(CONFIG_USER_ONLY)
3200 /* Hardware reset vector */
3201 env->hreset_vector = 0xFFFFFFFCUL;
3202#endif
3fc6c082
FB		 3203}
3204
a750fc0b 3205/* PowerPC 403 GCX */
082c6681
JM		 3206#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3207 PPC_DCR | PPC_WRTEE | \
3208 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3209 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3210 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3211 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3212 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3213#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3214#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3215#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3216#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3217#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3218#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3219 POWERPC_FLAG_BUS_CLK)
2f462816 3220#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3221
3222static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3223{
a750fc0b
JM		 3224 gen_spr_40x(env);
3225 gen_spr_401_403(env);
3226 gen_spr_403(env);
3227 gen_spr_403_real(env);
3228 gen_spr_403_mmu(env);
3229 /* Bus access control */
035feb88 3230 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3231 spr_register(env, SPR_40x_SGR, "SGR",
3232 SPR_NOACCESS, SPR_NOACCESS,
3233 &spr_read_generic, &spr_write_generic,
3234 0xFFFFFFFF);
035feb88 3235 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3236 spr_register(env, SPR_40x_DCWR, "DCWR",
3237 SPR_NOACCESS, SPR_NOACCESS,
3238 &spr_read_generic, &spr_write_generic,
3239 0x00000000);
3240 /* Memory management */
f2e63a42 3241#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3242 env->nb_tlb = 64;
3243 env->nb_ways = 1;
3244 env->id_tlbs = 0;
f2e63a42 3245#endif
80d11f44
JM		 3246 init_excp_4xx_softmmu(env);
3247 env->dcache_line_size = 32;
3248 env->icache_line_size = 32;
3249 /* Allocate hardware IRQ controller */
3250 ppc40x_irq_init(env);
3251}
3252
3253/* PowerPC 405 */
082c6681
JM		 3254#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3255 PPC_DCR | PPC_WRTEE | \
3256 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3257 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3258 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3259 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3260 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
80d11f44
JM		 3261#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3262#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3263#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3264#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3265#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3266#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3267 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3268#define check_pow_405 check_pow_nocheck
3269
3270static void init_proc_405 (CPUPPCState *env)
3271{
3272 /* Time base */
3273 gen_tbl(env);
3274 gen_spr_40x(env);
3275 gen_spr_405(env);
3276 /* Bus access control */
3277 /* not emulated, as Qemu never does speculative access */
3278 spr_register(env, SPR_40x_SGR, "SGR",
3279 SPR_NOACCESS, SPR_NOACCESS,
3280 &spr_read_generic, &spr_write_generic,
3281 0xFFFFFFFF);
3282 /* not emulated, as Qemu do not emulate caches */
3283 spr_register(env, SPR_40x_DCWR, "DCWR",
3284 SPR_NOACCESS, SPR_NOACCESS,
3285 &spr_read_generic, &spr_write_generic,
3286 0x00000000);
3287 /* Memory management */
3288#if !defined(CONFIG_USER_ONLY)
3289 env->nb_tlb = 64;
3290 env->nb_ways = 1;
3291 env->id_tlbs = 0;
3292#endif
3293 init_excp_4xx_softmmu(env);
3294 env->dcache_line_size = 32;
3295 env->icache_line_size = 32;
3296 /* Allocate hardware IRQ controller */
3297 ppc40x_irq_init(env);
3298}
3299
3300/* PowerPC 440 EP */
082c6681
JM		 3301#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3302 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3303 PPC_CACHE | PPC_CACHE_ICBI | \
3304 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3305 PPC_MEM_TLBSYNC | \
80d11f44 3306 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3307 PPC_440_SPEC)
80d11f44
JM		 3308#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3309#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3310#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3311#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3312#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3313#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3314 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3315#define check_pow_440EP check_pow_nocheck
3316
3317__attribute__ (( unused ))
3318static void init_proc_440EP (CPUPPCState *env)
3319{
3320 /* Time base */
3321 gen_tbl(env);
3322 gen_spr_BookE(env, 0x000000000000FFFFULL);
3323 gen_spr_440(env);
3324 gen_spr_usprgh(env);
3325 /* Processor identification */
3326 spr_register(env, SPR_BOOKE_PIR, "PIR",
3327 SPR_NOACCESS, SPR_NOACCESS,
3328 &spr_read_generic, &spr_write_pir,
3329 0x00000000);
3330 /* XXX : not implemented */
3331 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3332 SPR_NOACCESS, SPR_NOACCESS,
3333 &spr_read_generic, &spr_write_generic,
3334 0x00000000);
3335 /* XXX : not implemented */
3336 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3337 SPR_NOACCESS, SPR_NOACCESS,
3338 &spr_read_generic, &spr_write_generic,
3339 0x00000000);
3340 /* XXX : not implemented */
3341 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3342 SPR_NOACCESS, SPR_NOACCESS,
3343 &spr_read_generic, &spr_write_generic,
3344 0x00000000);
3345 /* XXX : not implemented */
3346 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3347 SPR_NOACCESS, SPR_NOACCESS,
3348 &spr_read_generic, &spr_write_generic,
3349 0x00000000);
3350 /* XXX : not implemented */
3351 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3352 SPR_NOACCESS, SPR_NOACCESS,
3353 &spr_read_generic, &spr_write_generic,
3354 0x00000000);
3355 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3356 SPR_NOACCESS, SPR_NOACCESS,
3357 &spr_read_generic, &spr_write_generic,
3358 0x00000000);
3359 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3360 SPR_NOACCESS, SPR_NOACCESS,
3361 &spr_read_generic, &spr_write_generic,
3362 0x00000000);
3363 /* XXX : not implemented */
3364 spr_register(env, SPR_440_CCR1, "CCR1",
3365 SPR_NOACCESS, SPR_NOACCESS,
3366 &spr_read_generic, &spr_write_generic,
3367 0x00000000);
3368 /* Memory management */
3369#if !defined(CONFIG_USER_ONLY)
3370 env->nb_tlb = 64;
3371 env->nb_ways = 1;
3372 env->id_tlbs = 0;
3373#endif
3374 init_excp_BookE(env);
3375 env->dcache_line_size = 32;
3376 env->icache_line_size = 32;
3377 /* XXX: TODO: allocate internal IRQ controller */
3378}
3379
3380/* PowerPC 440 GP */
082c6681
JM		 3381#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3382 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3383 PPC_CACHE | PPC_CACHE_ICBI | \
3384 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3385 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3386 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3387 PPC_440_SPEC)
80d11f44
JM		 3388#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3389#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3390#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3391#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3392#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3393#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3394 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3395#define check_pow_440GP check_pow_nocheck
3396
3397__attribute__ (( unused ))
3398static void init_proc_440GP (CPUPPCState *env)
3399{
3400 /* Time base */
3401 gen_tbl(env);
3402 gen_spr_BookE(env, 0x000000000000FFFFULL);
3403 gen_spr_440(env);
3404 gen_spr_usprgh(env);
3405 /* Processor identification */
3406 spr_register(env, SPR_BOOKE_PIR, "PIR",
3407 SPR_NOACCESS, SPR_NOACCESS,
3408 &spr_read_generic, &spr_write_pir,
3409 0x00000000);
3410 /* XXX : not implemented */
3411 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3412 SPR_NOACCESS, SPR_NOACCESS,
3413 &spr_read_generic, &spr_write_generic,
3414 0x00000000);
3415 /* XXX : not implemented */
3416 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3417 SPR_NOACCESS, SPR_NOACCESS,
3418 &spr_read_generic, &spr_write_generic,
3419 0x00000000);
3420 /* XXX : not implemented */
3421 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3422 SPR_NOACCESS, SPR_NOACCESS,
3423 &spr_read_generic, &spr_write_generic,
3424 0x00000000);
3425 /* XXX : not implemented */
3426 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3427 SPR_NOACCESS, SPR_NOACCESS,
3428 &spr_read_generic, &spr_write_generic,
3429 0x00000000);
3430 /* Memory management */
3431#if !defined(CONFIG_USER_ONLY)
3432 env->nb_tlb = 64;
3433 env->nb_ways = 1;
3434 env->id_tlbs = 0;
3435#endif
3436 init_excp_BookE(env);
3437 env->dcache_line_size = 32;
3438 env->icache_line_size = 32;
3439 /* XXX: TODO: allocate internal IRQ controller */
3440}
3441
3442/* PowerPC 440x4 */
082c6681
JM		 3443#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3444 PPC_DCR | PPC_WRTEE | \
3445 PPC_CACHE | PPC_CACHE_ICBI | \
3446 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3447 PPC_MEM_TLBSYNC | \
80d11f44
JM		 3448 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3449 PPC_440_SPEC)
3450#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3451#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3452#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3453#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3454#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3455#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3456 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3457#define check_pow_440x4 check_pow_nocheck
3458
3459__attribute__ (( unused ))
3460static void init_proc_440x4 (CPUPPCState *env)
3461{
3462 /* Time base */
3463 gen_tbl(env);
3464 gen_spr_BookE(env, 0x000000000000FFFFULL);
3465 gen_spr_440(env);
3466 gen_spr_usprgh(env);
3467 /* Processor identification */
3468 spr_register(env, SPR_BOOKE_PIR, "PIR",
3469 SPR_NOACCESS, SPR_NOACCESS,
3470 &spr_read_generic, &spr_write_pir,
3471 0x00000000);
3472 /* XXX : not implemented */
3473 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3474 SPR_NOACCESS, SPR_NOACCESS,
3475 &spr_read_generic, &spr_write_generic,
3476 0x00000000);
3477 /* XXX : not implemented */
3478 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3479 SPR_NOACCESS, SPR_NOACCESS,
3480 &spr_read_generic, &spr_write_generic,
3481 0x00000000);
3482 /* XXX : not implemented */
3483 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3484 SPR_NOACCESS, SPR_NOACCESS,
3485 &spr_read_generic, &spr_write_generic,
3486 0x00000000);
3487 /* XXX : not implemented */
3488 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3489 SPR_NOACCESS, SPR_NOACCESS,
3490 &spr_read_generic, &spr_write_generic,
3491 0x00000000);
3492 /* Memory management */
3493#if !defined(CONFIG_USER_ONLY)
3494 env->nb_tlb = 64;
3495 env->nb_ways = 1;
3496 env->id_tlbs = 0;
3497#endif
3498 init_excp_BookE(env);
d63001d1
JM		 3499 env->dcache_line_size = 32;
3500 env->icache_line_size = 32;
80d11f44 3501 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3502}
3503
80d11f44 3504/* PowerPC 440x5 */
082c6681
JM		 3505#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3506 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3507 PPC_CACHE | PPC_CACHE_ICBI | \
3508 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3509 PPC_MEM_TLBSYNC | \
80d11f44 3510 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3511 PPC_440_SPEC)
80d11f44
JM		 3512#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3513#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3514#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3515#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3516#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3517#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3518 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3519#define check_pow_440x5 check_pow_nocheck
a750fc0b 3520
80d11f44
JM		 3521__attribute__ (( unused ))
3522static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3523{
a750fc0b
JM		 3524 /* Time base */
3525 gen_tbl(env);
80d11f44
JM		 3526 gen_spr_BookE(env, 0x000000000000FFFFULL);
3527 gen_spr_440(env);
3528 gen_spr_usprgh(env);
3529 /* Processor identification */
3530 spr_register(env, SPR_BOOKE_PIR, "PIR",
3531 SPR_NOACCESS, SPR_NOACCESS,
3532 &spr_read_generic, &spr_write_pir,
3533 0x00000000);
3534 /* XXX : not implemented */
3535 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3536 SPR_NOACCESS, SPR_NOACCESS,
3537 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3538 0x00000000);
3539 /* XXX : not implemented */
3540 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3541 SPR_NOACCESS, SPR_NOACCESS,
3542 &spr_read_generic, &spr_write_generic,
3543 0x00000000);
3544 /* XXX : not implemented */
3545 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3546 SPR_NOACCESS, SPR_NOACCESS,
3547 &spr_read_generic, &spr_write_generic,
3548 0x00000000);
3549 /* XXX : not implemented */
3550 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3551 SPR_NOACCESS, SPR_NOACCESS,
3552 &spr_read_generic, &spr_write_generic,
3553 0x00000000);
3554 /* XXX : not implemented */
3555 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3556 SPR_NOACCESS, SPR_NOACCESS,
3557 &spr_read_generic, &spr_write_generic,
3558 0x00000000);
3559 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_generic,
3562 0x00000000);
3563 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3564 SPR_NOACCESS, SPR_NOACCESS,
3565 &spr_read_generic, &spr_write_generic,
3566 0x00000000);
3567 /* XXX : not implemented */
3568 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3569 SPR_NOACCESS, SPR_NOACCESS,
3570 &spr_read_generic, &spr_write_generic,
3571 0x00000000);
3572 /* Memory management */
f2e63a42 3573#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3574 env->nb_tlb = 64;
3575 env->nb_ways = 1;
3576 env->id_tlbs = 0;
f2e63a42 3577#endif
80d11f44 3578 init_excp_BookE(env);
d63001d1
JM		 3579 env->dcache_line_size = 32;
3580 env->icache_line_size = 32;
80d11f44 3581 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3582}
3583
80d11f44 3584/* PowerPC 460 (guessed) */
082c6681 3585#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3586 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
082c6681
JM		 3587 PPC_WRTEE | PPC_MFAPIDI | \
3588 PPC_CACHE | PPC_CACHE_ICBI | \
3589 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3590 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3591 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3592 PPC_440_SPEC)
80d11f44
JM		 3593#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3594#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3595#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3596#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3597#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3598#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3599 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3600#define check_pow_460 check_pow_nocheck
a750fc0b 3601
80d11f44
JM		 3602__attribute__ (( unused ))
3603static void init_proc_460 (CPUPPCState *env)
3fc6c082 3604{
a750fc0b
JM		 3605 /* Time base */
3606 gen_tbl(env);
80d11f44 3607 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3608 gen_spr_440(env);
80d11f44
JM		 3609 gen_spr_usprgh(env);
3610 /* Processor identification */
3611 spr_register(env, SPR_BOOKE_PIR, "PIR",
3612 SPR_NOACCESS, SPR_NOACCESS,
3613 &spr_read_generic, &spr_write_pir,
3614 0x00000000);
3615 /* XXX : not implemented */
3616 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3617 SPR_NOACCESS, SPR_NOACCESS,
3618 &spr_read_generic, &spr_write_generic,
3619 0x00000000);
3620 /* XXX : not implemented */
3621 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 /* XXX : not implemented */
3626 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3629 0x00000000);
3630 /* XXX : not implemented */
3631 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3632 SPR_NOACCESS, SPR_NOACCESS,
3633 &spr_read_generic, &spr_write_generic,
3634 0x00000000);
578bb252 3635 /* XXX : not implemented */
a750fc0b
JM		 3636 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3637 SPR_NOACCESS, SPR_NOACCESS,
3638 &spr_read_generic, &spr_write_generic,
3639 0x00000000);
3640 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
578bb252 3648 /* XXX : not implemented */
a750fc0b
JM		 3649 spr_register(env, SPR_440_CCR1, "CCR1",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
80d11f44
JM		 3653 /* XXX : not implemented */
3654 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3655 &spr_read_generic, &spr_write_generic,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
a750fc0b 3658 /* Memory management */
f2e63a42 3659#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3660 env->nb_tlb = 64;
3661 env->nb_ways = 1;
3662 env->id_tlbs = 0;
f2e63a42 3663#endif
e1833e1f 3664 init_excp_BookE(env);
d63001d1
JM		 3665 env->dcache_line_size = 32;
3666 env->icache_line_size = 32;
a750fc0b 3667 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3668}
3669
80d11f44 3670/* PowerPC 460F (guessed) */
082c6681
JM		 3671#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3672 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3673 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
80d11f44 3674 PPC_FLOAT_STFIWX | \
082c6681
JM		 3675 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3676 PPC_WRTEE | PPC_MFAPIDI | \
3677 PPC_CACHE | PPC_CACHE_ICBI | \
3678 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3679 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3680 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3681 PPC_440_SPEC)
80d11f44
JM		 3682#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3683#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3684#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3685#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3686#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3687#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3688 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3689#define check_pow_460F check_pow_nocheck
a750fc0b 3690
80d11f44
JM		 3691__attribute__ (( unused ))
3692static void init_proc_460F (CPUPPCState *env)
3fc6c082 3693{
a750fc0b
JM		 3694 /* Time base */
3695 gen_tbl(env);
80d11f44 3696 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3697 gen_spr_440(env);
80d11f44
JM		 3698 gen_spr_usprgh(env);
3699 /* Processor identification */
3700 spr_register(env, SPR_BOOKE_PIR, "PIR",
3701 SPR_NOACCESS, SPR_NOACCESS,
3702 &spr_read_generic, &spr_write_pir,
3703 0x00000000);
3704 /* XXX : not implemented */
3705 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3706 SPR_NOACCESS, SPR_NOACCESS,
3707 &spr_read_generic, &spr_write_generic,
3708 0x00000000);
3709 /* XXX : not implemented */
3710 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3711 SPR_NOACCESS, SPR_NOACCESS,
3712 &spr_read_generic, &spr_write_generic,
3713 0x00000000);
3714 /* XXX : not implemented */
3715 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3716 SPR_NOACCESS, SPR_NOACCESS,
3717 &spr_read_generic, &spr_write_generic,
3718 0x00000000);
3719 /* XXX : not implemented */
3720 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_generic,
3723 0x00000000);
3724 /* XXX : not implemented */
3725 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 /* XXX : not implemented */
3738 spr_register(env, SPR_440_CCR1, "CCR1",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
3742 /* XXX : not implemented */
3743 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3744 &spr_read_generic, &spr_write_generic,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
a750fc0b 3747 /* Memory management */
f2e63a42 3748#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3749 env->nb_tlb = 64;
3750 env->nb_ways = 1;
3751 env->id_tlbs = 0;
f2e63a42 3752#endif
e1833e1f 3753 init_excp_BookE(env);
d63001d1
JM		 3754 env->dcache_line_size = 32;
3755 env->icache_line_size = 32;
a750fc0b 3756 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3757}
3758
80d11f44
JM		 3759/* Freescale 5xx cores (aka RCPU) */
3760#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3761 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3762 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3763 PPC_MFTB)
3764#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3765#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3766#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3767#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3768#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3769#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3770 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3771#define check_pow_MPC5xx check_pow_none
3772
3773__attribute__ (( unused ))
3774static void init_proc_MPC5xx (CPUPPCState *env)
3775{
3776 /* Time base */
3777 gen_tbl(env);
3778 gen_spr_5xx_8xx(env);
3779 gen_spr_5xx(env);
3780 init_excp_MPC5xx(env);
3781 env->dcache_line_size = 32;
3782 env->icache_line_size = 32;
3783 /* XXX: TODO: allocate internal IRQ controller */
3784}
3785
3786/* Freescale 8xx cores (aka PowerQUICC) */
3787#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3788 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3789 PPC_CACHE_ICBI | PPC_MFTB)
3790#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3791#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3792#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3793#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3794#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3795#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3796 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3797#define check_pow_MPC8xx check_pow_none
3798
3799__attribute__ (( unused ))
3800static void init_proc_MPC8xx (CPUPPCState *env)
3801{
3802 /* Time base */
3803 gen_tbl(env);
3804 gen_spr_5xx_8xx(env);
3805 gen_spr_8xx(env);
3806 init_excp_MPC8xx(env);
3807 env->dcache_line_size = 32;
3808 env->icache_line_size = 32;
3809 /* XXX: TODO: allocate internal IRQ controller */
3810}
3811
3812/* Freescale 82xx cores (aka PowerQUICC-II) */
3813/* PowerPC G2 */
082c6681
JM		 3814#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3815 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3816 PPC_FLOAT_STFIWX | \
3817 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3818 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3819 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3820 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3821#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3822#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3823//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3824#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3825#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3826#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3827 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3828#define check_pow_G2 check_pow_hid0
a750fc0b 3829
80d11f44 3830static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3831{
80d11f44
JM		 3832 gen_spr_ne_601(env);
3833 gen_spr_G2_755(env);
3834 gen_spr_G2(env);
a750fc0b
JM		 3835 /* Time base */
3836 gen_tbl(env);
80d11f44
JM		 3837 /* Hardware implementation register */
3838 /* XXX : not implemented */
3839 spr_register(env, SPR_HID0, "HID0",
3840 SPR_NOACCESS, SPR_NOACCESS,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* XXX : not implemented */
3844 spr_register(env, SPR_HID1, "HID1",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 /* XXX : not implemented */
3849 spr_register(env, SPR_HID2, "HID2",
3850 SPR_NOACCESS, SPR_NOACCESS,
3851 &spr_read_generic, &spr_write_generic,
3852 0x00000000);
a750fc0b 3853 /* Memory management */
80d11f44
JM		 3854 gen_low_BATs(env);
3855 gen_high_BATs(env);
3856 gen_6xx_7xx_soft_tlb(env, 64, 2);
3857 init_excp_G2(env);
d63001d1
JM		 3858 env->dcache_line_size = 32;
3859 env->icache_line_size = 32;
80d11f44
JM		 3860 /* Allocate hardware IRQ controller */
3861 ppc6xx_irq_init(env);
3fc6c082 3862}
a750fc0b 3863
80d11f44 3864/* PowerPC G2LE */
082c6681
JM		 3865#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3866 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3867 PPC_FLOAT_STFIWX | \
3868 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3869 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3870 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3871 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3872#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3873#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3874#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3875#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3876#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3877#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3878 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3879#define check_pow_G2LE check_pow_hid0
a750fc0b 3880
80d11f44 3881static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3882{
80d11f44
JM		 3883 gen_spr_ne_601(env);
3884 gen_spr_G2_755(env);
3885 gen_spr_G2(env);
a750fc0b
JM		 3886 /* Time base */
3887 gen_tbl(env);
80d11f44 3888 /* Hardware implementation register */
578bb252 3889 /* XXX : not implemented */
80d11f44 3890 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
80d11f44
JM		 3894 /* XXX : not implemented */
3895 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
578bb252 3899 /* XXX : not implemented */
80d11f44 3900 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* Memory management */
80d11f44
JM		 3905 gen_low_BATs(env);
3906 gen_high_BATs(env);
3907 gen_6xx_7xx_soft_tlb(env, 64, 2);
3908 init_excp_G2(env);
d63001d1
JM		 3909 env->dcache_line_size = 32;
3910 env->icache_line_size = 32;
80d11f44
JM		 3911 /* Allocate hardware IRQ controller */
3912 ppc6xx_irq_init(env);
3fc6c082
FB		 3913}
3914
80d11f44
JM		 3915/* e200 core */
3916/* XXX: unimplemented instructions:
3917 * dcblc
3918 * dcbtlst
3919 * dcbtstls
3920 * icblc
3921 * icbtls
3922 * tlbivax
3923 * all SPE multiply-accumulate instructions
3924 */
082c6681 3925#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
80d11f44 3926 PPC_SPE | PPC_SPEFPU | \
082c6681
JM		 3927 PPC_WRTEE | PPC_RFDI | \
3928 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
3929 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 3930 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 3931 PPC_BOOKE)
80d11f44
JM		 3932#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3933#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3934#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3935#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3936#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3937#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 3938 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
3939 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3940#define check_pow_e200 check_pow_hid0
3941
578bb252 3942__attribute__ (( unused ))
80d11f44 3943static void init_proc_e200 (CPUPPCState *env)
3fc6c082 3944{
e1833e1f
JM		 3945 /* Time base */
3946 gen_tbl(env);
80d11f44 3947 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 3948 /* XXX : not implemented */
80d11f44 3949 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
e1833e1f
JM		 3950 SPR_NOACCESS, SPR_NOACCESS,
3951 &spr_read_generic, &spr_write_generic,
3952 0x00000000);
80d11f44
JM		 3953 /* Memory management */
3954 gen_spr_BookE_FSL(env, 0x0000005D);
3955 /* XXX : not implemented */
3956 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 3957 SPR_NOACCESS, SPR_NOACCESS,
3958 &spr_read_generic, &spr_write_generic,
3959 0x00000000);
80d11f44
JM		 3960 /* XXX : not implemented */
3961 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_generic,
3964 0x00000000);
578bb252 3965 /* XXX : not implemented */
80d11f44 3966 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
578bb252 3970 /* XXX : not implemented */
80d11f44
JM		 3971 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3972 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 3973 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 /* XXX : not implemented */
3981 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
3985 /* XXX : not implemented */
3986 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 /* XXX : not implemented */
3991 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3992 SPR_NOACCESS, SPR_NOACCESS,
3993 &spr_read_generic, &spr_write_generic,
3994 0x00000000);
3995 /* XXX : not implemented */
3996 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3997 SPR_NOACCESS, SPR_NOACCESS,
3998 &spr_read_generic, &spr_write_generic,
3999 0x00000000);
4000 /* XXX : not implemented */
4001 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4002 SPR_NOACCESS, SPR_NOACCESS,
4003 &spr_read_generic, &spr_write_generic,
4004 0x00000000);
4005 /* XXX : not implemented */
4006 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4007 SPR_NOACCESS, SPR_NOACCESS,
4008 &spr_read_generic, &spr_write_generic,
4009 0x00000000);
4010 /* XXX : not implemented */
4011 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4012 SPR_NOACCESS, SPR_NOACCESS,
4013 &spr_read_generic, &spr_write_generic,
4014 0x00000000);
4015 /* XXX : not implemented */
4016 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4017 SPR_NOACCESS, SPR_NOACCESS,
4018 &spr_read_generic, &spr_write_generic,
4019 0x00000000);
4020 /* XXX : not implemented */
4021 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4022 SPR_NOACCESS, SPR_NOACCESS,
4023 &spr_read_generic, &spr_write_generic,
4024 0x00000000);
4025 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4026 SPR_NOACCESS, SPR_NOACCESS,
4027 &spr_read_generic, &spr_write_generic,
4028 0x00000000);
4029 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4030 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4031 &spr_read_generic, &spr_write_generic,
4032 0x00000000);
f2e63a42 4033#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4034 env->nb_tlb = 64;
4035 env->nb_ways = 1;
4036 env->id_tlbs = 0;
f2e63a42 4037#endif
80d11f44 4038 init_excp_e200(env);
d63001d1
JM		 4039 env->dcache_line_size = 32;
4040 env->icache_line_size = 32;
e1833e1f 4041 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4042}
a750fc0b 4043
80d11f44 4044/* e300 core */
082c6681
JM		 4045#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4046 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4047 PPC_FLOAT_STFIWX | \
4048 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4049 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4050 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4051 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4052#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4053#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4054#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4055#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4056#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4057#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4058 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4059#define check_pow_e300 check_pow_hid0
a750fc0b 4060
578bb252 4061__attribute__ (( unused ))
80d11f44 4062static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4063{
80d11f44
JM		 4064 gen_spr_ne_601(env);
4065 gen_spr_603(env);
a750fc0b
JM		 4066 /* Time base */
4067 gen_tbl(env);
80d11f44
JM		 4068 /* hardware implementation registers */
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_HID0, "HID0",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000);
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_HID1, "HID1",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* Memory management */
4080 gen_low_BATs(env);
4081 gen_6xx_7xx_soft_tlb(env, 64, 2);
4082 init_excp_603(env);
4083 env->dcache_line_size = 32;
4084 env->icache_line_size = 32;
4085 /* Allocate hardware IRQ controller */
4086 ppc6xx_irq_init(env);
4087}
4088
4089/* e500 core */
082c6681 4090#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
80d11f44 4091 PPC_SPE | PPC_SPEFPU | \
082c6681
JM		 4092 PPC_WRTEE | PPC_RFDI | \
4093 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4094 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4095 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4096 PPC_BOOKE)
80d11f44
JM		 4097#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
4098#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
4099#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
4100#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
4101#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
4102#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4103 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4104 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4105#define check_pow_e500 check_pow_hid0
4106
4107__attribute__ (( unused ))
4108static void init_proc_e500 (CPUPPCState *env)
4109{
4110 /* Time base */
4111 gen_tbl(env);
4112 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4113 /* Processor identification */
4114 spr_register(env, SPR_BOOKE_PIR, "PIR",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_pir,
4117 0x00000000);
4118 /* XXX : not implemented */
4119 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4120 SPR_NOACCESS, SPR_NOACCESS,
4121 &spr_read_generic, &spr_write_generic,
4122 0x00000000);
4123 /* Memory management */
4124#if !defined(CONFIG_USER_ONLY)
4125 env->nb_pids = 3;
4126#endif
4127 gen_spr_BookE_FSL(env, 0x0000005F);
4128 /* XXX : not implemented */
4129 spr_register(env, SPR_HID0, "HID0",
4130 SPR_NOACCESS, SPR_NOACCESS,
4131 &spr_read_generic, &spr_write_generic,
4132 0x00000000);
4133 /* XXX : not implemented */
4134 spr_register(env, SPR_HID1, "HID1",
4135 SPR_NOACCESS, SPR_NOACCESS,
4136 &spr_read_generic, &spr_write_generic,
4137 0x00000000);
4138 /* XXX : not implemented */
4139 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4140 SPR_NOACCESS, SPR_NOACCESS,
4141 &spr_read_generic, &spr_write_generic,
4142 0x00000000);
4143 /* XXX : not implemented */
4144 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
578bb252 4153 /* XXX : not implemented */
a750fc0b
JM		 4154 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4155 SPR_NOACCESS, SPR_NOACCESS,
4156 &spr_read_generic, &spr_write_generic,
4157 0x00000000);
80d11f44
JM		 4158 /* XXX : not implemented */
4159 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
80d11f44
JM		 4163 /* XXX : not implemented */
4164 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
578bb252 4168 /* XXX : not implemented */
80d11f44 4169 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4170 SPR_NOACCESS, SPR_NOACCESS,
4171 &spr_read_generic, &spr_write_generic,
4172 0x00000000);
578bb252 4173 /* XXX : not implemented */
80d11f44
JM		 4174 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4175 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4176 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4177 0x00000000);
4178 /* XXX : not implemented */
4179 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4180 SPR_NOACCESS, SPR_NOACCESS,
4181 &spr_read_generic, &spr_write_generic,
4182 0x00000000);
4183 /* XXX : not implemented */
4184 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4185 SPR_NOACCESS, SPR_NOACCESS,
4186 &spr_read_generic, &spr_write_generic,
4187 0x00000000);
4188 /* XXX : not implemented */
4189 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4190 SPR_NOACCESS, SPR_NOACCESS,
4191 &spr_read_generic, &spr_write_generic,
4192 0x00000000);
4193 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, &spr_write_generic,
4196 0x00000000);
4197 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4198 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4199 &spr_read_generic, &spr_write_generic,
4200 0x00000000);
f2e63a42 4201#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4202 env->nb_tlb = 64;
4203 env->nb_ways = 1;
4204 env->id_tlbs = 0;
f2e63a42 4205#endif
80d11f44 4206 init_excp_e200(env);
d63001d1
JM		 4207 env->dcache_line_size = 32;
4208 env->icache_line_size = 32;
a750fc0b 4209 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4210}
a750fc0b 4211
a750fc0b 4212/* Non-embedded PowerPC */
a750fc0b
JM		 4213
4214/* POWER : same as 601, without mfmsr, mfsr */
4215#if defined(TODO)
4216#define POWERPC_INSNS_POWER (XXX_TODO)
4217/* POWER RSC (from RAD6000) */
4218#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4219#endif /* TODO */
4220
4221/* PowerPC 601 */
082c6681
JM		 4222#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4223 PPC_FLOAT | \
4224 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4225 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4226 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4227#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4228#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4229//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4230//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4231#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4232#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4233#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4234#define check_pow_601 check_pow_none
a750fc0b
JM		 4235
4236static void init_proc_601 (CPUPPCState *env)
3fc6c082 4237{
a750fc0b
JM		 4238 gen_spr_ne_601(env);
4239 gen_spr_601(env);
4240 /* Hardware implementation registers */
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_HID0, "HID0",
4243 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4244 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4245 0x80010080);
a750fc0b
JM		 4246 /* XXX : not implemented */
4247 spr_register(env, SPR_HID1, "HID1",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_601_HID2, "HID2",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_601_HID5, "HID5",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
a750fc0b 4261 /* Memory management */
e1833e1f 4262 init_excp_601(env);
082c6681
JM		 4263 /* XXX: beware that dcache line size is 64
4264 * but dcbz uses 32 bytes "sectors"
4265 * XXX: this breaks clcs instruction !
4266 */
4267 env->dcache_line_size = 32;
d63001d1 4268 env->icache_line_size = 64;
faadf50e
JM		 4269 /* Allocate hardware IRQ controller */
4270 ppc6xx_irq_init(env);
3fc6c082
FB		 4271}
4272
082c6681
JM		 4273/* PowerPC 601v */
4274#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4275 PPC_FLOAT | \
4276 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4277 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4278 PPC_SEGMENT | PPC_EXTERN)
4279#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4280#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4281#define POWERPC_MMU_601v (POWERPC_MMU_601)
4282#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4283#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4284#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4285#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4286#define check_pow_601v check_pow_none
4287
4288static void init_proc_601v (CPUPPCState *env)
4289{
4290 init_proc_601(env);
4291 /* XXX : not implemented */
4292 spr_register(env, SPR_601_HID15, "HID15",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000);
4296}
4297
a750fc0b 4298/* PowerPC 602 */
082c6681
JM		 4299#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4300 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4301 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4302 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4303 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4304 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4305 PPC_SEGMENT | PPC_602_SPEC)
082c6681
JM		 4306#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4307/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4308#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4309//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4310#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4311#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4312#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4313 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4314#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4315
4316static void init_proc_602 (CPUPPCState *env)
3fc6c082 4317{
a750fc0b
JM		 4318 gen_spr_ne_601(env);
4319 gen_spr_602(env);
4320 /* Time base */
4321 gen_tbl(env);
4322 /* hardware implementation registers */
4323 /* XXX : not implemented */
4324 spr_register(env, SPR_HID0, "HID0",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 /* XXX : not implemented */
4329 spr_register(env, SPR_HID1, "HID1",
4330 SPR_NOACCESS, SPR_NOACCESS,
4331 &spr_read_generic, &spr_write_generic,
4332 0x00000000);
4333 /* Memory management */
4334 gen_low_BATs(env);
4335 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4336 init_excp_602(env);
d63001d1
JM		 4337 env->dcache_line_size = 32;
4338 env->icache_line_size = 32;
a750fc0b
JM		 4339 /* Allocate hardware IRQ controller */
4340 ppc6xx_irq_init(env);
4341}
3fc6c082 4342
a750fc0b 4343/* PowerPC 603 */
082c6681
JM		 4344#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4345 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4346 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4347 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4348 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4349 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4350 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4351#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4352#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4353//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4354#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4355#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4356#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4357 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4358#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4359
4360static void init_proc_603 (CPUPPCState *env)
4361{
4362 gen_spr_ne_601(env);
4363 gen_spr_603(env);
4364 /* Time base */
4365 gen_tbl(env);
4366 /* hardware implementation registers */
4367 /* XXX : not implemented */
4368 spr_register(env, SPR_HID0, "HID0",
4369 SPR_NOACCESS, SPR_NOACCESS,
4370 &spr_read_generic, &spr_write_generic,
4371 0x00000000);
4372 /* XXX : not implemented */
4373 spr_register(env, SPR_HID1, "HID1",
4374 SPR_NOACCESS, SPR_NOACCESS,
4375 &spr_read_generic, &spr_write_generic,
4376 0x00000000);
4377 /* Memory management */
4378 gen_low_BATs(env);
4379 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4380 init_excp_603(env);
d63001d1
JM		 4381 env->dcache_line_size = 32;
4382 env->icache_line_size = 32;
a750fc0b
JM		 4383 /* Allocate hardware IRQ controller */
4384 ppc6xx_irq_init(env);
3fc6c082
FB		 4385}
4386
a750fc0b 4387/* PowerPC 603e */
082c6681
JM		 4388#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4389 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4390 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4391 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4392 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4393 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4394 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4395#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4396#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4397//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4398#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4399#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4400#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4401 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4402#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4403
4404static void init_proc_603E (CPUPPCState *env)
4405{
4406 gen_spr_ne_601(env);
4407 gen_spr_603(env);
4408 /* Time base */
4409 gen_tbl(env);
4410 /* hardware implementation registers */
4411 /* XXX : not implemented */
4412 spr_register(env, SPR_HID0, "HID0",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* XXX : not implemented */
4417 spr_register(env, SPR_HID1, "HID1",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421 /* XXX : not implemented */
4422 spr_register(env, SPR_IABR, "IABR",
4423 SPR_NOACCESS, SPR_NOACCESS,
4424 &spr_read_generic, &spr_write_generic,
4425 0x00000000);
4426 /* Memory management */
4427 gen_low_BATs(env);
4428 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4429 init_excp_603(env);
d63001d1
JM		 4430 env->dcache_line_size = 32;
4431 env->icache_line_size = 32;
a750fc0b
JM		 4432 /* Allocate hardware IRQ controller */
4433 ppc6xx_irq_init(env);
4434}
4435
a750fc0b 4436/* PowerPC 604 */
082c6681
JM		 4437#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4438 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4439 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4440 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4441 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4442 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4443 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4444#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4445#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4446//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4447#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4448#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4449#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4450 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4451#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4452
4453static void init_proc_604 (CPUPPCState *env)
4454{
4455 gen_spr_ne_601(env);
4456 gen_spr_604(env);
4457 /* Time base */
4458 gen_tbl(env);
4459 /* Hardware implementation registers */
4460 /* XXX : not implemented */
082c6681
JM		 4461 spr_register(env, SPR_HID0, "HID0",
4462 SPR_NOACCESS, SPR_NOACCESS,
4463 &spr_read_generic, &spr_write_generic,
4464 0x00000000);
4465 /* Memory management */
4466 gen_low_BATs(env);
4467 init_excp_604(env);
4468 env->dcache_line_size = 32;
4469 env->icache_line_size = 32;
4470 /* Allocate hardware IRQ controller */
4471 ppc6xx_irq_init(env);
4472}
4473
4474/* PowerPC 604E */
4475#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4476 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4477 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4478 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4479 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4480 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4481 PPC_SEGMENT | PPC_EXTERN)
4482#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4483#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4484#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4485#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4486#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4487#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4488 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4489#define check_pow_604E check_pow_nocheck
4490
4491static void init_proc_604E (CPUPPCState *env)
4492{
4493 gen_spr_ne_601(env);
4494 gen_spr_604(env);
4495 /* XXX : not implemented */
4496 spr_register(env, SPR_MMCR1, "MMCR1",
4497 SPR_NOACCESS, SPR_NOACCESS,
4498 &spr_read_generic, &spr_write_generic,
4499 0x00000000);
4500 /* XXX : not implemented */
4501 spr_register(env, SPR_PMC3, "PMC3",
4502 SPR_NOACCESS, SPR_NOACCESS,
4503 &spr_read_generic, &spr_write_generic,
4504 0x00000000);
4505 /* XXX : not implemented */
4506 spr_register(env, SPR_PMC4, "PMC4",
4507 SPR_NOACCESS, SPR_NOACCESS,
4508 &spr_read_generic, &spr_write_generic,
4509 0x00000000);
4510 /* Time base */
4511 gen_tbl(env);
4512 /* Hardware implementation registers */
4513 /* XXX : not implemented */
a750fc0b
JM		 4514 spr_register(env, SPR_HID0, "HID0",
4515 SPR_NOACCESS, SPR_NOACCESS,
4516 &spr_read_generic, &spr_write_generic,
4517 0x00000000);
4518 /* XXX : not implemented */
4519 spr_register(env, SPR_HID1, "HID1",
4520 SPR_NOACCESS, SPR_NOACCESS,
4521 &spr_read_generic, &spr_write_generic,
4522 0x00000000);
4523 /* Memory management */
4524 gen_low_BATs(env);
e1833e1f 4525 init_excp_604(env);
d63001d1
JM		 4526 env->dcache_line_size = 32;
4527 env->icache_line_size = 32;
a750fc0b
JM		 4528 /* Allocate hardware IRQ controller */
4529 ppc6xx_irq_init(env);
4530}
4531
4532/* PowerPC 740/750 (aka G3) */
082c6681
JM		 4533#define POWERPC_INSNS_7x0 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4534 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4535 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4536 PPC_FLOAT_STFIWX | \
4537 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4538 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4540 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4541#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
a750fc0b
JM		 4542#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
4543//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
4544#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 4545#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
25ba3a68 4546#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4547 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4548#define check_pow_7x0 check_pow_hid0
a750fc0b
JM		 4549
4550static void init_proc_7x0 (CPUPPCState *env)
4551{
4552 gen_spr_ne_601(env);
4553 gen_spr_7xx(env);
4554 /* Time base */
4555 gen_tbl(env);
4556 /* Thermal management */
4557 gen_spr_thrm(env);
4558 /* Hardware implementation registers */
4559 /* XXX : not implemented */
4560 spr_register(env, SPR_HID0, "HID0",
4561 SPR_NOACCESS, SPR_NOACCESS,
4562 &spr_read_generic, &spr_write_generic,
4563 0x00000000);
4564 /* XXX : not implemented */
4565 spr_register(env, SPR_HID1, "HID1",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_generic,
4568 0x00000000);
4569 /* Memory management */
4570 gen_low_BATs(env);
e1833e1f 4571 init_excp_7x0(env);
d63001d1
JM		 4572 env->dcache_line_size = 32;
4573 env->icache_line_size = 32;
a750fc0b
JM		 4574 /* Allocate hardware IRQ controller */
4575 ppc6xx_irq_init(env);
4576}
4577
4578/* PowerPC 750FX/GX */
082c6681
JM		 4579#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4580 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4581 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4582 PPC_FLOAT_STFIWX | \
4583 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4584 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4585 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4586 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4587#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4588#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4589#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4590#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4591#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 4592#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4593 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4594#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4595
4596static void init_proc_750fx (CPUPPCState *env)
4597{
4598 gen_spr_ne_601(env);
4599 gen_spr_7xx(env);
4600 /* Time base */
4601 gen_tbl(env);
4602 /* Thermal management */
4603 gen_spr_thrm(env);
4604 /* Hardware implementation registers */
4605 /* XXX : not implemented */
4606 spr_register(env, SPR_HID0, "HID0",
4607 SPR_NOACCESS, SPR_NOACCESS,
4608 &spr_read_generic, &spr_write_generic,
4609 0x00000000);
4610 /* XXX : not implemented */
4611 spr_register(env, SPR_HID1, "HID1",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
4615 /* XXX : not implemented */
4616 spr_register(env, SPR_750_HID2, "HID2",
4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
4620 /* Memory management */
4621 gen_low_BATs(env);
4622 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4623 gen_high_BATs(env);
e1833e1f 4624 init_excp_750FX(env);
d63001d1
JM		 4625 env->dcache_line_size = 32;
4626 env->icache_line_size = 32;
a750fc0b
JM		 4627 /* Allocate hardware IRQ controller */
4628 ppc6xx_irq_init(env);
4629}
4630
4631/* PowerPC 745/755 */
082c6681
JM		 4632#define POWERPC_INSNS_7x5 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4633 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4634 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4635 PPC_FLOAT_STFIWX | \
4636 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4637 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4638 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4639 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4640#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
a750fc0b
JM		 4641#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
4642//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
4643#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 4644#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
25ba3a68 4645#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4646 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4647#define check_pow_7x5 check_pow_hid0
a750fc0b
JM		 4648
4649static void init_proc_7x5 (CPUPPCState *env)
4650{
4651 gen_spr_ne_601(env);
4652 gen_spr_G2_755(env);
4653 /* Time base */
4654 gen_tbl(env);
4655 /* L2 cache control */
4656 /* XXX : not implemented */
4657 spr_register(env, SPR_ICTC, "ICTC",
4658 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_read_generic, &spr_write_generic,
4660 0x00000000);
4661 /* XXX : not implemented */
4662 spr_register(env, SPR_L2PMCR, "L2PMCR",
4663 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_generic, &spr_write_generic,
4665 0x00000000);
4666 /* Hardware implementation registers */
4667 /* XXX : not implemented */
4668 spr_register(env, SPR_HID0, "HID0",
4669 SPR_NOACCESS, SPR_NOACCESS,
4670 &spr_read_generic, &spr_write_generic,
4671 0x00000000);
4672 /* XXX : not implemented */
4673 spr_register(env, SPR_HID1, "HID1",
4674 SPR_NOACCESS, SPR_NOACCESS,
4675 &spr_read_generic, &spr_write_generic,
4676 0x00000000);
4677 /* XXX : not implemented */
4678 spr_register(env, SPR_HID2, "HID2",
4679 SPR_NOACCESS, SPR_NOACCESS,
4680 &spr_read_generic, &spr_write_generic,
4681 0x00000000);
4682 /* Memory management */
4683 gen_low_BATs(env);
4684 gen_high_BATs(env);
4685 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 4686 init_excp_7x5(env);
d63001d1
JM		 4687 env->dcache_line_size = 32;
4688 env->icache_line_size = 32;
a750fc0b
JM		 4689 /* Allocate hardware IRQ controller */
4690 ppc6xx_irq_init(env);
d63001d1
JM		 4691#if !defined(CONFIG_USER_ONLY)
4692 /* Hardware reset vector */
4693 env->hreset_vector = 0xFFFFFFFCUL;
4694#endif
a750fc0b
JM		 4695}
4696
4697/* PowerPC 7400 (aka G4) */
082c6681
JM		 4698#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4699 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4700 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4701 PPC_FLOAT_STFIWX | \
4702 PPC_CACHE | PPC_CACHE_ICBI | \
4703 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
4704 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4705 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4706 PPC_MEM_TLBIA | \
4707 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 4708 PPC_ALTIVEC)
4709#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
4710#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
4711#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
4712#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 4713#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 4714#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 4715 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
4716 POWERPC_FLAG_BUS_CLK)
2f462816 4717#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 4718
4719static void init_proc_7400 (CPUPPCState *env)
4720{
4721 gen_spr_ne_601(env);
4722 gen_spr_7xx(env);
4723 /* Time base */
4724 gen_tbl(env);
4725 /* 74xx specific SPR */
4726 gen_spr_74xx(env);
4727 /* Thermal management */
4728 gen_spr_thrm(env);
4729 /* Memory management */
4730 gen_low_BATs(env);
e1833e1f 4731 init_excp_7400(env);
d63001d1
JM		 4732 env->dcache_line_size = 32;
4733 env->icache_line_size = 32;
a750fc0b
JM		 4734 /* Allocate hardware IRQ controller */
4735 ppc6xx_irq_init(env);
4736}
4737
4738/* PowerPC 7410 (aka G4) */
082c6681
JM		 4739#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4740 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4741 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4742 PPC_FLOAT_STFIWX | \
4743 PPC_CACHE | PPC_CACHE_ICBI | \
4744 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
4745 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4746 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4747 PPC_MEM_TLBIA | \
4748 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 4749 PPC_ALTIVEC)
4750#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
4751#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
4752#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
4753#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 4754#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 4755#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 4756 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
4757 POWERPC_FLAG_BUS_CLK)
2f462816 4758#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 4759
4760static void init_proc_7410 (CPUPPCState *env)
4761{
4762 gen_spr_ne_601(env);
4763 gen_spr_7xx(env);
4764 /* Time base */
4765 gen_tbl(env);
4766 /* 74xx specific SPR */
4767 gen_spr_74xx(env);
4768 /* Thermal management */
4769 gen_spr_thrm(env);
4770 /* L2PMCR */
4771 /* XXX : not implemented */
4772 spr_register(env, SPR_L2PMCR, "L2PMCR",
4773 SPR_NOACCESS, SPR_NOACCESS,
4774 &spr_read_generic, &spr_write_generic,
4775 0x00000000);
4776 /* LDSTDB */
4777 /* XXX : not implemented */
4778 spr_register(env, SPR_LDSTDB, "LDSTDB",
4779 SPR_NOACCESS, SPR_NOACCESS,
4780 &spr_read_generic, &spr_write_generic,
4781 0x00000000);
4782 /* Memory management */
4783 gen_low_BATs(env);
e1833e1f 4784 init_excp_7400(env);
d63001d1
JM		 4785 env->dcache_line_size = 32;
4786 env->icache_line_size = 32;
a750fc0b
JM		 4787 /* Allocate hardware IRQ controller */
4788 ppc6xx_irq_init(env);
4789}
4790
4791/* PowerPC 7440 (aka G4) */
082c6681
JM		 4792#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4793 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4794 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4795 PPC_FLOAT_STFIWX | \
4796 PPC_CACHE | PPC_CACHE_ICBI | \
4797 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
4798 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4799 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4800 PPC_MEM_TLBIA | PPC_74xx_TLB | \
4801 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 4802 PPC_ALTIVEC)
4803#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
4804#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
4805#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
4806#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 4807#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 4808#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 4809 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
4810 POWERPC_FLAG_BUS_CLK)
2f462816 4811#define check_pow_7440 check_pow_hid0
a750fc0b 4812
578bb252 4813__attribute__ (( unused ))
a750fc0b
JM		 4814static void init_proc_7440 (CPUPPCState *env)
4815{
4816 gen_spr_ne_601(env);
4817 gen_spr_7xx(env);
4818 /* Time base */
4819 gen_tbl(env);
4820 /* 74xx specific SPR */
4821 gen_spr_74xx(env);
4822 /* LDSTCR */
4823 /* XXX : not implemented */
4824 spr_register(env, SPR_LDSTCR, "LDSTCR",
4825 SPR_NOACCESS, SPR_NOACCESS,
4826 &spr_read_generic, &spr_write_generic,
4827 0x00000000);
4828 /* ICTRL */
4829 /* XXX : not implemented */
4830 spr_register(env, SPR_ICTRL, "ICTRL",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* MSSSR0 */
578bb252 4835 /* XXX : not implemented */
a750fc0b
JM		 4836 spr_register(env, SPR_MSSSR0, "MSSSR0",
4837 SPR_NOACCESS, SPR_NOACCESS,
4838 &spr_read_generic, &spr_write_generic,
4839 0x00000000);
4840 /* PMC */
4841 /* XXX : not implemented */
4842 spr_register(env, SPR_PMC5, "PMC5",
4843 SPR_NOACCESS, SPR_NOACCESS,
4844 &spr_read_generic, &spr_write_generic,
4845 0x00000000);
578bb252 4846 /* XXX : not implemented */
a750fc0b
JM		 4847 spr_register(env, SPR_UPMC5, "UPMC5",
4848 &spr_read_ureg, SPR_NOACCESS,
4849 &spr_read_ureg, SPR_NOACCESS,
4850 0x00000000);
578bb252 4851 /* XXX : not implemented */
a750fc0b
JM		 4852 spr_register(env, SPR_PMC6, "PMC6",
4853 SPR_NOACCESS, SPR_NOACCESS,
4854 &spr_read_generic, &spr_write_generic,
4855 0x00000000);
578bb252 4856 /* XXX : not implemented */
a750fc0b
JM		 4857 spr_register(env, SPR_UPMC6, "UPMC6",
4858 &spr_read_ureg, SPR_NOACCESS,
4859 &spr_read_ureg, SPR_NOACCESS,
4860 0x00000000);
4861 /* Memory management */
4862 gen_low_BATs(env);
578bb252 4863 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 4864 init_excp_7450(env);
d63001d1
JM		 4865 env->dcache_line_size = 32;
4866 env->icache_line_size = 32;
a750fc0b
JM		 4867 /* Allocate hardware IRQ controller */
4868 ppc6xx_irq_init(env);
4869}
a750fc0b
JM		 4870
4871/* PowerPC 7450 (aka G4) */
082c6681
JM		 4872#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4873 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4874 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4875 PPC_FLOAT_STFIWX | \
4876 PPC_CACHE | PPC_CACHE_ICBI | \
4877 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
4878 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4879 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4880 PPC_MEM_TLBIA | PPC_74xx_TLB | \
4881 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 4882 PPC_ALTIVEC)
4883#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
4884#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
4885#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
4886#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 4887#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 4888#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 4889 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
4890 POWERPC_FLAG_BUS_CLK)
2f462816 4891#define check_pow_7450 check_pow_hid0
a750fc0b 4892
578bb252 4893__attribute__ (( unused ))
a750fc0b
JM		 4894static void init_proc_7450 (CPUPPCState *env)
4895{
4896 gen_spr_ne_601(env);
4897 gen_spr_7xx(env);
4898 /* Time base */
4899 gen_tbl(env);
4900 /* 74xx specific SPR */
4901 gen_spr_74xx(env);
4902 /* Level 3 cache control */
4903 gen_l3_ctrl(env);
4904 /* LDSTCR */
4905 /* XXX : not implemented */
4906 spr_register(env, SPR_LDSTCR, "LDSTCR",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910 /* ICTRL */
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_ICTRL, "ICTRL",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* MSSSR0 */
578bb252 4917 /* XXX : not implemented */
a750fc0b
JM		 4918 spr_register(env, SPR_MSSSR0, "MSSSR0",
4919 SPR_NOACCESS, SPR_NOACCESS,
4920 &spr_read_generic, &spr_write_generic,
4921 0x00000000);
4922 /* PMC */
4923 /* XXX : not implemented */
4924 spr_register(env, SPR_PMC5, "PMC5",
4925 SPR_NOACCESS, SPR_NOACCESS,
4926 &spr_read_generic, &spr_write_generic,
4927 0x00000000);
578bb252 4928 /* XXX : not implemented */
a750fc0b
JM		 4929 spr_register(env, SPR_UPMC5, "UPMC5",
4930 &spr_read_ureg, SPR_NOACCESS,
4931 &spr_read_ureg, SPR_NOACCESS,
4932 0x00000000);
578bb252 4933 /* XXX : not implemented */
a750fc0b
JM		 4934 spr_register(env, SPR_PMC6, "PMC6",
4935 SPR_NOACCESS, SPR_NOACCESS,
4936 &spr_read_generic, &spr_write_generic,
4937 0x00000000);
578bb252 4938 /* XXX : not implemented */
a750fc0b
JM		 4939 spr_register(env, SPR_UPMC6, "UPMC6",
4940 &spr_read_ureg, SPR_NOACCESS,
4941 &spr_read_ureg, SPR_NOACCESS,
4942 0x00000000);
4943 /* Memory management */
4944 gen_low_BATs(env);
578bb252 4945 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4946 init_excp_7450(env);
d63001d1
JM		 4947 env->dcache_line_size = 32;
4948 env->icache_line_size = 32;
a750fc0b
JM		 4949 /* Allocate hardware IRQ controller */
4950 ppc6xx_irq_init(env);
4951}
a750fc0b
JM		 4952
4953/* PowerPC 7445 (aka G4) */
082c6681
JM		 4954#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4955 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4956 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
4957 PPC_FLOAT_STFIWX | \
4958 PPC_CACHE | PPC_CACHE_ICBI | \
4959 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
4960 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4961 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4962 PPC_MEM_TLBIA | PPC_74xx_TLB | \
4963 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 4964 PPC_ALTIVEC)
4965#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
4966#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
4967#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
4968#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 4969#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 4970#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 4971 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
4972 POWERPC_FLAG_BUS_CLK)
2f462816 4973#define check_pow_7445 check_pow_hid0
a750fc0b 4974
578bb252 4975__attribute__ (( unused ))
a750fc0b
JM		 4976static void init_proc_7445 (CPUPPCState *env)
4977{
4978 gen_spr_ne_601(env);
4979 gen_spr_7xx(env);
4980 /* Time base */
4981 gen_tbl(env);
4982 /* 74xx specific SPR */
4983 gen_spr_74xx(env);
4984 /* LDSTCR */
4985 /* XXX : not implemented */
4986 spr_register(env, SPR_LDSTCR, "LDSTCR",
4987 SPR_NOACCESS, SPR_NOACCESS,
4988 &spr_read_generic, &spr_write_generic,
4989 0x00000000);
4990 /* ICTRL */
4991 /* XXX : not implemented */
4992 spr_register(env, SPR_ICTRL, "ICTRL",
4993 SPR_NOACCESS, SPR_NOACCESS,
4994 &spr_read_generic, &spr_write_generic,
4995 0x00000000);
4996 /* MSSSR0 */
578bb252 4997 /* XXX : not implemented */
a750fc0b
JM		 4998 spr_register(env, SPR_MSSSR0, "MSSSR0",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 /* PMC */
5003 /* XXX : not implemented */
5004 spr_register(env, SPR_PMC5, "PMC5",
5005 SPR_NOACCESS, SPR_NOACCESS,
5006 &spr_read_generic, &spr_write_generic,
5007 0x00000000);
578bb252 5008 /* XXX : not implemented */
a750fc0b
JM		 5009 spr_register(env, SPR_UPMC5, "UPMC5",
5010 &spr_read_ureg, SPR_NOACCESS,
5011 &spr_read_ureg, SPR_NOACCESS,
5012 0x00000000);
578bb252 5013 /* XXX : not implemented */
a750fc0b
JM		 5014 spr_register(env, SPR_PMC6, "PMC6",
5015 SPR_NOACCESS, SPR_NOACCESS,
5016 &spr_read_generic, &spr_write_generic,
5017 0x00000000);
578bb252 5018 /* XXX : not implemented */
a750fc0b
JM		 5019 spr_register(env, SPR_UPMC6, "UPMC6",
5020 &spr_read_ureg, SPR_NOACCESS,
5021 &spr_read_ureg, SPR_NOACCESS,
5022 0x00000000);
5023 /* SPRGs */
5024 spr_register(env, SPR_SPRG4, "SPRG4",
5025 SPR_NOACCESS, SPR_NOACCESS,
5026 &spr_read_generic, &spr_write_generic,
5027 0x00000000);
5028 spr_register(env, SPR_USPRG4, "USPRG4",
5029 &spr_read_ureg, SPR_NOACCESS,
5030 &spr_read_ureg, SPR_NOACCESS,
5031 0x00000000);
5032 spr_register(env, SPR_SPRG5, "SPRG5",
5033 SPR_NOACCESS, SPR_NOACCESS,
5034 &spr_read_generic, &spr_write_generic,
5035 0x00000000);
5036 spr_register(env, SPR_USPRG5, "USPRG5",
5037 &spr_read_ureg, SPR_NOACCESS,
5038 &spr_read_ureg, SPR_NOACCESS,
5039 0x00000000);
5040 spr_register(env, SPR_SPRG6, "SPRG6",
5041 SPR_NOACCESS, SPR_NOACCESS,
5042 &spr_read_generic, &spr_write_generic,
5043 0x00000000);
5044 spr_register(env, SPR_USPRG6, "USPRG6",
5045 &spr_read_ureg, SPR_NOACCESS,
5046 &spr_read_ureg, SPR_NOACCESS,
5047 0x00000000);
5048 spr_register(env, SPR_SPRG7, "SPRG7",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_generic,
5051 0x00000000);
5052 spr_register(env, SPR_USPRG7, "USPRG7",
5053 &spr_read_ureg, SPR_NOACCESS,
5054 &spr_read_ureg, SPR_NOACCESS,
5055 0x00000000);
5056 /* Memory management */
5057 gen_low_BATs(env);
5058 gen_high_BATs(env);
578bb252 5059 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5060 init_excp_7450(env);
d63001d1
JM		 5061 env->dcache_line_size = 32;
5062 env->icache_line_size = 32;
a750fc0b
JM		 5063 /* Allocate hardware IRQ controller */
5064 ppc6xx_irq_init(env);
5065}
a750fc0b
JM		 5066
5067/* PowerPC 7455 (aka G4) */
082c6681
JM		 5068#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5069 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5070 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5071 PPC_FLOAT_STFIWX | \
5072 PPC_CACHE | PPC_CACHE_ICBI | \
5073 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5074 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5075 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5076 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5077 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5078 PPC_ALTIVEC)
5079#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5080#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5081#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5082#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5083#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5084#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5085 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5086 POWERPC_FLAG_BUS_CLK)
2f462816 5087#define check_pow_7455 check_pow_hid0
a750fc0b 5088
578bb252 5089__attribute__ (( unused ))
a750fc0b
JM		 5090static void init_proc_7455 (CPUPPCState *env)
5091{
5092 gen_spr_ne_601(env);
5093 gen_spr_7xx(env);
5094 /* Time base */
5095 gen_tbl(env);
5096 /* 74xx specific SPR */
5097 gen_spr_74xx(env);
5098 /* Level 3 cache control */
5099 gen_l3_ctrl(env);
5100 /* LDSTCR */
5101 /* XXX : not implemented */
5102 spr_register(env, SPR_LDSTCR, "LDSTCR",
5103 SPR_NOACCESS, SPR_NOACCESS,
5104 &spr_read_generic, &spr_write_generic,
5105 0x00000000);
5106 /* ICTRL */
5107 /* XXX : not implemented */
5108 spr_register(env, SPR_ICTRL, "ICTRL",
5109 SPR_NOACCESS, SPR_NOACCESS,
5110 &spr_read_generic, &spr_write_generic,
5111 0x00000000);
5112 /* MSSSR0 */
578bb252 5113 /* XXX : not implemented */
a750fc0b
JM		 5114 spr_register(env, SPR_MSSSR0, "MSSSR0",
5115 SPR_NOACCESS, SPR_NOACCESS,
5116 &spr_read_generic, &spr_write_generic,
5117 0x00000000);
5118 /* PMC */
5119 /* XXX : not implemented */
5120 spr_register(env, SPR_PMC5, "PMC5",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 &spr_read_generic, &spr_write_generic,
5123 0x00000000);
578bb252 5124 /* XXX : not implemented */
a750fc0b
JM		 5125 spr_register(env, SPR_UPMC5, "UPMC5",
5126 &spr_read_ureg, SPR_NOACCESS,
5127 &spr_read_ureg, SPR_NOACCESS,
5128 0x00000000);
578bb252 5129 /* XXX : not implemented */
a750fc0b
JM		 5130 spr_register(env, SPR_PMC6, "PMC6",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, &spr_write_generic,
5133 0x00000000);
578bb252 5134 /* XXX : not implemented */
a750fc0b
JM		 5135 spr_register(env, SPR_UPMC6, "UPMC6",
5136 &spr_read_ureg, SPR_NOACCESS,
5137 &spr_read_ureg, SPR_NOACCESS,
5138 0x00000000);
5139 /* SPRGs */
5140 spr_register(env, SPR_SPRG4, "SPRG4",
5141 SPR_NOACCESS, SPR_NOACCESS,
5142 &spr_read_generic, &spr_write_generic,
5143 0x00000000);
5144 spr_register(env, SPR_USPRG4, "USPRG4",
5145 &spr_read_ureg, SPR_NOACCESS,
5146 &spr_read_ureg, SPR_NOACCESS,
5147 0x00000000);
5148 spr_register(env, SPR_SPRG5, "SPRG5",
5149 SPR_NOACCESS, SPR_NOACCESS,
5150 &spr_read_generic, &spr_write_generic,
5151 0x00000000);
5152 spr_register(env, SPR_USPRG5, "USPRG5",
5153 &spr_read_ureg, SPR_NOACCESS,
5154 &spr_read_ureg, SPR_NOACCESS,
5155 0x00000000);
5156 spr_register(env, SPR_SPRG6, "SPRG6",
5157 SPR_NOACCESS, SPR_NOACCESS,
5158 &spr_read_generic, &spr_write_generic,
5159 0x00000000);
5160 spr_register(env, SPR_USPRG6, "USPRG6",
5161 &spr_read_ureg, SPR_NOACCESS,
5162 &spr_read_ureg, SPR_NOACCESS,
5163 0x00000000);
5164 spr_register(env, SPR_SPRG7, "SPRG7",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_generic,
5167 0x00000000);
5168 spr_register(env, SPR_USPRG7, "USPRG7",
5169 &spr_read_ureg, SPR_NOACCESS,
5170 &spr_read_ureg, SPR_NOACCESS,
5171 0x00000000);
5172 /* Memory management */
5173 gen_low_BATs(env);
5174 gen_high_BATs(env);
578bb252 5175 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5176 init_excp_7450(env);
d63001d1
JM		 5177 env->dcache_line_size = 32;
5178 env->icache_line_size = 32;
a750fc0b
JM		 5179 /* Allocate hardware IRQ controller */
5180 ppc6xx_irq_init(env);
5181}
a750fc0b
JM		 5182
5183#if defined (TARGET_PPC64)
5184/* PowerPC 970 */
082c6681
JM		 5185#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5186 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5187 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5188 PPC_FLOAT_STFIWX | \
5189 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5190 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5191 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5192 PPC_64B | PPC_ALTIVEC | \
12de9a39 5193 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5194#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 5195#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 5196//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5197#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 5198#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 5199#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5200 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5201 POWERPC_FLAG_BUS_CLK)
a750fc0b 5202
417bf010
JM		 5203#if defined(CONFIG_USER_ONLY)
5204#define POWERPC970_HID5_INIT 0x00000080
5205#else
5206#define POWERPC970_HID5_INIT 0x00000000
5207#endif
5208
2f462816
JM		 5209static int check_pow_970 (CPUPPCState *env)
5210{
5211 if (env->spr[SPR_HID0] & 0x00600000)
5212 return 1;
5213
5214 return 0;
5215}
5216
a750fc0b
JM		 5217static void init_proc_970 (CPUPPCState *env)
5218{
5219 gen_spr_ne_601(env);
5220 gen_spr_7xx(env);
5221 /* Time base */
5222 gen_tbl(env);
5223 /* Hardware implementation registers */
5224 /* XXX : not implemented */
5225 spr_register(env, SPR_HID0, "HID0",
5226 SPR_NOACCESS, SPR_NOACCESS,
06403421 5227 &spr_read_generic, &spr_write_clear,
d63001d1 5228 0x60000000);
a750fc0b
JM		 5229 /* XXX : not implemented */
5230 spr_register(env, SPR_HID1, "HID1",
5231 SPR_NOACCESS, SPR_NOACCESS,
5232 &spr_read_generic, &spr_write_generic,
5233 0x00000000);
5234 /* XXX : not implemented */
5235 spr_register(env, SPR_750_HID2, "HID2",
5236 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic,
5238 0x00000000);
e57448f1
JM		 5239 /* XXX : not implemented */
5240 spr_register(env, SPR_970_HID5, "HID5",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
417bf010 5243 POWERPC970_HID5_INIT);
a750fc0b
JM		 5244 /* Memory management */
5245 /* XXX: not correct */
5246 gen_low_BATs(env);
12de9a39
JM		 5247 /* XXX : not implemented */
5248 spr_register(env, SPR_MMUCFG, "MMUCFG",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, SPR_NOACCESS,
5251 0x00000000); /* TOFIX */
5252 /* XXX : not implemented */
5253 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5254 SPR_NOACCESS, SPR_NOACCESS,
5255 &spr_read_generic, &spr_write_generic,
5256 0x00000000); /* TOFIX */
5257 spr_register(env, SPR_HIOR, "SPR_HIOR",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5261#if !defined(CONFIG_USER_ONLY)
12de9a39 5262 env->slb_nr = 32;
f2e63a42 5263#endif
e1833e1f 5264 init_excp_970(env);
d63001d1
JM		 5265 env->dcache_line_size = 128;
5266 env->icache_line_size = 128;
a750fc0b
JM		 5267 /* Allocate hardware IRQ controller */
5268 ppc970_irq_init(env);
5269}
a750fc0b
JM		 5270
5271/* PowerPC 970FX (aka G5) */
082c6681
JM		 5272#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5273 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5274 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5275 PPC_FLOAT_STFIWX | \
5276 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5277 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5278 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5279 PPC_64B | PPC_ALTIVEC | \
12de9a39 5280 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5281#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 5282#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 5283#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5284#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 5285#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 5286#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5287 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5288 POWERPC_FLAG_BUS_CLK)
a750fc0b 5289
2f462816
JM		 5290static int check_pow_970FX (CPUPPCState *env)
5291{
5292 if (env->spr[SPR_HID0] & 0x00600000)
5293 return 1;
5294
5295 return 0;
5296}
5297
a750fc0b
JM		 5298static void init_proc_970FX (CPUPPCState *env)
5299{
5300 gen_spr_ne_601(env);
5301 gen_spr_7xx(env);
5302 /* Time base */
5303 gen_tbl(env);
5304 /* Hardware implementation registers */
5305 /* XXX : not implemented */
5306 spr_register(env, SPR_HID0, "HID0",
5307 SPR_NOACCESS, SPR_NOACCESS,
06403421 5308 &spr_read_generic, &spr_write_clear,
d63001d1 5309 0x60000000);
a750fc0b
JM		 5310 /* XXX : not implemented */
5311 spr_register(env, SPR_HID1, "HID1",
5312 SPR_NOACCESS, SPR_NOACCESS,
5313 &spr_read_generic, &spr_write_generic,
5314 0x00000000);
5315 /* XXX : not implemented */
5316 spr_register(env, SPR_750_HID2, "HID2",
5317 SPR_NOACCESS, SPR_NOACCESS,
5318 &spr_read_generic, &spr_write_generic,
5319 0x00000000);
d63001d1
JM		 5320 /* XXX : not implemented */
5321 spr_register(env, SPR_970_HID5, "HID5",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
417bf010 5324 POWERPC970_HID5_INIT);
a750fc0b
JM		 5325 /* Memory management */
5326 /* XXX: not correct */
5327 gen_low_BATs(env);
12de9a39
JM		 5328 /* XXX : not implemented */
5329 spr_register(env, SPR_MMUCFG, "MMUCFG",
5330 SPR_NOACCESS, SPR_NOACCESS,
5331 &spr_read_generic, SPR_NOACCESS,
5332 0x00000000); /* TOFIX */
5333 /* XXX : not implemented */
5334 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5335 SPR_NOACCESS, SPR_NOACCESS,
5336 &spr_read_generic, &spr_write_generic,
5337 0x00000000); /* TOFIX */
5338 spr_register(env, SPR_HIOR, "SPR_HIOR",
5339 SPR_NOACCESS, SPR_NOACCESS,
5340 &spr_read_generic, &spr_write_generic,
5341 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5342#if !defined(CONFIG_USER_ONLY)
12de9a39 5343 env->slb_nr = 32;
f2e63a42 5344#endif
e1833e1f 5345 init_excp_970(env);
d63001d1
JM		 5346 env->dcache_line_size = 128;
5347 env->icache_line_size = 128;
a750fc0b
JM		 5348 /* Allocate hardware IRQ controller */
5349 ppc970_irq_init(env);
5350}
a750fc0b
JM		 5351
5352/* PowerPC 970 GX */
082c6681
JM		 5353#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5354 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5355 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5356 PPC_FLOAT_STFIWX | \
5357 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5358 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5359 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5360 PPC_64B | PPC_ALTIVEC | \
12de9a39 5361 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5362#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 5363#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 5364#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
5365#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 5366#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 5367#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5368 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5369 POWERPC_FLAG_BUS_CLK)
a750fc0b 5370
2f462816
JM		 5371static int check_pow_970GX (CPUPPCState *env)
5372{
5373 if (env->spr[SPR_HID0] & 0x00600000)
5374 return 1;
5375
5376 return 0;
5377}
5378
a750fc0b
JM		 5379static void init_proc_970GX (CPUPPCState *env)
5380{
5381 gen_spr_ne_601(env);
5382 gen_spr_7xx(env);
5383 /* Time base */
5384 gen_tbl(env);
5385 /* Hardware implementation registers */
5386 /* XXX : not implemented */
5387 spr_register(env, SPR_HID0, "HID0",
5388 SPR_NOACCESS, SPR_NOACCESS,
06403421 5389 &spr_read_generic, &spr_write_clear,
d63001d1 5390 0x60000000);
a750fc0b
JM		 5391 /* XXX : not implemented */
5392 spr_register(env, SPR_HID1, "HID1",
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 &spr_read_generic, &spr_write_generic,
5395 0x00000000);
5396 /* XXX : not implemented */
5397 spr_register(env, SPR_750_HID2, "HID2",
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 &spr_read_generic, &spr_write_generic,
5400 0x00000000);
d63001d1
JM		 5401 /* XXX : not implemented */
5402 spr_register(env, SPR_970_HID5, "HID5",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic,
417bf010 5405 POWERPC970_HID5_INIT);
a750fc0b
JM		 5406 /* Memory management */
5407 /* XXX: not correct */
5408 gen_low_BATs(env);
12de9a39
JM		 5409 /* XXX : not implemented */
5410 spr_register(env, SPR_MMUCFG, "MMUCFG",
5411 SPR_NOACCESS, SPR_NOACCESS,
5412 &spr_read_generic, SPR_NOACCESS,
5413 0x00000000); /* TOFIX */
5414 /* XXX : not implemented */
5415 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5416 SPR_NOACCESS, SPR_NOACCESS,
5417 &spr_read_generic, &spr_write_generic,
5418 0x00000000); /* TOFIX */
5419 spr_register(env, SPR_HIOR, "SPR_HIOR",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5423#if !defined(CONFIG_USER_ONLY)
12de9a39 5424 env->slb_nr = 32;
f2e63a42 5425#endif
e1833e1f 5426 init_excp_970(env);
d63001d1
JM		 5427 env->dcache_line_size = 128;
5428 env->icache_line_size = 128;
a750fc0b
JM		 5429 /* Allocate hardware IRQ controller */
5430 ppc970_irq_init(env);
5431}
a750fc0b 5432
2f462816 5433/* PowerPC 970 MP */
082c6681
JM		 5434#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5435 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5436 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5437 PPC_FLOAT_STFIWX | \
5438 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5439 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5440 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 5441 PPC_64B | PPC_ALTIVEC | \
5442 PPC_SEGMENT_64B | PPC_SLBI)
5443#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
5444#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
5445#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
5446#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
5447#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
5448#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5449 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5450 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 5451
5452static int check_pow_970MP (CPUPPCState *env)
5453{
5454 if (env->spr[SPR_HID0] & 0x01C00000)
5455 return 1;
5456
5457 return 0;
5458}
5459
5460static void init_proc_970MP (CPUPPCState *env)
5461{
5462 gen_spr_ne_601(env);
5463 gen_spr_7xx(env);
5464 /* Time base */
5465 gen_tbl(env);
5466 /* Hardware implementation registers */
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_HID0, "HID0",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_clear,
5471 0x60000000);
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_HID1, "HID1",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* XXX : not implemented */
5478 spr_register(env, SPR_750_HID2, "HID2",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* XXX : not implemented */
5483 spr_register(env, SPR_970_HID5, "HID5",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic,
5486 POWERPC970_HID5_INIT);
5487 /* Memory management */
5488 /* XXX: not correct */
5489 gen_low_BATs(env);
5490 /* XXX : not implemented */
5491 spr_register(env, SPR_MMUCFG, "MMUCFG",
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 &spr_read_generic, SPR_NOACCESS,
5494 0x00000000); /* TOFIX */
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 &spr_read_generic, &spr_write_generic,
5499 0x00000000); /* TOFIX */
5500 spr_register(env, SPR_HIOR, "SPR_HIOR",
5501 SPR_NOACCESS, SPR_NOACCESS,
5502 &spr_read_generic, &spr_write_generic,
5503 0xFFF00000); /* XXX: This is a hack */
2f462816
JM		 5504#if !defined(CONFIG_USER_ONLY)
5505 env->slb_nr = 32;
5506#endif
5507 init_excp_970(env);
5508 env->dcache_line_size = 128;
5509 env->icache_line_size = 128;
5510 /* Allocate hardware IRQ controller */
5511 ppc970_irq_init(env);
5512}
5513
a750fc0b 5514/* PowerPC 620 */
082c6681
JM		 5515#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5516 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5517 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5518 PPC_FLOAT_STFIWX | \
5519 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5520 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5521 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5522 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5523 PPC_64B | PPC_SLBI)
add78955
JM		 5524#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
5525//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 5526#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 5527#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 5528#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 5529#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 5530 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 5531#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 5532
578bb252 5533__attribute__ (( unused ))
a750fc0b
JM		 5534static void init_proc_620 (CPUPPCState *env)
5535{
5536 gen_spr_ne_601(env);
5537 gen_spr_620(env);
5538 /* Time base */
5539 gen_tbl(env);
5540 /* Hardware implementation registers */
5541 /* XXX : not implemented */
5542 spr_register(env, SPR_HID0, "HID0",
5543 SPR_NOACCESS, SPR_NOACCESS,
5544 &spr_read_generic, &spr_write_generic,
5545 0x00000000);
5546 /* Memory management */
5547 gen_low_BATs(env);
e1833e1f 5548 init_excp_620(env);
d63001d1
JM		 5549 env->dcache_line_size = 64;
5550 env->icache_line_size = 64;
faadf50e
JM		 5551 /* Allocate hardware IRQ controller */
5552 ppc6xx_irq_init(env);
a750fc0b 5553}
a750fc0b
JM		 5554#endif /* defined (TARGET_PPC64) */
5555
5556/* Default 32 bits PowerPC target will be 604 */
5557#define CPU_POWERPC_PPC32 CPU_POWERPC_604
5558#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
5559#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
5560#define POWERPC_MMU_PPC32 POWERPC_MMU_604
5561#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
5562#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 5563#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 5564#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 5565#define check_pow_PPC32 check_pow_604
5566#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 5567
5568/* Default 64 bits PowerPC target will be 970 FX */
5569#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
5570#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
5571#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
5572#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
5573#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
5574#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 5575#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 5576#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 5577#define check_pow_PPC64 check_pow_970FX
5578#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 5579
5580/* Default PowerPC target will be PowerPC 32 */
5581#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 5582#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
5583#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
5584#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
5585#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
5586#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
5587#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 5588#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 5589#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 5590#define check_pow_DEFAULT check_pow_PPC64
5591#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 5592#else
d12f4c38
JM		 5593#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
5594#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
5595#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
5596#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
5597#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
5598#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 5599#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 5600#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 5601#define check_pow_DEFAULT check_pow_PPC32
5602#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 5603#endif
5604
5605/*****************************************************************************/
5606/* PVR definitions for most known PowerPC */
5607enum {
5608 /* PowerPC 401 family */
5609 /* Generic PowerPC 401 */
80d11f44 5610#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 5611 /* PowerPC 401 cores */
80d11f44
JM		 5612 CPU_POWERPC_401A1 = 0x00210000,
5613 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 5614#if 0
80d11f44 5615 CPU_POWERPC_401B3 = xxx,
a750fc0b 5616#endif
80d11f44
JM		 5617 CPU_POWERPC_401C2 = 0x00230000,
5618 CPU_POWERPC_401D2 = 0x00240000,
5619 CPU_POWERPC_401E2 = 0x00250000,
5620 CPU_POWERPC_401F2 = 0x00260000,
5621 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 5622 /* PowerPC 401 microcontrolers */
5623#if 0
80d11f44 5624 CPU_POWERPC_401GF = xxx,
a750fc0b 5625#endif
80d11f44 5626#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 5627 /* IBM Processor for Network Resources */
80d11f44 5628 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 5629#if 0
80d11f44 5630 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 5631#endif
5632 /* PowerPC 403 family */
5633 /* Generic PowerPC 403 */
80d11f44 5634#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 5635 /* PowerPC 403 microcontrollers */
80d11f44
JM		 5636 CPU_POWERPC_403GA = 0x00200011,
5637 CPU_POWERPC_403GB = 0x00200100,
5638 CPU_POWERPC_403GC = 0x00200200,
5639 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 5640#if 0
80d11f44 5641 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 5642#endif
5643 /* PowerPC 405 family */
5644 /* Generic PowerPC 405 */
80d11f44 5645#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 5646 /* PowerPC 405 cores */
5647#if 0
80d11f44 5648 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 5649#endif
5650#if 0
80d11f44 5651 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 5652#endif
5653#if 0
80d11f44 5654 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 5655#endif
5656#if 0
80d11f44 5657 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 5658#endif
5659#if 0
80d11f44 5660 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 5661#endif
5662#if 0
80d11f44 5663 CPU_POWERPC_405C4 = xxx,
a750fc0b 5664#endif
80d11f44 5665 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 5666#if 0
80d11f44 5667 CPU_POWERPC_405D3 = xxx,
a750fc0b 5668#endif
80d11f44 5669 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 5670#if 0
80d11f44 5671 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 5672#endif
5673#if 0
80d11f44 5674 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 5675#endif
5676#if 0
80d11f44 5677 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 5678#endif
5679#if 0
80d11f44 5680 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 5681#endif
5682#if 0
80d11f44 5683 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 5684#endif
5685 /* PowerPC 405 microcontrolers */
5686 /* XXX: missing 0x200108a0 */
80d11f44
JM		 5687#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
5688 CPU_POWERPC_405CRa = 0x40110041,
5689 CPU_POWERPC_405CRb = 0x401100C5,
5690 CPU_POWERPC_405CRc = 0x40110145,
5691 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 5692#if 0
80d11f44 5693 CPU_POWERPC_405EXr = xxx,
a750fc0b 5694#endif
80d11f44 5695 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 5696#if 0
80d11f44
JM		 5697 CPU_POWERPC_405FX = xxx,
5698#endif
5699#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
5700 CPU_POWERPC_405GPa = 0x40110000,
5701 CPU_POWERPC_405GPb = 0x40110040,
5702 CPU_POWERPC_405GPc = 0x40110082,
5703 CPU_POWERPC_405GPd = 0x401100C4,
5704#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
5705 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 5706#if 0
80d11f44 5707 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 5708#endif
5709#if 0
80d11f44 5710 CPU_POWERPC_405L = xxx,
a750fc0b 5711#endif
80d11f44 5712 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 5713#if 0
80d11f44 5714 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 5715#endif
5716#if 0
80d11f44 5717 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 5718#endif
5719#if 0
80d11f44 5720 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 5721#endif
5722 /* IBM network processors */
80d11f44
JM		 5723 CPU_POWERPC_NPE405H = 0x414100C0,
5724 CPU_POWERPC_NPE405H2 = 0x41410140,
5725 CPU_POWERPC_NPE405L = 0x416100C0,
5726 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 5727#if 0
80d11f44 5728 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 5729#endif
5730#if 0
80d11f44 5731 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 5732#endif
5733#if 0
80d11f44 5734 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 5735#endif
5736 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
5737#if 0
80d11f44 5738 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 5739#endif
5740#if 0
80d11f44 5741 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 5742#endif
5743#if 0
80d11f44 5744 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 5745#endif
80d11f44 5746 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 5747#if 0
80d11f44 5748 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 5749#endif
5750#if 0
80d11f44 5751 CPU_POWERPC_STB045 = xxx,
a750fc0b 5752#endif
80d11f44
JM		 5753 CPU_POWERPC_STB04 = 0x41810000,
5754 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 5755#if 0
80d11f44 5756 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 5757#endif
5758 /* Xilinx cores */
80d11f44
JM		 5759 CPU_POWERPC_X2VP4 = 0x20010820,
5760#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
5761 CPU_POWERPC_X2VP20 = 0x20010860,
5762#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 5763#if 0
80d11f44 5764 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 5765#endif
5766#if 0
80d11f44 5767 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 5768#endif
5769#if 0
80d11f44 5770 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 5771#endif
5772#if 0
80d11f44 5773 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 5774#endif
5775 /* PowerPC 440 family */
5776 /* Generic PowerPC 440 */
80d11f44 5777#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 5778 /* PowerPC 440 cores */
5779#if 0
80d11f44 5780 CPU_POWERPC_440A4 = xxx,
a750fc0b
JM		 5781#endif
5782#if 0
80d11f44 5783 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 5784#endif
5785#if 0
80d11f44 5786 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 5787#endif
5788#if 0
80d11f44 5789 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 5790#endif
5791#if 0
80d11f44 5792 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 5793#endif
5794#if 0
80d11f44 5795 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 5796#endif
5797#if 0
80d11f44 5798 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 5799#endif
5800 /* PowerPC 440 microcontrolers */
80d11f44
JM		 5801#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
5802 CPU_POWERPC_440EPa = 0x42221850,
5803 CPU_POWERPC_440EPb = 0x422218D3,
5804#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
5805 CPU_POWERPC_440GPb = 0x40120440,
5806 CPU_POWERPC_440GPc = 0x40120481,
5807#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
5808#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
5809 CPU_POWERPC_440GRX = 0x200008D0,
5810#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
5811#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
5812 CPU_POWERPC_440GXa = 0x51B21850,
5813 CPU_POWERPC_440GXb = 0x51B21851,
5814 CPU_POWERPC_440GXc = 0x51B21892,
5815 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 5816#if 0
80d11f44 5817 CPU_POWERPC_440S = xxx,
a750fc0b 5818#endif
80d11f44
JM		 5819 CPU_POWERPC_440SP = 0x53221850,
5820 CPU_POWERPC_440SP2 = 0x53221891,
5821 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 5822 /* PowerPC 460 family */
5823#if 0
5824 /* Generic PowerPC 464 */
80d11f44 5825#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 5826#endif
5827 /* PowerPC 464 microcontrolers */
5828#if 0
80d11f44 5829 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 5830#endif
5831#if 0
80d11f44 5832 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 5833#endif
5834 /* Freescale embedded PowerPC cores */
c3e36823 5835 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 5836 CPU_POWERPC_MPC5xx = 0x00020020,
5837#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
5838#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
5839#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
5840#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
5841#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
5842#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
5843#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
5844#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
5845#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
5846#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
5847#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
5848#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
5849#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 5850 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 5851 CPU_POWERPC_MPC8xx = 0x00500000,
5852#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
5853#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
5854#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
5855#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
5856#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
5857#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
5858#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
5859#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
5860#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
5861#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
5862#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
5863#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
5864#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
5865#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
5866#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 5867 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 5868 CPU_POWERPC_G2 = 0x00810011,
5869 CPU_POWERPC_G2H4 = 0x80811010,
5870 CPU_POWERPC_G2gp = 0x80821010,
5871 CPU_POWERPC_G2ls = 0x90810010,
5872 CPU_POWERPC_MPC603 = 0x00810100,
5873 CPU_POWERPC_G2_HIP3 = 0x00810101,
5874 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 5875 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 5876 CPU_POWERPC_G2LE = 0x80820010,
5877 CPU_POWERPC_G2LEgp = 0x80822010,
5878 CPU_POWERPC_G2LEls = 0xA0822010,
5879 CPU_POWERPC_G2LEgp1 = 0x80822011,
5880 CPU_POWERPC_G2LEgp3 = 0x80822013,
5881 /* MPC52xx microcontrollers */
c3e36823 5882 /* XXX: MPC 5121 ? */
80d11f44
JM		 5883#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
5884#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
5885#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
5886#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
5887#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
5888#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
5889#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
5890#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
5891 /* MPC82xx microcontrollers */
5892#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
5893#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
5894#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
5895#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
5896#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
5897#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
5898#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
5899#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
5900#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
5901#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
5902#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
5903#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
5904#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
5905#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
5906#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
5907#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
5908#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
5909#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
5910#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
5911#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
5912#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
5913#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
5914#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
5915#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
5916#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
5917#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
5918#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
5919#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
5920#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 5921 /* e200 family */
80d11f44
JM		 5922 /* e200 cores */
5923#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 5924#if 0
80d11f44 5925 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 5926#endif
5927#if 0
80d11f44 5928 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 5929#endif
5930#if 0 /* ? */
80d11f44
JM		 5931 CPU_POWERPC_e200z3 = 0x81120000,
5932#endif
5933 CPU_POWERPC_e200z5 = 0x81000000,
5934 CPU_POWERPC_e200z6 = 0x81120000,
5935 /* MPC55xx microcontrollers */
5936#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
5937#if 0
5938#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
5939#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
5940#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
5941#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
5942#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
5943#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
5944#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
5945#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
5946#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
5947#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
5948#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
5949#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
5950#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
5951#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
5952#endif
5953#if 0
5954#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
5955#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
5956#endif
5957#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
5958#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
5959#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
5960#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
5961#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
5962#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 5963 /* e300 family */
80d11f44
JM		 5964 /* e300 cores */
5965#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
5966 CPU_POWERPC_e300c1 = 0x00830010,
5967 CPU_POWERPC_e300c2 = 0x00840010,
5968 CPU_POWERPC_e300c3 = 0x00850010,
5969 CPU_POWERPC_e300c4 = 0x00860010,
5970 /* MPC83xx microcontrollers */
5971#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
5972#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
5973#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
5974#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
5975#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
5976#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
5977#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
5978#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
5979#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
5980#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
5981#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
5982#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
5983#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
5984#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
5985#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
5986#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
5987#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
5988#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
5989#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
5990#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
5991#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
5992#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
5993#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
5994#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
5995#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
5996#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
5997#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
5998#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
5999#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6000#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
a750fc0b 6001 /* e500 family */
80d11f44
JM		 6002 /* e500 cores */
6003#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
6004#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
6005 CPU_POWERPC_e500_v10 = 0x80200010,
6006 CPU_POWERPC_e500_v20 = 0x80200020,
6007 CPU_POWERPC_e500v2_v10 = 0x80210010,
6008 CPU_POWERPC_e500v2_v11 = 0x80210011,
6009 CPU_POWERPC_e500v2_v20 = 0x80210020,
6010 CPU_POWERPC_e500v2_v21 = 0x80210021,
6011 CPU_POWERPC_e500v2_v22 = 0x80210022,
6012 CPU_POWERPC_e500v2_v30 = 0x80210030,
6013 /* MPC85xx microcontrollers */
6014#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6015#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6016#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6017#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6018#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6019#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6020#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
6021#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
6022#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
6023#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
6024#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
6025#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
6026#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
6027#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
6028#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
6029#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
6030#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6031#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6032#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6033#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6034#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6035#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6036#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6037#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6038#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6039#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6040#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6041#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6042#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6043#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6044#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6045#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6046#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6047#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6048#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6049#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6050#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6051#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6052#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6053#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6054#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6055#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6056#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6057#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6058#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6059#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6060#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6061#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6062#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6063#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6064#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6065#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6066#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6067#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6068#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6069#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6070#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6071#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6072#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6073#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6074#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6075#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6076#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6077#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6078#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6079#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6080#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6081#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6082#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6083#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 6084 /* e600 family */
80d11f44
JM		 6085 /* e600 cores */
6086 CPU_POWERPC_e600 = 0x80040010,
6087 /* MPC86xx microcontrollers */
6088#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6089#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6090#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 6091 /* PowerPC 6xx cores */
80d11f44
JM		 6092#define CPU_POWERPC_601 CPU_POWERPC_601_v2
6093 CPU_POWERPC_601_v0 = 0x00010001,
6094 CPU_POWERPC_601_v1 = 0x00010001,
6095 CPU_POWERPC_601_v2 = 0x00010002,
6096 CPU_POWERPC_602 = 0x00050100,
6097 CPU_POWERPC_603 = 0x00030100,
6098#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6099 CPU_POWERPC_603E_v11 = 0x00060101,
6100 CPU_POWERPC_603E_v12 = 0x00060102,
6101 CPU_POWERPC_603E_v13 = 0x00060103,
6102 CPU_POWERPC_603E_v14 = 0x00060104,
6103 CPU_POWERPC_603E_v22 = 0x00060202,
6104 CPU_POWERPC_603E_v3 = 0x00060300,
6105 CPU_POWERPC_603E_v4 = 0x00060400,
6106 CPU_POWERPC_603E_v41 = 0x00060401,
6107 CPU_POWERPC_603E7t = 0x00071201,
6108 CPU_POWERPC_603E7v = 0x00070100,
6109 CPU_POWERPC_603E7v1 = 0x00070101,
6110 CPU_POWERPC_603E7v2 = 0x00070201,
6111 CPU_POWERPC_603E7 = 0x00070200,
6112 CPU_POWERPC_603P = 0x00070000,
6113#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 6114 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 6115 CPU_POWERPC_604 = 0x00040103,
6116#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 6117 /* XXX: missing 0x00091203 */
6118 /* XXX: missing 0x00092110 */
6119 /* XXX: missing 0x00092120 */
80d11f44
JM		 6120 CPU_POWERPC_604E_v10 = 0x00090100,
6121 CPU_POWERPC_604E_v22 = 0x00090202,
6122 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 6123 /* XXX: missing 0x000a0100 */
6124 /* XXX: missing 0x00093102 */
80d11f44 6125 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 6126#if 0
80d11f44 6127 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 6128#endif
6129 /* PowerPC 740/750 cores (aka G3) */
6130 /* XXX: missing 0x00084202 */
80d11f44
JM		 6131#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
6132 CPU_POWERPC_7x0_v20 = 0x00080200,
6133 CPU_POWERPC_7x0_v21 = 0x00080201,
6134 CPU_POWERPC_7x0_v22 = 0x00080202,
6135 CPU_POWERPC_7x0_v30 = 0x00080300,
6136 CPU_POWERPC_7x0_v31 = 0x00080301,
6137 CPU_POWERPC_740E = 0x00080100,
6138 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 6139 /* XXX: missing 0x00087010 (CL ?) */
80d11f44
JM		 6140 CPU_POWERPC_750CL = 0x00087200,
6141#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
6142 CPU_POWERPC_750CX_v21 = 0x00082201,
6143 CPU_POWERPC_750CX_v22 = 0x00082202,
6144#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6145 CPU_POWERPC_750CXE_v21 = 0x00082211,
6146 CPU_POWERPC_750CXE_v22 = 0x00082212,
6147 CPU_POWERPC_750CXE_v23 = 0x00082213,
6148 CPU_POWERPC_750CXE_v24 = 0x00082214,
6149 CPU_POWERPC_750CXE_v24b = 0x00083214,
6150 CPU_POWERPC_750CXE_v31 = 0x00083211,
6151 CPU_POWERPC_750CXE_v31b = 0x00083311,
6152 CPU_POWERPC_750CXR = 0x00083410,
6153 CPU_POWERPC_750E = 0x00080200,
6154 CPU_POWERPC_750FL = 0x700A0203,
6155#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6156 CPU_POWERPC_750FX_v10 = 0x70000100,
6157 CPU_POWERPC_750FX_v20 = 0x70000200,
6158 CPU_POWERPC_750FX_v21 = 0x70000201,
6159 CPU_POWERPC_750FX_v22 = 0x70000202,
6160 CPU_POWERPC_750FX_v23 = 0x70000203,
6161 CPU_POWERPC_750GL = 0x70020102,
6162#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6163 CPU_POWERPC_750GX_v10 = 0x70020100,
6164 CPU_POWERPC_750GX_v11 = 0x70020101,
6165 CPU_POWERPC_750GX_v12 = 0x70020102,
6166#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
6167 CPU_POWERPC_750L_v22 = 0x00088202,
6168 CPU_POWERPC_750L_v30 = 0x00088300,
6169 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 6170 /* PowerPC 745/755 cores */
80d11f44
JM		 6171#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6172 CPU_POWERPC_7x5_v10 = 0x00083100,
6173 CPU_POWERPC_7x5_v11 = 0x00083101,
6174 CPU_POWERPC_7x5_v20 = 0x00083200,
6175 CPU_POWERPC_7x5_v21 = 0x00083201,
6176 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6177 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6178 CPU_POWERPC_7x5_v24 = 0x00083204,
6179 CPU_POWERPC_7x5_v25 = 0x00083205,
6180 CPU_POWERPC_7x5_v26 = 0x00083206,
6181 CPU_POWERPC_7x5_v27 = 0x00083207,
6182 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 6183#if 0
80d11f44 6184 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 6185#endif
6186 /* PowerPC 74xx cores (aka G4) */
6187 /* XXX: missing 0x000C1101 */
80d11f44
JM		 6188#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6189 CPU_POWERPC_7400_v10 = 0x000C0100,
6190 CPU_POWERPC_7400_v11 = 0x000C0101,
6191 CPU_POWERPC_7400_v20 = 0x000C0200,
6192 CPU_POWERPC_7400_v22 = 0x000C0202,
6193 CPU_POWERPC_7400_v26 = 0x000C0206,
6194 CPU_POWERPC_7400_v27 = 0x000C0207,
6195 CPU_POWERPC_7400_v28 = 0x000C0208,
6196 CPU_POWERPC_7400_v29 = 0x000C0209,
6197#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6198 CPU_POWERPC_7410_v10 = 0x800C1100,
6199 CPU_POWERPC_7410_v11 = 0x800C1101,
6200 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6201 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6202 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6203#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6204 CPU_POWERPC_7448_v10 = 0x80040100,
6205 CPU_POWERPC_7448_v11 = 0x80040101,
6206 CPU_POWERPC_7448_v20 = 0x80040200,
6207 CPU_POWERPC_7448_v21 = 0x80040201,
6208#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6209 CPU_POWERPC_7450_v10 = 0x80000100,
6210 CPU_POWERPC_7450_v11 = 0x80000101,
6211 CPU_POWERPC_7450_v12 = 0x80000102,
6212 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
6213 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
6214 CPU_POWERPC_74x1 = 0x80000203,
6215 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
6216#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6217 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 6218 /* XXX: missing 0x80010200 */
80d11f44
JM		 6219 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6220 CPU_POWERPC_74x5_v32 = 0x80010302,
6221 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6222 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6223#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 6224 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 6225 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 6226 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 6227#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6228 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6229 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6230 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 6231 /* 64 bits PowerPC */
00af685f 6232#if defined(TARGET_PPC64)
80d11f44
JM		 6233 CPU_POWERPC_620 = 0x00140000,
6234 CPU_POWERPC_630 = 0x00400000,
6235 CPU_POWERPC_631 = 0x00410104,
6236 CPU_POWERPC_POWER4 = 0x00350000,
6237 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 6238 /* XXX: missing 0x003A0201 */
80d11f44
JM		 6239 CPU_POWERPC_POWER5 = 0x003A0203,
6240#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6241 CPU_POWERPC_POWER5P = 0x003B0000,
6242#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6243 CPU_POWERPC_POWER6 = 0x003E0000,
6244 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6245 CPU_POWERPC_POWER6A = 0x0F000002,
6246 CPU_POWERPC_970 = 0x00390202,
6247#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6248 CPU_POWERPC_970FX_v10 = 0x00391100,
6249 CPU_POWERPC_970FX_v20 = 0x003C0200,
6250 CPU_POWERPC_970FX_v21 = 0x003C0201,
6251 CPU_POWERPC_970FX_v30 = 0x003C0300,
6252 CPU_POWERPC_970FX_v31 = 0x003C0301,
6253 CPU_POWERPC_970GX = 0x00450000,
6254#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6255 CPU_POWERPC_970MP_v10 = 0x00440100,
6256 CPU_POWERPC_970MP_v11 = 0x00440101,
6257#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6258 CPU_POWERPC_CELL_v10 = 0x00700100,
6259 CPU_POWERPC_CELL_v20 = 0x00700400,
6260 CPU_POWERPC_CELL_v30 = 0x00700500,
6261 CPU_POWERPC_CELL_v31 = 0x00700501,
6262#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
6263 CPU_POWERPC_RS64 = 0x00330000,
6264 CPU_POWERPC_RS64II = 0x00340000,
6265 CPU_POWERPC_RS64III = 0x00360000,
6266 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 6267#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 6268 /* Original POWER */
6269 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6270 * POWER2 (RIOS2) & RSC2 (P2SC) here
6271 */
6272#if 0
80d11f44 6273 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 6274#endif
6275#if 0
80d11f44 6276 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 6277#endif
6278 /* PA Semi core */
80d11f44 6279 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 6280};
6281
6282/* System version register (used on MPC 8xxx) */
6283enum {
80d11f44
JM		 6284 POWERPC_SVR_NONE = 0x00000000,
6285#define POWERPC_SVR_52xx POWERPC_SVR_5200
6286#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
6287 POWERPC_SVR_5200_v10 = 0x80110010,
6288 POWERPC_SVR_5200_v11 = 0x80110011,
6289 POWERPC_SVR_5200_v12 = 0x80110012,
6290#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
6291 POWERPC_SVR_5200B_v20 = 0x80110020,
6292 POWERPC_SVR_5200B_v21 = 0x80110021,
6293#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 6294#if 0
80d11f44 6295 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 6296#endif
6297#if 0
80d11f44 6298 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 6299#endif
6300#if 0
80d11f44 6301 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 6302#endif
6303#if 0
80d11f44 6304 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 6305#endif
6306#if 0
80d11f44 6307 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 6308#endif
6309#if 0
80d11f44 6310 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 6311#endif
6312#if 0
80d11f44 6313 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 6314#endif
6315#if 0
80d11f44 6316 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 6317#endif
6318#if 0
80d11f44 6319 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 6320#endif
6321#if 0
80d11f44 6322 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 6323#endif
6324#if 0
80d11f44 6325 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 6326#endif
6327#if 0
80d11f44 6328 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 6329#endif
6330#if 0
80d11f44 6331 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 6332#endif
6333#if 0
80d11f44 6334 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 6335#endif
6336#if 0
80d11f44 6337 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 6338#endif
6339#if 0
80d11f44 6340 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 6341#endif
6342#if 0
80d11f44 6343 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 6344#endif
6345#if 0
80d11f44
JM		 6346 POWERPC_SVR_8323E = xxx,
6347#endif
6348 POWERPC_SVR_8343A = 0x80570030,
6349 POWERPC_SVR_8343EA = 0x80560030,
6350#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
6351 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
6352 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
6353#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
6354 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
6355 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
6356 POWERPC_SVR_8349 = 0x80510010,
6357 POWERPC_SVR_8349A = 0x80510030,
6358 POWERPC_SVR_8349E = 0x80500010,
6359 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 6360#if 0
80d11f44 6361 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 6362#endif
6363#if 0
80d11f44
JM		 6364 POWERPC_SVR_8360E = xxx,
6365#endif
6366#define POWERPC_SVR_E500 0x40000000
6367 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
6368 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
6369 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
6370 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
6371 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
6372 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
6373#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
6374 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
6375 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
6376#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
6377 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
6378 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
6379#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
6380 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
6381 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
6382 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
6383#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
6384 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
6385 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
6386#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
6387 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
6388 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
6389#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
6390 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
6391 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
6392 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
6393 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
6394#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
6395 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
6396 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
6397 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
6398 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
6399#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
6400 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
6401 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
6402#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
6403 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
6404 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
6405#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
6406 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
6407 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
6408#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
6409 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
6410 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
6411#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
6412 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
6413 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
6414#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
6415 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
6416 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
6417 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
6418 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
6419#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
6420 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
6421 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
6422 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
6423 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
6424#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
6425 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
6426 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
6427#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
6428 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
6429 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
6430#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
6431 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
6432 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
6433 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
6434 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
6435 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
6436 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
6437 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
6438 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
6439 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 6440#if 0
80d11f44 6441 POWERPC_SVR_8610 = xxx,
c3e36823 6442#endif
80d11f44
JM		 6443 POWERPC_SVR_8641 = 0x80900021,
6444 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 6445};
6446
3fc6c082 6447/*****************************************************************************/
a750fc0b 6448/* PowerPC CPU definitions */
80d11f44 6449#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 6450 { \
6451 .name = _name, \
6452 .pvr = _pvr, \
80d11f44 6453 .svr = _svr, \
a750fc0b
JM		 6454 .insns_flags = glue(POWERPC_INSNS_,_type), \
6455 .msr_mask = glue(POWERPC_MSRM_,_type), \
6456 .mmu_model = glue(POWERPC_MMU_,_type), \
6457 .excp_model = glue(POWERPC_EXCP_,_type), \
6458 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 6459 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 6460 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 6461 .init_proc = &glue(init_proc_,_type), \
2f462816 6462 .check_pow = &glue(check_pow_,_type), \
a750fc0b 6463 }
80d11f44
JM		 6464#define POWERPC_DEF(_name, _pvr, _type) \
6465POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 6466
ee4e83ed 6467static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 6468 /* Embedded PowerPC */
6469 /* PowerPC 401 family */
2662a059 6470 /* Generic PowerPC 401 */
80d11f44 6471 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 6472 /* PowerPC 401 cores */
2662a059 6473 /* PowerPC 401A1 */
80d11f44 6474 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 6475 /* PowerPC 401B2 */
80d11f44 6476 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 6477#if defined (TODO)
a750fc0b 6478 /* PowerPC 401B3 */
80d11f44 6479 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 6480#endif
6481 /* PowerPC 401C2 */
80d11f44 6482 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 6483 /* PowerPC 401D2 */
80d11f44 6484 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 6485 /* PowerPC 401E2 */
80d11f44 6486 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 6487 /* PowerPC 401F2 */
80d11f44 6488 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 6489 /* PowerPC 401G2 */
6490 /* XXX: to be checked */
80d11f44 6491 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 6492 /* PowerPC 401 microcontrolers */
2662a059 6493#if defined (TODO)
a750fc0b 6494 /* PowerPC 401GF */
80d11f44 6495 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 6496#endif
a750fc0b 6497 /* IOP480 (401 microcontroler) */
80d11f44 6498 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 6499 /* IBM Processor for Network Resources */
80d11f44 6500 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 6501#if defined (TODO)
80d11f44 6502 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 6503#endif
a750fc0b
JM		 6504 /* PowerPC 403 family */
6505 /* Generic PowerPC 403 */
80d11f44 6506 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 6507 /* PowerPC 403 microcontrolers */
6508 /* PowerPC 403 GA */
80d11f44 6509 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 6510 /* PowerPC 403 GB */
80d11f44 6511 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 6512 /* PowerPC 403 GC */
80d11f44 6513 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 6514 /* PowerPC 403 GCX */
80d11f44 6515 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 6516#if defined (TODO)
a750fc0b 6517 /* PowerPC 403 GP */
80d11f44 6518 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 6519#endif
a750fc0b
JM		 6520 /* PowerPC 405 family */
6521 /* Generic PowerPC 405 */
80d11f44 6522 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 6523 /* PowerPC 405 cores */
2662a059 6524#if defined (TODO)
a750fc0b 6525 /* PowerPC 405 A3 */
80d11f44 6526 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 6527#endif
3a607854 6528#if defined (TODO)
a750fc0b 6529 /* PowerPC 405 A4 */
80d11f44 6530 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 6531#endif
3a607854 6532#if defined (TODO)
a750fc0b 6533 /* PowerPC 405 B3 */
80d11f44 6534 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 6535#endif
6536#if defined (TODO)
a750fc0b 6537 /* PowerPC 405 B4 */
80d11f44 6538 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 6539#endif
6540#if defined (TODO)
6541 /* PowerPC 405 C3 */
80d11f44 6542 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 6543#endif
6544#if defined (TODO)
6545 /* PowerPC 405 C4 */
80d11f44 6546 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 6547#endif
6548 /* PowerPC 405 D2 */
80d11f44 6549 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 6550#if defined (TODO)
6551 /* PowerPC 405 D3 */
80d11f44 6552 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 6553#endif
6554 /* PowerPC 405 D4 */
80d11f44 6555 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 6556#if defined (TODO)
6557 /* PowerPC 405 D5 */
80d11f44 6558 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 6559#endif
6560#if defined (TODO)
6561 /* PowerPC 405 E4 */
80d11f44 6562 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 6563#endif
6564#if defined (TODO)
6565 /* PowerPC 405 F4 */
80d11f44 6566 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 6567#endif
6568#if defined (TODO)
6569 /* PowerPC 405 F5 */
80d11f44 6570 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 6571#endif
6572#if defined (TODO)
6573 /* PowerPC 405 F6 */
80d11f44 6574 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 6575#endif
6576 /* PowerPC 405 microcontrolers */
6577 /* PowerPC 405 CR */
80d11f44 6578 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 6579 /* PowerPC 405 CRa */
80d11f44 6580 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 6581 /* PowerPC 405 CRb */
80d11f44 6582 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 6583 /* PowerPC 405 CRc */
80d11f44 6584 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 6585 /* PowerPC 405 EP */
80d11f44 6586 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 6587#if defined(TODO)
6588 /* PowerPC 405 EXr */
80d11f44 6589 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 6590#endif
6591 /* PowerPC 405 EZ */
80d11f44 6592 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 6593#if defined(TODO)
6594 /* PowerPC 405 FX */
80d11f44 6595 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 6596#endif
6597 /* PowerPC 405 GP */
80d11f44 6598 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 6599 /* PowerPC 405 GPa */
80d11f44 6600 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 6601 /* PowerPC 405 GPb */
80d11f44 6602 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 6603 /* PowerPC 405 GPc */
80d11f44 6604 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 6605 /* PowerPC 405 GPd */
80d11f44 6606 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 6607 /* PowerPC 405 GPe */
80d11f44 6608 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 6609 /* PowerPC 405 GPR */
80d11f44 6610 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 6611#if defined(TODO)
6612 /* PowerPC 405 H */
80d11f44 6613 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 6614#endif
6615#if defined(TODO)
6616 /* PowerPC 405 L */
80d11f44 6617 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 6618#endif
6619 /* PowerPC 405 LP */
80d11f44 6620 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 6621#if defined(TODO)
6622 /* PowerPC 405 PM */
80d11f44 6623 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 6624#endif
6625#if defined(TODO)
6626 /* PowerPC 405 PS */
80d11f44 6627 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 6628#endif
6629#if defined(TODO)
6630 /* PowerPC 405 S */
80d11f44 6631 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 6632#endif
6633 /* Npe405 H */
80d11f44 6634 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 6635 /* Npe405 H2 */
80d11f44 6636 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 6637 /* Npe405 L */
80d11f44 6638 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 6639 /* Npe4GS3 */
80d11f44 6640 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 6641#if defined (TODO)
80d11f44 6642 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 6643#endif
6644#if defined (TODO)
80d11f44 6645 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 6646#endif
6647#if defined (TODO)
6648 /* PowerPC LC77700 (Sanyo) */
80d11f44 6649 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 6650#endif
6651 /* PowerPC 401/403/405 based set-top-box microcontrolers */
6652#if defined (TODO)
6653 /* STB010000 */
80d11f44 6654 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 6655#endif
6656#if defined (TODO)
6657 /* STB01010 */
80d11f44 6658 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 6659#endif
6660#if defined (TODO)
6661 /* STB0210 */
80d11f44 6662 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 6663#endif
6664 /* STB03xx */
80d11f44 6665 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 6666#if defined (TODO)
6667 /* STB043x */
80d11f44 6668 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 6669#endif
6670#if defined (TODO)
6671 /* STB045x */
80d11f44 6672 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 6673#endif
6674 /* STB04xx */
80d11f44 6675 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 6676 /* STB25xx */
80d11f44 6677 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 6678#if defined (TODO)
6679 /* STB130 */
80d11f44 6680 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 6681#endif
6682 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 6683 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
6684 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
6685 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
6686 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 6687#if defined (TODO)
6688 /* Zarlink ZL10310 */
80d11f44 6689 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 6690#endif
6691#if defined (TODO)
6692 /* Zarlink ZL10311 */
80d11f44 6693 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 6694#endif
6695#if defined (TODO)
6696 /* Zarlink ZL10320 */
80d11f44 6697 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 6698#endif
6699#if defined (TODO)
6700 /* Zarlink ZL10321 */
80d11f44 6701 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 6702#endif
6703 /* PowerPC 440 family */
80d11f44 6704#if defined(TODO_USER_ONLY)
a750fc0b 6705 /* Generic PowerPC 440 */
80d11f44
JM		 6706 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
6707#endif
a750fc0b
JM		 6708 /* PowerPC 440 cores */
6709#if defined (TODO)
6710 /* PowerPC 440 A4 */
80d11f44 6711 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b
JM		 6712#endif
6713#if defined (TODO)
6714 /* PowerPC 440 A5 */
80d11f44 6715 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 6716#endif
6717#if defined (TODO)
6718 /* PowerPC 440 B4 */
80d11f44 6719 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 6720#endif
6721#if defined (TODO)
6722 /* PowerPC 440 G4 */
80d11f44 6723 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 6724#endif
6725#if defined (TODO)
6726 /* PowerPC 440 F5 */
80d11f44 6727 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 6728#endif
6729#if defined (TODO)
6730 /* PowerPC 440 G5 */
80d11f44 6731 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 6732#endif
6733#if defined (TODO)
6734 /* PowerPC 440H4 */
80d11f44 6735 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 6736#endif
6737#if defined (TODO)
6738 /* PowerPC 440H6 */
80d11f44 6739 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 6740#endif
6741 /* PowerPC 440 microcontrolers */
80d11f44 6742#if defined(TODO_USER_ONLY)
a750fc0b 6743 /* PowerPC 440 EP */
80d11f44
JM		 6744 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
6745#endif
6746#if defined(TODO_USER_ONLY)
a750fc0b 6747 /* PowerPC 440 EPa */
80d11f44
JM		 6748 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
6749#endif
6750#if defined(TODO_USER_ONLY)
a750fc0b 6751 /* PowerPC 440 EPb */
80d11f44
JM		 6752 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
6753#endif
6754#if defined(TODO_USER_ONLY)
a750fc0b 6755 /* PowerPC 440 EPX */
80d11f44
JM		 6756 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
6757#endif
6758#if defined(TODO_USER_ONLY)
a750fc0b 6759 /* PowerPC 440 GP */
80d11f44
JM		 6760 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
6761#endif
6762#if defined(TODO_USER_ONLY)
a750fc0b 6763 /* PowerPC 440 GPb */
80d11f44
JM		 6764 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
6765#endif
6766#if defined(TODO_USER_ONLY)
a750fc0b 6767 /* PowerPC 440 GPc */
80d11f44
JM		 6768 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
6769#endif
6770#if defined(TODO_USER_ONLY)
a750fc0b 6771 /* PowerPC 440 GR */
80d11f44
JM		 6772 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
6773#endif
6774#if defined(TODO_USER_ONLY)
a750fc0b 6775 /* PowerPC 440 GRa */
80d11f44
JM		 6776 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
6777#endif
6778#if defined(TODO_USER_ONLY)
a750fc0b 6779 /* PowerPC 440 GRX */
80d11f44
JM		 6780 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
6781#endif
6782#if defined(TODO_USER_ONLY)
a750fc0b 6783 /* PowerPC 440 GX */
80d11f44
JM		 6784 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
6785#endif
6786#if defined(TODO_USER_ONLY)
a750fc0b 6787 /* PowerPC 440 GXa */
80d11f44
JM		 6788 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
6789#endif
6790#if defined(TODO_USER_ONLY)
a750fc0b 6791 /* PowerPC 440 GXb */
80d11f44
JM		 6792 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
6793#endif
6794#if defined(TODO_USER_ONLY)
a750fc0b 6795 /* PowerPC 440 GXc */
80d11f44
JM		 6796 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
6797#endif
6798#if defined(TODO_USER_ONLY)
a750fc0b 6799 /* PowerPC 440 GXf */
80d11f44
JM		 6800 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
6801#endif
a750fc0b
JM		 6802#if defined(TODO)
6803 /* PowerPC 440 S */
80d11f44 6804 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 6805#endif
80d11f44 6806#if defined(TODO_USER_ONLY)
a750fc0b 6807 /* PowerPC 440 SP */
80d11f44
JM		 6808 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
6809#endif
6810#if defined(TODO_USER_ONLY)
a750fc0b 6811 /* PowerPC 440 SP2 */
80d11f44
JM		 6812 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
6813#endif
6814#if defined(TODO_USER_ONLY)
a750fc0b 6815 /* PowerPC 440 SPE */
80d11f44
JM		 6816 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
6817#endif
a750fc0b
JM		 6818 /* PowerPC 460 family */
6819#if defined (TODO)
6820 /* Generic PowerPC 464 */
80d11f44 6821 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 6822#endif
6823 /* PowerPC 464 microcontrolers */
6824#if defined (TODO)
6825 /* PowerPC 464H90 */
80d11f44 6826 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 6827#endif
6828#if defined (TODO)
6829 /* PowerPC 464H90F */
80d11f44 6830 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 6831#endif
6832 /* Freescale embedded PowerPC cores */
80d11f44
JM		 6833 /* MPC5xx family (aka RCPU) */
6834#if defined(TODO_USER_ONLY)
6835 /* Generic MPC5xx core */
6836 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
6837#endif
6838#if defined(TODO_USER_ONLY)
6839 /* Codename for MPC5xx core */
6840 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
6841#endif
6842 /* MPC5xx microcontrollers */
6843#if defined(TODO_USER_ONLY)
6844 /* MGT560 */
6845 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
6846#endif
6847#if defined(TODO_USER_ONLY)
6848 /* MPC509 */
6849 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
6850#endif
6851#if defined(TODO_USER_ONLY)
6852 /* MPC533 */
6853 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
6854#endif
6855#if defined(TODO_USER_ONLY)
6856 /* MPC534 */
6857 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
6858#endif
6859#if defined(TODO_USER_ONLY)
6860 /* MPC555 */
6861 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
6862#endif
6863#if defined(TODO_USER_ONLY)
6864 /* MPC556 */
6865 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
6866#endif
6867#if defined(TODO_USER_ONLY)
6868 /* MPC560 */
6869 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
6870#endif
6871#if defined(TODO_USER_ONLY)
6872 /* MPC561 */
6873 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
6874#endif
6875#if defined(TODO_USER_ONLY)
6876 /* MPC562 */
6877 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
6878#endif
6879#if defined(TODO_USER_ONLY)
6880 /* MPC563 */
6881 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
6882#endif
6883#if defined(TODO_USER_ONLY)
6884 /* MPC564 */
6885 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
6886#endif
6887#if defined(TODO_USER_ONLY)
6888 /* MPC565 */
6889 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
6890#endif
6891#if defined(TODO_USER_ONLY)
6892 /* MPC566 */
6893 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
6894#endif
6895 /* MPC8xx family (aka PowerQUICC) */
6896#if defined(TODO_USER_ONLY)
6897 /* Generic MPC8xx core */
6898 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
6899#endif
6900#if defined(TODO_USER_ONLY)
6901 /* Codename for MPC8xx core */
6902 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
6903#endif
6904 /* MPC8xx microcontrollers */
6905#if defined(TODO_USER_ONLY)
6906 /* MGT823 */
6907 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
6908#endif
6909#if defined(TODO_USER_ONLY)
6910 /* MPC821 */
6911 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
6912#endif
6913#if defined(TODO_USER_ONLY)
6914 /* MPC823 */
6915 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
6916#endif
6917#if defined(TODO_USER_ONLY)
6918 /* MPC850 */
6919 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
6920#endif
6921#if defined(TODO_USER_ONLY)
6922 /* MPC852T */
6923 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
6924#endif
6925#if defined(TODO_USER_ONLY)
6926 /* MPC855T */
6927 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
6928#endif
6929#if defined(TODO_USER_ONLY)
6930 /* MPC857 */
6931 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
6932#endif
6933#if defined(TODO_USER_ONLY)
6934 /* MPC859 */
6935 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
6936#endif
6937#if defined(TODO_USER_ONLY)
6938 /* MPC860 */
6939 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
6940#endif
6941#if defined(TODO_USER_ONLY)
6942 /* MPC862 */
6943 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
6944#endif
6945#if defined(TODO_USER_ONLY)
6946 /* MPC866 */
6947 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
6948#endif
6949#if defined(TODO_USER_ONLY)
6950 /* MPC870 */
6951 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
6952#endif
6953#if defined(TODO_USER_ONLY)
6954 /* MPC875 */
6955 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
6956#endif
6957#if defined(TODO_USER_ONLY)
6958 /* MPC880 */
6959 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
6960#endif
6961#if defined(TODO_USER_ONLY)
6962 /* MPC885 */
6963 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
6964#endif
6965 /* MPC82xx family (aka PowerQUICC-II) */
6966 /* Generic MPC52xx core */
6967 POWERPC_DEF_SVR("MPC52xx",
6968 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
6969 /* Generic MPC82xx core */
6970 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
6971 /* Codename for MPC82xx */
6972 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
6973 /* PowerPC G2 core */
6974 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
6975 /* PowerPC G2 H4 core */
6976 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
6977 /* PowerPC G2 GP core */
6978 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
6979 /* PowerPC G2 LS core */
6980 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
6981 /* PowerPC G2 HiP3 core */
6982 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
6983 /* PowerPC G2 HiP4 core */
6984 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
6985 /* PowerPC MPC603 core */
6986 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
6987 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
6988 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
6989 /* PowerPC G2LE GP core */
6990 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
6991 /* PowerPC G2LE LS core */
6992 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
6993 /* PowerPC G2LE GP1 core */
6994 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
6995 /* PowerPC G2LE GP3 core */
6996 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
6997 /* PowerPC MPC603 microcontrollers */
6998 /* MPC8240 */
6999 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7000 /* PowerPC G2 microcontrollers */
082c6681 7001#if defined(TODO)
80d11f44
JM		 7002 /* MPC5121 */
7003 POWERPC_DEF_SVR("MPC5121",
7004 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7005#endif
7006 /* MPC5200 */
7007 POWERPC_DEF_SVR("MPC5200",
7008 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7009 /* MPC5200 v1.0 */
7010 POWERPC_DEF_SVR("MPC5200_v10",
7011 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7012 /* MPC5200 v1.1 */
7013 POWERPC_DEF_SVR("MPC5200_v11",
7014 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7015 /* MPC5200 v1.2 */
7016 POWERPC_DEF_SVR("MPC5200_v12",
7017 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7018 /* MPC5200B */
7019 POWERPC_DEF_SVR("MPC5200B",
7020 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7021 /* MPC5200B v2.0 */
7022 POWERPC_DEF_SVR("MPC5200B_v20",
7023 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7024 /* MPC5200B v2.1 */
7025 POWERPC_DEF_SVR("MPC5200B_v21",
7026 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7027 /* MPC8241 */
7028 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7029 /* MPC8245 */
7030 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7031 /* MPC8247 */
7032 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7033 /* MPC8248 */
7034 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7035 /* MPC8250 */
7036 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7037 /* MPC8250 HiP3 */
7038 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7039 /* MPC8250 HiP4 */
7040 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7041 /* MPC8255 */
7042 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7043 /* MPC8255 HiP3 */
7044 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7045 /* MPC8255 HiP4 */
7046 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7047 /* MPC8260 */
7048 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7049 /* MPC8260 HiP3 */
7050 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7051 /* MPC8260 HiP4 */
7052 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7053 /* MPC8264 */
7054 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7055 /* MPC8264 HiP3 */
7056 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7057 /* MPC8264 HiP4 */
7058 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7059 /* MPC8265 */
7060 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7061 /* MPC8265 HiP3 */
7062 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7063 /* MPC8265 HiP4 */
7064 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7065 /* MPC8266 */
7066 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7067 /* MPC8266 HiP3 */
7068 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7069 /* MPC8266 HiP4 */
7070 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7071 /* MPC8270 */
7072 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7073 /* MPC8271 */
7074 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7075 /* MPC8272 */
7076 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7077 /* MPC8275 */
7078 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7079 /* MPC8280 */
7080 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 7081 /* e200 family */
a750fc0b 7082 /* Generic PowerPC e200 core */
80d11f44
JM		 7083 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7084 /* Generic MPC55xx core */
7085#if defined (TODO)
7086 POWERPC_DEF_SVR("MPC55xx",
7087 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 7088#endif
7089#if defined (TODO)
80d11f44
JM		 7090 /* PowerPC e200z0 core */
7091 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 7092#endif
7093#if defined (TODO)
80d11f44
JM		 7094 /* PowerPC e200z1 core */
7095 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7096#endif
7097#if defined (TODO)
7098 /* PowerPC e200z3 core */
7099 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7100#endif
7101 /* PowerPC e200z5 core */
7102 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 7103 /* PowerPC e200z6 core */
80d11f44
JM		 7104 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7105 /* PowerPC e200 microcontrollers */
7106#if defined (TODO)
7107 /* MPC5514E */
7108 POWERPC_DEF_SVR("MPC5514E",
7109 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 7110#endif
a750fc0b 7111#if defined (TODO)
80d11f44
JM		 7112 /* MPC5514E v0 */
7113 POWERPC_DEF_SVR("MPC5514E_v0",
7114 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 7115#endif
7116#if defined (TODO)
80d11f44
JM		 7117 /* MPC5514E v1 */
7118 POWERPC_DEF_SVR("MPC5514E_v1",
7119 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 7120#endif
7121#if defined (TODO)
80d11f44
JM		 7122 /* MPC5514G */
7123 POWERPC_DEF_SVR("MPC5514G",
7124 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 7125#endif
7126#if defined (TODO)
80d11f44
JM		 7127 /* MPC5514G v0 */
7128 POWERPC_DEF_SVR("MPC5514G_v0",
7129 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 7130#endif
a750fc0b 7131#if defined (TODO)
80d11f44
JM		 7132 /* MPC5514G v1 */
7133 POWERPC_DEF_SVR("MPC5514G_v1",
7134 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 7135#endif
7136#if defined (TODO)
80d11f44
JM		 7137 /* MPC5515S */
7138 POWERPC_DEF_SVR("MPC5515S",
7139 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 7140#endif
7141#if defined (TODO)
80d11f44
JM		 7142 /* MPC5516E */
7143 POWERPC_DEF_SVR("MPC5516E",
7144 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 7145#endif
7146#if defined (TODO)
80d11f44
JM		 7147 /* MPC5516E v0 */
7148 POWERPC_DEF_SVR("MPC5516E_v0",
7149 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 7150#endif
7151#if defined (TODO)
80d11f44
JM		 7152 /* MPC5516E v1 */
7153 POWERPC_DEF_SVR("MPC5516E_v1",
7154 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 7155#endif
a750fc0b 7156#if defined (TODO)
80d11f44
JM		 7157 /* MPC5516G */
7158 POWERPC_DEF_SVR("MPC5516G",
7159 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 7160#endif
a750fc0b 7161#if defined (TODO)
80d11f44
JM		 7162 /* MPC5516G v0 */
7163 POWERPC_DEF_SVR("MPC5516G_v0",
7164 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 7165#endif
a750fc0b 7166#if defined (TODO)
80d11f44
JM		 7167 /* MPC5516G v1 */
7168 POWERPC_DEF_SVR("MPC5516G_v1",
7169 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 7170#endif
a750fc0b 7171#if defined (TODO)
80d11f44
JM		 7172 /* MPC5516S */
7173 POWERPC_DEF_SVR("MPC5516S",
7174 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 7175#endif
7176#if defined (TODO)
80d11f44
JM		 7177 /* MPC5533 */
7178 POWERPC_DEF_SVR("MPC5533",
7179 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 7180#endif
7181#if defined (TODO)
80d11f44
JM		 7182 /* MPC5534 */
7183 POWERPC_DEF_SVR("MPC5534",
7184 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 7185#endif
80d11f44
JM		 7186#if defined (TODO)
7187 /* MPC5553 */
7188 POWERPC_DEF_SVR("MPC5553",
7189 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7190#endif
7191#if defined (TODO)
7192 /* MPC5554 */
7193 POWERPC_DEF_SVR("MPC5554",
7194 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7195#endif
7196#if defined (TODO)
7197 /* MPC5561 */
7198 POWERPC_DEF_SVR("MPC5561",
7199 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7200#endif
7201#if defined (TODO)
7202 /* MPC5565 */
7203 POWERPC_DEF_SVR("MPC5565",
7204 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7205#endif
7206#if defined (TODO)
7207 /* MPC5566 */
7208 POWERPC_DEF_SVR("MPC5566",
7209 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7210#endif
7211#if defined (TODO)
7212 /* MPC5567 */
7213 POWERPC_DEF_SVR("MPC5567",
7214 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7215#endif
7216 /* e300 family */
7217 /* Generic PowerPC e300 core */
7218 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7219 /* PowerPC e300c1 core */
7220 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7221 /* PowerPC e300c2 core */
7222 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7223 /* PowerPC e300c3 core */
7224 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7225 /* PowerPC e300c4 core */
7226 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7227 /* PowerPC e300 microcontrollers */
7228#if defined (TODO)
7229 /* MPC8313 */
7230 POWERPC_DEF_SVR("MPC8313",
7231 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
7232#endif
7233#if defined (TODO)
7234 /* MPC8313E */
7235 POWERPC_DEF_SVR("MPC8313E",
7236 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
7237#endif
7238#if defined (TODO)
7239 /* MPC8314 */
7240 POWERPC_DEF_SVR("MPC8314",
7241 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
7242#endif
7243#if defined (TODO)
7244 /* MPC8314E */
7245 POWERPC_DEF_SVR("MPC8314E",
7246 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
7247#endif
7248#if defined (TODO)
7249 /* MPC8315 */
7250 POWERPC_DEF_SVR("MPC8315",
7251 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
7252#endif
7253#if defined (TODO)
7254 /* MPC8315E */
7255 POWERPC_DEF_SVR("MPC8315E",
7256 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
7257#endif
7258#if defined (TODO)
7259 /* MPC8321 */
7260 POWERPC_DEF_SVR("MPC8321",
7261 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
7262#endif
7263#if defined (TODO)
7264 /* MPC8321E */
7265 POWERPC_DEF_SVR("MPC8321E",
7266 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
7267#endif
7268#if defined (TODO)
7269 /* MPC8323 */
7270 POWERPC_DEF_SVR("MPC8323",
7271 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
7272#endif
7273#if defined (TODO)
7274 /* MPC8323E */
7275 POWERPC_DEF_SVR("MPC8323E",
7276 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
7277#endif
7278 /* MPC8343A */
7279 POWERPC_DEF_SVR("MPC8343A",
7280 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
7281 /* MPC8343EA */
7282 POWERPC_DEF_SVR("MPC8343EA",
7283 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
7284 /* MPC8347A */
7285 POWERPC_DEF_SVR("MPC8347A",
7286 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
7287 /* MPC8347AT */
7288 POWERPC_DEF_SVR("MPC8347AT",
7289 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
7290 /* MPC8347AP */
7291 POWERPC_DEF_SVR("MPC8347AP",
7292 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
7293 /* MPC8347EA */
7294 POWERPC_DEF_SVR("MPC8347EA",
7295 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
7296 /* MPC8347EAT */
7297 POWERPC_DEF_SVR("MPC8347EAT",
7298 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
7299 /* MPC8343EAP */
7300 POWERPC_DEF_SVR("MPC8347EAP",
7301 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
7302 /* MPC8349 */
7303 POWERPC_DEF_SVR("MPC8349",
7304 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
7305 /* MPC8349A */
7306 POWERPC_DEF_SVR("MPC8349A",
7307 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
7308 /* MPC8349E */
7309 POWERPC_DEF_SVR("MPC8349E",
7310 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
7311 /* MPC8349EA */
7312 POWERPC_DEF_SVR("MPC8349EA",
7313 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
7314#if defined (TODO)
7315 /* MPC8358E */
7316 POWERPC_DEF_SVR("MPC8358E",
7317 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
7318#endif
7319#if defined (TODO)
7320 /* MPC8360E */
7321 POWERPC_DEF_SVR("MPC8360E",
7322 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
7323#endif
7324 /* MPC8377 */
7325 POWERPC_DEF_SVR("MPC8377",
7326 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
7327 /* MPC8377E */
7328 POWERPC_DEF_SVR("MPC8377E",
7329 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
7330 /* MPC8378 */
7331 POWERPC_DEF_SVR("MPC8378",
7332 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
7333 /* MPC8378E */
7334 POWERPC_DEF_SVR("MPC8378E",
7335 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
7336 /* MPC8379 */
7337 POWERPC_DEF_SVR("MPC8379",
7338 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
7339 /* MPC8379E */
7340 POWERPC_DEF_SVR("MPC8379E",
7341 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
7342 /* e500 family */
7343 /* PowerPC e500 core */
7344 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
7345 /* PowerPC e500 v1.0 core */
7346 POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
7347 /* PowerPC e500 v2.0 core */
7348 POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
7349 /* PowerPC e500v2 core */
7350 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
7351 /* PowerPC e500v2 v1.0 core */
7352 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
7353 /* PowerPC e500v2 v2.0 core */
7354 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
7355 /* PowerPC e500v2 v2.1 core */
7356 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
7357 /* PowerPC e500v2 v2.2 core */
7358 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
7359 /* PowerPC e500v2 v3.0 core */
7360 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
7361 /* PowerPC e500 microcontrollers */
7362 /* MPC8533 */
7363 POWERPC_DEF_SVR("MPC8533",
7364 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
7365 /* MPC8533 v1.0 */
7366 POWERPC_DEF_SVR("MPC8533_v10",
7367 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
7368 /* MPC8533 v1.1 */
7369 POWERPC_DEF_SVR("MPC8533_v11",
7370 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
7371 /* MPC8533E */
7372 POWERPC_DEF_SVR("MPC8533E",
7373 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
7374 /* MPC8533E v1.0 */
7375 POWERPC_DEF_SVR("MPC8533E_v10",
7376 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
7377 POWERPC_DEF_SVR("MPC8533E_v11",
7378 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
7379 /* MPC8540 */
7380 POWERPC_DEF_SVR("MPC8540",
7381 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
7382 /* MPC8540 v1.0 */
7383 POWERPC_DEF_SVR("MPC8540_v10",
7384 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
7385 /* MPC8540 v2.0 */
7386 POWERPC_DEF_SVR("MPC8540_v20",
7387 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
7388 /* MPC8540 v2.1 */
7389 POWERPC_DEF_SVR("MPC8540_v21",
7390 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
7391 /* MPC8541 */
7392 POWERPC_DEF_SVR("MPC8541",
7393 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
7394 /* MPC8541 v1.0 */
7395 POWERPC_DEF_SVR("MPC8541_v10",
7396 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
7397 /* MPC8541 v1.1 */
7398 POWERPC_DEF_SVR("MPC8541_v11",
7399 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
7400 /* MPC8541E */
7401 POWERPC_DEF_SVR("MPC8541E",
7402 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
7403 /* MPC8541E v1.0 */
7404 POWERPC_DEF_SVR("MPC8541E_v10",
7405 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
7406 /* MPC8541E v1.1 */
7407 POWERPC_DEF_SVR("MPC8541E_v11",
7408 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
7409 /* MPC8543 */
7410 POWERPC_DEF_SVR("MPC8543",
7411 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
7412 /* MPC8543 v1.0 */
7413 POWERPC_DEF_SVR("MPC8543_v10",
7414 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
7415 /* MPC8543 v1.1 */
7416 POWERPC_DEF_SVR("MPC8543_v11",
7417 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
7418 /* MPC8543 v2.0 */
7419 POWERPC_DEF_SVR("MPC8543_v20",
7420 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
7421 /* MPC8543 v2.1 */
7422 POWERPC_DEF_SVR("MPC8543_v21",
7423 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
7424 /* MPC8543E */
7425 POWERPC_DEF_SVR("MPC8543E",
7426 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
7427 /* MPC8543E v1.0 */
7428 POWERPC_DEF_SVR("MPC8543E_v10",
7429 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
7430 /* MPC8543E v1.1 */
7431 POWERPC_DEF_SVR("MPC8543E_v11",
7432 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
7433 /* MPC8543E v2.0 */
7434 POWERPC_DEF_SVR("MPC8543E_v20",
7435 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
7436 /* MPC8543E v2.1 */
7437 POWERPC_DEF_SVR("MPC8543E_v21",
7438 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
7439 /* MPC8544 */
7440 POWERPC_DEF_SVR("MPC8544",
7441 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
7442 /* MPC8544 v1.0 */
7443 POWERPC_DEF_SVR("MPC8544_v10",
7444 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
7445 /* MPC8544 v1.1 */
7446 POWERPC_DEF_SVR("MPC8544_v11",
7447 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
7448 /* MPC8544E */
7449 POWERPC_DEF_SVR("MPC8544E",
7450 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
7451 /* MPC8544E v1.0 */
7452 POWERPC_DEF_SVR("MPC8544E_v10",
7453 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
7454 /* MPC8544E v1.1 */
7455 POWERPC_DEF_SVR("MPC8544E_v11",
7456 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
7457 /* MPC8545 */
7458 POWERPC_DEF_SVR("MPC8545",
7459 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
7460 /* MPC8545 v2.0 */
7461 POWERPC_DEF_SVR("MPC8545_v20",
7462 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
7463 /* MPC8545 v2.1 */
7464 POWERPC_DEF_SVR("MPC8545_v21",
7465 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
7466 /* MPC8545E */
7467 POWERPC_DEF_SVR("MPC8545E",
7468 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
7469 /* MPC8545E v2.0 */
7470 POWERPC_DEF_SVR("MPC8545E_v20",
7471 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
7472 /* MPC8545E v2.1 */
7473 POWERPC_DEF_SVR("MPC8545E_v21",
7474 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
7475 /* MPC8547E */
7476 POWERPC_DEF_SVR("MPC8547E",
7477 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
7478 /* MPC8547E v2.0 */
7479 POWERPC_DEF_SVR("MPC8547E_v20",
7480 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
7481 /* MPC8547E v2.1 */
7482 POWERPC_DEF_SVR("MPC8547E_v21",
7483 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
7484 /* MPC8548 */
7485 POWERPC_DEF_SVR("MPC8548",
7486 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
7487 /* MPC8548 v1.0 */
7488 POWERPC_DEF_SVR("MPC8548_v10",
7489 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
7490 /* MPC8548 v1.1 */
7491 POWERPC_DEF_SVR("MPC8548_v11",
7492 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
7493 /* MPC8548 v2.0 */
7494 POWERPC_DEF_SVR("MPC8548_v20",
7495 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
7496 /* MPC8548 v2.1 */
7497 POWERPC_DEF_SVR("MPC8548_v21",
7498 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
7499 /* MPC8548E */
7500 POWERPC_DEF_SVR("MPC8548E",
7501 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
7502 /* MPC8548E v1.0 */
7503 POWERPC_DEF_SVR("MPC8548E_v10",
7504 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
7505 /* MPC8548E v1.1 */
7506 POWERPC_DEF_SVR("MPC8548E_v11",
7507 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
7508 /* MPC8548E v2.0 */
7509 POWERPC_DEF_SVR("MPC8548E_v20",
7510 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
7511 /* MPC8548E v2.1 */
7512 POWERPC_DEF_SVR("MPC8548E_v21",
7513 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
7514 /* MPC8555 */
7515 POWERPC_DEF_SVR("MPC8555",
7516 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
7517 /* MPC8555 v1.0 */
7518 POWERPC_DEF_SVR("MPC8555_v10",
7519 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
7520 /* MPC8555 v1.1 */
7521 POWERPC_DEF_SVR("MPC8555_v11",
7522 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
7523 /* MPC8555E */
7524 POWERPC_DEF_SVR("MPC8555E",
7525 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
7526 /* MPC8555E v1.0 */
7527 POWERPC_DEF_SVR("MPC8555E_v10",
7528 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
7529 /* MPC8555E v1.1 */
7530 POWERPC_DEF_SVR("MPC8555E_v11",
7531 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
7532 /* MPC8560 */
7533 POWERPC_DEF_SVR("MPC8560",
7534 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
7535 /* MPC8560 v1.0 */
7536 POWERPC_DEF_SVR("MPC8560_v10",
7537 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
7538 /* MPC8560 v2.0 */
7539 POWERPC_DEF_SVR("MPC8560_v20",
7540 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
7541 /* MPC8560 v2.1 */
7542 POWERPC_DEF_SVR("MPC8560_v21",
7543 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
7544 /* MPC8567 */
7545 POWERPC_DEF_SVR("MPC8567",
7546 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
7547 /* MPC8567E */
7548 POWERPC_DEF_SVR("MPC8567E",
7549 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
7550 /* MPC8568 */
7551 POWERPC_DEF_SVR("MPC8568",
7552 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
7553 /* MPC8568E */
7554 POWERPC_DEF_SVR("MPC8568E",
7555 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
7556 /* MPC8572 */
7557 POWERPC_DEF_SVR("MPC8572",
7558 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
7559 /* MPC8572E */
7560 POWERPC_DEF_SVR("MPC8572E",
7561 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
7562 /* e600 family */
7563 /* PowerPC e600 core */
7564 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
7565 /* PowerPC e600 microcontrollers */
7566#if defined (TODO)
7567 /* MPC8610 */
7568 POWERPC_DEF_SVR("MPC8610",
7569 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
7570#endif
7571 /* MPC8641 */
7572 POWERPC_DEF_SVR("MPC8641",
7573 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
7574 /* MPC8641D */
7575 POWERPC_DEF_SVR("MPC8641D",
7576 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 7577 /* 32 bits "classic" PowerPC */
7578 /* PowerPC 6xx family */
7579 /* PowerPC 601 */
80d11f44 7580 POWERPC_DEF("601", CPU_POWERPC_601, 601),
c3e36823 7581 /* PowerPC 601v0 */
082c6681 7582 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 7583 /* PowerPC 601v1 */
082c6681
JM		 7584 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
7585 /* PowerPC 601v */
7586 POWERPC_DEF("601v", CPU_POWERPC_601, 601v),
a750fc0b 7587 /* PowerPC 601v2 */
082c6681 7588 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 7589 /* PowerPC 602 */
80d11f44 7590 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 7591 /* PowerPC 603 */
80d11f44 7592 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 7593 /* Code name for PowerPC 603 */
80d11f44 7594 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 7595 /* PowerPC 603e (aka PID6) */
80d11f44 7596 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 7597 /* Code name for PowerPC 603e */
80d11f44 7598 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 7599 /* PowerPC 603e v1.1 */
80d11f44 7600 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 7601 /* PowerPC 603e v1.2 */
80d11f44 7602 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 7603 /* PowerPC 603e v1.3 */
80d11f44 7604 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 7605 /* PowerPC 603e v1.4 */
80d11f44 7606 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 7607 /* PowerPC 603e v2.2 */
80d11f44 7608 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 7609 /* PowerPC 603e v3 */
80d11f44 7610 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 7611 /* PowerPC 603e v4 */
80d11f44 7612 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 7613 /* PowerPC 603e v4.1 */
80d11f44 7614 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 7615 /* PowerPC 603e (aka PID7) */
80d11f44 7616 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 7617 /* PowerPC 603e7t */
80d11f44 7618 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 7619 /* PowerPC 603e7v */
80d11f44 7620 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 7621 /* Code name for PowerPC 603ev */
80d11f44 7622 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 7623 /* PowerPC 603e7v1 */
80d11f44 7624 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 7625 /* PowerPC 603e7v2 */
80d11f44 7626 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 7627 /* PowerPC 603p (aka PID7v) */
7628 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
7629 /* PowerPC 603r (aka PID7t) */
80d11f44 7630 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 7631 /* Code name for PowerPC 603r */
80d11f44 7632 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 7633 /* PowerPC 604 */
80d11f44 7634 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 7635 /* PowerPC 604e (aka PID9) */
7636 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
7637 /* Code name for PowerPC 604e */
7638 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 7639 /* PowerPC 604e v1.0 */
082c6681 7640 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 7641 /* PowerPC 604e v2.2 */
082c6681 7642 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 7643 /* PowerPC 604e v2.4 */
082c6681
JM		 7644 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
7645 /* PowerPC 604r (aka PIDA) */
7646 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
7647 /* Code name for PowerPC 604r */
7648 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 7649#if defined(TODO)
7650 /* PowerPC 604ev */
082c6681 7651 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 7652#endif
7653 /* PowerPC 7xx family */
7654 /* Generic PowerPC 740 (G3) */
80d11f44 7655 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
082c6681
JM		 7656 /* Code name for PowerPC 740 */
7657 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
a750fc0b 7658 /* Generic PowerPC 750 (G3) */
80d11f44 7659 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
082c6681
JM		 7660 /* Code name for PowerPC 750 */
7661 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 7x0),
a750fc0b 7662 /* PowerPC 740/750 is also known as G3 */
80d11f44 7663 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
a750fc0b 7664 /* PowerPC 740 v2.0 (G3) */
80d11f44 7665 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0),
a750fc0b 7666 /* PowerPC 750 v2.0 (G3) */
80d11f44 7667 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0),
a750fc0b 7668 /* PowerPC 740 v2.1 (G3) */
80d11f44 7669 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0),
a750fc0b 7670 /* PowerPC 750 v2.1 (G3) */
80d11f44 7671 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0),
a750fc0b 7672 /* PowerPC 740 v2.2 (G3) */
80d11f44 7673 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0),
a750fc0b 7674 /* PowerPC 750 v2.2 (G3) */
80d11f44 7675 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0),
a750fc0b 7676 /* PowerPC 740 v3.0 (G3) */
80d11f44 7677 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0),
a750fc0b 7678 /* PowerPC 750 v3.0 (G3) */
80d11f44 7679 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0),
a750fc0b 7680 /* PowerPC 740 v3.1 (G3) */
80d11f44 7681 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0),
a750fc0b 7682 /* PowerPC 750 v3.1 (G3) */
80d11f44 7683 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0),
a750fc0b 7684 /* PowerPC 740E (G3) */
80d11f44 7685 POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
a750fc0b 7686 /* PowerPC 740P (G3) */
80d11f44 7687 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7688 /* PowerPC 750P (G3) */
80d11f44 7689 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7690 /* Code name for PowerPC 740P/750P (G3) */
80d11f44 7691 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7692 /* PowerPC 750CL (G3 embedded) */
80d11f44 7693 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
a750fc0b 7694 /* PowerPC 750CX (G3 embedded) */
80d11f44 7695 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
a750fc0b 7696 /* PowerPC 750CX v2.1 (G3 embedded) */
80d11f44 7697 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0),
a750fc0b 7698 /* PowerPC 750CX v2.2 (G3 embedded) */
80d11f44 7699 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0),
a750fc0b 7700 /* PowerPC 750CXe (G3 embedded) */
80d11f44 7701 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
a750fc0b 7702 /* PowerPC 750CXe v2.1 (G3 embedded) */
082c6681 7703 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 7x0),
a750fc0b 7704 /* PowerPC 750CXe v2.2 (G3 embedded) */
082c6681 7705 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 7x0),
a750fc0b 7706 /* PowerPC 750CXe v2.3 (G3 embedded) */
082c6681 7707 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 7x0),
a750fc0b 7708 /* PowerPC 750CXe v2.4 (G3 embedded) */
082c6681 7709 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 7x0),
a750fc0b 7710 /* PowerPC 750CXe v2.4b (G3 embedded) */
082c6681 7711 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 7x0),
a750fc0b 7712 /* PowerPC 750CXe v3.1 (G3 embedded) */
082c6681 7713 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 7x0),
a750fc0b 7714 /* PowerPC 750CXe v3.1b (G3 embedded) */
80d11f44 7715 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
a750fc0b 7716 /* PowerPC 750CXr (G3 embedded) */
80d11f44 7717 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
a750fc0b 7718 /* PowerPC 750E (G3) */
80d11f44 7719 POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
a750fc0b 7720 /* PowerPC 750FL (G3 embedded) */
80d11f44 7721 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 7722 /* PowerPC 750FX (G3 embedded) */
80d11f44 7723 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 7724 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 7725 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 7726 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 7727 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 7728 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 7729 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 7730 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 7731 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 7732 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 7733 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 7734 /* PowerPC 750GL (G3 embedded) */
80d11f44 7735 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
a750fc0b 7736 /* PowerPC 750GX (G3 embedded) */
80d11f44 7737 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
a750fc0b 7738 /* PowerPC 750GX v1.0 (G3 embedded) */
80d11f44 7739 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx),
a750fc0b 7740 /* PowerPC 750GX v1.1 (G3 embedded) */
80d11f44 7741 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx),
a750fc0b 7742 /* PowerPC 750GX v1.2 (G3 embedded) */
80d11f44 7743 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx),
a750fc0b 7744 /* PowerPC 750L (G3 embedded) */
80d11f44 7745 POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
a750fc0b 7746 /* Code name for PowerPC 750L (G3 embedded) */
80d11f44 7747 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
a750fc0b 7748 /* PowerPC 750L v2.2 (G3 embedded) */
80d11f44 7749 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0),
a750fc0b 7750 /* PowerPC 750L v3.0 (G3 embedded) */
80d11f44 7751 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0),
a750fc0b 7752 /* PowerPC 750L v3.2 (G3 embedded) */
80d11f44 7753 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0),
a750fc0b 7754 /* Generic PowerPC 745 */
80d11f44 7755 POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
a750fc0b 7756 /* Generic PowerPC 755 */
80d11f44 7757 POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
a750fc0b 7758 /* Code name for PowerPC 745/755 */
80d11f44 7759 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
a750fc0b 7760 /* PowerPC 745 v1.0 */
80d11f44 7761 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5),
a750fc0b 7762 /* PowerPC 755 v1.0 */
80d11f44 7763 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5),
a750fc0b 7764 /* PowerPC 745 v1.1 */
80d11f44 7765 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5),
a750fc0b 7766 /* PowerPC 755 v1.1 */
80d11f44 7767 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5),
a750fc0b 7768 /* PowerPC 745 v2.0 */
80d11f44 7769 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5),
a750fc0b 7770 /* PowerPC 755 v2.0 */
80d11f44 7771 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5),
a750fc0b 7772 /* PowerPC 745 v2.1 */
80d11f44 7773 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5),
a750fc0b 7774 /* PowerPC 755 v2.1 */
80d11f44 7775 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5),
a750fc0b 7776 /* PowerPC 745 v2.2 */
80d11f44 7777 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5),
a750fc0b 7778 /* PowerPC 755 v2.2 */
80d11f44 7779 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5),
a750fc0b 7780 /* PowerPC 745 v2.3 */
80d11f44 7781 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5),
a750fc0b 7782 /* PowerPC 755 v2.3 */
80d11f44 7783 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5),
a750fc0b 7784 /* PowerPC 745 v2.4 */
80d11f44 7785 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5),
a750fc0b 7786 /* PowerPC 755 v2.4 */
80d11f44 7787 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5),
a750fc0b 7788 /* PowerPC 745 v2.5 */
80d11f44 7789 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5),
a750fc0b 7790 /* PowerPC 755 v2.5 */
80d11f44 7791 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5),
a750fc0b 7792 /* PowerPC 745 v2.6 */
80d11f44 7793 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5),
a750fc0b 7794 /* PowerPC 755 v2.6 */
80d11f44 7795 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5),
a750fc0b 7796 /* PowerPC 745 v2.7 */
80d11f44 7797 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5),
a750fc0b 7798 /* PowerPC 755 v2.7 */
80d11f44 7799 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5),
a750fc0b 7800 /* PowerPC 745 v2.8 */
80d11f44 7801 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5),
a750fc0b 7802 /* PowerPC 755 v2.8 */
80d11f44 7803 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5),
a750fc0b
JM		 7804#if defined (TODO)
7805 /* PowerPC 745P (G3) */
80d11f44 7806 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
a750fc0b 7807 /* PowerPC 755P (G3) */
80d11f44 7808 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
a750fc0b
JM		 7809#endif
7810 /* PowerPC 74xx family */
7811 /* PowerPC 7400 (G4) */
80d11f44 7812 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 7813 /* Code name for PowerPC 7400 */
80d11f44 7814 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 7815 /* PowerPC 74xx is also well known as G4 */
80d11f44 7816 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 7817 /* PowerPC 7400 v1.0 (G4) */
80d11f44 7818 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 7819 /* PowerPC 7400 v1.1 (G4) */
80d11f44 7820 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 7821 /* PowerPC 7400 v2.0 (G4) */
80d11f44 7822 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
a750fc0b 7823 /* PowerPC 7400 v2.2 (G4) */
80d11f44 7824 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 7825 /* PowerPC 7400 v2.6 (G4) */
80d11f44 7826 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 7827 /* PowerPC 7400 v2.7 (G4) */
80d11f44 7828 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 7829 /* PowerPC 7400 v2.8 (G4) */
80d11f44 7830 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 7831 /* PowerPC 7400 v2.9 (G4) */
80d11f44 7832 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 7833 /* PowerPC 7410 (G4) */
80d11f44 7834 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 7835 /* Code name for PowerPC 7410 */
80d11f44 7836 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 7837 /* PowerPC 7410 v1.0 (G4) */
80d11f44 7838 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 7839 /* PowerPC 7410 v1.1 (G4) */
80d11f44 7840 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 7841 /* PowerPC 7410 v1.2 (G4) */
80d11f44 7842 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 7843 /* PowerPC 7410 v1.3 (G4) */
80d11f44 7844 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 7845 /* PowerPC 7410 v1.4 (G4) */
80d11f44 7846 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 7847 /* PowerPC 7448 (G4) */
80d11f44 7848 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 7849 /* PowerPC 7448 v1.0 (G4) */
80d11f44 7850 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 7851 /* PowerPC 7448 v1.1 (G4) */
80d11f44 7852 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 7853 /* PowerPC 7448 v2.0 (G4) */
80d11f44 7854 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 7855 /* PowerPC 7448 v2.1 (G4) */
80d11f44 7856 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 7857 /* PowerPC 7450 (G4) */
80d11f44 7858 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 7859 /* Code name for PowerPC 7450 */
80d11f44 7860 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 7861 /* PowerPC 7450 v1.0 (G4) */
80d11f44 7862 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 7863 /* PowerPC 7450 v1.1 (G4) */
80d11f44 7864 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 7865 /* PowerPC 7450 v1.2 (G4) */
80d11f44 7866 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 7867 /* PowerPC 7450 v2.0 (G4) */
80d11f44 7868 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 7869 /* PowerPC 7450 v2.1 (G4) */
80d11f44 7870 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 7871 /* PowerPC 7441 (G4) */
80d11f44 7872 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 7873 /* PowerPC 7451 (G4) */
80d11f44 7874 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
a750fc0b 7875 /* PowerPC 7441g (G4) */
80d11f44 7876 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
a750fc0b 7877 /* PowerPC 7451g (G4) */
80d11f44 7878 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
a750fc0b 7879 /* PowerPC 7445 (G4) */
80d11f44 7880 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 7881 /* PowerPC 7455 (G4) */
80d11f44 7882 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 7883 /* Code name for PowerPC 7445/7455 */
80d11f44 7884 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 7885 /* PowerPC 7445 v1.0 (G4) */
80d11f44 7886 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 7887 /* PowerPC 7455 v1.0 (G4) */
80d11f44 7888 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 7889 /* PowerPC 7445 v2.1 (G4) */
80d11f44 7890 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 7891 /* PowerPC 7455 v2.1 (G4) */
80d11f44 7892 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 7893 /* PowerPC 7445 v3.2 (G4) */
80d11f44 7894 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 7895 /* PowerPC 7455 v3.2 (G4) */
80d11f44 7896 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 7897 /* PowerPC 7445 v3.3 (G4) */
80d11f44 7898 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 7899 /* PowerPC 7455 v3.3 (G4) */
80d11f44 7900 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 7901 /* PowerPC 7445 v3.4 (G4) */
80d11f44 7902 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 7903 /* PowerPC 7455 v3.4 (G4) */
80d11f44 7904 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 7905 /* PowerPC 7447 (G4) */
80d11f44 7906 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 7907 /* PowerPC 7457 (G4) */
80d11f44 7908 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 7909 /* Code name for PowerPC 7447/7457 */
80d11f44 7910 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 7911 /* PowerPC 7447 v1.0 (G4) */
80d11f44 7912 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 7913 /* PowerPC 7457 v1.0 (G4) */
80d11f44 7914 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 7915 /* PowerPC 7447 v1.1 (G4) */
80d11f44 7916 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 7917 /* PowerPC 7457 v1.1 (G4) */
80d11f44 7918 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 7919 /* PowerPC 7447 v1.2 (G4) */
80d11f44 7920 POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
a750fc0b 7921 /* PowerPC 7457 v1.2 (G4) */
80d11f44 7922 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 7923 /* PowerPC 7447A (G4) */
7924 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
7925 /* PowerPC 7457A (G4) */
7926 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
7927 /* PowerPC 7447A v1.0 (G4) */
7928 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
7929 /* PowerPC 7457A v1.0 (G4) */
7930 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
7931 /* Code name for PowerPC 7447A/7457A */
7932 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
7933 /* PowerPC 7447A v1.1 (G4) */
7934 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
7935 /* PowerPC 7457A v1.1 (G4) */
7936 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
7937 /* PowerPC 7447A v1.2 (G4) */
7938 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
7939 /* PowerPC 7457A v1.2 (G4) */
7940 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 7941 /* 64 bits PowerPC */
7942#if defined (TARGET_PPC64)
a750fc0b 7943 /* PowerPC 620 */
80d11f44 7944 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 7945 /* Code name for PowerPC 620 */
7946 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 7947#if defined (TODO)
a750fc0b 7948 /* PowerPC 630 (POWER3) */
80d11f44
JM		 7949 POWERPC_DEF("630", CPU_POWERPC_630, 630),
7950 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 7951 /* Code names for POWER3 */
7952 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
7953 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 7954#endif
3a607854 7955#if defined (TODO)
a750fc0b 7956 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 7957 POWERPC_DEF("631", CPU_POWERPC_631, 631),
7958 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 7959#endif
7960#if defined (TODO)
a750fc0b 7961 /* POWER4 */
80d11f44 7962 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 7963#endif
3a607854 7964#if defined (TODO)
a750fc0b 7965 /* POWER4p */
80d11f44 7966 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 7967#endif
2662a059 7968#if defined (TODO)
a750fc0b 7969 /* POWER5 */
80d11f44 7970 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 7971 /* POWER5GR */
80d11f44 7972 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 7973#endif
3a607854 7974#if defined (TODO)
a750fc0b 7975 /* POWER5+ */
80d11f44 7976 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 7977 /* POWER5GS */
80d11f44 7978 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 7979#endif
2662a059 7980#if defined (TODO)
a750fc0b 7981 /* POWER6 */
80d11f44 7982 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 7983 /* POWER6 running in POWER5 mode */
80d11f44 7984 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 7985 /* POWER6A */
80d11f44 7986 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 7987#endif
a750fc0b 7988 /* PowerPC 970 */
80d11f44 7989 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 7990 /* PowerPC 970FX (G5) */
80d11f44 7991 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 7992 /* PowerPC 970FX v1.0 (G5) */
80d11f44 7993 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 7994 /* PowerPC 970FX v2.0 (G5) */
80d11f44 7995 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 7996 /* PowerPC 970FX v2.1 (G5) */
80d11f44 7997 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 7998 /* PowerPC 970FX v3.0 (G5) */
80d11f44 7999 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 8000 /* PowerPC 970FX v3.1 (G5) */
80d11f44 8001 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 8002 /* PowerPC 970GX (G5) */
80d11f44 8003 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 8004 /* PowerPC 970MP */
80d11f44 8005 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 8006 /* PowerPC 970MP v1.0 */
80d11f44 8007 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 8008 /* PowerPC 970MP v1.1 */
80d11f44 8009 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 8010#if defined (TODO)
a750fc0b 8011 /* PowerPC Cell */
80d11f44 8012 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 8013#endif
8014#if defined (TODO)
a750fc0b 8015 /* PowerPC Cell v1.0 */
80d11f44 8016 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 8017#endif
8018#if defined (TODO)
a750fc0b 8019 /* PowerPC Cell v2.0 */
80d11f44 8020 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 8021#endif
8022#if defined (TODO)
a750fc0b 8023 /* PowerPC Cell v3.0 */
80d11f44 8024 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 8025#endif
3a607854 8026#if defined (TODO)
a750fc0b 8027 /* PowerPC Cell v3.1 */
80d11f44 8028 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 8029#endif
8030#if defined (TODO)
a750fc0b 8031 /* PowerPC Cell v3.2 */
80d11f44 8032 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 8033#endif
8034#if defined (TODO)
a750fc0b
JM		 8035 /* RS64 (Apache/A35) */
8036 /* This one seems to support the whole POWER2 instruction set
8037 * and the PowerPC 64 one.
8038 */
8039 /* What about A10 & A30 ? */
80d11f44
JM		 8040 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8041 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8042 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 8043#endif
8044#if defined (TODO)
a750fc0b 8045 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 8046 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8047 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8048 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 8049#endif
8050#if defined (TODO)
a750fc0b 8051 /* RS64-III (Pulsar) */
80d11f44
JM		 8052 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8053 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 8054#endif
8055#if defined (TODO)
a750fc0b 8056 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 8057 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8058 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8059 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8060 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 8061#endif
a750fc0b
JM		 8062#endif /* defined (TARGET_PPC64) */
8063 /* POWER */
3fc6c082 8064#if defined (TODO)
a750fc0b 8065 /* Original POWER */
80d11f44
JM		 8066 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8067 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8068 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8069 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8070 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 8071#endif
8072#if defined (TODO)
a750fc0b 8073 /* POWER2 */
80d11f44
JM		 8074 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8075 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8076 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 8077#endif
8078 /* PA semi cores */
8079#if defined (TODO)
8080 /* PA PA6T */
80d11f44 8081 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 8082#endif
8083 /* Generic PowerPCs */
8084#if defined (TARGET_PPC64)
80d11f44 8085 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 8086#endif
80d11f44
JM		 8087 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8088 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 8089 /* Fallback */
80d11f44 8090 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 8091};
8092
8093/*****************************************************************************/
8094/* Generic CPU instanciation routine */
aaed909a 8095static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8096{
8097#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 8098 int i;
8099
a750fc0b 8100 env->irq_inputs = NULL;
e1833e1f
JM		 8101 /* Set all exception vectors to an invalid address */
8102 for (i = 0; i < POWERPC_EXCP_NB; i++)
8103 env->excp_vectors[i] = (target_ulong)(-1ULL);
8104 env->excp_prefix = 0x00000000;
8105 env->ivor_mask = 0x00000000;
8106 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 8107 /* Default MMU definitions */
8108 env->nb_BATs = 0;
8109 env->nb_tlb = 0;
8110 env->nb_ways = 0;
f2e63a42 8111#endif
a750fc0b
JM		 8112 /* Register SPR common to all PowerPC implementations */
8113 gen_spr_generic(env);
8114 spr_register(env, SPR_PVR, "PVR",
8115 SPR_NOACCESS, SPR_NOACCESS,
8116 &spr_read_generic, SPR_NOACCESS,
8117 def->pvr);
80d11f44
JM		 8118 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8119 if (def->svr != POWERPC_SVR_NONE) {
8120 if (def->svr & POWERPC_SVR_E500) {
8121 spr_register(env, SPR_E500_SVR, "SVR",
8122 SPR_NOACCESS, SPR_NOACCESS,
8123 &spr_read_generic, SPR_NOACCESS,
8124 def->svr & ~POWERPC_SVR_E500);
8125 } else {
8126 spr_register(env, SPR_SVR, "SVR",
8127 SPR_NOACCESS, SPR_NOACCESS,
8128 &spr_read_generic, SPR_NOACCESS,
8129 def->svr);
8130 }
8131 }
a750fc0b
JM		 8132 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8133 (*def->init_proc)(env);
25ba3a68
JM		 8134 /* MSR bits & flags consistency checks */
8135 if (env->msr_mask & (1 << 25)) {
8136 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8137 case POWERPC_FLAG_SPE:
8138 case POWERPC_FLAG_VRE:
8139 break;
8140 default:
8141 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8142 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8143 exit(1);
8144 }
8145 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8146 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8147 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8148 exit(1);
8149 }
8150 if (env->msr_mask & (1 << 17)) {
8151 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8152 case POWERPC_FLAG_TGPR:
8153 case POWERPC_FLAG_CE:
8154 break;
8155 default:
8156 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8157 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8158 exit(1);
8159 }
8160 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8161 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8162 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8163 exit(1);
8164 }
8165 if (env->msr_mask & (1 << 10)) {
8166 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8167 POWERPC_FLAG_UBLE)) {
8168 case POWERPC_FLAG_SE:
8169 case POWERPC_FLAG_DWE:
8170 case POWERPC_FLAG_UBLE:
8171 break;
8172 default:
8173 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8174 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8175 "POWERPC_FLAG_UBLE\n");
8176 exit(1);
8177 }
8178 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8179 POWERPC_FLAG_UBLE)) {
8180 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8181 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8182 "POWERPC_FLAG_UBLE\n");
8183 exit(1);
8184 }
8185 if (env->msr_mask & (1 << 9)) {
8186 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8187 case POWERPC_FLAG_BE:
8188 case POWERPC_FLAG_DE:
8189 break;
8190 default:
8191 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8192 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8193 exit(1);
8194 }
8195 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8196 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8197 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8198 exit(1);
8199 }
8200 if (env->msr_mask & (1 << 2)) {
8201 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8202 case POWERPC_FLAG_PX:
8203 case POWERPC_FLAG_PMM:
8204 break;
8205 default:
8206 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8207 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8208 exit(1);
8209 }
8210 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8211 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8212 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8213 exit(1);
8214 }
4018bae9
JM		 8215 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8216 fprintf(stderr, "PowerPC flags inconsistency\n"
8217 "Should define the time-base and decrementer clock source\n");
8218 exit(1);
8219 }
a750fc0b 8220 /* Allocate TLBs buffer when needed */
f2e63a42 8221#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8222 if (env->nb_tlb != 0) {
8223 int nb_tlb = env->nb_tlb;
8224 if (env->id_tlbs != 0)
8225 nb_tlb *= 2;
8226 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8227 /* Pre-compute some useful values */
8228 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8229 }
a750fc0b
JM		 8230 if (env->irq_inputs == NULL) {
8231 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8232 " Attempt Qemu to crash very soon !\n");
8233 }
8234#endif
2f462816
JM		 8235 if (env->check_pow == NULL) {
8236 fprintf(stderr, "WARNING: no power management check handler "
8237 "registered.\n"
8238 " Attempt Qemu to crash very soon !\n");
8239 }
a750fc0b
JM		 8240}
8241
8242#if defined(PPC_DUMP_CPU)
8243static void dump_ppc_sprs (CPUPPCState *env)
8244{
8245 ppc_spr_t *spr;
8246#if !defined(CONFIG_USER_ONLY)
8247 uint32_t sr, sw;
8248#endif
8249 uint32_t ur, uw;
8250 int i, j, n;
8251
8252 printf("Special purpose registers:\n");
8253 for (i = 0; i < 32; i++) {
8254 for (j = 0; j < 32; j++) {
8255 n = (i << 5) | j;
8256 spr = &env->spr_cb[n];
8257 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8258 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8259#if !defined(CONFIG_USER_ONLY)
8260 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8261 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8262 if (sw || sr || uw || ur) {
8263 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8264 (i << 5) | j, (i << 5) | j, spr->name,
8265 sw ? 'w' : '-', sr ? 'r' : '-',
8266 uw ? 'w' : '-', ur ? 'r' : '-');
8267 }
8268#else
8269 if (uw || ur) {
8270 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8271 (i << 5) | j, (i << 5) | j, spr->name,
8272 uw ? 'w' : '-', ur ? 'r' : '-');
8273 }
8274#endif
8275 }
8276 }
8277 fflush(stdout);
8278 fflush(stderr);
8279}
8280#endif
8281
8282/*****************************************************************************/
8283#include <stdlib.h>
8284#include <string.h>
8285
8286int fflush (FILE *stream);
8287
8288/* Opcode types */
8289enum {
8290 PPC_DIRECT = 0, /* Opcode routine */
8291 PPC_INDIRECT = 1, /* Indirect opcode table */
8292};
8293
8294static inline int is_indirect_opcode (void *handler)
8295{
8296 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
8297}
8298
8299static inline opc_handler_t **ind_table(void *handler)
8300{
8301 return (opc_handler_t **)((unsigned long)handler & ~3);
8302}
8303
8304/* Instruction table creation */
8305/* Opcodes tables creation */
8306static void fill_new_table (opc_handler_t **table, int len)
8307{
8308 int i;
8309
8310 for (i = 0; i < len; i++)
8311 table[i] = &invalid_handler;
8312}
8313
8314static int create_new_table (opc_handler_t **table, unsigned char idx)
8315{
8316 opc_handler_t **tmp;
8317
8318 tmp = malloc(0x20 * sizeof(opc_handler_t));
8319 if (tmp == NULL)
8320 return -1;
8321 fill_new_table(tmp, 0x20);
8322 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
8323
8324 return 0;
8325}
8326
8327static int insert_in_table (opc_handler_t **table, unsigned char idx,
8328 opc_handler_t *handler)
8329{
8330 if (table[idx] != &invalid_handler)
8331 return -1;
8332 table[idx] = handler;
8333
8334 return 0;
8335}
8336
8337static int register_direct_insn (opc_handler_t **ppc_opcodes,
8338 unsigned char idx, opc_handler_t *handler)
8339{
8340 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8341 printf("*** ERROR: opcode %02x already assigned in main "
8342 "opcode table\n", idx);
4c1b1bfe
JM		 8343#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8344 printf(" Registered handler '%s' - new handler '%s'\n",
8345 ppc_opcodes[idx]->oname, handler->oname);
8346#endif
a750fc0b
JM		 8347 return -1;
8348 }
8349
8350 return 0;
8351}
8352
8353static int register_ind_in_table (opc_handler_t **table,
8354 unsigned char idx1, unsigned char idx2,
8355 opc_handler_t *handler)
8356{
8357 if (table[idx1] == &invalid_handler) {
8358 if (create_new_table(table, idx1) < 0) {
8359 printf("*** ERROR: unable to create indirect table "
8360 "idx=%02x\n", idx1);
8361 return -1;
8362 }
8363 } else {
8364 if (!is_indirect_opcode(table[idx1])) {
8365 printf("*** ERROR: idx %02x already assigned to a direct "
8366 "opcode\n", idx1);
4c1b1bfe
JM		 8367#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8368 printf(" Registered handler '%s' - new handler '%s'\n",
8369 ind_table(table[idx1])[idx2]->oname, handler->oname);
8370#endif
a750fc0b
JM		 8371 return -1;
8372 }
3a607854 8373 }
a750fc0b
JM		 8374 if (handler != NULL &&
8375 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8376 printf("*** ERROR: opcode %02x already assigned in "
8377 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 8378#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8379 printf(" Registered handler '%s' - new handler '%s'\n",
8380 ind_table(table[idx1])[idx2]->oname, handler->oname);
8381#endif
a750fc0b 8382 return -1;
3a607854 8383 }
a750fc0b
JM		 8384
8385 return 0;
8386}
8387
8388static int register_ind_insn (opc_handler_t **ppc_opcodes,
8389 unsigned char idx1, unsigned char idx2,
8390 opc_handler_t *handler)
8391{
8392 int ret;
8393
8394 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8395
8396 return ret;
8397}
8398
8399static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8400 unsigned char idx1, unsigned char idx2,
8401 unsigned char idx3, opc_handler_t *handler)
8402{
8403 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8404 printf("*** ERROR: unable to join indirect table idx "
8405 "[%02x-%02x]\n", idx1, idx2);
8406 return -1;
8407 }
8408 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8409 handler) < 0) {
8410 printf("*** ERROR: unable to insert opcode "
8411 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8412 return -1;
8413 }
8414
8415 return 0;
8416}
8417
8418static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8419{
8420 if (insn->opc2 != 0xFF) {
8421 if (insn->opc3 != 0xFF) {
8422 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8423 insn->opc3, &insn->handler) < 0)
8424 return -1;
8425 } else {
8426 if (register_ind_insn(ppc_opcodes, insn->opc1,
8427 insn->opc2, &insn->handler) < 0)
8428 return -1;
8429 }
8430 } else {
8431 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8432 return -1;
8433 }
8434
8435 return 0;
8436}
8437
8438static int test_opcode_table (opc_handler_t **table, int len)
8439{
8440 int i, count, tmp;
8441
8442 for (i = 0, count = 0; i < len; i++) {
8443 /* Consistency fixup */
8444 if (table[i] == NULL)
8445 table[i] = &invalid_handler;
8446 if (table[i] != &invalid_handler) {
8447 if (is_indirect_opcode(table[i])) {
8448 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8449 if (tmp == 0) {
8450 free(table[i]);
8451 table[i] = &invalid_handler;
8452 } else {
8453 count++;
8454 }
8455 } else {
8456 count++;
8457 }
8458 }
8459 }
8460
8461 return count;
8462}
8463
8464static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8465{
8466 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8467 printf("*** WARNING: no opcode defined !\n");
8468}
8469
8470/*****************************************************************************/
aaed909a 8471static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8472{
8473 opcode_t *opc, *start, *end;
8474
8475 fill_new_table(env->opcodes, 0x40);
8476 if (&opc_start < &opc_end) {
8477 start = &opc_start;
8478 end = &opc_end;
8479 } else {
8480 start = &opc_end;
8481 end = &opc_start;
8482 }
8483 for (opc = start + 1; opc != end; opc++) {
8484 if ((opc->handler.type & def->insns_flags) != 0) {
8485 if (register_insn(env->opcodes, opc) < 0) {
8486 printf("*** ERROR initializing PowerPC instruction "
8487 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
8488 opc->opc3);
8489 return -1;
8490 }
8491 }
8492 }
8493 fix_opcode_tables(env->opcodes);
8494 fflush(stdout);
8495 fflush(stderr);
8496
8497 return 0;
8498}
8499
8500#if defined(PPC_DUMP_CPU)
25ba3a68 8501static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 8502{
8503 opc_handler_t **table, *handler;
4c1b1bfe 8504 const unsigned char *p, *q;
a750fc0b
JM		 8505 uint8_t opc1, opc2, opc3;
8506
8507 printf("Instructions set:\n");
8508 /* opc1 is 6 bits long */
8509 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8510 table = env->opcodes;
8511 handler = table[opc1];
8512 if (is_indirect_opcode(handler)) {
8513 /* opc2 is 5 bits long */
8514 for (opc2 = 0; opc2 < 0x20; opc2++) {
8515 table = env->opcodes;
8516 handler = env->opcodes[opc1];
8517 table = ind_table(handler);
8518 handler = table[opc2];
8519 if (is_indirect_opcode(handler)) {
8520 table = ind_table(handler);
8521 /* opc3 is 5 bits long */
8522 for (opc3 = 0; opc3 < 0x20; opc3++) {
8523 handler = table[opc3];
8524 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 8525 /* Special hack to properly dump SPE insns */
8526 p = strchr(handler->oname, '_');
8527 if (p == NULL) {
8528 printf("INSN: %02x %02x %02x (%02d %04d) : "
8529 "%s\n",
8530 opc1, opc2, opc3, opc1,
8531 (opc3 << 5) | opc2,
8532 handler->oname);
8533 } else {
8534 q = "speundef";
8535 if ((p - handler->oname) != strlen(q) ||
8536 memcmp(handler->oname, q, strlen(q)) != 0) {
8537 /* First instruction */
8538 printf("INSN: %02x %02x %02x (%02d %04d) : "
8539 "%.*s\n",
8540 opc1, opc2 << 1, opc3, opc1,
8541 (opc3 << 6) | (opc2 << 1),
8542 (int)(p - handler->oname),
8543 handler->oname);
8544 }
8545 if (strcmp(p + 1, q) != 0) {
8546 /* Second instruction */
8547 printf("INSN: %02x %02x %02x (%02d %04d) : "
8548 "%s\n",
8549 opc1, (opc2 << 1) | 1, opc3, opc1,
8550 (opc3 << 6) | (opc2 << 1) | 1,
8551 p + 1);
8552 }
8553 }
a750fc0b
JM		 8554 }
8555 }
8556 } else {
8557 if (handler->handler != &gen_invalid) {
8558 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8559 opc1, opc2, opc1, opc2, handler->oname);
8560 }
8561 }
8562 }
8563 } else {
8564 if (handler->handler != &gen_invalid) {
8565 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8566 opc1, opc1, handler->oname);
8567 }
8568 }
8569 }
8570}
3a607854 8571#endif
a750fc0b 8572
aaed909a 8573int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8574{
8575 env->msr_mask = def->msr_mask;
8576 env->mmu_model = def->mmu_model;
8577 env->excp_model = def->excp_model;
8578 env->bus_model = def->bus_model;
d26bfc9a 8579 env->flags = def->flags;
237c0af0 8580 env->bfd_mach = def->bfd_mach;
2f462816 8581 env->check_pow = def->check_pow;
a750fc0b
JM		 8582 if (create_ppc_opcodes(env, def) < 0)
8583 return -1;
8584 init_ppc_proc(env, def);
8585#if defined(PPC_DUMP_CPU)
3a607854 8586 {
a750fc0b
JM		 8587 const unsigned char *mmu_model, *excp_model, *bus_model;
8588 switch (env->mmu_model) {
8589 case POWERPC_MMU_32B:
8590 mmu_model = "PowerPC 32";
8591 break;
a750fc0b
JM		 8592 case POWERPC_MMU_SOFT_6xx:
8593 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8594 break;
8595 case POWERPC_MMU_SOFT_74xx:
8596 mmu_model = "PowerPC 74xx with software driven TLBs";
8597 break;
8598 case POWERPC_MMU_SOFT_4xx:
8599 mmu_model = "PowerPC 4xx with software driven TLBs";
8600 break;
8601 case POWERPC_MMU_SOFT_4xx_Z:
8602 mmu_model = "PowerPC 4xx with software driven TLBs "
8603 "and zones protections";
8604 break;
b4095fed
JM		 8605 case POWERPC_MMU_REAL:
8606 mmu_model = "PowerPC real mode only";
8607 break;
8608 case POWERPC_MMU_MPC8xx:
8609 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 8610 break;
8611 case POWERPC_MMU_BOOKE:
8612 mmu_model = "PowerPC BookE";
8613 break;
8614 case POWERPC_MMU_BOOKE_FSL:
8615 mmu_model = "PowerPC BookE FSL";
8616 break;
b4095fed
JM		 8617 case POWERPC_MMU_601:
8618 mmu_model = "PowerPC 601";
8619 break;
00af685f
JM		 8620#if defined (TARGET_PPC64)
8621 case POWERPC_MMU_64B:
8622 mmu_model = "PowerPC 64";
8623 break;
add78955
JM		 8624 case POWERPC_MMU_620:
8625 mmu_model = "PowerPC 620";
8626 break;
00af685f 8627#endif
a750fc0b
JM		 8628 default:
8629 mmu_model = "Unknown or invalid";
8630 break;
8631 }
8632 switch (env->excp_model) {
8633 case POWERPC_EXCP_STD:
8634 excp_model = "PowerPC";
8635 break;
8636 case POWERPC_EXCP_40x:
8637 excp_model = "PowerPC 40x";
8638 break;
8639 case POWERPC_EXCP_601:
8640 excp_model = "PowerPC 601";
8641 break;
8642 case POWERPC_EXCP_602:
8643 excp_model = "PowerPC 602";
8644 break;
8645 case POWERPC_EXCP_603:
8646 excp_model = "PowerPC 603";
8647 break;
8648 case POWERPC_EXCP_603E:
8649 excp_model = "PowerPC 603e";
8650 break;
8651 case POWERPC_EXCP_604:
8652 excp_model = "PowerPC 604";
8653 break;
8654 case POWERPC_EXCP_7x0:
8655 excp_model = "PowerPC 740/750";
8656 break;
8657 case POWERPC_EXCP_7x5:
8658 excp_model = "PowerPC 745/755";
8659 break;
8660 case POWERPC_EXCP_74xx:
8661 excp_model = "PowerPC 74xx";
8662 break;
a750fc0b
JM		 8663 case POWERPC_EXCP_BOOKE:
8664 excp_model = "PowerPC BookE";
8665 break;
00af685f
JM		 8666#if defined (TARGET_PPC64)
8667 case POWERPC_EXCP_970:
8668 excp_model = "PowerPC 970";
8669 break;
8670#endif
a750fc0b
JM		 8671 default:
8672 excp_model = "Unknown or invalid";
8673 break;
8674 }
8675 switch (env->bus_model) {
8676 case PPC_FLAGS_INPUT_6xx:
8677 bus_model = "PowerPC 6xx";
8678 break;
8679 case PPC_FLAGS_INPUT_BookE:
8680 bus_model = "PowerPC BookE";
8681 break;
8682 case PPC_FLAGS_INPUT_405:
8683 bus_model = "PowerPC 405";
8684 break;
a750fc0b
JM		 8685 case PPC_FLAGS_INPUT_401:
8686 bus_model = "PowerPC 401/403";
8687 break;
b4095fed
JM		 8688 case PPC_FLAGS_INPUT_RCPU:
8689 bus_model = "RCPU / MPC8xx";
8690 break;
00af685f
JM		 8691#if defined (TARGET_PPC64)
8692 case PPC_FLAGS_INPUT_970:
8693 bus_model = "PowerPC 970";
8694 break;
8695#endif
a750fc0b
JM		 8696 default:
8697 bus_model = "Unknown or invalid";
8698 break;
8699 }
8700 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8701 " MMU model : %s\n",
8702 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 8703#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8704 if (env->tlb != NULL) {
8705 printf(" %d %s TLB in %d ways\n",
8706 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8707 env->nb_ways);
8708 }
f2e63a42 8709#endif
a750fc0b
JM		 8710 printf(" Exceptions model : %s\n"
8711 " Bus model : %s\n",
8712 excp_model, bus_model);
25ba3a68
JM		 8713 printf(" MSR features :\n");
8714 if (env->flags & POWERPC_FLAG_SPE)
8715 printf(" signal processing engine enable"
8716 "\n");
8717 else if (env->flags & POWERPC_FLAG_VRE)
8718 printf(" vector processor enable\n");
8719 if (env->flags & POWERPC_FLAG_TGPR)
8720 printf(" temporary GPRs\n");
8721 else if (env->flags & POWERPC_FLAG_CE)
8722 printf(" critical input enable\n");
8723 if (env->flags & POWERPC_FLAG_SE)
8724 printf(" single-step trace mode\n");
8725 else if (env->flags & POWERPC_FLAG_DWE)
8726 printf(" debug wait enable\n");
8727 else if (env->flags & POWERPC_FLAG_UBLE)
8728 printf(" user BTB lock enable\n");
8729 if (env->flags & POWERPC_FLAG_BE)
8730 printf(" branch-step trace mode\n");
8731 else if (env->flags & POWERPC_FLAG_DE)
8732 printf(" debug interrupt enable\n");
8733 if (env->flags & POWERPC_FLAG_PX)
8734 printf(" inclusive protection\n");
8735 else if (env->flags & POWERPC_FLAG_PMM)
8736 printf(" performance monitor mark\n");
8737 if (env->flags == POWERPC_FLAG_NONE)
8738 printf(" none\n");
4018bae9
JM		 8739 printf(" Time-base/decrementer clock source: %s\n",
8740 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 8741 }
8742 dump_ppc_insns(env);
8743 dump_ppc_sprs(env);
8744 fflush(stdout);
3a607854 8745#endif
a750fc0b
JM		 8746
8747 return 0;
8748}
3fc6c082 8749
ee4e83ed 8750static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 8751{
ee4e83ed
JM		 8752 const ppc_def_t *ret;
8753 uint32_t pvr_rev;
8754 int i, best, match, best_match, max;
3fc6c082 8755
ee4e83ed 8756 ret = NULL;
068abdc8 8757 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
ee4e83ed
JM		 8758 best = -1;
8759 pvr_rev = pvr & 0xFFFF;
8760 /* We want all specified bits to match */
8761 best_match = 32 - ctz32(pvr_rev);
068abdc8 8762 for (i = 0; i < max; i++) {
ee4e83ed
JM		 8763 /* We check that the 16 higher bits are the same to ensure the CPU
8764 * model will be the choosen one.
8765 */
8766 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
8767 /* We want as much as possible of the low-level 16 bits
8768 * to be the same but we allow inexact matches.
8769 */
8770 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
8771 /* We check '>=' instead of '>' because the PPC_defs table
8772 * is ordered by increasing revision.
4c1b1bfe 8773 * Then, we will match the higher revision compatible
ee4e83ed
JM		 8774 * with the requested PVR
8775 */
8776 if (match >= best_match) {
8777 best = i;
8778 best_match = match;
8779 }
3fc6c082
FB		 8780 }
8781 }
ee4e83ed
JM		 8782 if (best != -1)
8783 ret = &ppc_defs[best];
8784
8785 return ret;
3fc6c082
FB		 8786}
8787
ee4e83ed 8788#include <ctype.h>
3fc6c082 8789
ee4e83ed
JM		 8790const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
8791{
8792 const ppc_def_t *ret;
8793 const unsigned char *p;
8794 int i, max, len;
8795
8796 /* Check if the given name is a PVR */
8797 len = strlen(name);
8798 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8799 p = name + 2;
8800 goto check_pvr;
8801 } else if (len == 8) {
8802 p = name;
8803 check_pvr:
8804 for (i = 0; i < 8; i++) {
8805 if (!isxdigit(*p++))
8806 break;
8807 }
8808 if (i == 8)
8809 return ppc_find_by_pvr(strtoul(name, NULL, 16));
8810 }
8811 ret = NULL;
068abdc8
JM		 8812 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
8813 for (i = 0; i < max; i++) {
ee4e83ed
JM		 8814 if (strcasecmp(name, ppc_defs[i].name) == 0) {
8815 ret = &ppc_defs[i];
8816 break;
3fc6c082
FB		 8817 }
8818 }
ee4e83ed
JM		 8819
8820 return ret;
3fc6c082
FB		 8821}
8822
8823void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
8824{
068abdc8 8825 int i, max;
3fc6c082 8826
068abdc8
JM		 8827 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
8828 for (i = 0; i < max; i++) {
a750fc0b
JM		 8829 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
8830 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 8831 }
8832}
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