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Merge mainstone.h header into mainstone.c
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 18 */
19
20/* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
237c0af0 25#include "dis-asm.h"
4e47ea67 26#include "gdbstub.h"
237c0af0 27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
80d11f44
JM		 30//#define PPC_DUMP_SPR_ACCESSES
31#if defined(CONFIG_USER_ONLY)
32#define TODO_USER_ONLY 1
33#endif
3fc6c082 34
c227f099 35struct ppc_def_t {
b55266b5 36 const char *name;
3fc6c082 37 uint32_t pvr;
80d11f44 38 uint32_t svr;
0487d6a8 39 uint64_t insns_flags;
3fc6c082 40 uint64_t msr_mask;
c227f099
AL		 41 powerpc_mmu_t mmu_model;
42 powerpc_excp_t excp_model;
43 powerpc_input_t bus_model;
d26bfc9a 44 uint32_t flags;
237c0af0 45 int bfd_mach;
a750fc0b 46 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 47 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 48};
49
e9df014c
JM		 50/* For user-mode emulation, we don't emulate any IRQ controller */
51#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 52#define PPC_IRQ_INIT_FN(name) \
53static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
54{ \
e9df014c
JM		 55}
56#else
a750fc0b 57#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 58void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
59#endif
a750fc0b 60
4e290a0b 61PPC_IRQ_INIT_FN(40x);
e9df014c 62PPC_IRQ_INIT_FN(6xx);
d0dfae6e 63PPC_IRQ_INIT_FN(970);
9fdc60bf 64PPC_IRQ_INIT_FN(e500);
e9df014c 65
3fc6c082
FB		 66/* Generic callbacks:
67 * do nothing but store/retrieve spr value
68 */
45d827d2 69static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 70{
45d827d2
AJ		 71 gen_load_spr(cpu_gpr[gprn], sprn);
72#ifdef PPC_DUMP_SPR_ACCESSES
73 {
74 TCGv t0 = tcg_const_i32(sprn);
75 gen_helper_load_dump_spr(t0);
76 tcg_temp_free_i32(t0);
77 }
78#endif
a496775f
JM		 79}
80
45d827d2 81static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 82{
45d827d2
AJ		 83 gen_store_spr(sprn, cpu_gpr[gprn]);
84#ifdef PPC_DUMP_SPR_ACCESSES
85 {
86 TCGv t0 = tcg_const_i32(sprn);
87 gen_helper_store_dump_spr(t0);
88 tcg_temp_free_i32(t0);
89 }
04f20795 90#endif
45d827d2 91}
a496775f
JM		 92
93#if !defined(CONFIG_USER_ONLY)
45d827d2 94static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 95{
45d827d2
AJ		 96 TCGv t0 = tcg_temp_new();
97 TCGv t1 = tcg_temp_new();
98 gen_load_spr(t0, sprn);
99 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
100 tcg_gen_and_tl(t0, t0, t1);
101 gen_store_spr(sprn, t0);
102 tcg_temp_free(t0);
103 tcg_temp_free(t1);
a496775f
JM		 104}
105#endif
106
76a66253 107/* SPR common to all PowerPC */
3fc6c082 108/* XER */
45d827d2 109static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 110{
45d827d2 111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 112}
113
45d827d2 114static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 115{
45d827d2 116 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 117}
118
119/* LR */
45d827d2 120static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 121{
45d827d2 122 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 123}
124
45d827d2 125static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 126{
45d827d2 127 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 128}
129
130/* CTR */
45d827d2 131static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 132{
45d827d2 133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 134}
135
45d827d2 136static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 137{
45d827d2 138 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 139}
140
141/* User read access to SPR */
142/* USPRx */
143/* UMMCRx */
144/* UPMCx */
145/* USIA */
146/* UDECR */
45d827d2 147static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 148{
45d827d2 149 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 150}
151
76a66253 152/* SPR common to all non-embedded PowerPC */
3fc6c082 153/* DECR */
76a66253 154#if !defined(CONFIG_USER_ONLY)
45d827d2 155static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 156{
45d827d2 157 gen_helper_load_decr(cpu_gpr[gprn]);
3fc6c082
FB		 158}
159
45d827d2 160static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 161{
45d827d2 162 gen_helper_store_decr(cpu_gpr[gprn]);
3fc6c082 163}
76a66253 164#endif
3fc6c082 165
76a66253 166/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 167/* Time base */
45d827d2 168static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 169{
45d827d2 170 gen_helper_load_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 171}
172
45d827d2 173static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 174{
45d827d2 175 gen_helper_load_tbu(cpu_gpr[gprn]);
3fc6c082
FB		 176}
177
a062e36c 178__attribute__ (( unused ))
45d827d2 179static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 180{
45d827d2 181 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 182}
183
184__attribute__ (( unused ))
45d827d2 185static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 186{
45d827d2 187 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 188}
189
76a66253 190#if !defined(CONFIG_USER_ONLY)
45d827d2 191static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 192{
45d827d2 193 gen_helper_store_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 194}
195
45d827d2 196static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 197{
45d827d2 198 gen_helper_store_tbu(cpu_gpr[gprn]);
3fc6c082 199}
a062e36c
JM		 200
201__attribute__ (( unused ))
45d827d2 202static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 203{
45d827d2 204 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 205}
206
207__attribute__ (( unused ))
45d827d2 208static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 209{
45d827d2 210 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 211}
76a66253 212#endif
3fc6c082 213
76a66253 214#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 215/* IBAT0U...IBAT0U */
216/* IBAT0L...IBAT7L */
45d827d2 217static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 218{
45d827d2 219 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 220}
221
45d827d2 222static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 223{
45d827d2 224 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 225}
226
45d827d2 227static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 228{
45d827d2
AJ		 229 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
230 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
231 tcg_temp_free_i32(t0);
3fc6c082
FB		 232}
233
45d827d2 234static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 235{
8daf1781 236 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
45d827d2
AJ		 237 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
238 tcg_temp_free_i32(t0);
3fc6c082
FB		 239}
240
45d827d2 241static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 242{
45d827d2
AJ		 243 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
244 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
245 tcg_temp_free_i32(t0);
3fc6c082
FB		 246}
247
45d827d2 248static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 249{
8daf1781 250 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
45d827d2
AJ		 251 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
252 tcg_temp_free_i32(t0);
3fc6c082
FB		 253}
254
255/* DBAT0U...DBAT7U */
256/* DBAT0L...DBAT7L */
45d827d2 257static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 258{
45d827d2 259 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 260}
261
45d827d2 262static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 263{
45d827d2 264 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 265}
266
45d827d2 267static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 268{
45d827d2
AJ		 269 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
270 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
271 tcg_temp_free_i32(t0);
3fc6c082
FB		 272}
273
45d827d2 274static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 275{
45d827d2
AJ		 276 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
277 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
278 tcg_temp_free_i32(t0);
3fc6c082
FB		 279}
280
45d827d2 281static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 282{
45d827d2
AJ		 283 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
284 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
285 tcg_temp_free_i32(t0);
3fc6c082
FB		 286}
287
45d827d2 288static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 289{
45d827d2
AJ		 290 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
291 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
292 tcg_temp_free_i32(t0);
3fc6c082
FB		 293}
294
295/* SDR1 */
45d827d2 296static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
3fc6c082 297{
45d827d2 298 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
3fc6c082
FB		 299}
300
45d827d2 301static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 302{
45d827d2 303 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 304}
305
76a66253
JM		 306/* 64 bits PowerPC specific SPRs */
307/* ASR */
578bb252 308#if defined(TARGET_PPC64)
2adab7d6
BS		 309static void spr_read_hior (void *opaque, int gprn, int sprn)
310{
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
312}
313
314static void spr_write_hior (void *opaque, int sprn, int gprn)
315{
316 TCGv t0 = tcg_temp_new();
317 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
318 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
319 tcg_temp_free(t0);
320}
321
45d827d2 322static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 323{
45d827d2 324 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 325}
326
45d827d2 327static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 328{
45d827d2 329 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 330}
331#endif
a750fc0b 332#endif
76a66253
JM		 333
334/* PowerPC 601 specific registers */
335/* RTC */
45d827d2 336static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 337{
45d827d2 338 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 339}
340
45d827d2 341static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 342{
45d827d2 343 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 344}
345
346#if !defined(CONFIG_USER_ONLY)
45d827d2 347static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 348{
45d827d2 349 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 350}
351
45d827d2 352static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 353{
45d827d2 354 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 355}
056401ea 356
45d827d2 357static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 358{
359 DisasContext *ctx = opaque;
360
45d827d2 361 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 362 /* Must stop the translation as endianness may have changed */
e06fcd75 363 gen_stop_exception(ctx);
056401ea 364}
76a66253
JM		 365#endif
366
367/* Unified bats */
368#if !defined(CONFIG_USER_ONLY)
45d827d2 369static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 370{
45d827d2 371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 372}
373
45d827d2 374static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 375{
45d827d2
AJ		 376 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
377 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
378 tcg_temp_free_i32(t0);
76a66253
JM		 379}
380
45d827d2 381static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 382{
45d827d2
AJ		 383 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
384 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
385 tcg_temp_free_i32(t0);
76a66253
JM		 386}
387#endif
388
389/* PowerPC 40x specific registers */
390#if !defined(CONFIG_USER_ONLY)
45d827d2 391static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 392{
45d827d2 393 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 394}
395
45d827d2 396static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 397{
45d827d2 398 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 399}
400
45d827d2 401static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 402{
403 DisasContext *ctx = opaque;
404
45d827d2 405 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 406 /* We must stop translation as we may have rebooted */
e06fcd75 407 gen_stop_exception(ctx);
8ecc7913
JM		 408}
409
45d827d2 410static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 411{
45d827d2 412 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 413}
414
45d827d2 415static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 416{
45d827d2 417 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 418}
419
45d827d2 420static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 421{
45d827d2 422 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 423}
424#endif
425
426/* PowerPC 403 specific registers */
427/* PBL1 / PBU1 / PBL2 / PBU2 */
428#if !defined(CONFIG_USER_ONLY)
45d827d2 429static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 430{
45d827d2 431 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 432}
433
45d827d2 434static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 435{
45d827d2
AJ		 436 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
437 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
438 tcg_temp_free_i32(t0);
76a66253
JM		 439}
440
45d827d2 441static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 442{
45d827d2
AJ		 443 TCGv t0 = tcg_temp_new();
444 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
445 gen_store_spr(SPR_PIR, t0);
446 tcg_temp_free(t0);
3fc6c082 447}
76a66253 448#endif
3fc6c082 449
d34defbc
AJ		 450/* SPE specific registers */
451static void spr_read_spefscr (void *opaque, int gprn, int sprn)
452{
453 TCGv_i32 t0 = tcg_temp_new_i32();
515e2f7e 454 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 455 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
456 tcg_temp_free_i32(t0);
457}
458
459static void spr_write_spefscr (void *opaque, int sprn, int gprn)
460{
461 TCGv_i32 t0 = tcg_temp_new_i32();
462 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515e2f7e 463 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 464 tcg_temp_free_i32(t0);
465}
466
6f5d427d
JM		 467#if !defined(CONFIG_USER_ONLY)
468/* Callback used to write the exception vector base */
45d827d2 469static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 470{
45d827d2
AJ		 471 TCGv t0 = tcg_temp_new();
472 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
473 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
474 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
475 gen_store_spr(sprn, t0);
69bd5820 476 tcg_temp_free(t0);
6f5d427d
JM		 477}
478
45d827d2 479static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 480{
481 DisasContext *ctx = opaque;
482
483 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 484 TCGv t0 = tcg_temp_new();
485 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
486 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
487 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
488 gen_store_spr(sprn, t0);
489 tcg_temp_free(t0);
6f5d427d 490 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 491 TCGv t0 = tcg_temp_new();
492 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
493 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
494 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
495 gen_store_spr(sprn, t0);
496 tcg_temp_free(t0);
6f5d427d
JM		 497 } else {
498 printf("Trying to write an unknown exception vector %d %03x\n",
499 sprn, sprn);
e06fcd75 500 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 501 }
502}
503#endif
504
cf8358c8
AJ		 505static inline void vscr_init (CPUPPCState *env, uint32_t val)
506{
507 env->vscr = val;
508 /* Altivec always uses round-to-nearest */
509 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
510 set_flush_to_zero(vscr_nj, &env->vec_status);
511}
512
76a66253
JM		 513#if defined(CONFIG_USER_ONLY)
514#define spr_register(env, num, name, uea_read, uea_write, \
515 oea_read, oea_write, initial_value) \
516do { \
517 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
518} while (0)
519static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 520 const char *name,
45d827d2
AJ		 521 void (*uea_read)(void *opaque, int gprn, int sprn),
522 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 523 target_ulong initial_value)
524#else
3fc6c082 525static inline void spr_register (CPUPPCState *env, int num,
b55266b5 526 const char *name,
45d827d2
AJ		 527 void (*uea_read)(void *opaque, int gprn, int sprn),
528 void (*uea_write)(void *opaque, int sprn, int gprn),
529 void (*oea_read)(void *opaque, int gprn, int sprn),
530 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 531 target_ulong initial_value)
76a66253 532#endif
3fc6c082 533{
c227f099 534 ppc_spr_t *spr;
3fc6c082
FB		 535
536 spr = &env->spr_cb[num];
537 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 538#if !defined(CONFIG_USER_ONLY)
539 spr->oea_read != NULL || spr->oea_write != NULL ||
540#endif
541 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 542 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
543 exit(1);
544 }
545#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 546 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
547 name, initial_value);
3fc6c082
FB		 548#endif
549 spr->name = name;
550 spr->uea_read = uea_read;
551 spr->uea_write = uea_write;
76a66253 552#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 553 spr->oea_read = oea_read;
554 spr->oea_write = oea_write;
76a66253 555#endif
3fc6c082
FB		 556 env->spr[num] = initial_value;
557}
558
559/* Generic PowerPC SPRs */
560static void gen_spr_generic (CPUPPCState *env)
561{
562 /* Integer processing */
563 spr_register(env, SPR_XER, "XER",
564 &spr_read_xer, &spr_write_xer,
565 &spr_read_xer, &spr_write_xer,
566 0x00000000);
567 /* Branch contol */
568 spr_register(env, SPR_LR, "LR",
569 &spr_read_lr, &spr_write_lr,
570 &spr_read_lr, &spr_write_lr,
571 0x00000000);
572 spr_register(env, SPR_CTR, "CTR",
573 &spr_read_ctr, &spr_write_ctr,
574 &spr_read_ctr, &spr_write_ctr,
575 0x00000000);
576 /* Interrupt processing */
577 spr_register(env, SPR_SRR0, "SRR0",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_generic, &spr_write_generic,
580 0x00000000);
581 spr_register(env, SPR_SRR1, "SRR1",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_generic, &spr_write_generic,
584 0x00000000);
585 /* Processor control */
586 spr_register(env, SPR_SPRG0, "SPRG0",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_generic, &spr_write_generic,
589 0x00000000);
590 spr_register(env, SPR_SPRG1, "SPRG1",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_generic, &spr_write_generic,
593 0x00000000);
594 spr_register(env, SPR_SPRG2, "SPRG2",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_generic, &spr_write_generic,
597 0x00000000);
598 spr_register(env, SPR_SPRG3, "SPRG3",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_generic, &spr_write_generic,
601 0x00000000);
602}
603
604/* SPR common to all non-embedded PowerPC, including 601 */
605static void gen_spr_ne_601 (CPUPPCState *env)
606{
607 /* Exception processing */
608 spr_register(env, SPR_DSISR, "DSISR",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_generic, &spr_write_generic,
611 0x00000000);
612 spr_register(env, SPR_DAR, "DAR",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_generic, &spr_write_generic,
615 0x00000000);
616 /* Timer */
617 spr_register(env, SPR_DECR, "DECR",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_decr, &spr_write_decr,
620 0x00000000);
621 /* Memory management */
622 spr_register(env, SPR_SDR1, "SDR1",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_sdr1, &spr_write_sdr1,
625 0x00000000);
626}
627
628/* BATs 0-3 */
629static void gen_low_BATs (CPUPPCState *env)
630{
f2e63a42 631#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 632 spr_register(env, SPR_IBAT0U, "IBAT0U",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_ibat, &spr_write_ibatu,
635 0x00000000);
636 spr_register(env, SPR_IBAT0L, "IBAT0L",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_ibat, &spr_write_ibatl,
639 0x00000000);
640 spr_register(env, SPR_IBAT1U, "IBAT1U",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_ibat, &spr_write_ibatu,
643 0x00000000);
644 spr_register(env, SPR_IBAT1L, "IBAT1L",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_ibat, &spr_write_ibatl,
647 0x00000000);
648 spr_register(env, SPR_IBAT2U, "IBAT2U",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_ibat, &spr_write_ibatu,
651 0x00000000);
652 spr_register(env, SPR_IBAT2L, "IBAT2L",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_ibat, &spr_write_ibatl,
655 0x00000000);
656 spr_register(env, SPR_IBAT3U, "IBAT3U",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_ibat, &spr_write_ibatu,
659 0x00000000);
660 spr_register(env, SPR_IBAT3L, "IBAT3L",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_ibat, &spr_write_ibatl,
663 0x00000000);
664 spr_register(env, SPR_DBAT0U, "DBAT0U",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_dbat, &spr_write_dbatu,
667 0x00000000);
668 spr_register(env, SPR_DBAT0L, "DBAT0L",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_dbat, &spr_write_dbatl,
671 0x00000000);
672 spr_register(env, SPR_DBAT1U, "DBAT1U",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_dbat, &spr_write_dbatu,
675 0x00000000);
676 spr_register(env, SPR_DBAT1L, "DBAT1L",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_dbat, &spr_write_dbatl,
679 0x00000000);
680 spr_register(env, SPR_DBAT2U, "DBAT2U",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_dbat, &spr_write_dbatu,
683 0x00000000);
684 spr_register(env, SPR_DBAT2L, "DBAT2L",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_dbat, &spr_write_dbatl,
687 0x00000000);
688 spr_register(env, SPR_DBAT3U, "DBAT3U",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_dbat, &spr_write_dbatu,
691 0x00000000);
692 spr_register(env, SPR_DBAT3L, "DBAT3L",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_dbat, &spr_write_dbatl,
695 0x00000000);
a750fc0b 696 env->nb_BATs += 4;
f2e63a42 697#endif
3fc6c082
FB		 698}
699
700/* BATs 4-7 */
701static void gen_high_BATs (CPUPPCState *env)
702{
f2e63a42 703#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 704 spr_register(env, SPR_IBAT4U, "IBAT4U",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat_h, &spr_write_ibatu_h,
707 0x00000000);
708 spr_register(env, SPR_IBAT4L, "IBAT4L",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat_h, &spr_write_ibatl_h,
711 0x00000000);
712 spr_register(env, SPR_IBAT5U, "IBAT5U",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat_h, &spr_write_ibatu_h,
715 0x00000000);
716 spr_register(env, SPR_IBAT5L, "IBAT5L",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat_h, &spr_write_ibatl_h,
719 0x00000000);
720 spr_register(env, SPR_IBAT6U, "IBAT6U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat_h, &spr_write_ibatu_h,
723 0x00000000);
724 spr_register(env, SPR_IBAT6L, "IBAT6L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_ibat_h, &spr_write_ibatl_h,
727 0x00000000);
728 spr_register(env, SPR_IBAT7U, "IBAT7U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_ibat_h, &spr_write_ibatu_h,
731 0x00000000);
732 spr_register(env, SPR_IBAT7L, "IBAT7L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_ibat_h, &spr_write_ibatl_h,
735 0x00000000);
736 spr_register(env, SPR_DBAT4U, "DBAT4U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat_h, &spr_write_dbatu_h,
739 0x00000000);
740 spr_register(env, SPR_DBAT4L, "DBAT4L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat_h, &spr_write_dbatl_h,
743 0x00000000);
744 spr_register(env, SPR_DBAT5U, "DBAT5U",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat_h, &spr_write_dbatu_h,
747 0x00000000);
748 spr_register(env, SPR_DBAT5L, "DBAT5L",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat_h, &spr_write_dbatl_h,
751 0x00000000);
752 spr_register(env, SPR_DBAT6U, "DBAT6U",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat_h, &spr_write_dbatu_h,
755 0x00000000);
756 spr_register(env, SPR_DBAT6L, "DBAT6L",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_dbat_h, &spr_write_dbatl_h,
759 0x00000000);
760 spr_register(env, SPR_DBAT7U, "DBAT7U",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_dbat_h, &spr_write_dbatu_h,
763 0x00000000);
764 spr_register(env, SPR_DBAT7L, "DBAT7L",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_dbat_h, &spr_write_dbatl_h,
767 0x00000000);
a750fc0b 768 env->nb_BATs += 4;
f2e63a42 769#endif
3fc6c082
FB		 770}
771
772/* Generic PowerPC time base */
773static void gen_tbl (CPUPPCState *env)
774{
775 spr_register(env, SPR_VTBL, "TBL",
776 &spr_read_tbl, SPR_NOACCESS,
777 &spr_read_tbl, SPR_NOACCESS,
778 0x00000000);
779 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 780 &spr_read_tbl, SPR_NOACCESS,
781 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 782 0x00000000);
783 spr_register(env, SPR_VTBU, "TBU",
784 &spr_read_tbu, SPR_NOACCESS,
785 &spr_read_tbu, SPR_NOACCESS,
786 0x00000000);
787 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 788 &spr_read_tbu, SPR_NOACCESS,
789 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 790 0x00000000);
791}
792
76a66253
JM		 793/* Softare table search registers */
794static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
795{
f2e63a42 796#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 797 env->nb_tlb = nb_tlbs;
798 env->nb_ways = nb_ways;
799 env->id_tlbs = 1;
800 spr_register(env, SPR_DMISS, "DMISS",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, SPR_NOACCESS,
803 0x00000000);
804 spr_register(env, SPR_DCMP, "DCMP",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, SPR_NOACCESS,
807 0x00000000);
808 spr_register(env, SPR_HASH1, "HASH1",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_generic, SPR_NOACCESS,
811 0x00000000);
812 spr_register(env, SPR_HASH2, "HASH2",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, SPR_NOACCESS,
815 0x00000000);
816 spr_register(env, SPR_IMISS, "IMISS",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, SPR_NOACCESS,
819 0x00000000);
820 spr_register(env, SPR_ICMP, "ICMP",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_generic, SPR_NOACCESS,
823 0x00000000);
824 spr_register(env, SPR_RPA, "RPA",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
f2e63a42 828#endif
76a66253
JM		 829}
830
831/* SPR common to MPC755 and G2 */
832static void gen_spr_G2_755 (CPUPPCState *env)
833{
834 /* SGPRs */
835 spr_register(env, SPR_SPRG4, "SPRG4",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_generic, &spr_write_generic,
838 0x00000000);
839 spr_register(env, SPR_SPRG5, "SPRG5",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_generic, &spr_write_generic,
842 0x00000000);
843 spr_register(env, SPR_SPRG6, "SPRG6",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_generic, &spr_write_generic,
846 0x00000000);
847 spr_register(env, SPR_SPRG7, "SPRG7",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, &spr_write_generic,
850 0x00000000);
76a66253
JM		 851}
852
3fc6c082
FB		 853/* SPR common to all 7xx PowerPC implementations */
854static void gen_spr_7xx (CPUPPCState *env)
855{
856 /* Breakpoints */
857 /* XXX : not implemented */
858 spr_register(env, SPR_DABR, "DABR",
859 SPR_NOACCESS, SPR_NOACCESS,
860 &spr_read_generic, &spr_write_generic,
861 0x00000000);
862 /* XXX : not implemented */
863 spr_register(env, SPR_IABR, "IABR",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, &spr_write_generic,
866 0x00000000);
867 /* Cache management */
868 /* XXX : not implemented */
869 spr_register(env, SPR_ICTC, "ICTC",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, &spr_write_generic,
872 0x00000000);
873 /* Performance monitors */
874 /* XXX : not implemented */
875 spr_register(env, SPR_MMCR0, "MMCR0",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, &spr_write_generic,
878 0x00000000);
879 /* XXX : not implemented */
880 spr_register(env, SPR_MMCR1, "MMCR1",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, &spr_write_generic,
883 0x00000000);
884 /* XXX : not implemented */
885 spr_register(env, SPR_PMC1, "PMC1",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 /* XXX : not implemented */
890 spr_register(env, SPR_PMC2, "PMC2",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 /* XXX : not implemented */
895 spr_register(env, SPR_PMC3, "PMC3",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899 /* XXX : not implemented */
900 spr_register(env, SPR_PMC4, "PMC4",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, &spr_write_generic,
903 0x00000000);
904 /* XXX : not implemented */
a750fc0b 905 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, SPR_NOACCESS,
908 0x00000000);
578bb252 909 /* XXX : not implemented */
3fc6c082
FB		 910 spr_register(env, SPR_UMMCR0, "UMMCR0",
911 &spr_read_ureg, SPR_NOACCESS,
912 &spr_read_ureg, SPR_NOACCESS,
913 0x00000000);
578bb252 914 /* XXX : not implemented */
3fc6c082
FB		 915 spr_register(env, SPR_UMMCR1, "UMMCR1",
916 &spr_read_ureg, SPR_NOACCESS,
917 &spr_read_ureg, SPR_NOACCESS,
918 0x00000000);
578bb252 919 /* XXX : not implemented */
3fc6c082
FB		 920 spr_register(env, SPR_UPMC1, "UPMC1",
921 &spr_read_ureg, SPR_NOACCESS,
922 &spr_read_ureg, SPR_NOACCESS,
923 0x00000000);
578bb252 924 /* XXX : not implemented */
3fc6c082
FB		 925 spr_register(env, SPR_UPMC2, "UPMC2",
926 &spr_read_ureg, SPR_NOACCESS,
927 &spr_read_ureg, SPR_NOACCESS,
928 0x00000000);
578bb252 929 /* XXX : not implemented */
3fc6c082
FB		 930 spr_register(env, SPR_UPMC3, "UPMC3",
931 &spr_read_ureg, SPR_NOACCESS,
932 &spr_read_ureg, SPR_NOACCESS,
933 0x00000000);
578bb252 934 /* XXX : not implemented */
3fc6c082
FB		 935 spr_register(env, SPR_UPMC4, "UPMC4",
936 &spr_read_ureg, SPR_NOACCESS,
937 &spr_read_ureg, SPR_NOACCESS,
938 0x00000000);
578bb252 939 /* XXX : not implemented */
a750fc0b 940 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 941 &spr_read_ureg, SPR_NOACCESS,
942 &spr_read_ureg, SPR_NOACCESS,
943 0x00000000);
a750fc0b 944 /* External access control */
3fc6c082 945 /* XXX : not implemented */
a750fc0b 946 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
a750fc0b
JM		 950}
951
952static void gen_spr_thrm (CPUPPCState *env)
953{
954 /* Thermal management */
3fc6c082 955 /* XXX : not implemented */
a750fc0b 956 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 /* XXX : not implemented */
a750fc0b 961 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
3fc6c082 965 /* XXX : not implemented */
a750fc0b 966 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970}
971
972/* SPR specific to PowerPC 604 implementation */
973static void gen_spr_604 (CPUPPCState *env)
974{
975 /* Processor identification */
976 spr_register(env, SPR_PIR, "PIR",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_pir,
979 0x00000000);
980 /* Breakpoints */
981 /* XXX : not implemented */
982 spr_register(env, SPR_IABR, "IABR",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 /* XXX : not implemented */
987 spr_register(env, SPR_DABR, "DABR",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
991 /* Performance counters */
992 /* XXX : not implemented */
993 spr_register(env, SPR_MMCR0, "MMCR0",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997 /* XXX : not implemented */
3fc6c082
FB		 998 spr_register(env, SPR_PMC1, "PMC1",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_PMC2, "PMC2",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 /* XXX : not implemented */
a750fc0b 1008 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, SPR_NOACCESS,
1011 0x00000000);
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_SDA, "SDA",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, SPR_NOACCESS,
1016 0x00000000);
1017 /* External access control */
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_EAR, "EAR",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023}
1024
76a66253
JM		 1025/* SPR specific to PowerPC 603 implementation */
1026static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1027{
76a66253
JM		 1028 /* External access control */
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1031 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
3fc6c082
FB		 1034}
1035
76a66253
JM		 1036/* SPR specific to PowerPC G2 implementation */
1037static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1038{
76a66253
JM		 1039 /* Memory base address */
1040 /* MBAR */
578bb252 1041 /* XXX : not implemented */
76a66253
JM		 1042 spr_register(env, SPR_MBAR, "MBAR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
76a66253 1046 /* Exception processing */
363be49c 1047 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
363be49c 1051 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* Breakpoints */
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_DABR, "DABR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_DABR2, "DABR2",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 0x00000000);
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_IABR, "IABR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_IABR2, "IABR2",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_IBCR, "IBCR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_DBCR, "DBCR",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086}
1087
1088/* SPR specific to PowerPC 602 implementation */
1089static void gen_spr_602 (CPUPPCState *env)
1090{
1091 /* ESA registers */
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_SER, "SER",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_SEBR, "SEBR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* XXX : not implemented */
a750fc0b 1103 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 /* Floating point status */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_SP, "SP",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register(env, SPR_LT, "LT",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* Watchdog timer */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_TCR, "TCR",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* Interrupt base */
1125 spr_register(env, SPR_IBR, "IBR",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
a750fc0b
JM		 1129 /* XXX : not implemented */
1130 spr_register(env, SPR_IABR, "IABR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
76a66253
JM		 1134}
1135
1136/* SPR specific to PowerPC 601 implementation */
1137static void gen_spr_601 (CPUPPCState *env)
1138{
1139 /* Multiplication/division register */
1140 /* MQ */
1141 spr_register(env, SPR_MQ, "MQ",
1142 &spr_read_generic, &spr_write_generic,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* RTC registers */
1146 spr_register(env, SPR_601_RTCU, "RTCU",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 SPR_NOACCESS, &spr_write_601_rtcu,
1149 0x00000000);
1150 spr_register(env, SPR_601_VRTCU, "RTCU",
1151 &spr_read_601_rtcu, SPR_NOACCESS,
1152 &spr_read_601_rtcu, SPR_NOACCESS,
1153 0x00000000);
1154 spr_register(env, SPR_601_RTCL, "RTCL",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 SPR_NOACCESS, &spr_write_601_rtcl,
1157 0x00000000);
1158 spr_register(env, SPR_601_VRTCL, "RTCL",
1159 &spr_read_601_rtcl, SPR_NOACCESS,
1160 &spr_read_601_rtcl, SPR_NOACCESS,
1161 0x00000000);
1162 /* Timer */
1163#if 0 /* ? */
1164 spr_register(env, SPR_601_UDECR, "UDECR",
1165 &spr_read_decr, SPR_NOACCESS,
1166 &spr_read_decr, SPR_NOACCESS,
1167 0x00000000);
1168#endif
1169 /* External access control */
1170 /* XXX : not implemented */
1171 spr_register(env, SPR_EAR, "EAR",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175 /* Memory management */
f2e63a42 1176#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1177 spr_register(env, SPR_IBAT0U, "IBAT0U",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_601_ubat, &spr_write_601_ubatu,
1180 0x00000000);
1181 spr_register(env, SPR_IBAT0L, "IBAT0L",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_601_ubat, &spr_write_601_ubatl,
1184 0x00000000);
1185 spr_register(env, SPR_IBAT1U, "IBAT1U",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_601_ubat, &spr_write_601_ubatu,
1188 0x00000000);
1189 spr_register(env, SPR_IBAT1L, "IBAT1L",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_601_ubat, &spr_write_601_ubatl,
1192 0x00000000);
1193 spr_register(env, SPR_IBAT2U, "IBAT2U",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_601_ubat, &spr_write_601_ubatu,
1196 0x00000000);
1197 spr_register(env, SPR_IBAT2L, "IBAT2L",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_601_ubat, &spr_write_601_ubatl,
1200 0x00000000);
1201 spr_register(env, SPR_IBAT3U, "IBAT3U",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_601_ubat, &spr_write_601_ubatu,
1204 0x00000000);
1205 spr_register(env, SPR_IBAT3L, "IBAT3L",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_601_ubat, &spr_write_601_ubatl,
1208 0x00000000);
a750fc0b 1209 env->nb_BATs = 4;
f2e63a42 1210#endif
a750fc0b
JM		 1211}
1212
1213static void gen_spr_74xx (CPUPPCState *env)
1214{
1215 /* Processor identification */
1216 spr_register(env, SPR_PIR, "PIR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_pir,
1219 0x00000000);
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_MMCR2, "MMCR2",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
578bb252 1225 /* XXX : not implemented */
a750fc0b
JM		 1226 spr_register(env, SPR_UMMCR2, "UMMCR2",
1227 &spr_read_ureg, SPR_NOACCESS,
1228 &spr_read_ureg, SPR_NOACCESS,
1229 0x00000000);
1230 /* XXX: not implemented */
1231 spr_register(env, SPR_BAMR, "BAMR",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_generic,
1234 0x00000000);
578bb252 1235 /* XXX : not implemented */
a750fc0b
JM		 1236 spr_register(env, SPR_MSSCR0, "MSSCR0",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 /* Hardware implementation registers */
1241 /* XXX : not implemented */
1242 spr_register(env, SPR_HID0, "HID0",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 /* XXX : not implemented */
1247 spr_register(env, SPR_HID1, "HID1",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251 /* Altivec */
1252 spr_register(env, SPR_VRSAVE, "VRSAVE",
1253 &spr_read_generic, &spr_write_generic,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
bd928eba
JM		 1256 /* XXX : not implemented */
1257 spr_register(env, SPR_L2CR, "L2CR",
1258 SPR_NOACCESS, SPR_NOACCESS,
1259 &spr_read_generic, &spr_write_generic,
1260 0x00000000);
cf8358c8
AJ		 1261 /* Not strictly an SPR */
1262 vscr_init(env, 0x00010000);
a750fc0b
JM		 1263}
1264
a750fc0b
JM		 1265static void gen_l3_ctrl (CPUPPCState *env)
1266{
1267 /* L3CR */
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_L3CR, "L3CR",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* L3ITCR0 */
578bb252 1274 /* XXX : not implemented */
a750fc0b
JM		 1275 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
a750fc0b 1279 /* L3PM */
578bb252 1280 /* XXX : not implemented */
a750fc0b
JM		 1281 spr_register(env, SPR_L3PM, "L3PM",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285}
a750fc0b 1286
578bb252 1287static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1288{
f2e63a42 1289#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1290 env->nb_tlb = nb_tlbs;
1291 env->nb_ways = nb_ways;
1292 env->id_tlbs = 1;
1293 /* XXX : not implemented */
a750fc0b
JM		 1294 spr_register(env, SPR_PTEHI, "PTEHI",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
578bb252 1298 /* XXX : not implemented */
a750fc0b
JM		 1299 spr_register(env, SPR_PTELO, "PTELO",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
578bb252 1303 /* XXX : not implemented */
a750fc0b
JM		 1304 spr_register(env, SPR_TLBMISS, "TLBMISS",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
f2e63a42 1308#endif
76a66253
JM		 1309}
1310
80d11f44 1311static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1312{
80d11f44
JM		 1313 spr_register(env, SPR_USPRG4, "USPRG4",
1314 &spr_read_ureg, SPR_NOACCESS,
1315 &spr_read_ureg, SPR_NOACCESS,
1316 0x00000000);
1317 spr_register(env, SPR_USPRG5, "USPRG5",
1318 &spr_read_ureg, SPR_NOACCESS,
1319 &spr_read_ureg, SPR_NOACCESS,
1320 0x00000000);
1321 spr_register(env, SPR_USPRG6, "USPRG6",
1322 &spr_read_ureg, SPR_NOACCESS,
1323 &spr_read_ureg, SPR_NOACCESS,
1324 0x00000000);
1325 spr_register(env, SPR_USPRG7, "USPRG7",
1326 &spr_read_ureg, SPR_NOACCESS,
1327 &spr_read_ureg, SPR_NOACCESS,
76a66253 1328 0x00000000);
80d11f44
JM		 1329}
1330
1331/* PowerPC BookE SPR */
1332static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1333{
b55266b5 1334 const char *ivor_names[64] = {
80d11f44
JM		 1335 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1336 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1337 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1338 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1339 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1340 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1341 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1342 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1343 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1344 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1345 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1346 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1347 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1348 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1349 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1350 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1351 };
1352#define SPR_BOOKE_IVORxx (-1)
1353 int ivor_sprn[64] = {
1354 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1355 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1356 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1357 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1358 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1359 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1360 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1361 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1362 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1363 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1364 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1365 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1366 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1367 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1368 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1369 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1370 };
1371 int i;
1372
76a66253 1373 /* Interrupt processing */
363be49c 1374 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
363be49c
JM		 1378 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
76a66253
JM		 1382 /* Debug */
1383 /* XXX : not implemented */
1384 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388 /* XXX : not implemented */
1389 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393 /* XXX : not implemented */
76a66253
JM		 1394 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398 /* XXX : not implemented */
1399 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403 /* XXX : not implemented */
76a66253
JM		 1404 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408 /* XXX : not implemented */
1409 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413 /* XXX : not implemented */
1414 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1420 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1421 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1422 0x00000000);
1423 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427 spr_register(env, SPR_BOOKE_ESR, "ESR",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
363be49c
JM		 1431 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1432 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1433 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1434 0x00000000);
1435 /* Exception vectors */
80d11f44
JM		 1436 for (i = 0; i < 64; i++) {
1437 if (ivor_mask & (1ULL << i)) {
1438 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1439 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1440 exit(1);
1441 }
1442 spr_register(env, ivor_sprn[i], ivor_names[i],
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_excp_vector,
1445 0x00000000);
1446 }
1447 }
76a66253
JM		 1448 spr_register(env, SPR_BOOKE_PID, "PID",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452 spr_register(env, SPR_BOOKE_TCR, "TCR",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_booke_tcr,
1455 0x00000000);
1456 spr_register(env, SPR_BOOKE_TSR, "TSR",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_booke_tsr,
1459 0x00000000);
1460 /* Timer */
1461 spr_register(env, SPR_DECR, "DECR",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_decr, &spr_write_decr,
1464 0x00000000);
1465 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 SPR_NOACCESS, &spr_write_generic,
1468 0x00000000);
1469 /* SPRGs */
1470 spr_register(env, SPR_USPRG0, "USPRG0",
1471 &spr_read_generic, &spr_write_generic,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 spr_register(env, SPR_SPRG4, "SPRG4",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
76a66253
JM		 1478 spr_register(env, SPR_SPRG5, "SPRG5",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
76a66253
JM		 1482 spr_register(env, SPR_SPRG6, "SPRG6",
1483 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_generic, &spr_write_generic,
1485 0x00000000);
76a66253
JM		 1486 spr_register(env, SPR_SPRG7, "SPRG7",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
76a66253
JM		 1490}
1491
363be49c 1492/* FSL storage control registers */
80d11f44 1493static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1494{
f2e63a42 1495#if !defined(CONFIG_USER_ONLY)
b55266b5 1496 const char *mas_names[8] = {
80d11f44
JM		 1497 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1498 };
1499 int mas_sprn[8] = {
1500 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1501 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1502 };
1503 int i;
1504
363be49c 1505 /* TLB assist registers */
578bb252 1506 /* XXX : not implemented */
80d11f44
JM		 1507 for (i = 0; i < 8; i++) {
1508 if (mas_mask & (1 << i)) {
1509 spr_register(env, mas_sprn[i], mas_names[i],
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_generic,
1512 0x00000000);
1513 }
1514 }
363be49c 1515 if (env->nb_pids > 1) {
578bb252 1516 /* XXX : not implemented */
363be49c
JM		 1517 spr_register(env, SPR_BOOKE_PID1, "PID1",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000);
1521 }
1522 if (env->nb_pids > 2) {
578bb252 1523 /* XXX : not implemented */
363be49c
JM		 1524 spr_register(env, SPR_BOOKE_PID2, "PID2",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528 }
578bb252 1529 /* XXX : not implemented */
65f9ee8d 1530 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, SPR_NOACCESS,
1533 0x00000000); /* TOFIX */
578bb252 1534 /* XXX : not implemented */
65f9ee8d 1535 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000); /* TOFIX */
1539 switch (env->nb_ways) {
1540 case 4:
578bb252 1541 /* XXX : not implemented */
363be49c
JM		 1542 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, SPR_NOACCESS,
1545 0x00000000); /* TOFIX */
1546 /* Fallthru */
1547 case 3:
578bb252 1548 /* XXX : not implemented */
363be49c
JM		 1549 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, SPR_NOACCESS,
1552 0x00000000); /* TOFIX */
1553 /* Fallthru */
1554 case 2:
578bb252 1555 /* XXX : not implemented */
363be49c
JM		 1556 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, SPR_NOACCESS,
1559 0x00000000); /* TOFIX */
1560 /* Fallthru */
1561 case 1:
578bb252 1562 /* XXX : not implemented */
363be49c
JM		 1563 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, SPR_NOACCESS,
1566 0x00000000); /* TOFIX */
1567 /* Fallthru */
1568 case 0:
1569 default:
1570 break;
1571 }
f2e63a42 1572#endif
363be49c
JM		 1573}
1574
76a66253
JM		 1575/* SPR specific to PowerPC 440 implementation */
1576static void gen_spr_440 (CPUPPCState *env)
1577{
1578 /* Cache control */
1579 /* XXX : not implemented */
1580 spr_register(env, SPR_440_DNV0, "DNV0",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584 /* XXX : not implemented */
1585 spr_register(env, SPR_440_DNV1, "DNV1",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589 /* XXX : not implemented */
1590 spr_register(env, SPR_440_DNV2, "DNV2",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594 /* XXX : not implemented */
1595 spr_register(env, SPR_440_DNV3, "DNV3",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 /* XXX : not implemented */
2662a059 1600 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604 /* XXX : not implemented */
2662a059 1605 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609 /* XXX : not implemented */
2662a059 1610 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 /* XXX : not implemented */
2662a059 1615 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 /* XXX : not implemented */
1620 spr_register(env, SPR_440_DVLIM, "DVLIM",
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, &spr_write_generic,
1623 0x00000000);
1624 /* XXX : not implemented */
1625 spr_register(env, SPR_440_INV0, "INV0",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_generic,
1628 0x00000000);
1629 /* XXX : not implemented */
1630 spr_register(env, SPR_440_INV1, "INV1",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 /* XXX : not implemented */
1635 spr_register(env, SPR_440_INV2, "INV2",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_generic,
1638 0x00000000);
1639 /* XXX : not implemented */
1640 spr_register(env, SPR_440_INV3, "INV3",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, &spr_write_generic,
1643 0x00000000);
1644 /* XXX : not implemented */
2662a059 1645 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1646 SPR_NOACCESS, SPR_NOACCESS,
1647 &spr_read_generic, &spr_write_generic,
1648 0x00000000);
1649 /* XXX : not implemented */
2662a059 1650 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, &spr_write_generic,
1653 0x00000000);
1654 /* XXX : not implemented */
2662a059 1655 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 /* XXX : not implemented */
2662a059 1660 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1661 SPR_NOACCESS, SPR_NOACCESS,
1662 &spr_read_generic, &spr_write_generic,
1663 0x00000000);
1664 /* XXX : not implemented */
1665 spr_register(env, SPR_440_IVLIM, "IVLIM",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_generic,
1668 0x00000000);
1669 /* Cache debug */
1670 /* XXX : not implemented */
2662a059 1671 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, SPR_NOACCESS,
1674 0x00000000);
1675 /* XXX : not implemented */
2662a059 1676 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, SPR_NOACCESS,
1679 0x00000000);
1680 /* XXX : not implemented */
2662a059 1681 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, SPR_NOACCESS,
1684 0x00000000);
1685 /* XXX : not implemented */
2662a059 1686 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, SPR_NOACCESS,
1689 0x00000000);
1690 /* XXX : not implemented */
2662a059 1691 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, SPR_NOACCESS,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_440_DBDR, "DBDR",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* Processor control */
1701 spr_register(env, SPR_4xx_CCR0, "CCR0",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, SPR_NOACCESS,
1708 0x00000000);
1709 /* Storage control */
1710 spr_register(env, SPR_440_MMUCR, "MMUCR",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714}
1715
1716/* SPR shared between PowerPC 40x implementations */
1717static void gen_spr_40x (CPUPPCState *env)
1718{
1719 /* Cache */
035feb88 1720 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1721 spr_register(env, SPR_40x_DCCR, "DCCR",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
035feb88 1725 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1726 spr_register(env, SPR_40x_ICCR, "ICCR",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
578bb252 1730 /* not emulated, as Qemu do not emulate caches */
2662a059 1731 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, SPR_NOACCESS,
1734 0x00000000);
76a66253
JM		 1735 /* Exception */
1736 spr_register(env, SPR_40x_DEAR, "DEAR",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 spr_register(env, SPR_40x_ESR, "ESR",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744 spr_register(env, SPR_40x_EVPR, "EVPR",
1745 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1746 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1747 0x00000000);
1748 spr_register(env, SPR_40x_SRR2, "SRR2",
1749 &spr_read_generic, &spr_write_generic,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_40x_SRR3, "SRR3",
1753 &spr_read_generic, &spr_write_generic,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 /* Timers */
1757 spr_register(env, SPR_40x_PIT, "PIT",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_40x_pit, &spr_write_40x_pit,
1760 0x00000000);
1761 spr_register(env, SPR_40x_TCR, "TCR",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_booke_tcr,
1764 0x00000000);
1765 spr_register(env, SPR_40x_TSR, "TSR",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_booke_tsr,
1768 0x00000000);
2662a059
JM		 1769}
1770
1771/* SPR specific to PowerPC 405 implementation */
1772static void gen_spr_405 (CPUPPCState *env)
1773{
1774 /* MMU */
1775 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
2662a059 1779 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1782 0x00700000);
1783 /* Debug interface */
76a66253
JM		 1784 /* XXX : not implemented */
1785 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1786 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1787 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1788 0x00000000);
1789 /* XXX : not implemented */
2662a059
JM		 1790 spr_register(env, SPR_405_DBCR1, "DBCR1",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
76a66253
JM		 1795 spr_register(env, SPR_40x_DBSR, "DBSR",
1796 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1797 &spr_read_generic, &spr_write_clear,
1798 /* Last reset was system reset */
76a66253
JM		 1799 0x00000300);
1800 /* XXX : not implemented */
2662a059 1801 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_generic,
1804 0x00000000);
2662a059 1805 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
2662a059
JM		 1809 /* XXX : not implemented */
1810 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
2662a059 1813 0x00000000);
76a66253 1814 /* XXX : not implemented */
2662a059 1815 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 /* XXX : not implemented */
2662a059 1820 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_generic,
1823 0x00000000);
2662a059 1824 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 /* XXX : not implemented */
1829 spr_register(env, SPR_405_IAC3, "IAC3",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
1833 /* XXX : not implemented */
1834 spr_register(env, SPR_405_IAC4, "IAC4",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, &spr_write_generic,
1837 0x00000000);
1838 /* Storage control */
035feb88 1839 /* XXX: TODO: not implemented */
76a66253
JM		 1840 spr_register(env, SPR_405_SLER, "SLER",
1841 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1842 &spr_read_generic, &spr_write_40x_sler,
76a66253 1843 0x00000000);
2662a059
JM		 1844 spr_register(env, SPR_40x_ZPR, "ZPR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
1847 0x00000000);
76a66253
JM		 1848 /* XXX : not implemented */
1849 spr_register(env, SPR_405_SU0R, "SU0R",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 /* SPRG */
1854 spr_register(env, SPR_USPRG0, "USPRG0",
1855 &spr_read_ureg, SPR_NOACCESS,
1856 &spr_read_ureg, SPR_NOACCESS,
1857 0x00000000);
1858 spr_register(env, SPR_SPRG4, "SPRG4",
1859 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1860 &spr_read_generic, &spr_write_generic,
76a66253 1861 0x00000000);
76a66253
JM		 1862 spr_register(env, SPR_SPRG5, "SPRG5",
1863 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1864 spr_read_generic, &spr_write_generic,
76a66253 1865 0x00000000);
76a66253
JM		 1866 spr_register(env, SPR_SPRG6, "SPRG6",
1867 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1868 spr_read_generic, &spr_write_generic,
76a66253 1869 0x00000000);
76a66253
JM		 1870 spr_register(env, SPR_SPRG7, "SPRG7",
1871 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1872 spr_read_generic, &spr_write_generic,
76a66253 1873 0x00000000);
80d11f44 1874 gen_spr_usprgh(env);
76a66253
JM		 1875}
1876
1877/* SPR shared between PowerPC 401 & 403 implementations */
1878static void gen_spr_401_403 (CPUPPCState *env)
1879{
1880 /* Time base */
1881 spr_register(env, SPR_403_VTBL, "TBL",
1882 &spr_read_tbl, SPR_NOACCESS,
1883 &spr_read_tbl, SPR_NOACCESS,
1884 0x00000000);
1885 spr_register(env, SPR_403_TBL, "TBL",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 SPR_NOACCESS, &spr_write_tbl,
1888 0x00000000);
1889 spr_register(env, SPR_403_VTBU, "TBU",
1890 &spr_read_tbu, SPR_NOACCESS,
1891 &spr_read_tbu, SPR_NOACCESS,
1892 0x00000000);
1893 spr_register(env, SPR_403_TBU, "TBU",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 SPR_NOACCESS, &spr_write_tbu,
1896 0x00000000);
1897 /* Debug */
578bb252 1898 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1899 spr_register(env, SPR_403_CDBCR, "CDBCR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
1903}
1904
2662a059
JM		 1905/* SPR specific to PowerPC 401 implementation */
1906static void gen_spr_401 (CPUPPCState *env)
1907{
1908 /* Debug interface */
1909 /* XXX : not implemented */
1910 spr_register(env, SPR_40x_DBCR0, "DBCR",
1911 SPR_NOACCESS, SPR_NOACCESS,
1912 &spr_read_generic, &spr_write_40x_dbcr0,
1913 0x00000000);
1914 /* XXX : not implemented */
1915 spr_register(env, SPR_40x_DBSR, "DBSR",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_clear,
1918 /* Last reset was system reset */
1919 0x00000300);
1920 /* XXX : not implemented */
1921 spr_register(env, SPR_40x_DAC1, "DAC",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 /* XXX : not implemented */
1926 spr_register(env, SPR_40x_IAC1, "IAC",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
1930 /* Storage control */
035feb88 1931 /* XXX: TODO: not implemented */
2662a059
JM		 1932 spr_register(env, SPR_405_SLER, "SLER",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_40x_sler,
1935 0x00000000);
035feb88
JM		 1936 /* not emulated, as Qemu never does speculative access */
1937 spr_register(env, SPR_40x_SGR, "SGR",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0xFFFFFFFF);
1941 /* not emulated, as Qemu do not emulate caches */
1942 spr_register(env, SPR_40x_DCWR, "DCWR",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
2662a059
JM		 1946}
1947
a750fc0b
JM		 1948static void gen_spr_401x2 (CPUPPCState *env)
1949{
1950 gen_spr_401(env);
1951 spr_register(env, SPR_40x_PID, "PID",
1952 SPR_NOACCESS, SPR_NOACCESS,
1953 &spr_read_generic, &spr_write_generic,
1954 0x00000000);
1955 spr_register(env, SPR_40x_ZPR, "ZPR",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959}
1960
76a66253
JM		 1961/* SPR specific to PowerPC 403 implementation */
1962static void gen_spr_403 (CPUPPCState *env)
1963{
2662a059
JM		 1964 /* Debug interface */
1965 /* XXX : not implemented */
1966 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_generic, &spr_write_40x_dbcr0,
1969 0x00000000);
1970 /* XXX : not implemented */
1971 spr_register(env, SPR_40x_DBSR, "DBSR",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_clear,
1974 /* Last reset was system reset */
1975 0x00000300);
1976 /* XXX : not implemented */
1977 spr_register(env, SPR_40x_DAC1, "DAC1",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
578bb252 1981 /* XXX : not implemented */
2662a059
JM		 1982 spr_register(env, SPR_40x_DAC2, "DAC2",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986 /* XXX : not implemented */
1987 spr_register(env, SPR_40x_IAC1, "IAC1",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
578bb252 1991 /* XXX : not implemented */
2662a059
JM		 1992 spr_register(env, SPR_40x_IAC2, "IAC2",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
a750fc0b
JM		 1996}
1997
1998static void gen_spr_403_real (CPUPPCState *env)
1999{
76a66253
JM		 2000 spr_register(env, SPR_403_PBL1, "PBL1",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_403_pbr, &spr_write_403_pbr,
2003 0x00000000);
2004 spr_register(env, SPR_403_PBU1, "PBU1",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_403_pbr, &spr_write_403_pbr,
2007 0x00000000);
2008 spr_register(env, SPR_403_PBL2, "PBL2",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_403_pbr, &spr_write_403_pbr,
2011 0x00000000);
2012 spr_register(env, SPR_403_PBU2, "PBU2",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_403_pbr, &spr_write_403_pbr,
2015 0x00000000);
a750fc0b
JM		 2016}
2017
2018static void gen_spr_403_mmu (CPUPPCState *env)
2019{
2020 /* MMU */
2021 spr_register(env, SPR_40x_PID, "PID",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2662a059 2025 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029}
2030
2031/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2032static void gen_spr_compress (CPUPPCState *env)
2033{
578bb252 2034 /* XXX : not implemented */
76a66253
JM		 2035 spr_register(env, SPR_401_SKR, "SKR",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039}
a750fc0b
JM		 2040
2041#if defined (TARGET_PPC64)
a750fc0b
JM		 2042/* SPR specific to PowerPC 620 */
2043static void gen_spr_620 (CPUPPCState *env)
2044{
082c6681
JM		 2045 /* Processor identification */
2046 spr_register(env, SPR_PIR, "PIR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_pir,
2049 0x00000000);
2050 spr_register(env, SPR_ASR, "ASR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_asr, &spr_write_asr,
2053 0x00000000);
2054 /* Breakpoints */
2055 /* XXX : not implemented */
2056 spr_register(env, SPR_IABR, "IABR",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2059 0x00000000);
2060 /* XXX : not implemented */
2061 spr_register(env, SPR_DABR, "DABR",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
2065 /* XXX : not implemented */
2066 spr_register(env, SPR_SIAR, "SIAR",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, SPR_NOACCESS,
2069 0x00000000);
2070 /* XXX : not implemented */
2071 spr_register(env, SPR_SDA, "SDA",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, SPR_NOACCESS,
2074 0x00000000);
2075 /* XXX : not implemented */
2076 spr_register(env, SPR_620_PMC1R, "PMC1",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, SPR_NOACCESS,
2079 0x00000000);
2080 spr_register(env, SPR_620_PMC1W, "PMC1",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 SPR_NOACCESS, &spr_write_generic,
2083 0x00000000);
2084 /* XXX : not implemented */
2085 spr_register(env, SPR_620_PMC2R, "PMC2",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, SPR_NOACCESS,
2088 0x00000000);
2089 spr_register(env, SPR_620_PMC2W, "PMC2",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 SPR_NOACCESS, &spr_write_generic,
2092 0x00000000);
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, SPR_NOACCESS,
2097 0x00000000);
2098 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 SPR_NOACCESS, &spr_write_generic,
2101 0x00000000);
2102 /* External access control */
2103 /* XXX : not implemented */
2104 spr_register(env, SPR_EAR, "EAR",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108#if 0 // XXX: check this
578bb252 2109 /* XXX : not implemented */
a750fc0b
JM		 2110 spr_register(env, SPR_620_PMR0, "PMR0",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
578bb252 2114 /* XXX : not implemented */
a750fc0b
JM		 2115 spr_register(env, SPR_620_PMR1, "PMR1",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_generic, &spr_write_generic,
2118 0x00000000);
578bb252 2119 /* XXX : not implemented */
a750fc0b
JM		 2120 spr_register(env, SPR_620_PMR2, "PMR2",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_generic,
2123 0x00000000);
578bb252 2124 /* XXX : not implemented */
a750fc0b
JM		 2125 spr_register(env, SPR_620_PMR3, "PMR3",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
578bb252 2129 /* XXX : not implemented */
a750fc0b
JM		 2130 spr_register(env, SPR_620_PMR4, "PMR4",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 &spr_read_generic, &spr_write_generic,
2133 0x00000000);
578bb252 2134 /* XXX : not implemented */
a750fc0b
JM		 2135 spr_register(env, SPR_620_PMR5, "PMR5",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
578bb252 2139 /* XXX : not implemented */
a750fc0b
JM		 2140 spr_register(env, SPR_620_PMR6, "PMR6",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
578bb252 2144 /* XXX : not implemented */
a750fc0b
JM		 2145 spr_register(env, SPR_620_PMR7, "PMR7",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
578bb252 2149 /* XXX : not implemented */
a750fc0b
JM		 2150 spr_register(env, SPR_620_PMR8, "PMR8",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
578bb252 2154 /* XXX : not implemented */
a750fc0b
JM		 2155 spr_register(env, SPR_620_PMR9, "PMR9",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
578bb252 2159 /* XXX : not implemented */
a750fc0b
JM		 2160 spr_register(env, SPR_620_PMRA, "PMR10",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
578bb252 2164 /* XXX : not implemented */
a750fc0b
JM		 2165 spr_register(env, SPR_620_PMRB, "PMR11",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
578bb252 2169 /* XXX : not implemented */
a750fc0b
JM		 2170 spr_register(env, SPR_620_PMRC, "PMR12",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
578bb252 2174 /* XXX : not implemented */
a750fc0b
JM		 2175 spr_register(env, SPR_620_PMRD, "PMR13",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
578bb252 2179 /* XXX : not implemented */
a750fc0b
JM		 2180 spr_register(env, SPR_620_PMRE, "PMR14",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
578bb252 2184 /* XXX : not implemented */
a750fc0b
JM		 2185 spr_register(env, SPR_620_PMRF, "PMR15",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
082c6681 2189#endif
578bb252 2190 /* XXX : not implemented */
082c6681 2191 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, &spr_write_generic,
2194 0x00000000);
578bb252 2195 /* XXX : not implemented */
082c6681
JM		 2196 spr_register(env, SPR_620_L2CR, "L2CR",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 0x00000000);
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205}
a750fc0b 2206#endif /* defined (TARGET_PPC64) */
76a66253 2207
80d11f44 2208static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2209{
80d11f44
JM		 2210 /* Exception processing */
2211 spr_register(env, SPR_DSISR, "DSISR",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 spr_register(env, SPR_DAR, "DAR",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* Timer */
2220 spr_register(env, SPR_DECR, "DECR",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_decr, &spr_write_decr,
2223 0x00000000);
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_MPC_EIE, "EIE",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_MPC_EID, "EID",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_NRI, "NRI",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_CMPA, "CMPA",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_CMPB, "CMPB",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_CMPC, "CMPC",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_CMPD, "CMPD",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_ECR, "ECR",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_DER, "DER",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_CMPE, "CMPE",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_CMPF, "CMPF",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_CMPG, "CMPG",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_MPC_CMPH, "CMPH",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_MPC_BAR, "BAR",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_MPC_DPDR, "DPDR",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_MPC_IMMR, "IMMR",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324}
2325
2326static void gen_spr_5xx (CPUPPCState *env)
2327{
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433}
2434
2435static void gen_spr_8xx (CPUPPCState *env)
2436{
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 /* XXX : not implemented */
2548 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2549 SPR_NOACCESS, SPR_NOACCESS,
2550 &spr_read_generic, &spr_write_generic,
2551 0x00000000);
2552 /* XXX : not implemented */
2553 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2554 SPR_NOACCESS, SPR_NOACCESS,
2555 &spr_read_generic, &spr_write_generic,
2556 0x00000000);
2557 /* XXX : not implemented */
2558 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2559 SPR_NOACCESS, SPR_NOACCESS,
2560 &spr_read_generic, &spr_write_generic,
2561 0x00000000);
2562}
2563
2564// XXX: TODO
2565/*
2566 * AMR => SPR 29 (Power 2.04)
2567 * CTRL => SPR 136 (Power 2.04)
2568 * CTRL => SPR 152 (Power 2.04)
2569 * SCOMC => SPR 276 (64 bits ?)
2570 * SCOMD => SPR 277 (64 bits ?)
2571 * TBU40 => SPR 286 (Power 2.04 hypv)
2572 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2573 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2574 * HDSISR => SPR 306 (Power 2.04 hypv)
2575 * HDAR => SPR 307 (Power 2.04 hypv)
2576 * PURR => SPR 309 (Power 2.04 hypv)
2577 * HDEC => SPR 310 (Power 2.04 hypv)
2578 * HIOR => SPR 311 (hypv)
2579 * RMOR => SPR 312 (970)
2580 * HRMOR => SPR 313 (Power 2.04 hypv)
2581 * HSRR0 => SPR 314 (Power 2.04 hypv)
2582 * HSRR1 => SPR 315 (Power 2.04 hypv)
2583 * LPCR => SPR 316 (970)
2584 * LPIDR => SPR 317 (970)
80d11f44
JM		 2585 * EPR => SPR 702 (Power 2.04 emb)
2586 * perf => 768-783 (Power 2.04)
2587 * perf => 784-799 (Power 2.04)
2588 * PPR => SPR 896 (Power 2.04)
2589 * EPLC => SPR 947 (Power 2.04 emb)
2590 * EPSC => SPR 948 (Power 2.04 emb)
2591 * DABRX => 1015 (Power 2.04 hypv)
2592 * FPECR => SPR 1022 (?)
2593 * ... and more (thermal management, performance counters, ...)
2594 */
2595
2596/*****************************************************************************/
2597/* Exception vectors models */
2598static void init_excp_4xx_real (CPUPPCState *env)
2599{
2600#if !defined(CONFIG_USER_ONLY)
2601 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2602 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2603 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2604 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2605 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2606 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2607 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2608 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2609 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2610 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2611 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2612 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2613 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2614 /* Hardware reset vector */
2615 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2616#endif
2617}
2618
80d11f44
JM		 2619static void init_excp_4xx_softmmu (CPUPPCState *env)
2620{
2621#if !defined(CONFIG_USER_ONLY)
2622 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2623 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2624 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2625 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2626 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2627 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2628 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2629 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2630 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2631 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2632 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2633 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2634 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2635 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2636 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2637 env->ivor_mask = 0x0000FFF0UL;
2638 env->ivpr_mask = 0xFFFF0000UL;
2639 /* Hardware reset vector */
2640 env->hreset_vector = 0xFFFFFFFCUL;
2641#endif
2642}
2643
2644static void init_excp_MPC5xx (CPUPPCState *env)
2645{
2646#if !defined(CONFIG_USER_ONLY)
2647 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2648 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2649 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2650 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2651 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2652 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2653 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2654 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2655 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2656 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2657 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2658 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2659 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2660 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2661 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2662 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2663 env->ivor_mask = 0x0000FFF0UL;
2664 env->ivpr_mask = 0xFFFF0000UL;
2665 /* Hardware reset vector */
2666 env->hreset_vector = 0xFFFFFFFCUL;
2667#endif
2668}
2669
2670static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2671{
2672#if !defined(CONFIG_USER_ONLY)
2673 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2674 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2675 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2676 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2677 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2678 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2679 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2680 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2681 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2682 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2683 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2684 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2685 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2686 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2687 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2688 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2689 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2690 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2691 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2692 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2693 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2694 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2695 env->ivor_mask = 0x0000FFF0UL;
2696 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2697 /* Hardware reset vector */
80d11f44 2698 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2699#endif
2700}
2701
80d11f44 2702static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2703{
2704#if !defined(CONFIG_USER_ONLY)
2705 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2706 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2707 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2708 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2709 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2710 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2711 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2712 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2713 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2714 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2715 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2716 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2717 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2718 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2719 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2720 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2721 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2722 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2723 /* Hardware reset vector */
2724 env->hreset_vector = 0xFFFFFFFCUL;
2725#endif
2726}
2727
2728static void init_excp_e200 (CPUPPCState *env)
2729{
2730#if !defined(CONFIG_USER_ONLY)
2731 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2732 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2751 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2752 env->ivor_mask = 0x0000FFF7UL;
2753 env->ivpr_mask = 0xFFFF0000UL;
2754 /* Hardware reset vector */
2755 env->hreset_vector = 0xFFFFFFFCUL;
2756#endif
2757}
2758
2759static void init_excp_BookE (CPUPPCState *env)
2760{
2761#if !defined(CONFIG_USER_ONLY)
2762 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2763 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2764 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2765 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2772 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2773 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2774 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2775 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2776 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2777 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2778 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2779 env->ivor_mask = 0x0000FFE0UL;
2780 env->ivpr_mask = 0xFFFF0000UL;
2781 /* Hardware reset vector */
2782 env->hreset_vector = 0xFFFFFFFCUL;
2783#endif
2784}
2785
2786static void init_excp_601 (CPUPPCState *env)
2787{
2788#if !defined(CONFIG_USER_ONLY)
2789 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2790 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2791 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2792 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2793 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2794 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2795 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2796 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2797 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2798 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2799 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2800 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2801 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2802 /* Hardware reset vector */
80d11f44 2803 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2804#endif
2805}
2806
80d11f44 2807static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2808{
2809#if !defined(CONFIG_USER_ONLY)
082c6681 2810 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2811 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2819 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2820 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2821 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2822 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2823 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2824 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2825 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2826 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2827 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2828 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2829 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2830 /* Hardware reset vector */
2831 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2832#endif
2833}
2834
80d11f44 2835static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2836{
2837#if !defined(CONFIG_USER_ONLY)
2838 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2847 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2848 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2849 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2850 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2851 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2852 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2853 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2854 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2855 /* Hardware reset vector */
2856 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2857#endif
2858}
2859
2860static void init_excp_604 (CPUPPCState *env)
2861{
2862#if !defined(CONFIG_USER_ONLY)
2863 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2864 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2865 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2866 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2867 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2868 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2869 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2870 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2871 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2872 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2873 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2874 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2875 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2876 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2877 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2878 /* Hardware reset vector */
2d3eb7bf 2879 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2880#endif
2881}
2882
578bb252 2883#if defined(TARGET_PPC64)
e1833e1f
JM		 2884static void init_excp_620 (CPUPPCState *env)
2885{
2886#if !defined(CONFIG_USER_ONLY)
2887 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2888 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2889 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2890 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2891 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2892 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2893 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2894 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2895 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2896 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2897 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2898 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2899 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2900 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2901 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2902 /* Hardware reset vector */
faadf50e 2903 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2904#endif
2905}
578bb252 2906#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2907
2908static void init_excp_7x0 (CPUPPCState *env)
2909{
2910#if !defined(CONFIG_USER_ONLY)
2911 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2912 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2913 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2914 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2915 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2916 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2917 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2918 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2920 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2921 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2922 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2923 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 2924 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 2925 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 2926 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2927 /* Hardware reset vector */
2928 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2929#endif
2930}
2931
bd928eba 2932static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 2933{
2934#if !defined(CONFIG_USER_ONLY)
2935 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2936 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2937 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2938 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2939 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2940 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2941 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2942 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2943 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2944 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2945 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2946 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2947 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2948 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2949 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 2950 /* Hardware reset vector */
2951 env->hreset_vector = 0xFFFFFFFCUL;
2952#endif
2953}
2954
2955static void init_excp_750cx (CPUPPCState *env)
2956{
2957#if !defined(CONFIG_USER_ONLY)
2958 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2959 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2960 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2961 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2962 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2963 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2964 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2965 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2966 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2967 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2968 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2969 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2970 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 2971 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 2972 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2973 /* Hardware reset vector */
2974 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2975#endif
2976}
2977
7a3a6927
JM		 2978/* XXX: Check if this is correct */
2979static void init_excp_7x5 (CPUPPCState *env)
2980{
2981#if !defined(CONFIG_USER_ONLY)
2982 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2983 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2984 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2985 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2986 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2987 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2988 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2989 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2990 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2991 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2992 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 2993 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 2994 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2995 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2996 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 2997 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2998 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 2999 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3000 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3001 /* Hardware reset vector */
3002 env->hreset_vector = 0xFFFFFFFCUL;
3003#endif
3004}
3005
e1833e1f
JM		 3006static void init_excp_7400 (CPUPPCState *env)
3007{
3008#if !defined(CONFIG_USER_ONLY)
3009 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3010 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3011 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3012 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3018 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3019 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3020 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3021 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3022 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3023 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3024 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3025 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3026 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3027 /* Hardware reset vector */
3028 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3029#endif
3030}
3031
e1833e1f
JM		 3032static void init_excp_7450 (CPUPPCState *env)
3033{
3034#if !defined(CONFIG_USER_ONLY)
3035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3038 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3044 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3045 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3046 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3047 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3048 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3049 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3050 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3053 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3054 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3055 /* Hardware reset vector */
3056 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3057#endif
3058}
e1833e1f
JM		 3059
3060#if defined (TARGET_PPC64)
3061static void init_excp_970 (CPUPPCState *env)
3062{
3063#if !defined(CONFIG_USER_ONLY)
3064 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3065 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3066 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3067 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3068 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3069 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3070 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3071 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3072 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3073 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3074 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3075 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3076 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3077 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3078 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3079 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3080 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3081 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3082 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3083 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3084 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3085 /* Hardware reset vector */
3086 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3087#endif
3088}
3089#endif
3090
2f462816
JM		 3091/*****************************************************************************/
3092/* Power management enable checks */
3093static int check_pow_none (CPUPPCState *env)
3094{
3095 return 0;
3096}
3097
3098static int check_pow_nocheck (CPUPPCState *env)
3099{
3100 return 1;
3101}
3102
3103static int check_pow_hid0 (CPUPPCState *env)
3104{
3105 if (env->spr[SPR_HID0] & 0x00E00000)
3106 return 1;
3107
3108 return 0;
3109}
3110
4e777442
JM		 3111static int check_pow_hid0_74xx (CPUPPCState *env)
3112{
3113 if (env->spr[SPR_HID0] & 0x00600000)
3114 return 1;
3115
3116 return 0;
3117}
3118
a750fc0b
JM		 3119/*****************************************************************************/
3120/* PowerPC implementations definitions */
76a66253 3121
a750fc0b 3122/* PowerPC 401 */
082c6681
JM		 3123#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3124 PPC_WRTEE | PPC_DCR | \
3125 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3126 PPC_CACHE_DCBZ | \
a750fc0b 3127 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3128 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3129#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3130#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3131#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3132#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3133#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3134#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3135 POWERPC_FLAG_BUS_CLK)
2f462816 3136#define check_pow_401 check_pow_nocheck
76a66253 3137
a750fc0b
JM		 3138static void init_proc_401 (CPUPPCState *env)
3139{
3140 gen_spr_40x(env);
3141 gen_spr_401_403(env);
3142 gen_spr_401(env);
e1833e1f 3143 init_excp_4xx_real(env);
d63001d1
JM		 3144 env->dcache_line_size = 32;
3145 env->icache_line_size = 32;
4e290a0b
JM		 3146 /* Allocate hardware IRQ controller */
3147 ppc40x_irq_init(env);
a750fc0b 3148}
76a66253 3149
a750fc0b 3150/* PowerPC 401x2 */
082c6681
JM		 3151#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3152 PPC_DCR | PPC_WRTEE | \
3153 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3154 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3155 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3156 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3157 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3158#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3159#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3160#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3161#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3162#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3163#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3164 POWERPC_FLAG_BUS_CLK)
2f462816 3165#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3166
3167static void init_proc_401x2 (CPUPPCState *env)
3168{
3169 gen_spr_40x(env);
3170 gen_spr_401_403(env);
3171 gen_spr_401x2(env);
3172 gen_spr_compress(env);
a750fc0b 3173 /* Memory management */
f2e63a42 3174#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3175 env->nb_tlb = 64;
3176 env->nb_ways = 1;
3177 env->id_tlbs = 0;
f2e63a42 3178#endif
e1833e1f 3179 init_excp_4xx_softmmu(env);
d63001d1
JM		 3180 env->dcache_line_size = 32;
3181 env->icache_line_size = 32;
4e290a0b
JM		 3182 /* Allocate hardware IRQ controller */
3183 ppc40x_irq_init(env);
76a66253
JM		 3184}
3185
a750fc0b 3186/* PowerPC 401x3 */
082c6681
JM		 3187#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3188 PPC_DCR | PPC_WRTEE | \
3189 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3190 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3191 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3192 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3193 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3194#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3195#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3196#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3197#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3198#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3199#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3200 POWERPC_FLAG_BUS_CLK)
2f462816 3201#define check_pow_401x3 check_pow_nocheck
a750fc0b 3202
578bb252 3203__attribute__ (( unused ))
e1833e1f 3204static void init_proc_401x3 (CPUPPCState *env)
76a66253 3205{
4e290a0b
JM		 3206 gen_spr_40x(env);
3207 gen_spr_401_403(env);
3208 gen_spr_401(env);
3209 gen_spr_401x2(env);
3210 gen_spr_compress(env);
e1833e1f 3211 init_excp_4xx_softmmu(env);
d63001d1
JM		 3212 env->dcache_line_size = 32;
3213 env->icache_line_size = 32;
4e290a0b
JM		 3214 /* Allocate hardware IRQ controller */
3215 ppc40x_irq_init(env);
3fc6c082 3216}
a750fc0b
JM		 3217
3218/* IOP480 */
082c6681
JM		 3219#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3220 PPC_DCR | PPC_WRTEE | \
3221 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3222 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3223 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3224 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3225 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3226#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3227#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3228#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3229#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3230#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3231#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3232 POWERPC_FLAG_BUS_CLK)
2f462816 3233#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3234
3235static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3236{
a750fc0b
JM		 3237 gen_spr_40x(env);
3238 gen_spr_401_403(env);
3239 gen_spr_401x2(env);
3240 gen_spr_compress(env);
a750fc0b 3241 /* Memory management */
f2e63a42 3242#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3243 env->nb_tlb = 64;
3244 env->nb_ways = 1;
3245 env->id_tlbs = 0;
f2e63a42 3246#endif
e1833e1f 3247 init_excp_4xx_softmmu(env);
d63001d1
JM		 3248 env->dcache_line_size = 32;
3249 env->icache_line_size = 32;
4e290a0b
JM		 3250 /* Allocate hardware IRQ controller */
3251 ppc40x_irq_init(env);
3fc6c082
FB		 3252}
3253
a750fc0b 3254/* PowerPC 403 */
082c6681
JM		 3255#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3256 PPC_DCR | PPC_WRTEE | \
3257 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3258 PPC_CACHE_DCBZ | \
a750fc0b 3259 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3260 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3261#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3262#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3263#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3264#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3265#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3266#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3267 POWERPC_FLAG_BUS_CLK)
2f462816 3268#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3269
3270static void init_proc_403 (CPUPPCState *env)
3fc6c082 3271{
a750fc0b
JM		 3272 gen_spr_40x(env);
3273 gen_spr_401_403(env);
3274 gen_spr_403(env);
3275 gen_spr_403_real(env);
e1833e1f 3276 init_excp_4xx_real(env);
d63001d1
JM		 3277 env->dcache_line_size = 32;
3278 env->icache_line_size = 32;
4e290a0b
JM		 3279 /* Allocate hardware IRQ controller */
3280 ppc40x_irq_init(env);
3fc6c082
FB		 3281}
3282
a750fc0b 3283/* PowerPC 403 GCX */
082c6681
JM		 3284#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3285 PPC_DCR | PPC_WRTEE | \
3286 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3287 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3288 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3289 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3290 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3291#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3292#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3293#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3294#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3295#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3296#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3297 POWERPC_FLAG_BUS_CLK)
2f462816 3298#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3299
3300static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3301{
a750fc0b
JM		 3302 gen_spr_40x(env);
3303 gen_spr_401_403(env);
3304 gen_spr_403(env);
3305 gen_spr_403_real(env);
3306 gen_spr_403_mmu(env);
3307 /* Bus access control */
035feb88 3308 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3309 spr_register(env, SPR_40x_SGR, "SGR",
3310 SPR_NOACCESS, SPR_NOACCESS,
3311 &spr_read_generic, &spr_write_generic,
3312 0xFFFFFFFF);
035feb88 3313 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3314 spr_register(env, SPR_40x_DCWR, "DCWR",
3315 SPR_NOACCESS, SPR_NOACCESS,
3316 &spr_read_generic, &spr_write_generic,
3317 0x00000000);
3318 /* Memory management */
f2e63a42 3319#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3320 env->nb_tlb = 64;
3321 env->nb_ways = 1;
3322 env->id_tlbs = 0;
f2e63a42 3323#endif
80d11f44
JM		 3324 init_excp_4xx_softmmu(env);
3325 env->dcache_line_size = 32;
3326 env->icache_line_size = 32;
3327 /* Allocate hardware IRQ controller */
3328 ppc40x_irq_init(env);
3329}
3330
3331/* PowerPC 405 */
082c6681
JM		 3332#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3333 PPC_DCR | PPC_WRTEE | \
3334 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3335 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3336 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3337 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3338 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
80d11f44
JM		 3339#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3340#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3341#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3342#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3343#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3344#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3345 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3346#define check_pow_405 check_pow_nocheck
3347
3348static void init_proc_405 (CPUPPCState *env)
3349{
3350 /* Time base */
3351 gen_tbl(env);
3352 gen_spr_40x(env);
3353 gen_spr_405(env);
3354 /* Bus access control */
3355 /* not emulated, as Qemu never does speculative access */
3356 spr_register(env, SPR_40x_SGR, "SGR",
3357 SPR_NOACCESS, SPR_NOACCESS,
3358 &spr_read_generic, &spr_write_generic,
3359 0xFFFFFFFF);
3360 /* not emulated, as Qemu do not emulate caches */
3361 spr_register(env, SPR_40x_DCWR, "DCWR",
3362 SPR_NOACCESS, SPR_NOACCESS,
3363 &spr_read_generic, &spr_write_generic,
3364 0x00000000);
3365 /* Memory management */
3366#if !defined(CONFIG_USER_ONLY)
3367 env->nb_tlb = 64;
3368 env->nb_ways = 1;
3369 env->id_tlbs = 0;
3370#endif
3371 init_excp_4xx_softmmu(env);
3372 env->dcache_line_size = 32;
3373 env->icache_line_size = 32;
3374 /* Allocate hardware IRQ controller */
3375 ppc40x_irq_init(env);
3376}
3377
3378/* PowerPC 440 EP */
082c6681
JM		 3379#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3380 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3381 PPC_CACHE | PPC_CACHE_ICBI | \
3382 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3383 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3384 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3385 PPC_440_SPEC)
80d11f44
JM		 3386#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3387#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3388#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3389#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3390#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3391#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3392 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3393#define check_pow_440EP check_pow_nocheck
3394
3395__attribute__ (( unused ))
3396static void init_proc_440EP (CPUPPCState *env)
3397{
3398 /* Time base */
3399 gen_tbl(env);
3400 gen_spr_BookE(env, 0x000000000000FFFFULL);
3401 gen_spr_440(env);
3402 gen_spr_usprgh(env);
3403 /* Processor identification */
3404 spr_register(env, SPR_BOOKE_PIR, "PIR",
3405 SPR_NOACCESS, SPR_NOACCESS,
3406 &spr_read_generic, &spr_write_pir,
3407 0x00000000);
3408 /* XXX : not implemented */
3409 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0x00000000);
3413 /* XXX : not implemented */
3414 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 /* XXX : not implemented */
3419 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3420 SPR_NOACCESS, SPR_NOACCESS,
3421 &spr_read_generic, &spr_write_generic,
3422 0x00000000);
3423 /* XXX : not implemented */
3424 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3425 SPR_NOACCESS, SPR_NOACCESS,
3426 &spr_read_generic, &spr_write_generic,
3427 0x00000000);
3428 /* XXX : not implemented */
3429 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3430 SPR_NOACCESS, SPR_NOACCESS,
3431 &spr_read_generic, &spr_write_generic,
3432 0x00000000);
3433 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3434 SPR_NOACCESS, SPR_NOACCESS,
3435 &spr_read_generic, &spr_write_generic,
3436 0x00000000);
3437 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3438 SPR_NOACCESS, SPR_NOACCESS,
3439 &spr_read_generic, &spr_write_generic,
3440 0x00000000);
3441 /* XXX : not implemented */
3442 spr_register(env, SPR_440_CCR1, "CCR1",
3443 SPR_NOACCESS, SPR_NOACCESS,
3444 &spr_read_generic, &spr_write_generic,
3445 0x00000000);
3446 /* Memory management */
3447#if !defined(CONFIG_USER_ONLY)
3448 env->nb_tlb = 64;
3449 env->nb_ways = 1;
3450 env->id_tlbs = 0;
3451#endif
3452 init_excp_BookE(env);
3453 env->dcache_line_size = 32;
3454 env->icache_line_size = 32;
3455 /* XXX: TODO: allocate internal IRQ controller */
3456}
3457
3458/* PowerPC 440 GP */
082c6681
JM		 3459#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3460 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3461 PPC_CACHE | PPC_CACHE_ICBI | \
3462 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3463 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
082c6681
JM		 3464 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3465 PPC_440_SPEC)
80d11f44
JM		 3466#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3467#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3468#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3469#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3470#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3471#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3472 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3473#define check_pow_440GP check_pow_nocheck
3474
3475__attribute__ (( unused ))
3476static void init_proc_440GP (CPUPPCState *env)
3477{
3478 /* Time base */
3479 gen_tbl(env);
3480 gen_spr_BookE(env, 0x000000000000FFFFULL);
3481 gen_spr_440(env);
3482 gen_spr_usprgh(env);
3483 /* Processor identification */
3484 spr_register(env, SPR_BOOKE_PIR, "PIR",
3485 SPR_NOACCESS, SPR_NOACCESS,
3486 &spr_read_generic, &spr_write_pir,
3487 0x00000000);
3488 /* XXX : not implemented */
3489 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3490 SPR_NOACCESS, SPR_NOACCESS,
3491 &spr_read_generic, &spr_write_generic,
3492 0x00000000);
3493 /* XXX : not implemented */
3494 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3495 SPR_NOACCESS, SPR_NOACCESS,
3496 &spr_read_generic, &spr_write_generic,
3497 0x00000000);
3498 /* XXX : not implemented */
3499 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3500 SPR_NOACCESS, SPR_NOACCESS,
3501 &spr_read_generic, &spr_write_generic,
3502 0x00000000);
3503 /* XXX : not implemented */
3504 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3505 SPR_NOACCESS, SPR_NOACCESS,
3506 &spr_read_generic, &spr_write_generic,
3507 0x00000000);
3508 /* Memory management */
3509#if !defined(CONFIG_USER_ONLY)
3510 env->nb_tlb = 64;
3511 env->nb_ways = 1;
3512 env->id_tlbs = 0;
3513#endif
3514 init_excp_BookE(env);
3515 env->dcache_line_size = 32;
3516 env->icache_line_size = 32;
3517 /* XXX: TODO: allocate internal IRQ controller */
3518}
3519
3520/* PowerPC 440x4 */
082c6681
JM		 3521#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3522 PPC_DCR | PPC_WRTEE | \
3523 PPC_CACHE | PPC_CACHE_ICBI | \
3524 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3525 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44
JM		 3526 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3527 PPC_440_SPEC)
3528#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3529#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3530#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3531#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3532#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3533#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3534 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3535#define check_pow_440x4 check_pow_nocheck
3536
3537__attribute__ (( unused ))
3538static void init_proc_440x4 (CPUPPCState *env)
3539{
3540 /* Time base */
3541 gen_tbl(env);
3542 gen_spr_BookE(env, 0x000000000000FFFFULL);
3543 gen_spr_440(env);
3544 gen_spr_usprgh(env);
3545 /* Processor identification */
3546 spr_register(env, SPR_BOOKE_PIR, "PIR",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_pir,
3549 0x00000000);
3550 /* XXX : not implemented */
3551 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3552 SPR_NOACCESS, SPR_NOACCESS,
3553 &spr_read_generic, &spr_write_generic,
3554 0x00000000);
3555 /* XXX : not implemented */
3556 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3557 SPR_NOACCESS, SPR_NOACCESS,
3558 &spr_read_generic, &spr_write_generic,
3559 0x00000000);
3560 /* XXX : not implemented */
3561 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3562 SPR_NOACCESS, SPR_NOACCESS,
3563 &spr_read_generic, &spr_write_generic,
3564 0x00000000);
3565 /* XXX : not implemented */
3566 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3567 SPR_NOACCESS, SPR_NOACCESS,
3568 &spr_read_generic, &spr_write_generic,
3569 0x00000000);
3570 /* Memory management */
3571#if !defined(CONFIG_USER_ONLY)
3572 env->nb_tlb = 64;
3573 env->nb_ways = 1;
3574 env->id_tlbs = 0;
3575#endif
3576 init_excp_BookE(env);
d63001d1
JM		 3577 env->dcache_line_size = 32;
3578 env->icache_line_size = 32;
80d11f44 3579 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3580}
3581
80d11f44 3582/* PowerPC 440x5 */
082c6681
JM		 3583#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3584 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3585 PPC_CACHE | PPC_CACHE_ICBI | \
3586 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3587 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3588 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3589 PPC_440_SPEC)
80d11f44
JM		 3590#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3591#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3592#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3593#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3594#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3595#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3596 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3597#define check_pow_440x5 check_pow_nocheck
a750fc0b 3598
80d11f44 3599static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3600{
a750fc0b
JM		 3601 /* Time base */
3602 gen_tbl(env);
80d11f44
JM		 3603 gen_spr_BookE(env, 0x000000000000FFFFULL);
3604 gen_spr_440(env);
3605 gen_spr_usprgh(env);
3606 /* Processor identification */
3607 spr_register(env, SPR_BOOKE_PIR, "PIR",
3608 SPR_NOACCESS, SPR_NOACCESS,
3609 &spr_read_generic, &spr_write_pir,
3610 0x00000000);
3611 /* XXX : not implemented */
3612 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3613 SPR_NOACCESS, SPR_NOACCESS,
3614 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3615 0x00000000);
3616 /* XXX : not implemented */
3617 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3618 SPR_NOACCESS, SPR_NOACCESS,
3619 &spr_read_generic, &spr_write_generic,
3620 0x00000000);
3621 /* XXX : not implemented */
3622 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3623 SPR_NOACCESS, SPR_NOACCESS,
3624 &spr_read_generic, &spr_write_generic,
3625 0x00000000);
3626 /* XXX : not implemented */
3627 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3628 SPR_NOACCESS, SPR_NOACCESS,
3629 &spr_read_generic, &spr_write_generic,
3630 0x00000000);
3631 /* XXX : not implemented */
3632 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_generic,
3635 0x00000000);
3636 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3637 SPR_NOACCESS, SPR_NOACCESS,
3638 &spr_read_generic, &spr_write_generic,
3639 0x00000000);
3640 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* Memory management */
f2e63a42 3650#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3651 env->nb_tlb = 64;
3652 env->nb_ways = 1;
3653 env->id_tlbs = 0;
f2e63a42 3654#endif
80d11f44 3655 init_excp_BookE(env);
d63001d1
JM		 3656 env->dcache_line_size = 32;
3657 env->icache_line_size = 32;
95070372 3658 ppc40x_irq_init(env);
3fc6c082
FB		 3659}
3660
80d11f44 3661/* PowerPC 460 (guessed) */
082c6681 3662#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3663 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
f4078236 3664 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
082c6681
JM		 3665 PPC_CACHE | PPC_CACHE_ICBI | \
3666 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3667 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3668 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3669 PPC_440_SPEC)
80d11f44
JM		 3670#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3671#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3672#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3673#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3674#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3675#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3676 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3677#define check_pow_460 check_pow_nocheck
a750fc0b 3678
80d11f44
JM		 3679__attribute__ (( unused ))
3680static void init_proc_460 (CPUPPCState *env)
3fc6c082 3681{
a750fc0b
JM		 3682 /* Time base */
3683 gen_tbl(env);
80d11f44 3684 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3685 gen_spr_440(env);
80d11f44
JM		 3686 gen_spr_usprgh(env);
3687 /* Processor identification */
3688 spr_register(env, SPR_BOOKE_PIR, "PIR",
3689 SPR_NOACCESS, SPR_NOACCESS,
3690 &spr_read_generic, &spr_write_pir,
3691 0x00000000);
3692 /* XXX : not implemented */
3693 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3694 SPR_NOACCESS, SPR_NOACCESS,
3695 &spr_read_generic, &spr_write_generic,
3696 0x00000000);
3697 /* XXX : not implemented */
3698 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_generic,
3701 0x00000000);
3702 /* XXX : not implemented */
3703 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 /* XXX : not implemented */
3708 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, &spr_write_generic,
3711 0x00000000);
578bb252 3712 /* XXX : not implemented */
a750fc0b
JM		 3713 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3718 SPR_NOACCESS, SPR_NOACCESS,
3719 &spr_read_generic, &spr_write_generic,
3720 0x00000000);
3721 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3722 SPR_NOACCESS, SPR_NOACCESS,
3723 &spr_read_generic, &spr_write_generic,
3724 0x00000000);
578bb252 3725 /* XXX : not implemented */
a750fc0b
JM		 3726 spr_register(env, SPR_440_CCR1, "CCR1",
3727 SPR_NOACCESS, SPR_NOACCESS,
3728 &spr_read_generic, &spr_write_generic,
3729 0x00000000);
80d11f44
JM		 3730 /* XXX : not implemented */
3731 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3732 &spr_read_generic, &spr_write_generic,
3733 &spr_read_generic, &spr_write_generic,
3734 0x00000000);
a750fc0b 3735 /* Memory management */
f2e63a42 3736#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3737 env->nb_tlb = 64;
3738 env->nb_ways = 1;
3739 env->id_tlbs = 0;
f2e63a42 3740#endif
e1833e1f 3741 init_excp_BookE(env);
d63001d1
JM		 3742 env->dcache_line_size = 32;
3743 env->icache_line_size = 32;
a750fc0b 3744 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3745}
3746
80d11f44 3747/* PowerPC 460F (guessed) */
082c6681
JM		 3748#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3749 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3750 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
f4078236 3751 PPC_FLOAT_STFIWX | PPC_MFTB | \
082c6681
JM		 3752 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3753 PPC_WRTEE | PPC_MFAPIDI | \
3754 PPC_CACHE | PPC_CACHE_ICBI | \
3755 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3756 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3757 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3758 PPC_440_SPEC)
80d11f44
JM		 3759#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3760#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3761#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3762#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3763#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3764#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3765 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3766#define check_pow_460F check_pow_nocheck
a750fc0b 3767
80d11f44
JM		 3768__attribute__ (( unused ))
3769static void init_proc_460F (CPUPPCState *env)
3fc6c082 3770{
a750fc0b
JM		 3771 /* Time base */
3772 gen_tbl(env);
80d11f44 3773 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3774 gen_spr_440(env);
80d11f44
JM		 3775 gen_spr_usprgh(env);
3776 /* Processor identification */
3777 spr_register(env, SPR_BOOKE_PIR, "PIR",
3778 SPR_NOACCESS, SPR_NOACCESS,
3779 &spr_read_generic, &spr_write_pir,
3780 0x00000000);
3781 /* XXX : not implemented */
3782 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3783 SPR_NOACCESS, SPR_NOACCESS,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 /* XXX : not implemented */
3792 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3793 SPR_NOACCESS, SPR_NOACCESS,
3794 &spr_read_generic, &spr_write_generic,
3795 0x00000000);
3796 /* XXX : not implemented */
3797 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_generic,
3800 0x00000000);
3801 /* XXX : not implemented */
3802 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3811 SPR_NOACCESS, SPR_NOACCESS,
3812 &spr_read_generic, &spr_write_generic,
3813 0x00000000);
3814 /* XXX : not implemented */
3815 spr_register(env, SPR_440_CCR1, "CCR1",
3816 SPR_NOACCESS, SPR_NOACCESS,
3817 &spr_read_generic, &spr_write_generic,
3818 0x00000000);
3819 /* XXX : not implemented */
3820 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3821 &spr_read_generic, &spr_write_generic,
3822 &spr_read_generic, &spr_write_generic,
3823 0x00000000);
a750fc0b 3824 /* Memory management */
f2e63a42 3825#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3826 env->nb_tlb = 64;
3827 env->nb_ways = 1;
3828 env->id_tlbs = 0;
f2e63a42 3829#endif
e1833e1f 3830 init_excp_BookE(env);
d63001d1
JM		 3831 env->dcache_line_size = 32;
3832 env->icache_line_size = 32;
a750fc0b 3833 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3834}
3835
80d11f44
JM		 3836/* Freescale 5xx cores (aka RCPU) */
3837#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3838 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3839 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3840 PPC_MFTB)
3841#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3842#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3843#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3844#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3845#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3846#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3847 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3848#define check_pow_MPC5xx check_pow_none
3849
3850__attribute__ (( unused ))
3851static void init_proc_MPC5xx (CPUPPCState *env)
3852{
3853 /* Time base */
3854 gen_tbl(env);
3855 gen_spr_5xx_8xx(env);
3856 gen_spr_5xx(env);
3857 init_excp_MPC5xx(env);
3858 env->dcache_line_size = 32;
3859 env->icache_line_size = 32;
3860 /* XXX: TODO: allocate internal IRQ controller */
3861}
3862
3863/* Freescale 8xx cores (aka PowerQUICC) */
3864#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3865 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3866 PPC_CACHE_ICBI | PPC_MFTB)
3867#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3868#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3869#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3870#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3871#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3872#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3873 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3874#define check_pow_MPC8xx check_pow_none
3875
3876__attribute__ (( unused ))
3877static void init_proc_MPC8xx (CPUPPCState *env)
3878{
3879 /* Time base */
3880 gen_tbl(env);
3881 gen_spr_5xx_8xx(env);
3882 gen_spr_8xx(env);
3883 init_excp_MPC8xx(env);
3884 env->dcache_line_size = 32;
3885 env->icache_line_size = 32;
3886 /* XXX: TODO: allocate internal IRQ controller */
3887}
3888
3889/* Freescale 82xx cores (aka PowerQUICC-II) */
3890/* PowerPC G2 */
082c6681
JM		 3891#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3892 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3893 PPC_FLOAT_STFIWX | \
3894 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3895 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3896 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3897 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3898#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3899#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3900//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3901#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3902#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3903#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3904 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3905#define check_pow_G2 check_pow_hid0
a750fc0b 3906
80d11f44 3907static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3908{
80d11f44
JM		 3909 gen_spr_ne_601(env);
3910 gen_spr_G2_755(env);
3911 gen_spr_G2(env);
a750fc0b
JM		 3912 /* Time base */
3913 gen_tbl(env);
bd928eba
JM		 3914 /* External access control */
3915 /* XXX : not implemented */
3916 spr_register(env, SPR_EAR, "EAR",
3917 SPR_NOACCESS, SPR_NOACCESS,
3918 &spr_read_generic, &spr_write_generic,
3919 0x00000000);
80d11f44
JM		 3920 /* Hardware implementation register */
3921 /* XXX : not implemented */
3922 spr_register(env, SPR_HID0, "HID0",
3923 SPR_NOACCESS, SPR_NOACCESS,
3924 &spr_read_generic, &spr_write_generic,
3925 0x00000000);
3926 /* XXX : not implemented */
3927 spr_register(env, SPR_HID1, "HID1",
3928 SPR_NOACCESS, SPR_NOACCESS,
3929 &spr_read_generic, &spr_write_generic,
3930 0x00000000);
3931 /* XXX : not implemented */
3932 spr_register(env, SPR_HID2, "HID2",
3933 SPR_NOACCESS, SPR_NOACCESS,
3934 &spr_read_generic, &spr_write_generic,
3935 0x00000000);
a750fc0b 3936 /* Memory management */
80d11f44
JM		 3937 gen_low_BATs(env);
3938 gen_high_BATs(env);
3939 gen_6xx_7xx_soft_tlb(env, 64, 2);
3940 init_excp_G2(env);
d63001d1
JM		 3941 env->dcache_line_size = 32;
3942 env->icache_line_size = 32;
80d11f44
JM		 3943 /* Allocate hardware IRQ controller */
3944 ppc6xx_irq_init(env);
3fc6c082 3945}
a750fc0b 3946
80d11f44 3947/* PowerPC G2LE */
082c6681
JM		 3948#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3949 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3950 PPC_FLOAT_STFIWX | \
3951 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3952 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3953 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3954 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3955#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3956#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3957#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3958#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3959#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3960#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3961 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3962#define check_pow_G2LE check_pow_hid0
a750fc0b 3963
80d11f44 3964static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3965{
80d11f44
JM		 3966 gen_spr_ne_601(env);
3967 gen_spr_G2_755(env);
3968 gen_spr_G2(env);
a750fc0b
JM		 3969 /* Time base */
3970 gen_tbl(env);
bd928eba
JM		 3971 /* External access control */
3972 /* XXX : not implemented */
3973 spr_register(env, SPR_EAR, "EAR",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
80d11f44 3977 /* Hardware implementation register */
578bb252 3978 /* XXX : not implemented */
80d11f44 3979 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, &spr_write_generic,
3982 0x00000000);
80d11f44
JM		 3983 /* XXX : not implemented */
3984 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
578bb252 3988 /* XXX : not implemented */
80d11f44 3989 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* Memory management */
80d11f44
JM		 3994 gen_low_BATs(env);
3995 gen_high_BATs(env);
3996 gen_6xx_7xx_soft_tlb(env, 64, 2);
3997 init_excp_G2(env);
d63001d1
JM		 3998 env->dcache_line_size = 32;
3999 env->icache_line_size = 32;
80d11f44
JM		 4000 /* Allocate hardware IRQ controller */
4001 ppc6xx_irq_init(env);
3fc6c082
FB		 4002}
4003
80d11f44
JM		 4004/* e200 core */
4005/* XXX: unimplemented instructions:
4006 * dcblc
4007 * dcbtlst
4008 * dcbtstls
4009 * icblc
4010 * icbtls
4011 * tlbivax
4012 * all SPE multiply-accumulate instructions
4013 */
082c6681 4014#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4015 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4016 PPC_WRTEE | PPC_RFDI | \
4017 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4018 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4019 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4020 PPC_BOOKE)
80d11f44
JM		 4021#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4022#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
4023#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4024#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4025#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4026#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4027 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4028 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4029#define check_pow_e200 check_pow_hid0
4030
578bb252 4031__attribute__ (( unused ))
80d11f44 4032static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4033{
e1833e1f
JM		 4034 /* Time base */
4035 gen_tbl(env);
80d11f44 4036 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4037 /* XXX : not implemented */
80d11f44 4038 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4039 &spr_read_spefscr, &spr_write_spefscr,
4040 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4041 0x00000000);
80d11f44
JM		 4042 /* Memory management */
4043 gen_spr_BookE_FSL(env, 0x0000005D);
4044 /* XXX : not implemented */
4045 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4046 SPR_NOACCESS, SPR_NOACCESS,
4047 &spr_read_generic, &spr_write_generic,
4048 0x00000000);
80d11f44
JM		 4049 /* XXX : not implemented */
4050 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4051 SPR_NOACCESS, SPR_NOACCESS,
4052 &spr_read_generic, &spr_write_generic,
4053 0x00000000);
578bb252 4054 /* XXX : not implemented */
80d11f44 4055 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4056 SPR_NOACCESS, SPR_NOACCESS,
4057 &spr_read_generic, &spr_write_generic,
4058 0x00000000);
578bb252 4059 /* XXX : not implemented */
80d11f44
JM		 4060 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4061 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4062 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4063 0x00000000);
4064 /* XXX : not implemented */
4065 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, &spr_write_generic,
4068 0x00000000);
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000);
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* XXX : not implemented */
4080 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4081 SPR_NOACCESS, SPR_NOACCESS,
4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
4084 /* XXX : not implemented */
4085 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4086 SPR_NOACCESS, SPR_NOACCESS,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 /* XXX : not implemented */
4090 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 /* XXX : not implemented */
4095 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_generic,
4098 0x00000000);
4099 /* XXX : not implemented */
4100 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4101 SPR_NOACCESS, SPR_NOACCESS,
4102 &spr_read_generic, &spr_write_generic,
4103 0x00000000);
4104 /* XXX : not implemented */
4105 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4106 SPR_NOACCESS, SPR_NOACCESS,
4107 &spr_read_generic, &spr_write_generic,
4108 0x00000000);
4109 /* XXX : not implemented */
4110 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4111 SPR_NOACCESS, SPR_NOACCESS,
4112 &spr_read_generic, &spr_write_generic,
4113 0x00000000);
4114 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_generic,
4117 0x00000000);
4118 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4119 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
f2e63a42 4122#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4123 env->nb_tlb = 64;
4124 env->nb_ways = 1;
4125 env->id_tlbs = 0;
f2e63a42 4126#endif
80d11f44 4127 init_excp_e200(env);
d63001d1
JM		 4128 env->dcache_line_size = 32;
4129 env->icache_line_size = 32;
e1833e1f 4130 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4131}
a750fc0b 4132
80d11f44 4133/* e300 core */
082c6681
JM		 4134#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4135 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4136 PPC_FLOAT_STFIWX | \
4137 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4138 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4139 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4140 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4141#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4142#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4143#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4144#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4145#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4146#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4147 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4148#define check_pow_e300 check_pow_hid0
a750fc0b 4149
578bb252 4150__attribute__ (( unused ))
80d11f44 4151static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4152{
80d11f44
JM		 4153 gen_spr_ne_601(env);
4154 gen_spr_603(env);
a750fc0b
JM		 4155 /* Time base */
4156 gen_tbl(env);
80d11f44
JM		 4157 /* hardware implementation registers */
4158 /* XXX : not implemented */
4159 spr_register(env, SPR_HID0, "HID0",
4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
4163 /* XXX : not implemented */
4164 spr_register(env, SPR_HID1, "HID1",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
8daf1781
TM		 4168 /* XXX : not implemented */
4169 spr_register(env, SPR_HID2, "HID2",
4170 SPR_NOACCESS, SPR_NOACCESS,
4171 &spr_read_generic, &spr_write_generic,
4172 0x00000000);
80d11f44
JM		 4173 /* Memory management */
4174 gen_low_BATs(env);
8daf1781 4175 gen_high_BATs(env);
80d11f44
JM		 4176 gen_6xx_7xx_soft_tlb(env, 64, 2);
4177 init_excp_603(env);
4178 env->dcache_line_size = 32;
4179 env->icache_line_size = 32;
4180 /* Allocate hardware IRQ controller */
4181 ppc6xx_irq_init(env);
4182}
4183
bd5ea513
AJ		 4184/* e500v1 core */
4185#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4186 PPC_SPE | PPC_SPE_SINGLE | \
4187 PPC_WRTEE | PPC_RFDI | \
4188 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4189 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4190 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4191 PPC_BOOKE)
4192#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4193#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
4194#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4195#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4196#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4197#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4198 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4199 POWERPC_FLAG_BUS_CLK)
4200#define check_pow_e500v1 check_pow_hid0
4201#define init_proc_e500v1 init_proc_e500
4202
4203/* e500v2 core */
4204#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4205 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4206 PPC_WRTEE | PPC_RFDI | \
4207 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4208 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4209 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4210 PPC_BOOKE)
4211#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4212#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
4213#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4214#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4215#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4216#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4217 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4218 POWERPC_FLAG_BUS_CLK)
4219#define check_pow_e500v2 check_pow_hid0
4220#define init_proc_e500v2 init_proc_e500
80d11f44 4221
80d11f44
JM		 4222static void init_proc_e500 (CPUPPCState *env)
4223{
4224 /* Time base */
4225 gen_tbl(env);
4226 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4227 /* Processor identification */
4228 spr_register(env, SPR_BOOKE_PIR, "PIR",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_pir,
4231 0x00000000);
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4234 &spr_read_spefscr, &spr_write_spefscr,
4235 &spr_read_spefscr, &spr_write_spefscr,
80d11f44
JM		 4236 0x00000000);
4237 /* Memory management */
4238#if !defined(CONFIG_USER_ONLY)
4239 env->nb_pids = 3;
4240#endif
4241 gen_spr_BookE_FSL(env, 0x0000005F);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_HID0, "HID0",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
4247 /* XXX : not implemented */
4248 spr_register(env, SPR_HID1, "HID1",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
4252 /* XXX : not implemented */
4253 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4254 SPR_NOACCESS, SPR_NOACCESS,
4255 &spr_read_generic, &spr_write_generic,
4256 0x00000000);
4257 /* XXX : not implemented */
4258 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4259 SPR_NOACCESS, SPR_NOACCESS,
4260 &spr_read_generic, &spr_write_generic,
4261 0x00000000);
4262 /* XXX : not implemented */
4263 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4264 SPR_NOACCESS, SPR_NOACCESS,
4265 &spr_read_generic, &spr_write_generic,
4266 0x00000000);
578bb252 4267 /* XXX : not implemented */
a750fc0b
JM		 4268 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, &spr_write_generic,
4271 0x00000000);
80d11f44
JM		 4272 /* XXX : not implemented */
4273 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
80d11f44
JM		 4277 /* XXX : not implemented */
4278 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
578bb252 4282 /* XXX : not implemented */
80d11f44 4283 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
578bb252 4287 /* XXX : not implemented */
80d11f44
JM		 4288 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4289 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4290 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4291 0x00000000);
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 /* XXX : not implemented */
4298 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302 /* XXX : not implemented */
4303 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4304 SPR_NOACCESS, SPR_NOACCESS,
4305 &spr_read_generic, &spr_write_generic,
4306 0x00000000);
4307 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4308 SPR_NOACCESS, SPR_NOACCESS,
4309 &spr_read_generic, &spr_write_generic,
4310 0x00000000);
4311 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4312 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4313 &spr_read_generic, &spr_write_generic,
4314 0x00000000);
f2e63a42 4315#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4316 env->nb_tlb = 64;
4317 env->nb_ways = 1;
4318 env->id_tlbs = 0;
f2e63a42 4319#endif
80d11f44 4320 init_excp_e200(env);
d63001d1
JM		 4321 env->dcache_line_size = 32;
4322 env->icache_line_size = 32;
9fdc60bf
AJ		 4323 /* Allocate hardware IRQ controller */
4324 ppce500_irq_init(env);
3fc6c082 4325}
a750fc0b 4326
a750fc0b 4327/* Non-embedded PowerPC */
a750fc0b
JM		 4328
4329/* POWER : same as 601, without mfmsr, mfsr */
4330#if defined(TODO)
4331#define POWERPC_INSNS_POWER (XXX_TODO)
4332/* POWER RSC (from RAD6000) */
4333#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4334#endif /* TODO */
4335
4336/* PowerPC 601 */
082c6681
JM		 4337#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4338 PPC_FLOAT | \
4339 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4340 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4341 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4342#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4343#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4344//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4345//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4346#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4347#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4348#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4349#define check_pow_601 check_pow_none
a750fc0b
JM		 4350
4351static void init_proc_601 (CPUPPCState *env)
3fc6c082 4352{
a750fc0b
JM		 4353 gen_spr_ne_601(env);
4354 gen_spr_601(env);
4355 /* Hardware implementation registers */
4356 /* XXX : not implemented */
4357 spr_register(env, SPR_HID0, "HID0",
4358 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4359 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4360 0x80010080);
a750fc0b
JM		 4361 /* XXX : not implemented */
4362 spr_register(env, SPR_HID1, "HID1",
4363 SPR_NOACCESS, SPR_NOACCESS,
4364 &spr_read_generic, &spr_write_generic,
4365 0x00000000);
4366 /* XXX : not implemented */
4367 spr_register(env, SPR_601_HID2, "HID2",
4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_601_HID5, "HID5",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
a750fc0b 4376 /* Memory management */
e1833e1f 4377 init_excp_601(env);
082c6681
JM		 4378 /* XXX: beware that dcache line size is 64
4379 * but dcbz uses 32 bytes "sectors"
4380 * XXX: this breaks clcs instruction !
4381 */
4382 env->dcache_line_size = 32;
d63001d1 4383 env->icache_line_size = 64;
faadf50e
JM		 4384 /* Allocate hardware IRQ controller */
4385 ppc6xx_irq_init(env);
3fc6c082
FB		 4386}
4387
082c6681
JM		 4388/* PowerPC 601v */
4389#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4390 PPC_FLOAT | \
4391 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4392 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4393 PPC_SEGMENT | PPC_EXTERN)
4394#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4395#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4396#define POWERPC_MMU_601v (POWERPC_MMU_601)
4397#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4398#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4399#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4400#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4401#define check_pow_601v check_pow_none
4402
4403static void init_proc_601v (CPUPPCState *env)
4404{
4405 init_proc_601(env);
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_601_HID15, "HID15",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 0x00000000);
4411}
4412
a750fc0b 4413/* PowerPC 602 */
082c6681
JM		 4414#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4415 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4416 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4417 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4418 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4419 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4420 PPC_SEGMENT | PPC_602_SPEC)
082c6681
JM		 4421#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4422/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4423#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4424//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4425#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4426#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4427#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4428 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4429#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4430
4431static void init_proc_602 (CPUPPCState *env)
3fc6c082 4432{
a750fc0b
JM		 4433 gen_spr_ne_601(env);
4434 gen_spr_602(env);
4435 /* Time base */
4436 gen_tbl(env);
4437 /* hardware implementation registers */
4438 /* XXX : not implemented */
4439 spr_register(env, SPR_HID0, "HID0",
4440 SPR_NOACCESS, SPR_NOACCESS,
4441 &spr_read_generic, &spr_write_generic,
4442 0x00000000);
4443 /* XXX : not implemented */
4444 spr_register(env, SPR_HID1, "HID1",
4445 SPR_NOACCESS, SPR_NOACCESS,
4446 &spr_read_generic, &spr_write_generic,
4447 0x00000000);
4448 /* Memory management */
4449 gen_low_BATs(env);
4450 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4451 init_excp_602(env);
d63001d1
JM		 4452 env->dcache_line_size = 32;
4453 env->icache_line_size = 32;
a750fc0b
JM		 4454 /* Allocate hardware IRQ controller */
4455 ppc6xx_irq_init(env);
4456}
3fc6c082 4457
a750fc0b 4458/* PowerPC 603 */
082c6681
JM		 4459#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4460 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4461 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4462 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4463 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4464 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4465 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4466#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4467#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4468//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4469#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4470#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4471#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4472 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4473#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4474
4475static void init_proc_603 (CPUPPCState *env)
4476{
4477 gen_spr_ne_601(env);
4478 gen_spr_603(env);
4479 /* Time base */
4480 gen_tbl(env);
4481 /* hardware implementation registers */
4482 /* XXX : not implemented */
4483 spr_register(env, SPR_HID0, "HID0",
4484 SPR_NOACCESS, SPR_NOACCESS,
4485 &spr_read_generic, &spr_write_generic,
4486 0x00000000);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_HID1, "HID1",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* Memory management */
4493 gen_low_BATs(env);
4494 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4495 init_excp_603(env);
d63001d1
JM		 4496 env->dcache_line_size = 32;
4497 env->icache_line_size = 32;
a750fc0b
JM		 4498 /* Allocate hardware IRQ controller */
4499 ppc6xx_irq_init(env);
3fc6c082
FB		 4500}
4501
a750fc0b 4502/* PowerPC 603e */
082c6681
JM		 4503#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4504 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4505 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4506 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4507 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4508 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4509 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4510#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4511#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4512//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4513#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4514#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4515#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4516 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4517#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4518
4519static void init_proc_603E (CPUPPCState *env)
4520{
4521 gen_spr_ne_601(env);
4522 gen_spr_603(env);
4523 /* Time base */
4524 gen_tbl(env);
4525 /* hardware implementation registers */
4526 /* XXX : not implemented */
4527 spr_register(env, SPR_HID0, "HID0",
4528 SPR_NOACCESS, SPR_NOACCESS,
4529 &spr_read_generic, &spr_write_generic,
4530 0x00000000);
4531 /* XXX : not implemented */
4532 spr_register(env, SPR_HID1, "HID1",
4533 SPR_NOACCESS, SPR_NOACCESS,
4534 &spr_read_generic, &spr_write_generic,
4535 0x00000000);
4536 /* XXX : not implemented */
4537 spr_register(env, SPR_IABR, "IABR",
4538 SPR_NOACCESS, SPR_NOACCESS,
4539 &spr_read_generic, &spr_write_generic,
4540 0x00000000);
4541 /* Memory management */
4542 gen_low_BATs(env);
4543 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4544 init_excp_603(env);
d63001d1
JM		 4545 env->dcache_line_size = 32;
4546 env->icache_line_size = 32;
a750fc0b
JM		 4547 /* Allocate hardware IRQ controller */
4548 ppc6xx_irq_init(env);
4549}
4550
a750fc0b 4551/* PowerPC 604 */
082c6681
JM		 4552#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4553 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4554 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4555 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4556 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4557 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4558 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4559#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4560#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4561//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4562#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4563#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4564#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4565 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4566#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4567
4568static void init_proc_604 (CPUPPCState *env)
4569{
4570 gen_spr_ne_601(env);
4571 gen_spr_604(env);
4572 /* Time base */
4573 gen_tbl(env);
4574 /* Hardware implementation registers */
4575 /* XXX : not implemented */
082c6681
JM		 4576 spr_register(env, SPR_HID0, "HID0",
4577 SPR_NOACCESS, SPR_NOACCESS,
4578 &spr_read_generic, &spr_write_generic,
4579 0x00000000);
4580 /* Memory management */
4581 gen_low_BATs(env);
4582 init_excp_604(env);
4583 env->dcache_line_size = 32;
4584 env->icache_line_size = 32;
4585 /* Allocate hardware IRQ controller */
4586 ppc6xx_irq_init(env);
4587}
4588
4589/* PowerPC 604E */
4590#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4591 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4592 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4593 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4594 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4595 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4596 PPC_SEGMENT | PPC_EXTERN)
4597#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4598#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4599#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4600#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4601#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4602#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4603 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4604#define check_pow_604E check_pow_nocheck
4605
4606static void init_proc_604E (CPUPPCState *env)
4607{
4608 gen_spr_ne_601(env);
4609 gen_spr_604(env);
4610 /* XXX : not implemented */
4611 spr_register(env, SPR_MMCR1, "MMCR1",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
4615 /* XXX : not implemented */
4616 spr_register(env, SPR_PMC3, "PMC3",
4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
4620 /* XXX : not implemented */
4621 spr_register(env, SPR_PMC4, "PMC4",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
4625 /* Time base */
4626 gen_tbl(env);
4627 /* Hardware implementation registers */
4628 /* XXX : not implemented */
a750fc0b
JM		 4629 spr_register(env, SPR_HID0, "HID0",
4630 SPR_NOACCESS, SPR_NOACCESS,
4631 &spr_read_generic, &spr_write_generic,
4632 0x00000000);
4633 /* XXX : not implemented */
4634 spr_register(env, SPR_HID1, "HID1",
4635 SPR_NOACCESS, SPR_NOACCESS,
4636 &spr_read_generic, &spr_write_generic,
4637 0x00000000);
4638 /* Memory management */
4639 gen_low_BATs(env);
e1833e1f 4640 init_excp_604(env);
d63001d1
JM		 4641 env->dcache_line_size = 32;
4642 env->icache_line_size = 32;
a750fc0b
JM		 4643 /* Allocate hardware IRQ controller */
4644 ppc6xx_irq_init(env);
4645}
4646
bd928eba
JM		 4647/* PowerPC 740 */
4648#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4649 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4650 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4651 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4652 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4653 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4654 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 4655#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4656#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4657#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4658#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4659#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4660#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4661 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4662#define check_pow_740 check_pow_hid0
a750fc0b 4663
bd928eba 4664static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4665{
4666 gen_spr_ne_601(env);
4667 gen_spr_7xx(env);
4668 /* Time base */
4669 gen_tbl(env);
4670 /* Thermal management */
4671 gen_spr_thrm(env);
4672 /* Hardware implementation registers */
4673 /* XXX : not implemented */
4674 spr_register(env, SPR_HID0, "HID0",
4675 SPR_NOACCESS, SPR_NOACCESS,
4676 &spr_read_generic, &spr_write_generic,
4677 0x00000000);
4678 /* XXX : not implemented */
4679 spr_register(env, SPR_HID1, "HID1",
4680 SPR_NOACCESS, SPR_NOACCESS,
4681 &spr_read_generic, &spr_write_generic,
4682 0x00000000);
4683 /* Memory management */
4684 gen_low_BATs(env);
e1833e1f 4685 init_excp_7x0(env);
d63001d1
JM		 4686 env->dcache_line_size = 32;
4687 env->icache_line_size = 32;
a750fc0b
JM		 4688 /* Allocate hardware IRQ controller */
4689 ppc6xx_irq_init(env);
4690}
4691
bd928eba
JM		 4692/* PowerPC 750 */
4693#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4694 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4695 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4696 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4697 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4698 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4699 PPC_SEGMENT | PPC_EXTERN)
4700#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4701#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4702#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4703#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4704#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4705#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4706 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4707#define check_pow_750 check_pow_hid0
4708
4709static void init_proc_750 (CPUPPCState *env)
4710{
4711 gen_spr_ne_601(env);
4712 gen_spr_7xx(env);
4713 /* XXX : not implemented */
4714 spr_register(env, SPR_L2CR, "L2CR",
4715 SPR_NOACCESS, SPR_NOACCESS,
4716 &spr_read_generic, &spr_write_generic,
4717 0x00000000);
4718 /* Time base */
4719 gen_tbl(env);
4720 /* Thermal management */
4721 gen_spr_thrm(env);
4722 /* Hardware implementation registers */
4723 /* XXX : not implemented */
4724 spr_register(env, SPR_HID0, "HID0",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_generic,
4727 0x00000000);
4728 /* XXX : not implemented */
4729 spr_register(env, SPR_HID1, "HID1",
4730 SPR_NOACCESS, SPR_NOACCESS,
4731 &spr_read_generic, &spr_write_generic,
4732 0x00000000);
4733 /* Memory management */
4734 gen_low_BATs(env);
4735 /* XXX: high BATs are also present but are known to be bugged on
4736 * die version 1.x
4737 */
4738 init_excp_7x0(env);
4739 env->dcache_line_size = 32;
4740 env->icache_line_size = 32;
4741 /* Allocate hardware IRQ controller */
4742 ppc6xx_irq_init(env);
4743}
4744
4745/* PowerPC 750 CL */
4746/* XXX: not implemented:
4747 * cache lock instructions:
4748 * dcbz_l
4749 * floating point paired instructions
4750 * psq_lux
4751 * psq_lx
4752 * psq_stux
4753 * psq_stx
4754 * ps_abs
4755 * ps_add
4756 * ps_cmpo0
4757 * ps_cmpo1
4758 * ps_cmpu0
4759 * ps_cmpu1
4760 * ps_div
4761 * ps_madd
4762 * ps_madds0
4763 * ps_madds1
4764 * ps_merge00
4765 * ps_merge01
4766 * ps_merge10
4767 * ps_merge11
4768 * ps_mr
4769 * ps_msub
4770 * ps_mul
4771 * ps_muls0
4772 * ps_muls1
4773 * ps_nabs
4774 * ps_neg
4775 * ps_nmadd
4776 * ps_nmsub
4777 * ps_res
4778 * ps_rsqrte
4779 * ps_sel
4780 * ps_sub
4781 * ps_sum0
4782 * ps_sum1
4783 */
4784#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4785 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4786 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4787 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4788 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4789 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4790 PPC_SEGMENT | PPC_EXTERN)
4791#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4792#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4793#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4794#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4795#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4796#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4797 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4798#define check_pow_750cl check_pow_hid0
4799
4800static void init_proc_750cl (CPUPPCState *env)
4801{
4802 gen_spr_ne_601(env);
4803 gen_spr_7xx(env);
4804 /* XXX : not implemented */
4805 spr_register(env, SPR_L2CR, "L2CR",
4806 SPR_NOACCESS, SPR_NOACCESS,
4807 &spr_read_generic, &spr_write_generic,
4808 0x00000000);
4809 /* Time base */
4810 gen_tbl(env);
4811 /* Thermal management */
4812 /* Those registers are fake on 750CL */
4813 spr_register(env, SPR_THRM1, "THRM1",
4814 SPR_NOACCESS, SPR_NOACCESS,
4815 &spr_read_generic, &spr_write_generic,
4816 0x00000000);
4817 spr_register(env, SPR_THRM2, "THRM2",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 spr_register(env, SPR_THRM3, "THRM3",
4822 SPR_NOACCESS, SPR_NOACCESS,
4823 &spr_read_generic, &spr_write_generic,
4824 0x00000000);
4825 /* XXX: not implemented */
4826 spr_register(env, SPR_750_TDCL, "TDCL",
4827 SPR_NOACCESS, SPR_NOACCESS,
4828 &spr_read_generic, &spr_write_generic,
4829 0x00000000);
4830 spr_register(env, SPR_750_TDCH, "TDCH",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* DMA */
4835 /* XXX : not implemented */
4836 spr_register(env, SPR_750_WPAR, "WPAR",
4837 SPR_NOACCESS, SPR_NOACCESS,
4838 &spr_read_generic, &spr_write_generic,
4839 0x00000000);
4840 spr_register(env, SPR_750_DMAL, "DMAL",
4841 SPR_NOACCESS, SPR_NOACCESS,
4842 &spr_read_generic, &spr_write_generic,
4843 0x00000000);
4844 spr_register(env, SPR_750_DMAU, "DMAU",
4845 SPR_NOACCESS, SPR_NOACCESS,
4846 &spr_read_generic, &spr_write_generic,
4847 0x00000000);
4848 /* Hardware implementation registers */
4849 /* XXX : not implemented */
4850 spr_register(env, SPR_HID0, "HID0",
4851 SPR_NOACCESS, SPR_NOACCESS,
4852 &spr_read_generic, &spr_write_generic,
4853 0x00000000);
4854 /* XXX : not implemented */
4855 spr_register(env, SPR_HID1, "HID1",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 /* XXX : not implemented */
4860 spr_register(env, SPR_750CL_HID2, "HID2",
4861 SPR_NOACCESS, SPR_NOACCESS,
4862 &spr_read_generic, &spr_write_generic,
4863 0x00000000);
4864 /* XXX : not implemented */
4865 spr_register(env, SPR_750CL_HID4, "HID4",
4866 SPR_NOACCESS, SPR_NOACCESS,
4867 &spr_read_generic, &spr_write_generic,
4868 0x00000000);
4869 /* Quantization registers */
4870 /* XXX : not implemented */
4871 spr_register(env, SPR_750_GQR0, "GQR0",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 /* XXX : not implemented */
4876 spr_register(env, SPR_750_GQR1, "GQR1",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 /* XXX : not implemented */
4881 spr_register(env, SPR_750_GQR2, "GQR2",
4882 SPR_NOACCESS, SPR_NOACCESS,
4883 &spr_read_generic, &spr_write_generic,
4884 0x00000000);
4885 /* XXX : not implemented */
4886 spr_register(env, SPR_750_GQR3, "GQR3",
4887 SPR_NOACCESS, SPR_NOACCESS,
4888 &spr_read_generic, &spr_write_generic,
4889 0x00000000);
4890 /* XXX : not implemented */
4891 spr_register(env, SPR_750_GQR4, "GQR4",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_generic,
4894 0x00000000);
4895 /* XXX : not implemented */
4896 spr_register(env, SPR_750_GQR5, "GQR5",
4897 SPR_NOACCESS, SPR_NOACCESS,
4898 &spr_read_generic, &spr_write_generic,
4899 0x00000000);
4900 /* XXX : not implemented */
4901 spr_register(env, SPR_750_GQR6, "GQR6",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 /* XXX : not implemented */
4906 spr_register(env, SPR_750_GQR7, "GQR7",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910 /* Memory management */
4911 gen_low_BATs(env);
4912 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4913 gen_high_BATs(env);
4914 init_excp_750cl(env);
4915 env->dcache_line_size = 32;
4916 env->icache_line_size = 32;
4917 /* Allocate hardware IRQ controller */
4918 ppc6xx_irq_init(env);
4919}
4920
4e777442 4921/* PowerPC 750CX */
bd928eba
JM		 4922#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4923 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4924 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4925 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4926 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4927 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4928 PPC_SEGMENT | PPC_EXTERN)
4929#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4930#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4931#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4932#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4933#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4934#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4935 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4936#define check_pow_750cx check_pow_hid0
4937
4938static void init_proc_750cx (CPUPPCState *env)
4939{
4940 gen_spr_ne_601(env);
4941 gen_spr_7xx(env);
4942 /* XXX : not implemented */
4943 spr_register(env, SPR_L2CR, "L2CR",
4944 SPR_NOACCESS, SPR_NOACCESS,
4945 &spr_read_generic, &spr_write_generic,
4946 0x00000000);
4947 /* Time base */
4948 gen_tbl(env);
4949 /* Thermal management */
4950 gen_spr_thrm(env);
4951 /* This register is not implemented but is present for compatibility */
4952 spr_register(env, SPR_SDA, "SDA",
4953 SPR_NOACCESS, SPR_NOACCESS,
4954 &spr_read_generic, &spr_write_generic,
4955 0x00000000);
4956 /* Hardware implementation registers */
4957 /* XXX : not implemented */
4958 spr_register(env, SPR_HID0, "HID0",
4959 SPR_NOACCESS, SPR_NOACCESS,
4960 &spr_read_generic, &spr_write_generic,
4961 0x00000000);
4962 /* XXX : not implemented */
4963 spr_register(env, SPR_HID1, "HID1",
4964 SPR_NOACCESS, SPR_NOACCESS,
4965 &spr_read_generic, &spr_write_generic,
4966 0x00000000);
4967 /* Memory management */
4968 gen_low_BATs(env);
4e777442
JM		 4969 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4970 gen_high_BATs(env);
bd928eba
JM		 4971 init_excp_750cx(env);
4972 env->dcache_line_size = 32;
4973 env->icache_line_size = 32;
4974 /* Allocate hardware IRQ controller */
4975 ppc6xx_irq_init(env);
4976}
4977
4978/* PowerPC 750FX */
082c6681
JM		 4979#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4980 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4981 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4982 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4983 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4984 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4985 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4986#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4987#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4988#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4989#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4990#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 4991#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4992 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4993#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4994
4995static void init_proc_750fx (CPUPPCState *env)
4996{
4997 gen_spr_ne_601(env);
4998 gen_spr_7xx(env);
bd928eba
JM		 4999 /* XXX : not implemented */
5000 spr_register(env, SPR_L2CR, "L2CR",
5001 SPR_NOACCESS, SPR_NOACCESS,
5002 &spr_read_generic, &spr_write_generic,
5003 0x00000000);
a750fc0b
JM		 5004 /* Time base */
5005 gen_tbl(env);
5006 /* Thermal management */
5007 gen_spr_thrm(env);
bd928eba
JM		 5008 /* XXX : not implemented */
5009 spr_register(env, SPR_750_THRM4, "THRM4",
5010 SPR_NOACCESS, SPR_NOACCESS,
5011 &spr_read_generic, &spr_write_generic,
5012 0x00000000);
a750fc0b
JM		 5013 /* Hardware implementation registers */
5014 /* XXX : not implemented */
5015 spr_register(env, SPR_HID0, "HID0",
5016 SPR_NOACCESS, SPR_NOACCESS,
5017 &spr_read_generic, &spr_write_generic,
5018 0x00000000);
5019 /* XXX : not implemented */
5020 spr_register(env, SPR_HID1, "HID1",
5021 SPR_NOACCESS, SPR_NOACCESS,
5022 &spr_read_generic, &spr_write_generic,
5023 0x00000000);
5024 /* XXX : not implemented */
bd928eba 5025 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5026 SPR_NOACCESS, SPR_NOACCESS,
5027 &spr_read_generic, &spr_write_generic,
5028 0x00000000);
5029 /* Memory management */
5030 gen_low_BATs(env);
5031 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5032 gen_high_BATs(env);
bd928eba 5033 init_excp_7x0(env);
d63001d1
JM		 5034 env->dcache_line_size = 32;
5035 env->icache_line_size = 32;
a750fc0b
JM		 5036 /* Allocate hardware IRQ controller */
5037 ppc6xx_irq_init(env);
5038}
5039
bd928eba
JM		 5040/* PowerPC 750GX */
5041#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5042 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5043 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5044 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5045 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5046 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5047 PPC_SEGMENT | PPC_EXTERN)
5048#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5049#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5050#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5051#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5052#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5053#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5054 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5055#define check_pow_750gx check_pow_hid0
5056
5057static void init_proc_750gx (CPUPPCState *env)
5058{
5059 gen_spr_ne_601(env);
5060 gen_spr_7xx(env);
5061 /* XXX : not implemented (XXX: different from 750fx) */
5062 spr_register(env, SPR_L2CR, "L2CR",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 /* Time base */
5067 gen_tbl(env);
5068 /* Thermal management */
5069 gen_spr_thrm(env);
5070 /* XXX : not implemented */
5071 spr_register(env, SPR_750_THRM4, "THRM4",
5072 SPR_NOACCESS, SPR_NOACCESS,
5073 &spr_read_generic, &spr_write_generic,
5074 0x00000000);
5075 /* Hardware implementation registers */
5076 /* XXX : not implemented (XXX: different from 750fx) */
5077 spr_register(env, SPR_HID0, "HID0",
5078 SPR_NOACCESS, SPR_NOACCESS,
5079 &spr_read_generic, &spr_write_generic,
5080 0x00000000);
5081 /* XXX : not implemented */
5082 spr_register(env, SPR_HID1, "HID1",
5083 SPR_NOACCESS, SPR_NOACCESS,
5084 &spr_read_generic, &spr_write_generic,
5085 0x00000000);
5086 /* XXX : not implemented (XXX: different from 750fx) */
5087 spr_register(env, SPR_750FX_HID2, "HID2",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_generic,
5090 0x00000000);
5091 /* Memory management */
5092 gen_low_BATs(env);
5093 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5094 gen_high_BATs(env);
5095 init_excp_7x0(env);
5096 env->dcache_line_size = 32;
5097 env->icache_line_size = 32;
5098 /* Allocate hardware IRQ controller */
5099 ppc6xx_irq_init(env);
5100}
5101
5102/* PowerPC 745 */
5103#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5104 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5105 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5106 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5107 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5108 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5109 PPC_SEGMENT | PPC_EXTERN)
5110#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5111#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5112#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5113#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5114#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5115#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5116 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5117#define check_pow_745 check_pow_hid0
5118
5119static void init_proc_745 (CPUPPCState *env)
5120{
5121 gen_spr_ne_601(env);
5122 gen_spr_7xx(env);
5123 gen_spr_G2_755(env);
5124 /* Time base */
5125 gen_tbl(env);
5126 /* Thermal management */
5127 gen_spr_thrm(env);
5128 /* Hardware implementation registers */
5129 /* XXX : not implemented */
5130 spr_register(env, SPR_HID0, "HID0",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, &spr_write_generic,
5133 0x00000000);
5134 /* XXX : not implemented */
5135 spr_register(env, SPR_HID1, "HID1",
5136 SPR_NOACCESS, SPR_NOACCESS,
5137 &spr_read_generic, &spr_write_generic,
5138 0x00000000);
5139 /* XXX : not implemented */
5140 spr_register(env, SPR_HID2, "HID2",
5141 SPR_NOACCESS, SPR_NOACCESS,
5142 &spr_read_generic, &spr_write_generic,
5143 0x00000000);
5144 /* Memory management */
5145 gen_low_BATs(env);
5146 gen_high_BATs(env);
5147 gen_6xx_7xx_soft_tlb(env, 64, 2);
5148 init_excp_7x5(env);
5149 env->dcache_line_size = 32;
5150 env->icache_line_size = 32;
5151 /* Allocate hardware IRQ controller */
5152 ppc6xx_irq_init(env);
5153}
5154
5155/* PowerPC 755 */
5156#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5157 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5158 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5159 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5160 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5161 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5162 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 5163#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5164#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5165#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5166#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5167#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5168#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5169 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5170#define check_pow_755 check_pow_hid0
a750fc0b 5171
bd928eba 5172static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5173{
5174 gen_spr_ne_601(env);
bd928eba 5175 gen_spr_7xx(env);
a750fc0b
JM		 5176 gen_spr_G2_755(env);
5177 /* Time base */
5178 gen_tbl(env);
5179 /* L2 cache control */
5180 /* XXX : not implemented */
bd928eba 5181 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5182 SPR_NOACCESS, SPR_NOACCESS,
5183 &spr_read_generic, &spr_write_generic,
5184 0x00000000);
5185 /* XXX : not implemented */
5186 spr_register(env, SPR_L2PMCR, "L2PMCR",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_generic,
5189 0x00000000);
bd928eba
JM		 5190 /* Thermal management */
5191 gen_spr_thrm(env);
a750fc0b
JM		 5192 /* Hardware implementation registers */
5193 /* XXX : not implemented */
5194 spr_register(env, SPR_HID0, "HID0",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_generic, &spr_write_generic,
5197 0x00000000);
5198 /* XXX : not implemented */
5199 spr_register(env, SPR_HID1, "HID1",
5200 SPR_NOACCESS, SPR_NOACCESS,
5201 &spr_read_generic, &spr_write_generic,
5202 0x00000000);
5203 /* XXX : not implemented */
5204 spr_register(env, SPR_HID2, "HID2",
5205 SPR_NOACCESS, SPR_NOACCESS,
5206 &spr_read_generic, &spr_write_generic,
5207 0x00000000);
5208 /* Memory management */
5209 gen_low_BATs(env);
5210 gen_high_BATs(env);
5211 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5212 init_excp_7x5(env);
d63001d1
JM		 5213 env->dcache_line_size = 32;
5214 env->icache_line_size = 32;
a750fc0b
JM		 5215 /* Allocate hardware IRQ controller */
5216 ppc6xx_irq_init(env);
5217}
5218
5219/* PowerPC 7400 (aka G4) */
082c6681
JM		 5220#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5221 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5222 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5223 PPC_FLOAT_STFIWX | \
5224 PPC_CACHE | PPC_CACHE_ICBI | \
5225 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5226 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5227 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5228 PPC_MEM_TLBIA | \
5229 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5230 PPC_ALTIVEC)
5231#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5232#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5233#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5234#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5235#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5236#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5237 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5238 POWERPC_FLAG_BUS_CLK)
488243b0 5239#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 5240
5241static void init_proc_7400 (CPUPPCState *env)
5242{
5243 gen_spr_ne_601(env);
5244 gen_spr_7xx(env);
5245 /* Time base */
5246 gen_tbl(env);
5247 /* 74xx specific SPR */
5248 gen_spr_74xx(env);
4e777442
JM		 5249 /* XXX : not implemented */
5250 spr_register(env, SPR_UBAMR, "UBAMR",
5251 &spr_read_ureg, SPR_NOACCESS,
5252 &spr_read_ureg, SPR_NOACCESS,
5253 0x00000000);
5254 /* XXX: this seems not implemented on all revisions. */
5255 /* XXX : not implemented */
5256 spr_register(env, SPR_MSSCR1, "MSSCR1",
5257 SPR_NOACCESS, SPR_NOACCESS,
5258 &spr_read_generic, &spr_write_generic,
5259 0x00000000);
a750fc0b
JM		 5260 /* Thermal management */
5261 gen_spr_thrm(env);
5262 /* Memory management */
5263 gen_low_BATs(env);
e1833e1f 5264 init_excp_7400(env);
d63001d1
JM		 5265 env->dcache_line_size = 32;
5266 env->icache_line_size = 32;
a750fc0b
JM		 5267 /* Allocate hardware IRQ controller */
5268 ppc6xx_irq_init(env);
5269}
5270
5271/* PowerPC 7410 (aka G4) */
082c6681
JM		 5272#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5273 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5274 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5275 PPC_FLOAT_STFIWX | \
5276 PPC_CACHE | PPC_CACHE_ICBI | \
5277 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5278 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5279 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5280 PPC_MEM_TLBIA | \
5281 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5282 PPC_ALTIVEC)
5283#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5284#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5285#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5286#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5287#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5288#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5289 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5290 POWERPC_FLAG_BUS_CLK)
488243b0 5291#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 5292
5293static void init_proc_7410 (CPUPPCState *env)
5294{
5295 gen_spr_ne_601(env);
5296 gen_spr_7xx(env);
5297 /* Time base */
5298 gen_tbl(env);
5299 /* 74xx specific SPR */
5300 gen_spr_74xx(env);
4e777442
JM		 5301 /* XXX : not implemented */
5302 spr_register(env, SPR_UBAMR, "UBAMR",
5303 &spr_read_ureg, SPR_NOACCESS,
5304 &spr_read_ureg, SPR_NOACCESS,
5305 0x00000000);
a750fc0b
JM		 5306 /* Thermal management */
5307 gen_spr_thrm(env);
5308 /* L2PMCR */
5309 /* XXX : not implemented */
5310 spr_register(env, SPR_L2PMCR, "L2PMCR",
5311 SPR_NOACCESS, SPR_NOACCESS,
5312 &spr_read_generic, &spr_write_generic,
5313 0x00000000);
5314 /* LDSTDB */
5315 /* XXX : not implemented */
5316 spr_register(env, SPR_LDSTDB, "LDSTDB",
5317 SPR_NOACCESS, SPR_NOACCESS,
5318 &spr_read_generic, &spr_write_generic,
5319 0x00000000);
5320 /* Memory management */
5321 gen_low_BATs(env);
e1833e1f 5322 init_excp_7400(env);
d63001d1
JM		 5323 env->dcache_line_size = 32;
5324 env->icache_line_size = 32;
a750fc0b
JM		 5325 /* Allocate hardware IRQ controller */
5326 ppc6xx_irq_init(env);
5327}
5328
5329/* PowerPC 7440 (aka G4) */
082c6681
JM		 5330#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5331 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5332 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5333 PPC_FLOAT_STFIWX | \
5334 PPC_CACHE | PPC_CACHE_ICBI | \
5335 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5336 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5337 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5338 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5339 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5340 PPC_ALTIVEC)
5341#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5342#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5343#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5344#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5345#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5346#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5347 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5348 POWERPC_FLAG_BUS_CLK)
4e777442 5349#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5350
578bb252 5351__attribute__ (( unused ))
a750fc0b
JM		 5352static void init_proc_7440 (CPUPPCState *env)
5353{
5354 gen_spr_ne_601(env);
5355 gen_spr_7xx(env);
5356 /* Time base */
5357 gen_tbl(env);
5358 /* 74xx specific SPR */
5359 gen_spr_74xx(env);
4e777442
JM		 5360 /* XXX : not implemented */
5361 spr_register(env, SPR_UBAMR, "UBAMR",
5362 &spr_read_ureg, SPR_NOACCESS,
5363 &spr_read_ureg, SPR_NOACCESS,
5364 0x00000000);
a750fc0b
JM		 5365 /* LDSTCR */
5366 /* XXX : not implemented */
5367 spr_register(env, SPR_LDSTCR, "LDSTCR",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, &spr_write_generic,
5370 0x00000000);
5371 /* ICTRL */
5372 /* XXX : not implemented */
5373 spr_register(env, SPR_ICTRL, "ICTRL",
5374 SPR_NOACCESS, SPR_NOACCESS,
5375 &spr_read_generic, &spr_write_generic,
5376 0x00000000);
5377 /* MSSSR0 */
578bb252 5378 /* XXX : not implemented */
a750fc0b
JM		 5379 spr_register(env, SPR_MSSSR0, "MSSSR0",
5380 SPR_NOACCESS, SPR_NOACCESS,
5381 &spr_read_generic, &spr_write_generic,
5382 0x00000000);
5383 /* PMC */
5384 /* XXX : not implemented */
5385 spr_register(env, SPR_PMC5, "PMC5",
5386 SPR_NOACCESS, SPR_NOACCESS,
5387 &spr_read_generic, &spr_write_generic,
5388 0x00000000);
578bb252 5389 /* XXX : not implemented */
a750fc0b
JM		 5390 spr_register(env, SPR_UPMC5, "UPMC5",
5391 &spr_read_ureg, SPR_NOACCESS,
5392 &spr_read_ureg, SPR_NOACCESS,
5393 0x00000000);
578bb252 5394 /* XXX : not implemented */
a750fc0b
JM		 5395 spr_register(env, SPR_PMC6, "PMC6",
5396 SPR_NOACCESS, SPR_NOACCESS,
5397 &spr_read_generic, &spr_write_generic,
5398 0x00000000);
578bb252 5399 /* XXX : not implemented */
a750fc0b
JM		 5400 spr_register(env, SPR_UPMC6, "UPMC6",
5401 &spr_read_ureg, SPR_NOACCESS,
5402 &spr_read_ureg, SPR_NOACCESS,
5403 0x00000000);
5404 /* Memory management */
5405 gen_low_BATs(env);
578bb252 5406 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5407 init_excp_7450(env);
d63001d1
JM		 5408 env->dcache_line_size = 32;
5409 env->icache_line_size = 32;
a750fc0b
JM		 5410 /* Allocate hardware IRQ controller */
5411 ppc6xx_irq_init(env);
5412}
a750fc0b
JM		 5413
5414/* PowerPC 7450 (aka G4) */
082c6681
JM		 5415#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5416 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5417 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5418 PPC_FLOAT_STFIWX | \
5419 PPC_CACHE | PPC_CACHE_ICBI | \
5420 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5421 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5422 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5423 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5424 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5425 PPC_ALTIVEC)
5426#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5427#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5428#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5429#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5430#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5431#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5432 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5433 POWERPC_FLAG_BUS_CLK)
4e777442 5434#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5435
578bb252 5436__attribute__ (( unused ))
a750fc0b
JM		 5437static void init_proc_7450 (CPUPPCState *env)
5438{
5439 gen_spr_ne_601(env);
5440 gen_spr_7xx(env);
5441 /* Time base */
5442 gen_tbl(env);
5443 /* 74xx specific SPR */
5444 gen_spr_74xx(env);
5445 /* Level 3 cache control */
5446 gen_l3_ctrl(env);
4e777442
JM		 5447 /* L3ITCR1 */
5448 /* XXX : not implemented */
5449 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_write_generic,
5452 0x00000000);
5453 /* L3ITCR2 */
5454 /* XXX : not implemented */
5455 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5456 SPR_NOACCESS, SPR_NOACCESS,
5457 &spr_read_generic, &spr_write_generic,
5458 0x00000000);
5459 /* L3ITCR3 */
5460 /* XXX : not implemented */
5461 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 /* L3OHCR */
5466 /* XXX : not implemented */
5467 spr_register(env, SPR_L3OHCR, "L3OHCR",
5468 SPR_NOACCESS, SPR_NOACCESS,
5469 &spr_read_generic, &spr_write_generic,
5470 0x00000000);
5471 /* XXX : not implemented */
5472 spr_register(env, SPR_UBAMR, "UBAMR",
5473 &spr_read_ureg, SPR_NOACCESS,
5474 &spr_read_ureg, SPR_NOACCESS,
5475 0x00000000);
a750fc0b
JM		 5476 /* LDSTCR */
5477 /* XXX : not implemented */
5478 spr_register(env, SPR_LDSTCR, "LDSTCR",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* ICTRL */
5483 /* XXX : not implemented */
5484 spr_register(env, SPR_ICTRL, "ICTRL",
5485 SPR_NOACCESS, SPR_NOACCESS,
5486 &spr_read_generic, &spr_write_generic,
5487 0x00000000);
5488 /* MSSSR0 */
578bb252 5489 /* XXX : not implemented */
a750fc0b
JM		 5490 spr_register(env, SPR_MSSSR0, "MSSSR0",
5491 SPR_NOACCESS, SPR_NOACCESS,
5492 &spr_read_generic, &spr_write_generic,
5493 0x00000000);
5494 /* PMC */
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_PMC5, "PMC5",
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 &spr_read_generic, &spr_write_generic,
5499 0x00000000);
578bb252 5500 /* XXX : not implemented */
a750fc0b
JM		 5501 spr_register(env, SPR_UPMC5, "UPMC5",
5502 &spr_read_ureg, SPR_NOACCESS,
5503 &spr_read_ureg, SPR_NOACCESS,
5504 0x00000000);
578bb252 5505 /* XXX : not implemented */
a750fc0b
JM		 5506 spr_register(env, SPR_PMC6, "PMC6",
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 0x00000000);
578bb252 5510 /* XXX : not implemented */
a750fc0b
JM		 5511 spr_register(env, SPR_UPMC6, "UPMC6",
5512 &spr_read_ureg, SPR_NOACCESS,
5513 &spr_read_ureg, SPR_NOACCESS,
5514 0x00000000);
5515 /* Memory management */
5516 gen_low_BATs(env);
578bb252 5517 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5518 init_excp_7450(env);
d63001d1
JM		 5519 env->dcache_line_size = 32;
5520 env->icache_line_size = 32;
a750fc0b
JM		 5521 /* Allocate hardware IRQ controller */
5522 ppc6xx_irq_init(env);
5523}
a750fc0b
JM		 5524
5525/* PowerPC 7445 (aka G4) */
082c6681
JM		 5526#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5527 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5528 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5529 PPC_FLOAT_STFIWX | \
5530 PPC_CACHE | PPC_CACHE_ICBI | \
5531 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5532 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5533 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5534 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5535 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5536 PPC_ALTIVEC)
5537#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5538#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5539#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5540#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5541#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5542#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5543 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5544 POWERPC_FLAG_BUS_CLK)
4e777442 5545#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5546
578bb252 5547__attribute__ (( unused ))
a750fc0b
JM		 5548static void init_proc_7445 (CPUPPCState *env)
5549{
5550 gen_spr_ne_601(env);
5551 gen_spr_7xx(env);
5552 /* Time base */
5553 gen_tbl(env);
5554 /* 74xx specific SPR */
5555 gen_spr_74xx(env);
5556 /* LDSTCR */
5557 /* XXX : not implemented */
5558 spr_register(env, SPR_LDSTCR, "LDSTCR",
5559 SPR_NOACCESS, SPR_NOACCESS,
5560 &spr_read_generic, &spr_write_generic,
5561 0x00000000);
5562 /* ICTRL */
5563 /* XXX : not implemented */
5564 spr_register(env, SPR_ICTRL, "ICTRL",
5565 SPR_NOACCESS, SPR_NOACCESS,
5566 &spr_read_generic, &spr_write_generic,
5567 0x00000000);
5568 /* MSSSR0 */
578bb252 5569 /* XXX : not implemented */
a750fc0b
JM		 5570 spr_register(env, SPR_MSSSR0, "MSSSR0",
5571 SPR_NOACCESS, SPR_NOACCESS,
5572 &spr_read_generic, &spr_write_generic,
5573 0x00000000);
5574 /* PMC */
5575 /* XXX : not implemented */
5576 spr_register(env, SPR_PMC5, "PMC5",
5577 SPR_NOACCESS, SPR_NOACCESS,
5578 &spr_read_generic, &spr_write_generic,
5579 0x00000000);
578bb252 5580 /* XXX : not implemented */
a750fc0b
JM		 5581 spr_register(env, SPR_UPMC5, "UPMC5",
5582 &spr_read_ureg, SPR_NOACCESS,
5583 &spr_read_ureg, SPR_NOACCESS,
5584 0x00000000);
578bb252 5585 /* XXX : not implemented */
a750fc0b
JM		 5586 spr_register(env, SPR_PMC6, "PMC6",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 &spr_read_generic, &spr_write_generic,
5589 0x00000000);
578bb252 5590 /* XXX : not implemented */
a750fc0b
JM		 5591 spr_register(env, SPR_UPMC6, "UPMC6",
5592 &spr_read_ureg, SPR_NOACCESS,
5593 &spr_read_ureg, SPR_NOACCESS,
5594 0x00000000);
5595 /* SPRGs */
5596 spr_register(env, SPR_SPRG4, "SPRG4",
5597 SPR_NOACCESS, SPR_NOACCESS,
5598 &spr_read_generic, &spr_write_generic,
5599 0x00000000);
5600 spr_register(env, SPR_USPRG4, "USPRG4",
5601 &spr_read_ureg, SPR_NOACCESS,
5602 &spr_read_ureg, SPR_NOACCESS,
5603 0x00000000);
5604 spr_register(env, SPR_SPRG5, "SPRG5",
5605 SPR_NOACCESS, SPR_NOACCESS,
5606 &spr_read_generic, &spr_write_generic,
5607 0x00000000);
5608 spr_register(env, SPR_USPRG5, "USPRG5",
5609 &spr_read_ureg, SPR_NOACCESS,
5610 &spr_read_ureg, SPR_NOACCESS,
5611 0x00000000);
5612 spr_register(env, SPR_SPRG6, "SPRG6",
5613 SPR_NOACCESS, SPR_NOACCESS,
5614 &spr_read_generic, &spr_write_generic,
5615 0x00000000);
5616 spr_register(env, SPR_USPRG6, "USPRG6",
5617 &spr_read_ureg, SPR_NOACCESS,
5618 &spr_read_ureg, SPR_NOACCESS,
5619 0x00000000);
5620 spr_register(env, SPR_SPRG7, "SPRG7",
5621 SPR_NOACCESS, SPR_NOACCESS,
5622 &spr_read_generic, &spr_write_generic,
5623 0x00000000);
5624 spr_register(env, SPR_USPRG7, "USPRG7",
5625 &spr_read_ureg, SPR_NOACCESS,
5626 &spr_read_ureg, SPR_NOACCESS,
5627 0x00000000);
5628 /* Memory management */
5629 gen_low_BATs(env);
5630 gen_high_BATs(env);
578bb252 5631 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5632 init_excp_7450(env);
d63001d1
JM		 5633 env->dcache_line_size = 32;
5634 env->icache_line_size = 32;
a750fc0b
JM		 5635 /* Allocate hardware IRQ controller */
5636 ppc6xx_irq_init(env);
5637}
a750fc0b
JM		 5638
5639/* PowerPC 7455 (aka G4) */
082c6681
JM		 5640#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5641 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5642 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5643 PPC_FLOAT_STFIWX | \
5644 PPC_CACHE | PPC_CACHE_ICBI | \
5645 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5646 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5647 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5648 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5649 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5650 PPC_ALTIVEC)
5651#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5652#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5653#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5654#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5655#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5656#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5657 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5658 POWERPC_FLAG_BUS_CLK)
4e777442 5659#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5660
578bb252 5661__attribute__ (( unused ))
a750fc0b
JM		 5662static void init_proc_7455 (CPUPPCState *env)
5663{
5664 gen_spr_ne_601(env);
5665 gen_spr_7xx(env);
5666 /* Time base */
5667 gen_tbl(env);
5668 /* 74xx specific SPR */
5669 gen_spr_74xx(env);
5670 /* Level 3 cache control */
5671 gen_l3_ctrl(env);
5672 /* LDSTCR */
5673 /* XXX : not implemented */
5674 spr_register(env, SPR_LDSTCR, "LDSTCR",
5675 SPR_NOACCESS, SPR_NOACCESS,
5676 &spr_read_generic, &spr_write_generic,
5677 0x00000000);
5678 /* ICTRL */
5679 /* XXX : not implemented */
5680 spr_register(env, SPR_ICTRL, "ICTRL",
5681 SPR_NOACCESS, SPR_NOACCESS,
5682 &spr_read_generic, &spr_write_generic,
5683 0x00000000);
5684 /* MSSSR0 */
578bb252 5685 /* XXX : not implemented */
a750fc0b
JM		 5686 spr_register(env, SPR_MSSSR0, "MSSSR0",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 /* PMC */
5691 /* XXX : not implemented */
5692 spr_register(env, SPR_PMC5, "PMC5",
5693 SPR_NOACCESS, SPR_NOACCESS,
5694 &spr_read_generic, &spr_write_generic,
5695 0x00000000);
578bb252 5696 /* XXX : not implemented */
a750fc0b
JM		 5697 spr_register(env, SPR_UPMC5, "UPMC5",
5698 &spr_read_ureg, SPR_NOACCESS,
5699 &spr_read_ureg, SPR_NOACCESS,
5700 0x00000000);
578bb252 5701 /* XXX : not implemented */
a750fc0b
JM		 5702 spr_register(env, SPR_PMC6, "PMC6",
5703 SPR_NOACCESS, SPR_NOACCESS,
5704 &spr_read_generic, &spr_write_generic,
5705 0x00000000);
578bb252 5706 /* XXX : not implemented */
a750fc0b
JM		 5707 spr_register(env, SPR_UPMC6, "UPMC6",
5708 &spr_read_ureg, SPR_NOACCESS,
5709 &spr_read_ureg, SPR_NOACCESS,
5710 0x00000000);
5711 /* SPRGs */
5712 spr_register(env, SPR_SPRG4, "SPRG4",
5713 SPR_NOACCESS, SPR_NOACCESS,
5714 &spr_read_generic, &spr_write_generic,
5715 0x00000000);
5716 spr_register(env, SPR_USPRG4, "USPRG4",
5717 &spr_read_ureg, SPR_NOACCESS,
5718 &spr_read_ureg, SPR_NOACCESS,
5719 0x00000000);
5720 spr_register(env, SPR_SPRG5, "SPRG5",
5721 SPR_NOACCESS, SPR_NOACCESS,
5722 &spr_read_generic, &spr_write_generic,
5723 0x00000000);
5724 spr_register(env, SPR_USPRG5, "USPRG5",
5725 &spr_read_ureg, SPR_NOACCESS,
5726 &spr_read_ureg, SPR_NOACCESS,
5727 0x00000000);
5728 spr_register(env, SPR_SPRG6, "SPRG6",
5729 SPR_NOACCESS, SPR_NOACCESS,
5730 &spr_read_generic, &spr_write_generic,
5731 0x00000000);
5732 spr_register(env, SPR_USPRG6, "USPRG6",
5733 &spr_read_ureg, SPR_NOACCESS,
5734 &spr_read_ureg, SPR_NOACCESS,
5735 0x00000000);
5736 spr_register(env, SPR_SPRG7, "SPRG7",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 0x00000000);
5740 spr_register(env, SPR_USPRG7, "USPRG7",
5741 &spr_read_ureg, SPR_NOACCESS,
5742 &spr_read_ureg, SPR_NOACCESS,
5743 0x00000000);
5744 /* Memory management */
5745 gen_low_BATs(env);
5746 gen_high_BATs(env);
578bb252 5747 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5748 init_excp_7450(env);
d63001d1
JM		 5749 env->dcache_line_size = 32;
5750 env->icache_line_size = 32;
a750fc0b
JM		 5751 /* Allocate hardware IRQ controller */
5752 ppc6xx_irq_init(env);
5753}
a750fc0b 5754
4e777442
JM		 5755/* PowerPC 7457 (aka G4) */
5756#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5757 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5758 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5759 PPC_FLOAT_STFIWX | \
5760 PPC_CACHE | PPC_CACHE_ICBI | \
5761 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5762 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5763 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5764 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5765 PPC_SEGMENT | PPC_EXTERN | \
5766 PPC_ALTIVEC)
5767#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5768#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5769#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5770#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5771#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5772#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5773 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5774 POWERPC_FLAG_BUS_CLK)
5775#define check_pow_7457 check_pow_hid0_74xx
5776
5777__attribute__ (( unused ))
5778static void init_proc_7457 (CPUPPCState *env)
5779{
5780 gen_spr_ne_601(env);
5781 gen_spr_7xx(env);
5782 /* Time base */
5783 gen_tbl(env);
5784 /* 74xx specific SPR */
5785 gen_spr_74xx(env);
5786 /* Level 3 cache control */
5787 gen_l3_ctrl(env);
5788 /* L3ITCR1 */
5789 /* XXX : not implemented */
5790 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 0x00000000);
5794 /* L3ITCR2 */
5795 /* XXX : not implemented */
5796 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5797 SPR_NOACCESS, SPR_NOACCESS,
5798 &spr_read_generic, &spr_write_generic,
5799 0x00000000);
5800 /* L3ITCR3 */
5801 /* XXX : not implemented */
5802 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5803 SPR_NOACCESS, SPR_NOACCESS,
5804 &spr_read_generic, &spr_write_generic,
5805 0x00000000);
5806 /* L3OHCR */
5807 /* XXX : not implemented */
5808 spr_register(env, SPR_L3OHCR, "L3OHCR",
5809 SPR_NOACCESS, SPR_NOACCESS,
5810 &spr_read_generic, &spr_write_generic,
5811 0x00000000);
5812 /* LDSTCR */
5813 /* XXX : not implemented */
5814 spr_register(env, SPR_LDSTCR, "LDSTCR",
5815 SPR_NOACCESS, SPR_NOACCESS,
5816 &spr_read_generic, &spr_write_generic,
5817 0x00000000);
5818 /* ICTRL */
5819 /* XXX : not implemented */
5820 spr_register(env, SPR_ICTRL, "ICTRL",
5821 SPR_NOACCESS, SPR_NOACCESS,
5822 &spr_read_generic, &spr_write_generic,
5823 0x00000000);
5824 /* MSSSR0 */
5825 /* XXX : not implemented */
5826 spr_register(env, SPR_MSSSR0, "MSSSR0",
5827 SPR_NOACCESS, SPR_NOACCESS,
5828 &spr_read_generic, &spr_write_generic,
5829 0x00000000);
5830 /* PMC */
5831 /* XXX : not implemented */
5832 spr_register(env, SPR_PMC5, "PMC5",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 0x00000000);
5836 /* XXX : not implemented */
5837 spr_register(env, SPR_UPMC5, "UPMC5",
5838 &spr_read_ureg, SPR_NOACCESS,
5839 &spr_read_ureg, SPR_NOACCESS,
5840 0x00000000);
5841 /* XXX : not implemented */
5842 spr_register(env, SPR_PMC6, "PMC6",
5843 SPR_NOACCESS, SPR_NOACCESS,
5844 &spr_read_generic, &spr_write_generic,
5845 0x00000000);
5846 /* XXX : not implemented */
5847 spr_register(env, SPR_UPMC6, "UPMC6",
5848 &spr_read_ureg, SPR_NOACCESS,
5849 &spr_read_ureg, SPR_NOACCESS,
5850 0x00000000);
5851 /* SPRGs */
5852 spr_register(env, SPR_SPRG4, "SPRG4",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 spr_register(env, SPR_USPRG4, "USPRG4",
5857 &spr_read_ureg, SPR_NOACCESS,
5858 &spr_read_ureg, SPR_NOACCESS,
5859 0x00000000);
5860 spr_register(env, SPR_SPRG5, "SPRG5",
5861 SPR_NOACCESS, SPR_NOACCESS,
5862 &spr_read_generic, &spr_write_generic,
5863 0x00000000);
5864 spr_register(env, SPR_USPRG5, "USPRG5",
5865 &spr_read_ureg, SPR_NOACCESS,
5866 &spr_read_ureg, SPR_NOACCESS,
5867 0x00000000);
5868 spr_register(env, SPR_SPRG6, "SPRG6",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 &spr_read_generic, &spr_write_generic,
5871 0x00000000);
5872 spr_register(env, SPR_USPRG6, "USPRG6",
5873 &spr_read_ureg, SPR_NOACCESS,
5874 &spr_read_ureg, SPR_NOACCESS,
5875 0x00000000);
5876 spr_register(env, SPR_SPRG7, "SPRG7",
5877 SPR_NOACCESS, SPR_NOACCESS,
5878 &spr_read_generic, &spr_write_generic,
5879 0x00000000);
5880 spr_register(env, SPR_USPRG7, "USPRG7",
5881 &spr_read_ureg, SPR_NOACCESS,
5882 &spr_read_ureg, SPR_NOACCESS,
5883 0x00000000);
5884 /* Memory management */
5885 gen_low_BATs(env);
5886 gen_high_BATs(env);
5887 gen_74xx_soft_tlb(env, 128, 2);
5888 init_excp_7450(env);
5889 env->dcache_line_size = 32;
5890 env->icache_line_size = 32;
5891 /* Allocate hardware IRQ controller */
5892 ppc6xx_irq_init(env);
5893}
5894
a750fc0b
JM		 5895#if defined (TARGET_PPC64)
5896/* PowerPC 970 */
082c6681
JM		 5897#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5898 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5899 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5900 PPC_FLOAT_STFIWX | \
5901 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5902 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5903 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5904 PPC_64B | PPC_ALTIVEC | \
12de9a39 5905 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5906#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 5907#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 5908//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5909#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 5910#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 5911#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5912 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5913 POWERPC_FLAG_BUS_CLK)
a750fc0b 5914
417bf010
JM		 5915#if defined(CONFIG_USER_ONLY)
5916#define POWERPC970_HID5_INIT 0x00000080
5917#else
5918#define POWERPC970_HID5_INIT 0x00000000
5919#endif
5920
2f462816
JM		 5921static int check_pow_970 (CPUPPCState *env)
5922{
5923 if (env->spr[SPR_HID0] & 0x00600000)
5924 return 1;
5925
5926 return 0;
5927}
5928
a750fc0b
JM		 5929static void init_proc_970 (CPUPPCState *env)
5930{
5931 gen_spr_ne_601(env);
5932 gen_spr_7xx(env);
5933 /* Time base */
5934 gen_tbl(env);
5935 /* Hardware implementation registers */
5936 /* XXX : not implemented */
5937 spr_register(env, SPR_HID0, "HID0",
5938 SPR_NOACCESS, SPR_NOACCESS,
06403421 5939 &spr_read_generic, &spr_write_clear,
d63001d1 5940 0x60000000);
a750fc0b
JM		 5941 /* XXX : not implemented */
5942 spr_register(env, SPR_HID1, "HID1",
5943 SPR_NOACCESS, SPR_NOACCESS,
5944 &spr_read_generic, &spr_write_generic,
5945 0x00000000);
5946 /* XXX : not implemented */
bd928eba 5947 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5948 SPR_NOACCESS, SPR_NOACCESS,
5949 &spr_read_generic, &spr_write_generic,
5950 0x00000000);
e57448f1
JM		 5951 /* XXX : not implemented */
5952 spr_register(env, SPR_970_HID5, "HID5",
5953 SPR_NOACCESS, SPR_NOACCESS,
5954 &spr_read_generic, &spr_write_generic,
417bf010 5955 POWERPC970_HID5_INIT);
bd928eba
JM		 5956 /* XXX : not implemented */
5957 spr_register(env, SPR_L2CR, "L2CR",
5958 SPR_NOACCESS, SPR_NOACCESS,
5959 &spr_read_generic, &spr_write_generic,
5960 0x00000000);
a750fc0b
JM		 5961 /* Memory management */
5962 /* XXX: not correct */
5963 gen_low_BATs(env);
12de9a39
JM		 5964 /* XXX : not implemented */
5965 spr_register(env, SPR_MMUCFG, "MMUCFG",
5966 SPR_NOACCESS, SPR_NOACCESS,
5967 &spr_read_generic, SPR_NOACCESS,
5968 0x00000000); /* TOFIX */
5969 /* XXX : not implemented */
5970 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5971 SPR_NOACCESS, SPR_NOACCESS,
5972 &spr_read_generic, &spr_write_generic,
5973 0x00000000); /* TOFIX */
5974 spr_register(env, SPR_HIOR, "SPR_HIOR",
5975 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 5976 &spr_read_hior, &spr_write_hior,
5977 0x00000000);
f2e63a42 5978#if !defined(CONFIG_USER_ONLY)
12de9a39 5979 env->slb_nr = 32;
f2e63a42 5980#endif
e1833e1f 5981 init_excp_970(env);
d63001d1
JM		 5982 env->dcache_line_size = 128;
5983 env->icache_line_size = 128;
a750fc0b
JM		 5984 /* Allocate hardware IRQ controller */
5985 ppc970_irq_init(env);
cf8358c8
AJ		 5986 /* Can't find information on what this should be on reset. This
5987 * value is the one used by 74xx processors. */
5988 vscr_init(env, 0x00010000);
a750fc0b 5989}
a750fc0b
JM		 5990
5991/* PowerPC 970FX (aka G5) */
082c6681
JM		 5992#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5993 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5994 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5995 PPC_FLOAT_STFIWX | \
5996 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5997 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5998 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5999 PPC_64B | PPC_ALTIVEC | \
12de9a39 6000 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6001#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6002#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6003#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6004#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6005#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6006#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6007 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6008 POWERPC_FLAG_BUS_CLK)
a750fc0b 6009
2f462816
JM		 6010static int check_pow_970FX (CPUPPCState *env)
6011{
6012 if (env->spr[SPR_HID0] & 0x00600000)
6013 return 1;
6014
6015 return 0;
6016}
6017
a750fc0b
JM		 6018static void init_proc_970FX (CPUPPCState *env)
6019{
6020 gen_spr_ne_601(env);
6021 gen_spr_7xx(env);
6022 /* Time base */
6023 gen_tbl(env);
6024 /* Hardware implementation registers */
6025 /* XXX : not implemented */
6026 spr_register(env, SPR_HID0, "HID0",
6027 SPR_NOACCESS, SPR_NOACCESS,
06403421 6028 &spr_read_generic, &spr_write_clear,
d63001d1 6029 0x60000000);
a750fc0b
JM		 6030 /* XXX : not implemented */
6031 spr_register(env, SPR_HID1, "HID1",
6032 SPR_NOACCESS, SPR_NOACCESS,
6033 &spr_read_generic, &spr_write_generic,
6034 0x00000000);
6035 /* XXX : not implemented */
bd928eba 6036 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6037 SPR_NOACCESS, SPR_NOACCESS,
6038 &spr_read_generic, &spr_write_generic,
6039 0x00000000);
d63001d1
JM		 6040 /* XXX : not implemented */
6041 spr_register(env, SPR_970_HID5, "HID5",
6042 SPR_NOACCESS, SPR_NOACCESS,
6043 &spr_read_generic, &spr_write_generic,
417bf010 6044 POWERPC970_HID5_INIT);
bd928eba
JM		 6045 /* XXX : not implemented */
6046 spr_register(env, SPR_L2CR, "L2CR",
6047 SPR_NOACCESS, SPR_NOACCESS,
6048 &spr_read_generic, &spr_write_generic,
6049 0x00000000);
a750fc0b
JM		 6050 /* Memory management */
6051 /* XXX: not correct */
6052 gen_low_BATs(env);
12de9a39
JM		 6053 /* XXX : not implemented */
6054 spr_register(env, SPR_MMUCFG, "MMUCFG",
6055 SPR_NOACCESS, SPR_NOACCESS,
6056 &spr_read_generic, SPR_NOACCESS,
6057 0x00000000); /* TOFIX */
6058 /* XXX : not implemented */
6059 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6060 SPR_NOACCESS, SPR_NOACCESS,
6061 &spr_read_generic, &spr_write_generic,
6062 0x00000000); /* TOFIX */
6063 spr_register(env, SPR_HIOR, "SPR_HIOR",
6064 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6065 &spr_read_hior, &spr_write_hior,
6066 0x00000000);
4e98d8cf
BS		 6067 spr_register(env, SPR_CTRL, "SPR_CTRL",
6068 SPR_NOACCESS, SPR_NOACCESS,
6069 &spr_read_generic, &spr_write_generic,
6070 0x00000000);
6071 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6072 SPR_NOACCESS, SPR_NOACCESS,
6073 &spr_read_generic, &spr_write_generic,
6074 0x00000000);
6075 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6076 &spr_read_generic, &spr_write_generic,
6077 &spr_read_generic, &spr_write_generic,
6078 0x00000000);
f2e63a42 6079#if !defined(CONFIG_USER_ONLY)
8eee0af9 6080 env->slb_nr = 64;
f2e63a42 6081#endif
e1833e1f 6082 init_excp_970(env);
d63001d1
JM		 6083 env->dcache_line_size = 128;
6084 env->icache_line_size = 128;
a750fc0b
JM		 6085 /* Allocate hardware IRQ controller */
6086 ppc970_irq_init(env);
cf8358c8
AJ		 6087 /* Can't find information on what this should be on reset. This
6088 * value is the one used by 74xx processors. */
6089 vscr_init(env, 0x00010000);
a750fc0b 6090}
a750fc0b
JM		 6091
6092/* PowerPC 970 GX */
082c6681
JM		 6093#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6094 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6095 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6096 PPC_FLOAT_STFIWX | \
6097 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6098 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6099 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6100 PPC_64B | PPC_ALTIVEC | \
12de9a39 6101 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6102#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6103#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6104#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6105#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6106#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6107#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6108 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6109 POWERPC_FLAG_BUS_CLK)
a750fc0b 6110
2f462816
JM		 6111static int check_pow_970GX (CPUPPCState *env)
6112{
6113 if (env->spr[SPR_HID0] & 0x00600000)
6114 return 1;
6115
6116 return 0;
6117}
6118
a750fc0b
JM		 6119static void init_proc_970GX (CPUPPCState *env)
6120{
6121 gen_spr_ne_601(env);
6122 gen_spr_7xx(env);
6123 /* Time base */
6124 gen_tbl(env);
6125 /* Hardware implementation registers */
6126 /* XXX : not implemented */
6127 spr_register(env, SPR_HID0, "HID0",
6128 SPR_NOACCESS, SPR_NOACCESS,
06403421 6129 &spr_read_generic, &spr_write_clear,
d63001d1 6130 0x60000000);
a750fc0b
JM		 6131 /* XXX : not implemented */
6132 spr_register(env, SPR_HID1, "HID1",
6133 SPR_NOACCESS, SPR_NOACCESS,
6134 &spr_read_generic, &spr_write_generic,
6135 0x00000000);
6136 /* XXX : not implemented */
bd928eba 6137 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6138 SPR_NOACCESS, SPR_NOACCESS,
6139 &spr_read_generic, &spr_write_generic,
6140 0x00000000);
d63001d1
JM		 6141 /* XXX : not implemented */
6142 spr_register(env, SPR_970_HID5, "HID5",
6143 SPR_NOACCESS, SPR_NOACCESS,
6144 &spr_read_generic, &spr_write_generic,
417bf010 6145 POWERPC970_HID5_INIT);
bd928eba
JM		 6146 /* XXX : not implemented */
6147 spr_register(env, SPR_L2CR, "L2CR",
6148 SPR_NOACCESS, SPR_NOACCESS,
6149 &spr_read_generic, &spr_write_generic,
6150 0x00000000);
a750fc0b
JM		 6151 /* Memory management */
6152 /* XXX: not correct */
6153 gen_low_BATs(env);
12de9a39
JM		 6154 /* XXX : not implemented */
6155 spr_register(env, SPR_MMUCFG, "MMUCFG",
6156 SPR_NOACCESS, SPR_NOACCESS,
6157 &spr_read_generic, SPR_NOACCESS,
6158 0x00000000); /* TOFIX */
6159 /* XXX : not implemented */
6160 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6161 SPR_NOACCESS, SPR_NOACCESS,
6162 &spr_read_generic, &spr_write_generic,
6163 0x00000000); /* TOFIX */
6164 spr_register(env, SPR_HIOR, "SPR_HIOR",
6165 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6166 &spr_read_hior, &spr_write_hior,
6167 0x00000000);
f2e63a42 6168#if !defined(CONFIG_USER_ONLY)
12de9a39 6169 env->slb_nr = 32;
f2e63a42 6170#endif
e1833e1f 6171 init_excp_970(env);
d63001d1
JM		 6172 env->dcache_line_size = 128;
6173 env->icache_line_size = 128;
a750fc0b
JM		 6174 /* Allocate hardware IRQ controller */
6175 ppc970_irq_init(env);
cf8358c8
AJ		 6176 /* Can't find information on what this should be on reset. This
6177 * value is the one used by 74xx processors. */
6178 vscr_init(env, 0x00010000);
a750fc0b 6179}
a750fc0b 6180
2f462816 6181/* PowerPC 970 MP */
082c6681
JM		 6182#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6183 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6184 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6185 PPC_FLOAT_STFIWX | \
6186 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6187 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6188 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6189 PPC_64B | PPC_ALTIVEC | \
6190 PPC_SEGMENT_64B | PPC_SLBI)
6191#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6192#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6193#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6194#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6195#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6196#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6197 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6198 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6199
6200static int check_pow_970MP (CPUPPCState *env)
6201{
6202 if (env->spr[SPR_HID0] & 0x01C00000)
6203 return 1;
6204
6205 return 0;
6206}
6207
6208static void init_proc_970MP (CPUPPCState *env)
6209{
6210 gen_spr_ne_601(env);
6211 gen_spr_7xx(env);
6212 /* Time base */
6213 gen_tbl(env);
6214 /* Hardware implementation registers */
6215 /* XXX : not implemented */
6216 spr_register(env, SPR_HID0, "HID0",
6217 SPR_NOACCESS, SPR_NOACCESS,
6218 &spr_read_generic, &spr_write_clear,
6219 0x60000000);
6220 /* XXX : not implemented */
6221 spr_register(env, SPR_HID1, "HID1",
6222 SPR_NOACCESS, SPR_NOACCESS,
6223 &spr_read_generic, &spr_write_generic,
6224 0x00000000);
6225 /* XXX : not implemented */
bd928eba 6226 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6227 SPR_NOACCESS, SPR_NOACCESS,
6228 &spr_read_generic, &spr_write_generic,
6229 0x00000000);
6230 /* XXX : not implemented */
6231 spr_register(env, SPR_970_HID5, "HID5",
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_generic,
6234 POWERPC970_HID5_INIT);
bd928eba
JM		 6235 /* XXX : not implemented */
6236 spr_register(env, SPR_L2CR, "L2CR",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
2f462816
JM		 6240 /* Memory management */
6241 /* XXX: not correct */
6242 gen_low_BATs(env);
6243 /* XXX : not implemented */
6244 spr_register(env, SPR_MMUCFG, "MMUCFG",
6245 SPR_NOACCESS, SPR_NOACCESS,
6246 &spr_read_generic, SPR_NOACCESS,
6247 0x00000000); /* TOFIX */
6248 /* XXX : not implemented */
6249 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6250 SPR_NOACCESS, SPR_NOACCESS,
6251 &spr_read_generic, &spr_write_generic,
6252 0x00000000); /* TOFIX */
6253 spr_register(env, SPR_HIOR, "SPR_HIOR",
6254 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6255 &spr_read_hior, &spr_write_hior,
6256 0x00000000);
2f462816
JM		 6257#if !defined(CONFIG_USER_ONLY)
6258 env->slb_nr = 32;
6259#endif
6260 init_excp_970(env);
6261 env->dcache_line_size = 128;
6262 env->icache_line_size = 128;
6263 /* Allocate hardware IRQ controller */
6264 ppc970_irq_init(env);
cf8358c8
AJ		 6265 /* Can't find information on what this should be on reset. This
6266 * value is the one used by 74xx processors. */
6267 vscr_init(env, 0x00010000);
2f462816
JM		 6268}
6269
a750fc0b 6270/* PowerPC 620 */
082c6681
JM		 6271#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6272 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6273 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6274 PPC_FLOAT_STFIWX | \
6275 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6276 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6277 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6278 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6279 PPC_64B | PPC_SLBI)
add78955
JM		 6280#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6281//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6282#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6283#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6284#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6285#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6286 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6287#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6288
578bb252 6289__attribute__ (( unused ))
a750fc0b
JM		 6290static void init_proc_620 (CPUPPCState *env)
6291{
6292 gen_spr_ne_601(env);
6293 gen_spr_620(env);
6294 /* Time base */
6295 gen_tbl(env);
6296 /* Hardware implementation registers */
6297 /* XXX : not implemented */
6298 spr_register(env, SPR_HID0, "HID0",
6299 SPR_NOACCESS, SPR_NOACCESS,
6300 &spr_read_generic, &spr_write_generic,
6301 0x00000000);
6302 /* Memory management */
6303 gen_low_BATs(env);
e1833e1f 6304 init_excp_620(env);
d63001d1
JM		 6305 env->dcache_line_size = 64;
6306 env->icache_line_size = 64;
faadf50e
JM		 6307 /* Allocate hardware IRQ controller */
6308 ppc6xx_irq_init(env);
a750fc0b 6309}
a750fc0b
JM		 6310#endif /* defined (TARGET_PPC64) */
6311
6312/* Default 32 bits PowerPC target will be 604 */
6313#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6314#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6315#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6316#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6317#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6318#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6319#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6320#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6321#define check_pow_PPC32 check_pow_604
6322#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6323
6324/* Default 64 bits PowerPC target will be 970 FX */
6325#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6326#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6327#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6328#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6329#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6330#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6331#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6332#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6333#define check_pow_PPC64 check_pow_970FX
6334#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6335
6336/* Default PowerPC target will be PowerPC 32 */
6337#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 6338#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6339#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6340#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6341#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6342#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6343#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 6344#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 6345#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 6346#define check_pow_DEFAULT check_pow_PPC64
6347#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6348#else
d12f4c38
JM		 6349#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6350#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6351#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6352#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6353#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6354#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 6355#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 6356#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 6357#define check_pow_DEFAULT check_pow_PPC32
6358#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6359#endif
6360
6361/*****************************************************************************/
6362/* PVR definitions for most known PowerPC */
6363enum {
6364 /* PowerPC 401 family */
6365 /* Generic PowerPC 401 */
80d11f44 6366#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6367 /* PowerPC 401 cores */
80d11f44
JM		 6368 CPU_POWERPC_401A1 = 0x00210000,
6369 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6370#if 0
80d11f44 6371 CPU_POWERPC_401B3 = xxx,
a750fc0b 6372#endif
80d11f44
JM		 6373 CPU_POWERPC_401C2 = 0x00230000,
6374 CPU_POWERPC_401D2 = 0x00240000,
6375 CPU_POWERPC_401E2 = 0x00250000,
6376 CPU_POWERPC_401F2 = 0x00260000,
6377 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6378 /* PowerPC 401 microcontrolers */
6379#if 0
80d11f44 6380 CPU_POWERPC_401GF = xxx,
a750fc0b 6381#endif
80d11f44 6382#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6383 /* IBM Processor for Network Resources */
80d11f44 6384 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6385#if 0
80d11f44 6386 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6387#endif
6388 /* PowerPC 403 family */
6389 /* Generic PowerPC 403 */
80d11f44 6390#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6391 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6392 CPU_POWERPC_403GA = 0x00200011,
6393 CPU_POWERPC_403GB = 0x00200100,
6394 CPU_POWERPC_403GC = 0x00200200,
6395 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6396#if 0
80d11f44 6397 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6398#endif
6399 /* PowerPC 405 family */
6400 /* Generic PowerPC 405 */
80d11f44 6401#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6402 /* PowerPC 405 cores */
6403#if 0
80d11f44 6404 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6405#endif
6406#if 0
80d11f44 6407 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6408#endif
6409#if 0
80d11f44 6410 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6411#endif
6412#if 0
80d11f44 6413 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6414#endif
6415#if 0
80d11f44 6416 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6417#endif
6418#if 0
80d11f44 6419 CPU_POWERPC_405C4 = xxx,
a750fc0b 6420#endif
80d11f44 6421 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6422#if 0
80d11f44 6423 CPU_POWERPC_405D3 = xxx,
a750fc0b 6424#endif
80d11f44 6425 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6426#if 0
80d11f44 6427 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6428#endif
6429#if 0
80d11f44 6430 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6431#endif
6432#if 0
80d11f44 6433 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6434#endif
6435#if 0
80d11f44 6436 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6437#endif
6438#if 0
80d11f44 6439 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6440#endif
6441 /* PowerPC 405 microcontrolers */
6442 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6443#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6444 CPU_POWERPC_405CRa = 0x40110041,
6445 CPU_POWERPC_405CRb = 0x401100C5,
6446 CPU_POWERPC_405CRc = 0x40110145,
6447 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6448#if 0
80d11f44 6449 CPU_POWERPC_405EXr = xxx,
a750fc0b 6450#endif
80d11f44 6451 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6452#if 0
80d11f44
JM		 6453 CPU_POWERPC_405FX = xxx,
6454#endif
6455#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6456 CPU_POWERPC_405GPa = 0x40110000,
6457 CPU_POWERPC_405GPb = 0x40110040,
6458 CPU_POWERPC_405GPc = 0x40110082,
6459 CPU_POWERPC_405GPd = 0x401100C4,
6460#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6461 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6462#if 0
80d11f44 6463 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6464#endif
6465#if 0
80d11f44 6466 CPU_POWERPC_405L = xxx,
a750fc0b 6467#endif
80d11f44 6468 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6469#if 0
80d11f44 6470 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6471#endif
6472#if 0
80d11f44 6473 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6474#endif
6475#if 0
80d11f44 6476 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6477#endif
6478 /* IBM network processors */
80d11f44
JM		 6479 CPU_POWERPC_NPE405H = 0x414100C0,
6480 CPU_POWERPC_NPE405H2 = 0x41410140,
6481 CPU_POWERPC_NPE405L = 0x416100C0,
6482 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6483#if 0
80d11f44 6484 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6485#endif
6486#if 0
80d11f44 6487 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6488#endif
6489#if 0
80d11f44 6490 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6491#endif
6492 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6493#if 0
80d11f44 6494 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6495#endif
6496#if 0
80d11f44 6497 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6498#endif
6499#if 0
80d11f44 6500 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6501#endif
80d11f44 6502 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6503#if 0
80d11f44 6504 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6505#endif
6506#if 0
80d11f44 6507 CPU_POWERPC_STB045 = xxx,
a750fc0b 6508#endif
80d11f44
JM		 6509 CPU_POWERPC_STB04 = 0x41810000,
6510 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6511#if 0
80d11f44 6512 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6513#endif
6514 /* Xilinx cores */
80d11f44
JM		 6515 CPU_POWERPC_X2VP4 = 0x20010820,
6516#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6517 CPU_POWERPC_X2VP20 = 0x20010860,
6518#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6519#if 0
80d11f44 6520 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6521#endif
6522#if 0
80d11f44 6523 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6524#endif
6525#if 0
80d11f44 6526 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6527#endif
6528#if 0
80d11f44 6529 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6530#endif
6531 /* PowerPC 440 family */
6532 /* Generic PowerPC 440 */
80d11f44 6533#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6534 /* PowerPC 440 cores */
6535#if 0
80d11f44 6536 CPU_POWERPC_440A4 = xxx,
a750fc0b 6537#endif
95070372 6538 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 6539#if 0
80d11f44 6540 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6541#endif
6542#if 0
80d11f44 6543 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6544#endif
6545#if 0
80d11f44 6546 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6547#endif
6548#if 0
80d11f44 6549 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6550#endif
6551#if 0
80d11f44 6552 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6553#endif
6554#if 0
80d11f44 6555 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6556#endif
6557 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6558#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6559 CPU_POWERPC_440EPa = 0x42221850,
6560 CPU_POWERPC_440EPb = 0x422218D3,
6561#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6562 CPU_POWERPC_440GPb = 0x40120440,
6563 CPU_POWERPC_440GPc = 0x40120481,
6564#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6565#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6566 CPU_POWERPC_440GRX = 0x200008D0,
6567#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6568#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6569 CPU_POWERPC_440GXa = 0x51B21850,
6570 CPU_POWERPC_440GXb = 0x51B21851,
6571 CPU_POWERPC_440GXc = 0x51B21892,
6572 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6573#if 0
80d11f44 6574 CPU_POWERPC_440S = xxx,
a750fc0b 6575#endif
80d11f44
JM		 6576 CPU_POWERPC_440SP = 0x53221850,
6577 CPU_POWERPC_440SP2 = 0x53221891,
6578 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6579 /* PowerPC 460 family */
6580#if 0
6581 /* Generic PowerPC 464 */
80d11f44 6582#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6583#endif
6584 /* PowerPC 464 microcontrolers */
6585#if 0
80d11f44 6586 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6587#endif
6588#if 0
80d11f44 6589 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6590#endif
6591 /* Freescale embedded PowerPC cores */
c3e36823 6592 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6593 CPU_POWERPC_MPC5xx = 0x00020020,
6594#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6595#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6596#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6597#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6598#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6599#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6600#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6601#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6602#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6603#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6604#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6605#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6606#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6607 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6608 CPU_POWERPC_MPC8xx = 0x00500000,
6609#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6610#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6611#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6612#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6613#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6614#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6615#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6616#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6617#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6618#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6619#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6620#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6621#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6622#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6623#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6624 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6625 CPU_POWERPC_G2 = 0x00810011,
6626 CPU_POWERPC_G2H4 = 0x80811010,
6627 CPU_POWERPC_G2gp = 0x80821010,
6628 CPU_POWERPC_G2ls = 0x90810010,
6629 CPU_POWERPC_MPC603 = 0x00810100,
6630 CPU_POWERPC_G2_HIP3 = 0x00810101,
6631 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6632 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6633 CPU_POWERPC_G2LE = 0x80820010,
6634 CPU_POWERPC_G2LEgp = 0x80822010,
6635 CPU_POWERPC_G2LEls = 0xA0822010,
6636 CPU_POWERPC_G2LEgp1 = 0x80822011,
6637 CPU_POWERPC_G2LEgp3 = 0x80822013,
6638 /* MPC52xx microcontrollers */
c3e36823 6639 /* XXX: MPC 5121 ? */
80d11f44
JM		 6640#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6641#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6642#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6643#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6644#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6645#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6646#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6647#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6648 /* MPC82xx microcontrollers */
6649#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6650#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6651#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6652#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6653#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6654#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6655#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6656#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6657#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6658#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6659#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6660#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6661#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6662#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6663#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6664#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6665#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6666#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6667#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6668#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6669#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6670#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6671#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6672#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6673#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6674#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6675#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6676#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6677#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6678 /* e200 family */
80d11f44
JM		 6679 /* e200 cores */
6680#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6681#if 0
80d11f44 6682 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6683#endif
6684#if 0
80d11f44 6685 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6686#endif
6687#if 0 /* ? */
80d11f44
JM		 6688 CPU_POWERPC_e200z3 = 0x81120000,
6689#endif
6690 CPU_POWERPC_e200z5 = 0x81000000,
6691 CPU_POWERPC_e200z6 = 0x81120000,
6692 /* MPC55xx microcontrollers */
6693#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6694#if 0
6695#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6696#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6697#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6698#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6699#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6700#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6701#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6702#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6703#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6704#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6705#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6706#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6707#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6708#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6709#endif
6710#if 0
6711#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6712#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6713#endif
6714#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6715#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6716#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6717#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6718#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6719#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 6720 /* e300 family */
80d11f44
JM		 6721 /* e300 cores */
6722#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6723 CPU_POWERPC_e300c1 = 0x00830010,
6724 CPU_POWERPC_e300c2 = 0x00840010,
6725 CPU_POWERPC_e300c3 = 0x00850010,
6726 CPU_POWERPC_e300c4 = 0x00860010,
6727 /* MPC83xx microcontrollers */
74d77cae
TM		 6728#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
6729#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
6730#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
6731#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
6732#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
6733#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 6734 /* e500 family */
80d11f44
JM		 6735 /* e500 cores */
6736#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 6737#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 6738#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 6739 CPU_POWERPC_e500v1_v10 = 0x80200010,
6740 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 6741 CPU_POWERPC_e500v2_v10 = 0x80210010,
6742 CPU_POWERPC_e500v2_v11 = 0x80210011,
6743 CPU_POWERPC_e500v2_v20 = 0x80210020,
6744 CPU_POWERPC_e500v2_v21 = 0x80210021,
6745 CPU_POWERPC_e500v2_v22 = 0x80210022,
6746 CPU_POWERPC_e500v2_v30 = 0x80210030,
6747 /* MPC85xx microcontrollers */
6748#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6749#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6750#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6751#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6752#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6753#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6754#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 6755#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
6756#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
6757#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 6758#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 6759#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
6760#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 6761#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 6762#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
6763#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 6764#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6765#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6766#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6767#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6768#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6769#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6770#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6771#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6772#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6773#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6774#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6775#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6776#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6777#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6778#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6779#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6780#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6781#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6782#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6783#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6784#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6785#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6786#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6787#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6788#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6789#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6790#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6791#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6792#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6793#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6794#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6795#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6796#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6797#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6798#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6799#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6800#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6801#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6802#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6803#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6804#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6805#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6806#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6807#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6808#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6809#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6810#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6811#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6812#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6813#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6814#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6815#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6816#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6817#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 6818 /* e600 family */
80d11f44
JM		 6819 /* e600 cores */
6820 CPU_POWERPC_e600 = 0x80040010,
6821 /* MPC86xx microcontrollers */
6822#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6823#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6824#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 6825 /* PowerPC 6xx cores */
80d11f44
JM		 6826#define CPU_POWERPC_601 CPU_POWERPC_601_v2
6827 CPU_POWERPC_601_v0 = 0x00010001,
6828 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 6829#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 6830 CPU_POWERPC_601_v2 = 0x00010002,
6831 CPU_POWERPC_602 = 0x00050100,
6832 CPU_POWERPC_603 = 0x00030100,
6833#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6834 CPU_POWERPC_603E_v11 = 0x00060101,
6835 CPU_POWERPC_603E_v12 = 0x00060102,
6836 CPU_POWERPC_603E_v13 = 0x00060103,
6837 CPU_POWERPC_603E_v14 = 0x00060104,
6838 CPU_POWERPC_603E_v22 = 0x00060202,
6839 CPU_POWERPC_603E_v3 = 0x00060300,
6840 CPU_POWERPC_603E_v4 = 0x00060400,
6841 CPU_POWERPC_603E_v41 = 0x00060401,
6842 CPU_POWERPC_603E7t = 0x00071201,
6843 CPU_POWERPC_603E7v = 0x00070100,
6844 CPU_POWERPC_603E7v1 = 0x00070101,
6845 CPU_POWERPC_603E7v2 = 0x00070201,
6846 CPU_POWERPC_603E7 = 0x00070200,
6847 CPU_POWERPC_603P = 0x00070000,
6848#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 6849 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 6850 CPU_POWERPC_604 = 0x00040103,
6851#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 6852 /* XXX: missing 0x00091203 */
6853 /* XXX: missing 0x00092110 */
6854 /* XXX: missing 0x00092120 */
80d11f44
JM		 6855 CPU_POWERPC_604E_v10 = 0x00090100,
6856 CPU_POWERPC_604E_v22 = 0x00090202,
6857 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 6858 /* XXX: missing 0x000a0100 */
6859 /* XXX: missing 0x00093102 */
80d11f44 6860 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 6861#if 0
80d11f44 6862 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 6863#endif
6864 /* PowerPC 740/750 cores (aka G3) */
6865 /* XXX: missing 0x00084202 */
80d11f44 6866#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 6867 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 6868 CPU_POWERPC_7x0_v20 = 0x00080200,
6869 CPU_POWERPC_7x0_v21 = 0x00080201,
6870 CPU_POWERPC_7x0_v22 = 0x00080202,
6871 CPU_POWERPC_7x0_v30 = 0x00080300,
6872 CPU_POWERPC_7x0_v31 = 0x00080301,
6873 CPU_POWERPC_740E = 0x00080100,
bd928eba 6874 CPU_POWERPC_750E = 0x00080200,
80d11f44 6875 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 6876 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 6877#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6878 CPU_POWERPC_750CL_v10 = 0x00087200,
6879 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 6880#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 6881 CPU_POWERPC_750CX_v10 = 0x00082100,
6882 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 6883 CPU_POWERPC_750CX_v21 = 0x00082201,
6884 CPU_POWERPC_750CX_v22 = 0x00082202,
6885#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6886 CPU_POWERPC_750CXE_v21 = 0x00082211,
6887 CPU_POWERPC_750CXE_v22 = 0x00082212,
6888 CPU_POWERPC_750CXE_v23 = 0x00082213,
6889 CPU_POWERPC_750CXE_v24 = 0x00082214,
6890 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 6891 CPU_POWERPC_750CXE_v30 = 0x00082310,
6892 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 6893 CPU_POWERPC_750CXE_v31b = 0x00083311,
6894 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 6895 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 6896#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6897 CPU_POWERPC_750FX_v10 = 0x70000100,
6898 CPU_POWERPC_750FX_v20 = 0x70000200,
6899 CPU_POWERPC_750FX_v21 = 0x70000201,
6900 CPU_POWERPC_750FX_v22 = 0x70000202,
6901 CPU_POWERPC_750FX_v23 = 0x70000203,
6902 CPU_POWERPC_750GL = 0x70020102,
6903#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6904 CPU_POWERPC_750GX_v10 = 0x70020100,
6905 CPU_POWERPC_750GX_v11 = 0x70020101,
6906 CPU_POWERPC_750GX_v12 = 0x70020102,
6907#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 6908 CPU_POWERPC_750L_v20 = 0x00088200,
6909 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 6910 CPU_POWERPC_750L_v22 = 0x00088202,
6911 CPU_POWERPC_750L_v30 = 0x00088300,
6912 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 6913 /* PowerPC 745/755 cores */
80d11f44
JM		 6914#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6915 CPU_POWERPC_7x5_v10 = 0x00083100,
6916 CPU_POWERPC_7x5_v11 = 0x00083101,
6917 CPU_POWERPC_7x5_v20 = 0x00083200,
6918 CPU_POWERPC_7x5_v21 = 0x00083201,
6919 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6920 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6921 CPU_POWERPC_7x5_v24 = 0x00083204,
6922 CPU_POWERPC_7x5_v25 = 0x00083205,
6923 CPU_POWERPC_7x5_v26 = 0x00083206,
6924 CPU_POWERPC_7x5_v27 = 0x00083207,
6925 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 6926#if 0
80d11f44 6927 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 6928#endif
6929 /* PowerPC 74xx cores (aka G4) */
6930 /* XXX: missing 0x000C1101 */
80d11f44
JM		 6931#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6932 CPU_POWERPC_7400_v10 = 0x000C0100,
6933 CPU_POWERPC_7400_v11 = 0x000C0101,
6934 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 6935 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 6936 CPU_POWERPC_7400_v22 = 0x000C0202,
6937 CPU_POWERPC_7400_v26 = 0x000C0206,
6938 CPU_POWERPC_7400_v27 = 0x000C0207,
6939 CPU_POWERPC_7400_v28 = 0x000C0208,
6940 CPU_POWERPC_7400_v29 = 0x000C0209,
6941#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6942 CPU_POWERPC_7410_v10 = 0x800C1100,
6943 CPU_POWERPC_7410_v11 = 0x800C1101,
6944 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6945 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6946 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6947#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6948 CPU_POWERPC_7448_v10 = 0x80040100,
6949 CPU_POWERPC_7448_v11 = 0x80040101,
6950 CPU_POWERPC_7448_v20 = 0x80040200,
6951 CPU_POWERPC_7448_v21 = 0x80040201,
6952#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6953 CPU_POWERPC_7450_v10 = 0x80000100,
6954 CPU_POWERPC_7450_v11 = 0x80000101,
6955 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 6956 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 6957 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 6958#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
6959 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
6960 /* XXX: this entry might be a bug in some documentation */
6961 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 6962#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6963 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 6964 /* XXX: missing 0x80010200 */
80d11f44
JM		 6965 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6966 CPU_POWERPC_74x5_v32 = 0x80010302,
6967 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6968 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6969#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 6970 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 6971 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 6972 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 6973#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6974 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6975 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6976 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 6977 /* 64 bits PowerPC */
00af685f 6978#if defined(TARGET_PPC64)
80d11f44
JM		 6979 CPU_POWERPC_620 = 0x00140000,
6980 CPU_POWERPC_630 = 0x00400000,
6981 CPU_POWERPC_631 = 0x00410104,
6982 CPU_POWERPC_POWER4 = 0x00350000,
6983 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 6984 /* XXX: missing 0x003A0201 */
80d11f44
JM		 6985 CPU_POWERPC_POWER5 = 0x003A0203,
6986#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6987 CPU_POWERPC_POWER5P = 0x003B0000,
6988#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6989 CPU_POWERPC_POWER6 = 0x003E0000,
6990 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6991 CPU_POWERPC_POWER6A = 0x0F000002,
6992 CPU_POWERPC_970 = 0x00390202,
6993#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6994 CPU_POWERPC_970FX_v10 = 0x00391100,
6995 CPU_POWERPC_970FX_v20 = 0x003C0200,
6996 CPU_POWERPC_970FX_v21 = 0x003C0201,
6997 CPU_POWERPC_970FX_v30 = 0x003C0300,
6998 CPU_POWERPC_970FX_v31 = 0x003C0301,
6999 CPU_POWERPC_970GX = 0x00450000,
7000#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7001 CPU_POWERPC_970MP_v10 = 0x00440100,
7002 CPU_POWERPC_970MP_v11 = 0x00440101,
7003#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7004 CPU_POWERPC_CELL_v10 = 0x00700100,
7005 CPU_POWERPC_CELL_v20 = 0x00700400,
7006 CPU_POWERPC_CELL_v30 = 0x00700500,
7007 CPU_POWERPC_CELL_v31 = 0x00700501,
7008#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7009 CPU_POWERPC_RS64 = 0x00330000,
7010 CPU_POWERPC_RS64II = 0x00340000,
7011 CPU_POWERPC_RS64III = 0x00360000,
7012 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7013#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7014 /* Original POWER */
7015 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7016 * POWER2 (RIOS2) & RSC2 (P2SC) here
7017 */
7018#if 0
80d11f44 7019 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7020#endif
7021#if 0
80d11f44 7022 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7023#endif
7024 /* PA Semi core */
80d11f44 7025 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7026};
7027
7028/* System version register (used on MPC 8xxx) */
7029enum {
80d11f44
JM		 7030 POWERPC_SVR_NONE = 0x00000000,
7031#define POWERPC_SVR_52xx POWERPC_SVR_5200
7032#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7033 POWERPC_SVR_5200_v10 = 0x80110010,
7034 POWERPC_SVR_5200_v11 = 0x80110011,
7035 POWERPC_SVR_5200_v12 = 0x80110012,
7036#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7037 POWERPC_SVR_5200B_v20 = 0x80110020,
7038 POWERPC_SVR_5200B_v21 = 0x80110021,
7039#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7040#if 0
80d11f44 7041 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7042#endif
7043#if 0
80d11f44 7044 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7045#endif
7046#if 0
80d11f44 7047 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7048#endif
7049#if 0
80d11f44 7050 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7051#endif
7052#if 0
80d11f44 7053 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7054#endif
7055#if 0
80d11f44 7056 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7057#endif
7058#if 0
80d11f44 7059 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7060#endif
7061#if 0
80d11f44 7062 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7063#endif
7064#if 0
80d11f44 7065 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7066#endif
7067#if 0
80d11f44 7068 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7069#endif
7070#if 0
80d11f44 7071 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7072#endif
7073#if 0
80d11f44 7074 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7075#endif
7076#if 0
80d11f44 7077 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7078#endif
7079#if 0
80d11f44 7080 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7081#endif
7082#if 0
80d11f44 7083 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7084#endif
7085#if 0
80d11f44 7086 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7087#endif
7088#if 0
80d11f44 7089 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7090#endif
7091#if 0
80d11f44
JM		 7092 POWERPC_SVR_8323E = xxx,
7093#endif
492d7bf5 7094 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7095 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7096 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7097 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7098#define POWERPC_SVR_8347 POWERPC_SVR_8347T
7099 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7100 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7101#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7102 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7103 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7104#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7105 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7106 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7107#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7108 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7109 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7110 POWERPC_SVR_8349 = 0x80510010,
7111 POWERPC_SVR_8349A = 0x80510030,
7112 POWERPC_SVR_8349E = 0x80500010,
7113 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7114#if 0
80d11f44 7115 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7116#endif
7117#if 0
80d11f44
JM		 7118 POWERPC_SVR_8360E = xxx,
7119#endif
7120#define POWERPC_SVR_E500 0x40000000
7121 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7122 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7123 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7124 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7125 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7126 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7127#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7128 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7129 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7130#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7131 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7132 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7133#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7134 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7135 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7136 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7137#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7138 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7139 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7140#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7141 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7142 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7143#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7144 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7145 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7146 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7147 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7148#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7149 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7150 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7151 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7152 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7153#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7154 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7155 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7156#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7157 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7158 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7159#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7160 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7161 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7162#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7163 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7164 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7165#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7166 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7167 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7168#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7169 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7170 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7171 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7172 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7173#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7174 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7175 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7176 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7177 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7178#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7179 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7180 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7181#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7182 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7183 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7184#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7185 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7186 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7187 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7188 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7189 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7190 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7191 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7192 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7193 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7194#if 0
80d11f44 7195 POWERPC_SVR_8610 = xxx,
c3e36823 7196#endif
80d11f44
JM		 7197 POWERPC_SVR_8641 = 0x80900021,
7198 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7199};
7200
3fc6c082 7201/*****************************************************************************/
a750fc0b 7202/* PowerPC CPU definitions */
80d11f44 7203#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 7204 { \
7205 .name = _name, \
7206 .pvr = _pvr, \
80d11f44 7207 .svr = _svr, \
a750fc0b
JM		 7208 .insns_flags = glue(POWERPC_INSNS_,_type), \
7209 .msr_mask = glue(POWERPC_MSRM_,_type), \
7210 .mmu_model = glue(POWERPC_MMU_,_type), \
7211 .excp_model = glue(POWERPC_EXCP_,_type), \
7212 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 7213 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 7214 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 7215 .init_proc = &glue(init_proc_,_type), \
2f462816 7216 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7217 }
80d11f44
JM		 7218#define POWERPC_DEF(_name, _pvr, _type) \
7219POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7220
c227f099 7221static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7222 /* Embedded PowerPC */
7223 /* PowerPC 401 family */
2662a059 7224 /* Generic PowerPC 401 */
80d11f44 7225 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7226 /* PowerPC 401 cores */
2662a059 7227 /* PowerPC 401A1 */
80d11f44 7228 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7229 /* PowerPC 401B2 */
80d11f44 7230 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7231#if defined (TODO)
a750fc0b 7232 /* PowerPC 401B3 */
80d11f44 7233 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7234#endif
7235 /* PowerPC 401C2 */
80d11f44 7236 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7237 /* PowerPC 401D2 */
80d11f44 7238 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7239 /* PowerPC 401E2 */
80d11f44 7240 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7241 /* PowerPC 401F2 */
80d11f44 7242 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7243 /* PowerPC 401G2 */
7244 /* XXX: to be checked */
80d11f44 7245 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7246 /* PowerPC 401 microcontrolers */
2662a059 7247#if defined (TODO)
a750fc0b 7248 /* PowerPC 401GF */
80d11f44 7249 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7250#endif
a750fc0b 7251 /* IOP480 (401 microcontroler) */
80d11f44 7252 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7253 /* IBM Processor for Network Resources */
80d11f44 7254 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7255#if defined (TODO)
80d11f44 7256 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7257#endif
a750fc0b
JM		 7258 /* PowerPC 403 family */
7259 /* Generic PowerPC 403 */
80d11f44 7260 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7261 /* PowerPC 403 microcontrolers */
7262 /* PowerPC 403 GA */
80d11f44 7263 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7264 /* PowerPC 403 GB */
80d11f44 7265 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7266 /* PowerPC 403 GC */
80d11f44 7267 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7268 /* PowerPC 403 GCX */
80d11f44 7269 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7270#if defined (TODO)
a750fc0b 7271 /* PowerPC 403 GP */
80d11f44 7272 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7273#endif
a750fc0b
JM		 7274 /* PowerPC 405 family */
7275 /* Generic PowerPC 405 */
80d11f44 7276 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7277 /* PowerPC 405 cores */
2662a059 7278#if defined (TODO)
a750fc0b 7279 /* PowerPC 405 A3 */
80d11f44 7280 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7281#endif
3a607854 7282#if defined (TODO)
a750fc0b 7283 /* PowerPC 405 A4 */
80d11f44 7284 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7285#endif
3a607854 7286#if defined (TODO)
a750fc0b 7287 /* PowerPC 405 B3 */
80d11f44 7288 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7289#endif
7290#if defined (TODO)
a750fc0b 7291 /* PowerPC 405 B4 */
80d11f44 7292 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7293#endif
7294#if defined (TODO)
7295 /* PowerPC 405 C3 */
80d11f44 7296 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7297#endif
7298#if defined (TODO)
7299 /* PowerPC 405 C4 */
80d11f44 7300 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7301#endif
7302 /* PowerPC 405 D2 */
80d11f44 7303 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7304#if defined (TODO)
7305 /* PowerPC 405 D3 */
80d11f44 7306 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7307#endif
7308 /* PowerPC 405 D4 */
80d11f44 7309 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7310#if defined (TODO)
7311 /* PowerPC 405 D5 */
80d11f44 7312 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7313#endif
7314#if defined (TODO)
7315 /* PowerPC 405 E4 */
80d11f44 7316 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7317#endif
7318#if defined (TODO)
7319 /* PowerPC 405 F4 */
80d11f44 7320 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7321#endif
7322#if defined (TODO)
7323 /* PowerPC 405 F5 */
80d11f44 7324 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7325#endif
7326#if defined (TODO)
7327 /* PowerPC 405 F6 */
80d11f44 7328 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7329#endif
7330 /* PowerPC 405 microcontrolers */
7331 /* PowerPC 405 CR */
80d11f44 7332 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7333 /* PowerPC 405 CRa */
80d11f44 7334 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7335 /* PowerPC 405 CRb */
80d11f44 7336 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7337 /* PowerPC 405 CRc */
80d11f44 7338 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7339 /* PowerPC 405 EP */
80d11f44 7340 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7341#if defined(TODO)
7342 /* PowerPC 405 EXr */
80d11f44 7343 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7344#endif
7345 /* PowerPC 405 EZ */
80d11f44 7346 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7347#if defined(TODO)
7348 /* PowerPC 405 FX */
80d11f44 7349 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7350#endif
7351 /* PowerPC 405 GP */
80d11f44 7352 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7353 /* PowerPC 405 GPa */
80d11f44 7354 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7355 /* PowerPC 405 GPb */
80d11f44 7356 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7357 /* PowerPC 405 GPc */
80d11f44 7358 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7359 /* PowerPC 405 GPd */
80d11f44 7360 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7361 /* PowerPC 405 GPe */
80d11f44 7362 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7363 /* PowerPC 405 GPR */
80d11f44 7364 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7365#if defined(TODO)
7366 /* PowerPC 405 H */
80d11f44 7367 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7368#endif
7369#if defined(TODO)
7370 /* PowerPC 405 L */
80d11f44 7371 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7372#endif
7373 /* PowerPC 405 LP */
80d11f44 7374 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7375#if defined(TODO)
7376 /* PowerPC 405 PM */
80d11f44 7377 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7378#endif
7379#if defined(TODO)
7380 /* PowerPC 405 PS */
80d11f44 7381 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7382#endif
7383#if defined(TODO)
7384 /* PowerPC 405 S */
80d11f44 7385 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7386#endif
7387 /* Npe405 H */
80d11f44 7388 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7389 /* Npe405 H2 */
80d11f44 7390 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7391 /* Npe405 L */
80d11f44 7392 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7393 /* Npe4GS3 */
80d11f44 7394 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7395#if defined (TODO)
80d11f44 7396 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7397#endif
7398#if defined (TODO)
80d11f44 7399 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7400#endif
7401#if defined (TODO)
7402 /* PowerPC LC77700 (Sanyo) */
80d11f44 7403 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7404#endif
7405 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7406#if defined (TODO)
7407 /* STB010000 */
80d11f44 7408 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7409#endif
7410#if defined (TODO)
7411 /* STB01010 */
80d11f44 7412 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7413#endif
7414#if defined (TODO)
7415 /* STB0210 */
80d11f44 7416 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7417#endif
7418 /* STB03xx */
80d11f44 7419 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7420#if defined (TODO)
7421 /* STB043x */
80d11f44 7422 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7423#endif
7424#if defined (TODO)
7425 /* STB045x */
80d11f44 7426 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7427#endif
7428 /* STB04xx */
80d11f44 7429 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7430 /* STB25xx */
80d11f44 7431 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7432#if defined (TODO)
7433 /* STB130 */
80d11f44 7434 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7435#endif
7436 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7437 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7438 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7439 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7440 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7441#if defined (TODO)
7442 /* Zarlink ZL10310 */
80d11f44 7443 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7444#endif
7445#if defined (TODO)
7446 /* Zarlink ZL10311 */
80d11f44 7447 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7448#endif
7449#if defined (TODO)
7450 /* Zarlink ZL10320 */
80d11f44 7451 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7452#endif
7453#if defined (TODO)
7454 /* Zarlink ZL10321 */
80d11f44 7455 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7456#endif
7457 /* PowerPC 440 family */
80d11f44 7458#if defined(TODO_USER_ONLY)
a750fc0b 7459 /* Generic PowerPC 440 */
80d11f44
JM		 7460 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7461#endif
a750fc0b
JM		 7462 /* PowerPC 440 cores */
7463#if defined (TODO)
7464 /* PowerPC 440 A4 */
80d11f44 7465 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b 7466#endif
95070372
EI		 7467 /* PowerPC 440 Xilinx 5 */
7468 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
a750fc0b
JM		 7469#if defined (TODO)
7470 /* PowerPC 440 A5 */
80d11f44 7471 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7472#endif
7473#if defined (TODO)
7474 /* PowerPC 440 B4 */
80d11f44 7475 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7476#endif
7477#if defined (TODO)
7478 /* PowerPC 440 G4 */
80d11f44 7479 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7480#endif
7481#if defined (TODO)
7482 /* PowerPC 440 F5 */
80d11f44 7483 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7484#endif
7485#if defined (TODO)
7486 /* PowerPC 440 G5 */
80d11f44 7487 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7488#endif
7489#if defined (TODO)
7490 /* PowerPC 440H4 */
80d11f44 7491 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7492#endif
7493#if defined (TODO)
7494 /* PowerPC 440H6 */
80d11f44 7495 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7496#endif
7497 /* PowerPC 440 microcontrolers */
80d11f44 7498#if defined(TODO_USER_ONLY)
a750fc0b 7499 /* PowerPC 440 EP */
80d11f44
JM		 7500 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7501#endif
7502#if defined(TODO_USER_ONLY)
a750fc0b 7503 /* PowerPC 440 EPa */
80d11f44
JM		 7504 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7505#endif
7506#if defined(TODO_USER_ONLY)
a750fc0b 7507 /* PowerPC 440 EPb */
80d11f44
JM		 7508 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7509#endif
7510#if defined(TODO_USER_ONLY)
a750fc0b 7511 /* PowerPC 440 EPX */
80d11f44
JM		 7512 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7513#endif
7514#if defined(TODO_USER_ONLY)
a750fc0b 7515 /* PowerPC 440 GP */
80d11f44
JM		 7516 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7517#endif
7518#if defined(TODO_USER_ONLY)
a750fc0b 7519 /* PowerPC 440 GPb */
80d11f44
JM		 7520 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7521#endif
7522#if defined(TODO_USER_ONLY)
a750fc0b 7523 /* PowerPC 440 GPc */
80d11f44
JM		 7524 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7525#endif
7526#if defined(TODO_USER_ONLY)
a750fc0b 7527 /* PowerPC 440 GR */
80d11f44
JM		 7528 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7529#endif
7530#if defined(TODO_USER_ONLY)
a750fc0b 7531 /* PowerPC 440 GRa */
80d11f44
JM		 7532 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7533#endif
7534#if defined(TODO_USER_ONLY)
a750fc0b 7535 /* PowerPC 440 GRX */
80d11f44
JM		 7536 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7537#endif
7538#if defined(TODO_USER_ONLY)
a750fc0b 7539 /* PowerPC 440 GX */
80d11f44
JM		 7540 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7541#endif
7542#if defined(TODO_USER_ONLY)
a750fc0b 7543 /* PowerPC 440 GXa */
80d11f44
JM		 7544 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7545#endif
7546#if defined(TODO_USER_ONLY)
a750fc0b 7547 /* PowerPC 440 GXb */
80d11f44
JM		 7548 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7549#endif
7550#if defined(TODO_USER_ONLY)
a750fc0b 7551 /* PowerPC 440 GXc */
80d11f44
JM		 7552 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7553#endif
7554#if defined(TODO_USER_ONLY)
a750fc0b 7555 /* PowerPC 440 GXf */
80d11f44
JM		 7556 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7557#endif
a750fc0b
JM		 7558#if defined(TODO)
7559 /* PowerPC 440 S */
80d11f44 7560 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7561#endif
80d11f44 7562#if defined(TODO_USER_ONLY)
a750fc0b 7563 /* PowerPC 440 SP */
80d11f44
JM		 7564 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7565#endif
7566#if defined(TODO_USER_ONLY)
a750fc0b 7567 /* PowerPC 440 SP2 */
80d11f44
JM		 7568 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7569#endif
7570#if defined(TODO_USER_ONLY)
a750fc0b 7571 /* PowerPC 440 SPE */
80d11f44
JM		 7572 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7573#endif
a750fc0b
JM		 7574 /* PowerPC 460 family */
7575#if defined (TODO)
7576 /* Generic PowerPC 464 */
80d11f44 7577 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7578#endif
7579 /* PowerPC 464 microcontrolers */
7580#if defined (TODO)
7581 /* PowerPC 464H90 */
80d11f44 7582 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7583#endif
7584#if defined (TODO)
7585 /* PowerPC 464H90F */
80d11f44 7586 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7587#endif
7588 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7589 /* MPC5xx family (aka RCPU) */
7590#if defined(TODO_USER_ONLY)
7591 /* Generic MPC5xx core */
7592 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7593#endif
7594#if defined(TODO_USER_ONLY)
7595 /* Codename for MPC5xx core */
7596 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7597#endif
7598 /* MPC5xx microcontrollers */
7599#if defined(TODO_USER_ONLY)
7600 /* MGT560 */
7601 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7602#endif
7603#if defined(TODO_USER_ONLY)
7604 /* MPC509 */
7605 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7606#endif
7607#if defined(TODO_USER_ONLY)
7608 /* MPC533 */
7609 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7610#endif
7611#if defined(TODO_USER_ONLY)
7612 /* MPC534 */
7613 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7614#endif
7615#if defined(TODO_USER_ONLY)
7616 /* MPC555 */
7617 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7618#endif
7619#if defined(TODO_USER_ONLY)
7620 /* MPC556 */
7621 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7622#endif
7623#if defined(TODO_USER_ONLY)
7624 /* MPC560 */
7625 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7626#endif
7627#if defined(TODO_USER_ONLY)
7628 /* MPC561 */
7629 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7630#endif
7631#if defined(TODO_USER_ONLY)
7632 /* MPC562 */
7633 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7634#endif
7635#if defined(TODO_USER_ONLY)
7636 /* MPC563 */
7637 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7638#endif
7639#if defined(TODO_USER_ONLY)
7640 /* MPC564 */
7641 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7642#endif
7643#if defined(TODO_USER_ONLY)
7644 /* MPC565 */
7645 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7646#endif
7647#if defined(TODO_USER_ONLY)
7648 /* MPC566 */
7649 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7650#endif
7651 /* MPC8xx family (aka PowerQUICC) */
7652#if defined(TODO_USER_ONLY)
7653 /* Generic MPC8xx core */
7654 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7655#endif
7656#if defined(TODO_USER_ONLY)
7657 /* Codename for MPC8xx core */
7658 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7659#endif
7660 /* MPC8xx microcontrollers */
7661#if defined(TODO_USER_ONLY)
7662 /* MGT823 */
7663 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7664#endif
7665#if defined(TODO_USER_ONLY)
7666 /* MPC821 */
7667 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7668#endif
7669#if defined(TODO_USER_ONLY)
7670 /* MPC823 */
7671 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7672#endif
7673#if defined(TODO_USER_ONLY)
7674 /* MPC850 */
7675 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7676#endif
7677#if defined(TODO_USER_ONLY)
7678 /* MPC852T */
7679 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7680#endif
7681#if defined(TODO_USER_ONLY)
7682 /* MPC855T */
7683 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7684#endif
7685#if defined(TODO_USER_ONLY)
7686 /* MPC857 */
7687 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7688#endif
7689#if defined(TODO_USER_ONLY)
7690 /* MPC859 */
7691 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7692#endif
7693#if defined(TODO_USER_ONLY)
7694 /* MPC860 */
7695 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7696#endif
7697#if defined(TODO_USER_ONLY)
7698 /* MPC862 */
7699 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7700#endif
7701#if defined(TODO_USER_ONLY)
7702 /* MPC866 */
7703 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7704#endif
7705#if defined(TODO_USER_ONLY)
7706 /* MPC870 */
7707 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7708#endif
7709#if defined(TODO_USER_ONLY)
7710 /* MPC875 */
7711 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7712#endif
7713#if defined(TODO_USER_ONLY)
7714 /* MPC880 */
7715 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7716#endif
7717#if defined(TODO_USER_ONLY)
7718 /* MPC885 */
7719 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7720#endif
7721 /* MPC82xx family (aka PowerQUICC-II) */
7722 /* Generic MPC52xx core */
7723 POWERPC_DEF_SVR("MPC52xx",
7724 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7725 /* Generic MPC82xx core */
7726 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7727 /* Codename for MPC82xx */
7728 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7729 /* PowerPC G2 core */
7730 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7731 /* PowerPC G2 H4 core */
7732 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7733 /* PowerPC G2 GP core */
7734 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7735 /* PowerPC G2 LS core */
7736 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7737 /* PowerPC G2 HiP3 core */
7738 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7739 /* PowerPC G2 HiP4 core */
7740 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7741 /* PowerPC MPC603 core */
7742 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7743 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7744 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7745 /* PowerPC G2LE GP core */
7746 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7747 /* PowerPC G2LE LS core */
7748 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7749 /* PowerPC G2LE GP1 core */
7750 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7751 /* PowerPC G2LE GP3 core */
7752 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7753 /* PowerPC MPC603 microcontrollers */
7754 /* MPC8240 */
7755 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7756 /* PowerPC G2 microcontrollers */
082c6681 7757#if defined(TODO)
80d11f44
JM		 7758 /* MPC5121 */
7759 POWERPC_DEF_SVR("MPC5121",
7760 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7761#endif
7762 /* MPC5200 */
7763 POWERPC_DEF_SVR("MPC5200",
7764 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7765 /* MPC5200 v1.0 */
7766 POWERPC_DEF_SVR("MPC5200_v10",
7767 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7768 /* MPC5200 v1.1 */
7769 POWERPC_DEF_SVR("MPC5200_v11",
7770 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7771 /* MPC5200 v1.2 */
7772 POWERPC_DEF_SVR("MPC5200_v12",
7773 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7774 /* MPC5200B */
7775 POWERPC_DEF_SVR("MPC5200B",
7776 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7777 /* MPC5200B v2.0 */
7778 POWERPC_DEF_SVR("MPC5200B_v20",
7779 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7780 /* MPC5200B v2.1 */
7781 POWERPC_DEF_SVR("MPC5200B_v21",
7782 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7783 /* MPC8241 */
7784 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7785 /* MPC8245 */
7786 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7787 /* MPC8247 */
7788 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7789 /* MPC8248 */
7790 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7791 /* MPC8250 */
7792 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7793 /* MPC8250 HiP3 */
7794 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7795 /* MPC8250 HiP4 */
7796 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7797 /* MPC8255 */
7798 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7799 /* MPC8255 HiP3 */
7800 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7801 /* MPC8255 HiP4 */
7802 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7803 /* MPC8260 */
7804 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7805 /* MPC8260 HiP3 */
7806 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7807 /* MPC8260 HiP4 */
7808 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7809 /* MPC8264 */
7810 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7811 /* MPC8264 HiP3 */
7812 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7813 /* MPC8264 HiP4 */
7814 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7815 /* MPC8265 */
7816 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7817 /* MPC8265 HiP3 */
7818 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7819 /* MPC8265 HiP4 */
7820 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7821 /* MPC8266 */
7822 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7823 /* MPC8266 HiP3 */
7824 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7825 /* MPC8266 HiP4 */
7826 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7827 /* MPC8270 */
7828 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7829 /* MPC8271 */
7830 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7831 /* MPC8272 */
7832 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7833 /* MPC8275 */
7834 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7835 /* MPC8280 */
7836 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 7837 /* e200 family */
a750fc0b 7838 /* Generic PowerPC e200 core */
80d11f44
JM		 7839 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7840 /* Generic MPC55xx core */
7841#if defined (TODO)
7842 POWERPC_DEF_SVR("MPC55xx",
7843 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 7844#endif
7845#if defined (TODO)
80d11f44
JM		 7846 /* PowerPC e200z0 core */
7847 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 7848#endif
7849#if defined (TODO)
80d11f44
JM		 7850 /* PowerPC e200z1 core */
7851 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7852#endif
7853#if defined (TODO)
7854 /* PowerPC e200z3 core */
7855 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7856#endif
7857 /* PowerPC e200z5 core */
7858 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 7859 /* PowerPC e200z6 core */
80d11f44
JM		 7860 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7861 /* PowerPC e200 microcontrollers */
7862#if defined (TODO)
7863 /* MPC5514E */
7864 POWERPC_DEF_SVR("MPC5514E",
7865 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 7866#endif
a750fc0b 7867#if defined (TODO)
80d11f44
JM		 7868 /* MPC5514E v0 */
7869 POWERPC_DEF_SVR("MPC5514E_v0",
7870 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 7871#endif
7872#if defined (TODO)
80d11f44
JM		 7873 /* MPC5514E v1 */
7874 POWERPC_DEF_SVR("MPC5514E_v1",
7875 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 7876#endif
7877#if defined (TODO)
80d11f44
JM		 7878 /* MPC5514G */
7879 POWERPC_DEF_SVR("MPC5514G",
7880 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 7881#endif
7882#if defined (TODO)
80d11f44
JM		 7883 /* MPC5514G v0 */
7884 POWERPC_DEF_SVR("MPC5514G_v0",
7885 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 7886#endif
a750fc0b 7887#if defined (TODO)
80d11f44
JM		 7888 /* MPC5514G v1 */
7889 POWERPC_DEF_SVR("MPC5514G_v1",
7890 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 7891#endif
7892#if defined (TODO)
80d11f44
JM		 7893 /* MPC5515S */
7894 POWERPC_DEF_SVR("MPC5515S",
7895 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 7896#endif
7897#if defined (TODO)
80d11f44
JM		 7898 /* MPC5516E */
7899 POWERPC_DEF_SVR("MPC5516E",
7900 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 7901#endif
7902#if defined (TODO)
80d11f44
JM		 7903 /* MPC5516E v0 */
7904 POWERPC_DEF_SVR("MPC5516E_v0",
7905 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 7906#endif
7907#if defined (TODO)
80d11f44
JM		 7908 /* MPC5516E v1 */
7909 POWERPC_DEF_SVR("MPC5516E_v1",
7910 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 7911#endif
a750fc0b 7912#if defined (TODO)
80d11f44
JM		 7913 /* MPC5516G */
7914 POWERPC_DEF_SVR("MPC5516G",
7915 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 7916#endif
a750fc0b 7917#if defined (TODO)
80d11f44
JM		 7918 /* MPC5516G v0 */
7919 POWERPC_DEF_SVR("MPC5516G_v0",
7920 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 7921#endif
a750fc0b 7922#if defined (TODO)
80d11f44
JM		 7923 /* MPC5516G v1 */
7924 POWERPC_DEF_SVR("MPC5516G_v1",
7925 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 7926#endif
a750fc0b 7927#if defined (TODO)
80d11f44
JM		 7928 /* MPC5516S */
7929 POWERPC_DEF_SVR("MPC5516S",
7930 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 7931#endif
7932#if defined (TODO)
80d11f44
JM		 7933 /* MPC5533 */
7934 POWERPC_DEF_SVR("MPC5533",
7935 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 7936#endif
7937#if defined (TODO)
80d11f44
JM		 7938 /* MPC5534 */
7939 POWERPC_DEF_SVR("MPC5534",
7940 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 7941#endif
80d11f44
JM		 7942#if defined (TODO)
7943 /* MPC5553 */
7944 POWERPC_DEF_SVR("MPC5553",
7945 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7946#endif
7947#if defined (TODO)
7948 /* MPC5554 */
7949 POWERPC_DEF_SVR("MPC5554",
7950 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7951#endif
7952#if defined (TODO)
7953 /* MPC5561 */
7954 POWERPC_DEF_SVR("MPC5561",
7955 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7956#endif
7957#if defined (TODO)
7958 /* MPC5565 */
7959 POWERPC_DEF_SVR("MPC5565",
7960 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7961#endif
7962#if defined (TODO)
7963 /* MPC5566 */
7964 POWERPC_DEF_SVR("MPC5566",
7965 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7966#endif
7967#if defined (TODO)
7968 /* MPC5567 */
7969 POWERPC_DEF_SVR("MPC5567",
7970 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7971#endif
7972 /* e300 family */
7973 /* Generic PowerPC e300 core */
7974 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7975 /* PowerPC e300c1 core */
7976 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7977 /* PowerPC e300c2 core */
7978 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7979 /* PowerPC e300c3 core */
7980 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7981 /* PowerPC e300c4 core */
7982 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7983 /* PowerPC e300 microcontrollers */
7984#if defined (TODO)
7985 /* MPC8313 */
7986 POWERPC_DEF_SVR("MPC8313",
74d77cae 7987 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
80d11f44
JM		 7988#endif
7989#if defined (TODO)
7990 /* MPC8313E */
7991 POWERPC_DEF_SVR("MPC8313E",
74d77cae 7992 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
80d11f44
JM		 7993#endif
7994#if defined (TODO)
7995 /* MPC8314 */
7996 POWERPC_DEF_SVR("MPC8314",
74d77cae 7997 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
80d11f44
JM		 7998#endif
7999#if defined (TODO)
8000 /* MPC8314E */
8001 POWERPC_DEF_SVR("MPC8314E",
74d77cae 8002 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
80d11f44
JM		 8003#endif
8004#if defined (TODO)
8005 /* MPC8315 */
8006 POWERPC_DEF_SVR("MPC8315",
74d77cae 8007 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
80d11f44
JM		 8008#endif
8009#if defined (TODO)
8010 /* MPC8315E */
8011 POWERPC_DEF_SVR("MPC8315E",
74d77cae 8012 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
80d11f44
JM		 8013#endif
8014#if defined (TODO)
8015 /* MPC8321 */
8016 POWERPC_DEF_SVR("MPC8321",
74d77cae 8017 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
80d11f44
JM		 8018#endif
8019#if defined (TODO)
8020 /* MPC8321E */
8021 POWERPC_DEF_SVR("MPC8321E",
74d77cae 8022 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
80d11f44
JM		 8023#endif
8024#if defined (TODO)
8025 /* MPC8323 */
8026 POWERPC_DEF_SVR("MPC8323",
74d77cae 8027 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
80d11f44
JM		 8028#endif
8029#if defined (TODO)
8030 /* MPC8323E */
8031 POWERPC_DEF_SVR("MPC8323E",
74d77cae 8032 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
80d11f44 8033#endif
492d7bf5
TM		 8034 /* MPC8343 */
8035 POWERPC_DEF_SVR("MPC8343",
74d77cae 8036 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
80d11f44
JM		 8037 /* MPC8343A */
8038 POWERPC_DEF_SVR("MPC8343A",
74d77cae 8039 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
492d7bf5
TM		 8040 /* MPC8343E */
8041 POWERPC_DEF_SVR("MPC8343E",
74d77cae 8042 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
80d11f44
JM		 8043 /* MPC8343EA */
8044 POWERPC_DEF_SVR("MPC8343EA",
74d77cae 8045 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
492d7bf5
TM		 8046 /* MPC8347 */
8047 POWERPC_DEF_SVR("MPC8347",
74d77cae 8048 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
492d7bf5
TM		 8049 /* MPC8347T */
8050 POWERPC_DEF_SVR("MPC8347T",
74d77cae 8051 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
492d7bf5
TM		 8052 /* MPC8347P */
8053 POWERPC_DEF_SVR("MPC8347P",
74d77cae 8054 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
80d11f44
JM		 8055 /* MPC8347A */
8056 POWERPC_DEF_SVR("MPC8347A",
74d77cae 8057 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
80d11f44
JM		 8058 /* MPC8347AT */
8059 POWERPC_DEF_SVR("MPC8347AT",
74d77cae 8060 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
80d11f44
JM		 8061 /* MPC8347AP */
8062 POWERPC_DEF_SVR("MPC8347AP",
74d77cae 8063 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
492d7bf5
TM		 8064 /* MPC8347E */
8065 POWERPC_DEF_SVR("MPC8347E",
74d77cae 8066 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
492d7bf5
TM		 8067 /* MPC8347ET */
8068 POWERPC_DEF_SVR("MPC8347ET",
74d77cae 8069 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
492d7bf5
TM		 8070 /* MPC8343EP */
8071 POWERPC_DEF_SVR("MPC8347EP",
74d77cae 8072 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
80d11f44
JM		 8073 /* MPC8347EA */
8074 POWERPC_DEF_SVR("MPC8347EA",
74d77cae 8075 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
80d11f44
JM		 8076 /* MPC8347EAT */
8077 POWERPC_DEF_SVR("MPC8347EAT",
74d77cae 8078 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
80d11f44
JM		 8079 /* MPC8343EAP */
8080 POWERPC_DEF_SVR("MPC8347EAP",
74d77cae 8081 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
80d11f44
JM		 8082 /* MPC8349 */
8083 POWERPC_DEF_SVR("MPC8349",
74d77cae 8084 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
80d11f44
JM		 8085 /* MPC8349A */
8086 POWERPC_DEF_SVR("MPC8349A",
74d77cae 8087 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
80d11f44
JM		 8088 /* MPC8349E */
8089 POWERPC_DEF_SVR("MPC8349E",
74d77cae 8090 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
80d11f44
JM		 8091 /* MPC8349EA */
8092 POWERPC_DEF_SVR("MPC8349EA",
74d77cae 8093 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
80d11f44
JM		 8094#if defined (TODO)
8095 /* MPC8358E */
8096 POWERPC_DEF_SVR("MPC8358E",
74d77cae 8097 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
80d11f44
JM		 8098#endif
8099#if defined (TODO)
8100 /* MPC8360E */
8101 POWERPC_DEF_SVR("MPC8360E",
74d77cae 8102 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
80d11f44
JM		 8103#endif
8104 /* MPC8377 */
8105 POWERPC_DEF_SVR("MPC8377",
74d77cae 8106 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
80d11f44
JM		 8107 /* MPC8377E */
8108 POWERPC_DEF_SVR("MPC8377E",
74d77cae 8109 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
80d11f44
JM		 8110 /* MPC8378 */
8111 POWERPC_DEF_SVR("MPC8378",
74d77cae 8112 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
80d11f44
JM		 8113 /* MPC8378E */
8114 POWERPC_DEF_SVR("MPC8378E",
74d77cae 8115 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
80d11f44
JM		 8116 /* MPC8379 */
8117 POWERPC_DEF_SVR("MPC8379",
74d77cae 8118 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
80d11f44
JM		 8119 /* MPC8379E */
8120 POWERPC_DEF_SVR("MPC8379E",
74d77cae 8121 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
80d11f44
JM		 8122 /* e500 family */
8123 /* PowerPC e500 core */
bd5ea513
AJ		 8124 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8125 /* PowerPC e500v1 core */
8126 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8127 /* PowerPC e500 v1.0 core */
bd5ea513 8128 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8129 /* PowerPC e500 v2.0 core */
bd5ea513 8130 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8131 /* PowerPC e500v2 core */
bd5ea513 8132 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8133 /* PowerPC e500v2 v1.0 core */
bd5ea513 8134 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8135 /* PowerPC e500v2 v2.0 core */
bd5ea513 8136 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8137 /* PowerPC e500v2 v2.1 core */
bd5ea513 8138 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8139 /* PowerPC e500v2 v2.2 core */
bd5ea513 8140 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8141 /* PowerPC e500v2 v3.0 core */
bd5ea513 8142 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
80d11f44
JM		 8143 /* PowerPC e500 microcontrollers */
8144 /* MPC8533 */
8145 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8146 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8147 /* MPC8533 v1.0 */
8148 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8149 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8150 /* MPC8533 v1.1 */
8151 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8152 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8153 /* MPC8533E */
8154 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8155 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8156 /* MPC8533E v1.0 */
8157 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8158 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8159 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8160 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8161 /* MPC8540 */
8162 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8163 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8164 /* MPC8540 v1.0 */
8165 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8166 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8167 /* MPC8540 v2.0 */
8168 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8169 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8170 /* MPC8540 v2.1 */
8171 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8172 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8173 /* MPC8541 */
8174 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8175 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8176 /* MPC8541 v1.0 */
8177 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8178 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8179 /* MPC8541 v1.1 */
8180 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8181 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8182 /* MPC8541E */
8183 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8184 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8185 /* MPC8541E v1.0 */
8186 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8187 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8188 /* MPC8541E v1.1 */
8189 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8190 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8191 /* MPC8543 */
8192 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8193 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8194 /* MPC8543 v1.0 */
8195 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8196 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8197 /* MPC8543 v1.1 */
8198 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8199 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8200 /* MPC8543 v2.0 */
8201 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8202 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8203 /* MPC8543 v2.1 */
8204 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8205 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8206 /* MPC8543E */
8207 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8208 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8209 /* MPC8543E v1.0 */
8210 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8211 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8212 /* MPC8543E v1.1 */
8213 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8214 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8215 /* MPC8543E v2.0 */
8216 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8217 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8218 /* MPC8543E v2.1 */
8219 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8220 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8221 /* MPC8544 */
8222 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8223 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8224 /* MPC8544 v1.0 */
8225 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8226 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8227 /* MPC8544 v1.1 */
8228 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8229 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8230 /* MPC8544E */
8231 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8232 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8233 /* MPC8544E v1.0 */
8234 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8235 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8236 /* MPC8544E v1.1 */
8237 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8238 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8239 /* MPC8545 */
8240 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8241 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8242 /* MPC8545 v2.0 */
8243 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8244 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8245 /* MPC8545 v2.1 */
8246 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8247 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8248 /* MPC8545E */
8249 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8250 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8251 /* MPC8545E v2.0 */
8252 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8253 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8254 /* MPC8545E v2.1 */
8255 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8256 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8257 /* MPC8547E */
8258 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8259 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8260 /* MPC8547E v2.0 */
8261 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8262 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8263 /* MPC8547E v2.1 */
8264 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8265 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8266 /* MPC8548 */
8267 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8268 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8269 /* MPC8548 v1.0 */
8270 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8271 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8272 /* MPC8548 v1.1 */
8273 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8274 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8275 /* MPC8548 v2.0 */
8276 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8277 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8278 /* MPC8548 v2.1 */
8279 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8280 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8281 /* MPC8548E */
8282 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8283 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8284 /* MPC8548E v1.0 */
8285 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8286 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8287 /* MPC8548E v1.1 */
8288 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8289 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8290 /* MPC8548E v2.0 */
8291 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8292 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8293 /* MPC8548E v2.1 */
8294 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8295 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8296 /* MPC8555 */
8297 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8298 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8299 /* MPC8555 v1.0 */
8300 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8301 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8302 /* MPC8555 v1.1 */
8303 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8304 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8305 /* MPC8555E */
8306 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8307 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8308 /* MPC8555E v1.0 */
8309 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8310 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8311 /* MPC8555E v1.1 */
8312 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8313 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8314 /* MPC8560 */
8315 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8316 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8317 /* MPC8560 v1.0 */
8318 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8319 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8320 /* MPC8560 v2.0 */
8321 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8322 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8323 /* MPC8560 v2.1 */
8324 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8325 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8326 /* MPC8567 */
8327 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8328 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8329 /* MPC8567E */
8330 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8331 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8332 /* MPC8568 */
8333 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8334 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8335 /* MPC8568E */
8336 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8337 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8338 /* MPC8572 */
8339 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8340 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8341 /* MPC8572E */
8342 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8343 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8344 /* e600 family */
8345 /* PowerPC e600 core */
8346 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8347 /* PowerPC e600 microcontrollers */
8348#if defined (TODO)
8349 /* MPC8610 */
8350 POWERPC_DEF_SVR("MPC8610",
8351 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8352#endif
8353 /* MPC8641 */
8354 POWERPC_DEF_SVR("MPC8641",
8355 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8356 /* MPC8641D */
8357 POWERPC_DEF_SVR("MPC8641D",
8358 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8359 /* 32 bits "classic" PowerPC */
8360 /* PowerPC 6xx family */
8361 /* PowerPC 601 */
bd928eba 8362 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8363 /* PowerPC 601v0 */
082c6681 8364 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8365 /* PowerPC 601v1 */
082c6681
JM		 8366 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8367 /* PowerPC 601v */
bd928eba 8368 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8369 /* PowerPC 601v2 */
082c6681 8370 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8371 /* PowerPC 602 */
80d11f44 8372 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8373 /* PowerPC 603 */
80d11f44 8374 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8375 /* Code name for PowerPC 603 */
80d11f44 8376 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8377 /* PowerPC 603e (aka PID6) */
80d11f44 8378 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8379 /* Code name for PowerPC 603e */
80d11f44 8380 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8381 /* PowerPC 603e v1.1 */
80d11f44 8382 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8383 /* PowerPC 603e v1.2 */
80d11f44 8384 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8385 /* PowerPC 603e v1.3 */
80d11f44 8386 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8387 /* PowerPC 603e v1.4 */
80d11f44 8388 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8389 /* PowerPC 603e v2.2 */
80d11f44 8390 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8391 /* PowerPC 603e v3 */
80d11f44 8392 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8393 /* PowerPC 603e v4 */
80d11f44 8394 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8395 /* PowerPC 603e v4.1 */
80d11f44 8396 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8397 /* PowerPC 603e (aka PID7) */
80d11f44 8398 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8399 /* PowerPC 603e7t */
80d11f44 8400 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8401 /* PowerPC 603e7v */
80d11f44 8402 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8403 /* Code name for PowerPC 603ev */
80d11f44 8404 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8405 /* PowerPC 603e7v1 */
80d11f44 8406 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8407 /* PowerPC 603e7v2 */
80d11f44 8408 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8409 /* PowerPC 603p (aka PID7v) */
8410 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8411 /* PowerPC 603r (aka PID7t) */
80d11f44 8412 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8413 /* Code name for PowerPC 603r */
80d11f44 8414 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8415 /* PowerPC 604 */
80d11f44 8416 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8417 /* PowerPC 604e (aka PID9) */
8418 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8419 /* Code name for PowerPC 604e */
8420 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8421 /* PowerPC 604e v1.0 */
082c6681 8422 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8423 /* PowerPC 604e v2.2 */
082c6681 8424 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8425 /* PowerPC 604e v2.4 */
082c6681
JM		 8426 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8427 /* PowerPC 604r (aka PIDA) */
8428 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8429 /* Code name for PowerPC 604r */
8430 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8431#if defined(TODO)
8432 /* PowerPC 604ev */
082c6681 8433 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8434#endif
8435 /* PowerPC 7xx family */
8436 /* Generic PowerPC 740 (G3) */
bd928eba 8437 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8438 /* Code name for PowerPC 740 */
bd928eba 8439 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8440 /* Generic PowerPC 750 (G3) */
bd928eba 8441 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8442 /* Code name for PowerPC 750 */
bd928eba 8443 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8444 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8445 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8446 /* PowerPC 740 v1.0 (G3) */
8447 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8448 /* PowerPC 750 v1.0 (G3) */
8449 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8450 /* PowerPC 740 v2.0 (G3) */
bd928eba 8451 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8452 /* PowerPC 750 v2.0 (G3) */
bd928eba 8453 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8454 /* PowerPC 740 v2.1 (G3) */
bd928eba 8455 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8456 /* PowerPC 750 v2.1 (G3) */
bd928eba 8457 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8458 /* PowerPC 740 v2.2 (G3) */
bd928eba 8459 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8460 /* PowerPC 750 v2.2 (G3) */
bd928eba 8461 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8462 /* PowerPC 740 v3.0 (G3) */
bd928eba 8463 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8464 /* PowerPC 750 v3.0 (G3) */
bd928eba 8465 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8466 /* PowerPC 740 v3.1 (G3) */
bd928eba 8467 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8468 /* PowerPC 750 v3.1 (G3) */
bd928eba 8469 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8470 /* PowerPC 740E (G3) */
bd928eba
JM		 8471 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8472 /* PowerPC 750E (G3) */
8473 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8474 /* PowerPC 740P (G3) */
bd928eba 8475 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8476 /* PowerPC 750P (G3) */
bd928eba 8477 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8478 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8479 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8480 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8481 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8482 /* PowerPC 750CL v1.0 */
8483 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8484 /* PowerPC 750CL v2.0 */
8485 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8486 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8487 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8488 /* PowerPC 750CX v1.0 (G3 embedded) */
8489 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8490 /* PowerPC 750CX v2.1 (G3 embedded) */
8491 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8492 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8493 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8494 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8495 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8496 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8497 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8498 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8499 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8500 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8501 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8502 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8503 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8504 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8505 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8506 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8507 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8508 /* PowerPC 750CXe v3.0 (G3 embedded) */
8509 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8510 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8511 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8512 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8513 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8514 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8515 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8516 /* PowerPC 750FL (G3 embedded) */
80d11f44 8517 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8518 /* PowerPC 750FX (G3 embedded) */
80d11f44 8519 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8520 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8521 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8522 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8523 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8524 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8525 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8526 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8527 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8528 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8529 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8530 /* PowerPC 750GL (G3 embedded) */
bd928eba 8531 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8532 /* PowerPC 750GX (G3 embedded) */
bd928eba 8533 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8534 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8535 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8536 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8537 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8538 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8539 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8540 /* PowerPC 750L (G3 embedded) */
bd928eba 8541 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8542 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8543 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8544 /* PowerPC 750L v2.0 (G3 embedded) */
8545 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8546 /* PowerPC 750L v2.1 (G3 embedded) */
8547 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8548 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8549 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8550 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8551 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8552 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8553 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8554 /* Generic PowerPC 745 */
bd928eba 8555 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8556 /* Generic PowerPC 755 */
bd928eba 8557 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8558 /* Code name for PowerPC 745/755 */
bd928eba 8559 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8560 /* PowerPC 745 v1.0 */
bd928eba 8561 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8562 /* PowerPC 755 v1.0 */
bd928eba 8563 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8564 /* PowerPC 745 v1.1 */
bd928eba 8565 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8566 /* PowerPC 755 v1.1 */
bd928eba 8567 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8568 /* PowerPC 745 v2.0 */
bd928eba 8569 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8570 /* PowerPC 755 v2.0 */
bd928eba 8571 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8572 /* PowerPC 745 v2.1 */
bd928eba 8573 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8574 /* PowerPC 755 v2.1 */
bd928eba 8575 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8576 /* PowerPC 745 v2.2 */
bd928eba 8577 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8578 /* PowerPC 755 v2.2 */
bd928eba 8579 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8580 /* PowerPC 745 v2.3 */
bd928eba 8581 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8582 /* PowerPC 755 v2.3 */
bd928eba 8583 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8584 /* PowerPC 745 v2.4 */
bd928eba 8585 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8586 /* PowerPC 755 v2.4 */
bd928eba 8587 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8588 /* PowerPC 745 v2.5 */
bd928eba 8589 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8590 /* PowerPC 755 v2.5 */
bd928eba 8591 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8592 /* PowerPC 745 v2.6 */
bd928eba 8593 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8594 /* PowerPC 755 v2.6 */
bd928eba 8595 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8596 /* PowerPC 745 v2.7 */
bd928eba 8597 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8598 /* PowerPC 755 v2.7 */
bd928eba 8599 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8600 /* PowerPC 745 v2.8 */
bd928eba 8601 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8602 /* PowerPC 755 v2.8 */
bd928eba 8603 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8604#if defined (TODO)
8605 /* PowerPC 745P (G3) */
bd928eba 8606 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8607 /* PowerPC 755P (G3) */
bd928eba 8608 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8609#endif
8610 /* PowerPC 74xx family */
8611 /* PowerPC 7400 (G4) */
80d11f44 8612 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8613 /* Code name for PowerPC 7400 */
80d11f44 8614 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8615 /* PowerPC 74xx is also well known as G4 */
80d11f44 8616 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8617 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8618 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8619 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8620 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8621 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8622 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8623 /* PowerPC 7400 v2.1 (G4) */
8624 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8625 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8626 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8627 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8628 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8629 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8630 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8631 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8632 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8633 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8634 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8635 /* PowerPC 7410 (G4) */
80d11f44 8636 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8637 /* Code name for PowerPC 7410 */
80d11f44 8638 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8639 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8640 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8641 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8642 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8643 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8644 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8645 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8646 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8647 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8648 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8649 /* PowerPC 7448 (G4) */
80d11f44 8650 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8651 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8652 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8653 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8654 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8655 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8656 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8657 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8658 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8659 /* PowerPC 7450 (G4) */
80d11f44 8660 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8661 /* Code name for PowerPC 7450 */
80d11f44 8662 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8663 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8664 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8665 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8666 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8667 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8668 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8669 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8670 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8671 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8672 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8673 /* PowerPC 7441 (G4) */
80d11f44 8674 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8675 /* PowerPC 7451 (G4) */
80d11f44 8676 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8677 /* PowerPC 7441 v2.1 (G4) */
8678 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8679 /* PowerPC 7441 v2.3 (G4) */
8680 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8681 /* PowerPC 7451 v2.3 (G4) */
8682 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8683 /* PowerPC 7441 v2.10 (G4) */
8684 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8685 /* PowerPC 7451 v2.10 (G4) */
8686 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8687 /* PowerPC 7445 (G4) */
80d11f44 8688 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8689 /* PowerPC 7455 (G4) */
80d11f44 8690 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8691 /* Code name for PowerPC 7445/7455 */
80d11f44 8692 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8693 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8694 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8695 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8696 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8697 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8698 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8699 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8700 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8701 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8702 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8703 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8704 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8705 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8706 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8707 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8708 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8709 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8710 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8711 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8712 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8713 /* PowerPC 7447 (G4) */
80d11f44 8714 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8715 /* PowerPC 7457 (G4) */
80d11f44 8716 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 8717 /* Code name for PowerPC 7447/7457 */
80d11f44 8718 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 8719 /* PowerPC 7447 v1.0 (G4) */
80d11f44 8720 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 8721 /* PowerPC 7457 v1.0 (G4) */
80d11f44 8722 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 8723 /* PowerPC 7447 v1.1 (G4) */
80d11f44 8724 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 8725 /* PowerPC 7457 v1.1 (G4) */
80d11f44 8726 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 8727 /* PowerPC 7457 v1.2 (G4) */
80d11f44 8728 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 8729 /* PowerPC 7447A (G4) */
8730 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8731 /* PowerPC 7457A (G4) */
8732 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8733 /* PowerPC 7447A v1.0 (G4) */
8734 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8735 /* PowerPC 7457A v1.0 (G4) */
8736 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8737 /* Code name for PowerPC 7447A/7457A */
8738 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8739 /* PowerPC 7447A v1.1 (G4) */
8740 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8741 /* PowerPC 7457A v1.1 (G4) */
8742 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8743 /* PowerPC 7447A v1.2 (G4) */
8744 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8745 /* PowerPC 7457A v1.2 (G4) */
8746 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 8747 /* 64 bits PowerPC */
8748#if defined (TARGET_PPC64)
a750fc0b 8749 /* PowerPC 620 */
80d11f44 8750 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 8751 /* Code name for PowerPC 620 */
8752 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 8753#if defined (TODO)
a750fc0b 8754 /* PowerPC 630 (POWER3) */
80d11f44
JM		 8755 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8756 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 8757 /* Code names for POWER3 */
8758 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8759 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 8760#endif
3a607854 8761#if defined (TODO)
a750fc0b 8762 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 8763 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8764 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 8765#endif
8766#if defined (TODO)
a750fc0b 8767 /* POWER4 */
80d11f44 8768 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 8769#endif
3a607854 8770#if defined (TODO)
a750fc0b 8771 /* POWER4p */
80d11f44 8772 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 8773#endif
2662a059 8774#if defined (TODO)
a750fc0b 8775 /* POWER5 */
80d11f44 8776 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 8777 /* POWER5GR */
80d11f44 8778 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 8779#endif
3a607854 8780#if defined (TODO)
a750fc0b 8781 /* POWER5+ */
80d11f44 8782 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 8783 /* POWER5GS */
80d11f44 8784 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 8785#endif
2662a059 8786#if defined (TODO)
a750fc0b 8787 /* POWER6 */
80d11f44 8788 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 8789 /* POWER6 running in POWER5 mode */
80d11f44 8790 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 8791 /* POWER6A */
80d11f44 8792 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 8793#endif
a750fc0b 8794 /* PowerPC 970 */
80d11f44 8795 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 8796 /* PowerPC 970FX (G5) */
80d11f44 8797 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 8798 /* PowerPC 970FX v1.0 (G5) */
80d11f44 8799 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 8800 /* PowerPC 970FX v2.0 (G5) */
80d11f44 8801 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 8802 /* PowerPC 970FX v2.1 (G5) */
80d11f44 8803 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 8804 /* PowerPC 970FX v3.0 (G5) */
80d11f44 8805 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 8806 /* PowerPC 970FX v3.1 (G5) */
80d11f44 8807 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 8808 /* PowerPC 970GX (G5) */
80d11f44 8809 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 8810 /* PowerPC 970MP */
80d11f44 8811 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 8812 /* PowerPC 970MP v1.0 */
80d11f44 8813 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 8814 /* PowerPC 970MP v1.1 */
80d11f44 8815 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 8816#if defined (TODO)
a750fc0b 8817 /* PowerPC Cell */
80d11f44 8818 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 8819#endif
8820#if defined (TODO)
a750fc0b 8821 /* PowerPC Cell v1.0 */
80d11f44 8822 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 8823#endif
8824#if defined (TODO)
a750fc0b 8825 /* PowerPC Cell v2.0 */
80d11f44 8826 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 8827#endif
8828#if defined (TODO)
a750fc0b 8829 /* PowerPC Cell v3.0 */
80d11f44 8830 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 8831#endif
3a607854 8832#if defined (TODO)
a750fc0b 8833 /* PowerPC Cell v3.1 */
80d11f44 8834 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 8835#endif
8836#if defined (TODO)
a750fc0b 8837 /* PowerPC Cell v3.2 */
80d11f44 8838 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 8839#endif
8840#if defined (TODO)
a750fc0b
JM		 8841 /* RS64 (Apache/A35) */
8842 /* This one seems to support the whole POWER2 instruction set
8843 * and the PowerPC 64 one.
8844 */
8845 /* What about A10 & A30 ? */
80d11f44
JM		 8846 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8847 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8848 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 8849#endif
8850#if defined (TODO)
a750fc0b 8851 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 8852 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8853 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8854 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 8855#endif
8856#if defined (TODO)
a750fc0b 8857 /* RS64-III (Pulsar) */
80d11f44
JM		 8858 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8859 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 8860#endif
8861#if defined (TODO)
a750fc0b 8862 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 8863 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8864 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8865 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8866 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 8867#endif
a750fc0b
JM		 8868#endif /* defined (TARGET_PPC64) */
8869 /* POWER */
3fc6c082 8870#if defined (TODO)
a750fc0b 8871 /* Original POWER */
80d11f44
JM		 8872 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8873 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8874 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8875 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8876 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 8877#endif
8878#if defined (TODO)
a750fc0b 8879 /* POWER2 */
80d11f44
JM		 8880 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8881 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8882 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 8883#endif
8884 /* PA semi cores */
8885#if defined (TODO)
8886 /* PA PA6T */
80d11f44 8887 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 8888#endif
8889 /* Generic PowerPCs */
8890#if defined (TARGET_PPC64)
80d11f44 8891 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 8892#endif
80d11f44
JM		 8893 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8894 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 8895 /* Fallback */
80d11f44 8896 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 8897};
8898
8899/*****************************************************************************/
8900/* Generic CPU instanciation routine */
c227f099 8901static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8902{
8903#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 8904 int i;
8905
a750fc0b 8906 env->irq_inputs = NULL;
e1833e1f
JM		 8907 /* Set all exception vectors to an invalid address */
8908 for (i = 0; i < POWERPC_EXCP_NB; i++)
8909 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 8910 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 8911 env->ivor_mask = 0x00000000;
8912 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 8913 /* Default MMU definitions */
8914 env->nb_BATs = 0;
8915 env->nb_tlb = 0;
8916 env->nb_ways = 0;
f2e63a42 8917#endif
a750fc0b
JM		 8918 /* Register SPR common to all PowerPC implementations */
8919 gen_spr_generic(env);
8920 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 8921 /* Linux permits userspace to read PVR */
8922#if defined(CONFIG_LINUX_USER)
8923 &spr_read_generic,
8924#else
8925 SPR_NOACCESS,
8926#endif
8927 SPR_NOACCESS,
a750fc0b
JM		 8928 &spr_read_generic, SPR_NOACCESS,
8929 def->pvr);
80d11f44
JM		 8930 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8931 if (def->svr != POWERPC_SVR_NONE) {
8932 if (def->svr & POWERPC_SVR_E500) {
8933 spr_register(env, SPR_E500_SVR, "SVR",
8934 SPR_NOACCESS, SPR_NOACCESS,
8935 &spr_read_generic, SPR_NOACCESS,
8936 def->svr & ~POWERPC_SVR_E500);
8937 } else {
8938 spr_register(env, SPR_SVR, "SVR",
8939 SPR_NOACCESS, SPR_NOACCESS,
8940 &spr_read_generic, SPR_NOACCESS,
8941 def->svr);
8942 }
8943 }
a750fc0b
JM		 8944 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8945 (*def->init_proc)(env);
fc1c67bc
BS		 8946#if !defined(CONFIG_USER_ONLY)
8947 env->excp_prefix = env->hreset_excp_prefix;
8948#endif
25ba3a68
JM		 8949 /* MSR bits & flags consistency checks */
8950 if (env->msr_mask & (1 << 25)) {
8951 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8952 case POWERPC_FLAG_SPE:
8953 case POWERPC_FLAG_VRE:
8954 break;
8955 default:
8956 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8957 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8958 exit(1);
8959 }
8960 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8961 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8962 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8963 exit(1);
8964 }
8965 if (env->msr_mask & (1 << 17)) {
8966 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8967 case POWERPC_FLAG_TGPR:
8968 case POWERPC_FLAG_CE:
8969 break;
8970 default:
8971 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8972 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8973 exit(1);
8974 }
8975 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8976 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8977 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8978 exit(1);
8979 }
8980 if (env->msr_mask & (1 << 10)) {
8981 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8982 POWERPC_FLAG_UBLE)) {
8983 case POWERPC_FLAG_SE:
8984 case POWERPC_FLAG_DWE:
8985 case POWERPC_FLAG_UBLE:
8986 break;
8987 default:
8988 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8989 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8990 "POWERPC_FLAG_UBLE\n");
8991 exit(1);
8992 }
8993 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8994 POWERPC_FLAG_UBLE)) {
8995 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8996 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8997 "POWERPC_FLAG_UBLE\n");
8998 exit(1);
8999 }
9000 if (env->msr_mask & (1 << 9)) {
9001 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9002 case POWERPC_FLAG_BE:
9003 case POWERPC_FLAG_DE:
9004 break;
9005 default:
9006 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9007 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9008 exit(1);
9009 }
9010 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9011 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9012 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9013 exit(1);
9014 }
9015 if (env->msr_mask & (1 << 2)) {
9016 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9017 case POWERPC_FLAG_PX:
9018 case POWERPC_FLAG_PMM:
9019 break;
9020 default:
9021 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9022 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9023 exit(1);
9024 }
9025 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9026 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9027 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9028 exit(1);
9029 }
4018bae9
JM		 9030 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9031 fprintf(stderr, "PowerPC flags inconsistency\n"
9032 "Should define the time-base and decrementer clock source\n");
9033 exit(1);
9034 }
a750fc0b 9035 /* Allocate TLBs buffer when needed */
f2e63a42 9036#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9037 if (env->nb_tlb != 0) {
9038 int nb_tlb = env->nb_tlb;
9039 if (env->id_tlbs != 0)
9040 nb_tlb *= 2;
c227f099 9041 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
a750fc0b
JM		 9042 /* Pre-compute some useful values */
9043 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9044 }
a750fc0b
JM		 9045 if (env->irq_inputs == NULL) {
9046 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9047 " Attempt Qemu to crash very soon !\n");
9048 }
9049#endif
2f462816
JM		 9050 if (env->check_pow == NULL) {
9051 fprintf(stderr, "WARNING: no power management check handler "
9052 "registered.\n"
9053 " Attempt Qemu to crash very soon !\n");
9054 }
a750fc0b
JM		 9055}
9056
9057#if defined(PPC_DUMP_CPU)
9058static void dump_ppc_sprs (CPUPPCState *env)
9059{
9060 ppc_spr_t *spr;
9061#if !defined(CONFIG_USER_ONLY)
9062 uint32_t sr, sw;
9063#endif
9064 uint32_t ur, uw;
9065 int i, j, n;
9066
9067 printf("Special purpose registers:\n");
9068 for (i = 0; i < 32; i++) {
9069 for (j = 0; j < 32; j++) {
9070 n = (i << 5) | j;
9071 spr = &env->spr_cb[n];
9072 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9073 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9074#if !defined(CONFIG_USER_ONLY)
9075 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9076 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9077 if (sw || sr || uw || ur) {
9078 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9079 (i << 5) | j, (i << 5) | j, spr->name,
9080 sw ? 'w' : '-', sr ? 'r' : '-',
9081 uw ? 'w' : '-', ur ? 'r' : '-');
9082 }
9083#else
9084 if (uw || ur) {
9085 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9086 (i << 5) | j, (i << 5) | j, spr->name,
9087 uw ? 'w' : '-', ur ? 'r' : '-');
9088 }
9089#endif
9090 }
9091 }
9092 fflush(stdout);
9093 fflush(stderr);
9094}
9095#endif
9096
9097/*****************************************************************************/
9098#include <stdlib.h>
9099#include <string.h>
9100
a750fc0b
JM		 9101/* Opcode types */
9102enum {
9103 PPC_DIRECT = 0, /* Opcode routine */
9104 PPC_INDIRECT = 1, /* Indirect opcode table */
9105};
9106
9107static inline int is_indirect_opcode (void *handler)
9108{
9109 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9110}
9111
c227f099 9112static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9113{
c227f099 9114 return (opc_handler_t **)((unsigned long)handler & ~3);
a750fc0b
JM		 9115}
9116
9117/* Instruction table creation */
9118/* Opcodes tables creation */
c227f099 9119static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9120{
9121 int i;
9122
9123 for (i = 0; i < len; i++)
9124 table[i] = &invalid_handler;
9125}
9126
c227f099 9127static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9128{
c227f099 9129 opc_handler_t **tmp;
a750fc0b 9130
c227f099 9131 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9132 fill_new_table(tmp, 0x20);
c227f099 9133 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
a750fc0b
JM		 9134
9135 return 0;
9136}
9137
c227f099
AL		 9138static int insert_in_table (opc_handler_t **table, unsigned char idx,
9139 opc_handler_t *handler)
a750fc0b
JM		 9140{
9141 if (table[idx] != &invalid_handler)
9142 return -1;
9143 table[idx] = handler;
9144
9145 return 0;
9146}
9147
c227f099
AL		 9148static int register_direct_insn (opc_handler_t **ppc_opcodes,
9149 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9150{
9151 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9152 printf("*** ERROR: opcode %02x already assigned in main "
9153 "opcode table\n", idx);
4c1b1bfe
JM		 9154#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9155 printf(" Registered handler '%s' - new handler '%s'\n",
9156 ppc_opcodes[idx]->oname, handler->oname);
9157#endif
a750fc0b
JM		 9158 return -1;
9159 }
9160
9161 return 0;
9162}
9163
c227f099 9164static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9165 unsigned char idx1, unsigned char idx2,
c227f099 9166 opc_handler_t *handler)
a750fc0b
JM		 9167{
9168 if (table[idx1] == &invalid_handler) {
9169 if (create_new_table(table, idx1) < 0) {
9170 printf("*** ERROR: unable to create indirect table "
9171 "idx=%02x\n", idx1);
9172 return -1;
9173 }
9174 } else {
9175 if (!is_indirect_opcode(table[idx1])) {
9176 printf("*** ERROR: idx %02x already assigned to a direct "
9177 "opcode\n", idx1);
4c1b1bfe
JM		 9178#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9179 printf(" Registered handler '%s' - new handler '%s'\n",
9180 ind_table(table[idx1])[idx2]->oname, handler->oname);
9181#endif
a750fc0b
JM		 9182 return -1;
9183 }
3a607854 9184 }
a750fc0b
JM		 9185 if (handler != NULL &&
9186 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9187 printf("*** ERROR: opcode %02x already assigned in "
9188 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9189#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9190 printf(" Registered handler '%s' - new handler '%s'\n",
9191 ind_table(table[idx1])[idx2]->oname, handler->oname);
9192#endif
a750fc0b 9193 return -1;
3a607854 9194 }
a750fc0b
JM		 9195
9196 return 0;
9197}
9198
c227f099 9199static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9200 unsigned char idx1, unsigned char idx2,
c227f099 9201 opc_handler_t *handler)
a750fc0b
JM		 9202{
9203 int ret;
9204
9205 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9206
9207 return ret;
9208}
9209
c227f099 9210static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9211 unsigned char idx1, unsigned char idx2,
c227f099 9212 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9213{
9214 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9215 printf("*** ERROR: unable to join indirect table idx "
9216 "[%02x-%02x]\n", idx1, idx2);
9217 return -1;
9218 }
9219 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9220 handler) < 0) {
9221 printf("*** ERROR: unable to insert opcode "
9222 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9223 return -1;
9224 }
9225
9226 return 0;
9227}
9228
c227f099 9229static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9230{
9231 if (insn->opc2 != 0xFF) {
9232 if (insn->opc3 != 0xFF) {
9233 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9234 insn->opc3, &insn->handler) < 0)
9235 return -1;
9236 } else {
9237 if (register_ind_insn(ppc_opcodes, insn->opc1,
9238 insn->opc2, &insn->handler) < 0)
9239 return -1;
9240 }
9241 } else {
9242 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9243 return -1;
9244 }
9245
9246 return 0;
9247}
9248
c227f099 9249static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9250{
9251 int i, count, tmp;
9252
9253 for (i = 0, count = 0; i < len; i++) {
9254 /* Consistency fixup */
9255 if (table[i] == NULL)
9256 table[i] = &invalid_handler;
9257 if (table[i] != &invalid_handler) {
9258 if (is_indirect_opcode(table[i])) {
c227f099 9259 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9260 if (tmp == 0) {
9261 free(table[i]);
9262 table[i] = &invalid_handler;
9263 } else {
9264 count++;
9265 }
9266 } else {
9267 count++;
9268 }
9269 }
9270 }
9271
9272 return count;
9273}
9274
c227f099 9275static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9276{
c227f099 9277 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9278 printf("*** WARNING: no opcode defined !\n");
9279}
9280
9281/*****************************************************************************/
c227f099 9282static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b 9283{
c227f099 9284 opcode_t *opc;
a750fc0b
JM		 9285
9286 fill_new_table(env->opcodes, 0x40);
5c55ff99 9287 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
a750fc0b
JM		 9288 if ((opc->handler.type & def->insns_flags) != 0) {
9289 if (register_insn(env->opcodes, opc) < 0) {
9290 printf("*** ERROR initializing PowerPC instruction "
9291 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9292 opc->opc3);
9293 return -1;
9294 }
9295 }
9296 }
c227f099 9297 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9298 fflush(stdout);
9299 fflush(stderr);
9300
9301 return 0;
9302}
9303
9304#if defined(PPC_DUMP_CPU)
25ba3a68 9305static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9306{
c227f099 9307 opc_handler_t **table, *handler;
b55266b5 9308 const char *p, *q;
a750fc0b
JM		 9309 uint8_t opc1, opc2, opc3;
9310
9311 printf("Instructions set:\n");
9312 /* opc1 is 6 bits long */
9313 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9314 table = env->opcodes;
9315 handler = table[opc1];
9316 if (is_indirect_opcode(handler)) {
9317 /* opc2 is 5 bits long */
9318 for (opc2 = 0; opc2 < 0x20; opc2++) {
9319 table = env->opcodes;
9320 handler = env->opcodes[opc1];
9321 table = ind_table(handler);
9322 handler = table[opc2];
9323 if (is_indirect_opcode(handler)) {
9324 table = ind_table(handler);
9325 /* opc3 is 5 bits long */
9326 for (opc3 = 0; opc3 < 0x20; opc3++) {
9327 handler = table[opc3];
9328 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9329 /* Special hack to properly dump SPE insns */
9330 p = strchr(handler->oname, '_');
9331 if (p == NULL) {
9332 printf("INSN: %02x %02x %02x (%02d %04d) : "
9333 "%s\n",
9334 opc1, opc2, opc3, opc1,
9335 (opc3 << 5) | opc2,
9336 handler->oname);
9337 } else {
9338 q = "speundef";
9339 if ((p - handler->oname) != strlen(q) ||
9340 memcmp(handler->oname, q, strlen(q)) != 0) {
9341 /* First instruction */
9342 printf("INSN: %02x %02x %02x (%02d %04d) : "
9343 "%.*s\n",
9344 opc1, opc2 << 1, opc3, opc1,
9345 (opc3 << 6) | (opc2 << 1),
9346 (int)(p - handler->oname),
9347 handler->oname);
9348 }
9349 if (strcmp(p + 1, q) != 0) {
9350 /* Second instruction */
9351 printf("INSN: %02x %02x %02x (%02d %04d) : "
9352 "%s\n",
9353 opc1, (opc2 << 1) | 1, opc3, opc1,
9354 (opc3 << 6) | (opc2 << 1) | 1,
9355 p + 1);
9356 }
9357 }
a750fc0b
JM		 9358 }
9359 }
9360 } else {
9361 if (handler->handler != &gen_invalid) {
9362 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9363 opc1, opc2, opc1, opc2, handler->oname);
9364 }
9365 }
9366 }
9367 } else {
9368 if (handler->handler != &gen_invalid) {
9369 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9370 opc1, opc1, handler->oname);
9371 }
9372 }
9373 }
9374}
3a607854 9375#endif
a750fc0b 9376
24951522
AJ		 9377static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9378{
9379 if (n < 32) {
9380 stfq_p(mem_buf, env->fpr[n]);
9381 return 8;
9382 }
9383 if (n == 32) {
9384 /* FPSCR not implemented */
9385 memset(mem_buf, 0, 4);
9386 return 4;
9387 }
9388 return 0;
9389}
9390
9391static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9392{
9393 if (n < 32) {
9394 env->fpr[n] = ldfq_p(mem_buf);
9395 return 8;
9396 }
9397 if (n == 32) {
9398 /* FPSCR not implemented */
9399 return 4;
9400 }
9401 return 0;
9402}
9403
b4f8d821
AJ		 9404static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9405{
9406 if (n < 32) {
e2542fe2 9407#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9408 stq_p(mem_buf, env->avr[n].u64[0]);
9409 stq_p(mem_buf+8, env->avr[n].u64[1]);
9410#else
9411 stq_p(mem_buf, env->avr[n].u64[1]);
9412 stq_p(mem_buf+8, env->avr[n].u64[0]);
9413#endif
9414 return 16;
9415 }
70976a79 9416 if (n == 32) {
b4f8d821
AJ		 9417 stl_p(mem_buf, env->vscr);
9418 return 4;
9419 }
70976a79 9420 if (n == 33) {
b4f8d821
AJ		 9421 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9422 return 4;
9423 }
9424 return 0;
9425}
9426
9427static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9428{
9429 if (n < 32) {
e2542fe2 9430#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9431 env->avr[n].u64[0] = ldq_p(mem_buf);
9432 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9433#else
9434 env->avr[n].u64[1] = ldq_p(mem_buf);
9435 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9436#endif
9437 return 16;
9438 }
70976a79 9439 if (n == 32) {
b4f8d821
AJ		 9440 env->vscr = ldl_p(mem_buf);
9441 return 4;
9442 }
70976a79 9443 if (n == 33) {
b4f8d821
AJ		 9444 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9445 return 4;
9446 }
9447 return 0;
9448}
9449
688890f7
AJ		 9450static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9451{
9452 if (n < 32) {
9453#if defined(TARGET_PPC64)
9454 stl_p(mem_buf, env->gpr[n] >> 32);
9455#else
9456 stl_p(mem_buf, env->gprh[n]);
9457#endif
9458 return 4;
9459 }
70976a79 9460 if (n == 32) {
688890f7
AJ		 9461 stq_p(mem_buf, env->spe_acc);
9462 return 8;
9463 }
70976a79 9464 if (n == 33) {
d34defbc 9465 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9466 return 4;
9467 }
9468 return 0;
9469}
9470
9471static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9472{
9473 if (n < 32) {
9474#if defined(TARGET_PPC64)
9475 target_ulong lo = (uint32_t)env->gpr[n];
9476 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9477 env->gpr[n] = lo | hi;
9478#else
9479 env->gprh[n] = ldl_p(mem_buf);
9480#endif
9481 return 4;
9482 }
70976a79 9483 if (n == 32) {
688890f7
AJ		 9484 env->spe_acc = ldq_p(mem_buf);
9485 return 8;
9486 }
70976a79 9487 if (n == 33) {
d34defbc 9488 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9489 return 4;
9490 }
9491 return 0;
9492}
9493
c227f099 9494int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9495{
9496 env->msr_mask = def->msr_mask;
9497 env->mmu_model = def->mmu_model;
9498 env->excp_model = def->excp_model;
9499 env->bus_model = def->bus_model;
c29b735c 9500 env->insns_flags = def->insns_flags;
d26bfc9a 9501 env->flags = def->flags;
237c0af0 9502 env->bfd_mach = def->bfd_mach;
2f462816 9503 env->check_pow = def->check_pow;
a750fc0b
JM		 9504 if (create_ppc_opcodes(env, def) < 0)
9505 return -1;
9506 init_ppc_proc(env, def);
24951522
AJ		 9507
9508 if (def->insns_flags & PPC_FLOAT) {
9509 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9510 33, "power-fpu.xml", 0);
9511 }
b4f8d821
AJ		 9512 if (def->insns_flags & PPC_ALTIVEC) {
9513 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9514 34, "power-altivec.xml", 0);
9515 }
40569b7e 9516 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9517 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9518 34, "power-spe.xml", 0);
9519 }
9520
a750fc0b 9521#if defined(PPC_DUMP_CPU)
3a607854 9522 {
b55266b5 9523 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9524 switch (env->mmu_model) {
9525 case POWERPC_MMU_32B:
9526 mmu_model = "PowerPC 32";
9527 break;
a750fc0b
JM		 9528 case POWERPC_MMU_SOFT_6xx:
9529 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9530 break;
9531 case POWERPC_MMU_SOFT_74xx:
9532 mmu_model = "PowerPC 74xx with software driven TLBs";
9533 break;
9534 case POWERPC_MMU_SOFT_4xx:
9535 mmu_model = "PowerPC 4xx with software driven TLBs";
9536 break;
9537 case POWERPC_MMU_SOFT_4xx_Z:
9538 mmu_model = "PowerPC 4xx with software driven TLBs "
9539 "and zones protections";
9540 break;
b4095fed
JM		 9541 case POWERPC_MMU_REAL:
9542 mmu_model = "PowerPC real mode only";
9543 break;
9544 case POWERPC_MMU_MPC8xx:
9545 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9546 break;
9547 case POWERPC_MMU_BOOKE:
9548 mmu_model = "PowerPC BookE";
9549 break;
9550 case POWERPC_MMU_BOOKE_FSL:
9551 mmu_model = "PowerPC BookE FSL";
9552 break;
b4095fed
JM		 9553 case POWERPC_MMU_601:
9554 mmu_model = "PowerPC 601";
9555 break;
00af685f
JM		 9556#if defined (TARGET_PPC64)
9557 case POWERPC_MMU_64B:
9558 mmu_model = "PowerPC 64";
9559 break;
add78955
JM		 9560 case POWERPC_MMU_620:
9561 mmu_model = "PowerPC 620";
9562 break;
00af685f 9563#endif
a750fc0b
JM		 9564 default:
9565 mmu_model = "Unknown or invalid";
9566 break;
9567 }
9568 switch (env->excp_model) {
9569 case POWERPC_EXCP_STD:
9570 excp_model = "PowerPC";
9571 break;
9572 case POWERPC_EXCP_40x:
9573 excp_model = "PowerPC 40x";
9574 break;
9575 case POWERPC_EXCP_601:
9576 excp_model = "PowerPC 601";
9577 break;
9578 case POWERPC_EXCP_602:
9579 excp_model = "PowerPC 602";
9580 break;
9581 case POWERPC_EXCP_603:
9582 excp_model = "PowerPC 603";
9583 break;
9584 case POWERPC_EXCP_603E:
9585 excp_model = "PowerPC 603e";
9586 break;
9587 case POWERPC_EXCP_604:
9588 excp_model = "PowerPC 604";
9589 break;
9590 case POWERPC_EXCP_7x0:
9591 excp_model = "PowerPC 740/750";
9592 break;
9593 case POWERPC_EXCP_7x5:
9594 excp_model = "PowerPC 745/755";
9595 break;
9596 case POWERPC_EXCP_74xx:
9597 excp_model = "PowerPC 74xx";
9598 break;
a750fc0b
JM		 9599 case POWERPC_EXCP_BOOKE:
9600 excp_model = "PowerPC BookE";
9601 break;
00af685f
JM		 9602#if defined (TARGET_PPC64)
9603 case POWERPC_EXCP_970:
9604 excp_model = "PowerPC 970";
9605 break;
9606#endif
a750fc0b
JM		 9607 default:
9608 excp_model = "Unknown or invalid";
9609 break;
9610 }
9611 switch (env->bus_model) {
9612 case PPC_FLAGS_INPUT_6xx:
9613 bus_model = "PowerPC 6xx";
9614 break;
9615 case PPC_FLAGS_INPUT_BookE:
9616 bus_model = "PowerPC BookE";
9617 break;
9618 case PPC_FLAGS_INPUT_405:
9619 bus_model = "PowerPC 405";
9620 break;
a750fc0b
JM		 9621 case PPC_FLAGS_INPUT_401:
9622 bus_model = "PowerPC 401/403";
9623 break;
b4095fed
JM		 9624 case PPC_FLAGS_INPUT_RCPU:
9625 bus_model = "RCPU / MPC8xx";
9626 break;
00af685f
JM		 9627#if defined (TARGET_PPC64)
9628 case PPC_FLAGS_INPUT_970:
9629 bus_model = "PowerPC 970";
9630 break;
9631#endif
a750fc0b
JM		 9632 default:
9633 bus_model = "Unknown or invalid";
9634 break;
9635 }
9636 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9637 " MMU model : %s\n",
9638 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9639#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9640 if (env->tlb != NULL) {
9641 printf(" %d %s TLB in %d ways\n",
9642 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9643 env->nb_ways);
9644 }
f2e63a42 9645#endif
a750fc0b
JM		 9646 printf(" Exceptions model : %s\n"
9647 " Bus model : %s\n",
9648 excp_model, bus_model);
25ba3a68
JM		 9649 printf(" MSR features :\n");
9650 if (env->flags & POWERPC_FLAG_SPE)
9651 printf(" signal processing engine enable"
9652 "\n");
9653 else if (env->flags & POWERPC_FLAG_VRE)
9654 printf(" vector processor enable\n");
9655 if (env->flags & POWERPC_FLAG_TGPR)
9656 printf(" temporary GPRs\n");
9657 else if (env->flags & POWERPC_FLAG_CE)
9658 printf(" critical input enable\n");
9659 if (env->flags & POWERPC_FLAG_SE)
9660 printf(" single-step trace mode\n");
9661 else if (env->flags & POWERPC_FLAG_DWE)
9662 printf(" debug wait enable\n");
9663 else if (env->flags & POWERPC_FLAG_UBLE)
9664 printf(" user BTB lock enable\n");
9665 if (env->flags & POWERPC_FLAG_BE)
9666 printf(" branch-step trace mode\n");
9667 else if (env->flags & POWERPC_FLAG_DE)
9668 printf(" debug interrupt enable\n");
9669 if (env->flags & POWERPC_FLAG_PX)
9670 printf(" inclusive protection\n");
9671 else if (env->flags & POWERPC_FLAG_PMM)
9672 printf(" performance monitor mark\n");
9673 if (env->flags == POWERPC_FLAG_NONE)
9674 printf(" none\n");
4018bae9
JM		 9675 printf(" Time-base/decrementer clock source: %s\n",
9676 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9677 }
9678 dump_ppc_insns(env);
9679 dump_ppc_sprs(env);
9680 fflush(stdout);
3a607854 9681#endif
a750fc0b
JM		 9682
9683 return 0;
9684}
3fc6c082 9685
c227f099 9686static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9687{
c227f099 9688 const ppc_def_t *ret;
ee4e83ed
JM		 9689 uint32_t pvr_rev;
9690 int i, best, match, best_match, max;
3fc6c082 9691
ee4e83ed 9692 ret = NULL;
b1503cda 9693 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9694 best = -1;
9695 pvr_rev = pvr & 0xFFFF;
9696 /* We want all specified bits to match */
9697 best_match = 32 - ctz32(pvr_rev);
068abdc8 9698 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9699 /* We check that the 16 higher bits are the same to ensure the CPU
9700 * model will be the choosen one.
9701 */
9702 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9703 /* We want as much as possible of the low-level 16 bits
9704 * to be the same but we allow inexact matches.
9705 */
9706 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9707 /* We check '>=' instead of '>' because the PPC_defs table
9708 * is ordered by increasing revision.
4c1b1bfe 9709 * Then, we will match the higher revision compatible
ee4e83ed
JM		 9710 * with the requested PVR
9711 */
9712 if (match >= best_match) {
9713 best = i;
9714 best_match = match;
9715 }
3fc6c082
FB		 9716 }
9717 }
ee4e83ed
JM		 9718 if (best != -1)
9719 ret = &ppc_defs[best];
9720
9721 return ret;
3fc6c082
FB		 9722}
9723
ee4e83ed 9724#include <ctype.h>
3fc6c082 9725
c227f099 9726const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed 9727{
c227f099 9728 const ppc_def_t *ret;
b55266b5 9729 const char *p;
ee4e83ed
JM		 9730 int i, max, len;
9731
9732 /* Check if the given name is a PVR */
9733 len = strlen(name);
9734 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9735 p = name + 2;
9736 goto check_pvr;
9737 } else if (len == 8) {
9738 p = name;
9739 check_pvr:
9740 for (i = 0; i < 8; i++) {
cd390083 9741 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 9742 break;
9743 }
9744 if (i == 8)
9745 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9746 }
9747 ret = NULL;
b1503cda 9748 max = ARRAY_SIZE(ppc_defs);
068abdc8 9749 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9750 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9751 ret = &ppc_defs[i];
9752 break;
3fc6c082
FB		 9753 }
9754 }
ee4e83ed
JM		 9755
9756 return ret;
3fc6c082
FB		 9757}
9758
9a78eead 9759void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
3fc6c082 9760{
068abdc8 9761 int i, max;
3fc6c082 9762
b1503cda 9763 max = ARRAY_SIZE(ppc_defs);
068abdc8 9764 for (i = 0; i < max; i++) {
a750fc0b
JM		 9765 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9766 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 9767 }
9768}
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