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kvm/powerpc: Add freescale pci controller's support
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
3fc6c082
FB		 19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
ee4e83ed 27#include "host-utils.h"
4e47ea67 28#include "gdbstub.h"
237c0af0 29
3fc6c082
FB		 30//#define PPC_DUMP_CPU
31//#define PPC_DEBUG_SPR
80d11f44
JM		 32//#define PPC_DUMP_SPR_ACCESSES
33#if defined(CONFIG_USER_ONLY)
34#define TODO_USER_ONLY 1
35#endif
3fc6c082
FB		 36
37struct ppc_def_t {
b55266b5 38 const char *name;
3fc6c082 39 uint32_t pvr;
80d11f44 40 uint32_t svr;
0487d6a8 41 uint64_t insns_flags;
3fc6c082 42 uint64_t msr_mask;
7820dbf3
JM		 43 powerpc_mmu_t mmu_model;
44 powerpc_excp_t excp_model;
45 powerpc_input_t bus_model;
d26bfc9a 46 uint32_t flags;
237c0af0 47 int bfd_mach;
a750fc0b 48 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 49 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 50};
51
e9df014c
JM		 52/* For user-mode emulation, we don't emulate any IRQ controller */
53#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 54#define PPC_IRQ_INIT_FN(name) \
55static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
56{ \
e9df014c
JM		 57}
58#else
a750fc0b 59#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 60void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
61#endif
a750fc0b 62
4e290a0b 63PPC_IRQ_INIT_FN(40x);
e9df014c 64PPC_IRQ_INIT_FN(6xx);
d0dfae6e 65PPC_IRQ_INIT_FN(970);
e9df014c 66
3fc6c082
FB		 67/* Generic callbacks:
68 * do nothing but store/retrieve spr value
69 */
45d827d2 70static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 71{
45d827d2
AJ		 72 gen_load_spr(cpu_gpr[gprn], sprn);
73#ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv t0 = tcg_const_i32(sprn);
76 gen_helper_load_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79#endif
a496775f
JM		 80}
81
45d827d2 82static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 83{
45d827d2
AJ		 84 gen_store_spr(sprn, cpu_gpr[gprn]);
85#ifdef PPC_DUMP_SPR_ACCESSES
86 {
87 TCGv t0 = tcg_const_i32(sprn);
88 gen_helper_store_dump_spr(t0);
89 tcg_temp_free_i32(t0);
90 }
04f20795 91#endif
45d827d2 92}
a496775f
JM		 93
94#if !defined(CONFIG_USER_ONLY)
45d827d2 95static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 96{
45d827d2
AJ		 97 TCGv t0 = tcg_temp_new();
98 TCGv t1 = tcg_temp_new();
99 gen_load_spr(t0, sprn);
100 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
101 tcg_gen_and_tl(t0, t0, t1);
102 gen_store_spr(sprn, t0);
103 tcg_temp_free(t0);
104 tcg_temp_free(t1);
a496775f
JM		 105}
106#endif
107
76a66253 108/* SPR common to all PowerPC */
3fc6c082 109/* XER */
45d827d2 110static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 111{
45d827d2 112 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 113}
114
45d827d2 115static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 116{
45d827d2 117 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 118}
119
120/* LR */
45d827d2 121static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 122{
45d827d2 123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 124}
125
45d827d2 126static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 127{
45d827d2 128 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 129}
130
131/* CTR */
45d827d2 132static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 133{
45d827d2 134 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 135}
136
45d827d2 137static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 138{
45d827d2 139 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 140}
141
142/* User read access to SPR */
143/* USPRx */
144/* UMMCRx */
145/* UPMCx */
146/* USIA */
147/* UDECR */
45d827d2 148static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 149{
45d827d2 150 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 151}
152
76a66253 153/* SPR common to all non-embedded PowerPC */
3fc6c082 154/* DECR */
76a66253 155#if !defined(CONFIG_USER_ONLY)
45d827d2 156static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 157{
45d827d2 158 gen_helper_load_decr(cpu_gpr[gprn]);
3fc6c082
FB		 159}
160
45d827d2 161static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 162{
45d827d2 163 gen_helper_store_decr(cpu_gpr[gprn]);
3fc6c082 164}
76a66253 165#endif
3fc6c082 166
76a66253 167/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 168/* Time base */
45d827d2 169static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 170{
45d827d2 171 gen_helper_load_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 172}
173
45d827d2 174static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 175{
45d827d2 176 gen_helper_load_tbu(cpu_gpr[gprn]);
3fc6c082
FB		 177}
178
a062e36c 179__attribute__ (( unused ))
45d827d2 180static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 181{
45d827d2 182 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 183}
184
185__attribute__ (( unused ))
45d827d2 186static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 187{
45d827d2 188 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 189}
190
76a66253 191#if !defined(CONFIG_USER_ONLY)
45d827d2 192static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 193{
45d827d2 194 gen_helper_store_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 195}
196
45d827d2 197static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 198{
45d827d2 199 gen_helper_store_tbu(cpu_gpr[gprn]);
3fc6c082 200}
a062e36c
JM		 201
202__attribute__ (( unused ))
45d827d2 203static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 204{
45d827d2 205 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 206}
207
208__attribute__ (( unused ))
45d827d2 209static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 210{
45d827d2 211 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 212}
76a66253 213#endif
3fc6c082 214
76a66253 215#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 216/* IBAT0U...IBAT0U */
217/* IBAT0L...IBAT7L */
45d827d2 218static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 219{
45d827d2 220 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 221}
222
45d827d2 223static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 224{
45d827d2 225 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 226}
227
45d827d2 228static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 229{
45d827d2
AJ		 230 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
231 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
232 tcg_temp_free_i32(t0);
3fc6c082
FB		 233}
234
45d827d2 235static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 236{
45d827d2
AJ		 237 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
238 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
239 tcg_temp_free_i32(t0);
3fc6c082
FB		 240}
241
45d827d2 242static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 243{
45d827d2
AJ		 244 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
245 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
246 tcg_temp_free_i32(t0);
3fc6c082
FB		 247}
248
45d827d2 249static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 250{
45d827d2
AJ		 251 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
252 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
253 tcg_temp_free_i32(t0);
3fc6c082
FB		 254}
255
256/* DBAT0U...DBAT7U */
257/* DBAT0L...DBAT7L */
45d827d2 258static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 259{
45d827d2 260 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 261}
262
45d827d2 263static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 264{
45d827d2 265 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 266}
267
45d827d2 268static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 269{
45d827d2
AJ		 270 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
271 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
272 tcg_temp_free_i32(t0);
3fc6c082
FB		 273}
274
45d827d2 275static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 276{
45d827d2
AJ		 277 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
278 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
279 tcg_temp_free_i32(t0);
3fc6c082
FB		 280}
281
45d827d2 282static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 283{
45d827d2
AJ		 284 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
285 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
286 tcg_temp_free_i32(t0);
3fc6c082
FB		 287}
288
45d827d2 289static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 290{
45d827d2
AJ		 291 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
292 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
293 tcg_temp_free_i32(t0);
3fc6c082
FB		 294}
295
296/* SDR1 */
45d827d2 297static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
3fc6c082 298{
45d827d2 299 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
3fc6c082
FB		 300}
301
45d827d2 302static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 303{
45d827d2 304 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 305}
306
76a66253
JM		 307/* 64 bits PowerPC specific SPRs */
308/* ASR */
578bb252 309#if defined(TARGET_PPC64)
2adab7d6
BS		 310static void spr_read_hior (void *opaque, int gprn, int sprn)
311{
312 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
313}
314
315static void spr_write_hior (void *opaque, int sprn, int gprn)
316{
317 TCGv t0 = tcg_temp_new();
318 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
319 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
320 tcg_temp_free(t0);
321}
322
45d827d2 323static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 324{
45d827d2 325 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 326}
327
45d827d2 328static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 329{
45d827d2 330 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 331}
332#endif
a750fc0b 333#endif
76a66253
JM		 334
335/* PowerPC 601 specific registers */
336/* RTC */
45d827d2 337static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 338{
45d827d2 339 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 340}
341
45d827d2 342static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 343{
45d827d2 344 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 345}
346
347#if !defined(CONFIG_USER_ONLY)
45d827d2 348static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 349{
45d827d2 350 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 351}
352
45d827d2 353static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 354{
45d827d2 355 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 356}
056401ea 357
45d827d2 358static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 359{
360 DisasContext *ctx = opaque;
361
45d827d2 362 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 363 /* Must stop the translation as endianness may have changed */
e06fcd75 364 gen_stop_exception(ctx);
056401ea 365}
76a66253
JM		 366#endif
367
368/* Unified bats */
369#if !defined(CONFIG_USER_ONLY)
45d827d2 370static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 371{
45d827d2 372 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 373}
374
45d827d2 375static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 376{
45d827d2
AJ		 377 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
378 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
379 tcg_temp_free_i32(t0);
76a66253
JM		 380}
381
45d827d2 382static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 383{
45d827d2
AJ		 384 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
385 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
386 tcg_temp_free_i32(t0);
76a66253
JM		 387}
388#endif
389
390/* PowerPC 40x specific registers */
391#if !defined(CONFIG_USER_ONLY)
45d827d2 392static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 393{
45d827d2 394 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 395}
396
45d827d2 397static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 398{
45d827d2 399 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 400}
401
45d827d2 402static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 403{
404 DisasContext *ctx = opaque;
405
45d827d2 406 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 407 /* We must stop translation as we may have rebooted */
e06fcd75 408 gen_stop_exception(ctx);
8ecc7913
JM		 409}
410
45d827d2 411static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 412{
45d827d2 413 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 414}
415
45d827d2 416static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 417{
45d827d2 418 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 419}
420
45d827d2 421static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 422{
45d827d2 423 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 424}
425#endif
426
427/* PowerPC 403 specific registers */
428/* PBL1 / PBU1 / PBL2 / PBU2 */
429#if !defined(CONFIG_USER_ONLY)
45d827d2 430static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 431{
45d827d2 432 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 433}
434
45d827d2 435static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 436{
45d827d2
AJ		 437 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
438 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
439 tcg_temp_free_i32(t0);
76a66253
JM		 440}
441
45d827d2 442static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 443{
45d827d2
AJ		 444 TCGv t0 = tcg_temp_new();
445 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
446 gen_store_spr(SPR_PIR, t0);
447 tcg_temp_free(t0);
3fc6c082 448}
76a66253 449#endif
3fc6c082 450
6f5d427d
JM		 451#if !defined(CONFIG_USER_ONLY)
452/* Callback used to write the exception vector base */
45d827d2 453static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 454{
45d827d2
AJ		 455 TCGv t0 = tcg_temp_new();
456 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
457 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
458 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
459 gen_store_spr(sprn, t0);
6f5d427d
JM		 460}
461
45d827d2 462static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 463{
464 DisasContext *ctx = opaque;
465
466 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 467 TCGv t0 = tcg_temp_new();
468 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
469 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
470 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
471 gen_store_spr(sprn, t0);
472 tcg_temp_free(t0);
6f5d427d 473 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 474 TCGv t0 = tcg_temp_new();
475 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
476 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
477 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
478 gen_store_spr(sprn, t0);
479 tcg_temp_free(t0);
6f5d427d
JM		 480 } else {
481 printf("Trying to write an unknown exception vector %d %03x\n",
482 sprn, sprn);
e06fcd75 483 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 484 }
485}
486#endif
487
cf8358c8
AJ		 488static inline void vscr_init (CPUPPCState *env, uint32_t val)
489{
490 env->vscr = val;
491 /* Altivec always uses round-to-nearest */
492 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
493 set_flush_to_zero(vscr_nj, &env->vec_status);
494}
495
76a66253
JM		 496#if defined(CONFIG_USER_ONLY)
497#define spr_register(env, num, name, uea_read, uea_write, \
498 oea_read, oea_write, initial_value) \
499do { \
500 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
501} while (0)
502static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 503 const char *name,
45d827d2
AJ		 504 void (*uea_read)(void *opaque, int gprn, int sprn),
505 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 506 target_ulong initial_value)
507#else
3fc6c082 508static inline void spr_register (CPUPPCState *env, int num,
b55266b5 509 const char *name,
45d827d2
AJ		 510 void (*uea_read)(void *opaque, int gprn, int sprn),
511 void (*uea_write)(void *opaque, int sprn, int gprn),
512 void (*oea_read)(void *opaque, int gprn, int sprn),
513 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 514 target_ulong initial_value)
76a66253 515#endif
3fc6c082
FB		 516{
517 ppc_spr_t *spr;
518
519 spr = &env->spr_cb[num];
520 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 521#if !defined(CONFIG_USER_ONLY)
522 spr->oea_read != NULL || spr->oea_write != NULL ||
523#endif
524 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 525 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
526 exit(1);
527 }
528#if defined(PPC_DEBUG_SPR)
1b9eb036 529 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 530 initial_value);
3fc6c082
FB		 531#endif
532 spr->name = name;
533 spr->uea_read = uea_read;
534 spr->uea_write = uea_write;
76a66253 535#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 536 spr->oea_read = oea_read;
537 spr->oea_write = oea_write;
76a66253 538#endif
3fc6c082
FB		 539 env->spr[num] = initial_value;
540}
541
542/* Generic PowerPC SPRs */
543static void gen_spr_generic (CPUPPCState *env)
544{
545 /* Integer processing */
546 spr_register(env, SPR_XER, "XER",
547 &spr_read_xer, &spr_write_xer,
548 &spr_read_xer, &spr_write_xer,
549 0x00000000);
550 /* Branch contol */
551 spr_register(env, SPR_LR, "LR",
552 &spr_read_lr, &spr_write_lr,
553 &spr_read_lr, &spr_write_lr,
554 0x00000000);
555 spr_register(env, SPR_CTR, "CTR",
556 &spr_read_ctr, &spr_write_ctr,
557 &spr_read_ctr, &spr_write_ctr,
558 0x00000000);
559 /* Interrupt processing */
560 spr_register(env, SPR_SRR0, "SRR0",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_generic, &spr_write_generic,
563 0x00000000);
564 spr_register(env, SPR_SRR1, "SRR1",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_generic, &spr_write_generic,
567 0x00000000);
568 /* Processor control */
569 spr_register(env, SPR_SPRG0, "SPRG0",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_generic, &spr_write_generic,
572 0x00000000);
573 spr_register(env, SPR_SPRG1, "SPRG1",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_generic, &spr_write_generic,
576 0x00000000);
577 spr_register(env, SPR_SPRG2, "SPRG2",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_generic, &spr_write_generic,
580 0x00000000);
581 spr_register(env, SPR_SPRG3, "SPRG3",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_generic, &spr_write_generic,
584 0x00000000);
585}
586
587/* SPR common to all non-embedded PowerPC, including 601 */
588static void gen_spr_ne_601 (CPUPPCState *env)
589{
590 /* Exception processing */
591 spr_register(env, SPR_DSISR, "DSISR",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_generic, &spr_write_generic,
594 0x00000000);
595 spr_register(env, SPR_DAR, "DAR",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_generic, &spr_write_generic,
598 0x00000000);
599 /* Timer */
600 spr_register(env, SPR_DECR, "DECR",
601 SPR_NOACCESS, SPR_NOACCESS,
602 &spr_read_decr, &spr_write_decr,
603 0x00000000);
604 /* Memory management */
605 spr_register(env, SPR_SDR1, "SDR1",
606 SPR_NOACCESS, SPR_NOACCESS,
607 &spr_read_sdr1, &spr_write_sdr1,
608 0x00000000);
609}
610
611/* BATs 0-3 */
612static void gen_low_BATs (CPUPPCState *env)
613{
f2e63a42 614#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 615 spr_register(env, SPR_IBAT0U, "IBAT0U",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_ibat, &spr_write_ibatu,
618 0x00000000);
619 spr_register(env, SPR_IBAT0L, "IBAT0L",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_ibat, &spr_write_ibatl,
622 0x00000000);
623 spr_register(env, SPR_IBAT1U, "IBAT1U",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_ibat, &spr_write_ibatu,
626 0x00000000);
627 spr_register(env, SPR_IBAT1L, "IBAT1L",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_ibat, &spr_write_ibatl,
630 0x00000000);
631 spr_register(env, SPR_IBAT2U, "IBAT2U",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_ibat, &spr_write_ibatu,
634 0x00000000);
635 spr_register(env, SPR_IBAT2L, "IBAT2L",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_ibat, &spr_write_ibatl,
638 0x00000000);
639 spr_register(env, SPR_IBAT3U, "IBAT3U",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_ibat, &spr_write_ibatu,
642 0x00000000);
643 spr_register(env, SPR_IBAT3L, "IBAT3L",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_ibat, &spr_write_ibatl,
646 0x00000000);
647 spr_register(env, SPR_DBAT0U, "DBAT0U",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_dbat, &spr_write_dbatu,
650 0x00000000);
651 spr_register(env, SPR_DBAT0L, "DBAT0L",
652 SPR_NOACCESS, SPR_NOACCESS,
653 &spr_read_dbat, &spr_write_dbatl,
654 0x00000000);
655 spr_register(env, SPR_DBAT1U, "DBAT1U",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_dbat, &spr_write_dbatu,
658 0x00000000);
659 spr_register(env, SPR_DBAT1L, "DBAT1L",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_dbat, &spr_write_dbatl,
662 0x00000000);
663 spr_register(env, SPR_DBAT2U, "DBAT2U",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_dbat, &spr_write_dbatu,
666 0x00000000);
667 spr_register(env, SPR_DBAT2L, "DBAT2L",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_dbat, &spr_write_dbatl,
670 0x00000000);
671 spr_register(env, SPR_DBAT3U, "DBAT3U",
672 SPR_NOACCESS, SPR_NOACCESS,
673 &spr_read_dbat, &spr_write_dbatu,
674 0x00000000);
675 spr_register(env, SPR_DBAT3L, "DBAT3L",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_dbat, &spr_write_dbatl,
678 0x00000000);
a750fc0b 679 env->nb_BATs += 4;
f2e63a42 680#endif
3fc6c082
FB		 681}
682
683/* BATs 4-7 */
684static void gen_high_BATs (CPUPPCState *env)
685{
f2e63a42 686#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 687 spr_register(env, SPR_IBAT4U, "IBAT4U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat_h, &spr_write_ibatu_h,
690 0x00000000);
691 spr_register(env, SPR_IBAT4L, "IBAT4L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat_h, &spr_write_ibatl_h,
694 0x00000000);
695 spr_register(env, SPR_IBAT5U, "IBAT5U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat_h, &spr_write_ibatu_h,
698 0x00000000);
699 spr_register(env, SPR_IBAT5L, "IBAT5L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat_h, &spr_write_ibatl_h,
702 0x00000000);
703 spr_register(env, SPR_IBAT6U, "IBAT6U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat_h, &spr_write_ibatu_h,
706 0x00000000);
707 spr_register(env, SPR_IBAT6L, "IBAT6L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat_h, &spr_write_ibatl_h,
710 0x00000000);
711 spr_register(env, SPR_IBAT7U, "IBAT7U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_ibat_h, &spr_write_ibatu_h,
714 0x00000000);
715 spr_register(env, SPR_IBAT7L, "IBAT7L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_ibat_h, &spr_write_ibatl_h,
718 0x00000000);
719 spr_register(env, SPR_DBAT4U, "DBAT4U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat_h, &spr_write_dbatu_h,
722 0x00000000);
723 spr_register(env, SPR_DBAT4L, "DBAT4L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat_h, &spr_write_dbatl_h,
726 0x00000000);
727 spr_register(env, SPR_DBAT5U, "DBAT5U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat_h, &spr_write_dbatu_h,
730 0x00000000);
731 spr_register(env, SPR_DBAT5L, "DBAT5L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat_h, &spr_write_dbatl_h,
734 0x00000000);
735 spr_register(env, SPR_DBAT6U, "DBAT6U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat_h, &spr_write_dbatu_h,
738 0x00000000);
739 spr_register(env, SPR_DBAT6L, "DBAT6L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat_h, &spr_write_dbatl_h,
742 0x00000000);
743 spr_register(env, SPR_DBAT7U, "DBAT7U",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_dbat_h, &spr_write_dbatu_h,
746 0x00000000);
747 spr_register(env, SPR_DBAT7L, "DBAT7L",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_dbat_h, &spr_write_dbatl_h,
750 0x00000000);
a750fc0b 751 env->nb_BATs += 4;
f2e63a42 752#endif
3fc6c082
FB		 753}
754
755/* Generic PowerPC time base */
756static void gen_tbl (CPUPPCState *env)
757{
758 spr_register(env, SPR_VTBL, "TBL",
759 &spr_read_tbl, SPR_NOACCESS,
760 &spr_read_tbl, SPR_NOACCESS,
761 0x00000000);
762 spr_register(env, SPR_TBL, "TBL",
763 SPR_NOACCESS, SPR_NOACCESS,
764 SPR_NOACCESS, &spr_write_tbl,
765 0x00000000);
766 spr_register(env, SPR_VTBU, "TBU",
767 &spr_read_tbu, SPR_NOACCESS,
768 &spr_read_tbu, SPR_NOACCESS,
769 0x00000000);
770 spr_register(env, SPR_TBU, "TBU",
771 SPR_NOACCESS, SPR_NOACCESS,
772 SPR_NOACCESS, &spr_write_tbu,
773 0x00000000);
774}
775
76a66253
JM		 776/* Softare table search registers */
777static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
778{
f2e63a42 779#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 780 env->nb_tlb = nb_tlbs;
781 env->nb_ways = nb_ways;
782 env->id_tlbs = 1;
783 spr_register(env, SPR_DMISS, "DMISS",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, SPR_NOACCESS,
786 0x00000000);
787 spr_register(env, SPR_DCMP, "DCMP",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_generic, SPR_NOACCESS,
790 0x00000000);
791 spr_register(env, SPR_HASH1, "HASH1",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, SPR_NOACCESS,
794 0x00000000);
795 spr_register(env, SPR_HASH2, "HASH2",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_generic, SPR_NOACCESS,
798 0x00000000);
799 spr_register(env, SPR_IMISS, "IMISS",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_generic, SPR_NOACCESS,
802 0x00000000);
803 spr_register(env, SPR_ICMP, "ICMP",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_generic, SPR_NOACCESS,
806 0x00000000);
807 spr_register(env, SPR_RPA, "RPA",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
f2e63a42 811#endif
76a66253
JM		 812}
813
814/* SPR common to MPC755 and G2 */
815static void gen_spr_G2_755 (CPUPPCState *env)
816{
817 /* SGPRs */
818 spr_register(env, SPR_SPRG4, "SPRG4",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_generic,
821 0x00000000);
822 spr_register(env, SPR_SPRG5, "SPRG5",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826 spr_register(env, SPR_SPRG6, "SPRG6",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_generic, &spr_write_generic,
829 0x00000000);
830 spr_register(env, SPR_SPRG7, "SPRG7",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_generic, &spr_write_generic,
833 0x00000000);
76a66253
JM		 834}
835
3fc6c082
FB		 836/* SPR common to all 7xx PowerPC implementations */
837static void gen_spr_7xx (CPUPPCState *env)
838{
839 /* Breakpoints */
840 /* XXX : not implemented */
841 spr_register(env, SPR_DABR, "DABR",
842 SPR_NOACCESS, SPR_NOACCESS,
843 &spr_read_generic, &spr_write_generic,
844 0x00000000);
845 /* XXX : not implemented */
846 spr_register(env, SPR_IABR, "IABR",
847 SPR_NOACCESS, SPR_NOACCESS,
848 &spr_read_generic, &spr_write_generic,
849 0x00000000);
850 /* Cache management */
851 /* XXX : not implemented */
852 spr_register(env, SPR_ICTC, "ICTC",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, &spr_write_generic,
855 0x00000000);
856 /* Performance monitors */
857 /* XXX : not implemented */
858 spr_register(env, SPR_MMCR0, "MMCR0",
859 SPR_NOACCESS, SPR_NOACCESS,
860 &spr_read_generic, &spr_write_generic,
861 0x00000000);
862 /* XXX : not implemented */
863 spr_register(env, SPR_MMCR1, "MMCR1",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, &spr_write_generic,
866 0x00000000);
867 /* XXX : not implemented */
868 spr_register(env, SPR_PMC1, "PMC1",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, &spr_write_generic,
871 0x00000000);
872 /* XXX : not implemented */
873 spr_register(env, SPR_PMC2, "PMC2",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
877 /* XXX : not implemented */
878 spr_register(env, SPR_PMC3, "PMC3",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_generic,
881 0x00000000);
882 /* XXX : not implemented */
883 spr_register(env, SPR_PMC4, "PMC4",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 /* XXX : not implemented */
a750fc0b 888 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, SPR_NOACCESS,
891 0x00000000);
578bb252 892 /* XXX : not implemented */
3fc6c082
FB		 893 spr_register(env, SPR_UMMCR0, "UMMCR0",
894 &spr_read_ureg, SPR_NOACCESS,
895 &spr_read_ureg, SPR_NOACCESS,
896 0x00000000);
578bb252 897 /* XXX : not implemented */
3fc6c082
FB		 898 spr_register(env, SPR_UMMCR1, "UMMCR1",
899 &spr_read_ureg, SPR_NOACCESS,
900 &spr_read_ureg, SPR_NOACCESS,
901 0x00000000);
578bb252 902 /* XXX : not implemented */
3fc6c082
FB		 903 spr_register(env, SPR_UPMC1, "UPMC1",
904 &spr_read_ureg, SPR_NOACCESS,
905 &spr_read_ureg, SPR_NOACCESS,
906 0x00000000);
578bb252 907 /* XXX : not implemented */
3fc6c082
FB		 908 spr_register(env, SPR_UPMC2, "UPMC2",
909 &spr_read_ureg, SPR_NOACCESS,
910 &spr_read_ureg, SPR_NOACCESS,
911 0x00000000);
578bb252 912 /* XXX : not implemented */
3fc6c082
FB		 913 spr_register(env, SPR_UPMC3, "UPMC3",
914 &spr_read_ureg, SPR_NOACCESS,
915 &spr_read_ureg, SPR_NOACCESS,
916 0x00000000);
578bb252 917 /* XXX : not implemented */
3fc6c082
FB		 918 spr_register(env, SPR_UPMC4, "UPMC4",
919 &spr_read_ureg, SPR_NOACCESS,
920 &spr_read_ureg, SPR_NOACCESS,
921 0x00000000);
578bb252 922 /* XXX : not implemented */
a750fc0b 923 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 924 &spr_read_ureg, SPR_NOACCESS,
925 &spr_read_ureg, SPR_NOACCESS,
926 0x00000000);
a750fc0b 927 /* External access control */
3fc6c082 928 /* XXX : not implemented */
a750fc0b 929 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
a750fc0b
JM		 933}
934
935static void gen_spr_thrm (CPUPPCState *env)
936{
937 /* Thermal management */
3fc6c082 938 /* XXX : not implemented */
a750fc0b 939 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* XXX : not implemented */
a750fc0b 944 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
3fc6c082 948 /* XXX : not implemented */
a750fc0b 949 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953}
954
955/* SPR specific to PowerPC 604 implementation */
956static void gen_spr_604 (CPUPPCState *env)
957{
958 /* Processor identification */
959 spr_register(env, SPR_PIR, "PIR",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_pir,
962 0x00000000);
963 /* Breakpoints */
964 /* XXX : not implemented */
965 spr_register(env, SPR_IABR, "IABR",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_DABR, "DABR",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* Performance counters */
975 /* XXX : not implemented */
976 spr_register(env, SPR_MMCR0, "MMCR0",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
3fc6c082
FB		 981 spr_register(env, SPR_PMC1, "PMC1",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_PMC2, "PMC2",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 /* XXX : not implemented */
a750fc0b 991 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, SPR_NOACCESS,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_SDA, "SDA",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, SPR_NOACCESS,
999 0x00000000);
1000 /* External access control */
1001 /* XXX : not implemented */
1002 spr_register(env, SPR_EAR, "EAR",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006}
1007
76a66253
JM		 1008/* SPR specific to PowerPC 603 implementation */
1009static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1010{
76a66253
JM		 1011 /* External access control */
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1014 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
3fc6c082
FB		 1017}
1018
76a66253
JM		 1019/* SPR specific to PowerPC G2 implementation */
1020static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1021{
76a66253
JM		 1022 /* Memory base address */
1023 /* MBAR */
578bb252 1024 /* XXX : not implemented */
76a66253
JM		 1025 spr_register(env, SPR_MBAR, "MBAR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
76a66253 1029 /* Exception processing */
363be49c 1030 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
363be49c 1034 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* Breakpoints */
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_DABR, "DABR",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_DABR2, "DABR2",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_IABR, "IABR",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_IABR2, "IABR2",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_IBCR, "IBCR",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 /* XXX : not implemented */
1065 spr_register(env, SPR_DBCR, "DBCR",
1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, &spr_write_generic,
1068 0x00000000);
1069}
1070
1071/* SPR specific to PowerPC 602 implementation */
1072static void gen_spr_602 (CPUPPCState *env)
1073{
1074 /* ESA registers */
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_SER, "SER",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
1080 /* XXX : not implemented */
1081 spr_register(env, SPR_SEBR, "SEBR",
1082 SPR_NOACCESS, SPR_NOACCESS,
1083 &spr_read_generic, &spr_write_generic,
1084 0x00000000);
1085 /* XXX : not implemented */
a750fc0b 1086 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_generic, &spr_write_generic,
1089 0x00000000);
1090 /* Floating point status */
1091 /* XXX : not implemented */
1092 spr_register(env, SPR_SP, "SP",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
1096 /* XXX : not implemented */
1097 spr_register(env, SPR_LT, "LT",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 /* Watchdog timer */
1102 /* XXX : not implemented */
1103 spr_register(env, SPR_TCR, "TCR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 /* Interrupt base */
1108 spr_register(env, SPR_IBR, "IBR",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
a750fc0b
JM		 1112 /* XXX : not implemented */
1113 spr_register(env, SPR_IABR, "IABR",
1114 SPR_NOACCESS, SPR_NOACCESS,
1115 &spr_read_generic, &spr_write_generic,
1116 0x00000000);
76a66253
JM		 1117}
1118
1119/* SPR specific to PowerPC 601 implementation */
1120static void gen_spr_601 (CPUPPCState *env)
1121{
1122 /* Multiplication/division register */
1123 /* MQ */
1124 spr_register(env, SPR_MQ, "MQ",
1125 &spr_read_generic, &spr_write_generic,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 /* RTC registers */
1129 spr_register(env, SPR_601_RTCU, "RTCU",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 SPR_NOACCESS, &spr_write_601_rtcu,
1132 0x00000000);
1133 spr_register(env, SPR_601_VRTCU, "RTCU",
1134 &spr_read_601_rtcu, SPR_NOACCESS,
1135 &spr_read_601_rtcu, SPR_NOACCESS,
1136 0x00000000);
1137 spr_register(env, SPR_601_RTCL, "RTCL",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 SPR_NOACCESS, &spr_write_601_rtcl,
1140 0x00000000);
1141 spr_register(env, SPR_601_VRTCL, "RTCL",
1142 &spr_read_601_rtcl, SPR_NOACCESS,
1143 &spr_read_601_rtcl, SPR_NOACCESS,
1144 0x00000000);
1145 /* Timer */
1146#if 0 /* ? */
1147 spr_register(env, SPR_601_UDECR, "UDECR",
1148 &spr_read_decr, SPR_NOACCESS,
1149 &spr_read_decr, SPR_NOACCESS,
1150 0x00000000);
1151#endif
1152 /* External access control */
1153 /* XXX : not implemented */
1154 spr_register(env, SPR_EAR, "EAR",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1157 0x00000000);
1158 /* Memory management */
f2e63a42 1159#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1160 spr_register(env, SPR_IBAT0U, "IBAT0U",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_601_ubat, &spr_write_601_ubatu,
1163 0x00000000);
1164 spr_register(env, SPR_IBAT0L, "IBAT0L",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_601_ubat, &spr_write_601_ubatl,
1167 0x00000000);
1168 spr_register(env, SPR_IBAT1U, "IBAT1U",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_601_ubat, &spr_write_601_ubatu,
1171 0x00000000);
1172 spr_register(env, SPR_IBAT1L, "IBAT1L",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_601_ubat, &spr_write_601_ubatl,
1175 0x00000000);
1176 spr_register(env, SPR_IBAT2U, "IBAT2U",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_601_ubat, &spr_write_601_ubatu,
1179 0x00000000);
1180 spr_register(env, SPR_IBAT2L, "IBAT2L",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_601_ubat, &spr_write_601_ubatl,
1183 0x00000000);
1184 spr_register(env, SPR_IBAT3U, "IBAT3U",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_601_ubat, &spr_write_601_ubatu,
1187 0x00000000);
1188 spr_register(env, SPR_IBAT3L, "IBAT3L",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_601_ubat, &spr_write_601_ubatl,
1191 0x00000000);
a750fc0b 1192 env->nb_BATs = 4;
f2e63a42 1193#endif
a750fc0b
JM		 1194}
1195
1196static void gen_spr_74xx (CPUPPCState *env)
1197{
1198 /* Processor identification */
1199 spr_register(env, SPR_PIR, "PIR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_pir,
1202 0x00000000);
1203 /* XXX : not implemented */
1204 spr_register(env, SPR_MMCR2, "MMCR2",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
578bb252 1208 /* XXX : not implemented */
a750fc0b
JM		 1209 spr_register(env, SPR_UMMCR2, "UMMCR2",
1210 &spr_read_ureg, SPR_NOACCESS,
1211 &spr_read_ureg, SPR_NOACCESS,
1212 0x00000000);
1213 /* XXX: not implemented */
1214 spr_register(env, SPR_BAMR, "BAMR",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
578bb252 1218 /* XXX : not implemented */
a750fc0b
JM		 1219 spr_register(env, SPR_MSSCR0, "MSSCR0",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* Hardware implementation registers */
1224 /* XXX : not implemented */
1225 spr_register(env, SPR_HID0, "HID0",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_generic, &spr_write_generic,
1228 0x00000000);
1229 /* XXX : not implemented */
1230 spr_register(env, SPR_HID1, "HID1",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 /* Altivec */
1235 spr_register(env, SPR_VRSAVE, "VRSAVE",
1236 &spr_read_generic, &spr_write_generic,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
bd928eba
JM		 1239 /* XXX : not implemented */
1240 spr_register(env, SPR_L2CR, "L2CR",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1243 0x00000000);
cf8358c8
AJ		 1244 /* Not strictly an SPR */
1245 vscr_init(env, 0x00010000);
a750fc0b
JM		 1246}
1247
a750fc0b
JM		 1248static void gen_l3_ctrl (CPUPPCState *env)
1249{
1250 /* L3CR */
1251 /* XXX : not implemented */
1252 spr_register(env, SPR_L3CR, "L3CR",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
1256 /* L3ITCR0 */
578bb252 1257 /* XXX : not implemented */
a750fc0b
JM		 1258 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
a750fc0b 1262 /* L3PM */
578bb252 1263 /* XXX : not implemented */
a750fc0b
JM		 1264 spr_register(env, SPR_L3PM, "L3PM",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268}
a750fc0b 1269
578bb252 1270static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1271{
f2e63a42 1272#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1273 env->nb_tlb = nb_tlbs;
1274 env->nb_ways = nb_ways;
1275 env->id_tlbs = 1;
1276 /* XXX : not implemented */
a750fc0b
JM		 1277 spr_register(env, SPR_PTEHI, "PTEHI",
1278 SPR_NOACCESS, SPR_NOACCESS,
1279 &spr_read_generic, &spr_write_generic,
1280 0x00000000);
578bb252 1281 /* XXX : not implemented */
a750fc0b
JM		 1282 spr_register(env, SPR_PTELO, "PTELO",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
578bb252 1286 /* XXX : not implemented */
a750fc0b
JM		 1287 spr_register(env, SPR_TLBMISS, "TLBMISS",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
f2e63a42 1291#endif
76a66253
JM		 1292}
1293
80d11f44 1294static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1295{
80d11f44
JM		 1296 spr_register(env, SPR_USPRG4, "USPRG4",
1297 &spr_read_ureg, SPR_NOACCESS,
1298 &spr_read_ureg, SPR_NOACCESS,
1299 0x00000000);
1300 spr_register(env, SPR_USPRG5, "USPRG5",
1301 &spr_read_ureg, SPR_NOACCESS,
1302 &spr_read_ureg, SPR_NOACCESS,
1303 0x00000000);
1304 spr_register(env, SPR_USPRG6, "USPRG6",
1305 &spr_read_ureg, SPR_NOACCESS,
1306 &spr_read_ureg, SPR_NOACCESS,
1307 0x00000000);
1308 spr_register(env, SPR_USPRG7, "USPRG7",
1309 &spr_read_ureg, SPR_NOACCESS,
1310 &spr_read_ureg, SPR_NOACCESS,
76a66253 1311 0x00000000);
80d11f44
JM		 1312}
1313
1314/* PowerPC BookE SPR */
1315static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1316{
b55266b5 1317 const char *ivor_names[64] = {
80d11f44
JM		 1318 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1319 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1320 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1321 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1322 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1323 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1324 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1325 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1326 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1327 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1328 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1329 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1330 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1331 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1332 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1333 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1334 };
1335#define SPR_BOOKE_IVORxx (-1)
1336 int ivor_sprn[64] = {
1337 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1338 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1339 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1340 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1341 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1342 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1343 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1344 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1345 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1346 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1347 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1348 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1349 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1350 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1351 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1352 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1353 };
1354 int i;
1355
76a66253 1356 /* Interrupt processing */
363be49c 1357 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
363be49c
JM		 1361 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
76a66253
JM		 1365 /* Debug */
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 /* XXX : not implemented */
1372 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 /* XXX : not implemented */
76a66253
JM		 1377 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1378 SPR_NOACCESS, SPR_NOACCESS,
1379 &spr_read_generic, &spr_write_generic,
1380 0x00000000);
1381 /* XXX : not implemented */
1382 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_generic,
1385 0x00000000);
1386 /* XXX : not implemented */
76a66253
JM		 1387 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 /* XXX : not implemented */
1392 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 /* XXX : not implemented */
1397 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 /* XXX : not implemented */
1402 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1403 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1404 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1405 0x00000000);
1406 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410 spr_register(env, SPR_BOOKE_ESR, "ESR",
1411 SPR_NOACCESS, SPR_NOACCESS,
1412 &spr_read_generic, &spr_write_generic,
1413 0x00000000);
363be49c
JM		 1414 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1415 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1416 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1417 0x00000000);
1418 /* Exception vectors */
80d11f44
JM		 1419 for (i = 0; i < 64; i++) {
1420 if (ivor_mask & (1ULL << i)) {
1421 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1422 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1423 exit(1);
1424 }
1425 spr_register(env, ivor_sprn[i], ivor_names[i],
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_excp_vector,
1428 0x00000000);
1429 }
1430 }
76a66253
JM		 1431 spr_register(env, SPR_BOOKE_PID, "PID",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435 spr_register(env, SPR_BOOKE_TCR, "TCR",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, &spr_write_booke_tcr,
1438 0x00000000);
1439 spr_register(env, SPR_BOOKE_TSR, "TSR",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_booke_tsr,
1442 0x00000000);
1443 /* Timer */
1444 spr_register(env, SPR_DECR, "DECR",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_decr, &spr_write_decr,
1447 0x00000000);
1448 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 SPR_NOACCESS, &spr_write_generic,
1451 0x00000000);
1452 /* SPRGs */
1453 spr_register(env, SPR_USPRG0, "USPRG0",
1454 &spr_read_generic, &spr_write_generic,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
1457 spr_register(env, SPR_SPRG4, "SPRG4",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_generic, &spr_write_generic,
1460 0x00000000);
76a66253
JM		 1461 spr_register(env, SPR_SPRG5, "SPRG5",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
76a66253
JM		 1465 spr_register(env, SPR_SPRG6, "SPRG6",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
76a66253
JM		 1469 spr_register(env, SPR_SPRG7, "SPRG7",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
76a66253
JM		 1473}
1474
363be49c 1475/* FSL storage control registers */
80d11f44 1476static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1477{
f2e63a42 1478#if !defined(CONFIG_USER_ONLY)
b55266b5 1479 const char *mas_names[8] = {
80d11f44
JM		 1480 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1481 };
1482 int mas_sprn[8] = {
1483 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1484 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1485 };
1486 int i;
1487
363be49c 1488 /* TLB assist registers */
578bb252 1489 /* XXX : not implemented */
80d11f44
JM		 1490 for (i = 0; i < 8; i++) {
1491 if (mas_mask & (1 << i)) {
1492 spr_register(env, mas_sprn[i], mas_names[i],
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, &spr_write_generic,
1495 0x00000000);
1496 }
1497 }
363be49c 1498 if (env->nb_pids > 1) {
578bb252 1499 /* XXX : not implemented */
363be49c
JM		 1500 spr_register(env, SPR_BOOKE_PID1, "PID1",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_generic,
1503 0x00000000);
1504 }
1505 if (env->nb_pids > 2) {
578bb252 1506 /* XXX : not implemented */
363be49c
JM		 1507 spr_register(env, SPR_BOOKE_PID2, "PID2",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_generic, &spr_write_generic,
1510 0x00000000);
1511 }
578bb252 1512 /* XXX : not implemented */
65f9ee8d 1513 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, SPR_NOACCESS,
1516 0x00000000); /* TOFIX */
578bb252 1517 /* XXX : not implemented */
65f9ee8d 1518 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000); /* TOFIX */
1522 switch (env->nb_ways) {
1523 case 4:
578bb252 1524 /* XXX : not implemented */
363be49c
JM		 1525 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, SPR_NOACCESS,
1528 0x00000000); /* TOFIX */
1529 /* Fallthru */
1530 case 3:
578bb252 1531 /* XXX : not implemented */
363be49c
JM		 1532 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, SPR_NOACCESS,
1535 0x00000000); /* TOFIX */
1536 /* Fallthru */
1537 case 2:
578bb252 1538 /* XXX : not implemented */
363be49c
JM		 1539 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, SPR_NOACCESS,
1542 0x00000000); /* TOFIX */
1543 /* Fallthru */
1544 case 1:
578bb252 1545 /* XXX : not implemented */
363be49c
JM		 1546 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, SPR_NOACCESS,
1549 0x00000000); /* TOFIX */
1550 /* Fallthru */
1551 case 0:
1552 default:
1553 break;
1554 }
f2e63a42 1555#endif
363be49c
JM		 1556}
1557
76a66253
JM		 1558/* SPR specific to PowerPC 440 implementation */
1559static void gen_spr_440 (CPUPPCState *env)
1560{
1561 /* Cache control */
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_440_DNV0, "DNV0",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_440_DNV1, "DNV1",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 /* XXX : not implemented */
1573 spr_register(env, SPR_440_DNV2, "DNV2",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577 /* XXX : not implemented */
1578 spr_register(env, SPR_440_DNV3, "DNV3",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 /* XXX : not implemented */
2662a059 1583 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 /* XXX : not implemented */
2662a059 1588 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592 /* XXX : not implemented */
2662a059 1593 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597 /* XXX : not implemented */
2662a059 1598 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_440_DVLIM, "DVLIM",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
1607 /* XXX : not implemented */
1608 spr_register(env, SPR_440_INV0, "INV0",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612 /* XXX : not implemented */
1613 spr_register(env, SPR_440_INV1, "INV1",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1616 0x00000000);
1617 /* XXX : not implemented */
1618 spr_register(env, SPR_440_INV2, "INV2",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_generic,
1621 0x00000000);
1622 /* XXX : not implemented */
1623 spr_register(env, SPR_440_INV3, "INV3",
1624 SPR_NOACCESS, SPR_NOACCESS,
1625 &spr_read_generic, &spr_write_generic,
1626 0x00000000);
1627 /* XXX : not implemented */
2662a059 1628 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632 /* XXX : not implemented */
2662a059 1633 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637 /* XXX : not implemented */
2662a059 1638 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 /* XXX : not implemented */
2662a059 1643 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 /* XXX : not implemented */
1648 spr_register(env, SPR_440_IVLIM, "IVLIM",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 /* Cache debug */
1653 /* XXX : not implemented */
2662a059 1654 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, SPR_NOACCESS,
1657 0x00000000);
1658 /* XXX : not implemented */
2662a059 1659 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, SPR_NOACCESS,
1662 0x00000000);
1663 /* XXX : not implemented */
2662a059 1664 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, SPR_NOACCESS,
1667 0x00000000);
1668 /* XXX : not implemented */
2662a059 1669 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, SPR_NOACCESS,
1672 0x00000000);
1673 /* XXX : not implemented */
2662a059 1674 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, SPR_NOACCESS,
1677 0x00000000);
1678 /* XXX : not implemented */
1679 spr_register(env, SPR_440_DBDR, "DBDR",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* Processor control */
1684 spr_register(env, SPR_4xx_CCR0, "CCR0",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, SPR_NOACCESS,
1691 0x00000000);
1692 /* Storage control */
1693 spr_register(env, SPR_440_MMUCR, "MMUCR",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697}
1698
1699/* SPR shared between PowerPC 40x implementations */
1700static void gen_spr_40x (CPUPPCState *env)
1701{
1702 /* Cache */
035feb88 1703 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1704 spr_register(env, SPR_40x_DCCR, "DCCR",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
035feb88 1708 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1709 spr_register(env, SPR_40x_ICCR, "ICCR",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
578bb252 1713 /* not emulated, as Qemu do not emulate caches */
2662a059 1714 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, SPR_NOACCESS,
1717 0x00000000);
76a66253
JM		 1718 /* Exception */
1719 spr_register(env, SPR_40x_DEAR, "DEAR",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 spr_register(env, SPR_40x_ESR, "ESR",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 spr_register(env, SPR_40x_EVPR, "EVPR",
1728 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1729 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1730 0x00000000);
1731 spr_register(env, SPR_40x_SRR2, "SRR2",
1732 &spr_read_generic, &spr_write_generic,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 spr_register(env, SPR_40x_SRR3, "SRR3",
1736 &spr_read_generic, &spr_write_generic,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739 /* Timers */
1740 spr_register(env, SPR_40x_PIT, "PIT",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_40x_pit, &spr_write_40x_pit,
1743 0x00000000);
1744 spr_register(env, SPR_40x_TCR, "TCR",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_booke_tcr,
1747 0x00000000);
1748 spr_register(env, SPR_40x_TSR, "TSR",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_booke_tsr,
1751 0x00000000);
2662a059
JM		 1752}
1753
1754/* SPR specific to PowerPC 405 implementation */
1755static void gen_spr_405 (CPUPPCState *env)
1756{
1757 /* MMU */
1758 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
2662a059 1762 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1765 0x00700000);
1766 /* Debug interface */
76a66253
JM		 1767 /* XXX : not implemented */
1768 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1769 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1770 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1771 0x00000000);
1772 /* XXX : not implemented */
2662a059
JM		 1773 spr_register(env, SPR_405_DBCR1, "DBCR1",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
76a66253
JM		 1778 spr_register(env, SPR_40x_DBSR, "DBSR",
1779 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1780 &spr_read_generic, &spr_write_clear,
1781 /* Last reset was system reset */
76a66253
JM		 1782 0x00000300);
1783 /* XXX : not implemented */
2662a059 1784 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
2662a059 1788 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
2662a059
JM		 1792 /* XXX : not implemented */
1793 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
2662a059 1796 0x00000000);
76a66253 1797 /* XXX : not implemented */
2662a059 1798 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 /* XXX : not implemented */
2662a059 1803 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
2662a059 1807 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_405_IAC3, "IAC3",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_405_IAC4, "IAC4",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* Storage control */
035feb88 1822 /* XXX: TODO: not implemented */
76a66253
JM		 1823 spr_register(env, SPR_405_SLER, "SLER",
1824 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1825 &spr_read_generic, &spr_write_40x_sler,
76a66253 1826 0x00000000);
2662a059
JM		 1827 spr_register(env, SPR_40x_ZPR, "ZPR",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
76a66253
JM		 1831 /* XXX : not implemented */
1832 spr_register(env, SPR_405_SU0R, "SU0R",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 /* SPRG */
1837 spr_register(env, SPR_USPRG0, "USPRG0",
1838 &spr_read_ureg, SPR_NOACCESS,
1839 &spr_read_ureg, SPR_NOACCESS,
1840 0x00000000);
1841 spr_register(env, SPR_SPRG4, "SPRG4",
1842 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1843 &spr_read_generic, &spr_write_generic,
76a66253 1844 0x00000000);
76a66253
JM		 1845 spr_register(env, SPR_SPRG5, "SPRG5",
1846 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1847 spr_read_generic, &spr_write_generic,
76a66253 1848 0x00000000);
76a66253
JM		 1849 spr_register(env, SPR_SPRG6, "SPRG6",
1850 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1851 spr_read_generic, &spr_write_generic,
76a66253 1852 0x00000000);
76a66253
JM		 1853 spr_register(env, SPR_SPRG7, "SPRG7",
1854 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1855 spr_read_generic, &spr_write_generic,
76a66253 1856 0x00000000);
80d11f44 1857 gen_spr_usprgh(env);
76a66253
JM		 1858}
1859
1860/* SPR shared between PowerPC 401 & 403 implementations */
1861static void gen_spr_401_403 (CPUPPCState *env)
1862{
1863 /* Time base */
1864 spr_register(env, SPR_403_VTBL, "TBL",
1865 &spr_read_tbl, SPR_NOACCESS,
1866 &spr_read_tbl, SPR_NOACCESS,
1867 0x00000000);
1868 spr_register(env, SPR_403_TBL, "TBL",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 SPR_NOACCESS, &spr_write_tbl,
1871 0x00000000);
1872 spr_register(env, SPR_403_VTBU, "TBU",
1873 &spr_read_tbu, SPR_NOACCESS,
1874 &spr_read_tbu, SPR_NOACCESS,
1875 0x00000000);
1876 spr_register(env, SPR_403_TBU, "TBU",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 SPR_NOACCESS, &spr_write_tbu,
1879 0x00000000);
1880 /* Debug */
578bb252 1881 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1882 spr_register(env, SPR_403_CDBCR, "CDBCR",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886}
1887
2662a059
JM		 1888/* SPR specific to PowerPC 401 implementation */
1889static void gen_spr_401 (CPUPPCState *env)
1890{
1891 /* Debug interface */
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_40x_DBCR0, "DBCR",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_40x_dbcr0,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_DBSR, "DBSR",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_clear,
1901 /* Last reset was system reset */
1902 0x00000300);
1903 /* XXX : not implemented */
1904 spr_register(env, SPR_40x_DAC1, "DAC",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 /* XXX : not implemented */
1909 spr_register(env, SPR_40x_IAC1, "IAC",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 /* Storage control */
035feb88 1914 /* XXX: TODO: not implemented */
2662a059
JM		 1915 spr_register(env, SPR_405_SLER, "SLER",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_40x_sler,
1918 0x00000000);
035feb88
JM		 1919 /* not emulated, as Qemu never does speculative access */
1920 spr_register(env, SPR_40x_SGR, "SGR",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0xFFFFFFFF);
1924 /* not emulated, as Qemu do not emulate caches */
1925 spr_register(env, SPR_40x_DCWR, "DCWR",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
2662a059
JM		 1929}
1930
a750fc0b
JM		 1931static void gen_spr_401x2 (CPUPPCState *env)
1932{
1933 gen_spr_401(env);
1934 spr_register(env, SPR_40x_PID, "PID",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_generic, &spr_write_generic,
1937 0x00000000);
1938 spr_register(env, SPR_40x_ZPR, "ZPR",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942}
1943
76a66253
JM		 1944/* SPR specific to PowerPC 403 implementation */
1945static void gen_spr_403 (CPUPPCState *env)
1946{
2662a059
JM		 1947 /* Debug interface */
1948 /* XXX : not implemented */
1949 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_40x_dbcr0,
1952 0x00000000);
1953 /* XXX : not implemented */
1954 spr_register(env, SPR_40x_DBSR, "DBSR",
1955 SPR_NOACCESS, SPR_NOACCESS,
1956 &spr_read_generic, &spr_write_clear,
1957 /* Last reset was system reset */
1958 0x00000300);
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_40x_DAC1, "DAC1",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
578bb252 1964 /* XXX : not implemented */
2662a059
JM		 1965 spr_register(env, SPR_40x_DAC2, "DAC2",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_40x_IAC1, "IAC1",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
578bb252 1974 /* XXX : not implemented */
2662a059
JM		 1975 spr_register(env, SPR_40x_IAC2, "IAC2",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
a750fc0b
JM		 1979}
1980
1981static void gen_spr_403_real (CPUPPCState *env)
1982{
76a66253
JM		 1983 spr_register(env, SPR_403_PBL1, "PBL1",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_403_pbr, &spr_write_403_pbr,
1986 0x00000000);
1987 spr_register(env, SPR_403_PBU1, "PBU1",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_403_pbr, &spr_write_403_pbr,
1990 0x00000000);
1991 spr_register(env, SPR_403_PBL2, "PBL2",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_403_pbr, &spr_write_403_pbr,
1994 0x00000000);
1995 spr_register(env, SPR_403_PBU2, "PBU2",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_403_pbr, &spr_write_403_pbr,
1998 0x00000000);
a750fc0b
JM		 1999}
2000
2001static void gen_spr_403_mmu (CPUPPCState *env)
2002{
2003 /* MMU */
2004 spr_register(env, SPR_40x_PID, "PID",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2662a059 2008 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012}
2013
2014/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2015static void gen_spr_compress (CPUPPCState *env)
2016{
578bb252 2017 /* XXX : not implemented */
76a66253
JM		 2018 spr_register(env, SPR_401_SKR, "SKR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022}
a750fc0b
JM		 2023
2024#if defined (TARGET_PPC64)
a750fc0b
JM		 2025/* SPR specific to PowerPC 620 */
2026static void gen_spr_620 (CPUPPCState *env)
2027{
082c6681
JM		 2028 /* Processor identification */
2029 spr_register(env, SPR_PIR, "PIR",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_pir,
2032 0x00000000);
2033 spr_register(env, SPR_ASR, "ASR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_asr, &spr_write_asr,
2036 0x00000000);
2037 /* Breakpoints */
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_IABR, "IABR",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_DABR, "DABR",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_SIAR, "SIAR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, SPR_NOACCESS,
2052 0x00000000);
2053 /* XXX : not implemented */
2054 spr_register(env, SPR_SDA, "SDA",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, SPR_NOACCESS,
2057 0x00000000);
2058 /* XXX : not implemented */
2059 spr_register(env, SPR_620_PMC1R, "PMC1",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, SPR_NOACCESS,
2062 0x00000000);
2063 spr_register(env, SPR_620_PMC1W, "PMC1",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 SPR_NOACCESS, &spr_write_generic,
2066 0x00000000);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_620_PMC2R, "PMC2",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, SPR_NOACCESS,
2071 0x00000000);
2072 spr_register(env, SPR_620_PMC2W, "PMC2",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 SPR_NOACCESS, &spr_write_generic,
2075 0x00000000);
2076 /* XXX : not implemented */
2077 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, SPR_NOACCESS,
2080 0x00000000);
2081 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 SPR_NOACCESS, &spr_write_generic,
2084 0x00000000);
2085 /* External access control */
2086 /* XXX : not implemented */
2087 spr_register(env, SPR_EAR, "EAR",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
2091#if 0 // XXX: check this
578bb252 2092 /* XXX : not implemented */
a750fc0b
JM		 2093 spr_register(env, SPR_620_PMR0, "PMR0",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_generic,
2096 0x00000000);
578bb252 2097 /* XXX : not implemented */
a750fc0b
JM		 2098 spr_register(env, SPR_620_PMR1, "PMR1",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
578bb252 2102 /* XXX : not implemented */
a750fc0b
JM		 2103 spr_register(env, SPR_620_PMR2, "PMR2",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
578bb252 2107 /* XXX : not implemented */
a750fc0b
JM		 2108 spr_register(env, SPR_620_PMR3, "PMR3",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
578bb252 2112 /* XXX : not implemented */
a750fc0b
JM		 2113 spr_register(env, SPR_620_PMR4, "PMR4",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
578bb252 2117 /* XXX : not implemented */
a750fc0b
JM		 2118 spr_register(env, SPR_620_PMR5, "PMR5",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
578bb252 2122 /* XXX : not implemented */
a750fc0b
JM		 2123 spr_register(env, SPR_620_PMR6, "PMR6",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
578bb252 2127 /* XXX : not implemented */
a750fc0b
JM		 2128 spr_register(env, SPR_620_PMR7, "PMR7",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
578bb252 2132 /* XXX : not implemented */
a750fc0b
JM		 2133 spr_register(env, SPR_620_PMR8, "PMR8",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2136 0x00000000);
578bb252 2137 /* XXX : not implemented */
a750fc0b
JM		 2138 spr_register(env, SPR_620_PMR9, "PMR9",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
578bb252 2142 /* XXX : not implemented */
a750fc0b
JM		 2143 spr_register(env, SPR_620_PMRA, "PMR10",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
578bb252 2147 /* XXX : not implemented */
a750fc0b
JM		 2148 spr_register(env, SPR_620_PMRB, "PMR11",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
578bb252 2152 /* XXX : not implemented */
a750fc0b
JM		 2153 spr_register(env, SPR_620_PMRC, "PMR12",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
578bb252 2157 /* XXX : not implemented */
a750fc0b
JM		 2158 spr_register(env, SPR_620_PMRD, "PMR13",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
578bb252 2162 /* XXX : not implemented */
a750fc0b
JM		 2163 spr_register(env, SPR_620_PMRE, "PMR14",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
578bb252 2167 /* XXX : not implemented */
a750fc0b
JM		 2168 spr_register(env, SPR_620_PMRF, "PMR15",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
082c6681 2172#endif
578bb252 2173 /* XXX : not implemented */
082c6681 2174 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
578bb252 2178 /* XXX : not implemented */
082c6681
JM		 2179 spr_register(env, SPR_620_L2CR, "L2CR",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 /* XXX : not implemented */
2184 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188}
a750fc0b 2189#endif /* defined (TARGET_PPC64) */
76a66253 2190
80d11f44 2191static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2192{
80d11f44
JM		 2193 /* Exception processing */
2194 spr_register(env, SPR_DSISR, "DSISR",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 spr_register(env, SPR_DAR, "DAR",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 /* Timer */
2203 spr_register(env, SPR_DECR, "DECR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_decr, &spr_write_decr,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_MPC_EIE, "EIE",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_MPC_EID, "EID",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_MPC_NRI, "NRI",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_MPC_CMPA, "CMPA",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_MPC_CMPB, "CMPB",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_MPC_CMPC, "CMPC",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_MPC_CMPD, "CMPD",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_MPC_ECR, "ECR",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_MPC_DER, "DER",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_MPC_CMPE, "CMPE",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_MPC_CMPF, "CMPF",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_MPC_CMPG, "CMPG",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_MPC_CMPH, "CMPH",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_MPC_BAR, "BAR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_MPC_DPDR, "DPDR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_IMMR, "IMMR",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307}
2308
2309static void gen_spr_5xx (CPUPPCState *env)
2310{
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 /* XXX : not implemented */
2382 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416}
2417
2418static void gen_spr_8xx (CPUPPCState *env)
2419{
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545}
2546
2547// XXX: TODO
2548/*
2549 * AMR => SPR 29 (Power 2.04)
2550 * CTRL => SPR 136 (Power 2.04)
2551 * CTRL => SPR 152 (Power 2.04)
2552 * SCOMC => SPR 276 (64 bits ?)
2553 * SCOMD => SPR 277 (64 bits ?)
2554 * TBU40 => SPR 286 (Power 2.04 hypv)
2555 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2556 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2557 * HDSISR => SPR 306 (Power 2.04 hypv)
2558 * HDAR => SPR 307 (Power 2.04 hypv)
2559 * PURR => SPR 309 (Power 2.04 hypv)
2560 * HDEC => SPR 310 (Power 2.04 hypv)
2561 * HIOR => SPR 311 (hypv)
2562 * RMOR => SPR 312 (970)
2563 * HRMOR => SPR 313 (Power 2.04 hypv)
2564 * HSRR0 => SPR 314 (Power 2.04 hypv)
2565 * HSRR1 => SPR 315 (Power 2.04 hypv)
2566 * LPCR => SPR 316 (970)
2567 * LPIDR => SPR 317 (970)
2568 * SPEFSCR => SPR 512 (Power 2.04 emb)
2569 * EPR => SPR 702 (Power 2.04 emb)
2570 * perf => 768-783 (Power 2.04)
2571 * perf => 784-799 (Power 2.04)
2572 * PPR => SPR 896 (Power 2.04)
2573 * EPLC => SPR 947 (Power 2.04 emb)
2574 * EPSC => SPR 948 (Power 2.04 emb)
2575 * DABRX => 1015 (Power 2.04 hypv)
2576 * FPECR => SPR 1022 (?)
2577 * ... and more (thermal management, performance counters, ...)
2578 */
2579
2580/*****************************************************************************/
2581/* Exception vectors models */
2582static void init_excp_4xx_real (CPUPPCState *env)
2583{
2584#if !defined(CONFIG_USER_ONLY)
2585 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2586 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2587 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2588 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2589 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2590 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2591 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2592 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2593 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2594 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
faadf50e 2595 env->excp_prefix = 0x00000000UL;
80d11f44 2596 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2597 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2598 /* Hardware reset vector */
2599 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2600#endif
2601}
2602
80d11f44
JM		 2603static void init_excp_4xx_softmmu (CPUPPCState *env)
2604{
2605#if !defined(CONFIG_USER_ONLY)
2606 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2607 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2608 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2609 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2610 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2611 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2612 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2613 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2614 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2615 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2616 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2617 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2618 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2619 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2620 env->excp_prefix = 0x00000000UL;
2621 env->ivor_mask = 0x0000FFF0UL;
2622 env->ivpr_mask = 0xFFFF0000UL;
2623 /* Hardware reset vector */
2624 env->hreset_vector = 0xFFFFFFFCUL;
2625#endif
2626}
2627
2628static void init_excp_MPC5xx (CPUPPCState *env)
2629{
2630#if !defined(CONFIG_USER_ONLY)
2631 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2632 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2633 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2634 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2635 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2636 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2637 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2638 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2639 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2640 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2641 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2642 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2643 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2644 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2645 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2646 env->excp_prefix = 0x00000000UL;
2647 env->ivor_mask = 0x0000FFF0UL;
2648 env->ivpr_mask = 0xFFFF0000UL;
2649 /* Hardware reset vector */
2650 env->hreset_vector = 0xFFFFFFFCUL;
2651#endif
2652}
2653
2654static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2655{
2656#if !defined(CONFIG_USER_ONLY)
2657 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2658 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2659 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2660 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2661 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2662 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2663 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2664 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2665 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2666 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2667 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2668 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2669 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2670 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2671 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2672 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2673 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2674 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2675 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2676 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2677 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2678 env->excp_prefix = 0x00000000UL;
2679 env->ivor_mask = 0x0000FFF0UL;
2680 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2681 /* Hardware reset vector */
80d11f44 2682 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2683#endif
2684}
2685
80d11f44 2686static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2687{
2688#if !defined(CONFIG_USER_ONLY)
2689 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2690 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2691 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2692 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2693 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2694 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2695 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2696 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2697 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2698 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2699 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2700 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2701 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2702 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2703 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2704 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2705 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2706 env->excp_prefix = 0x00000000UL;
2707 /* Hardware reset vector */
2708 env->hreset_vector = 0xFFFFFFFCUL;
2709#endif
2710}
2711
2712static void init_excp_e200 (CPUPPCState *env)
2713{
2714#if !defined(CONFIG_USER_ONLY)
2715 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2716 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2717 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2722 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2723 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2735 env->excp_prefix = 0x00000000UL;
2736 env->ivor_mask = 0x0000FFF7UL;
2737 env->ivpr_mask = 0xFFFF0000UL;
2738 /* Hardware reset vector */
2739 env->hreset_vector = 0xFFFFFFFCUL;
2740#endif
2741}
2742
2743static void init_excp_BookE (CPUPPCState *env)
2744{
2745#if !defined(CONFIG_USER_ONLY)
2746 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2762 env->excp_prefix = 0x00000000UL;
2763 env->ivor_mask = 0x0000FFE0UL;
2764 env->ivpr_mask = 0xFFFF0000UL;
2765 /* Hardware reset vector */
2766 env->hreset_vector = 0xFFFFFFFCUL;
2767#endif
2768}
2769
2770static void init_excp_601 (CPUPPCState *env)
2771{
2772#if !defined(CONFIG_USER_ONLY)
2773 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2774 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2775 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2776 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2777 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2778 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2779 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2780 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2781 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2782 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2783 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2784 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
faadf50e 2785 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2786 /* Hardware reset vector */
80d11f44 2787 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2788#endif
2789}
2790
80d11f44 2791static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2792{
2793#if !defined(CONFIG_USER_ONLY)
082c6681 2794 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2795 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2796 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2797 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2798 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2799 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2800 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2801 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2802 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2803 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2804 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2805 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2806 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2807 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2808 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2809 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2810 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2811 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2812 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2813 env->excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2814 /* Hardware reset vector */
2815 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2816#endif
2817}
2818
80d11f44 2819static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2820{
2821#if !defined(CONFIG_USER_ONLY)
2822 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2823 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2824 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2825 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2826 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2827 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2828 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2829 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2830 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2831 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2832 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2833 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2834 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2835 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2836 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2837 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2838 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2839 /* Hardware reset vector */
2840 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2841#endif
2842}
2843
2844static void init_excp_604 (CPUPPCState *env)
2845{
2846#if !defined(CONFIG_USER_ONLY)
2847 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2848 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2849 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2850 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2851 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2852 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2853 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2854 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2855 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2856 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2857 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2858 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2859 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2860 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2861 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2862 /* Hardware reset vector */
2863 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2864#endif
2865}
2866
578bb252 2867#if defined(TARGET_PPC64)
e1833e1f
JM		 2868static void init_excp_620 (CPUPPCState *env)
2869{
2870#if !defined(CONFIG_USER_ONLY)
2871 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2872 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2873 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2874 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2875 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2876 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2877 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2878 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2879 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2880 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2881 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2882 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2883 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2884 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2885 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2886 /* Hardware reset vector */
faadf50e 2887 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2888#endif
2889}
578bb252 2890#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2891
2892static void init_excp_7x0 (CPUPPCState *env)
2893{
2894#if !defined(CONFIG_USER_ONLY)
2895 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2896 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2897 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2898 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2899 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2900 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2901 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2902 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2903 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2904 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2905 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2906 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2907 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 2908 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 2909 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2910 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2911 /* Hardware reset vector */
2912 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2913#endif
2914}
2915
bd928eba 2916static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 2917{
2918#if !defined(CONFIG_USER_ONLY)
2919 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2920 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2921 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2922 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2923 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2924 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2925 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2926 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2927 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2928 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2929 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2930 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2931 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2932 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba
JM		 2933 env->excp_prefix = 0x00000000UL;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
2936#endif
2937}
2938
2939static void init_excp_750cx (CPUPPCState *env)
2940{
2941#if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2954 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 2955 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2956 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2957 /* Hardware reset vector */
2958 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2959#endif
2960}
2961
7a3a6927
JM		 2962/* XXX: Check if this is correct */
2963static void init_excp_7x5 (CPUPPCState *env)
2964{
2965#if !defined(CONFIG_USER_ONLY)
2966 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2974 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2975 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2976 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 2977 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 2978 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2979 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2980 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 2981 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2982 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 2983 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2984 env->excp_prefix = 0x00000000UL;
7a3a6927
JM		 2985 /* Hardware reset vector */
2986 env->hreset_vector = 0xFFFFFFFCUL;
2987#endif
2988}
2989
e1833e1f
JM		 2990static void init_excp_7400 (CPUPPCState *env)
2991{
2992#if !defined(CONFIG_USER_ONLY)
2993 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2994 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2995 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2996 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2997 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2998 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2999 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3000 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3001 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3002 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3003 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3004 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3005 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3006 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3007 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3008 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3009 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 3010 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3011 /* Hardware reset vector */
3012 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3013#endif
3014}
3015
e1833e1f
JM		 3016static void init_excp_7450 (CPUPPCState *env)
3017{
3018#if !defined(CONFIG_USER_ONLY)
3019 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3020 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3021 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3022 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3023 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3024 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3025 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3026 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3027 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3028 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3029 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3030 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3031 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3032 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3033 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3034 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3035 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3036 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3037 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
faadf50e 3038 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3039 /* Hardware reset vector */
3040 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3041#endif
3042}
e1833e1f
JM		 3043
3044#if defined (TARGET_PPC64)
3045static void init_excp_970 (CPUPPCState *env)
3046{
3047#if !defined(CONFIG_USER_ONLY)
3048 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3049 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3050 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3051 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3052 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3053 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3054 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3055 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3056 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3057 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3058 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3059 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3060 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3061 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3062 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3063 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3064 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3065 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3066 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3067 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
faadf50e 3068 env->excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3069 /* Hardware reset vector */
3070 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3071#endif
3072}
3073#endif
3074
2f462816
JM		 3075/*****************************************************************************/
3076/* Power management enable checks */
3077static int check_pow_none (CPUPPCState *env)
3078{
3079 return 0;
3080}
3081
3082static int check_pow_nocheck (CPUPPCState *env)
3083{
3084 return 1;
3085}
3086
3087static int check_pow_hid0 (CPUPPCState *env)
3088{
3089 if (env->spr[SPR_HID0] & 0x00E00000)
3090 return 1;
3091
3092 return 0;
3093}
3094
4e777442
JM		 3095static int check_pow_hid0_74xx (CPUPPCState *env)
3096{
3097 if (env->spr[SPR_HID0] & 0x00600000)
3098 return 1;
3099
3100 return 0;
3101}
3102
a750fc0b
JM		 3103/*****************************************************************************/
3104/* PowerPC implementations definitions */
76a66253 3105
a750fc0b 3106/* PowerPC 401 */
082c6681
JM		 3107#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3108 PPC_WRTEE | PPC_DCR | \
3109 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3110 PPC_CACHE_DCBZ | \
a750fc0b 3111 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3112 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3113#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3114#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3115#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3116#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3117#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3118#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3119 POWERPC_FLAG_BUS_CLK)
2f462816 3120#define check_pow_401 check_pow_nocheck
76a66253 3121
a750fc0b
JM		 3122static void init_proc_401 (CPUPPCState *env)
3123{
3124 gen_spr_40x(env);
3125 gen_spr_401_403(env);
3126 gen_spr_401(env);
e1833e1f 3127 init_excp_4xx_real(env);
d63001d1
JM		 3128 env->dcache_line_size = 32;
3129 env->icache_line_size = 32;
4e290a0b
JM		 3130 /* Allocate hardware IRQ controller */
3131 ppc40x_irq_init(env);
a750fc0b 3132}
76a66253 3133
a750fc0b 3134/* PowerPC 401x2 */
082c6681
JM		 3135#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3136 PPC_DCR | PPC_WRTEE | \
3137 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3138 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3139 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3140 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3141 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3142#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3143#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3144#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3145#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3146#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3147#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3148 POWERPC_FLAG_BUS_CLK)
2f462816 3149#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3150
3151static void init_proc_401x2 (CPUPPCState *env)
3152{
3153 gen_spr_40x(env);
3154 gen_spr_401_403(env);
3155 gen_spr_401x2(env);
3156 gen_spr_compress(env);
a750fc0b 3157 /* Memory management */
f2e63a42 3158#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3159 env->nb_tlb = 64;
3160 env->nb_ways = 1;
3161 env->id_tlbs = 0;
f2e63a42 3162#endif
e1833e1f 3163 init_excp_4xx_softmmu(env);
d63001d1
JM		 3164 env->dcache_line_size = 32;
3165 env->icache_line_size = 32;
4e290a0b
JM		 3166 /* Allocate hardware IRQ controller */
3167 ppc40x_irq_init(env);
76a66253
JM		 3168}
3169
a750fc0b 3170/* PowerPC 401x3 */
082c6681
JM		 3171#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3172 PPC_DCR | PPC_WRTEE | \
3173 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3174 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3175 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3176 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3177 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3178#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3179#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3180#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3181#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3182#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3183#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3184 POWERPC_FLAG_BUS_CLK)
2f462816 3185#define check_pow_401x3 check_pow_nocheck
a750fc0b 3186
578bb252 3187__attribute__ (( unused ))
e1833e1f 3188static void init_proc_401x3 (CPUPPCState *env)
76a66253 3189{
4e290a0b
JM		 3190 gen_spr_40x(env);
3191 gen_spr_401_403(env);
3192 gen_spr_401(env);
3193 gen_spr_401x2(env);
3194 gen_spr_compress(env);
e1833e1f 3195 init_excp_4xx_softmmu(env);
d63001d1
JM		 3196 env->dcache_line_size = 32;
3197 env->icache_line_size = 32;
4e290a0b
JM		 3198 /* Allocate hardware IRQ controller */
3199 ppc40x_irq_init(env);
3fc6c082 3200}
a750fc0b
JM		 3201
3202/* IOP480 */
082c6681
JM		 3203#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3204 PPC_DCR | PPC_WRTEE | \
3205 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3207 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3208 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3209 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3210#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3211#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3212#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3213#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3214#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3215#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3216 POWERPC_FLAG_BUS_CLK)
2f462816 3217#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3218
3219static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3220{
a750fc0b
JM		 3221 gen_spr_40x(env);
3222 gen_spr_401_403(env);
3223 gen_spr_401x2(env);
3224 gen_spr_compress(env);
a750fc0b 3225 /* Memory management */
f2e63a42 3226#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3227 env->nb_tlb = 64;
3228 env->nb_ways = 1;
3229 env->id_tlbs = 0;
f2e63a42 3230#endif
e1833e1f 3231 init_excp_4xx_softmmu(env);
d63001d1
JM		 3232 env->dcache_line_size = 32;
3233 env->icache_line_size = 32;
4e290a0b
JM		 3234 /* Allocate hardware IRQ controller */
3235 ppc40x_irq_init(env);
3fc6c082
FB		 3236}
3237
a750fc0b 3238/* PowerPC 403 */
082c6681
JM		 3239#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3240 PPC_DCR | PPC_WRTEE | \
3241 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3242 PPC_CACHE_DCBZ | \
a750fc0b 3243 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3244 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3245#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3246#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3247#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3248#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3249#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3250#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3251 POWERPC_FLAG_BUS_CLK)
2f462816 3252#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3253
3254static void init_proc_403 (CPUPPCState *env)
3fc6c082 3255{
a750fc0b
JM		 3256 gen_spr_40x(env);
3257 gen_spr_401_403(env);
3258 gen_spr_403(env);
3259 gen_spr_403_real(env);
e1833e1f 3260 init_excp_4xx_real(env);
d63001d1
JM		 3261 env->dcache_line_size = 32;
3262 env->icache_line_size = 32;
4e290a0b
JM		 3263 /* Allocate hardware IRQ controller */
3264 ppc40x_irq_init(env);
3fc6c082
FB		 3265}
3266
a750fc0b 3267/* PowerPC 403 GCX */
082c6681
JM		 3268#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3269 PPC_DCR | PPC_WRTEE | \
3270 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3271 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3272 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3273 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3274 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3275#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3276#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3277#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3278#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3279#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3280#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3281 POWERPC_FLAG_BUS_CLK)
2f462816 3282#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3283
3284static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3285{
a750fc0b
JM		 3286 gen_spr_40x(env);
3287 gen_spr_401_403(env);
3288 gen_spr_403(env);
3289 gen_spr_403_real(env);
3290 gen_spr_403_mmu(env);
3291 /* Bus access control */
035feb88 3292 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3293 spr_register(env, SPR_40x_SGR, "SGR",
3294 SPR_NOACCESS, SPR_NOACCESS,
3295 &spr_read_generic, &spr_write_generic,
3296 0xFFFFFFFF);
035feb88 3297 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3298 spr_register(env, SPR_40x_DCWR, "DCWR",
3299 SPR_NOACCESS, SPR_NOACCESS,
3300 &spr_read_generic, &spr_write_generic,
3301 0x00000000);
3302 /* Memory management */
f2e63a42 3303#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3304 env->nb_tlb = 64;
3305 env->nb_ways = 1;
3306 env->id_tlbs = 0;
f2e63a42 3307#endif
80d11f44
JM		 3308 init_excp_4xx_softmmu(env);
3309 env->dcache_line_size = 32;
3310 env->icache_line_size = 32;
3311 /* Allocate hardware IRQ controller */
3312 ppc40x_irq_init(env);
3313}
3314
3315/* PowerPC 405 */
082c6681
JM		 3316#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3317 PPC_DCR | PPC_WRTEE | \
3318 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3319 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3320 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3321 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3322 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
80d11f44
JM		 3323#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3324#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3325#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3326#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3327#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3328#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3329 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3330#define check_pow_405 check_pow_nocheck
3331
3332static void init_proc_405 (CPUPPCState *env)
3333{
3334 /* Time base */
3335 gen_tbl(env);
3336 gen_spr_40x(env);
3337 gen_spr_405(env);
3338 /* Bus access control */
3339 /* not emulated, as Qemu never does speculative access */
3340 spr_register(env, SPR_40x_SGR, "SGR",
3341 SPR_NOACCESS, SPR_NOACCESS,
3342 &spr_read_generic, &spr_write_generic,
3343 0xFFFFFFFF);
3344 /* not emulated, as Qemu do not emulate caches */
3345 spr_register(env, SPR_40x_DCWR, "DCWR",
3346 SPR_NOACCESS, SPR_NOACCESS,
3347 &spr_read_generic, &spr_write_generic,
3348 0x00000000);
3349 /* Memory management */
3350#if !defined(CONFIG_USER_ONLY)
3351 env->nb_tlb = 64;
3352 env->nb_ways = 1;
3353 env->id_tlbs = 0;
3354#endif
3355 init_excp_4xx_softmmu(env);
3356 env->dcache_line_size = 32;
3357 env->icache_line_size = 32;
3358 /* Allocate hardware IRQ controller */
3359 ppc40x_irq_init(env);
3360}
3361
3362/* PowerPC 440 EP */
082c6681
JM		 3363#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3364 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3365 PPC_CACHE | PPC_CACHE_ICBI | \
3366 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3367 PPC_MEM_TLBSYNC | \
80d11f44 3368 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3369 PPC_440_SPEC)
80d11f44
JM		 3370#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3371#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3372#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3373#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3374#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3375#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3376 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3377#define check_pow_440EP check_pow_nocheck
3378
3379__attribute__ (( unused ))
3380static void init_proc_440EP (CPUPPCState *env)
3381{
3382 /* Time base */
3383 gen_tbl(env);
3384 gen_spr_BookE(env, 0x000000000000FFFFULL);
3385 gen_spr_440(env);
3386 gen_spr_usprgh(env);
3387 /* Processor identification */
3388 spr_register(env, SPR_BOOKE_PIR, "PIR",
3389 SPR_NOACCESS, SPR_NOACCESS,
3390 &spr_read_generic, &spr_write_pir,
3391 0x00000000);
3392 /* XXX : not implemented */
3393 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3394 SPR_NOACCESS, SPR_NOACCESS,
3395 &spr_read_generic, &spr_write_generic,
3396 0x00000000);
3397 /* XXX : not implemented */
3398 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3399 SPR_NOACCESS, SPR_NOACCESS,
3400 &spr_read_generic, &spr_write_generic,
3401 0x00000000);
3402 /* XXX : not implemented */
3403 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3404 SPR_NOACCESS, SPR_NOACCESS,
3405 &spr_read_generic, &spr_write_generic,
3406 0x00000000);
3407 /* XXX : not implemented */
3408 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3409 SPR_NOACCESS, SPR_NOACCESS,
3410 &spr_read_generic, &spr_write_generic,
3411 0x00000000);
3412 /* XXX : not implemented */
3413 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_generic,
3416 0x00000000);
3417 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3418 SPR_NOACCESS, SPR_NOACCESS,
3419 &spr_read_generic, &spr_write_generic,
3420 0x00000000);
3421 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3422 SPR_NOACCESS, SPR_NOACCESS,
3423 &spr_read_generic, &spr_write_generic,
3424 0x00000000);
3425 /* XXX : not implemented */
3426 spr_register(env, SPR_440_CCR1, "CCR1",
3427 SPR_NOACCESS, SPR_NOACCESS,
3428 &spr_read_generic, &spr_write_generic,
3429 0x00000000);
3430 /* Memory management */
3431#if !defined(CONFIG_USER_ONLY)
3432 env->nb_tlb = 64;
3433 env->nb_ways = 1;
3434 env->id_tlbs = 0;
3435#endif
3436 init_excp_BookE(env);
3437 env->dcache_line_size = 32;
3438 env->icache_line_size = 32;
3439 /* XXX: TODO: allocate internal IRQ controller */
3440}
3441
3442/* PowerPC 440 GP */
082c6681
JM		 3443#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3444 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3445 PPC_CACHE | PPC_CACHE_ICBI | \
3446 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3447 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3448 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3449 PPC_440_SPEC)
80d11f44
JM		 3450#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3451#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3452#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3453#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3454#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3455#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3456 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3457#define check_pow_440GP check_pow_nocheck
3458
3459__attribute__ (( unused ))
3460static void init_proc_440GP (CPUPPCState *env)
3461{
3462 /* Time base */
3463 gen_tbl(env);
3464 gen_spr_BookE(env, 0x000000000000FFFFULL);
3465 gen_spr_440(env);
3466 gen_spr_usprgh(env);
3467 /* Processor identification */
3468 spr_register(env, SPR_BOOKE_PIR, "PIR",
3469 SPR_NOACCESS, SPR_NOACCESS,
3470 &spr_read_generic, &spr_write_pir,
3471 0x00000000);
3472 /* XXX : not implemented */
3473 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3474 SPR_NOACCESS, SPR_NOACCESS,
3475 &spr_read_generic, &spr_write_generic,
3476 0x00000000);
3477 /* XXX : not implemented */
3478 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3479 SPR_NOACCESS, SPR_NOACCESS,
3480 &spr_read_generic, &spr_write_generic,
3481 0x00000000);
3482 /* XXX : not implemented */
3483 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3484 SPR_NOACCESS, SPR_NOACCESS,
3485 &spr_read_generic, &spr_write_generic,
3486 0x00000000);
3487 /* XXX : not implemented */
3488 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3489 SPR_NOACCESS, SPR_NOACCESS,
3490 &spr_read_generic, &spr_write_generic,
3491 0x00000000);
3492 /* Memory management */
3493#if !defined(CONFIG_USER_ONLY)
3494 env->nb_tlb = 64;
3495 env->nb_ways = 1;
3496 env->id_tlbs = 0;
3497#endif
3498 init_excp_BookE(env);
3499 env->dcache_line_size = 32;
3500 env->icache_line_size = 32;
3501 /* XXX: TODO: allocate internal IRQ controller */
3502}
3503
3504/* PowerPC 440x4 */
082c6681
JM		 3505#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3506 PPC_DCR | PPC_WRTEE | \
3507 PPC_CACHE | PPC_CACHE_ICBI | \
3508 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3509 PPC_MEM_TLBSYNC | \
80d11f44
JM		 3510 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3511 PPC_440_SPEC)
3512#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3513#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3514#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3515#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3516#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3517#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3518 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3519#define check_pow_440x4 check_pow_nocheck
3520
3521__attribute__ (( unused ))
3522static void init_proc_440x4 (CPUPPCState *env)
3523{
3524 /* Time base */
3525 gen_tbl(env);
3526 gen_spr_BookE(env, 0x000000000000FFFFULL);
3527 gen_spr_440(env);
3528 gen_spr_usprgh(env);
3529 /* Processor identification */
3530 spr_register(env, SPR_BOOKE_PIR, "PIR",
3531 SPR_NOACCESS, SPR_NOACCESS,
3532 &spr_read_generic, &spr_write_pir,
3533 0x00000000);
3534 /* XXX : not implemented */
3535 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3536 SPR_NOACCESS, SPR_NOACCESS,
3537 &spr_read_generic, &spr_write_generic,
3538 0x00000000);
3539 /* XXX : not implemented */
3540 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3541 SPR_NOACCESS, SPR_NOACCESS,
3542 &spr_read_generic, &spr_write_generic,
3543 0x00000000);
3544 /* XXX : not implemented */
3545 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3546 SPR_NOACCESS, SPR_NOACCESS,
3547 &spr_read_generic, &spr_write_generic,
3548 0x00000000);
3549 /* XXX : not implemented */
3550 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3551 SPR_NOACCESS, SPR_NOACCESS,
3552 &spr_read_generic, &spr_write_generic,
3553 0x00000000);
3554 /* Memory management */
3555#if !defined(CONFIG_USER_ONLY)
3556 env->nb_tlb = 64;
3557 env->nb_ways = 1;
3558 env->id_tlbs = 0;
3559#endif
3560 init_excp_BookE(env);
d63001d1
JM		 3561 env->dcache_line_size = 32;
3562 env->icache_line_size = 32;
80d11f44 3563 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3564}
3565
80d11f44 3566/* PowerPC 440x5 */
082c6681
JM		 3567#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3568 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3569 PPC_CACHE | PPC_CACHE_ICBI | \
3570 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3571 PPC_MEM_TLBSYNC | \
80d11f44 3572 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3573 PPC_440_SPEC)
80d11f44
JM		 3574#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3575#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3576#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3577#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3578#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3579#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3580 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3581#define check_pow_440x5 check_pow_nocheck
a750fc0b 3582
80d11f44
JM		 3583__attribute__ (( unused ))
3584static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3585{
a750fc0b
JM		 3586 /* Time base */
3587 gen_tbl(env);
80d11f44
JM		 3588 gen_spr_BookE(env, 0x000000000000FFFFULL);
3589 gen_spr_440(env);
3590 gen_spr_usprgh(env);
3591 /* Processor identification */
3592 spr_register(env, SPR_BOOKE_PIR, "PIR",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_pir,
3595 0x00000000);
3596 /* XXX : not implemented */
3597 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3598 SPR_NOACCESS, SPR_NOACCESS,
3599 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3600 0x00000000);
3601 /* XXX : not implemented */
3602 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3603 SPR_NOACCESS, SPR_NOACCESS,
3604 &spr_read_generic, &spr_write_generic,
3605 0x00000000);
3606 /* XXX : not implemented */
3607 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3608 SPR_NOACCESS, SPR_NOACCESS,
3609 &spr_read_generic, &spr_write_generic,
3610 0x00000000);
3611 /* XXX : not implemented */
3612 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3613 SPR_NOACCESS, SPR_NOACCESS,
3614 &spr_read_generic, &spr_write_generic,
3615 0x00000000);
3616 /* XXX : not implemented */
3617 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3618 SPR_NOACCESS, SPR_NOACCESS,
3619 &spr_read_generic, &spr_write_generic,
3620 0x00000000);
3621 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 /* XXX : not implemented */
3630 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634 /* Memory management */
f2e63a42 3635#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3636 env->nb_tlb = 64;
3637 env->nb_ways = 1;
3638 env->id_tlbs = 0;
f2e63a42 3639#endif
80d11f44 3640 init_excp_BookE(env);
d63001d1
JM		 3641 env->dcache_line_size = 32;
3642 env->icache_line_size = 32;
80d11f44 3643 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3644}
3645
80d11f44 3646/* PowerPC 460 (guessed) */
082c6681 3647#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3648 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
082c6681
JM		 3649 PPC_WRTEE | PPC_MFAPIDI | \
3650 PPC_CACHE | PPC_CACHE_ICBI | \
3651 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3652 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3653 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3654 PPC_440_SPEC)
80d11f44
JM		 3655#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3656#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3657#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3658#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3659#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3660#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3661 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3662#define check_pow_460 check_pow_nocheck
a750fc0b 3663
80d11f44
JM		 3664__attribute__ (( unused ))
3665static void init_proc_460 (CPUPPCState *env)
3fc6c082 3666{
a750fc0b
JM		 3667 /* Time base */
3668 gen_tbl(env);
80d11f44 3669 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3670 gen_spr_440(env);
80d11f44
JM		 3671 gen_spr_usprgh(env);
3672 /* Processor identification */
3673 spr_register(env, SPR_BOOKE_PIR, "PIR",
3674 SPR_NOACCESS, SPR_NOACCESS,
3675 &spr_read_generic, &spr_write_pir,
3676 0x00000000);
3677 /* XXX : not implemented */
3678 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3679 SPR_NOACCESS, SPR_NOACCESS,
3680 &spr_read_generic, &spr_write_generic,
3681 0x00000000);
3682 /* XXX : not implemented */
3683 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3686 0x00000000);
3687 /* XXX : not implemented */
3688 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3689 SPR_NOACCESS, SPR_NOACCESS,
3690 &spr_read_generic, &spr_write_generic,
3691 0x00000000);
3692 /* XXX : not implemented */
3693 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3694 SPR_NOACCESS, SPR_NOACCESS,
3695 &spr_read_generic, &spr_write_generic,
3696 0x00000000);
578bb252 3697 /* XXX : not implemented */
a750fc0b
JM		 3698 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_generic,
3701 0x00000000);
3702 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3703 SPR_NOACCESS, SPR_NOACCESS,
3704 &spr_read_generic, &spr_write_generic,
3705 0x00000000);
3706 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3707 SPR_NOACCESS, SPR_NOACCESS,
3708 &spr_read_generic, &spr_write_generic,
3709 0x00000000);
578bb252 3710 /* XXX : not implemented */
a750fc0b
JM		 3711 spr_register(env, SPR_440_CCR1, "CCR1",
3712 SPR_NOACCESS, SPR_NOACCESS,
3713 &spr_read_generic, &spr_write_generic,
3714 0x00000000);
80d11f44
JM		 3715 /* XXX : not implemented */
3716 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3717 &spr_read_generic, &spr_write_generic,
3718 &spr_read_generic, &spr_write_generic,
3719 0x00000000);
a750fc0b 3720 /* Memory management */
f2e63a42 3721#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3722 env->nb_tlb = 64;
3723 env->nb_ways = 1;
3724 env->id_tlbs = 0;
f2e63a42 3725#endif
e1833e1f 3726 init_excp_BookE(env);
d63001d1
JM		 3727 env->dcache_line_size = 32;
3728 env->icache_line_size = 32;
a750fc0b 3729 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3730}
3731
80d11f44 3732/* PowerPC 460F (guessed) */
082c6681
JM		 3733#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3734 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3735 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
80d11f44 3736 PPC_FLOAT_STFIWX | \
082c6681
JM		 3737 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3738 PPC_WRTEE | PPC_MFAPIDI | \
3739 PPC_CACHE | PPC_CACHE_ICBI | \
3740 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3741 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3742 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3743 PPC_440_SPEC)
80d11f44
JM		 3744#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3745#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3746#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3747#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3748#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3749#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3750 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3751#define check_pow_460F check_pow_nocheck
a750fc0b 3752
80d11f44
JM		 3753__attribute__ (( unused ))
3754static void init_proc_460F (CPUPPCState *env)
3fc6c082 3755{
a750fc0b
JM		 3756 /* Time base */
3757 gen_tbl(env);
80d11f44 3758 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3759 gen_spr_440(env);
80d11f44
JM		 3760 gen_spr_usprgh(env);
3761 /* Processor identification */
3762 spr_register(env, SPR_BOOKE_PIR, "PIR",
3763 SPR_NOACCESS, SPR_NOACCESS,
3764 &spr_read_generic, &spr_write_pir,
3765 0x00000000);
3766 /* XXX : not implemented */
3767 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3768 SPR_NOACCESS, SPR_NOACCESS,
3769 &spr_read_generic, &spr_write_generic,
3770 0x00000000);
3771 /* XXX : not implemented */
3772 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3773 SPR_NOACCESS, SPR_NOACCESS,
3774 &spr_read_generic, &spr_write_generic,
3775 0x00000000);
3776 /* XXX : not implemented */
3777 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3778 SPR_NOACCESS, SPR_NOACCESS,
3779 &spr_read_generic, &spr_write_generic,
3780 0x00000000);
3781 /* XXX : not implemented */
3782 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3783 SPR_NOACCESS, SPR_NOACCESS,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3796 SPR_NOACCESS, SPR_NOACCESS,
3797 &spr_read_generic, &spr_write_generic,
3798 0x00000000);
3799 /* XXX : not implemented */
3800 spr_register(env, SPR_440_CCR1, "CCR1",
3801 SPR_NOACCESS, SPR_NOACCESS,
3802 &spr_read_generic, &spr_write_generic,
3803 0x00000000);
3804 /* XXX : not implemented */
3805 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3806 &spr_read_generic, &spr_write_generic,
3807 &spr_read_generic, &spr_write_generic,
3808 0x00000000);
a750fc0b 3809 /* Memory management */
f2e63a42 3810#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3811 env->nb_tlb = 64;
3812 env->nb_ways = 1;
3813 env->id_tlbs = 0;
f2e63a42 3814#endif
e1833e1f 3815 init_excp_BookE(env);
d63001d1
JM		 3816 env->dcache_line_size = 32;
3817 env->icache_line_size = 32;
a750fc0b 3818 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3819}
3820
80d11f44
JM		 3821/* Freescale 5xx cores (aka RCPU) */
3822#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3823 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3824 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3825 PPC_MFTB)
3826#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3827#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3828#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3829#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3830#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3831#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3832 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3833#define check_pow_MPC5xx check_pow_none
3834
3835__attribute__ (( unused ))
3836static void init_proc_MPC5xx (CPUPPCState *env)
3837{
3838 /* Time base */
3839 gen_tbl(env);
3840 gen_spr_5xx_8xx(env);
3841 gen_spr_5xx(env);
3842 init_excp_MPC5xx(env);
3843 env->dcache_line_size = 32;
3844 env->icache_line_size = 32;
3845 /* XXX: TODO: allocate internal IRQ controller */
3846}
3847
3848/* Freescale 8xx cores (aka PowerQUICC) */
3849#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3850 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3851 PPC_CACHE_ICBI | PPC_MFTB)
3852#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3853#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3854#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3855#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3856#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3857#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3858 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3859#define check_pow_MPC8xx check_pow_none
3860
3861__attribute__ (( unused ))
3862static void init_proc_MPC8xx (CPUPPCState *env)
3863{
3864 /* Time base */
3865 gen_tbl(env);
3866 gen_spr_5xx_8xx(env);
3867 gen_spr_8xx(env);
3868 init_excp_MPC8xx(env);
3869 env->dcache_line_size = 32;
3870 env->icache_line_size = 32;
3871 /* XXX: TODO: allocate internal IRQ controller */
3872}
3873
3874/* Freescale 82xx cores (aka PowerQUICC-II) */
3875/* PowerPC G2 */
082c6681
JM		 3876#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3877 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3878 PPC_FLOAT_STFIWX | \
3879 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3880 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3881 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3882 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3883#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3884#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3885//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3886#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3887#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3888#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3889 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3890#define check_pow_G2 check_pow_hid0
a750fc0b 3891
80d11f44 3892static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3893{
80d11f44
JM		 3894 gen_spr_ne_601(env);
3895 gen_spr_G2_755(env);
3896 gen_spr_G2(env);
a750fc0b
JM		 3897 /* Time base */
3898 gen_tbl(env);
bd928eba
JM		 3899 /* External access control */
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_EAR, "EAR",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
80d11f44
JM		 3905 /* Hardware implementation register */
3906 /* XXX : not implemented */
3907 spr_register(env, SPR_HID0, "HID0",
3908 SPR_NOACCESS, SPR_NOACCESS,
3909 &spr_read_generic, &spr_write_generic,
3910 0x00000000);
3911 /* XXX : not implemented */
3912 spr_register(env, SPR_HID1, "HID1",
3913 SPR_NOACCESS, SPR_NOACCESS,
3914 &spr_read_generic, &spr_write_generic,
3915 0x00000000);
3916 /* XXX : not implemented */
3917 spr_register(env, SPR_HID2, "HID2",
3918 SPR_NOACCESS, SPR_NOACCESS,
3919 &spr_read_generic, &spr_write_generic,
3920 0x00000000);
a750fc0b 3921 /* Memory management */
80d11f44
JM		 3922 gen_low_BATs(env);
3923 gen_high_BATs(env);
3924 gen_6xx_7xx_soft_tlb(env, 64, 2);
3925 init_excp_G2(env);
d63001d1
JM		 3926 env->dcache_line_size = 32;
3927 env->icache_line_size = 32;
80d11f44
JM		 3928 /* Allocate hardware IRQ controller */
3929 ppc6xx_irq_init(env);
3fc6c082 3930}
a750fc0b 3931
80d11f44 3932/* PowerPC G2LE */
082c6681
JM		 3933#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3934 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3935 PPC_FLOAT_STFIWX | \
3936 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3937 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3938 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3939 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3940#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3941#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3942#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3943#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3944#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3945#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3946 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3947#define check_pow_G2LE check_pow_hid0
a750fc0b 3948
80d11f44 3949static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3950{
80d11f44
JM		 3951 gen_spr_ne_601(env);
3952 gen_spr_G2_755(env);
3953 gen_spr_G2(env);
a750fc0b
JM		 3954 /* Time base */
3955 gen_tbl(env);
bd928eba
JM		 3956 /* External access control */
3957 /* XXX : not implemented */
3958 spr_register(env, SPR_EAR, "EAR",
3959 SPR_NOACCESS, SPR_NOACCESS,
3960 &spr_read_generic, &spr_write_generic,
3961 0x00000000);
80d11f44 3962 /* Hardware implementation register */
578bb252 3963 /* XXX : not implemented */
80d11f44 3964 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3965 SPR_NOACCESS, SPR_NOACCESS,
3966 &spr_read_generic, &spr_write_generic,
3967 0x00000000);
80d11f44
JM		 3968 /* XXX : not implemented */
3969 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3970 SPR_NOACCESS, SPR_NOACCESS,
3971 &spr_read_generic, &spr_write_generic,
3972 0x00000000);
578bb252 3973 /* XXX : not implemented */
80d11f44 3974 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 /* Memory management */
80d11f44
JM		 3979 gen_low_BATs(env);
3980 gen_high_BATs(env);
3981 gen_6xx_7xx_soft_tlb(env, 64, 2);
3982 init_excp_G2(env);
d63001d1
JM		 3983 env->dcache_line_size = 32;
3984 env->icache_line_size = 32;
80d11f44
JM		 3985 /* Allocate hardware IRQ controller */
3986 ppc6xx_irq_init(env);
3fc6c082
FB		 3987}
3988
80d11f44
JM		 3989/* e200 core */
3990/* XXX: unimplemented instructions:
3991 * dcblc
3992 * dcbtlst
3993 * dcbtstls
3994 * icblc
3995 * icbtls
3996 * tlbivax
3997 * all SPE multiply-accumulate instructions
3998 */
082c6681 3999#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4000 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4001 PPC_WRTEE | PPC_RFDI | \
4002 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4003 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4004 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4005 PPC_BOOKE)
80d11f44
JM		 4006#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4007#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
4008#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4009#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4010#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4011#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4012 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4013 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4014#define check_pow_e200 check_pow_hid0
4015
578bb252 4016__attribute__ (( unused ))
80d11f44 4017static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4018{
e1833e1f
JM		 4019 /* Time base */
4020 gen_tbl(env);
80d11f44 4021 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4022 /* XXX : not implemented */
80d11f44 4023 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
e1833e1f
JM		 4024 SPR_NOACCESS, SPR_NOACCESS,
4025 &spr_read_generic, &spr_write_generic,
4026 0x00000000);
80d11f44
JM		 4027 /* Memory management */
4028 gen_spr_BookE_FSL(env, 0x0000005D);
4029 /* XXX : not implemented */
4030 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4031 SPR_NOACCESS, SPR_NOACCESS,
4032 &spr_read_generic, &spr_write_generic,
4033 0x00000000);
80d11f44
JM		 4034 /* XXX : not implemented */
4035 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4036 SPR_NOACCESS, SPR_NOACCESS,
4037 &spr_read_generic, &spr_write_generic,
4038 0x00000000);
578bb252 4039 /* XXX : not implemented */
80d11f44 4040 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, &spr_write_generic,
4043 0x00000000);
578bb252 4044 /* XXX : not implemented */
80d11f44
JM		 4045 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4046 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4047 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4048 0x00000000);
4049 /* XXX : not implemented */
4050 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4051 SPR_NOACCESS, SPR_NOACCESS,
4052 &spr_read_generic, &spr_write_generic,
4053 0x00000000);
4054 /* XXX : not implemented */
4055 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4056 SPR_NOACCESS, SPR_NOACCESS,
4057 &spr_read_generic, &spr_write_generic,
4058 0x00000000);
4059 /* XXX : not implemented */
4060 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4061 SPR_NOACCESS, SPR_NOACCESS,
4062 &spr_read_generic, &spr_write_generic,
4063 0x00000000);
4064 /* XXX : not implemented */
4065 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, &spr_write_generic,
4068 0x00000000);
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000);
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* XXX : not implemented */
4080 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4081 SPR_NOACCESS, SPR_NOACCESS,
4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
4084 /* XXX : not implemented */
4085 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4086 SPR_NOACCESS, SPR_NOACCESS,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 /* XXX : not implemented */
4090 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 /* XXX : not implemented */
4095 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_generic,
4098 0x00000000);
4099 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, &spr_write_generic,
4102 0x00000000);
4103 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4104 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4105 &spr_read_generic, &spr_write_generic,
4106 0x00000000);
f2e63a42 4107#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4108 env->nb_tlb = 64;
4109 env->nb_ways = 1;
4110 env->id_tlbs = 0;
f2e63a42 4111#endif
80d11f44 4112 init_excp_e200(env);
d63001d1
JM		 4113 env->dcache_line_size = 32;
4114 env->icache_line_size = 32;
e1833e1f 4115 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4116}
a750fc0b 4117
80d11f44 4118/* e300 core */
082c6681
JM		 4119#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4120 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4121 PPC_FLOAT_STFIWX | \
4122 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4123 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4124 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4125 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4126#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4127#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4128#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4129#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4130#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4131#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4132 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4133#define check_pow_e300 check_pow_hid0
a750fc0b 4134
578bb252 4135__attribute__ (( unused ))
80d11f44 4136static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4137{
80d11f44
JM		 4138 gen_spr_ne_601(env);
4139 gen_spr_603(env);
a750fc0b
JM		 4140 /* Time base */
4141 gen_tbl(env);
80d11f44
JM		 4142 /* hardware implementation registers */
4143 /* XXX : not implemented */
4144 spr_register(env, SPR_HID0, "HID0",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_HID1, "HID1",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 /* Memory management */
4154 gen_low_BATs(env);
4155 gen_6xx_7xx_soft_tlb(env, 64, 2);
4156 init_excp_603(env);
4157 env->dcache_line_size = 32;
4158 env->icache_line_size = 32;
4159 /* Allocate hardware IRQ controller */
4160 ppc6xx_irq_init(env);
4161}
4162
bd5ea513
AJ		 4163/* e500v1 core */
4164#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4165 PPC_SPE | PPC_SPE_SINGLE | \
4166 PPC_WRTEE | PPC_RFDI | \
4167 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4168 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4169 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4170 PPC_BOOKE)
4171#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4172#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
4173#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4174#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4175#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4176#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4177 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4178 POWERPC_FLAG_BUS_CLK)
4179#define check_pow_e500v1 check_pow_hid0
4180#define init_proc_e500v1 init_proc_e500
4181
4182/* e500v2 core */
4183#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4184 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4185 PPC_WRTEE | PPC_RFDI | \
4186 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4187 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4188 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4189 PPC_BOOKE)
4190#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4191#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
4192#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4193#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4194#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4195#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4196 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4197 POWERPC_FLAG_BUS_CLK)
4198#define check_pow_e500v2 check_pow_hid0
4199#define init_proc_e500v2 init_proc_e500
80d11f44
JM		 4200
4201__attribute__ (( unused ))
4202static void init_proc_e500 (CPUPPCState *env)
4203{
4204 /* Time base */
4205 gen_tbl(env);
4206 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4207 /* Processor identification */
4208 spr_register(env, SPR_BOOKE_PIR, "PIR",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_pir,
4211 0x00000000);
4212 /* XXX : not implemented */
4213 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 /* Memory management */
4218#if !defined(CONFIG_USER_ONLY)
4219 env->nb_pids = 3;
4220#endif
4221 gen_spr_BookE_FSL(env, 0x0000005F);
4222 /* XXX : not implemented */
4223 spr_register(env, SPR_HID0, "HID0",
4224 SPR_NOACCESS, SPR_NOACCESS,
4225 &spr_read_generic, &spr_write_generic,
4226 0x00000000);
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_HID1, "HID1",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
4237 /* XXX : not implemented */
4238 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
578bb252 4247 /* XXX : not implemented */
a750fc0b
JM		 4248 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
80d11f44
JM		 4252 /* XXX : not implemented */
4253 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4254 SPR_NOACCESS, SPR_NOACCESS,
4255 &spr_read_generic, &spr_write_generic,
4256 0x00000000);
80d11f44
JM		 4257 /* XXX : not implemented */
4258 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4259 SPR_NOACCESS, SPR_NOACCESS,
4260 &spr_read_generic, &spr_write_generic,
4261 0x00000000);
578bb252 4262 /* XXX : not implemented */
80d11f44 4263 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4264 SPR_NOACCESS, SPR_NOACCESS,
4265 &spr_read_generic, &spr_write_generic,
4266 0x00000000);
578bb252 4267 /* XXX : not implemented */
80d11f44
JM		 4268 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4269 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4270 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4271 0x00000000);
4272 /* XXX : not implemented */
4273 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277 /* XXX : not implemented */
4278 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4292 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4293 &spr_read_generic, &spr_write_generic,
4294 0x00000000);
f2e63a42 4295#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4296 env->nb_tlb = 64;
4297 env->nb_ways = 1;
4298 env->id_tlbs = 0;
f2e63a42 4299#endif
80d11f44 4300 init_excp_e200(env);
d63001d1
JM		 4301 env->dcache_line_size = 32;
4302 env->icache_line_size = 32;
a750fc0b 4303 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4304}
a750fc0b 4305
a750fc0b 4306/* Non-embedded PowerPC */
a750fc0b
JM		 4307
4308/* POWER : same as 601, without mfmsr, mfsr */
4309#if defined(TODO)
4310#define POWERPC_INSNS_POWER (XXX_TODO)
4311/* POWER RSC (from RAD6000) */
4312#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4313#endif /* TODO */
4314
4315/* PowerPC 601 */
082c6681
JM		 4316#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4317 PPC_FLOAT | \
4318 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4319 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4320 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4321#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4322#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4323//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4324//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4325#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4326#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4327#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4328#define check_pow_601 check_pow_none
a750fc0b
JM		 4329
4330static void init_proc_601 (CPUPPCState *env)
3fc6c082 4331{
a750fc0b
JM		 4332 gen_spr_ne_601(env);
4333 gen_spr_601(env);
4334 /* Hardware implementation registers */
4335 /* XXX : not implemented */
4336 spr_register(env, SPR_HID0, "HID0",
4337 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4338 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4339 0x80010080);
a750fc0b
JM		 4340 /* XXX : not implemented */
4341 spr_register(env, SPR_HID1, "HID1",
4342 SPR_NOACCESS, SPR_NOACCESS,
4343 &spr_read_generic, &spr_write_generic,
4344 0x00000000);
4345 /* XXX : not implemented */
4346 spr_register(env, SPR_601_HID2, "HID2",
4347 SPR_NOACCESS, SPR_NOACCESS,
4348 &spr_read_generic, &spr_write_generic,
4349 0x00000000);
4350 /* XXX : not implemented */
4351 spr_register(env, SPR_601_HID5, "HID5",
4352 SPR_NOACCESS, SPR_NOACCESS,
4353 &spr_read_generic, &spr_write_generic,
4354 0x00000000);
a750fc0b 4355 /* Memory management */
e1833e1f 4356 init_excp_601(env);
082c6681
JM		 4357 /* XXX: beware that dcache line size is 64
4358 * but dcbz uses 32 bytes "sectors"
4359 * XXX: this breaks clcs instruction !
4360 */
4361 env->dcache_line_size = 32;
d63001d1 4362 env->icache_line_size = 64;
faadf50e
JM		 4363 /* Allocate hardware IRQ controller */
4364 ppc6xx_irq_init(env);
3fc6c082
FB		 4365}
4366
082c6681
JM		 4367/* PowerPC 601v */
4368#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4369 PPC_FLOAT | \
4370 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4371 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4372 PPC_SEGMENT | PPC_EXTERN)
4373#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4374#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4375#define POWERPC_MMU_601v (POWERPC_MMU_601)
4376#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4377#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4378#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4379#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4380#define check_pow_601v check_pow_none
4381
4382static void init_proc_601v (CPUPPCState *env)
4383{
4384 init_proc_601(env);
4385 /* XXX : not implemented */
4386 spr_register(env, SPR_601_HID15, "HID15",
4387 SPR_NOACCESS, SPR_NOACCESS,
4388 &spr_read_generic, &spr_write_generic,
4389 0x00000000);
4390}
4391
a750fc0b 4392/* PowerPC 602 */
082c6681
JM		 4393#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4395 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4396 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4397 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4398 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4399 PPC_SEGMENT | PPC_602_SPEC)
082c6681
JM		 4400#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4401/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4402#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4403//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4404#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4405#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4406#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4407 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4408#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4409
4410static void init_proc_602 (CPUPPCState *env)
3fc6c082 4411{
a750fc0b
JM		 4412 gen_spr_ne_601(env);
4413 gen_spr_602(env);
4414 /* Time base */
4415 gen_tbl(env);
4416 /* hardware implementation registers */
4417 /* XXX : not implemented */
4418 spr_register(env, SPR_HID0, "HID0",
4419 SPR_NOACCESS, SPR_NOACCESS,
4420 &spr_read_generic, &spr_write_generic,
4421 0x00000000);
4422 /* XXX : not implemented */
4423 spr_register(env, SPR_HID1, "HID1",
4424 SPR_NOACCESS, SPR_NOACCESS,
4425 &spr_read_generic, &spr_write_generic,
4426 0x00000000);
4427 /* Memory management */
4428 gen_low_BATs(env);
4429 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4430 init_excp_602(env);
d63001d1
JM		 4431 env->dcache_line_size = 32;
4432 env->icache_line_size = 32;
a750fc0b
JM		 4433 /* Allocate hardware IRQ controller */
4434 ppc6xx_irq_init(env);
4435}
3fc6c082 4436
a750fc0b 4437/* PowerPC 603 */
082c6681
JM		 4438#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4439 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4440 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4441 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4442 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4443 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4444 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4445#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4446#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4447//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4448#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4449#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4450#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4451 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4452#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4453
4454static void init_proc_603 (CPUPPCState *env)
4455{
4456 gen_spr_ne_601(env);
4457 gen_spr_603(env);
4458 /* Time base */
4459 gen_tbl(env);
4460 /* hardware implementation registers */
4461 /* XXX : not implemented */
4462 spr_register(env, SPR_HID0, "HID0",
4463 SPR_NOACCESS, SPR_NOACCESS,
4464 &spr_read_generic, &spr_write_generic,
4465 0x00000000);
4466 /* XXX : not implemented */
4467 spr_register(env, SPR_HID1, "HID1",
4468 SPR_NOACCESS, SPR_NOACCESS,
4469 &spr_read_generic, &spr_write_generic,
4470 0x00000000);
4471 /* Memory management */
4472 gen_low_BATs(env);
4473 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4474 init_excp_603(env);
d63001d1
JM		 4475 env->dcache_line_size = 32;
4476 env->icache_line_size = 32;
a750fc0b
JM		 4477 /* Allocate hardware IRQ controller */
4478 ppc6xx_irq_init(env);
3fc6c082
FB		 4479}
4480
a750fc0b 4481/* PowerPC 603e */
082c6681
JM		 4482#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4483 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4484 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4485 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4486 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4487 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4488 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4489#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4490#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4491//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4492#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4493#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4494#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4495 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4496#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4497
4498static void init_proc_603E (CPUPPCState *env)
4499{
4500 gen_spr_ne_601(env);
4501 gen_spr_603(env);
4502 /* Time base */
4503 gen_tbl(env);
4504 /* hardware implementation registers */
4505 /* XXX : not implemented */
4506 spr_register(env, SPR_HID0, "HID0",
4507 SPR_NOACCESS, SPR_NOACCESS,
4508 &spr_read_generic, &spr_write_generic,
4509 0x00000000);
4510 /* XXX : not implemented */
4511 spr_register(env, SPR_HID1, "HID1",
4512 SPR_NOACCESS, SPR_NOACCESS,
4513 &spr_read_generic, &spr_write_generic,
4514 0x00000000);
4515 /* XXX : not implemented */
4516 spr_register(env, SPR_IABR, "IABR",
4517 SPR_NOACCESS, SPR_NOACCESS,
4518 &spr_read_generic, &spr_write_generic,
4519 0x00000000);
4520 /* Memory management */
4521 gen_low_BATs(env);
4522 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4523 init_excp_603(env);
d63001d1
JM		 4524 env->dcache_line_size = 32;
4525 env->icache_line_size = 32;
a750fc0b
JM		 4526 /* Allocate hardware IRQ controller */
4527 ppc6xx_irq_init(env);
4528}
4529
a750fc0b 4530/* PowerPC 604 */
082c6681
JM		 4531#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4532 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4533 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4534 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4535 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4536 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4537 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4538#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4539#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4540//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4541#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4542#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4543#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4544 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4545#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4546
4547static void init_proc_604 (CPUPPCState *env)
4548{
4549 gen_spr_ne_601(env);
4550 gen_spr_604(env);
4551 /* Time base */
4552 gen_tbl(env);
4553 /* Hardware implementation registers */
4554 /* XXX : not implemented */
082c6681
JM		 4555 spr_register(env, SPR_HID0, "HID0",
4556 SPR_NOACCESS, SPR_NOACCESS,
4557 &spr_read_generic, &spr_write_generic,
4558 0x00000000);
4559 /* Memory management */
4560 gen_low_BATs(env);
4561 init_excp_604(env);
4562 env->dcache_line_size = 32;
4563 env->icache_line_size = 32;
4564 /* Allocate hardware IRQ controller */
4565 ppc6xx_irq_init(env);
4566}
4567
4568/* PowerPC 604E */
4569#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4570 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4571 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4572 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4573 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4574 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4575 PPC_SEGMENT | PPC_EXTERN)
4576#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4577#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4578#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4579#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4580#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4581#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4582 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4583#define check_pow_604E check_pow_nocheck
4584
4585static void init_proc_604E (CPUPPCState *env)
4586{
4587 gen_spr_ne_601(env);
4588 gen_spr_604(env);
4589 /* XXX : not implemented */
4590 spr_register(env, SPR_MMCR1, "MMCR1",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, &spr_write_generic,
4593 0x00000000);
4594 /* XXX : not implemented */
4595 spr_register(env, SPR_PMC3, "PMC3",
4596 SPR_NOACCESS, SPR_NOACCESS,
4597 &spr_read_generic, &spr_write_generic,
4598 0x00000000);
4599 /* XXX : not implemented */
4600 spr_register(env, SPR_PMC4, "PMC4",
4601 SPR_NOACCESS, SPR_NOACCESS,
4602 &spr_read_generic, &spr_write_generic,
4603 0x00000000);
4604 /* Time base */
4605 gen_tbl(env);
4606 /* Hardware implementation registers */
4607 /* XXX : not implemented */
a750fc0b
JM		 4608 spr_register(env, SPR_HID0, "HID0",
4609 SPR_NOACCESS, SPR_NOACCESS,
4610 &spr_read_generic, &spr_write_generic,
4611 0x00000000);
4612 /* XXX : not implemented */
4613 spr_register(env, SPR_HID1, "HID1",
4614 SPR_NOACCESS, SPR_NOACCESS,
4615 &spr_read_generic, &spr_write_generic,
4616 0x00000000);
4617 /* Memory management */
4618 gen_low_BATs(env);
e1833e1f 4619 init_excp_604(env);
d63001d1
JM		 4620 env->dcache_line_size = 32;
4621 env->icache_line_size = 32;
a750fc0b
JM		 4622 /* Allocate hardware IRQ controller */
4623 ppc6xx_irq_init(env);
4624}
4625
bd928eba
JM		 4626/* PowerPC 740 */
4627#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4628 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4629 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4630 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4631 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4632 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4633 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 4634#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4635#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4636#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4637#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4638#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4639#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4640 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4641#define check_pow_740 check_pow_hid0
a750fc0b 4642
bd928eba 4643static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4644{
4645 gen_spr_ne_601(env);
4646 gen_spr_7xx(env);
4647 /* Time base */
4648 gen_tbl(env);
4649 /* Thermal management */
4650 gen_spr_thrm(env);
4651 /* Hardware implementation registers */
4652 /* XXX : not implemented */
4653 spr_register(env, SPR_HID0, "HID0",
4654 SPR_NOACCESS, SPR_NOACCESS,
4655 &spr_read_generic, &spr_write_generic,
4656 0x00000000);
4657 /* XXX : not implemented */
4658 spr_register(env, SPR_HID1, "HID1",
4659 SPR_NOACCESS, SPR_NOACCESS,
4660 &spr_read_generic, &spr_write_generic,
4661 0x00000000);
4662 /* Memory management */
4663 gen_low_BATs(env);
e1833e1f 4664 init_excp_7x0(env);
d63001d1
JM		 4665 env->dcache_line_size = 32;
4666 env->icache_line_size = 32;
a750fc0b
JM		 4667 /* Allocate hardware IRQ controller */
4668 ppc6xx_irq_init(env);
4669}
4670
bd928eba
JM		 4671/* PowerPC 750 */
4672#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4673 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4674 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4675 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4676 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4677 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4678 PPC_SEGMENT | PPC_EXTERN)
4679#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4680#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4681#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4682#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4683#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4684#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4685 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4686#define check_pow_750 check_pow_hid0
4687
4688static void init_proc_750 (CPUPPCState *env)
4689{
4690 gen_spr_ne_601(env);
4691 gen_spr_7xx(env);
4692 /* XXX : not implemented */
4693 spr_register(env, SPR_L2CR, "L2CR",
4694 SPR_NOACCESS, SPR_NOACCESS,
4695 &spr_read_generic, &spr_write_generic,
4696 0x00000000);
4697 /* Time base */
4698 gen_tbl(env);
4699 /* Thermal management */
4700 gen_spr_thrm(env);
4701 /* Hardware implementation registers */
4702 /* XXX : not implemented */
4703 spr_register(env, SPR_HID0, "HID0",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 /* XXX : not implemented */
4708 spr_register(env, SPR_HID1, "HID1",
4709 SPR_NOACCESS, SPR_NOACCESS,
4710 &spr_read_generic, &spr_write_generic,
4711 0x00000000);
4712 /* Memory management */
4713 gen_low_BATs(env);
4714 /* XXX: high BATs are also present but are known to be bugged on
4715 * die version 1.x
4716 */
4717 init_excp_7x0(env);
4718 env->dcache_line_size = 32;
4719 env->icache_line_size = 32;
4720 /* Allocate hardware IRQ controller */
4721 ppc6xx_irq_init(env);
4722}
4723
4724/* PowerPC 750 CL */
4725/* XXX: not implemented:
4726 * cache lock instructions:
4727 * dcbz_l
4728 * floating point paired instructions
4729 * psq_lux
4730 * psq_lx
4731 * psq_stux
4732 * psq_stx
4733 * ps_abs
4734 * ps_add
4735 * ps_cmpo0
4736 * ps_cmpo1
4737 * ps_cmpu0
4738 * ps_cmpu1
4739 * ps_div
4740 * ps_madd
4741 * ps_madds0
4742 * ps_madds1
4743 * ps_merge00
4744 * ps_merge01
4745 * ps_merge10
4746 * ps_merge11
4747 * ps_mr
4748 * ps_msub
4749 * ps_mul
4750 * ps_muls0
4751 * ps_muls1
4752 * ps_nabs
4753 * ps_neg
4754 * ps_nmadd
4755 * ps_nmsub
4756 * ps_res
4757 * ps_rsqrte
4758 * ps_sel
4759 * ps_sub
4760 * ps_sum0
4761 * ps_sum1
4762 */
4763#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4765 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4766 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4767 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4769 PPC_SEGMENT | PPC_EXTERN)
4770#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4771#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4772#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4773#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4774#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4775#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4776 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4777#define check_pow_750cl check_pow_hid0
4778
4779static void init_proc_750cl (CPUPPCState *env)
4780{
4781 gen_spr_ne_601(env);
4782 gen_spr_7xx(env);
4783 /* XXX : not implemented */
4784 spr_register(env, SPR_L2CR, "L2CR",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788 /* Time base */
4789 gen_tbl(env);
4790 /* Thermal management */
4791 /* Those registers are fake on 750CL */
4792 spr_register(env, SPR_THRM1, "THRM1",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 spr_register(env, SPR_THRM2, "THRM2",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800 spr_register(env, SPR_THRM3, "THRM3",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, &spr_write_generic,
4803 0x00000000);
4804 /* XXX: not implemented */
4805 spr_register(env, SPR_750_TDCL, "TDCL",
4806 SPR_NOACCESS, SPR_NOACCESS,
4807 &spr_read_generic, &spr_write_generic,
4808 0x00000000);
4809 spr_register(env, SPR_750_TDCH, "TDCH",
4810 SPR_NOACCESS, SPR_NOACCESS,
4811 &spr_read_generic, &spr_write_generic,
4812 0x00000000);
4813 /* DMA */
4814 /* XXX : not implemented */
4815 spr_register(env, SPR_750_WPAR, "WPAR",
4816 SPR_NOACCESS, SPR_NOACCESS,
4817 &spr_read_generic, &spr_write_generic,
4818 0x00000000);
4819 spr_register(env, SPR_750_DMAL, "DMAL",
4820 SPR_NOACCESS, SPR_NOACCESS,
4821 &spr_read_generic, &spr_write_generic,
4822 0x00000000);
4823 spr_register(env, SPR_750_DMAU, "DMAU",
4824 SPR_NOACCESS, SPR_NOACCESS,
4825 &spr_read_generic, &spr_write_generic,
4826 0x00000000);
4827 /* Hardware implementation registers */
4828 /* XXX : not implemented */
4829 spr_register(env, SPR_HID0, "HID0",
4830 SPR_NOACCESS, SPR_NOACCESS,
4831 &spr_read_generic, &spr_write_generic,
4832 0x00000000);
4833 /* XXX : not implemented */
4834 spr_register(env, SPR_HID1, "HID1",
4835 SPR_NOACCESS, SPR_NOACCESS,
4836 &spr_read_generic, &spr_write_generic,
4837 0x00000000);
4838 /* XXX : not implemented */
4839 spr_register(env, SPR_750CL_HID2, "HID2",
4840 SPR_NOACCESS, SPR_NOACCESS,
4841 &spr_read_generic, &spr_write_generic,
4842 0x00000000);
4843 /* XXX : not implemented */
4844 spr_register(env, SPR_750CL_HID4, "HID4",
4845 SPR_NOACCESS, SPR_NOACCESS,
4846 &spr_read_generic, &spr_write_generic,
4847 0x00000000);
4848 /* Quantization registers */
4849 /* XXX : not implemented */
4850 spr_register(env, SPR_750_GQR0, "GQR0",
4851 SPR_NOACCESS, SPR_NOACCESS,
4852 &spr_read_generic, &spr_write_generic,
4853 0x00000000);
4854 /* XXX : not implemented */
4855 spr_register(env, SPR_750_GQR1, "GQR1",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 /* XXX : not implemented */
4860 spr_register(env, SPR_750_GQR2, "GQR2",
4861 SPR_NOACCESS, SPR_NOACCESS,
4862 &spr_read_generic, &spr_write_generic,
4863 0x00000000);
4864 /* XXX : not implemented */
4865 spr_register(env, SPR_750_GQR3, "GQR3",
4866 SPR_NOACCESS, SPR_NOACCESS,
4867 &spr_read_generic, &spr_write_generic,
4868 0x00000000);
4869 /* XXX : not implemented */
4870 spr_register(env, SPR_750_GQR4, "GQR4",
4871 SPR_NOACCESS, SPR_NOACCESS,
4872 &spr_read_generic, &spr_write_generic,
4873 0x00000000);
4874 /* XXX : not implemented */
4875 spr_register(env, SPR_750_GQR5, "GQR5",
4876 SPR_NOACCESS, SPR_NOACCESS,
4877 &spr_read_generic, &spr_write_generic,
4878 0x00000000);
4879 /* XXX : not implemented */
4880 spr_register(env, SPR_750_GQR6, "GQR6",
4881 SPR_NOACCESS, SPR_NOACCESS,
4882 &spr_read_generic, &spr_write_generic,
4883 0x00000000);
4884 /* XXX : not implemented */
4885 spr_register(env, SPR_750_GQR7, "GQR7",
4886 SPR_NOACCESS, SPR_NOACCESS,
4887 &spr_read_generic, &spr_write_generic,
4888 0x00000000);
4889 /* Memory management */
4890 gen_low_BATs(env);
4891 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4892 gen_high_BATs(env);
4893 init_excp_750cl(env);
4894 env->dcache_line_size = 32;
4895 env->icache_line_size = 32;
4896 /* Allocate hardware IRQ controller */
4897 ppc6xx_irq_init(env);
4898}
4899
4e777442 4900/* PowerPC 750CX */
bd928eba
JM		 4901#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4902 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4903 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4904 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4905 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4906 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4907 PPC_SEGMENT | PPC_EXTERN)
4908#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4909#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4910#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4911#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4912#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4913#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4914 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4915#define check_pow_750cx check_pow_hid0
4916
4917static void init_proc_750cx (CPUPPCState *env)
4918{
4919 gen_spr_ne_601(env);
4920 gen_spr_7xx(env);
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_L2CR, "L2CR",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926 /* Time base */
4927 gen_tbl(env);
4928 /* Thermal management */
4929 gen_spr_thrm(env);
4930 /* This register is not implemented but is present for compatibility */
4931 spr_register(env, SPR_SDA, "SDA",
4932 SPR_NOACCESS, SPR_NOACCESS,
4933 &spr_read_generic, &spr_write_generic,
4934 0x00000000);
4935 /* Hardware implementation registers */
4936 /* XXX : not implemented */
4937 spr_register(env, SPR_HID0, "HID0",
4938 SPR_NOACCESS, SPR_NOACCESS,
4939 &spr_read_generic, &spr_write_generic,
4940 0x00000000);
4941 /* XXX : not implemented */
4942 spr_register(env, SPR_HID1, "HID1",
4943 SPR_NOACCESS, SPR_NOACCESS,
4944 &spr_read_generic, &spr_write_generic,
4945 0x00000000);
4946 /* Memory management */
4947 gen_low_BATs(env);
4e777442
JM		 4948 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4949 gen_high_BATs(env);
bd928eba
JM		 4950 init_excp_750cx(env);
4951 env->dcache_line_size = 32;
4952 env->icache_line_size = 32;
4953 /* Allocate hardware IRQ controller */
4954 ppc6xx_irq_init(env);
4955}
4956
4957/* PowerPC 750FX */
082c6681
JM		 4958#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4959 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4960 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4961 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4962 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4963 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4964 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4965#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4966#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4967#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4968#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4969#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 4970#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4971 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4972#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4973
4974static void init_proc_750fx (CPUPPCState *env)
4975{
4976 gen_spr_ne_601(env);
4977 gen_spr_7xx(env);
bd928eba
JM		 4978 /* XXX : not implemented */
4979 spr_register(env, SPR_L2CR, "L2CR",
4980 SPR_NOACCESS, SPR_NOACCESS,
4981 &spr_read_generic, &spr_write_generic,
4982 0x00000000);
a750fc0b
JM		 4983 /* Time base */
4984 gen_tbl(env);
4985 /* Thermal management */
4986 gen_spr_thrm(env);
bd928eba
JM		 4987 /* XXX : not implemented */
4988 spr_register(env, SPR_750_THRM4, "THRM4",
4989 SPR_NOACCESS, SPR_NOACCESS,
4990 &spr_read_generic, &spr_write_generic,
4991 0x00000000);
a750fc0b
JM		 4992 /* Hardware implementation registers */
4993 /* XXX : not implemented */
4994 spr_register(env, SPR_HID0, "HID0",
4995 SPR_NOACCESS, SPR_NOACCESS,
4996 &spr_read_generic, &spr_write_generic,
4997 0x00000000);
4998 /* XXX : not implemented */
4999 spr_register(env, SPR_HID1, "HID1",
5000 SPR_NOACCESS, SPR_NOACCESS,
5001 &spr_read_generic, &spr_write_generic,
5002 0x00000000);
5003 /* XXX : not implemented */
bd928eba 5004 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5005 SPR_NOACCESS, SPR_NOACCESS,
5006 &spr_read_generic, &spr_write_generic,
5007 0x00000000);
5008 /* Memory management */
5009 gen_low_BATs(env);
5010 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5011 gen_high_BATs(env);
bd928eba 5012 init_excp_7x0(env);
d63001d1
JM		 5013 env->dcache_line_size = 32;
5014 env->icache_line_size = 32;
a750fc0b
JM		 5015 /* Allocate hardware IRQ controller */
5016 ppc6xx_irq_init(env);
5017}
5018
bd928eba
JM		 5019/* PowerPC 750GX */
5020#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5021 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5022 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5023 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5024 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5025 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5026 PPC_SEGMENT | PPC_EXTERN)
5027#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5028#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5029#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5030#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5031#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5032#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5033 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5034#define check_pow_750gx check_pow_hid0
5035
5036static void init_proc_750gx (CPUPPCState *env)
5037{
5038 gen_spr_ne_601(env);
5039 gen_spr_7xx(env);
5040 /* XXX : not implemented (XXX: different from 750fx) */
5041 spr_register(env, SPR_L2CR, "L2CR",
5042 SPR_NOACCESS, SPR_NOACCESS,
5043 &spr_read_generic, &spr_write_generic,
5044 0x00000000);
5045 /* Time base */
5046 gen_tbl(env);
5047 /* Thermal management */
5048 gen_spr_thrm(env);
5049 /* XXX : not implemented */
5050 spr_register(env, SPR_750_THRM4, "THRM4",
5051 SPR_NOACCESS, SPR_NOACCESS,
5052 &spr_read_generic, &spr_write_generic,
5053 0x00000000);
5054 /* Hardware implementation registers */
5055 /* XXX : not implemented (XXX: different from 750fx) */
5056 spr_register(env, SPR_HID0, "HID0",
5057 SPR_NOACCESS, SPR_NOACCESS,
5058 &spr_read_generic, &spr_write_generic,
5059 0x00000000);
5060 /* XXX : not implemented */
5061 spr_register(env, SPR_HID1, "HID1",
5062 SPR_NOACCESS, SPR_NOACCESS,
5063 &spr_read_generic, &spr_write_generic,
5064 0x00000000);
5065 /* XXX : not implemented (XXX: different from 750fx) */
5066 spr_register(env, SPR_750FX_HID2, "HID2",
5067 SPR_NOACCESS, SPR_NOACCESS,
5068 &spr_read_generic, &spr_write_generic,
5069 0x00000000);
5070 /* Memory management */
5071 gen_low_BATs(env);
5072 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5073 gen_high_BATs(env);
5074 init_excp_7x0(env);
5075 env->dcache_line_size = 32;
5076 env->icache_line_size = 32;
5077 /* Allocate hardware IRQ controller */
5078 ppc6xx_irq_init(env);
5079}
5080
5081/* PowerPC 745 */
5082#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5084 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5086 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5088 PPC_SEGMENT | PPC_EXTERN)
5089#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5090#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5091#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5092#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5093#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5094#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5095 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5096#define check_pow_745 check_pow_hid0
5097
5098static void init_proc_745 (CPUPPCState *env)
5099{
5100 gen_spr_ne_601(env);
5101 gen_spr_7xx(env);
5102 gen_spr_G2_755(env);
5103 /* Time base */
5104 gen_tbl(env);
5105 /* Thermal management */
5106 gen_spr_thrm(env);
5107 /* Hardware implementation registers */
5108 /* XXX : not implemented */
5109 spr_register(env, SPR_HID0, "HID0",
5110 SPR_NOACCESS, SPR_NOACCESS,
5111 &spr_read_generic, &spr_write_generic,
5112 0x00000000);
5113 /* XXX : not implemented */
5114 spr_register(env, SPR_HID1, "HID1",
5115 SPR_NOACCESS, SPR_NOACCESS,
5116 &spr_read_generic, &spr_write_generic,
5117 0x00000000);
5118 /* XXX : not implemented */
5119 spr_register(env, SPR_HID2, "HID2",
5120 SPR_NOACCESS, SPR_NOACCESS,
5121 &spr_read_generic, &spr_write_generic,
5122 0x00000000);
5123 /* Memory management */
5124 gen_low_BATs(env);
5125 gen_high_BATs(env);
5126 gen_6xx_7xx_soft_tlb(env, 64, 2);
5127 init_excp_7x5(env);
5128 env->dcache_line_size = 32;
5129 env->icache_line_size = 32;
5130 /* Allocate hardware IRQ controller */
5131 ppc6xx_irq_init(env);
5132}
5133
5134/* PowerPC 755 */
5135#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5136 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5137 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5138 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5139 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5140 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5141 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 5142#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5143#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5144#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5145#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5146#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5147#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5148 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5149#define check_pow_755 check_pow_hid0
a750fc0b 5150
bd928eba 5151static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5152{
5153 gen_spr_ne_601(env);
bd928eba 5154 gen_spr_7xx(env);
a750fc0b
JM		 5155 gen_spr_G2_755(env);
5156 /* Time base */
5157 gen_tbl(env);
5158 /* L2 cache control */
5159 /* XXX : not implemented */
bd928eba 5160 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_generic, &spr_write_generic,
5163 0x00000000);
5164 /* XXX : not implemented */
5165 spr_register(env, SPR_L2PMCR, "L2PMCR",
5166 SPR_NOACCESS, SPR_NOACCESS,
5167 &spr_read_generic, &spr_write_generic,
5168 0x00000000);
bd928eba
JM		 5169 /* Thermal management */
5170 gen_spr_thrm(env);
a750fc0b
JM		 5171 /* Hardware implementation registers */
5172 /* XXX : not implemented */
5173 spr_register(env, SPR_HID0, "HID0",
5174 SPR_NOACCESS, SPR_NOACCESS,
5175 &spr_read_generic, &spr_write_generic,
5176 0x00000000);
5177 /* XXX : not implemented */
5178 spr_register(env, SPR_HID1, "HID1",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 /* XXX : not implemented */
5183 spr_register(env, SPR_HID2, "HID2",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 0x00000000);
5187 /* Memory management */
5188 gen_low_BATs(env);
5189 gen_high_BATs(env);
5190 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5191 init_excp_7x5(env);
d63001d1
JM		 5192 env->dcache_line_size = 32;
5193 env->icache_line_size = 32;
a750fc0b
JM		 5194 /* Allocate hardware IRQ controller */
5195 ppc6xx_irq_init(env);
5196}
5197
5198/* PowerPC 7400 (aka G4) */
082c6681
JM		 5199#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5200 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5201 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5202 PPC_FLOAT_STFIWX | \
5203 PPC_CACHE | PPC_CACHE_ICBI | \
5204 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5205 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5206 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5207 PPC_MEM_TLBIA | \
5208 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5209 PPC_ALTIVEC)
5210#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5211#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5212#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5213#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5214#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5215#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5216 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5217 POWERPC_FLAG_BUS_CLK)
4e777442 5218#define check_pow_7400 check_pow_hid0_74xx
a750fc0b
JM		 5219
5220static void init_proc_7400 (CPUPPCState *env)
5221{
5222 gen_spr_ne_601(env);
5223 gen_spr_7xx(env);
5224 /* Time base */
5225 gen_tbl(env);
5226 /* 74xx specific SPR */
5227 gen_spr_74xx(env);
4e777442
JM		 5228 /* XXX : not implemented */
5229 spr_register(env, SPR_UBAMR, "UBAMR",
5230 &spr_read_ureg, SPR_NOACCESS,
5231 &spr_read_ureg, SPR_NOACCESS,
5232 0x00000000);
5233 /* XXX: this seems not implemented on all revisions. */
5234 /* XXX : not implemented */
5235 spr_register(env, SPR_MSSCR1, "MSSCR1",
5236 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic,
5238 0x00000000);
a750fc0b
JM		 5239 /* Thermal management */
5240 gen_spr_thrm(env);
5241 /* Memory management */
5242 gen_low_BATs(env);
e1833e1f 5243 init_excp_7400(env);
d63001d1
JM		 5244 env->dcache_line_size = 32;
5245 env->icache_line_size = 32;
a750fc0b
JM		 5246 /* Allocate hardware IRQ controller */
5247 ppc6xx_irq_init(env);
5248}
5249
5250/* PowerPC 7410 (aka G4) */
082c6681
JM		 5251#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5252 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5253 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5254 PPC_FLOAT_STFIWX | \
5255 PPC_CACHE | PPC_CACHE_ICBI | \
5256 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5257 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5258 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5259 PPC_MEM_TLBIA | \
5260 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5261 PPC_ALTIVEC)
5262#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5263#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5264#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5265#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5266#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5267#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5268 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5269 POWERPC_FLAG_BUS_CLK)
4e777442 5270#define check_pow_7410 check_pow_hid0_74xx
a750fc0b
JM		 5271
5272static void init_proc_7410 (CPUPPCState *env)
5273{
5274 gen_spr_ne_601(env);
5275 gen_spr_7xx(env);
5276 /* Time base */
5277 gen_tbl(env);
5278 /* 74xx specific SPR */
5279 gen_spr_74xx(env);
4e777442
JM		 5280 /* XXX : not implemented */
5281 spr_register(env, SPR_UBAMR, "UBAMR",
5282 &spr_read_ureg, SPR_NOACCESS,
5283 &spr_read_ureg, SPR_NOACCESS,
5284 0x00000000);
a750fc0b
JM		 5285 /* Thermal management */
5286 gen_spr_thrm(env);
5287 /* L2PMCR */
5288 /* XXX : not implemented */
5289 spr_register(env, SPR_L2PMCR, "L2PMCR",
5290 SPR_NOACCESS, SPR_NOACCESS,
5291 &spr_read_generic, &spr_write_generic,
5292 0x00000000);
5293 /* LDSTDB */
5294 /* XXX : not implemented */
5295 spr_register(env, SPR_LDSTDB, "LDSTDB",
5296 SPR_NOACCESS, SPR_NOACCESS,
5297 &spr_read_generic, &spr_write_generic,
5298 0x00000000);
5299 /* Memory management */
5300 gen_low_BATs(env);
e1833e1f 5301 init_excp_7400(env);
d63001d1
JM		 5302 env->dcache_line_size = 32;
5303 env->icache_line_size = 32;
a750fc0b
JM		 5304 /* Allocate hardware IRQ controller */
5305 ppc6xx_irq_init(env);
5306}
5307
5308/* PowerPC 7440 (aka G4) */
082c6681
JM		 5309#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5310 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5311 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5312 PPC_FLOAT_STFIWX | \
5313 PPC_CACHE | PPC_CACHE_ICBI | \
5314 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5315 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5317 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5318 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5319 PPC_ALTIVEC)
5320#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5321#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5322#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5323#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5324#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5325#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5326 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5327 POWERPC_FLAG_BUS_CLK)
4e777442 5328#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5329
578bb252 5330__attribute__ (( unused ))
a750fc0b
JM		 5331static void init_proc_7440 (CPUPPCState *env)
5332{
5333 gen_spr_ne_601(env);
5334 gen_spr_7xx(env);
5335 /* Time base */
5336 gen_tbl(env);
5337 /* 74xx specific SPR */
5338 gen_spr_74xx(env);
4e777442
JM		 5339 /* XXX : not implemented */
5340 spr_register(env, SPR_UBAMR, "UBAMR",
5341 &spr_read_ureg, SPR_NOACCESS,
5342 &spr_read_ureg, SPR_NOACCESS,
5343 0x00000000);
a750fc0b
JM		 5344 /* LDSTCR */
5345 /* XXX : not implemented */
5346 spr_register(env, SPR_LDSTCR, "LDSTCR",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 0x00000000);
5350 /* ICTRL */
5351 /* XXX : not implemented */
5352 spr_register(env, SPR_ICTRL, "ICTRL",
5353 SPR_NOACCESS, SPR_NOACCESS,
5354 &spr_read_generic, &spr_write_generic,
5355 0x00000000);
5356 /* MSSSR0 */
578bb252 5357 /* XXX : not implemented */
a750fc0b
JM		 5358 spr_register(env, SPR_MSSSR0, "MSSSR0",
5359 SPR_NOACCESS, SPR_NOACCESS,
5360 &spr_read_generic, &spr_write_generic,
5361 0x00000000);
5362 /* PMC */
5363 /* XXX : not implemented */
5364 spr_register(env, SPR_PMC5, "PMC5",
5365 SPR_NOACCESS, SPR_NOACCESS,
5366 &spr_read_generic, &spr_write_generic,
5367 0x00000000);
578bb252 5368 /* XXX : not implemented */
a750fc0b
JM		 5369 spr_register(env, SPR_UPMC5, "UPMC5",
5370 &spr_read_ureg, SPR_NOACCESS,
5371 &spr_read_ureg, SPR_NOACCESS,
5372 0x00000000);
578bb252 5373 /* XXX : not implemented */
a750fc0b
JM		 5374 spr_register(env, SPR_PMC6, "PMC6",
5375 SPR_NOACCESS, SPR_NOACCESS,
5376 &spr_read_generic, &spr_write_generic,
5377 0x00000000);
578bb252 5378 /* XXX : not implemented */
a750fc0b
JM		 5379 spr_register(env, SPR_UPMC6, "UPMC6",
5380 &spr_read_ureg, SPR_NOACCESS,
5381 &spr_read_ureg, SPR_NOACCESS,
5382 0x00000000);
5383 /* Memory management */
5384 gen_low_BATs(env);
578bb252 5385 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5386 init_excp_7450(env);
d63001d1
JM		 5387 env->dcache_line_size = 32;
5388 env->icache_line_size = 32;
a750fc0b
JM		 5389 /* Allocate hardware IRQ controller */
5390 ppc6xx_irq_init(env);
5391}
a750fc0b
JM		 5392
5393/* PowerPC 7450 (aka G4) */
082c6681
JM		 5394#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5395 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5396 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5397 PPC_FLOAT_STFIWX | \
5398 PPC_CACHE | PPC_CACHE_ICBI | \
5399 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5400 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5401 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5402 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5403 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5404 PPC_ALTIVEC)
5405#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5406#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5407#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5408#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5409#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5410#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5411 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5412 POWERPC_FLAG_BUS_CLK)
4e777442 5413#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5414
578bb252 5415__attribute__ (( unused ))
a750fc0b
JM		 5416static void init_proc_7450 (CPUPPCState *env)
5417{
5418 gen_spr_ne_601(env);
5419 gen_spr_7xx(env);
5420 /* Time base */
5421 gen_tbl(env);
5422 /* 74xx specific SPR */
5423 gen_spr_74xx(env);
5424 /* Level 3 cache control */
5425 gen_l3_ctrl(env);
4e777442
JM		 5426 /* L3ITCR1 */
5427 /* XXX : not implemented */
5428 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5429 SPR_NOACCESS, SPR_NOACCESS,
5430 &spr_read_generic, &spr_write_generic,
5431 0x00000000);
5432 /* L3ITCR2 */
5433 /* XXX : not implemented */
5434 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
5438 /* L3ITCR3 */
5439 /* XXX : not implemented */
5440 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5441 SPR_NOACCESS, SPR_NOACCESS,
5442 &spr_read_generic, &spr_write_generic,
5443 0x00000000);
5444 /* L3OHCR */
5445 /* XXX : not implemented */
5446 spr_register(env, SPR_L3OHCR, "L3OHCR",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 &spr_read_generic, &spr_write_generic,
5449 0x00000000);
5450 /* XXX : not implemented */
5451 spr_register(env, SPR_UBAMR, "UBAMR",
5452 &spr_read_ureg, SPR_NOACCESS,
5453 &spr_read_ureg, SPR_NOACCESS,
5454 0x00000000);
a750fc0b
JM		 5455 /* LDSTCR */
5456 /* XXX : not implemented */
5457 spr_register(env, SPR_LDSTCR, "LDSTCR",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 /* ICTRL */
5462 /* XXX : not implemented */
5463 spr_register(env, SPR_ICTRL, "ICTRL",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, &spr_write_generic,
5466 0x00000000);
5467 /* MSSSR0 */
578bb252 5468 /* XXX : not implemented */
a750fc0b
JM		 5469 spr_register(env, SPR_MSSSR0, "MSSSR0",
5470 SPR_NOACCESS, SPR_NOACCESS,
5471 &spr_read_generic, &spr_write_generic,
5472 0x00000000);
5473 /* PMC */
5474 /* XXX : not implemented */
5475 spr_register(env, SPR_PMC5, "PMC5",
5476 SPR_NOACCESS, SPR_NOACCESS,
5477 &spr_read_generic, &spr_write_generic,
5478 0x00000000);
578bb252 5479 /* XXX : not implemented */
a750fc0b
JM		 5480 spr_register(env, SPR_UPMC5, "UPMC5",
5481 &spr_read_ureg, SPR_NOACCESS,
5482 &spr_read_ureg, SPR_NOACCESS,
5483 0x00000000);
578bb252 5484 /* XXX : not implemented */
a750fc0b
JM		 5485 spr_register(env, SPR_PMC6, "PMC6",
5486 SPR_NOACCESS, SPR_NOACCESS,
5487 &spr_read_generic, &spr_write_generic,
5488 0x00000000);
578bb252 5489 /* XXX : not implemented */
a750fc0b
JM		 5490 spr_register(env, SPR_UPMC6, "UPMC6",
5491 &spr_read_ureg, SPR_NOACCESS,
5492 &spr_read_ureg, SPR_NOACCESS,
5493 0x00000000);
5494 /* Memory management */
5495 gen_low_BATs(env);
578bb252 5496 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5497 init_excp_7450(env);
d63001d1
JM		 5498 env->dcache_line_size = 32;
5499 env->icache_line_size = 32;
a750fc0b
JM		 5500 /* Allocate hardware IRQ controller */
5501 ppc6xx_irq_init(env);
5502}
a750fc0b
JM		 5503
5504/* PowerPC 7445 (aka G4) */
082c6681
JM		 5505#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5506 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5507 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5508 PPC_FLOAT_STFIWX | \
5509 PPC_CACHE | PPC_CACHE_ICBI | \
5510 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5511 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5512 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5513 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5514 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5515 PPC_ALTIVEC)
5516#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5517#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5518#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5519#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5520#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5521#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5522 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5523 POWERPC_FLAG_BUS_CLK)
4e777442 5524#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5525
578bb252 5526__attribute__ (( unused ))
a750fc0b
JM		 5527static void init_proc_7445 (CPUPPCState *env)
5528{
5529 gen_spr_ne_601(env);
5530 gen_spr_7xx(env);
5531 /* Time base */
5532 gen_tbl(env);
5533 /* 74xx specific SPR */
5534 gen_spr_74xx(env);
5535 /* LDSTCR */
5536 /* XXX : not implemented */
5537 spr_register(env, SPR_LDSTCR, "LDSTCR",
5538 SPR_NOACCESS, SPR_NOACCESS,
5539 &spr_read_generic, &spr_write_generic,
5540 0x00000000);
5541 /* ICTRL */
5542 /* XXX : not implemented */
5543 spr_register(env, SPR_ICTRL, "ICTRL",
5544 SPR_NOACCESS, SPR_NOACCESS,
5545 &spr_read_generic, &spr_write_generic,
5546 0x00000000);
5547 /* MSSSR0 */
578bb252 5548 /* XXX : not implemented */
a750fc0b
JM		 5549 spr_register(env, SPR_MSSSR0, "MSSSR0",
5550 SPR_NOACCESS, SPR_NOACCESS,
5551 &spr_read_generic, &spr_write_generic,
5552 0x00000000);
5553 /* PMC */
5554 /* XXX : not implemented */
5555 spr_register(env, SPR_PMC5, "PMC5",
5556 SPR_NOACCESS, SPR_NOACCESS,
5557 &spr_read_generic, &spr_write_generic,
5558 0x00000000);
578bb252 5559 /* XXX : not implemented */
a750fc0b
JM		 5560 spr_register(env, SPR_UPMC5, "UPMC5",
5561 &spr_read_ureg, SPR_NOACCESS,
5562 &spr_read_ureg, SPR_NOACCESS,
5563 0x00000000);
578bb252 5564 /* XXX : not implemented */
a750fc0b
JM		 5565 spr_register(env, SPR_PMC6, "PMC6",
5566 SPR_NOACCESS, SPR_NOACCESS,
5567 &spr_read_generic, &spr_write_generic,
5568 0x00000000);
578bb252 5569 /* XXX : not implemented */
a750fc0b
JM		 5570 spr_register(env, SPR_UPMC6, "UPMC6",
5571 &spr_read_ureg, SPR_NOACCESS,
5572 &spr_read_ureg, SPR_NOACCESS,
5573 0x00000000);
5574 /* SPRGs */
5575 spr_register(env, SPR_SPRG4, "SPRG4",
5576 SPR_NOACCESS, SPR_NOACCESS,
5577 &spr_read_generic, &spr_write_generic,
5578 0x00000000);
5579 spr_register(env, SPR_USPRG4, "USPRG4",
5580 &spr_read_ureg, SPR_NOACCESS,
5581 &spr_read_ureg, SPR_NOACCESS,
5582 0x00000000);
5583 spr_register(env, SPR_SPRG5, "SPRG5",
5584 SPR_NOACCESS, SPR_NOACCESS,
5585 &spr_read_generic, &spr_write_generic,
5586 0x00000000);
5587 spr_register(env, SPR_USPRG5, "USPRG5",
5588 &spr_read_ureg, SPR_NOACCESS,
5589 &spr_read_ureg, SPR_NOACCESS,
5590 0x00000000);
5591 spr_register(env, SPR_SPRG6, "SPRG6",
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_generic,
5594 0x00000000);
5595 spr_register(env, SPR_USPRG6, "USPRG6",
5596 &spr_read_ureg, SPR_NOACCESS,
5597 &spr_read_ureg, SPR_NOACCESS,
5598 0x00000000);
5599 spr_register(env, SPR_SPRG7, "SPRG7",
5600 SPR_NOACCESS, SPR_NOACCESS,
5601 &spr_read_generic, &spr_write_generic,
5602 0x00000000);
5603 spr_register(env, SPR_USPRG7, "USPRG7",
5604 &spr_read_ureg, SPR_NOACCESS,
5605 &spr_read_ureg, SPR_NOACCESS,
5606 0x00000000);
5607 /* Memory management */
5608 gen_low_BATs(env);
5609 gen_high_BATs(env);
578bb252 5610 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5611 init_excp_7450(env);
d63001d1
JM		 5612 env->dcache_line_size = 32;
5613 env->icache_line_size = 32;
a750fc0b
JM		 5614 /* Allocate hardware IRQ controller */
5615 ppc6xx_irq_init(env);
5616}
a750fc0b
JM		 5617
5618/* PowerPC 7455 (aka G4) */
082c6681
JM		 5619#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5620 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5621 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5622 PPC_FLOAT_STFIWX | \
5623 PPC_CACHE | PPC_CACHE_ICBI | \
5624 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5625 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5626 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5627 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5628 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5629 PPC_ALTIVEC)
5630#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5631#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5632#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5633#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5634#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5635#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5636 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5637 POWERPC_FLAG_BUS_CLK)
4e777442 5638#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5639
578bb252 5640__attribute__ (( unused ))
a750fc0b
JM		 5641static void init_proc_7455 (CPUPPCState *env)
5642{
5643 gen_spr_ne_601(env);
5644 gen_spr_7xx(env);
5645 /* Time base */
5646 gen_tbl(env);
5647 /* 74xx specific SPR */
5648 gen_spr_74xx(env);
5649 /* Level 3 cache control */
5650 gen_l3_ctrl(env);
5651 /* LDSTCR */
5652 /* XXX : not implemented */
5653 spr_register(env, SPR_LDSTCR, "LDSTCR",
5654 SPR_NOACCESS, SPR_NOACCESS,
5655 &spr_read_generic, &spr_write_generic,
5656 0x00000000);
5657 /* ICTRL */
5658 /* XXX : not implemented */
5659 spr_register(env, SPR_ICTRL, "ICTRL",
5660 SPR_NOACCESS, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 0x00000000);
5663 /* MSSSR0 */
578bb252 5664 /* XXX : not implemented */
a750fc0b
JM		 5665 spr_register(env, SPR_MSSSR0, "MSSSR0",
5666 SPR_NOACCESS, SPR_NOACCESS,
5667 &spr_read_generic, &spr_write_generic,
5668 0x00000000);
5669 /* PMC */
5670 /* XXX : not implemented */
5671 spr_register(env, SPR_PMC5, "PMC5",
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 &spr_read_generic, &spr_write_generic,
5674 0x00000000);
578bb252 5675 /* XXX : not implemented */
a750fc0b
JM		 5676 spr_register(env, SPR_UPMC5, "UPMC5",
5677 &spr_read_ureg, SPR_NOACCESS,
5678 &spr_read_ureg, SPR_NOACCESS,
5679 0x00000000);
578bb252 5680 /* XXX : not implemented */
a750fc0b
JM		 5681 spr_register(env, SPR_PMC6, "PMC6",
5682 SPR_NOACCESS, SPR_NOACCESS,
5683 &spr_read_generic, &spr_write_generic,
5684 0x00000000);
578bb252 5685 /* XXX : not implemented */
a750fc0b
JM		 5686 spr_register(env, SPR_UPMC6, "UPMC6",
5687 &spr_read_ureg, SPR_NOACCESS,
5688 &spr_read_ureg, SPR_NOACCESS,
5689 0x00000000);
5690 /* SPRGs */
5691 spr_register(env, SPR_SPRG4, "SPRG4",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_generic, &spr_write_generic,
5694 0x00000000);
5695 spr_register(env, SPR_USPRG4, "USPRG4",
5696 &spr_read_ureg, SPR_NOACCESS,
5697 &spr_read_ureg, SPR_NOACCESS,
5698 0x00000000);
5699 spr_register(env, SPR_SPRG5, "SPRG5",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, &spr_write_generic,
5702 0x00000000);
5703 spr_register(env, SPR_USPRG5, "USPRG5",
5704 &spr_read_ureg, SPR_NOACCESS,
5705 &spr_read_ureg, SPR_NOACCESS,
5706 0x00000000);
5707 spr_register(env, SPR_SPRG6, "SPRG6",
5708 SPR_NOACCESS, SPR_NOACCESS,
5709 &spr_read_generic, &spr_write_generic,
5710 0x00000000);
5711 spr_register(env, SPR_USPRG6, "USPRG6",
5712 &spr_read_ureg, SPR_NOACCESS,
5713 &spr_read_ureg, SPR_NOACCESS,
5714 0x00000000);
5715 spr_register(env, SPR_SPRG7, "SPRG7",
5716 SPR_NOACCESS, SPR_NOACCESS,
5717 &spr_read_generic, &spr_write_generic,
5718 0x00000000);
5719 spr_register(env, SPR_USPRG7, "USPRG7",
5720 &spr_read_ureg, SPR_NOACCESS,
5721 &spr_read_ureg, SPR_NOACCESS,
5722 0x00000000);
5723 /* Memory management */
5724 gen_low_BATs(env);
5725 gen_high_BATs(env);
578bb252 5726 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5727 init_excp_7450(env);
d63001d1
JM		 5728 env->dcache_line_size = 32;
5729 env->icache_line_size = 32;
a750fc0b
JM		 5730 /* Allocate hardware IRQ controller */
5731 ppc6xx_irq_init(env);
5732}
a750fc0b 5733
4e777442
JM		 5734/* PowerPC 7457 (aka G4) */
5735#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5736 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5737 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5738 PPC_FLOAT_STFIWX | \
5739 PPC_CACHE | PPC_CACHE_ICBI | \
5740 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5741 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5742 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5743 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5744 PPC_SEGMENT | PPC_EXTERN | \
5745 PPC_ALTIVEC)
5746#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5747#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5748#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5749#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5750#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5751#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5752 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5753 POWERPC_FLAG_BUS_CLK)
5754#define check_pow_7457 check_pow_hid0_74xx
5755
5756__attribute__ (( unused ))
5757static void init_proc_7457 (CPUPPCState *env)
5758{
5759 gen_spr_ne_601(env);
5760 gen_spr_7xx(env);
5761 /* Time base */
5762 gen_tbl(env);
5763 /* 74xx specific SPR */
5764 gen_spr_74xx(env);
5765 /* Level 3 cache control */
5766 gen_l3_ctrl(env);
5767 /* L3ITCR1 */
5768 /* XXX : not implemented */
5769 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5770 SPR_NOACCESS, SPR_NOACCESS,
5771 &spr_read_generic, &spr_write_generic,
5772 0x00000000);
5773 /* L3ITCR2 */
5774 /* XXX : not implemented */
5775 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5776 SPR_NOACCESS, SPR_NOACCESS,
5777 &spr_read_generic, &spr_write_generic,
5778 0x00000000);
5779 /* L3ITCR3 */
5780 /* XXX : not implemented */
5781 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 0x00000000);
5785 /* L3OHCR */
5786 /* XXX : not implemented */
5787 spr_register(env, SPR_L3OHCR, "L3OHCR",
5788 SPR_NOACCESS, SPR_NOACCESS,
5789 &spr_read_generic, &spr_write_generic,
5790 0x00000000);
5791 /* LDSTCR */
5792 /* XXX : not implemented */
5793 spr_register(env, SPR_LDSTCR, "LDSTCR",
5794 SPR_NOACCESS, SPR_NOACCESS,
5795 &spr_read_generic, &spr_write_generic,
5796 0x00000000);
5797 /* ICTRL */
5798 /* XXX : not implemented */
5799 spr_register(env, SPR_ICTRL, "ICTRL",
5800 SPR_NOACCESS, SPR_NOACCESS,
5801 &spr_read_generic, &spr_write_generic,
5802 0x00000000);
5803 /* MSSSR0 */
5804 /* XXX : not implemented */
5805 spr_register(env, SPR_MSSSR0, "MSSSR0",
5806 SPR_NOACCESS, SPR_NOACCESS,
5807 &spr_read_generic, &spr_write_generic,
5808 0x00000000);
5809 /* PMC */
5810 /* XXX : not implemented */
5811 spr_register(env, SPR_PMC5, "PMC5",
5812 SPR_NOACCESS, SPR_NOACCESS,
5813 &spr_read_generic, &spr_write_generic,
5814 0x00000000);
5815 /* XXX : not implemented */
5816 spr_register(env, SPR_UPMC5, "UPMC5",
5817 &spr_read_ureg, SPR_NOACCESS,
5818 &spr_read_ureg, SPR_NOACCESS,
5819 0x00000000);
5820 /* XXX : not implemented */
5821 spr_register(env, SPR_PMC6, "PMC6",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_generic,
5824 0x00000000);
5825 /* XXX : not implemented */
5826 spr_register(env, SPR_UPMC6, "UPMC6",
5827 &spr_read_ureg, SPR_NOACCESS,
5828 &spr_read_ureg, SPR_NOACCESS,
5829 0x00000000);
5830 /* SPRGs */
5831 spr_register(env, SPR_SPRG4, "SPRG4",
5832 SPR_NOACCESS, SPR_NOACCESS,
5833 &spr_read_generic, &spr_write_generic,
5834 0x00000000);
5835 spr_register(env, SPR_USPRG4, "USPRG4",
5836 &spr_read_ureg, SPR_NOACCESS,
5837 &spr_read_ureg, SPR_NOACCESS,
5838 0x00000000);
5839 spr_register(env, SPR_SPRG5, "SPRG5",
5840 SPR_NOACCESS, SPR_NOACCESS,
5841 &spr_read_generic, &spr_write_generic,
5842 0x00000000);
5843 spr_register(env, SPR_USPRG5, "USPRG5",
5844 &spr_read_ureg, SPR_NOACCESS,
5845 &spr_read_ureg, SPR_NOACCESS,
5846 0x00000000);
5847 spr_register(env, SPR_SPRG6, "SPRG6",
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_generic,
5850 0x00000000);
5851 spr_register(env, SPR_USPRG6, "USPRG6",
5852 &spr_read_ureg, SPR_NOACCESS,
5853 &spr_read_ureg, SPR_NOACCESS,
5854 0x00000000);
5855 spr_register(env, SPR_SPRG7, "SPRG7",
5856 SPR_NOACCESS, SPR_NOACCESS,
5857 &spr_read_generic, &spr_write_generic,
5858 0x00000000);
5859 spr_register(env, SPR_USPRG7, "USPRG7",
5860 &spr_read_ureg, SPR_NOACCESS,
5861 &spr_read_ureg, SPR_NOACCESS,
5862 0x00000000);
5863 /* Memory management */
5864 gen_low_BATs(env);
5865 gen_high_BATs(env);
5866 gen_74xx_soft_tlb(env, 128, 2);
5867 init_excp_7450(env);
5868 env->dcache_line_size = 32;
5869 env->icache_line_size = 32;
5870 /* Allocate hardware IRQ controller */
5871 ppc6xx_irq_init(env);
5872}
5873
a750fc0b
JM		 5874#if defined (TARGET_PPC64)
5875/* PowerPC 970 */
082c6681
JM		 5876#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5877 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5878 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5879 PPC_FLOAT_STFIWX | \
5880 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5881 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5882 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5883 PPC_64B | PPC_ALTIVEC | \
12de9a39 5884 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5885#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 5886#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 5887//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5888#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 5889#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 5890#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5891 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5892 POWERPC_FLAG_BUS_CLK)
a750fc0b 5893
417bf010
JM		 5894#if defined(CONFIG_USER_ONLY)
5895#define POWERPC970_HID5_INIT 0x00000080
5896#else
5897#define POWERPC970_HID5_INIT 0x00000000
5898#endif
5899
2f462816
JM		 5900static int check_pow_970 (CPUPPCState *env)
5901{
5902 if (env->spr[SPR_HID0] & 0x00600000)
5903 return 1;
5904
5905 return 0;
5906}
5907
a750fc0b
JM		 5908static void init_proc_970 (CPUPPCState *env)
5909{
5910 gen_spr_ne_601(env);
5911 gen_spr_7xx(env);
5912 /* Time base */
5913 gen_tbl(env);
5914 /* Hardware implementation registers */
5915 /* XXX : not implemented */
5916 spr_register(env, SPR_HID0, "HID0",
5917 SPR_NOACCESS, SPR_NOACCESS,
06403421 5918 &spr_read_generic, &spr_write_clear,
d63001d1 5919 0x60000000);
a750fc0b
JM		 5920 /* XXX : not implemented */
5921 spr_register(env, SPR_HID1, "HID1",
5922 SPR_NOACCESS, SPR_NOACCESS,
5923 &spr_read_generic, &spr_write_generic,
5924 0x00000000);
5925 /* XXX : not implemented */
bd928eba 5926 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5927 SPR_NOACCESS, SPR_NOACCESS,
5928 &spr_read_generic, &spr_write_generic,
5929 0x00000000);
e57448f1
JM		 5930 /* XXX : not implemented */
5931 spr_register(env, SPR_970_HID5, "HID5",
5932 SPR_NOACCESS, SPR_NOACCESS,
5933 &spr_read_generic, &spr_write_generic,
417bf010 5934 POWERPC970_HID5_INIT);
bd928eba
JM		 5935 /* XXX : not implemented */
5936 spr_register(env, SPR_L2CR, "L2CR",
5937 SPR_NOACCESS, SPR_NOACCESS,
5938 &spr_read_generic, &spr_write_generic,
5939 0x00000000);
a750fc0b
JM		 5940 /* Memory management */
5941 /* XXX: not correct */
5942 gen_low_BATs(env);
12de9a39
JM		 5943 /* XXX : not implemented */
5944 spr_register(env, SPR_MMUCFG, "MMUCFG",
5945 SPR_NOACCESS, SPR_NOACCESS,
5946 &spr_read_generic, SPR_NOACCESS,
5947 0x00000000); /* TOFIX */
5948 /* XXX : not implemented */
5949 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5950 SPR_NOACCESS, SPR_NOACCESS,
5951 &spr_read_generic, &spr_write_generic,
5952 0x00000000); /* TOFIX */
5953 spr_register(env, SPR_HIOR, "SPR_HIOR",
5954 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 5955 &spr_read_hior, &spr_write_hior,
5956 0x00000000);
f2e63a42 5957#if !defined(CONFIG_USER_ONLY)
12de9a39 5958 env->slb_nr = 32;
f2e63a42 5959#endif
e1833e1f 5960 init_excp_970(env);
d63001d1
JM		 5961 env->dcache_line_size = 128;
5962 env->icache_line_size = 128;
a750fc0b
JM		 5963 /* Allocate hardware IRQ controller */
5964 ppc970_irq_init(env);
cf8358c8
AJ		 5965 /* Can't find information on what this should be on reset. This
5966 * value is the one used by 74xx processors. */
5967 vscr_init(env, 0x00010000);
a750fc0b 5968}
a750fc0b
JM		 5969
5970/* PowerPC 970FX (aka G5) */
082c6681
JM		 5971#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5972 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5973 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5974 PPC_FLOAT_STFIWX | \
5975 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5976 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5977 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5978 PPC_64B | PPC_ALTIVEC | \
12de9a39 5979 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5980#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 5981#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 5982#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5983#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 5984#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 5985#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5986 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5987 POWERPC_FLAG_BUS_CLK)
a750fc0b 5988
2f462816
JM		 5989static int check_pow_970FX (CPUPPCState *env)
5990{
5991 if (env->spr[SPR_HID0] & 0x00600000)
5992 return 1;
5993
5994 return 0;
5995}
5996
a750fc0b
JM		 5997static void init_proc_970FX (CPUPPCState *env)
5998{
5999 gen_spr_ne_601(env);
6000 gen_spr_7xx(env);
6001 /* Time base */
6002 gen_tbl(env);
6003 /* Hardware implementation registers */
6004 /* XXX : not implemented */
6005 spr_register(env, SPR_HID0, "HID0",
6006 SPR_NOACCESS, SPR_NOACCESS,
06403421 6007 &spr_read_generic, &spr_write_clear,
d63001d1 6008 0x60000000);
a750fc0b
JM		 6009 /* XXX : not implemented */
6010 spr_register(env, SPR_HID1, "HID1",
6011 SPR_NOACCESS, SPR_NOACCESS,
6012 &spr_read_generic, &spr_write_generic,
6013 0x00000000);
6014 /* XXX : not implemented */
bd928eba 6015 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6016 SPR_NOACCESS, SPR_NOACCESS,
6017 &spr_read_generic, &spr_write_generic,
6018 0x00000000);
d63001d1
JM		 6019 /* XXX : not implemented */
6020 spr_register(env, SPR_970_HID5, "HID5",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, &spr_write_generic,
417bf010 6023 POWERPC970_HID5_INIT);
bd928eba
JM		 6024 /* XXX : not implemented */
6025 spr_register(env, SPR_L2CR, "L2CR",
6026 SPR_NOACCESS, SPR_NOACCESS,
6027 &spr_read_generic, &spr_write_generic,
6028 0x00000000);
a750fc0b
JM		 6029 /* Memory management */
6030 /* XXX: not correct */
6031 gen_low_BATs(env);
12de9a39
JM		 6032 /* XXX : not implemented */
6033 spr_register(env, SPR_MMUCFG, "MMUCFG",
6034 SPR_NOACCESS, SPR_NOACCESS,
6035 &spr_read_generic, SPR_NOACCESS,
6036 0x00000000); /* TOFIX */
6037 /* XXX : not implemented */
6038 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6039 SPR_NOACCESS, SPR_NOACCESS,
6040 &spr_read_generic, &spr_write_generic,
6041 0x00000000); /* TOFIX */
6042 spr_register(env, SPR_HIOR, "SPR_HIOR",
6043 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6044 &spr_read_hior, &spr_write_hior,
6045 0x00000000);
f2e63a42 6046#if !defined(CONFIG_USER_ONLY)
12de9a39 6047 env->slb_nr = 32;
f2e63a42 6048#endif
e1833e1f 6049 init_excp_970(env);
d63001d1
JM		 6050 env->dcache_line_size = 128;
6051 env->icache_line_size = 128;
a750fc0b
JM		 6052 /* Allocate hardware IRQ controller */
6053 ppc970_irq_init(env);
cf8358c8
AJ		 6054 /* Can't find information on what this should be on reset. This
6055 * value is the one used by 74xx processors. */
6056 vscr_init(env, 0x00010000);
a750fc0b 6057}
a750fc0b
JM		 6058
6059/* PowerPC 970 GX */
082c6681
JM		 6060#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6061 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6062 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6063 PPC_FLOAT_STFIWX | \
6064 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6065 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6066 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6067 PPC_64B | PPC_ALTIVEC | \
12de9a39 6068 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6069#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6070#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6071#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6072#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6073#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6074#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6075 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6076 POWERPC_FLAG_BUS_CLK)
a750fc0b 6077
2f462816
JM		 6078static int check_pow_970GX (CPUPPCState *env)
6079{
6080 if (env->spr[SPR_HID0] & 0x00600000)
6081 return 1;
6082
6083 return 0;
6084}
6085
a750fc0b
JM		 6086static void init_proc_970GX (CPUPPCState *env)
6087{
6088 gen_spr_ne_601(env);
6089 gen_spr_7xx(env);
6090 /* Time base */
6091 gen_tbl(env);
6092 /* Hardware implementation registers */
6093 /* XXX : not implemented */
6094 spr_register(env, SPR_HID0, "HID0",
6095 SPR_NOACCESS, SPR_NOACCESS,
06403421 6096 &spr_read_generic, &spr_write_clear,
d63001d1 6097 0x60000000);
a750fc0b
JM		 6098 /* XXX : not implemented */
6099 spr_register(env, SPR_HID1, "HID1",
6100 SPR_NOACCESS, SPR_NOACCESS,
6101 &spr_read_generic, &spr_write_generic,
6102 0x00000000);
6103 /* XXX : not implemented */
bd928eba 6104 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6105 SPR_NOACCESS, SPR_NOACCESS,
6106 &spr_read_generic, &spr_write_generic,
6107 0x00000000);
d63001d1
JM		 6108 /* XXX : not implemented */
6109 spr_register(env, SPR_970_HID5, "HID5",
6110 SPR_NOACCESS, SPR_NOACCESS,
6111 &spr_read_generic, &spr_write_generic,
417bf010 6112 POWERPC970_HID5_INIT);
bd928eba
JM		 6113 /* XXX : not implemented */
6114 spr_register(env, SPR_L2CR, "L2CR",
6115 SPR_NOACCESS, SPR_NOACCESS,
6116 &spr_read_generic, &spr_write_generic,
6117 0x00000000);
a750fc0b
JM		 6118 /* Memory management */
6119 /* XXX: not correct */
6120 gen_low_BATs(env);
12de9a39
JM		 6121 /* XXX : not implemented */
6122 spr_register(env, SPR_MMUCFG, "MMUCFG",
6123 SPR_NOACCESS, SPR_NOACCESS,
6124 &spr_read_generic, SPR_NOACCESS,
6125 0x00000000); /* TOFIX */
6126 /* XXX : not implemented */
6127 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6128 SPR_NOACCESS, SPR_NOACCESS,
6129 &spr_read_generic, &spr_write_generic,
6130 0x00000000); /* TOFIX */
6131 spr_register(env, SPR_HIOR, "SPR_HIOR",
6132 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6133 &spr_read_hior, &spr_write_hior,
6134 0x00000000);
f2e63a42 6135#if !defined(CONFIG_USER_ONLY)
12de9a39 6136 env->slb_nr = 32;
f2e63a42 6137#endif
e1833e1f 6138 init_excp_970(env);
d63001d1
JM		 6139 env->dcache_line_size = 128;
6140 env->icache_line_size = 128;
a750fc0b
JM		 6141 /* Allocate hardware IRQ controller */
6142 ppc970_irq_init(env);
cf8358c8
AJ		 6143 /* Can't find information on what this should be on reset. This
6144 * value is the one used by 74xx processors. */
6145 vscr_init(env, 0x00010000);
a750fc0b 6146}
a750fc0b 6147
2f462816 6148/* PowerPC 970 MP */
082c6681
JM		 6149#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6151 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6152 PPC_FLOAT_STFIWX | \
6153 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6154 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6155 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6156 PPC_64B | PPC_ALTIVEC | \
6157 PPC_SEGMENT_64B | PPC_SLBI)
6158#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6159#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6160#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6161#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6162#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6163#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6164 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6165 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6166
6167static int check_pow_970MP (CPUPPCState *env)
6168{
6169 if (env->spr[SPR_HID0] & 0x01C00000)
6170 return 1;
6171
6172 return 0;
6173}
6174
6175static void init_proc_970MP (CPUPPCState *env)
6176{
6177 gen_spr_ne_601(env);
6178 gen_spr_7xx(env);
6179 /* Time base */
6180 gen_tbl(env);
6181 /* Hardware implementation registers */
6182 /* XXX : not implemented */
6183 spr_register(env, SPR_HID0, "HID0",
6184 SPR_NOACCESS, SPR_NOACCESS,
6185 &spr_read_generic, &spr_write_clear,
6186 0x60000000);
6187 /* XXX : not implemented */
6188 spr_register(env, SPR_HID1, "HID1",
6189 SPR_NOACCESS, SPR_NOACCESS,
6190 &spr_read_generic, &spr_write_generic,
6191 0x00000000);
6192 /* XXX : not implemented */
bd928eba 6193 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6194 SPR_NOACCESS, SPR_NOACCESS,
6195 &spr_read_generic, &spr_write_generic,
6196 0x00000000);
6197 /* XXX : not implemented */
6198 spr_register(env, SPR_970_HID5, "HID5",
6199 SPR_NOACCESS, SPR_NOACCESS,
6200 &spr_read_generic, &spr_write_generic,
6201 POWERPC970_HID5_INIT);
bd928eba
JM		 6202 /* XXX : not implemented */
6203 spr_register(env, SPR_L2CR, "L2CR",
6204 SPR_NOACCESS, SPR_NOACCESS,
6205 &spr_read_generic, &spr_write_generic,
6206 0x00000000);
2f462816
JM		 6207 /* Memory management */
6208 /* XXX: not correct */
6209 gen_low_BATs(env);
6210 /* XXX : not implemented */
6211 spr_register(env, SPR_MMUCFG, "MMUCFG",
6212 SPR_NOACCESS, SPR_NOACCESS,
6213 &spr_read_generic, SPR_NOACCESS,
6214 0x00000000); /* TOFIX */
6215 /* XXX : not implemented */
6216 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6217 SPR_NOACCESS, SPR_NOACCESS,
6218 &spr_read_generic, &spr_write_generic,
6219 0x00000000); /* TOFIX */
6220 spr_register(env, SPR_HIOR, "SPR_HIOR",
6221 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6222 &spr_read_hior, &spr_write_hior,
6223 0x00000000);
2f462816
JM		 6224#if !defined(CONFIG_USER_ONLY)
6225 env->slb_nr = 32;
6226#endif
6227 init_excp_970(env);
6228 env->dcache_line_size = 128;
6229 env->icache_line_size = 128;
6230 /* Allocate hardware IRQ controller */
6231 ppc970_irq_init(env);
cf8358c8
AJ		 6232 /* Can't find information on what this should be on reset. This
6233 * value is the one used by 74xx processors. */
6234 vscr_init(env, 0x00010000);
2f462816
JM		 6235}
6236
a750fc0b 6237/* PowerPC 620 */
082c6681
JM		 6238#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6239 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6240 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6241 PPC_FLOAT_STFIWX | \
6242 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6243 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6244 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6245 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6246 PPC_64B | PPC_SLBI)
add78955
JM		 6247#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6248//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6249#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6250#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6251#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6252#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6253 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6254#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6255
578bb252 6256__attribute__ (( unused ))
a750fc0b
JM		 6257static void init_proc_620 (CPUPPCState *env)
6258{
6259 gen_spr_ne_601(env);
6260 gen_spr_620(env);
6261 /* Time base */
6262 gen_tbl(env);
6263 /* Hardware implementation registers */
6264 /* XXX : not implemented */
6265 spr_register(env, SPR_HID0, "HID0",
6266 SPR_NOACCESS, SPR_NOACCESS,
6267 &spr_read_generic, &spr_write_generic,
6268 0x00000000);
6269 /* Memory management */
6270 gen_low_BATs(env);
e1833e1f 6271 init_excp_620(env);
d63001d1
JM		 6272 env->dcache_line_size = 64;
6273 env->icache_line_size = 64;
faadf50e
JM		 6274 /* Allocate hardware IRQ controller */
6275 ppc6xx_irq_init(env);
a750fc0b 6276}
a750fc0b
JM		 6277#endif /* defined (TARGET_PPC64) */
6278
6279/* Default 32 bits PowerPC target will be 604 */
6280#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6281#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6282#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6283#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6284#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6285#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6286#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6287#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6288#define check_pow_PPC32 check_pow_604
6289#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6290
6291/* Default 64 bits PowerPC target will be 970 FX */
6292#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6293#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6294#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6295#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6296#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6297#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6298#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6299#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6300#define check_pow_PPC64 check_pow_970FX
6301#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6302
6303/* Default PowerPC target will be PowerPC 32 */
6304#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 6305#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6306#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6307#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6308#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6309#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6310#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 6311#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 6312#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 6313#define check_pow_DEFAULT check_pow_PPC64
6314#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6315#else
d12f4c38
JM		 6316#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6317#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6318#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6319#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6320#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6321#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 6322#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 6323#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 6324#define check_pow_DEFAULT check_pow_PPC32
6325#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6326#endif
6327
6328/*****************************************************************************/
6329/* PVR definitions for most known PowerPC */
6330enum {
6331 /* PowerPC 401 family */
6332 /* Generic PowerPC 401 */
80d11f44 6333#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6334 /* PowerPC 401 cores */
80d11f44
JM		 6335 CPU_POWERPC_401A1 = 0x00210000,
6336 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6337#if 0
80d11f44 6338 CPU_POWERPC_401B3 = xxx,
a750fc0b 6339#endif
80d11f44
JM		 6340 CPU_POWERPC_401C2 = 0x00230000,
6341 CPU_POWERPC_401D2 = 0x00240000,
6342 CPU_POWERPC_401E2 = 0x00250000,
6343 CPU_POWERPC_401F2 = 0x00260000,
6344 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6345 /* PowerPC 401 microcontrolers */
6346#if 0
80d11f44 6347 CPU_POWERPC_401GF = xxx,
a750fc0b 6348#endif
80d11f44 6349#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6350 /* IBM Processor for Network Resources */
80d11f44 6351 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6352#if 0
80d11f44 6353 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6354#endif
6355 /* PowerPC 403 family */
6356 /* Generic PowerPC 403 */
80d11f44 6357#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6358 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6359 CPU_POWERPC_403GA = 0x00200011,
6360 CPU_POWERPC_403GB = 0x00200100,
6361 CPU_POWERPC_403GC = 0x00200200,
6362 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6363#if 0
80d11f44 6364 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6365#endif
6366 /* PowerPC 405 family */
6367 /* Generic PowerPC 405 */
80d11f44 6368#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6369 /* PowerPC 405 cores */
6370#if 0
80d11f44 6371 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6372#endif
6373#if 0
80d11f44 6374 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6375#endif
6376#if 0
80d11f44 6377 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6378#endif
6379#if 0
80d11f44 6380 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6381#endif
6382#if 0
80d11f44 6383 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6384#endif
6385#if 0
80d11f44 6386 CPU_POWERPC_405C4 = xxx,
a750fc0b 6387#endif
80d11f44 6388 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6389#if 0
80d11f44 6390 CPU_POWERPC_405D3 = xxx,
a750fc0b 6391#endif
80d11f44 6392 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6393#if 0
80d11f44 6394 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6395#endif
6396#if 0
80d11f44 6397 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6398#endif
6399#if 0
80d11f44 6400 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6401#endif
6402#if 0
80d11f44 6403 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6404#endif
6405#if 0
80d11f44 6406 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6407#endif
6408 /* PowerPC 405 microcontrolers */
6409 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6410#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6411 CPU_POWERPC_405CRa = 0x40110041,
6412 CPU_POWERPC_405CRb = 0x401100C5,
6413 CPU_POWERPC_405CRc = 0x40110145,
6414 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6415#if 0
80d11f44 6416 CPU_POWERPC_405EXr = xxx,
a750fc0b 6417#endif
80d11f44 6418 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6419#if 0
80d11f44
JM		 6420 CPU_POWERPC_405FX = xxx,
6421#endif
6422#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6423 CPU_POWERPC_405GPa = 0x40110000,
6424 CPU_POWERPC_405GPb = 0x40110040,
6425 CPU_POWERPC_405GPc = 0x40110082,
6426 CPU_POWERPC_405GPd = 0x401100C4,
6427#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6428 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6429#if 0
80d11f44 6430 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6431#endif
6432#if 0
80d11f44 6433 CPU_POWERPC_405L = xxx,
a750fc0b 6434#endif
80d11f44 6435 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6436#if 0
80d11f44 6437 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6438#endif
6439#if 0
80d11f44 6440 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6441#endif
6442#if 0
80d11f44 6443 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6444#endif
6445 /* IBM network processors */
80d11f44
JM		 6446 CPU_POWERPC_NPE405H = 0x414100C0,
6447 CPU_POWERPC_NPE405H2 = 0x41410140,
6448 CPU_POWERPC_NPE405L = 0x416100C0,
6449 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6450#if 0
80d11f44 6451 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6452#endif
6453#if 0
80d11f44 6454 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6455#endif
6456#if 0
80d11f44 6457 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6458#endif
6459 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6460#if 0
80d11f44 6461 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6462#endif
6463#if 0
80d11f44 6464 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6465#endif
6466#if 0
80d11f44 6467 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6468#endif
80d11f44 6469 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6470#if 0
80d11f44 6471 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6472#endif
6473#if 0
80d11f44 6474 CPU_POWERPC_STB045 = xxx,
a750fc0b 6475#endif
80d11f44
JM		 6476 CPU_POWERPC_STB04 = 0x41810000,
6477 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6478#if 0
80d11f44 6479 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6480#endif
6481 /* Xilinx cores */
80d11f44
JM		 6482 CPU_POWERPC_X2VP4 = 0x20010820,
6483#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6484 CPU_POWERPC_X2VP20 = 0x20010860,
6485#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6486#if 0
80d11f44 6487 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6488#endif
6489#if 0
80d11f44 6490 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6491#endif
6492#if 0
80d11f44 6493 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6494#endif
6495#if 0
80d11f44 6496 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6497#endif
6498 /* PowerPC 440 family */
6499 /* Generic PowerPC 440 */
80d11f44 6500#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6501 /* PowerPC 440 cores */
6502#if 0
80d11f44 6503 CPU_POWERPC_440A4 = xxx,
a750fc0b
JM		 6504#endif
6505#if 0
80d11f44 6506 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6507#endif
6508#if 0
80d11f44 6509 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6510#endif
6511#if 0
80d11f44 6512 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6513#endif
6514#if 0
80d11f44 6515 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6516#endif
6517#if 0
80d11f44 6518 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6519#endif
6520#if 0
80d11f44 6521 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6522#endif
6523 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6524#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6525 CPU_POWERPC_440EPa = 0x42221850,
6526 CPU_POWERPC_440EPb = 0x422218D3,
6527#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6528 CPU_POWERPC_440GPb = 0x40120440,
6529 CPU_POWERPC_440GPc = 0x40120481,
6530#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6531#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6532 CPU_POWERPC_440GRX = 0x200008D0,
6533#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6534#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6535 CPU_POWERPC_440GXa = 0x51B21850,
6536 CPU_POWERPC_440GXb = 0x51B21851,
6537 CPU_POWERPC_440GXc = 0x51B21892,
6538 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6539#if 0
80d11f44 6540 CPU_POWERPC_440S = xxx,
a750fc0b 6541#endif
80d11f44
JM		 6542 CPU_POWERPC_440SP = 0x53221850,
6543 CPU_POWERPC_440SP2 = 0x53221891,
6544 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6545 /* PowerPC 460 family */
6546#if 0
6547 /* Generic PowerPC 464 */
80d11f44 6548#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6549#endif
6550 /* PowerPC 464 microcontrolers */
6551#if 0
80d11f44 6552 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6553#endif
6554#if 0
80d11f44 6555 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6556#endif
6557 /* Freescale embedded PowerPC cores */
c3e36823 6558 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6559 CPU_POWERPC_MPC5xx = 0x00020020,
6560#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6561#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6562#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6563#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6564#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6565#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6566#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6567#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6568#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6569#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6570#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6571#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6572#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6573 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6574 CPU_POWERPC_MPC8xx = 0x00500000,
6575#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6576#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6577#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6578#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6579#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6580#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6581#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6582#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6583#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6584#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6585#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6586#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6587#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6588#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6589#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6590 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6591 CPU_POWERPC_G2 = 0x00810011,
6592 CPU_POWERPC_G2H4 = 0x80811010,
6593 CPU_POWERPC_G2gp = 0x80821010,
6594 CPU_POWERPC_G2ls = 0x90810010,
6595 CPU_POWERPC_MPC603 = 0x00810100,
6596 CPU_POWERPC_G2_HIP3 = 0x00810101,
6597 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6598 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6599 CPU_POWERPC_G2LE = 0x80820010,
6600 CPU_POWERPC_G2LEgp = 0x80822010,
6601 CPU_POWERPC_G2LEls = 0xA0822010,
6602 CPU_POWERPC_G2LEgp1 = 0x80822011,
6603 CPU_POWERPC_G2LEgp3 = 0x80822013,
6604 /* MPC52xx microcontrollers */
c3e36823 6605 /* XXX: MPC 5121 ? */
80d11f44
JM		 6606#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6607#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6608#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6609#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6610#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6611#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6612#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6613#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6614 /* MPC82xx microcontrollers */
6615#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6616#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6617#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6618#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6619#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6620#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6621#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6622#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6623#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6624#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6625#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6626#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6627#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6628#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6629#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6630#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6631#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6632#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6633#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6634#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6635#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6636#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6637#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6638#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6639#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6640#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6641#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6642#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6643#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6644 /* e200 family */
80d11f44
JM		 6645 /* e200 cores */
6646#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6647#if 0
80d11f44 6648 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6649#endif
6650#if 0
80d11f44 6651 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6652#endif
6653#if 0 /* ? */
80d11f44
JM		 6654 CPU_POWERPC_e200z3 = 0x81120000,
6655#endif
6656 CPU_POWERPC_e200z5 = 0x81000000,
6657 CPU_POWERPC_e200z6 = 0x81120000,
6658 /* MPC55xx microcontrollers */
6659#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6660#if 0
6661#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6662#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6663#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6664#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6665#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6666#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6667#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6668#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6669#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6670#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6671#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6672#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6673#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6674#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6675#endif
6676#if 0
6677#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6678#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6679#endif
6680#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6681#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6682#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6683#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6684#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6685#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 6686 /* e300 family */
80d11f44
JM		 6687 /* e300 cores */
6688#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6689 CPU_POWERPC_e300c1 = 0x00830010,
6690 CPU_POWERPC_e300c2 = 0x00840010,
6691 CPU_POWERPC_e300c3 = 0x00850010,
6692 CPU_POWERPC_e300c4 = 0x00860010,
6693 /* MPC83xx microcontrollers */
6694#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
6695#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
6696#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
6697#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
6698#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
6699#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
6700#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
6701#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
6702#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
6703#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
6704#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
6705#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
6706#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
6707#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
6708#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
6709#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
6710#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
6711#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
6712#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
6713#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
6714#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
6715#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
6716#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
6717#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
6718#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
6719#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
6720#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
6721#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
6722#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6723#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
a750fc0b 6724 /* e500 family */
80d11f44
JM		 6725 /* e500 cores */
6726#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 6727#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 6728#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 6729 CPU_POWERPC_e500v1_v10 = 0x80200010,
6730 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 6731 CPU_POWERPC_e500v2_v10 = 0x80210010,
6732 CPU_POWERPC_e500v2_v11 = 0x80210011,
6733 CPU_POWERPC_e500v2_v20 = 0x80210020,
6734 CPU_POWERPC_e500v2_v21 = 0x80210021,
6735 CPU_POWERPC_e500v2_v22 = 0x80210022,
6736 CPU_POWERPC_e500v2_v30 = 0x80210030,
6737 /* MPC85xx microcontrollers */
6738#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6739#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6740#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6741#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6742#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6743#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6744#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 6745#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
6746#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
6747#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 6748#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 6749#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
6750#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 6751#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 6752#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
6753#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 6754#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6755#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6756#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6757#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6758#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6759#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6760#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6761#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6762#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6763#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6764#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6765#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6766#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6767#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6768#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6769#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6770#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6771#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6772#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6773#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6774#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6775#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6776#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6777#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6778#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6779#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6780#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6781#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6782#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6783#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6784#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6785#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6786#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6787#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6788#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6789#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6790#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6791#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6792#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6793#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6794#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6795#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6796#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6797#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6798#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6799#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6800#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6801#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6802#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6803#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6804#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6805#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6806#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6807#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 6808 /* e600 family */
80d11f44
JM		 6809 /* e600 cores */
6810 CPU_POWERPC_e600 = 0x80040010,
6811 /* MPC86xx microcontrollers */
6812#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6813#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6814#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 6815 /* PowerPC 6xx cores */
80d11f44
JM		 6816#define CPU_POWERPC_601 CPU_POWERPC_601_v2
6817 CPU_POWERPC_601_v0 = 0x00010001,
6818 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 6819#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 6820 CPU_POWERPC_601_v2 = 0x00010002,
6821 CPU_POWERPC_602 = 0x00050100,
6822 CPU_POWERPC_603 = 0x00030100,
6823#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6824 CPU_POWERPC_603E_v11 = 0x00060101,
6825 CPU_POWERPC_603E_v12 = 0x00060102,
6826 CPU_POWERPC_603E_v13 = 0x00060103,
6827 CPU_POWERPC_603E_v14 = 0x00060104,
6828 CPU_POWERPC_603E_v22 = 0x00060202,
6829 CPU_POWERPC_603E_v3 = 0x00060300,
6830 CPU_POWERPC_603E_v4 = 0x00060400,
6831 CPU_POWERPC_603E_v41 = 0x00060401,
6832 CPU_POWERPC_603E7t = 0x00071201,
6833 CPU_POWERPC_603E7v = 0x00070100,
6834 CPU_POWERPC_603E7v1 = 0x00070101,
6835 CPU_POWERPC_603E7v2 = 0x00070201,
6836 CPU_POWERPC_603E7 = 0x00070200,
6837 CPU_POWERPC_603P = 0x00070000,
6838#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 6839 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 6840 CPU_POWERPC_604 = 0x00040103,
6841#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 6842 /* XXX: missing 0x00091203 */
6843 /* XXX: missing 0x00092110 */
6844 /* XXX: missing 0x00092120 */
80d11f44
JM		 6845 CPU_POWERPC_604E_v10 = 0x00090100,
6846 CPU_POWERPC_604E_v22 = 0x00090202,
6847 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 6848 /* XXX: missing 0x000a0100 */
6849 /* XXX: missing 0x00093102 */
80d11f44 6850 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 6851#if 0
80d11f44 6852 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 6853#endif
6854 /* PowerPC 740/750 cores (aka G3) */
6855 /* XXX: missing 0x00084202 */
80d11f44 6856#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 6857 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 6858 CPU_POWERPC_7x0_v20 = 0x00080200,
6859 CPU_POWERPC_7x0_v21 = 0x00080201,
6860 CPU_POWERPC_7x0_v22 = 0x00080202,
6861 CPU_POWERPC_7x0_v30 = 0x00080300,
6862 CPU_POWERPC_7x0_v31 = 0x00080301,
6863 CPU_POWERPC_740E = 0x00080100,
bd928eba 6864 CPU_POWERPC_750E = 0x00080200,
80d11f44 6865 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 6866 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 6867#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6868 CPU_POWERPC_750CL_v10 = 0x00087200,
6869 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 6870#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 6871 CPU_POWERPC_750CX_v10 = 0x00082100,
6872 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 6873 CPU_POWERPC_750CX_v21 = 0x00082201,
6874 CPU_POWERPC_750CX_v22 = 0x00082202,
6875#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6876 CPU_POWERPC_750CXE_v21 = 0x00082211,
6877 CPU_POWERPC_750CXE_v22 = 0x00082212,
6878 CPU_POWERPC_750CXE_v23 = 0x00082213,
6879 CPU_POWERPC_750CXE_v24 = 0x00082214,
6880 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 6881 CPU_POWERPC_750CXE_v30 = 0x00082310,
6882 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 6883 CPU_POWERPC_750CXE_v31b = 0x00083311,
6884 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 6885 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 6886#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6887 CPU_POWERPC_750FX_v10 = 0x70000100,
6888 CPU_POWERPC_750FX_v20 = 0x70000200,
6889 CPU_POWERPC_750FX_v21 = 0x70000201,
6890 CPU_POWERPC_750FX_v22 = 0x70000202,
6891 CPU_POWERPC_750FX_v23 = 0x70000203,
6892 CPU_POWERPC_750GL = 0x70020102,
6893#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6894 CPU_POWERPC_750GX_v10 = 0x70020100,
6895 CPU_POWERPC_750GX_v11 = 0x70020101,
6896 CPU_POWERPC_750GX_v12 = 0x70020102,
6897#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 6898 CPU_POWERPC_750L_v20 = 0x00088200,
6899 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 6900 CPU_POWERPC_750L_v22 = 0x00088202,
6901 CPU_POWERPC_750L_v30 = 0x00088300,
6902 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 6903 /* PowerPC 745/755 cores */
80d11f44
JM		 6904#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6905 CPU_POWERPC_7x5_v10 = 0x00083100,
6906 CPU_POWERPC_7x5_v11 = 0x00083101,
6907 CPU_POWERPC_7x5_v20 = 0x00083200,
6908 CPU_POWERPC_7x5_v21 = 0x00083201,
6909 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6910 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6911 CPU_POWERPC_7x5_v24 = 0x00083204,
6912 CPU_POWERPC_7x5_v25 = 0x00083205,
6913 CPU_POWERPC_7x5_v26 = 0x00083206,
6914 CPU_POWERPC_7x5_v27 = 0x00083207,
6915 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 6916#if 0
80d11f44 6917 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 6918#endif
6919 /* PowerPC 74xx cores (aka G4) */
6920 /* XXX: missing 0x000C1101 */
80d11f44
JM		 6921#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6922 CPU_POWERPC_7400_v10 = 0x000C0100,
6923 CPU_POWERPC_7400_v11 = 0x000C0101,
6924 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 6925 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 6926 CPU_POWERPC_7400_v22 = 0x000C0202,
6927 CPU_POWERPC_7400_v26 = 0x000C0206,
6928 CPU_POWERPC_7400_v27 = 0x000C0207,
6929 CPU_POWERPC_7400_v28 = 0x000C0208,
6930 CPU_POWERPC_7400_v29 = 0x000C0209,
6931#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6932 CPU_POWERPC_7410_v10 = 0x800C1100,
6933 CPU_POWERPC_7410_v11 = 0x800C1101,
6934 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6935 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6936 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6937#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6938 CPU_POWERPC_7448_v10 = 0x80040100,
6939 CPU_POWERPC_7448_v11 = 0x80040101,
6940 CPU_POWERPC_7448_v20 = 0x80040200,
6941 CPU_POWERPC_7448_v21 = 0x80040201,
6942#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6943 CPU_POWERPC_7450_v10 = 0x80000100,
6944 CPU_POWERPC_7450_v11 = 0x80000101,
6945 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 6946 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 6947 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 6948#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
6949 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
6950 /* XXX: this entry might be a bug in some documentation */
6951 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 6952#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6953 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 6954 /* XXX: missing 0x80010200 */
80d11f44
JM		 6955 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6956 CPU_POWERPC_74x5_v32 = 0x80010302,
6957 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6958 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6959#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 6960 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 6961 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 6962 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 6963#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6964 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6965 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6966 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 6967 /* 64 bits PowerPC */
00af685f 6968#if defined(TARGET_PPC64)
80d11f44
JM		 6969 CPU_POWERPC_620 = 0x00140000,
6970 CPU_POWERPC_630 = 0x00400000,
6971 CPU_POWERPC_631 = 0x00410104,
6972 CPU_POWERPC_POWER4 = 0x00350000,
6973 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 6974 /* XXX: missing 0x003A0201 */
80d11f44
JM		 6975 CPU_POWERPC_POWER5 = 0x003A0203,
6976#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6977 CPU_POWERPC_POWER5P = 0x003B0000,
6978#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6979 CPU_POWERPC_POWER6 = 0x003E0000,
6980 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6981 CPU_POWERPC_POWER6A = 0x0F000002,
6982 CPU_POWERPC_970 = 0x00390202,
6983#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6984 CPU_POWERPC_970FX_v10 = 0x00391100,
6985 CPU_POWERPC_970FX_v20 = 0x003C0200,
6986 CPU_POWERPC_970FX_v21 = 0x003C0201,
6987 CPU_POWERPC_970FX_v30 = 0x003C0300,
6988 CPU_POWERPC_970FX_v31 = 0x003C0301,
6989 CPU_POWERPC_970GX = 0x00450000,
6990#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6991 CPU_POWERPC_970MP_v10 = 0x00440100,
6992 CPU_POWERPC_970MP_v11 = 0x00440101,
6993#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6994 CPU_POWERPC_CELL_v10 = 0x00700100,
6995 CPU_POWERPC_CELL_v20 = 0x00700400,
6996 CPU_POWERPC_CELL_v30 = 0x00700500,
6997 CPU_POWERPC_CELL_v31 = 0x00700501,
6998#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
6999 CPU_POWERPC_RS64 = 0x00330000,
7000 CPU_POWERPC_RS64II = 0x00340000,
7001 CPU_POWERPC_RS64III = 0x00360000,
7002 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7003#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7004 /* Original POWER */
7005 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7006 * POWER2 (RIOS2) & RSC2 (P2SC) here
7007 */
7008#if 0
80d11f44 7009 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7010#endif
7011#if 0
80d11f44 7012 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7013#endif
7014 /* PA Semi core */
80d11f44 7015 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7016};
7017
7018/* System version register (used on MPC 8xxx) */
7019enum {
80d11f44
JM		 7020 POWERPC_SVR_NONE = 0x00000000,
7021#define POWERPC_SVR_52xx POWERPC_SVR_5200
7022#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7023 POWERPC_SVR_5200_v10 = 0x80110010,
7024 POWERPC_SVR_5200_v11 = 0x80110011,
7025 POWERPC_SVR_5200_v12 = 0x80110012,
7026#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7027 POWERPC_SVR_5200B_v20 = 0x80110020,
7028 POWERPC_SVR_5200B_v21 = 0x80110021,
7029#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7030#if 0
80d11f44 7031 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7032#endif
7033#if 0
80d11f44 7034 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7035#endif
7036#if 0
80d11f44 7037 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7038#endif
7039#if 0
80d11f44 7040 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7041#endif
7042#if 0
80d11f44 7043 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7044#endif
7045#if 0
80d11f44 7046 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7047#endif
7048#if 0
80d11f44 7049 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7050#endif
7051#if 0
80d11f44 7052 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7053#endif
7054#if 0
80d11f44 7055 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7056#endif
7057#if 0
80d11f44 7058 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7059#endif
7060#if 0
80d11f44 7061 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7062#endif
7063#if 0
80d11f44 7064 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7065#endif
7066#if 0
80d11f44 7067 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7068#endif
7069#if 0
80d11f44 7070 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7071#endif
7072#if 0
80d11f44 7073 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7074#endif
7075#if 0
80d11f44 7076 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7077#endif
7078#if 0
80d11f44 7079 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7080#endif
7081#if 0
80d11f44
JM		 7082 POWERPC_SVR_8323E = xxx,
7083#endif
7084 POWERPC_SVR_8343A = 0x80570030,
7085 POWERPC_SVR_8343EA = 0x80560030,
7086#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7087 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7088 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7089#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7090 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7091 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7092 POWERPC_SVR_8349 = 0x80510010,
7093 POWERPC_SVR_8349A = 0x80510030,
7094 POWERPC_SVR_8349E = 0x80500010,
7095 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7096#if 0
80d11f44 7097 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7098#endif
7099#if 0
80d11f44
JM		 7100 POWERPC_SVR_8360E = xxx,
7101#endif
7102#define POWERPC_SVR_E500 0x40000000
7103 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7104 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7105 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7106 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7107 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7108 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7109#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7110 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7111 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7112#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7113 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7114 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7115#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7116 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7117 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7118 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7119#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7120 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7121 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7122#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7123 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7124 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7125#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7126 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7127 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7128 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7129 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7130#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7131 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7132 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7133 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7134 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7135#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7136 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7137 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7138#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7139 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7140 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7141#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7142 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7143 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7144#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7145 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7146 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7147#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7148 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7149 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7150#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7151 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7152 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7153 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7154 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7155#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7156 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7157 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7158 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7159 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7160#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7161 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7162 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7163#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7164 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7165 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7166#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7167 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7168 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7169 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7170 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7171 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7172 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7173 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7174 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7175 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7176#if 0
80d11f44 7177 POWERPC_SVR_8610 = xxx,
c3e36823 7178#endif
80d11f44
JM		 7179 POWERPC_SVR_8641 = 0x80900021,
7180 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7181};
7182
3fc6c082 7183/*****************************************************************************/
a750fc0b 7184/* PowerPC CPU definitions */
80d11f44 7185#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 7186 { \
7187 .name = _name, \
7188 .pvr = _pvr, \
80d11f44 7189 .svr = _svr, \
a750fc0b
JM		 7190 .insns_flags = glue(POWERPC_INSNS_,_type), \
7191 .msr_mask = glue(POWERPC_MSRM_,_type), \
7192 .mmu_model = glue(POWERPC_MMU_,_type), \
7193 .excp_model = glue(POWERPC_EXCP_,_type), \
7194 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 7195 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 7196 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 7197 .init_proc = &glue(init_proc_,_type), \
2f462816 7198 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7199 }
80d11f44
JM		 7200#define POWERPC_DEF(_name, _pvr, _type) \
7201POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7202
ee4e83ed 7203static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7204 /* Embedded PowerPC */
7205 /* PowerPC 401 family */
2662a059 7206 /* Generic PowerPC 401 */
80d11f44 7207 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7208 /* PowerPC 401 cores */
2662a059 7209 /* PowerPC 401A1 */
80d11f44 7210 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7211 /* PowerPC 401B2 */
80d11f44 7212 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7213#if defined (TODO)
a750fc0b 7214 /* PowerPC 401B3 */
80d11f44 7215 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7216#endif
7217 /* PowerPC 401C2 */
80d11f44 7218 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7219 /* PowerPC 401D2 */
80d11f44 7220 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7221 /* PowerPC 401E2 */
80d11f44 7222 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7223 /* PowerPC 401F2 */
80d11f44 7224 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7225 /* PowerPC 401G2 */
7226 /* XXX: to be checked */
80d11f44 7227 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7228 /* PowerPC 401 microcontrolers */
2662a059 7229#if defined (TODO)
a750fc0b 7230 /* PowerPC 401GF */
80d11f44 7231 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7232#endif
a750fc0b 7233 /* IOP480 (401 microcontroler) */
80d11f44 7234 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7235 /* IBM Processor for Network Resources */
80d11f44 7236 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7237#if defined (TODO)
80d11f44 7238 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7239#endif
a750fc0b
JM		 7240 /* PowerPC 403 family */
7241 /* Generic PowerPC 403 */
80d11f44 7242 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7243 /* PowerPC 403 microcontrolers */
7244 /* PowerPC 403 GA */
80d11f44 7245 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7246 /* PowerPC 403 GB */
80d11f44 7247 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7248 /* PowerPC 403 GC */
80d11f44 7249 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7250 /* PowerPC 403 GCX */
80d11f44 7251 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7252#if defined (TODO)
a750fc0b 7253 /* PowerPC 403 GP */
80d11f44 7254 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7255#endif
a750fc0b
JM		 7256 /* PowerPC 405 family */
7257 /* Generic PowerPC 405 */
80d11f44 7258 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7259 /* PowerPC 405 cores */
2662a059 7260#if defined (TODO)
a750fc0b 7261 /* PowerPC 405 A3 */
80d11f44 7262 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7263#endif
3a607854 7264#if defined (TODO)
a750fc0b 7265 /* PowerPC 405 A4 */
80d11f44 7266 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7267#endif
3a607854 7268#if defined (TODO)
a750fc0b 7269 /* PowerPC 405 B3 */
80d11f44 7270 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7271#endif
7272#if defined (TODO)
a750fc0b 7273 /* PowerPC 405 B4 */
80d11f44 7274 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7275#endif
7276#if defined (TODO)
7277 /* PowerPC 405 C3 */
80d11f44 7278 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7279#endif
7280#if defined (TODO)
7281 /* PowerPC 405 C4 */
80d11f44 7282 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7283#endif
7284 /* PowerPC 405 D2 */
80d11f44 7285 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7286#if defined (TODO)
7287 /* PowerPC 405 D3 */
80d11f44 7288 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7289#endif
7290 /* PowerPC 405 D4 */
80d11f44 7291 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7292#if defined (TODO)
7293 /* PowerPC 405 D5 */
80d11f44 7294 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7295#endif
7296#if defined (TODO)
7297 /* PowerPC 405 E4 */
80d11f44 7298 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7299#endif
7300#if defined (TODO)
7301 /* PowerPC 405 F4 */
80d11f44 7302 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7303#endif
7304#if defined (TODO)
7305 /* PowerPC 405 F5 */
80d11f44 7306 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7307#endif
7308#if defined (TODO)
7309 /* PowerPC 405 F6 */
80d11f44 7310 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7311#endif
7312 /* PowerPC 405 microcontrolers */
7313 /* PowerPC 405 CR */
80d11f44 7314 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7315 /* PowerPC 405 CRa */
80d11f44 7316 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7317 /* PowerPC 405 CRb */
80d11f44 7318 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7319 /* PowerPC 405 CRc */
80d11f44 7320 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7321 /* PowerPC 405 EP */
80d11f44 7322 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7323#if defined(TODO)
7324 /* PowerPC 405 EXr */
80d11f44 7325 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7326#endif
7327 /* PowerPC 405 EZ */
80d11f44 7328 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7329#if defined(TODO)
7330 /* PowerPC 405 FX */
80d11f44 7331 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7332#endif
7333 /* PowerPC 405 GP */
80d11f44 7334 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7335 /* PowerPC 405 GPa */
80d11f44 7336 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7337 /* PowerPC 405 GPb */
80d11f44 7338 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7339 /* PowerPC 405 GPc */
80d11f44 7340 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7341 /* PowerPC 405 GPd */
80d11f44 7342 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7343 /* PowerPC 405 GPe */
80d11f44 7344 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7345 /* PowerPC 405 GPR */
80d11f44 7346 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7347#if defined(TODO)
7348 /* PowerPC 405 H */
80d11f44 7349 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7350#endif
7351#if defined(TODO)
7352 /* PowerPC 405 L */
80d11f44 7353 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7354#endif
7355 /* PowerPC 405 LP */
80d11f44 7356 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7357#if defined(TODO)
7358 /* PowerPC 405 PM */
80d11f44 7359 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7360#endif
7361#if defined(TODO)
7362 /* PowerPC 405 PS */
80d11f44 7363 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7364#endif
7365#if defined(TODO)
7366 /* PowerPC 405 S */
80d11f44 7367 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7368#endif
7369 /* Npe405 H */
80d11f44 7370 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7371 /* Npe405 H2 */
80d11f44 7372 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7373 /* Npe405 L */
80d11f44 7374 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7375 /* Npe4GS3 */
80d11f44 7376 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7377#if defined (TODO)
80d11f44 7378 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7379#endif
7380#if defined (TODO)
80d11f44 7381 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7382#endif
7383#if defined (TODO)
7384 /* PowerPC LC77700 (Sanyo) */
80d11f44 7385 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7386#endif
7387 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7388#if defined (TODO)
7389 /* STB010000 */
80d11f44 7390 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7391#endif
7392#if defined (TODO)
7393 /* STB01010 */
80d11f44 7394 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7395#endif
7396#if defined (TODO)
7397 /* STB0210 */
80d11f44 7398 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7399#endif
7400 /* STB03xx */
80d11f44 7401 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7402#if defined (TODO)
7403 /* STB043x */
80d11f44 7404 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7405#endif
7406#if defined (TODO)
7407 /* STB045x */
80d11f44 7408 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7409#endif
7410 /* STB04xx */
80d11f44 7411 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7412 /* STB25xx */
80d11f44 7413 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7414#if defined (TODO)
7415 /* STB130 */
80d11f44 7416 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7417#endif
7418 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7419 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7420 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7421 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7422 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7423#if defined (TODO)
7424 /* Zarlink ZL10310 */
80d11f44 7425 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7426#endif
7427#if defined (TODO)
7428 /* Zarlink ZL10311 */
80d11f44 7429 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7430#endif
7431#if defined (TODO)
7432 /* Zarlink ZL10320 */
80d11f44 7433 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7434#endif
7435#if defined (TODO)
7436 /* Zarlink ZL10321 */
80d11f44 7437 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7438#endif
7439 /* PowerPC 440 family */
80d11f44 7440#if defined(TODO_USER_ONLY)
a750fc0b 7441 /* Generic PowerPC 440 */
80d11f44
JM		 7442 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7443#endif
a750fc0b
JM		 7444 /* PowerPC 440 cores */
7445#if defined (TODO)
7446 /* PowerPC 440 A4 */
80d11f44 7447 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b
JM		 7448#endif
7449#if defined (TODO)
7450 /* PowerPC 440 A5 */
80d11f44 7451 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7452#endif
7453#if defined (TODO)
7454 /* PowerPC 440 B4 */
80d11f44 7455 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7456#endif
7457#if defined (TODO)
7458 /* PowerPC 440 G4 */
80d11f44 7459 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7460#endif
7461#if defined (TODO)
7462 /* PowerPC 440 F5 */
80d11f44 7463 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7464#endif
7465#if defined (TODO)
7466 /* PowerPC 440 G5 */
80d11f44 7467 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7468#endif
7469#if defined (TODO)
7470 /* PowerPC 440H4 */
80d11f44 7471 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7472#endif
7473#if defined (TODO)
7474 /* PowerPC 440H6 */
80d11f44 7475 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7476#endif
7477 /* PowerPC 440 microcontrolers */
80d11f44 7478#if defined(TODO_USER_ONLY)
a750fc0b 7479 /* PowerPC 440 EP */
80d11f44
JM		 7480 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7481#endif
7482#if defined(TODO_USER_ONLY)
a750fc0b 7483 /* PowerPC 440 EPa */
80d11f44
JM		 7484 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7485#endif
7486#if defined(TODO_USER_ONLY)
a750fc0b 7487 /* PowerPC 440 EPb */
80d11f44
JM		 7488 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7489#endif
7490#if defined(TODO_USER_ONLY)
a750fc0b 7491 /* PowerPC 440 EPX */
80d11f44
JM		 7492 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7493#endif
7494#if defined(TODO_USER_ONLY)
a750fc0b 7495 /* PowerPC 440 GP */
80d11f44
JM		 7496 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7497#endif
7498#if defined(TODO_USER_ONLY)
a750fc0b 7499 /* PowerPC 440 GPb */
80d11f44
JM		 7500 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7501#endif
7502#if defined(TODO_USER_ONLY)
a750fc0b 7503 /* PowerPC 440 GPc */
80d11f44
JM		 7504 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7505#endif
7506#if defined(TODO_USER_ONLY)
a750fc0b 7507 /* PowerPC 440 GR */
80d11f44
JM		 7508 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7509#endif
7510#if defined(TODO_USER_ONLY)
a750fc0b 7511 /* PowerPC 440 GRa */
80d11f44
JM		 7512 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7513#endif
7514#if defined(TODO_USER_ONLY)
a750fc0b 7515 /* PowerPC 440 GRX */
80d11f44
JM		 7516 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7517#endif
7518#if defined(TODO_USER_ONLY)
a750fc0b 7519 /* PowerPC 440 GX */
80d11f44
JM		 7520 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7521#endif
7522#if defined(TODO_USER_ONLY)
a750fc0b 7523 /* PowerPC 440 GXa */
80d11f44
JM		 7524 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7525#endif
7526#if defined(TODO_USER_ONLY)
a750fc0b 7527 /* PowerPC 440 GXb */
80d11f44
JM		 7528 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7529#endif
7530#if defined(TODO_USER_ONLY)
a750fc0b 7531 /* PowerPC 440 GXc */
80d11f44
JM		 7532 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7533#endif
7534#if defined(TODO_USER_ONLY)
a750fc0b 7535 /* PowerPC 440 GXf */
80d11f44
JM		 7536 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7537#endif
a750fc0b
JM		 7538#if defined(TODO)
7539 /* PowerPC 440 S */
80d11f44 7540 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7541#endif
80d11f44 7542#if defined(TODO_USER_ONLY)
a750fc0b 7543 /* PowerPC 440 SP */
80d11f44
JM		 7544 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7545#endif
7546#if defined(TODO_USER_ONLY)
a750fc0b 7547 /* PowerPC 440 SP2 */
80d11f44
JM		 7548 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7549#endif
7550#if defined(TODO_USER_ONLY)
a750fc0b 7551 /* PowerPC 440 SPE */
80d11f44
JM		 7552 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7553#endif
a750fc0b
JM		 7554 /* PowerPC 460 family */
7555#if defined (TODO)
7556 /* Generic PowerPC 464 */
80d11f44 7557 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7558#endif
7559 /* PowerPC 464 microcontrolers */
7560#if defined (TODO)
7561 /* PowerPC 464H90 */
80d11f44 7562 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7563#endif
7564#if defined (TODO)
7565 /* PowerPC 464H90F */
80d11f44 7566 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7567#endif
7568 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7569 /* MPC5xx family (aka RCPU) */
7570#if defined(TODO_USER_ONLY)
7571 /* Generic MPC5xx core */
7572 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7573#endif
7574#if defined(TODO_USER_ONLY)
7575 /* Codename for MPC5xx core */
7576 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7577#endif
7578 /* MPC5xx microcontrollers */
7579#if defined(TODO_USER_ONLY)
7580 /* MGT560 */
7581 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7582#endif
7583#if defined(TODO_USER_ONLY)
7584 /* MPC509 */
7585 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7586#endif
7587#if defined(TODO_USER_ONLY)
7588 /* MPC533 */
7589 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7590#endif
7591#if defined(TODO_USER_ONLY)
7592 /* MPC534 */
7593 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7594#endif
7595#if defined(TODO_USER_ONLY)
7596 /* MPC555 */
7597 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7598#endif
7599#if defined(TODO_USER_ONLY)
7600 /* MPC556 */
7601 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7602#endif
7603#if defined(TODO_USER_ONLY)
7604 /* MPC560 */
7605 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7606#endif
7607#if defined(TODO_USER_ONLY)
7608 /* MPC561 */
7609 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7610#endif
7611#if defined(TODO_USER_ONLY)
7612 /* MPC562 */
7613 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7614#endif
7615#if defined(TODO_USER_ONLY)
7616 /* MPC563 */
7617 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7618#endif
7619#if defined(TODO_USER_ONLY)
7620 /* MPC564 */
7621 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7622#endif
7623#if defined(TODO_USER_ONLY)
7624 /* MPC565 */
7625 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7626#endif
7627#if defined(TODO_USER_ONLY)
7628 /* MPC566 */
7629 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7630#endif
7631 /* MPC8xx family (aka PowerQUICC) */
7632#if defined(TODO_USER_ONLY)
7633 /* Generic MPC8xx core */
7634 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7635#endif
7636#if defined(TODO_USER_ONLY)
7637 /* Codename for MPC8xx core */
7638 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7639#endif
7640 /* MPC8xx microcontrollers */
7641#if defined(TODO_USER_ONLY)
7642 /* MGT823 */
7643 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7644#endif
7645#if defined(TODO_USER_ONLY)
7646 /* MPC821 */
7647 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7648#endif
7649#if defined(TODO_USER_ONLY)
7650 /* MPC823 */
7651 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7652#endif
7653#if defined(TODO_USER_ONLY)
7654 /* MPC850 */
7655 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7656#endif
7657#if defined(TODO_USER_ONLY)
7658 /* MPC852T */
7659 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7660#endif
7661#if defined(TODO_USER_ONLY)
7662 /* MPC855T */
7663 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7664#endif
7665#if defined(TODO_USER_ONLY)
7666 /* MPC857 */
7667 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7668#endif
7669#if defined(TODO_USER_ONLY)
7670 /* MPC859 */
7671 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7672#endif
7673#if defined(TODO_USER_ONLY)
7674 /* MPC860 */
7675 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7676#endif
7677#if defined(TODO_USER_ONLY)
7678 /* MPC862 */
7679 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7680#endif
7681#if defined(TODO_USER_ONLY)
7682 /* MPC866 */
7683 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7684#endif
7685#if defined(TODO_USER_ONLY)
7686 /* MPC870 */
7687 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7688#endif
7689#if defined(TODO_USER_ONLY)
7690 /* MPC875 */
7691 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7692#endif
7693#if defined(TODO_USER_ONLY)
7694 /* MPC880 */
7695 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7696#endif
7697#if defined(TODO_USER_ONLY)
7698 /* MPC885 */
7699 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7700#endif
7701 /* MPC82xx family (aka PowerQUICC-II) */
7702 /* Generic MPC52xx core */
7703 POWERPC_DEF_SVR("MPC52xx",
7704 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7705 /* Generic MPC82xx core */
7706 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7707 /* Codename for MPC82xx */
7708 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7709 /* PowerPC G2 core */
7710 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7711 /* PowerPC G2 H4 core */
7712 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7713 /* PowerPC G2 GP core */
7714 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7715 /* PowerPC G2 LS core */
7716 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7717 /* PowerPC G2 HiP3 core */
7718 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7719 /* PowerPC G2 HiP4 core */
7720 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7721 /* PowerPC MPC603 core */
7722 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7723 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7724 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7725 /* PowerPC G2LE GP core */
7726 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7727 /* PowerPC G2LE LS core */
7728 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7729 /* PowerPC G2LE GP1 core */
7730 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7731 /* PowerPC G2LE GP3 core */
7732 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7733 /* PowerPC MPC603 microcontrollers */
7734 /* MPC8240 */
7735 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7736 /* PowerPC G2 microcontrollers */
082c6681 7737#if defined(TODO)
80d11f44
JM		 7738 /* MPC5121 */
7739 POWERPC_DEF_SVR("MPC5121",
7740 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7741#endif
7742 /* MPC5200 */
7743 POWERPC_DEF_SVR("MPC5200",
7744 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7745 /* MPC5200 v1.0 */
7746 POWERPC_DEF_SVR("MPC5200_v10",
7747 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7748 /* MPC5200 v1.1 */
7749 POWERPC_DEF_SVR("MPC5200_v11",
7750 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7751 /* MPC5200 v1.2 */
7752 POWERPC_DEF_SVR("MPC5200_v12",
7753 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7754 /* MPC5200B */
7755 POWERPC_DEF_SVR("MPC5200B",
7756 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7757 /* MPC5200B v2.0 */
7758 POWERPC_DEF_SVR("MPC5200B_v20",
7759 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7760 /* MPC5200B v2.1 */
7761 POWERPC_DEF_SVR("MPC5200B_v21",
7762 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7763 /* MPC8241 */
7764 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7765 /* MPC8245 */
7766 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7767 /* MPC8247 */
7768 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7769 /* MPC8248 */
7770 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7771 /* MPC8250 */
7772 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7773 /* MPC8250 HiP3 */
7774 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7775 /* MPC8250 HiP4 */
7776 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7777 /* MPC8255 */
7778 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7779 /* MPC8255 HiP3 */
7780 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7781 /* MPC8255 HiP4 */
7782 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7783 /* MPC8260 */
7784 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7785 /* MPC8260 HiP3 */
7786 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7787 /* MPC8260 HiP4 */
7788 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7789 /* MPC8264 */
7790 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7791 /* MPC8264 HiP3 */
7792 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7793 /* MPC8264 HiP4 */
7794 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7795 /* MPC8265 */
7796 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7797 /* MPC8265 HiP3 */
7798 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7799 /* MPC8265 HiP4 */
7800 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7801 /* MPC8266 */
7802 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7803 /* MPC8266 HiP3 */
7804 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7805 /* MPC8266 HiP4 */
7806 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7807 /* MPC8270 */
7808 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7809 /* MPC8271 */
7810 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7811 /* MPC8272 */
7812 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7813 /* MPC8275 */
7814 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7815 /* MPC8280 */
7816 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 7817 /* e200 family */
a750fc0b 7818 /* Generic PowerPC e200 core */
80d11f44
JM		 7819 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7820 /* Generic MPC55xx core */
7821#if defined (TODO)
7822 POWERPC_DEF_SVR("MPC55xx",
7823 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 7824#endif
7825#if defined (TODO)
80d11f44
JM		 7826 /* PowerPC e200z0 core */
7827 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 7828#endif
7829#if defined (TODO)
80d11f44
JM		 7830 /* PowerPC e200z1 core */
7831 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7832#endif
7833#if defined (TODO)
7834 /* PowerPC e200z3 core */
7835 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7836#endif
7837 /* PowerPC e200z5 core */
7838 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 7839 /* PowerPC e200z6 core */
80d11f44
JM		 7840 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7841 /* PowerPC e200 microcontrollers */
7842#if defined (TODO)
7843 /* MPC5514E */
7844 POWERPC_DEF_SVR("MPC5514E",
7845 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 7846#endif
a750fc0b 7847#if defined (TODO)
80d11f44
JM		 7848 /* MPC5514E v0 */
7849 POWERPC_DEF_SVR("MPC5514E_v0",
7850 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 7851#endif
7852#if defined (TODO)
80d11f44
JM		 7853 /* MPC5514E v1 */
7854 POWERPC_DEF_SVR("MPC5514E_v1",
7855 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 7856#endif
7857#if defined (TODO)
80d11f44
JM		 7858 /* MPC5514G */
7859 POWERPC_DEF_SVR("MPC5514G",
7860 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 7861#endif
7862#if defined (TODO)
80d11f44
JM		 7863 /* MPC5514G v0 */
7864 POWERPC_DEF_SVR("MPC5514G_v0",
7865 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 7866#endif
a750fc0b 7867#if defined (TODO)
80d11f44
JM		 7868 /* MPC5514G v1 */
7869 POWERPC_DEF_SVR("MPC5514G_v1",
7870 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 7871#endif
7872#if defined (TODO)
80d11f44
JM		 7873 /* MPC5515S */
7874 POWERPC_DEF_SVR("MPC5515S",
7875 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 7876#endif
7877#if defined (TODO)
80d11f44
JM		 7878 /* MPC5516E */
7879 POWERPC_DEF_SVR("MPC5516E",
7880 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 7881#endif
7882#if defined (TODO)
80d11f44
JM		 7883 /* MPC5516E v0 */
7884 POWERPC_DEF_SVR("MPC5516E_v0",
7885 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 7886#endif
7887#if defined (TODO)
80d11f44
JM		 7888 /* MPC5516E v1 */
7889 POWERPC_DEF_SVR("MPC5516E_v1",
7890 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 7891#endif
a750fc0b 7892#if defined (TODO)
80d11f44
JM		 7893 /* MPC5516G */
7894 POWERPC_DEF_SVR("MPC5516G",
7895 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 7896#endif
a750fc0b 7897#if defined (TODO)
80d11f44
JM		 7898 /* MPC5516G v0 */
7899 POWERPC_DEF_SVR("MPC5516G_v0",
7900 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 7901#endif
a750fc0b 7902#if defined (TODO)
80d11f44
JM		 7903 /* MPC5516G v1 */
7904 POWERPC_DEF_SVR("MPC5516G_v1",
7905 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 7906#endif
a750fc0b 7907#if defined (TODO)
80d11f44
JM		 7908 /* MPC5516S */
7909 POWERPC_DEF_SVR("MPC5516S",
7910 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 7911#endif
7912#if defined (TODO)
80d11f44
JM		 7913 /* MPC5533 */
7914 POWERPC_DEF_SVR("MPC5533",
7915 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 7916#endif
7917#if defined (TODO)
80d11f44
JM		 7918 /* MPC5534 */
7919 POWERPC_DEF_SVR("MPC5534",
7920 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 7921#endif
80d11f44
JM		 7922#if defined (TODO)
7923 /* MPC5553 */
7924 POWERPC_DEF_SVR("MPC5553",
7925 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7926#endif
7927#if defined (TODO)
7928 /* MPC5554 */
7929 POWERPC_DEF_SVR("MPC5554",
7930 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7931#endif
7932#if defined (TODO)
7933 /* MPC5561 */
7934 POWERPC_DEF_SVR("MPC5561",
7935 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7936#endif
7937#if defined (TODO)
7938 /* MPC5565 */
7939 POWERPC_DEF_SVR("MPC5565",
7940 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7941#endif
7942#if defined (TODO)
7943 /* MPC5566 */
7944 POWERPC_DEF_SVR("MPC5566",
7945 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7946#endif
7947#if defined (TODO)
7948 /* MPC5567 */
7949 POWERPC_DEF_SVR("MPC5567",
7950 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7951#endif
7952 /* e300 family */
7953 /* Generic PowerPC e300 core */
7954 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7955 /* PowerPC e300c1 core */
7956 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7957 /* PowerPC e300c2 core */
7958 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7959 /* PowerPC e300c3 core */
7960 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7961 /* PowerPC e300c4 core */
7962 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7963 /* PowerPC e300 microcontrollers */
7964#if defined (TODO)
7965 /* MPC8313 */
7966 POWERPC_DEF_SVR("MPC8313",
7967 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
7968#endif
7969#if defined (TODO)
7970 /* MPC8313E */
7971 POWERPC_DEF_SVR("MPC8313E",
7972 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
7973#endif
7974#if defined (TODO)
7975 /* MPC8314 */
7976 POWERPC_DEF_SVR("MPC8314",
7977 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
7978#endif
7979#if defined (TODO)
7980 /* MPC8314E */
7981 POWERPC_DEF_SVR("MPC8314E",
7982 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
7983#endif
7984#if defined (TODO)
7985 /* MPC8315 */
7986 POWERPC_DEF_SVR("MPC8315",
7987 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
7988#endif
7989#if defined (TODO)
7990 /* MPC8315E */
7991 POWERPC_DEF_SVR("MPC8315E",
7992 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
7993#endif
7994#if defined (TODO)
7995 /* MPC8321 */
7996 POWERPC_DEF_SVR("MPC8321",
7997 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
7998#endif
7999#if defined (TODO)
8000 /* MPC8321E */
8001 POWERPC_DEF_SVR("MPC8321E",
8002 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
8003#endif
8004#if defined (TODO)
8005 /* MPC8323 */
8006 POWERPC_DEF_SVR("MPC8323",
8007 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
8008#endif
8009#if defined (TODO)
8010 /* MPC8323E */
8011 POWERPC_DEF_SVR("MPC8323E",
8012 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
8013#endif
8014 /* MPC8343A */
8015 POWERPC_DEF_SVR("MPC8343A",
8016 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
8017 /* MPC8343EA */
8018 POWERPC_DEF_SVR("MPC8343EA",
8019 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
8020 /* MPC8347A */
8021 POWERPC_DEF_SVR("MPC8347A",
8022 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
8023 /* MPC8347AT */
8024 POWERPC_DEF_SVR("MPC8347AT",
8025 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
8026 /* MPC8347AP */
8027 POWERPC_DEF_SVR("MPC8347AP",
8028 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
8029 /* MPC8347EA */
8030 POWERPC_DEF_SVR("MPC8347EA",
8031 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
8032 /* MPC8347EAT */
8033 POWERPC_DEF_SVR("MPC8347EAT",
8034 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
8035 /* MPC8343EAP */
8036 POWERPC_DEF_SVR("MPC8347EAP",
8037 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
8038 /* MPC8349 */
8039 POWERPC_DEF_SVR("MPC8349",
8040 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
8041 /* MPC8349A */
8042 POWERPC_DEF_SVR("MPC8349A",
8043 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
8044 /* MPC8349E */
8045 POWERPC_DEF_SVR("MPC8349E",
8046 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
8047 /* MPC8349EA */
8048 POWERPC_DEF_SVR("MPC8349EA",
8049 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
8050#if defined (TODO)
8051 /* MPC8358E */
8052 POWERPC_DEF_SVR("MPC8358E",
8053 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
8054#endif
8055#if defined (TODO)
8056 /* MPC8360E */
8057 POWERPC_DEF_SVR("MPC8360E",
8058 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
8059#endif
8060 /* MPC8377 */
8061 POWERPC_DEF_SVR("MPC8377",
8062 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
8063 /* MPC8377E */
8064 POWERPC_DEF_SVR("MPC8377E",
8065 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
8066 /* MPC8378 */
8067 POWERPC_DEF_SVR("MPC8378",
8068 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
8069 /* MPC8378E */
8070 POWERPC_DEF_SVR("MPC8378E",
8071 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
8072 /* MPC8379 */
8073 POWERPC_DEF_SVR("MPC8379",
8074 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
8075 /* MPC8379E */
8076 POWERPC_DEF_SVR("MPC8379E",
8077 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
8078 /* e500 family */
8079 /* PowerPC e500 core */
bd5ea513
AJ		 8080 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8081 /* PowerPC e500v1 core */
8082 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8083 /* PowerPC e500 v1.0 core */
bd5ea513 8084 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8085 /* PowerPC e500 v2.0 core */
bd5ea513 8086 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8087 /* PowerPC e500v2 core */
bd5ea513 8088 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8089 /* PowerPC e500v2 v1.0 core */
bd5ea513 8090 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8091 /* PowerPC e500v2 v2.0 core */
bd5ea513 8092 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8093 /* PowerPC e500v2 v2.1 core */
bd5ea513 8094 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8095 /* PowerPC e500v2 v2.2 core */
bd5ea513 8096 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8097 /* PowerPC e500v2 v3.0 core */
bd5ea513 8098 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
80d11f44
JM		 8099 /* PowerPC e500 microcontrollers */
8100 /* MPC8533 */
8101 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8102 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8103 /* MPC8533 v1.0 */
8104 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8105 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8106 /* MPC8533 v1.1 */
8107 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8108 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8109 /* MPC8533E */
8110 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8111 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8112 /* MPC8533E v1.0 */
8113 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8114 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8115 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8116 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8117 /* MPC8540 */
8118 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8119 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8120 /* MPC8540 v1.0 */
8121 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8122 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8123 /* MPC8540 v2.0 */
8124 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8125 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8126 /* MPC8540 v2.1 */
8127 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8128 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8129 /* MPC8541 */
8130 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8131 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8132 /* MPC8541 v1.0 */
8133 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8134 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8135 /* MPC8541 v1.1 */
8136 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8137 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8138 /* MPC8541E */
8139 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8140 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8141 /* MPC8541E v1.0 */
8142 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8143 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8144 /* MPC8541E v1.1 */
8145 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8146 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8147 /* MPC8543 */
8148 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8149 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8150 /* MPC8543 v1.0 */
8151 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8152 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8153 /* MPC8543 v1.1 */
8154 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8155 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8156 /* MPC8543 v2.0 */
8157 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8158 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8159 /* MPC8543 v2.1 */
8160 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8161 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8162 /* MPC8543E */
8163 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8164 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8165 /* MPC8543E v1.0 */
8166 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8167 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8168 /* MPC8543E v1.1 */
8169 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8170 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8171 /* MPC8543E v2.0 */
8172 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8173 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8174 /* MPC8543E v2.1 */
8175 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8176 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8177 /* MPC8544 */
8178 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8179 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8180 /* MPC8544 v1.0 */
8181 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8182 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8183 /* MPC8544 v1.1 */
8184 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8185 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8186 /* MPC8544E */
8187 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8188 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8189 /* MPC8544E v1.0 */
8190 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8191 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8192 /* MPC8544E v1.1 */
8193 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8194 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8195 /* MPC8545 */
8196 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8197 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8198 /* MPC8545 v2.0 */
8199 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8200 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8201 /* MPC8545 v2.1 */
8202 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8203 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8204 /* MPC8545E */
8205 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8206 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8207 /* MPC8545E v2.0 */
8208 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8209 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8210 /* MPC8545E v2.1 */
8211 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8212 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8213 /* MPC8547E */
8214 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8215 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8216 /* MPC8547E v2.0 */
8217 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8218 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8219 /* MPC8547E v2.1 */
8220 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8221 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8222 /* MPC8548 */
8223 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8224 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8225 /* MPC8548 v1.0 */
8226 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8227 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8228 /* MPC8548 v1.1 */
8229 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8230 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8231 /* MPC8548 v2.0 */
8232 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8233 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8234 /* MPC8548 v2.1 */
8235 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8236 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8237 /* MPC8548E */
8238 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8239 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8240 /* MPC8548E v1.0 */
8241 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8242 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8243 /* MPC8548E v1.1 */
8244 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8245 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8246 /* MPC8548E v2.0 */
8247 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8248 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8249 /* MPC8548E v2.1 */
8250 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8251 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8252 /* MPC8555 */
8253 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8254 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8255 /* MPC8555 v1.0 */
8256 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8257 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8258 /* MPC8555 v1.1 */
8259 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8260 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8261 /* MPC8555E */
8262 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8263 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8264 /* MPC8555E v1.0 */
8265 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8266 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8267 /* MPC8555E v1.1 */
8268 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8269 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8270 /* MPC8560 */
8271 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8272 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8273 /* MPC8560 v1.0 */
8274 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8275 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8276 /* MPC8560 v2.0 */
8277 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8278 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8279 /* MPC8560 v2.1 */
8280 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8281 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8282 /* MPC8567 */
8283 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8284 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8285 /* MPC8567E */
8286 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8287 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8288 /* MPC8568 */
8289 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8290 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8291 /* MPC8568E */
8292 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8293 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8294 /* MPC8572 */
8295 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8296 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8297 /* MPC8572E */
8298 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8299 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8300 /* e600 family */
8301 /* PowerPC e600 core */
8302 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8303 /* PowerPC e600 microcontrollers */
8304#if defined (TODO)
8305 /* MPC8610 */
8306 POWERPC_DEF_SVR("MPC8610",
8307 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8308#endif
8309 /* MPC8641 */
8310 POWERPC_DEF_SVR("MPC8641",
8311 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8312 /* MPC8641D */
8313 POWERPC_DEF_SVR("MPC8641D",
8314 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8315 /* 32 bits "classic" PowerPC */
8316 /* PowerPC 6xx family */
8317 /* PowerPC 601 */
bd928eba 8318 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8319 /* PowerPC 601v0 */
082c6681 8320 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8321 /* PowerPC 601v1 */
082c6681
JM		 8322 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8323 /* PowerPC 601v */
bd928eba 8324 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8325 /* PowerPC 601v2 */
082c6681 8326 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8327 /* PowerPC 602 */
80d11f44 8328 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8329 /* PowerPC 603 */
80d11f44 8330 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8331 /* Code name for PowerPC 603 */
80d11f44 8332 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8333 /* PowerPC 603e (aka PID6) */
80d11f44 8334 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8335 /* Code name for PowerPC 603e */
80d11f44 8336 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8337 /* PowerPC 603e v1.1 */
80d11f44 8338 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8339 /* PowerPC 603e v1.2 */
80d11f44 8340 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8341 /* PowerPC 603e v1.3 */
80d11f44 8342 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8343 /* PowerPC 603e v1.4 */
80d11f44 8344 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8345 /* PowerPC 603e v2.2 */
80d11f44 8346 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8347 /* PowerPC 603e v3 */
80d11f44 8348 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8349 /* PowerPC 603e v4 */
80d11f44 8350 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8351 /* PowerPC 603e v4.1 */
80d11f44 8352 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8353 /* PowerPC 603e (aka PID7) */
80d11f44 8354 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8355 /* PowerPC 603e7t */
80d11f44 8356 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8357 /* PowerPC 603e7v */
80d11f44 8358 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8359 /* Code name for PowerPC 603ev */
80d11f44 8360 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8361 /* PowerPC 603e7v1 */
80d11f44 8362 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8363 /* PowerPC 603e7v2 */
80d11f44 8364 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8365 /* PowerPC 603p (aka PID7v) */
8366 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8367 /* PowerPC 603r (aka PID7t) */
80d11f44 8368 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8369 /* Code name for PowerPC 603r */
80d11f44 8370 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8371 /* PowerPC 604 */
80d11f44 8372 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8373 /* PowerPC 604e (aka PID9) */
8374 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8375 /* Code name for PowerPC 604e */
8376 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8377 /* PowerPC 604e v1.0 */
082c6681 8378 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8379 /* PowerPC 604e v2.2 */
082c6681 8380 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8381 /* PowerPC 604e v2.4 */
082c6681
JM		 8382 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8383 /* PowerPC 604r (aka PIDA) */
8384 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8385 /* Code name for PowerPC 604r */
8386 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8387#if defined(TODO)
8388 /* PowerPC 604ev */
082c6681 8389 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8390#endif
8391 /* PowerPC 7xx family */
8392 /* Generic PowerPC 740 (G3) */
bd928eba 8393 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8394 /* Code name for PowerPC 740 */
bd928eba 8395 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8396 /* Generic PowerPC 750 (G3) */
bd928eba 8397 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8398 /* Code name for PowerPC 750 */
bd928eba 8399 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8400 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8401 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8402 /* PowerPC 740 v1.0 (G3) */
8403 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8404 /* PowerPC 750 v1.0 (G3) */
8405 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8406 /* PowerPC 740 v2.0 (G3) */
bd928eba 8407 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8408 /* PowerPC 750 v2.0 (G3) */
bd928eba 8409 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8410 /* PowerPC 740 v2.1 (G3) */
bd928eba 8411 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8412 /* PowerPC 750 v2.1 (G3) */
bd928eba 8413 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8414 /* PowerPC 740 v2.2 (G3) */
bd928eba 8415 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8416 /* PowerPC 750 v2.2 (G3) */
bd928eba 8417 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8418 /* PowerPC 740 v3.0 (G3) */
bd928eba 8419 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8420 /* PowerPC 750 v3.0 (G3) */
bd928eba 8421 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8422 /* PowerPC 740 v3.1 (G3) */
bd928eba 8423 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8424 /* PowerPC 750 v3.1 (G3) */
bd928eba 8425 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8426 /* PowerPC 740E (G3) */
bd928eba
JM		 8427 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8428 /* PowerPC 750E (G3) */
8429 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8430 /* PowerPC 740P (G3) */
bd928eba 8431 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8432 /* PowerPC 750P (G3) */
bd928eba 8433 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8434 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8435 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8436 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8437 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8438 /* PowerPC 750CL v1.0 */
8439 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8440 /* PowerPC 750CL v2.0 */
8441 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8442 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8443 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8444 /* PowerPC 750CX v1.0 (G3 embedded) */
8445 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8446 /* PowerPC 750CX v2.1 (G3 embedded) */
8447 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8448 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8449 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8450 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8451 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8452 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8453 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8454 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8455 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8456 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8457 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8458 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8459 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8460 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8461 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8462 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8463 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8464 /* PowerPC 750CXe v3.0 (G3 embedded) */
8465 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8466 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8467 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8468 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8469 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8470 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8471 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8472 /* PowerPC 750FL (G3 embedded) */
80d11f44 8473 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8474 /* PowerPC 750FX (G3 embedded) */
80d11f44 8475 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8476 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8477 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8478 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8479 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8480 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8481 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8482 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8483 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8484 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8485 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8486 /* PowerPC 750GL (G3 embedded) */
bd928eba 8487 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8488 /* PowerPC 750GX (G3 embedded) */
bd928eba 8489 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8490 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8491 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8492 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8493 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8494 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8495 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8496 /* PowerPC 750L (G3 embedded) */
bd928eba 8497 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8498 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8499 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8500 /* PowerPC 750L v2.0 (G3 embedded) */
8501 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8502 /* PowerPC 750L v2.1 (G3 embedded) */
8503 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8504 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8505 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8506 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8507 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8508 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8509 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8510 /* Generic PowerPC 745 */
bd928eba 8511 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8512 /* Generic PowerPC 755 */
bd928eba 8513 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8514 /* Code name for PowerPC 745/755 */
bd928eba 8515 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8516 /* PowerPC 745 v1.0 */
bd928eba 8517 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8518 /* PowerPC 755 v1.0 */
bd928eba 8519 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8520 /* PowerPC 745 v1.1 */
bd928eba 8521 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8522 /* PowerPC 755 v1.1 */
bd928eba 8523 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8524 /* PowerPC 745 v2.0 */
bd928eba 8525 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8526 /* PowerPC 755 v2.0 */
bd928eba 8527 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8528 /* PowerPC 745 v2.1 */
bd928eba 8529 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8530 /* PowerPC 755 v2.1 */
bd928eba 8531 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8532 /* PowerPC 745 v2.2 */
bd928eba 8533 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8534 /* PowerPC 755 v2.2 */
bd928eba 8535 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8536 /* PowerPC 745 v2.3 */
bd928eba 8537 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8538 /* PowerPC 755 v2.3 */
bd928eba 8539 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8540 /* PowerPC 745 v2.4 */
bd928eba 8541 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8542 /* PowerPC 755 v2.4 */
bd928eba 8543 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8544 /* PowerPC 745 v2.5 */
bd928eba 8545 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8546 /* PowerPC 755 v2.5 */
bd928eba 8547 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8548 /* PowerPC 745 v2.6 */
bd928eba 8549 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8550 /* PowerPC 755 v2.6 */
bd928eba 8551 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8552 /* PowerPC 745 v2.7 */
bd928eba 8553 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8554 /* PowerPC 755 v2.7 */
bd928eba 8555 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8556 /* PowerPC 745 v2.8 */
bd928eba 8557 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8558 /* PowerPC 755 v2.8 */
bd928eba 8559 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8560#if defined (TODO)
8561 /* PowerPC 745P (G3) */
bd928eba 8562 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8563 /* PowerPC 755P (G3) */
bd928eba 8564 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8565#endif
8566 /* PowerPC 74xx family */
8567 /* PowerPC 7400 (G4) */
80d11f44 8568 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8569 /* Code name for PowerPC 7400 */
80d11f44 8570 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8571 /* PowerPC 74xx is also well known as G4 */
80d11f44 8572 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8573 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8574 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8575 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8576 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8577 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8578 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8579 /* PowerPC 7400 v2.1 (G4) */
8580 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8581 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8582 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8583 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8584 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8585 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8586 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8587 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8588 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8589 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8590 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8591 /* PowerPC 7410 (G4) */
80d11f44 8592 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8593 /* Code name for PowerPC 7410 */
80d11f44 8594 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8595 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8596 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8597 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8598 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8599 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8600 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8601 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8602 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8603 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8604 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8605 /* PowerPC 7448 (G4) */
80d11f44 8606 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8607 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8608 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8609 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8610 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8611 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8612 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8613 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8614 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8615 /* PowerPC 7450 (G4) */
80d11f44 8616 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8617 /* Code name for PowerPC 7450 */
80d11f44 8618 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8619 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8620 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8621 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8622 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8623 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8624 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8625 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8626 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8627 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8628 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8629 /* PowerPC 7441 (G4) */
80d11f44 8630 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8631 /* PowerPC 7451 (G4) */
80d11f44 8632 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8633 /* PowerPC 7441 v2.1 (G4) */
8634 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8635 /* PowerPC 7441 v2.3 (G4) */
8636 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8637 /* PowerPC 7451 v2.3 (G4) */
8638 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8639 /* PowerPC 7441 v2.10 (G4) */
8640 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8641 /* PowerPC 7451 v2.10 (G4) */
8642 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8643 /* PowerPC 7445 (G4) */
80d11f44 8644 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8645 /* PowerPC 7455 (G4) */
80d11f44 8646 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8647 /* Code name for PowerPC 7445/7455 */
80d11f44 8648 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8649 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8650 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8651 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8652 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8653 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8654 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8655 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8656 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8657 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8658 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8659 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8660 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8661 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8662 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8663 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8664 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8665 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8666 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8667 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8668 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8669 /* PowerPC 7447 (G4) */
80d11f44 8670 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8671 /* PowerPC 7457 (G4) */
80d11f44 8672 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 8673 /* Code name for PowerPC 7447/7457 */
80d11f44 8674 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 8675 /* PowerPC 7447 v1.0 (G4) */
80d11f44 8676 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 8677 /* PowerPC 7457 v1.0 (G4) */
80d11f44 8678 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 8679 /* PowerPC 7447 v1.1 (G4) */
80d11f44 8680 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 8681 /* PowerPC 7457 v1.1 (G4) */
80d11f44 8682 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 8683 /* PowerPC 7457 v1.2 (G4) */
80d11f44 8684 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 8685 /* PowerPC 7447A (G4) */
8686 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8687 /* PowerPC 7457A (G4) */
8688 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8689 /* PowerPC 7447A v1.0 (G4) */
8690 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8691 /* PowerPC 7457A v1.0 (G4) */
8692 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8693 /* Code name for PowerPC 7447A/7457A */
8694 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8695 /* PowerPC 7447A v1.1 (G4) */
8696 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8697 /* PowerPC 7457A v1.1 (G4) */
8698 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8699 /* PowerPC 7447A v1.2 (G4) */
8700 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8701 /* PowerPC 7457A v1.2 (G4) */
8702 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 8703 /* 64 bits PowerPC */
8704#if defined (TARGET_PPC64)
a750fc0b 8705 /* PowerPC 620 */
80d11f44 8706 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 8707 /* Code name for PowerPC 620 */
8708 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 8709#if defined (TODO)
a750fc0b 8710 /* PowerPC 630 (POWER3) */
80d11f44
JM		 8711 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8712 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 8713 /* Code names for POWER3 */
8714 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8715 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 8716#endif
3a607854 8717#if defined (TODO)
a750fc0b 8718 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 8719 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8720 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 8721#endif
8722#if defined (TODO)
a750fc0b 8723 /* POWER4 */
80d11f44 8724 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 8725#endif
3a607854 8726#if defined (TODO)
a750fc0b 8727 /* POWER4p */
80d11f44 8728 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 8729#endif
2662a059 8730#if defined (TODO)
a750fc0b 8731 /* POWER5 */
80d11f44 8732 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 8733 /* POWER5GR */
80d11f44 8734 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 8735#endif
3a607854 8736#if defined (TODO)
a750fc0b 8737 /* POWER5+ */
80d11f44 8738 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 8739 /* POWER5GS */
80d11f44 8740 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 8741#endif
2662a059 8742#if defined (TODO)
a750fc0b 8743 /* POWER6 */
80d11f44 8744 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 8745 /* POWER6 running in POWER5 mode */
80d11f44 8746 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 8747 /* POWER6A */
80d11f44 8748 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 8749#endif
a750fc0b 8750 /* PowerPC 970 */
80d11f44 8751 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 8752 /* PowerPC 970FX (G5) */
80d11f44 8753 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 8754 /* PowerPC 970FX v1.0 (G5) */
80d11f44 8755 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 8756 /* PowerPC 970FX v2.0 (G5) */
80d11f44 8757 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 8758 /* PowerPC 970FX v2.1 (G5) */
80d11f44 8759 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 8760 /* PowerPC 970FX v3.0 (G5) */
80d11f44 8761 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 8762 /* PowerPC 970FX v3.1 (G5) */
80d11f44 8763 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 8764 /* PowerPC 970GX (G5) */
80d11f44 8765 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 8766 /* PowerPC 970MP */
80d11f44 8767 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 8768 /* PowerPC 970MP v1.0 */
80d11f44 8769 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 8770 /* PowerPC 970MP v1.1 */
80d11f44 8771 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 8772#if defined (TODO)
a750fc0b 8773 /* PowerPC Cell */
80d11f44 8774 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 8775#endif
8776#if defined (TODO)
a750fc0b 8777 /* PowerPC Cell v1.0 */
80d11f44 8778 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 8779#endif
8780#if defined (TODO)
a750fc0b 8781 /* PowerPC Cell v2.0 */
80d11f44 8782 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 8783#endif
8784#if defined (TODO)
a750fc0b 8785 /* PowerPC Cell v3.0 */
80d11f44 8786 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 8787#endif
3a607854 8788#if defined (TODO)
a750fc0b 8789 /* PowerPC Cell v3.1 */
80d11f44 8790 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 8791#endif
8792#if defined (TODO)
a750fc0b 8793 /* PowerPC Cell v3.2 */
80d11f44 8794 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 8795#endif
8796#if defined (TODO)
a750fc0b
JM		 8797 /* RS64 (Apache/A35) */
8798 /* This one seems to support the whole POWER2 instruction set
8799 * and the PowerPC 64 one.
8800 */
8801 /* What about A10 & A30 ? */
80d11f44
JM		 8802 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8803 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8804 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 8805#endif
8806#if defined (TODO)
a750fc0b 8807 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 8808 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8809 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8810 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 8811#endif
8812#if defined (TODO)
a750fc0b 8813 /* RS64-III (Pulsar) */
80d11f44
JM		 8814 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8815 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 8816#endif
8817#if defined (TODO)
a750fc0b 8818 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 8819 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8820 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8821 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8822 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 8823#endif
a750fc0b
JM		 8824#endif /* defined (TARGET_PPC64) */
8825 /* POWER */
3fc6c082 8826#if defined (TODO)
a750fc0b 8827 /* Original POWER */
80d11f44
JM		 8828 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8829 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8830 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8831 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8832 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 8833#endif
8834#if defined (TODO)
a750fc0b 8835 /* POWER2 */
80d11f44
JM		 8836 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8837 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8838 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 8839#endif
8840 /* PA semi cores */
8841#if defined (TODO)
8842 /* PA PA6T */
80d11f44 8843 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 8844#endif
8845 /* Generic PowerPCs */
8846#if defined (TARGET_PPC64)
80d11f44 8847 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 8848#endif
80d11f44
JM		 8849 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8850 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 8851 /* Fallback */
80d11f44 8852 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 8853};
8854
8855/*****************************************************************************/
8856/* Generic CPU instanciation routine */
aaed909a 8857static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8858{
8859#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 8860 int i;
8861
a750fc0b 8862 env->irq_inputs = NULL;
e1833e1f
JM		 8863 /* Set all exception vectors to an invalid address */
8864 for (i = 0; i < POWERPC_EXCP_NB; i++)
8865 env->excp_vectors[i] = (target_ulong)(-1ULL);
8866 env->excp_prefix = 0x00000000;
8867 env->ivor_mask = 0x00000000;
8868 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 8869 /* Default MMU definitions */
8870 env->nb_BATs = 0;
8871 env->nb_tlb = 0;
8872 env->nb_ways = 0;
f2e63a42 8873#endif
a750fc0b
JM		 8874 /* Register SPR common to all PowerPC implementations */
8875 gen_spr_generic(env);
8876 spr_register(env, SPR_PVR, "PVR",
8877 SPR_NOACCESS, SPR_NOACCESS,
8878 &spr_read_generic, SPR_NOACCESS,
8879 def->pvr);
80d11f44
JM		 8880 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8881 if (def->svr != POWERPC_SVR_NONE) {
8882 if (def->svr & POWERPC_SVR_E500) {
8883 spr_register(env, SPR_E500_SVR, "SVR",
8884 SPR_NOACCESS, SPR_NOACCESS,
8885 &spr_read_generic, SPR_NOACCESS,
8886 def->svr & ~POWERPC_SVR_E500);
8887 } else {
8888 spr_register(env, SPR_SVR, "SVR",
8889 SPR_NOACCESS, SPR_NOACCESS,
8890 &spr_read_generic, SPR_NOACCESS,
8891 def->svr);
8892 }
8893 }
a750fc0b
JM		 8894 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8895 (*def->init_proc)(env);
25ba3a68
JM		 8896 /* MSR bits & flags consistency checks */
8897 if (env->msr_mask & (1 << 25)) {
8898 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8899 case POWERPC_FLAG_SPE:
8900 case POWERPC_FLAG_VRE:
8901 break;
8902 default:
8903 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8904 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8905 exit(1);
8906 }
8907 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8908 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8909 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8910 exit(1);
8911 }
8912 if (env->msr_mask & (1 << 17)) {
8913 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8914 case POWERPC_FLAG_TGPR:
8915 case POWERPC_FLAG_CE:
8916 break;
8917 default:
8918 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8919 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8920 exit(1);
8921 }
8922 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8923 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8924 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8925 exit(1);
8926 }
8927 if (env->msr_mask & (1 << 10)) {
8928 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8929 POWERPC_FLAG_UBLE)) {
8930 case POWERPC_FLAG_SE:
8931 case POWERPC_FLAG_DWE:
8932 case POWERPC_FLAG_UBLE:
8933 break;
8934 default:
8935 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8936 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8937 "POWERPC_FLAG_UBLE\n");
8938 exit(1);
8939 }
8940 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8941 POWERPC_FLAG_UBLE)) {
8942 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8943 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8944 "POWERPC_FLAG_UBLE\n");
8945 exit(1);
8946 }
8947 if (env->msr_mask & (1 << 9)) {
8948 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8949 case POWERPC_FLAG_BE:
8950 case POWERPC_FLAG_DE:
8951 break;
8952 default:
8953 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8954 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8955 exit(1);
8956 }
8957 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8958 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8959 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8960 exit(1);
8961 }
8962 if (env->msr_mask & (1 << 2)) {
8963 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8964 case POWERPC_FLAG_PX:
8965 case POWERPC_FLAG_PMM:
8966 break;
8967 default:
8968 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8969 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8970 exit(1);
8971 }
8972 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8973 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8974 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8975 exit(1);
8976 }
4018bae9
JM		 8977 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8978 fprintf(stderr, "PowerPC flags inconsistency\n"
8979 "Should define the time-base and decrementer clock source\n");
8980 exit(1);
8981 }
a750fc0b 8982 /* Allocate TLBs buffer when needed */
f2e63a42 8983#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8984 if (env->nb_tlb != 0) {
8985 int nb_tlb = env->nb_tlb;
8986 if (env->id_tlbs != 0)
8987 nb_tlb *= 2;
8988 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8989 /* Pre-compute some useful values */
8990 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8991 }
a750fc0b
JM		 8992 if (env->irq_inputs == NULL) {
8993 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8994 " Attempt Qemu to crash very soon !\n");
8995 }
8996#endif
2f462816
JM		 8997 if (env->check_pow == NULL) {
8998 fprintf(stderr, "WARNING: no power management check handler "
8999 "registered.\n"
9000 " Attempt Qemu to crash very soon !\n");
9001 }
a750fc0b
JM		 9002}
9003
9004#if defined(PPC_DUMP_CPU)
9005static void dump_ppc_sprs (CPUPPCState *env)
9006{
9007 ppc_spr_t *spr;
9008#if !defined(CONFIG_USER_ONLY)
9009 uint32_t sr, sw;
9010#endif
9011 uint32_t ur, uw;
9012 int i, j, n;
9013
9014 printf("Special purpose registers:\n");
9015 for (i = 0; i < 32; i++) {
9016 for (j = 0; j < 32; j++) {
9017 n = (i << 5) | j;
9018 spr = &env->spr_cb[n];
9019 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9020 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9021#if !defined(CONFIG_USER_ONLY)
9022 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9023 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9024 if (sw || sr || uw || ur) {
9025 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9026 (i << 5) | j, (i << 5) | j, spr->name,
9027 sw ? 'w' : '-', sr ? 'r' : '-',
9028 uw ? 'w' : '-', ur ? 'r' : '-');
9029 }
9030#else
9031 if (uw || ur) {
9032 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9033 (i << 5) | j, (i << 5) | j, spr->name,
9034 uw ? 'w' : '-', ur ? 'r' : '-');
9035 }
9036#endif
9037 }
9038 }
9039 fflush(stdout);
9040 fflush(stderr);
9041}
9042#endif
9043
9044/*****************************************************************************/
9045#include <stdlib.h>
9046#include <string.h>
9047
a750fc0b
JM		 9048/* Opcode types */
9049enum {
9050 PPC_DIRECT = 0, /* Opcode routine */
9051 PPC_INDIRECT = 1, /* Indirect opcode table */
9052};
9053
9054static inline int is_indirect_opcode (void *handler)
9055{
9056 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9057}
9058
9059static inline opc_handler_t **ind_table(void *handler)
9060{
9061 return (opc_handler_t **)((unsigned long)handler & ~3);
9062}
9063
9064/* Instruction table creation */
9065/* Opcodes tables creation */
9066static void fill_new_table (opc_handler_t **table, int len)
9067{
9068 int i;
9069
9070 for (i = 0; i < len; i++)
9071 table[i] = &invalid_handler;
9072}
9073
9074static int create_new_table (opc_handler_t **table, unsigned char idx)
9075{
9076 opc_handler_t **tmp;
9077
9078 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b
JM		 9079 fill_new_table(tmp, 0x20);
9080 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9081
9082 return 0;
9083}
9084
9085static int insert_in_table (opc_handler_t **table, unsigned char idx,
9086 opc_handler_t *handler)
9087{
9088 if (table[idx] != &invalid_handler)
9089 return -1;
9090 table[idx] = handler;
9091
9092 return 0;
9093}
9094
9095static int register_direct_insn (opc_handler_t **ppc_opcodes,
9096 unsigned char idx, opc_handler_t *handler)
9097{
9098 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9099 printf("*** ERROR: opcode %02x already assigned in main "
9100 "opcode table\n", idx);
4c1b1bfe
JM		 9101#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9102 printf(" Registered handler '%s' - new handler '%s'\n",
9103 ppc_opcodes[idx]->oname, handler->oname);
9104#endif
a750fc0b
JM		 9105 return -1;
9106 }
9107
9108 return 0;
9109}
9110
9111static int register_ind_in_table (opc_handler_t **table,
9112 unsigned char idx1, unsigned char idx2,
9113 opc_handler_t *handler)
9114{
9115 if (table[idx1] == &invalid_handler) {
9116 if (create_new_table(table, idx1) < 0) {
9117 printf("*** ERROR: unable to create indirect table "
9118 "idx=%02x\n", idx1);
9119 return -1;
9120 }
9121 } else {
9122 if (!is_indirect_opcode(table[idx1])) {
9123 printf("*** ERROR: idx %02x already assigned to a direct "
9124 "opcode\n", idx1);
4c1b1bfe
JM		 9125#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9126 printf(" Registered handler '%s' - new handler '%s'\n",
9127 ind_table(table[idx1])[idx2]->oname, handler->oname);
9128#endif
a750fc0b
JM		 9129 return -1;
9130 }
3a607854 9131 }
a750fc0b
JM		 9132 if (handler != NULL &&
9133 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9134 printf("*** ERROR: opcode %02x already assigned in "
9135 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9136#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9137 printf(" Registered handler '%s' - new handler '%s'\n",
9138 ind_table(table[idx1])[idx2]->oname, handler->oname);
9139#endif
a750fc0b 9140 return -1;
3a607854 9141 }
a750fc0b
JM		 9142
9143 return 0;
9144}
9145
9146static int register_ind_insn (opc_handler_t **ppc_opcodes,
9147 unsigned char idx1, unsigned char idx2,
9148 opc_handler_t *handler)
9149{
9150 int ret;
9151
9152 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9153
9154 return ret;
9155}
9156
9157static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9158 unsigned char idx1, unsigned char idx2,
9159 unsigned char idx3, opc_handler_t *handler)
9160{
9161 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9162 printf("*** ERROR: unable to join indirect table idx "
9163 "[%02x-%02x]\n", idx1, idx2);
9164 return -1;
9165 }
9166 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9167 handler) < 0) {
9168 printf("*** ERROR: unable to insert opcode "
9169 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9170 return -1;
9171 }
9172
9173 return 0;
9174}
9175
9176static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9177{
9178 if (insn->opc2 != 0xFF) {
9179 if (insn->opc3 != 0xFF) {
9180 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9181 insn->opc3, &insn->handler) < 0)
9182 return -1;
9183 } else {
9184 if (register_ind_insn(ppc_opcodes, insn->opc1,
9185 insn->opc2, &insn->handler) < 0)
9186 return -1;
9187 }
9188 } else {
9189 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9190 return -1;
9191 }
9192
9193 return 0;
9194}
9195
9196static int test_opcode_table (opc_handler_t **table, int len)
9197{
9198 int i, count, tmp;
9199
9200 for (i = 0, count = 0; i < len; i++) {
9201 /* Consistency fixup */
9202 if (table[i] == NULL)
9203 table[i] = &invalid_handler;
9204 if (table[i] != &invalid_handler) {
9205 if (is_indirect_opcode(table[i])) {
9206 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9207 if (tmp == 0) {
9208 free(table[i]);
9209 table[i] = &invalid_handler;
9210 } else {
9211 count++;
9212 }
9213 } else {
9214 count++;
9215 }
9216 }
9217 }
9218
9219 return count;
9220}
9221
9222static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9223{
9224 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9225 printf("*** WARNING: no opcode defined !\n");
9226}
9227
9228/*****************************************************************************/
aaed909a 9229static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9230{
9231 opcode_t *opc, *start, *end;
9232
9233 fill_new_table(env->opcodes, 0x40);
9234 if (&opc_start < &opc_end) {
9235 start = &opc_start;
9236 end = &opc_end;
9237 } else {
9238 start = &opc_end;
9239 end = &opc_start;
9240 }
9241 for (opc = start + 1; opc != end; opc++) {
9242 if ((opc->handler.type & def->insns_flags) != 0) {
9243 if (register_insn(env->opcodes, opc) < 0) {
9244 printf("*** ERROR initializing PowerPC instruction "
9245 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9246 opc->opc3);
9247 return -1;
9248 }
9249 }
9250 }
9251 fix_opcode_tables(env->opcodes);
9252 fflush(stdout);
9253 fflush(stderr);
9254
9255 return 0;
9256}
9257
9258#if defined(PPC_DUMP_CPU)
25ba3a68 9259static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 9260{
9261 opc_handler_t **table, *handler;
b55266b5 9262 const char *p, *q;
a750fc0b
JM		 9263 uint8_t opc1, opc2, opc3;
9264
9265 printf("Instructions set:\n");
9266 /* opc1 is 6 bits long */
9267 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9268 table = env->opcodes;
9269 handler = table[opc1];
9270 if (is_indirect_opcode(handler)) {
9271 /* opc2 is 5 bits long */
9272 for (opc2 = 0; opc2 < 0x20; opc2++) {
9273 table = env->opcodes;
9274 handler = env->opcodes[opc1];
9275 table = ind_table(handler);
9276 handler = table[opc2];
9277 if (is_indirect_opcode(handler)) {
9278 table = ind_table(handler);
9279 /* opc3 is 5 bits long */
9280 for (opc3 = 0; opc3 < 0x20; opc3++) {
9281 handler = table[opc3];
9282 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9283 /* Special hack to properly dump SPE insns */
9284 p = strchr(handler->oname, '_');
9285 if (p == NULL) {
9286 printf("INSN: %02x %02x %02x (%02d %04d) : "
9287 "%s\n",
9288 opc1, opc2, opc3, opc1,
9289 (opc3 << 5) | opc2,
9290 handler->oname);
9291 } else {
9292 q = "speundef";
9293 if ((p - handler->oname) != strlen(q) ||
9294 memcmp(handler->oname, q, strlen(q)) != 0) {
9295 /* First instruction */
9296 printf("INSN: %02x %02x %02x (%02d %04d) : "
9297 "%.*s\n",
9298 opc1, opc2 << 1, opc3, opc1,
9299 (opc3 << 6) | (opc2 << 1),
9300 (int)(p - handler->oname),
9301 handler->oname);
9302 }
9303 if (strcmp(p + 1, q) != 0) {
9304 /* Second instruction */
9305 printf("INSN: %02x %02x %02x (%02d %04d) : "
9306 "%s\n",
9307 opc1, (opc2 << 1) | 1, opc3, opc1,
9308 (opc3 << 6) | (opc2 << 1) | 1,
9309 p + 1);
9310 }
9311 }
a750fc0b
JM		 9312 }
9313 }
9314 } else {
9315 if (handler->handler != &gen_invalid) {
9316 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9317 opc1, opc2, opc1, opc2, handler->oname);
9318 }
9319 }
9320 }
9321 } else {
9322 if (handler->handler != &gen_invalid) {
9323 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9324 opc1, opc1, handler->oname);
9325 }
9326 }
9327 }
9328}
3a607854 9329#endif
a750fc0b 9330
24951522
AJ		 9331static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9332{
9333 if (n < 32) {
9334 stfq_p(mem_buf, env->fpr[n]);
9335 return 8;
9336 }
9337 if (n == 32) {
9338 /* FPSCR not implemented */
9339 memset(mem_buf, 0, 4);
9340 return 4;
9341 }
9342 return 0;
9343}
9344
9345static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9346{
9347 if (n < 32) {
9348 env->fpr[n] = ldfq_p(mem_buf);
9349 return 8;
9350 }
9351 if (n == 32) {
9352 /* FPSCR not implemented */
9353 return 4;
9354 }
9355 return 0;
9356}
9357
b4f8d821
AJ		 9358static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9359{
9360 if (n < 32) {
9361#ifdef WORDS_BIGENDIAN
9362 stq_p(mem_buf, env->avr[n].u64[0]);
9363 stq_p(mem_buf+8, env->avr[n].u64[1]);
9364#else
9365 stq_p(mem_buf, env->avr[n].u64[1]);
9366 stq_p(mem_buf+8, env->avr[n].u64[0]);
9367#endif
9368 return 16;
9369 }
9370 if (n == 33) {
9371 stl_p(mem_buf, env->vscr);
9372 return 4;
9373 }
9374 if (n == 34) {
9375 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9376 return 4;
9377 }
9378 return 0;
9379}
9380
9381static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9382{
9383 if (n < 32) {
9384#ifdef WORDS_BIGENDIAN
9385 env->avr[n].u64[0] = ldq_p(mem_buf);
9386 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9387#else
9388 env->avr[n].u64[1] = ldq_p(mem_buf);
9389 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9390#endif
9391 return 16;
9392 }
9393 if (n == 33) {
9394 env->vscr = ldl_p(mem_buf);
9395 return 4;
9396 }
9397 if (n == 34) {
9398 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9399 return 4;
9400 }
9401 return 0;
9402}
9403
688890f7
AJ		 9404static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9405{
9406 if (n < 32) {
9407#if defined(TARGET_PPC64)
9408 stl_p(mem_buf, env->gpr[n] >> 32);
9409#else
9410 stl_p(mem_buf, env->gprh[n]);
9411#endif
9412 return 4;
9413 }
9414 if (n == 33) {
9415 stq_p(mem_buf, env->spe_acc);
9416 return 8;
9417 }
9418 if (n == 34) {
9419 /* SPEFSCR not implemented */
9420 memset(mem_buf, 0, 4);
9421 return 4;
9422 }
9423 return 0;
9424}
9425
9426static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9427{
9428 if (n < 32) {
9429#if defined(TARGET_PPC64)
9430 target_ulong lo = (uint32_t)env->gpr[n];
9431 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9432 env->gpr[n] = lo | hi;
9433#else
9434 env->gprh[n] = ldl_p(mem_buf);
9435#endif
9436 return 4;
9437 }
9438 if (n == 33) {
9439 env->spe_acc = ldq_p(mem_buf);
9440 return 8;
9441 }
9442 if (n == 34) {
9443 /* SPEFSCR not implemented */
9444 return 4;
9445 }
9446 return 0;
9447}
9448
aaed909a 9449int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9450{
9451 env->msr_mask = def->msr_mask;
9452 env->mmu_model = def->mmu_model;
9453 env->excp_model = def->excp_model;
9454 env->bus_model = def->bus_model;
d26bfc9a 9455 env->flags = def->flags;
237c0af0 9456 env->bfd_mach = def->bfd_mach;
2f462816 9457 env->check_pow = def->check_pow;
a750fc0b
JM		 9458 if (create_ppc_opcodes(env, def) < 0)
9459 return -1;
9460 init_ppc_proc(env, def);
24951522
AJ		 9461
9462 if (def->insns_flags & PPC_FLOAT) {
9463 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9464 33, "power-fpu.xml", 0);
9465 }
b4f8d821
AJ		 9466 if (def->insns_flags & PPC_ALTIVEC) {
9467 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9468 34, "power-altivec.xml", 0);
9469 }
40569b7e 9470 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9471 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9472 34, "power-spe.xml", 0);
9473 }
9474
a750fc0b 9475#if defined(PPC_DUMP_CPU)
3a607854 9476 {
b55266b5 9477 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9478 switch (env->mmu_model) {
9479 case POWERPC_MMU_32B:
9480 mmu_model = "PowerPC 32";
9481 break;
a750fc0b
JM		 9482 case POWERPC_MMU_SOFT_6xx:
9483 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9484 break;
9485 case POWERPC_MMU_SOFT_74xx:
9486 mmu_model = "PowerPC 74xx with software driven TLBs";
9487 break;
9488 case POWERPC_MMU_SOFT_4xx:
9489 mmu_model = "PowerPC 4xx with software driven TLBs";
9490 break;
9491 case POWERPC_MMU_SOFT_4xx_Z:
9492 mmu_model = "PowerPC 4xx with software driven TLBs "
9493 "and zones protections";
9494 break;
b4095fed
JM		 9495 case POWERPC_MMU_REAL:
9496 mmu_model = "PowerPC real mode only";
9497 break;
9498 case POWERPC_MMU_MPC8xx:
9499 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9500 break;
9501 case POWERPC_MMU_BOOKE:
9502 mmu_model = "PowerPC BookE";
9503 break;
9504 case POWERPC_MMU_BOOKE_FSL:
9505 mmu_model = "PowerPC BookE FSL";
9506 break;
b4095fed
JM		 9507 case POWERPC_MMU_601:
9508 mmu_model = "PowerPC 601";
9509 break;
00af685f
JM		 9510#if defined (TARGET_PPC64)
9511 case POWERPC_MMU_64B:
9512 mmu_model = "PowerPC 64";
9513 break;
add78955
JM		 9514 case POWERPC_MMU_620:
9515 mmu_model = "PowerPC 620";
9516 break;
00af685f 9517#endif
a750fc0b
JM		 9518 default:
9519 mmu_model = "Unknown or invalid";
9520 break;
9521 }
9522 switch (env->excp_model) {
9523 case POWERPC_EXCP_STD:
9524 excp_model = "PowerPC";
9525 break;
9526 case POWERPC_EXCP_40x:
9527 excp_model = "PowerPC 40x";
9528 break;
9529 case POWERPC_EXCP_601:
9530 excp_model = "PowerPC 601";
9531 break;
9532 case POWERPC_EXCP_602:
9533 excp_model = "PowerPC 602";
9534 break;
9535 case POWERPC_EXCP_603:
9536 excp_model = "PowerPC 603";
9537 break;
9538 case POWERPC_EXCP_603E:
9539 excp_model = "PowerPC 603e";
9540 break;
9541 case POWERPC_EXCP_604:
9542 excp_model = "PowerPC 604";
9543 break;
9544 case POWERPC_EXCP_7x0:
9545 excp_model = "PowerPC 740/750";
9546 break;
9547 case POWERPC_EXCP_7x5:
9548 excp_model = "PowerPC 745/755";
9549 break;
9550 case POWERPC_EXCP_74xx:
9551 excp_model = "PowerPC 74xx";
9552 break;
a750fc0b
JM		 9553 case POWERPC_EXCP_BOOKE:
9554 excp_model = "PowerPC BookE";
9555 break;
00af685f
JM		 9556#if defined (TARGET_PPC64)
9557 case POWERPC_EXCP_970:
9558 excp_model = "PowerPC 970";
9559 break;
9560#endif
a750fc0b
JM		 9561 default:
9562 excp_model = "Unknown or invalid";
9563 break;
9564 }
9565 switch (env->bus_model) {
9566 case PPC_FLAGS_INPUT_6xx:
9567 bus_model = "PowerPC 6xx";
9568 break;
9569 case PPC_FLAGS_INPUT_BookE:
9570 bus_model = "PowerPC BookE";
9571 break;
9572 case PPC_FLAGS_INPUT_405:
9573 bus_model = "PowerPC 405";
9574 break;
a750fc0b
JM		 9575 case PPC_FLAGS_INPUT_401:
9576 bus_model = "PowerPC 401/403";
9577 break;
b4095fed
JM		 9578 case PPC_FLAGS_INPUT_RCPU:
9579 bus_model = "RCPU / MPC8xx";
9580 break;
00af685f
JM		 9581#if defined (TARGET_PPC64)
9582 case PPC_FLAGS_INPUT_970:
9583 bus_model = "PowerPC 970";
9584 break;
9585#endif
a750fc0b
JM		 9586 default:
9587 bus_model = "Unknown or invalid";
9588 break;
9589 }
9590 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9591 " MMU model : %s\n",
9592 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9593#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9594 if (env->tlb != NULL) {
9595 printf(" %d %s TLB in %d ways\n",
9596 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9597 env->nb_ways);
9598 }
f2e63a42 9599#endif
a750fc0b
JM		 9600 printf(" Exceptions model : %s\n"
9601 " Bus model : %s\n",
9602 excp_model, bus_model);
25ba3a68
JM		 9603 printf(" MSR features :\n");
9604 if (env->flags & POWERPC_FLAG_SPE)
9605 printf(" signal processing engine enable"
9606 "\n");
9607 else if (env->flags & POWERPC_FLAG_VRE)
9608 printf(" vector processor enable\n");
9609 if (env->flags & POWERPC_FLAG_TGPR)
9610 printf(" temporary GPRs\n");
9611 else if (env->flags & POWERPC_FLAG_CE)
9612 printf(" critical input enable\n");
9613 if (env->flags & POWERPC_FLAG_SE)
9614 printf(" single-step trace mode\n");
9615 else if (env->flags & POWERPC_FLAG_DWE)
9616 printf(" debug wait enable\n");
9617 else if (env->flags & POWERPC_FLAG_UBLE)
9618 printf(" user BTB lock enable\n");
9619 if (env->flags & POWERPC_FLAG_BE)
9620 printf(" branch-step trace mode\n");
9621 else if (env->flags & POWERPC_FLAG_DE)
9622 printf(" debug interrupt enable\n");
9623 if (env->flags & POWERPC_FLAG_PX)
9624 printf(" inclusive protection\n");
9625 else if (env->flags & POWERPC_FLAG_PMM)
9626 printf(" performance monitor mark\n");
9627 if (env->flags == POWERPC_FLAG_NONE)
9628 printf(" none\n");
4018bae9
JM		 9629 printf(" Time-base/decrementer clock source: %s\n",
9630 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9631 }
9632 dump_ppc_insns(env);
9633 dump_ppc_sprs(env);
9634 fflush(stdout);
3a607854 9635#endif
a750fc0b
JM		 9636
9637 return 0;
9638}
3fc6c082 9639
ee4e83ed 9640static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9641{
ee4e83ed
JM		 9642 const ppc_def_t *ret;
9643 uint32_t pvr_rev;
9644 int i, best, match, best_match, max;
3fc6c082 9645
ee4e83ed 9646 ret = NULL;
b1503cda 9647 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9648 best = -1;
9649 pvr_rev = pvr & 0xFFFF;
9650 /* We want all specified bits to match */
9651 best_match = 32 - ctz32(pvr_rev);
068abdc8 9652 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9653 /* We check that the 16 higher bits are the same to ensure the CPU
9654 * model will be the choosen one.
9655 */
9656 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9657 /* We want as much as possible of the low-level 16 bits
9658 * to be the same but we allow inexact matches.
9659 */
9660 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9661 /* We check '>=' instead of '>' because the PPC_defs table
9662 * is ordered by increasing revision.
4c1b1bfe 9663 * Then, we will match the higher revision compatible
ee4e83ed
JM		 9664 * with the requested PVR
9665 */
9666 if (match >= best_match) {
9667 best = i;
9668 best_match = match;
9669 }
3fc6c082
FB		 9670 }
9671 }
ee4e83ed
JM		 9672 if (best != -1)
9673 ret = &ppc_defs[best];
9674
9675 return ret;
3fc6c082
FB		 9676}
9677
ee4e83ed 9678#include <ctype.h>
3fc6c082 9679
b55266b5 9680const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed
JM		 9681{
9682 const ppc_def_t *ret;
b55266b5 9683 const char *p;
ee4e83ed
JM		 9684 int i, max, len;
9685
9686 /* Check if the given name is a PVR */
9687 len = strlen(name);
9688 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9689 p = name + 2;
9690 goto check_pvr;
9691 } else if (len == 8) {
9692 p = name;
9693 check_pvr:
9694 for (i = 0; i < 8; i++) {
cd390083 9695 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 9696 break;
9697 }
9698 if (i == 8)
9699 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9700 }
9701 ret = NULL;
b1503cda 9702 max = ARRAY_SIZE(ppc_defs);
068abdc8 9703 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9704 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9705 ret = &ppc_defs[i];
9706 break;
3fc6c082
FB		 9707 }
9708 }
ee4e83ed
JM		 9709
9710 return ret;
3fc6c082
FB		 9711}
9712
9713void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9714{
068abdc8 9715 int i, max;
3fc6c082 9716
b1503cda 9717 max = ARRAY_SIZE(ppc_defs);
068abdc8 9718 for (i = 0; i < max; i++) {
a750fc0b
JM		 9719 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9720 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 9721 }
9722}
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