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3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0
JM		 26#include "dis-asm.h"
27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
a496775f 30//#define PPC_DEBUG_IRQ
3fc6c082
FB		 31
32struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
0487d6a8 36 uint64_t insns_flags;
3fc6c082 37 uint64_t msr_mask;
a750fc0b
JM		 38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
237c0af0 42 int bfd_mach;
a750fc0b 43 void (*init_proc)(CPUPPCState *env);
3fc6c082
FB		 44};
45
e9df014c
JM		 46/* For user-mode emulation, we don't emulate any IRQ controller */
47#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 48#define PPC_IRQ_INIT_FN(name) \
49static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
50{ \
e9df014c
JM		 51}
52#else
a750fc0b 53#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 54void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
55#endif
a750fc0b 56
4e290a0b 57PPC_IRQ_INIT_FN(40x);
e9df014c 58PPC_IRQ_INIT_FN(6xx);
d0dfae6e 59PPC_IRQ_INIT_FN(970);
e9df014c 60
3fc6c082
FB		 61/* Generic callbacks:
62 * do nothing but store/retrieve spr value
63 */
04f20795 64#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 65static void spr_read_generic (void *opaque, int sprn)
66{
04f20795 67 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 68}
69
70static void spr_write_generic (void *opaque, int sprn)
71{
04f20795 72 gen_op_store_dump_spr(sprn);
3fc6c082 73}
04f20795
JM		 74#else
75static void spr_read_generic (void *opaque, int sprn)
a496775f 76{
04f20795 77 gen_op_load_spr(sprn);
a496775f
JM		 78}
79
04f20795 80static void spr_write_generic (void *opaque, int sprn)
a496775f 81{
04f20795 82 gen_op_store_spr(sprn);
a496775f 83}
04f20795 84#endif
a496775f
JM		 85
86#if !defined(CONFIG_USER_ONLY)
87static void spr_write_clear (void *opaque, int sprn)
88{
89 gen_op_mask_spr(sprn);
90}
91#endif
92
76a66253 93/* SPR common to all PowerPC */
3fc6c082
FB		 94/* XER */
95static void spr_read_xer (void *opaque, int sprn)
96{
97 gen_op_load_xer();
98}
99
100static void spr_write_xer (void *opaque, int sprn)
101{
102 gen_op_store_xer();
103}
104
105/* LR */
106static void spr_read_lr (void *opaque, int sprn)
107{
108 gen_op_load_lr();
109}
110
111static void spr_write_lr (void *opaque, int sprn)
112{
113 gen_op_store_lr();
114}
115
116/* CTR */
117static void spr_read_ctr (void *opaque, int sprn)
118{
119 gen_op_load_ctr();
120}
121
122static void spr_write_ctr (void *opaque, int sprn)
123{
124 gen_op_store_ctr();
125}
126
127/* User read access to SPR */
128/* USPRx */
129/* UMMCRx */
130/* UPMCx */
131/* USIA */
132/* UDECR */
133static void spr_read_ureg (void *opaque, int sprn)
134{
135 gen_op_load_spr(sprn + 0x10);
136}
137
76a66253 138/* SPR common to all non-embedded PowerPC */
3fc6c082 139/* DECR */
76a66253 140#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 141static void spr_read_decr (void *opaque, int sprn)
142{
143 gen_op_load_decr();
144}
145
146static void spr_write_decr (void *opaque, int sprn)
147{
148 gen_op_store_decr();
149}
76a66253 150#endif
3fc6c082 151
76a66253 152/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 153/* Time base */
154static void spr_read_tbl (void *opaque, int sprn)
155{
156 gen_op_load_tbl();
157}
158
76a66253 159static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 160{
76a66253 161 gen_op_load_tbu();
3fc6c082
FB		 162}
163
a062e36c
JM		 164__attribute__ (( unused ))
165static void spr_read_atbl (void *opaque, int sprn)
166{
167 gen_op_load_atbl();
168}
169
170__attribute__ (( unused ))
171static void spr_read_atbu (void *opaque, int sprn)
172{
173 gen_op_load_atbu();
174}
175
76a66253
JM		 176#if !defined(CONFIG_USER_ONLY)
177static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 178{
76a66253 179 gen_op_store_tbl();
3fc6c082
FB		 180}
181
182static void spr_write_tbu (void *opaque, int sprn)
183{
184 gen_op_store_tbu();
185}
a062e36c
JM		 186
187__attribute__ (( unused ))
188static void spr_write_atbl (void *opaque, int sprn)
189{
190 gen_op_store_atbl();
191}
192
193__attribute__ (( unused ))
194static void spr_write_atbu (void *opaque, int sprn)
195{
196 gen_op_store_atbu();
197}
76a66253 198#endif
3fc6c082 199
76a66253 200#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 201/* IBAT0U...IBAT0U */
202/* IBAT0L...IBAT7L */
203static void spr_read_ibat (void *opaque, int sprn)
204{
205 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
206}
207
208static void spr_read_ibat_h (void *opaque, int sprn)
209{
210 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
211}
212
213static void spr_write_ibatu (void *opaque, int sprn)
214{
3fc6c082 215 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 216}
217
218static void spr_write_ibatu_h (void *opaque, int sprn)
219{
3fc6c082 220 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 221}
222
223static void spr_write_ibatl (void *opaque, int sprn)
224{
3fc6c082 225 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 226}
227
228static void spr_write_ibatl_h (void *opaque, int sprn)
229{
3fc6c082 230 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 231}
232
233/* DBAT0U...DBAT7U */
234/* DBAT0L...DBAT7L */
235static void spr_read_dbat (void *opaque, int sprn)
236{
237 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
238}
239
240static void spr_read_dbat_h (void *opaque, int sprn)
241{
242 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
243}
244
245static void spr_write_dbatu (void *opaque, int sprn)
246{
3fc6c082 247 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 248}
249
250static void spr_write_dbatu_h (void *opaque, int sprn)
251{
3fc6c082 252 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
3fc6c082
FB		 253}
254
255static void spr_write_dbatl (void *opaque, int sprn)
256{
3fc6c082 257 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 258}
259
260static void spr_write_dbatl_h (void *opaque, int sprn)
261{
3fc6c082 262 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
3fc6c082
FB		 263}
264
265/* SDR1 */
266static void spr_read_sdr1 (void *opaque, int sprn)
267{
268 gen_op_load_sdr1();
269}
270
271static void spr_write_sdr1 (void *opaque, int sprn)
272{
3fc6c082 273 gen_op_store_sdr1();
3fc6c082
FB		 274}
275
76a66253
JM		 276/* 64 bits PowerPC specific SPRs */
277/* ASR */
578bb252
JM		 278#if defined(TARGET_PPC64)
279__attribute__ (( unused ))
76a66253
JM		 280static void spr_read_asr (void *opaque, int sprn)
281{
282 gen_op_load_asr();
283}
284
578bb252 285__attribute__ (( unused ))
76a66253
JM		 286static void spr_write_asr (void *opaque, int sprn)
287{
76a66253 288 gen_op_store_asr();
76a66253
JM		 289}
290#endif
a750fc0b 291#endif
76a66253
JM		 292
293/* PowerPC 601 specific registers */
294/* RTC */
295static void spr_read_601_rtcl (void *opaque, int sprn)
296{
297 gen_op_load_601_rtcl();
298}
299
300static void spr_read_601_rtcu (void *opaque, int sprn)
301{
302 gen_op_load_601_rtcu();
303}
304
305#if !defined(CONFIG_USER_ONLY)
306static void spr_write_601_rtcu (void *opaque, int sprn)
307{
308 gen_op_store_601_rtcu();
309}
310
311static void spr_write_601_rtcl (void *opaque, int sprn)
312{
313 gen_op_store_601_rtcl();
314}
315#endif
316
317/* Unified bats */
318#if !defined(CONFIG_USER_ONLY)
319static void spr_read_601_ubat (void *opaque, int sprn)
320{
321 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
322}
323
324static void spr_write_601_ubatu (void *opaque, int sprn)
325{
76a66253 326 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 327}
328
329static void spr_write_601_ubatl (void *opaque, int sprn)
330{
76a66253 331 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 332}
333#endif
334
335/* PowerPC 40x specific registers */
336#if !defined(CONFIG_USER_ONLY)
337static void spr_read_40x_pit (void *opaque, int sprn)
338{
339 gen_op_load_40x_pit();
340}
341
342static void spr_write_40x_pit (void *opaque, int sprn)
343{
344 gen_op_store_40x_pit();
345}
346
8ecc7913
JM		 347static void spr_write_40x_dbcr0 (void *opaque, int sprn)
348{
349 DisasContext *ctx = opaque;
350
351 gen_op_store_40x_dbcr0();
352 /* We must stop translation as we may have rebooted */
e1833e1f 353 GEN_STOP(ctx);
8ecc7913
JM		 354}
355
c294fc58
JM		 356static void spr_write_40x_sler (void *opaque, int sprn)
357{
c294fc58 358 gen_op_store_40x_sler();
c294fc58
JM		 359}
360
76a66253
JM		 361static void spr_write_booke_tcr (void *opaque, int sprn)
362{
363 gen_op_store_booke_tcr();
364}
365
366static void spr_write_booke_tsr (void *opaque, int sprn)
367{
368 gen_op_store_booke_tsr();
369}
370#endif
371
372/* PowerPC 403 specific registers */
373/* PBL1 / PBU1 / PBL2 / PBU2 */
374#if !defined(CONFIG_USER_ONLY)
375static void spr_read_403_pbr (void *opaque, int sprn)
376{
377 gen_op_load_403_pb(sprn - SPR_403_PBL1);
378}
379
380static void spr_write_403_pbr (void *opaque, int sprn)
381{
76a66253 382 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 383}
384
3fc6c082
FB		 385static void spr_write_pir (void *opaque, int sprn)
386{
387 gen_op_store_pir();
388}
76a66253 389#endif
3fc6c082 390
6f5d427d
JM		 391#if !defined(CONFIG_USER_ONLY)
392/* Callback used to write the exception vector base */
393static void spr_write_excp_prefix (void *opaque, int sprn)
394{
395 gen_op_store_excp_prefix();
396 gen_op_store_spr(sprn);
397}
398
399static void spr_write_excp_vector (void *opaque, int sprn)
400{
401 DisasContext *ctx = opaque;
402
403 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
404 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
405 gen_op_store_spr(sprn);
406 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
407 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
408 gen_op_store_spr(sprn);
409 } else {
410 printf("Trying to write an unknown exception vector %d %03x\n",
411 sprn, sprn);
412 GEN_EXCP_PRIVREG(ctx);
413 }
414}
415#endif
416
76a66253
JM		 417#if defined(CONFIG_USER_ONLY)
418#define spr_register(env, num, name, uea_read, uea_write, \
419 oea_read, oea_write, initial_value) \
420do { \
421 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
422} while (0)
423static inline void _spr_register (CPUPPCState *env, int num,
424 const unsigned char *name,
425 void (*uea_read)(void *opaque, int sprn),
426 void (*uea_write)(void *opaque, int sprn),
427 target_ulong initial_value)
428#else
3fc6c082
FB		 429static inline void spr_register (CPUPPCState *env, int num,
430 const unsigned char *name,
431 void (*uea_read)(void *opaque, int sprn),
432 void (*uea_write)(void *opaque, int sprn),
433 void (*oea_read)(void *opaque, int sprn),
434 void (*oea_write)(void *opaque, int sprn),
435 target_ulong initial_value)
76a66253 436#endif
3fc6c082
FB		 437{
438 ppc_spr_t *spr;
439
440 spr = &env->spr_cb[num];
441 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 442#if !defined(CONFIG_USER_ONLY)
443 spr->oea_read != NULL || spr->oea_write != NULL ||
444#endif
445 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 446 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
447 exit(1);
448 }
449#if defined(PPC_DEBUG_SPR)
1b9eb036 450 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 451 initial_value);
3fc6c082
FB		 452#endif
453 spr->name = name;
454 spr->uea_read = uea_read;
455 spr->uea_write = uea_write;
76a66253 456#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 457 spr->oea_read = oea_read;
458 spr->oea_write = oea_write;
76a66253 459#endif
3fc6c082
FB		 460 env->spr[num] = initial_value;
461}
462
463/* Generic PowerPC SPRs */
464static void gen_spr_generic (CPUPPCState *env)
465{
466 /* Integer processing */
467 spr_register(env, SPR_XER, "XER",
468 &spr_read_xer, &spr_write_xer,
469 &spr_read_xer, &spr_write_xer,
470 0x00000000);
471 /* Branch contol */
472 spr_register(env, SPR_LR, "LR",
473 &spr_read_lr, &spr_write_lr,
474 &spr_read_lr, &spr_write_lr,
475 0x00000000);
476 spr_register(env, SPR_CTR, "CTR",
477 &spr_read_ctr, &spr_write_ctr,
478 &spr_read_ctr, &spr_write_ctr,
479 0x00000000);
480 /* Interrupt processing */
481 spr_register(env, SPR_SRR0, "SRR0",
482 SPR_NOACCESS, SPR_NOACCESS,
483 &spr_read_generic, &spr_write_generic,
484 0x00000000);
485 spr_register(env, SPR_SRR1, "SRR1",
486 SPR_NOACCESS, SPR_NOACCESS,
487 &spr_read_generic, &spr_write_generic,
488 0x00000000);
489 /* Processor control */
490 spr_register(env, SPR_SPRG0, "SPRG0",
491 SPR_NOACCESS, SPR_NOACCESS,
492 &spr_read_generic, &spr_write_generic,
493 0x00000000);
494 spr_register(env, SPR_SPRG1, "SPRG1",
495 SPR_NOACCESS, SPR_NOACCESS,
496 &spr_read_generic, &spr_write_generic,
497 0x00000000);
498 spr_register(env, SPR_SPRG2, "SPRG2",
499 SPR_NOACCESS, SPR_NOACCESS,
500 &spr_read_generic, &spr_write_generic,
501 0x00000000);
502 spr_register(env, SPR_SPRG3, "SPRG3",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506}
507
508/* SPR common to all non-embedded PowerPC, including 601 */
509static void gen_spr_ne_601 (CPUPPCState *env)
510{
511 /* Exception processing */
512 spr_register(env, SPR_DSISR, "DSISR",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516 spr_register(env, SPR_DAR, "DAR",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520 /* Timer */
521 spr_register(env, SPR_DECR, "DECR",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_decr, &spr_write_decr,
524 0x00000000);
525 /* Memory management */
526 spr_register(env, SPR_SDR1, "SDR1",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_sdr1, &spr_write_sdr1,
529 0x00000000);
530}
531
532/* BATs 0-3 */
533static void gen_low_BATs (CPUPPCState *env)
534{
535 spr_register(env, SPR_IBAT0U, "IBAT0U",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_ibat, &spr_write_ibatu,
538 0x00000000);
539 spr_register(env, SPR_IBAT0L, "IBAT0L",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_ibat, &spr_write_ibatl,
542 0x00000000);
543 spr_register(env, SPR_IBAT1U, "IBAT1U",
544 SPR_NOACCESS, SPR_NOACCESS,
545 &spr_read_ibat, &spr_write_ibatu,
546 0x00000000);
547 spr_register(env, SPR_IBAT1L, "IBAT1L",
548 SPR_NOACCESS, SPR_NOACCESS,
549 &spr_read_ibat, &spr_write_ibatl,
550 0x00000000);
551 spr_register(env, SPR_IBAT2U, "IBAT2U",
552 SPR_NOACCESS, SPR_NOACCESS,
553 &spr_read_ibat, &spr_write_ibatu,
554 0x00000000);
555 spr_register(env, SPR_IBAT2L, "IBAT2L",
556 SPR_NOACCESS, SPR_NOACCESS,
557 &spr_read_ibat, &spr_write_ibatl,
558 0x00000000);
559 spr_register(env, SPR_IBAT3U, "IBAT3U",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_ibat, &spr_write_ibatu,
562 0x00000000);
563 spr_register(env, SPR_IBAT3L, "IBAT3L",
564 SPR_NOACCESS, SPR_NOACCESS,
565 &spr_read_ibat, &spr_write_ibatl,
566 0x00000000);
567 spr_register(env, SPR_DBAT0U, "DBAT0U",
568 SPR_NOACCESS, SPR_NOACCESS,
569 &spr_read_dbat, &spr_write_dbatu,
570 0x00000000);
571 spr_register(env, SPR_DBAT0L, "DBAT0L",
572 SPR_NOACCESS, SPR_NOACCESS,
573 &spr_read_dbat, &spr_write_dbatl,
574 0x00000000);
575 spr_register(env, SPR_DBAT1U, "DBAT1U",
576 SPR_NOACCESS, SPR_NOACCESS,
577 &spr_read_dbat, &spr_write_dbatu,
578 0x00000000);
579 spr_register(env, SPR_DBAT1L, "DBAT1L",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_dbat, &spr_write_dbatl,
582 0x00000000);
583 spr_register(env, SPR_DBAT2U, "DBAT2U",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_dbat, &spr_write_dbatu,
586 0x00000000);
587 spr_register(env, SPR_DBAT2L, "DBAT2L",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_dbat, &spr_write_dbatl,
590 0x00000000);
591 spr_register(env, SPR_DBAT3U, "DBAT3U",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_dbat, &spr_write_dbatu,
594 0x00000000);
595 spr_register(env, SPR_DBAT3L, "DBAT3L",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_dbat, &spr_write_dbatl,
598 0x00000000);
a750fc0b 599 env->nb_BATs += 4;
3fc6c082
FB		 600}
601
602/* BATs 4-7 */
603static void gen_high_BATs (CPUPPCState *env)
604{
605 spr_register(env, SPR_IBAT4U, "IBAT4U",
606 SPR_NOACCESS, SPR_NOACCESS,
607 &spr_read_ibat_h, &spr_write_ibatu_h,
608 0x00000000);
609 spr_register(env, SPR_IBAT4L, "IBAT4L",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_ibat_h, &spr_write_ibatl_h,
612 0x00000000);
613 spr_register(env, SPR_IBAT5U, "IBAT5U",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_ibat_h, &spr_write_ibatu_h,
616 0x00000000);
617 spr_register(env, SPR_IBAT5L, "IBAT5L",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_ibat_h, &spr_write_ibatl_h,
620 0x00000000);
621 spr_register(env, SPR_IBAT6U, "IBAT6U",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_ibat_h, &spr_write_ibatu_h,
624 0x00000000);
625 spr_register(env, SPR_IBAT6L, "IBAT6L",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_ibat_h, &spr_write_ibatl_h,
628 0x00000000);
629 spr_register(env, SPR_IBAT7U, "IBAT7U",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_ibat_h, &spr_write_ibatu_h,
632 0x00000000);
633 spr_register(env, SPR_IBAT7L, "IBAT7L",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_ibat_h, &spr_write_ibatl_h,
636 0x00000000);
637 spr_register(env, SPR_DBAT4U, "DBAT4U",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_dbat_h, &spr_write_dbatu_h,
640 0x00000000);
641 spr_register(env, SPR_DBAT4L, "DBAT4L",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_dbat_h, &spr_write_dbatl_h,
644 0x00000000);
645 spr_register(env, SPR_DBAT5U, "DBAT5U",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_dbat_h, &spr_write_dbatu_h,
648 0x00000000);
649 spr_register(env, SPR_DBAT5L, "DBAT5L",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_dbat_h, &spr_write_dbatl_h,
652 0x00000000);
653 spr_register(env, SPR_DBAT6U, "DBAT6U",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_dbat_h, &spr_write_dbatu_h,
656 0x00000000);
657 spr_register(env, SPR_DBAT6L, "DBAT6L",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_dbat_h, &spr_write_dbatl_h,
660 0x00000000);
661 spr_register(env, SPR_DBAT7U, "DBAT7U",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_dbat_h, &spr_write_dbatu_h,
664 0x00000000);
665 spr_register(env, SPR_DBAT7L, "DBAT7L",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_dbat_h, &spr_write_dbatl_h,
668 0x00000000);
a750fc0b 669 env->nb_BATs += 4;
3fc6c082
FB		 670}
671
672/* Generic PowerPC time base */
673static void gen_tbl (CPUPPCState *env)
674{
675 spr_register(env, SPR_VTBL, "TBL",
676 &spr_read_tbl, SPR_NOACCESS,
677 &spr_read_tbl, SPR_NOACCESS,
678 0x00000000);
679 spr_register(env, SPR_TBL, "TBL",
680 SPR_NOACCESS, SPR_NOACCESS,
681 SPR_NOACCESS, &spr_write_tbl,
682 0x00000000);
683 spr_register(env, SPR_VTBU, "TBU",
684 &spr_read_tbu, SPR_NOACCESS,
685 &spr_read_tbu, SPR_NOACCESS,
686 0x00000000);
687 spr_register(env, SPR_TBU, "TBU",
688 SPR_NOACCESS, SPR_NOACCESS,
689 SPR_NOACCESS, &spr_write_tbu,
690 0x00000000);
691}
692
76a66253
JM		 693/* Softare table search registers */
694static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
695{
696 env->nb_tlb = nb_tlbs;
697 env->nb_ways = nb_ways;
698 env->id_tlbs = 1;
699 spr_register(env, SPR_DMISS, "DMISS",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, SPR_NOACCESS,
702 0x00000000);
703 spr_register(env, SPR_DCMP, "DCMP",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, SPR_NOACCESS,
706 0x00000000);
707 spr_register(env, SPR_HASH1, "HASH1",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, SPR_NOACCESS,
710 0x00000000);
711 spr_register(env, SPR_HASH2, "HASH2",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, SPR_NOACCESS,
714 0x00000000);
715 spr_register(env, SPR_IMISS, "IMISS",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, SPR_NOACCESS,
718 0x00000000);
719 spr_register(env, SPR_ICMP, "ICMP",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, SPR_NOACCESS,
722 0x00000000);
723 spr_register(env, SPR_RPA, "RPA",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, &spr_write_generic,
726 0x00000000);
727}
728
729/* SPR common to MPC755 and G2 */
730static void gen_spr_G2_755 (CPUPPCState *env)
731{
732 /* SGPRs */
733 spr_register(env, SPR_SPRG4, "SPRG4",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 0x00000000);
737 spr_register(env, SPR_SPRG5, "SPRG5",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
740 0x00000000);
741 spr_register(env, SPR_SPRG6, "SPRG6",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 spr_register(env, SPR_SPRG7, "SPRG7",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_generic, &spr_write_generic,
748 0x00000000);
749 /* External access control */
750 /* XXX : not implemented */
751 spr_register(env, SPR_EAR, "EAR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755}
756
3fc6c082
FB		 757/* SPR common to all 7xx PowerPC implementations */
758static void gen_spr_7xx (CPUPPCState *env)
759{
760 /* Breakpoints */
761 /* XXX : not implemented */
762 spr_register(env, SPR_DABR, "DABR",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_generic, &spr_write_generic,
765 0x00000000);
766 /* XXX : not implemented */
767 spr_register(env, SPR_IABR, "IABR",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_generic, &spr_write_generic,
770 0x00000000);
771 /* Cache management */
772 /* XXX : not implemented */
773 spr_register(env, SPR_ICTC, "ICTC",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_generic, &spr_write_generic,
776 0x00000000);
76a66253
JM		 777 /* XXX : not implemented */
778 spr_register(env, SPR_L2CR, "L2CR",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_generic,
781 0x00000000);
3fc6c082
FB		 782 /* Performance monitors */
783 /* XXX : not implemented */
784 spr_register(env, SPR_MMCR0, "MMCR0",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_generic,
787 0x00000000);
788 /* XXX : not implemented */
789 spr_register(env, SPR_MMCR1, "MMCR1",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_generic, &spr_write_generic,
792 0x00000000);
793 /* XXX : not implemented */
794 spr_register(env, SPR_PMC1, "PMC1",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
798 /* XXX : not implemented */
799 spr_register(env, SPR_PMC2, "PMC2",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_generic, &spr_write_generic,
802 0x00000000);
803 /* XXX : not implemented */
804 spr_register(env, SPR_PMC3, "PMC3",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 /* XXX : not implemented */
809 spr_register(env, SPR_PMC4, "PMC4",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_generic, &spr_write_generic,
812 0x00000000);
813 /* XXX : not implemented */
a750fc0b 814 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, SPR_NOACCESS,
817 0x00000000);
578bb252 818 /* XXX : not implemented */
3fc6c082
FB		 819 spr_register(env, SPR_UMMCR0, "UMMCR0",
820 &spr_read_ureg, SPR_NOACCESS,
821 &spr_read_ureg, SPR_NOACCESS,
822 0x00000000);
578bb252 823 /* XXX : not implemented */
3fc6c082
FB		 824 spr_register(env, SPR_UMMCR1, "UMMCR1",
825 &spr_read_ureg, SPR_NOACCESS,
826 &spr_read_ureg, SPR_NOACCESS,
827 0x00000000);
578bb252 828 /* XXX : not implemented */
3fc6c082
FB		 829 spr_register(env, SPR_UPMC1, "UPMC1",
830 &spr_read_ureg, SPR_NOACCESS,
831 &spr_read_ureg, SPR_NOACCESS,
832 0x00000000);
578bb252 833 /* XXX : not implemented */
3fc6c082
FB		 834 spr_register(env, SPR_UPMC2, "UPMC2",
835 &spr_read_ureg, SPR_NOACCESS,
836 &spr_read_ureg, SPR_NOACCESS,
837 0x00000000);
578bb252 838 /* XXX : not implemented */
3fc6c082
FB		 839 spr_register(env, SPR_UPMC3, "UPMC3",
840 &spr_read_ureg, SPR_NOACCESS,
841 &spr_read_ureg, SPR_NOACCESS,
842 0x00000000);
578bb252 843 /* XXX : not implemented */
3fc6c082
FB		 844 spr_register(env, SPR_UPMC4, "UPMC4",
845 &spr_read_ureg, SPR_NOACCESS,
846 &spr_read_ureg, SPR_NOACCESS,
847 0x00000000);
578bb252 848 /* XXX : not implemented */
a750fc0b 849 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 850 &spr_read_ureg, SPR_NOACCESS,
851 &spr_read_ureg, SPR_NOACCESS,
852 0x00000000);
a750fc0b 853 /* External access control */
3fc6c082 854 /* XXX : not implemented */
a750fc0b 855 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, &spr_write_generic,
858 0x00000000);
a750fc0b
JM		 859}
860
861static void gen_spr_thrm (CPUPPCState *env)
862{
863 /* Thermal management */
3fc6c082 864 /* XXX : not implemented */
a750fc0b 865 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_generic,
868 0x00000000);
869 /* XXX : not implemented */
a750fc0b 870 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, &spr_write_generic,
873 0x00000000);
3fc6c082 874 /* XXX : not implemented */
a750fc0b 875 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, &spr_write_generic,
878 0x00000000);
879}
880
881/* SPR specific to PowerPC 604 implementation */
882static void gen_spr_604 (CPUPPCState *env)
883{
884 /* Processor identification */
885 spr_register(env, SPR_PIR, "PIR",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_pir,
888 0x00000000);
889 /* Breakpoints */
890 /* XXX : not implemented */
891 spr_register(env, SPR_IABR, "IABR",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 /* XXX : not implemented */
896 spr_register(env, SPR_DABR, "DABR",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
900 /* Performance counters */
901 /* XXX : not implemented */
902 spr_register(env, SPR_MMCR0, "MMCR0",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 /* XXX : not implemented */
907 spr_register(env, SPR_MMCR1, "MMCR1",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_PMC1, "PMC1",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 /* XXX : not implemented */
917 spr_register(env, SPR_PMC2, "PMC2",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 /* XXX : not implemented */
922 spr_register(env, SPR_PMC3, "PMC3",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 /* XXX : not implemented */
927 spr_register(env, SPR_PMC4, "PMC4",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
a750fc0b 932 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, SPR_NOACCESS,
935 0x00000000);
936 /* XXX : not implemented */
937 spr_register(env, SPR_SDA, "SDA",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, SPR_NOACCESS,
940 0x00000000);
941 /* External access control */
942 /* XXX : not implemented */
943 spr_register(env, SPR_EAR, "EAR",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947}
948
76a66253
JM		 949/* SPR specific to PowerPC 603 implementation */
950static void gen_spr_603 (CPUPPCState *env)
3fc6c082 951{
76a66253
JM		 952 /* External access control */
953 /* XXX : not implemented */
954 spr_register(env, SPR_EAR, "EAR",
3fc6c082 955 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
3fc6c082
FB		 958}
959
76a66253
JM		 960/* SPR specific to PowerPC G2 implementation */
961static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 962{
76a66253
JM		 963 /* Memory base address */
964 /* MBAR */
578bb252 965 /* XXX : not implemented */
76a66253
JM		 966 spr_register(env, SPR_MBAR, "MBAR",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970 /* System version register */
971 /* SVR */
578bb252 972 /* XXX : TODO: initialize it to an appropriate value */
76a66253
JM		 973 spr_register(env, SPR_SVR, "SVR",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, SPR_NOACCESS,
976 0x00000000);
977 /* Exception processing */
363be49c 978 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 979 SPR_NOACCESS, SPR_NOACCESS,
980 &spr_read_generic, &spr_write_generic,
981 0x00000000);
363be49c 982 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 /* Breakpoints */
987 /* XXX : not implemented */
988 spr_register(env, SPR_DABR, "DABR",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_generic,
991 0x00000000);
992 /* XXX : not implemented */
993 spr_register(env, SPR_DABR2, "DABR2",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997 /* XXX : not implemented */
998 spr_register(env, SPR_IABR, "IABR",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_IABR2, "IABR2",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 /* XXX : not implemented */
1008 spr_register(env, SPR_IBCR, "IBCR",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_DBCR, "DBCR",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017}
1018
1019/* SPR specific to PowerPC 602 implementation */
1020static void gen_spr_602 (CPUPPCState *env)
1021{
1022 /* ESA registers */
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_SER, "SER",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1027 0x00000000);
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_SEBR, "SEBR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* XXX : not implemented */
a750fc0b 1034 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* Floating point status */
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_SP, "SP",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_LT, "LT",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* Watchdog timer */
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_TCR, "TCR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* Interrupt base */
1056 spr_register(env, SPR_IBR, "IBR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
a750fc0b
JM		 1060 /* XXX : not implemented */
1061 spr_register(env, SPR_IABR, "IABR",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
76a66253
JM		 1065}
1066
1067/* SPR specific to PowerPC 601 implementation */
1068static void gen_spr_601 (CPUPPCState *env)
1069{
1070 /* Multiplication/division register */
1071 /* MQ */
1072 spr_register(env, SPR_MQ, "MQ",
1073 &spr_read_generic, &spr_write_generic,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* RTC registers */
1077 spr_register(env, SPR_601_RTCU, "RTCU",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 SPR_NOACCESS, &spr_write_601_rtcu,
1080 0x00000000);
1081 spr_register(env, SPR_601_VRTCU, "RTCU",
1082 &spr_read_601_rtcu, SPR_NOACCESS,
1083 &spr_read_601_rtcu, SPR_NOACCESS,
1084 0x00000000);
1085 spr_register(env, SPR_601_RTCL, "RTCL",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 SPR_NOACCESS, &spr_write_601_rtcl,
1088 0x00000000);
1089 spr_register(env, SPR_601_VRTCL, "RTCL",
1090 &spr_read_601_rtcl, SPR_NOACCESS,
1091 &spr_read_601_rtcl, SPR_NOACCESS,
1092 0x00000000);
1093 /* Timer */
1094#if 0 /* ? */
1095 spr_register(env, SPR_601_UDECR, "UDECR",
1096 &spr_read_decr, SPR_NOACCESS,
1097 &spr_read_decr, SPR_NOACCESS,
1098 0x00000000);
1099#endif
1100 /* External access control */
1101 /* XXX : not implemented */
1102 spr_register(env, SPR_EAR, "EAR",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 /* Memory management */
1107 spr_register(env, SPR_IBAT0U, "IBAT0U",
1108 SPR_NOACCESS, SPR_NOACCESS,
1109 &spr_read_601_ubat, &spr_write_601_ubatu,
1110 0x00000000);
1111 spr_register(env, SPR_IBAT0L, "IBAT0L",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_601_ubat, &spr_write_601_ubatl,
1114 0x00000000);
1115 spr_register(env, SPR_IBAT1U, "IBAT1U",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_601_ubat, &spr_write_601_ubatu,
1118 0x00000000);
1119 spr_register(env, SPR_IBAT1L, "IBAT1L",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_601_ubat, &spr_write_601_ubatl,
1122 0x00000000);
1123 spr_register(env, SPR_IBAT2U, "IBAT2U",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_601_ubat, &spr_write_601_ubatu,
1126 0x00000000);
1127 spr_register(env, SPR_IBAT2L, "IBAT2L",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_601_ubat, &spr_write_601_ubatl,
1130 0x00000000);
1131 spr_register(env, SPR_IBAT3U, "IBAT3U",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_601_ubat, &spr_write_601_ubatu,
1134 0x00000000);
1135 spr_register(env, SPR_IBAT3L, "IBAT3L",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_601_ubat, &spr_write_601_ubatl,
1138 0x00000000);
a750fc0b
JM		 1139 env->nb_BATs = 4;
1140}
1141
1142static void gen_spr_74xx (CPUPPCState *env)
1143{
1144 /* Processor identification */
1145 spr_register(env, SPR_PIR, "PIR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_pir,
1148 0x00000000);
1149 /* XXX : not implemented */
1150 spr_register(env, SPR_MMCR2, "MMCR2",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00000000);
578bb252 1154 /* XXX : not implemented */
a750fc0b
JM		 1155 spr_register(env, SPR_UMMCR2, "UMMCR2",
1156 &spr_read_ureg, SPR_NOACCESS,
1157 &spr_read_ureg, SPR_NOACCESS,
1158 0x00000000);
1159 /* XXX: not implemented */
1160 spr_register(env, SPR_BAMR, "BAMR",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
578bb252 1164 /* XXX : not implemented */
a750fc0b
JM		 1165 spr_register(env, SPR_UBAMR, "UBAMR",
1166 &spr_read_ureg, SPR_NOACCESS,
1167 &spr_read_ureg, SPR_NOACCESS,
1168 0x00000000);
578bb252 1169 /* XXX : not implemented */
a750fc0b
JM		 1170 spr_register(env, SPR_MSSCR0, "MSSCR0",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
1174 /* Hardware implementation registers */
1175 /* XXX : not implemented */
1176 spr_register(env, SPR_HID0, "HID0",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 /* XXX : not implemented */
1181 spr_register(env, SPR_HID1, "HID1",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 /* Altivec */
1186 spr_register(env, SPR_VRSAVE, "VRSAVE",
1187 &spr_read_generic, &spr_write_generic,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190}
1191
a750fc0b
JM		 1192static void gen_l3_ctrl (CPUPPCState *env)
1193{
1194 /* L3CR */
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_L3CR, "L3CR",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* L3ITCR0 */
578bb252 1201 /* XXX : not implemented */
a750fc0b
JM		 1202 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* L3ITCR1 */
578bb252 1207 /* XXX : not implemented */
a750fc0b
JM		 1208 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic, &spr_write_generic,
1211 0x00000000);
1212 /* L3ITCR2 */
578bb252 1213 /* XXX : not implemented */
a750fc0b
JM		 1214 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
1218 /* L3ITCR3 */
578bb252 1219 /* XXX : not implemented */
a750fc0b
JM		 1220 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* L3OHCR */
578bb252 1225 /* XXX : not implemented */
a750fc0b
JM		 1226 spr_register(env, SPR_L3OHCR, "L3OHCR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 /* L3PM */
578bb252 1231 /* XXX : not implemented */
a750fc0b
JM		 1232 spr_register(env, SPR_L3PM, "L3PM",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236}
a750fc0b 1237
578bb252 1238static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1239{
578bb252
JM		 1240 env->nb_tlb = nb_tlbs;
1241 env->nb_ways = nb_ways;
1242 env->id_tlbs = 1;
1243 /* XXX : not implemented */
a750fc0b
JM		 1244 spr_register(env, SPR_PTEHI, "PTEHI",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_generic, &spr_write_generic,
1247 0x00000000);
578bb252 1248 /* XXX : not implemented */
a750fc0b
JM		 1249 spr_register(env, SPR_PTELO, "PTELO",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0x00000000);
578bb252 1253 /* XXX : not implemented */
a750fc0b
JM		 1254 spr_register(env, SPR_TLBMISS, "TLBMISS",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
76a66253
JM		 1258}
1259
1260/* PowerPC BookE SPR */
1261static void gen_spr_BookE (CPUPPCState *env)
1262{
1263 /* Processor identification */
1264 spr_register(env, SPR_BOOKE_PIR, "PIR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_pir,
1267 0x00000000);
1268 /* Interrupt processing */
363be49c 1269 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
363be49c
JM		 1273 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_generic, &spr_write_generic,
1276 0x00000000);
2662a059 1277#if 0
363be49c
JM		 1278 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
2662a059 1286#endif
76a66253
JM		 1287 /* Debug */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 /* XXX : not implemented */
1334 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1345 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1346 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1347 0x00000000);
1348 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 spr_register(env, SPR_BOOKE_ESR, "ESR",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
363be49c
JM		 1356 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1357 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1358 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1359 0x00000000);
1360 /* Exception vectors */
76a66253
JM		 1361 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1362 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1363 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1364 0x00000000);
1365 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1366 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1367 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1368 0x00000000);
1369 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1370 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1371 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1372 0x00000000);
1373 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1374 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1375 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1376 0x00000000);
1377 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1378 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1379 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1380 0x00000000);
1381 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1382 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1383 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1384 0x00000000);
1385 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1386 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1387 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1388 0x00000000);
1389 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1390 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1391 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1394 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1395 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1396 0x00000000);
1397 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1398 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1399 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1400 0x00000000);
1401 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1402 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1403 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1404 0x00000000);
1405 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1406 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1407 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1408 0x00000000);
1409 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1410 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1411 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1412 0x00000000);
1413 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1414 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1415 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1416 0x00000000);
1417 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1418 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1419 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1420 0x00000000);
1421 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1422 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1423 &spr_read_generic, &spr_write_excp_vector,
76a66253 1424 0x00000000);
2662a059 1425#if 0
363be49c
JM		 1426 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1427 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1428 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1429 0x00000000);
1430 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1431 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1432 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1433 0x00000000);
1434 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1435 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1436 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1437 0x00000000);
1438 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1439 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1440 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1441 0x00000000);
1442 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1443 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1444 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1445 0x00000000);
1446 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1447 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1448 &spr_read_generic, &spr_write_excp_vector,
363be49c 1449 0x00000000);
2662a059 1450#endif
76a66253
JM		 1451 spr_register(env, SPR_BOOKE_PID, "PID",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, &spr_write_generic,
1454 0x00000000);
1455 spr_register(env, SPR_BOOKE_TCR, "TCR",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_booke_tcr,
1458 0x00000000);
1459 spr_register(env, SPR_BOOKE_TSR, "TSR",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_booke_tsr,
1462 0x00000000);
1463 /* Timer */
1464 spr_register(env, SPR_DECR, "DECR",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_decr, &spr_write_decr,
1467 0x00000000);
1468 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 SPR_NOACCESS, &spr_write_generic,
1471 0x00000000);
1472 /* SPRGs */
1473 spr_register(env, SPR_USPRG0, "USPRG0",
1474 &spr_read_generic, &spr_write_generic,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 spr_register(env, SPR_SPRG4, "SPRG4",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1480 0x00000000);
1481 spr_register(env, SPR_USPRG4, "USPRG4",
1482 &spr_read_ureg, SPR_NOACCESS,
1483 &spr_read_ureg, SPR_NOACCESS,
1484 0x00000000);
1485 spr_register(env, SPR_SPRG5, "SPRG5",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 spr_register(env, SPR_USPRG5, "USPRG5",
1490 &spr_read_ureg, SPR_NOACCESS,
1491 &spr_read_ureg, SPR_NOACCESS,
1492 0x00000000);
1493 spr_register(env, SPR_SPRG6, "SPRG6",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 spr_register(env, SPR_USPRG6, "USPRG6",
1498 &spr_read_ureg, SPR_NOACCESS,
1499 &spr_read_ureg, SPR_NOACCESS,
1500 0x00000000);
1501 spr_register(env, SPR_SPRG7, "SPRG7",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 spr_register(env, SPR_USPRG7, "USPRG7",
1506 &spr_read_ureg, SPR_NOACCESS,
1507 &spr_read_ureg, SPR_NOACCESS,
1508 0x00000000);
1509}
1510
363be49c
JM		 1511/* FSL storage control registers */
1512static void gen_spr_BookE_FSL (CPUPPCState *env)
1513{
1514 /* TLB assist registers */
578bb252 1515 /* XXX : not implemented */
363be49c
JM		 1516 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
578bb252 1520 /* XXX : not implemented */
363be49c
JM		 1521 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
578bb252 1525 /* XXX : not implemented */
363be49c
JM		 1526 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_generic,
1529 0x00000000);
578bb252 1530 /* XXX : not implemented */
363be49c
JM		 1531 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
578bb252 1535 /* XXX : not implemented */
363be49c
JM		 1536 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
578bb252 1540 /* XXX : not implemented */
363be49c
JM		 1541 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
578bb252 1545 /* XXX : not implemented */
363be49c
JM		 1546 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 if (env->nb_pids > 1) {
578bb252 1551 /* XXX : not implemented */
363be49c
JM		 1552 spr_register(env, SPR_BOOKE_PID1, "PID1",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556 }
1557 if (env->nb_pids > 2) {
578bb252 1558 /* XXX : not implemented */
363be49c
JM		 1559 spr_register(env, SPR_BOOKE_PID2, "PID2",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 }
578bb252 1564 /* XXX : not implemented */
65f9ee8d 1565 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, SPR_NOACCESS,
1568 0x00000000); /* TOFIX */
578bb252 1569 /* XXX : not implemented */
65f9ee8d 1570 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000); /* TOFIX */
1574 switch (env->nb_ways) {
1575 case 4:
578bb252 1576 /* XXX : not implemented */
363be49c
JM		 1577 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, SPR_NOACCESS,
1580 0x00000000); /* TOFIX */
1581 /* Fallthru */
1582 case 3:
578bb252 1583 /* XXX : not implemented */
363be49c
JM		 1584 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, SPR_NOACCESS,
1587 0x00000000); /* TOFIX */
1588 /* Fallthru */
1589 case 2:
578bb252 1590 /* XXX : not implemented */
363be49c
JM		 1591 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, SPR_NOACCESS,
1594 0x00000000); /* TOFIX */
1595 /* Fallthru */
1596 case 1:
578bb252 1597 /* XXX : not implemented */
363be49c
JM		 1598 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, SPR_NOACCESS,
1601 0x00000000); /* TOFIX */
1602 /* Fallthru */
1603 case 0:
1604 default:
1605 break;
1606 }
1607}
1608
76a66253
JM		 1609/* SPR specific to PowerPC 440 implementation */
1610static void gen_spr_440 (CPUPPCState *env)
1611{
1612 /* Cache control */
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_440_DNV0, "DNV0",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_440_DNV1, "DNV1",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_440_DNV2, "DNV2",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 /* XXX : not implemented */
1629 spr_register(env, SPR_440_DNV3, "DNV3",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 /* XXX : not implemented */
2662a059 1634 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 /* XXX : not implemented */
2662a059 1639 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 /* XXX : not implemented */
2662a059 1644 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 /* XXX : not implemented */
2662a059 1649 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, &spr_write_generic,
1652 0x00000000);
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_440_DVLIM, "DVLIM",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_440_INV0, "INV0",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_440_INV1, "INV1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_440_INV2, "INV2",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_440_INV3, "INV3",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_generic,
1677 0x00000000);
1678 /* XXX : not implemented */
2662a059 1679 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* XXX : not implemented */
2662a059 1684 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
2662a059 1689 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
2662a059 1694 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_IVLIM, "IVLIM",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* Cache debug */
1704 /* XXX : not implemented */
2662a059 1705 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, SPR_NOACCESS,
1708 0x00000000);
1709 /* XXX : not implemented */
2662a059 1710 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, SPR_NOACCESS,
1713 0x00000000);
1714 /* XXX : not implemented */
2662a059 1715 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, SPR_NOACCESS,
1718 0x00000000);
1719 /* XXX : not implemented */
2662a059 1720 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, SPR_NOACCESS,
1723 0x00000000);
1724 /* XXX : not implemented */
2662a059 1725 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, SPR_NOACCESS,
1728 0x00000000);
1729 /* XXX : not implemented */
1730 spr_register(env, SPR_440_DBDR, "DBDR",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734 /* Processor control */
1735 spr_register(env, SPR_4xx_CCR0, "CCR0",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, SPR_NOACCESS,
1742 0x00000000);
1743 /* Storage control */
1744 spr_register(env, SPR_440_MMUCR, "MMUCR",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748}
1749
1750/* SPR shared between PowerPC 40x implementations */
1751static void gen_spr_40x (CPUPPCState *env)
1752{
1753 /* Cache */
035feb88 1754 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1755 spr_register(env, SPR_40x_DCCR, "DCCR",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_generic,
1758 0x00000000);
035feb88 1759 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1760 spr_register(env, SPR_40x_ICCR, "ICCR",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
578bb252 1764 /* not emulated, as Qemu do not emulate caches */
2662a059 1765 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, SPR_NOACCESS,
1768 0x00000000);
76a66253
JM		 1769 /* Exception */
1770 spr_register(env, SPR_40x_DEAR, "DEAR",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774 spr_register(env, SPR_40x_ESR, "ESR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 spr_register(env, SPR_40x_EVPR, "EVPR",
1779 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1780 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1781 0x00000000);
1782 spr_register(env, SPR_40x_SRR2, "SRR2",
1783 &spr_read_generic, &spr_write_generic,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 spr_register(env, SPR_40x_SRR3, "SRR3",
1787 &spr_read_generic, &spr_write_generic,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790 /* Timers */
1791 spr_register(env, SPR_40x_PIT, "PIT",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_40x_pit, &spr_write_40x_pit,
1794 0x00000000);
1795 spr_register(env, SPR_40x_TCR, "TCR",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_booke_tcr,
1798 0x00000000);
1799 spr_register(env, SPR_40x_TSR, "TSR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_booke_tsr,
1802 0x00000000);
2662a059
JM		 1803}
1804
1805/* SPR specific to PowerPC 405 implementation */
1806static void gen_spr_405 (CPUPPCState *env)
1807{
1808 /* MMU */
1809 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
2662a059 1813 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1816 0x00700000);
1817 /* Debug interface */
76a66253
JM		 1818 /* XXX : not implemented */
1819 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1820 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1821 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1822 0x00000000);
1823 /* XXX : not implemented */
2662a059
JM		 1824 spr_register(env, SPR_405_DBCR1, "DBCR1",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 /* XXX : not implemented */
76a66253
JM		 1829 spr_register(env, SPR_40x_DBSR, "DBSR",
1830 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1831 &spr_read_generic, &spr_write_clear,
1832 /* Last reset was system reset */
76a66253
JM		 1833 0x00000300);
1834 /* XXX : not implemented */
2662a059 1835 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_generic,
1838 0x00000000);
2662a059 1839 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
2662a059
JM		 1843 /* XXX : not implemented */
1844 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
2662a059 1847 0x00000000);
76a66253 1848 /* XXX : not implemented */
2662a059 1849 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 /* XXX : not implemented */
2662a059 1854 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_generic,
1857 0x00000000);
2662a059 1858 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_405_IAC3, "IAC3",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_405_IAC4, "IAC4",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* Storage control */
035feb88 1873 /* XXX: TODO: not implemented */
76a66253
JM		 1874 spr_register(env, SPR_405_SLER, "SLER",
1875 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1876 &spr_read_generic, &spr_write_40x_sler,
76a66253 1877 0x00000000);
2662a059
JM		 1878 spr_register(env, SPR_40x_ZPR, "ZPR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
76a66253
JM		 1882 /* XXX : not implemented */
1883 spr_register(env, SPR_405_SU0R, "SU0R",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* SPRG */
1888 spr_register(env, SPR_USPRG0, "USPRG0",
1889 &spr_read_ureg, SPR_NOACCESS,
1890 &spr_read_ureg, SPR_NOACCESS,
1891 0x00000000);
1892 spr_register(env, SPR_SPRG4, "SPRG4",
1893 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1894 &spr_read_generic, &spr_write_generic,
76a66253
JM		 1895 0x00000000);
1896 spr_register(env, SPR_USPRG4, "USPRG4",
1897 &spr_read_ureg, SPR_NOACCESS,
1898 &spr_read_ureg, SPR_NOACCESS,
1899 0x00000000);
1900 spr_register(env, SPR_SPRG5, "SPRG5",
1901 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1902 spr_read_generic, &spr_write_generic,
76a66253
JM		 1903 0x00000000);
1904 spr_register(env, SPR_USPRG5, "USPRG5",
1905 &spr_read_ureg, SPR_NOACCESS,
1906 &spr_read_ureg, SPR_NOACCESS,
1907 0x00000000);
1908 spr_register(env, SPR_SPRG6, "SPRG6",
1909 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1910 spr_read_generic, &spr_write_generic,
76a66253
JM		 1911 0x00000000);
1912 spr_register(env, SPR_USPRG6, "USPRG6",
1913 &spr_read_ureg, SPR_NOACCESS,
1914 &spr_read_ureg, SPR_NOACCESS,
1915 0x00000000);
1916 spr_register(env, SPR_SPRG7, "SPRG7",
1917 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1918 spr_read_generic, &spr_write_generic,
76a66253
JM		 1919 0x00000000);
1920 spr_register(env, SPR_USPRG7, "USPRG7",
1921 &spr_read_ureg, SPR_NOACCESS,
1922 &spr_read_ureg, SPR_NOACCESS,
1923 0x00000000);
76a66253
JM		 1924}
1925
1926/* SPR shared between PowerPC 401 & 403 implementations */
1927static void gen_spr_401_403 (CPUPPCState *env)
1928{
1929 /* Time base */
1930 spr_register(env, SPR_403_VTBL, "TBL",
1931 &spr_read_tbl, SPR_NOACCESS,
1932 &spr_read_tbl, SPR_NOACCESS,
1933 0x00000000);
1934 spr_register(env, SPR_403_TBL, "TBL",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 SPR_NOACCESS, &spr_write_tbl,
1937 0x00000000);
1938 spr_register(env, SPR_403_VTBU, "TBU",
1939 &spr_read_tbu, SPR_NOACCESS,
1940 &spr_read_tbu, SPR_NOACCESS,
1941 0x00000000);
1942 spr_register(env, SPR_403_TBU, "TBU",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 SPR_NOACCESS, &spr_write_tbu,
1945 0x00000000);
1946 /* Debug */
578bb252 1947 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1948 spr_register(env, SPR_403_CDBCR, "CDBCR",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952}
1953
2662a059
JM		 1954/* SPR specific to PowerPC 401 implementation */
1955static void gen_spr_401 (CPUPPCState *env)
1956{
1957 /* Debug interface */
1958 /* XXX : not implemented */
1959 spr_register(env, SPR_40x_DBCR0, "DBCR",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, &spr_write_40x_dbcr0,
1962 0x00000000);
1963 /* XXX : not implemented */
1964 spr_register(env, SPR_40x_DBSR, "DBSR",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, &spr_write_clear,
1967 /* Last reset was system reset */
1968 0x00000300);
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_40x_DAC1, "DAC",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_40x_IAC1, "IAC",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 /* Storage control */
035feb88 1980 /* XXX: TODO: not implemented */
2662a059
JM		 1981 spr_register(env, SPR_405_SLER, "SLER",
1982 SPR_NOACCESS, SPR_NOACCESS,
1983 &spr_read_generic, &spr_write_40x_sler,
1984 0x00000000);
035feb88
JM		 1985 /* not emulated, as Qemu never does speculative access */
1986 spr_register(env, SPR_40x_SGR, "SGR",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_generic,
1989 0xFFFFFFFF);
1990 /* not emulated, as Qemu do not emulate caches */
1991 spr_register(env, SPR_40x_DCWR, "DCWR",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_generic,
1994 0x00000000);
2662a059
JM		 1995}
1996
a750fc0b
JM		 1997static void gen_spr_401x2 (CPUPPCState *env)
1998{
1999 gen_spr_401(env);
2000 spr_register(env, SPR_40x_PID, "PID",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 spr_register(env, SPR_40x_ZPR, "ZPR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008}
2009
76a66253
JM		 2010/* SPR specific to PowerPC 403 implementation */
2011static void gen_spr_403 (CPUPPCState *env)
2012{
2662a059
JM		 2013 /* Debug interface */
2014 /* XXX : not implemented */
2015 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_40x_dbcr0,
2018 0x00000000);
2019 /* XXX : not implemented */
2020 spr_register(env, SPR_40x_DBSR, "DBSR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_clear,
2023 /* Last reset was system reset */
2024 0x00000300);
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_40x_DAC1, "DAC1",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
578bb252 2030 /* XXX : not implemented */
2662a059
JM		 2031 spr_register(env, SPR_40x_DAC2, "DAC2",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, &spr_write_generic,
2034 0x00000000);
2035 /* XXX : not implemented */
2036 spr_register(env, SPR_40x_IAC1, "IAC1",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_generic,
2039 0x00000000);
578bb252 2040 /* XXX : not implemented */
2662a059
JM		 2041 spr_register(env, SPR_40x_IAC2, "IAC2",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, &spr_write_generic,
2044 0x00000000);
a750fc0b
JM		 2045}
2046
2047static void gen_spr_403_real (CPUPPCState *env)
2048{
76a66253
JM		 2049 spr_register(env, SPR_403_PBL1, "PBL1",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_403_pbr, &spr_write_403_pbr,
2052 0x00000000);
2053 spr_register(env, SPR_403_PBU1, "PBU1",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_403_pbr, &spr_write_403_pbr,
2056 0x00000000);
2057 spr_register(env, SPR_403_PBL2, "PBL2",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_403_pbr, &spr_write_403_pbr,
2060 0x00000000);
2061 spr_register(env, SPR_403_PBU2, "PBU2",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_403_pbr, &spr_write_403_pbr,
2064 0x00000000);
a750fc0b
JM		 2065}
2066
2067static void gen_spr_403_mmu (CPUPPCState *env)
2068{
2069 /* MMU */
2070 spr_register(env, SPR_40x_PID, "PID",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2662a059 2074 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_generic,
2077 0x00000000);
2078}
2079
2080/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2081static void gen_spr_compress (CPUPPCState *env)
2082{
578bb252 2083 /* XXX : not implemented */
76a66253
JM		 2084 spr_register(env, SPR_401_SKR, "SKR",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088}
a750fc0b
JM		 2089
2090#if defined (TARGET_PPC64)
a750fc0b
JM		 2091/* SPR specific to PowerPC 620 */
2092static void gen_spr_620 (CPUPPCState *env)
2093{
578bb252 2094 /* XXX : not implemented */
a750fc0b
JM		 2095 spr_register(env, SPR_620_PMR0, "PMR0",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
578bb252 2099 /* XXX : not implemented */
a750fc0b
JM		 2100 spr_register(env, SPR_620_PMR1, "PMR1",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
578bb252 2104 /* XXX : not implemented */
a750fc0b
JM		 2105 spr_register(env, SPR_620_PMR2, "PMR2",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
578bb252 2109 /* XXX : not implemented */
a750fc0b
JM		 2110 spr_register(env, SPR_620_PMR3, "PMR3",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
578bb252 2114 /* XXX : not implemented */
a750fc0b
JM		 2115 spr_register(env, SPR_620_PMR4, "PMR4",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_generic, &spr_write_generic,
2118 0x00000000);
578bb252 2119 /* XXX : not implemented */
a750fc0b
JM		 2120 spr_register(env, SPR_620_PMR5, "PMR5",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_generic,
2123 0x00000000);
578bb252 2124 /* XXX : not implemented */
a750fc0b
JM		 2125 spr_register(env, SPR_620_PMR6, "PMR6",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
578bb252 2129 /* XXX : not implemented */
a750fc0b
JM		 2130 spr_register(env, SPR_620_PMR7, "PMR7",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 &spr_read_generic, &spr_write_generic,
2133 0x00000000);
578bb252 2134 /* XXX : not implemented */
a750fc0b
JM		 2135 spr_register(env, SPR_620_PMR8, "PMR8",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
578bb252 2139 /* XXX : not implemented */
a750fc0b
JM		 2140 spr_register(env, SPR_620_PMR9, "PMR9",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
578bb252 2144 /* XXX : not implemented */
a750fc0b
JM		 2145 spr_register(env, SPR_620_PMRA, "PMR10",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
578bb252 2149 /* XXX : not implemented */
a750fc0b
JM		 2150 spr_register(env, SPR_620_PMRB, "PMR11",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
578bb252 2154 /* XXX : not implemented */
a750fc0b
JM		 2155 spr_register(env, SPR_620_PMRC, "PMR12",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
578bb252 2159 /* XXX : not implemented */
a750fc0b
JM		 2160 spr_register(env, SPR_620_PMRD, "PMR13",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
578bb252 2164 /* XXX : not implemented */
a750fc0b
JM		 2165 spr_register(env, SPR_620_PMRE, "PMR14",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
578bb252 2169 /* XXX : not implemented */
a750fc0b
JM		 2170 spr_register(env, SPR_620_PMRF, "PMR15",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
578bb252 2174 /* XXX : not implemented */
a750fc0b
JM		 2175 spr_register(env, SPR_620_HID8, "HID8",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
578bb252 2179 /* XXX : not implemented */
a750fc0b
JM		 2180 spr_register(env, SPR_620_HID9, "HID9",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184}
a750fc0b 2185#endif /* defined (TARGET_PPC64) */
76a66253 2186
2662a059 2187// XXX: TODO
76a66253 2188/*
2662a059
JM		 2189 * AMR => SPR 29 (Power 2.04)
2190 * CTRL => SPR 136 (Power 2.04)
2191 * CTRL => SPR 152 (Power 2.04)
2662a059
JM		 2192 * SCOMC => SPR 276 (64 bits ?)
2193 * SCOMD => SPR 277 (64 bits ?)
2662a059
JM		 2194 * TBU40 => SPR 286 (Power 2.04 hypv)
2195 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2196 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2197 * HDSISR => SPR 306 (Power 2.04 hypv)
2198 * HDAR => SPR 307 (Power 2.04 hypv)
2199 * PURR => SPR 309 (Power 2.04 hypv)
2200 * HDEC => SPR 310 (Power 2.04 hypv)
2201 * HIOR => SPR 311 (hypv)
2202 * RMOR => SPR 312 (970)
2203 * HRMOR => SPR 313 (Power 2.04 hypv)
2204 * HSRR0 => SPR 314 (Power 2.04 hypv)
2205 * HSRR1 => SPR 315 (Power 2.04 hypv)
2206 * LPCR => SPR 316 (970)
2207 * LPIDR => SPR 317 (970)
2208 * SPEFSCR => SPR 512 (Power 2.04 emb)
2662a059
JM		 2209 * EPR => SPR 702 (Power 2.04 emb)
2210 * perf => 768-783 (Power 2.04)
2211 * perf => 784-799 (Power 2.04)
2212 * PPR => SPR 896 (Power 2.04)
2213 * EPLC => SPR 947 (Power 2.04 emb)
2214 * EPSC => SPR 948 (Power 2.04 emb)
2215 * DABRX => 1015 (Power 2.04 hypv)
2216 * FPECR => SPR 1022 (?)
76a66253
JM		 2217 * ... and more (thermal management, performance counters, ...)
2218 */
2219
e1833e1f
JM		 2220/*****************************************************************************/
2221/* Exception vectors models */
2222static void init_excp_4xx_real (CPUPPCState *env)
2223{
2224#if !defined(CONFIG_USER_ONLY)
2225 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2226 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2227 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2228 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2229 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2230 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2231 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2232 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2233 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2234 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2235 env->excp_prefix = 0x00000000;
2236 env->ivor_mask = 0x0000FFF0;
2237 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2238 /* Hardware reset vector */
2239 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2240#endif
2241}
2242
2243static void init_excp_4xx_softmmu (CPUPPCState *env)
2244{
2245#if !defined(CONFIG_USER_ONLY)
2246 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2247 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2248 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2249 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2250 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2251 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2252 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2253 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2254 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2255 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2256 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2257 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2258 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2259 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2260 env->excp_prefix = 0x00000000;
2261 env->ivor_mask = 0x0000FFF0;
2262 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2263 /* Hardware reset vector */
2264 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2265#endif
2266}
2267
2268static void init_excp_BookE (CPUPPCState *env)
2269{
2270#if !defined(CONFIG_USER_ONLY)
2271 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2272 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2273 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2274 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2275 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2276 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2277 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2278 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2279 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2280 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2281 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2282 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2283 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2284 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2285 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2287 env->excp_prefix = 0x00000000;
2288 env->ivor_mask = 0x0000FFE0;
2289 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2290 /* Hardware reset vector */
2291 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2292#endif
2293}
2294
2295static void init_excp_601 (CPUPPCState *env)
2296{
2297#if !defined(CONFIG_USER_ONLY)
2298 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2299 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2300 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2301 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2302 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2303 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2304 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2305 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2306 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2307 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2308 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2309 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2310 env->excp_prefix = 0xFFF00000;
1c27f8fb
JM		 2311 /* Hardware reset vector */
2312 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2313#endif
2314}
2315
2316static void init_excp_602 (CPUPPCState *env)
2317{
2318#if !defined(CONFIG_USER_ONLY)
2319 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2320 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2321 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2322 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2323 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2324 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2325 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2326 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2327 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2328 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2329 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2330 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2331 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2332 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2333 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2334 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2335 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2336 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2337 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2338 env->excp_prefix = 0xFFF00000;
1c27f8fb
JM		 2339 /* Hardware reset vector */
2340 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2341#endif
2342}
2343
2344static void init_excp_603 (CPUPPCState *env)
2345{
2346#if !defined(CONFIG_USER_ONLY)
2347 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2348 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2349 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2350 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2351 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2352 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2353 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2354 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2355 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2356 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2357 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2358 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2359 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2360 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2361 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2362 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2363 /* Hardware reset vector */
2364 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2365#endif
2366}
2367
2368static void init_excp_G2 (CPUPPCState *env)
2369{
2370#if !defined(CONFIG_USER_ONLY)
2371 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2372 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2373 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2374 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2375 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2376 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2377 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2378 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2379 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2380 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2381 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2382 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2383 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2384 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2385 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2386 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2387 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2388 /* Hardware reset vector */
2389 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2390#endif
2391}
2392
2393static void init_excp_604 (CPUPPCState *env)
2394{
2395#if !defined(CONFIG_USER_ONLY)
2396 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2397 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2398 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2399 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2400 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2401 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2402 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2403 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2404 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2405 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2406 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2407 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2408 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2409 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2410 /* Hardware reset vector */
2411 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2412#endif
2413}
2414
578bb252 2415#if defined(TARGET_PPC64)
e1833e1f
JM		 2416static void init_excp_620 (CPUPPCState *env)
2417{
2418#if !defined(CONFIG_USER_ONLY)
2419 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2420 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2421 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2422 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2423 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2424 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2425 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2426 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2427 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2428 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2429 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2430 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2431 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2432 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2433 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2434 /* Hardware reset vector */
2435 env->hreset_vector = 0x0000000000000100ULL; /* ? */
e1833e1f
JM		 2436#endif
2437}
578bb252 2438#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2439
2440static void init_excp_7x0 (CPUPPCState *env)
2441{
2442#if !defined(CONFIG_USER_ONLY)
2443 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2444 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2445 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2446 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2447 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2448 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2449 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2450 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2451 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2452 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2453 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2454 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2455 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2456 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2457 /* Hardware reset vector */
2458 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2459#endif
2460}
2461
2462static void init_excp_750FX (CPUPPCState *env)
2463{
2464#if !defined(CONFIG_USER_ONLY)
2465 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2466 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2467 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2468 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2469 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2470 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2471 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2472 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2473 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2474 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2475 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2476 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2477 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2478 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2479 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2480 /* Hardware reset vector */
2481 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2482#endif
2483}
2484
2485static void init_excp_7400 (CPUPPCState *env)
2486{
2487#if !defined(CONFIG_USER_ONLY)
2488 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2489 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2490 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2491 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2492 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2493 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2494 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2495 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2496 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2497 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2498 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2499 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2500 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2501 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2502 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2503 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2504 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2505 /* Hardware reset vector */
2506 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2507#endif
2508}
2509
e1833e1f
JM		 2510static void init_excp_7450 (CPUPPCState *env)
2511{
2512#if !defined(CONFIG_USER_ONLY)
2513 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2514 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2515 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2516 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2517 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2518 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2519 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2520 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2521 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2522 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2523 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2524 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2525 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2526 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2527 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2528 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2529 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2530 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2531 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb
JM		 2532 /* Hardware reset vector */
2533 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2534#endif
2535}
e1833e1f
JM		 2536
2537#if defined (TARGET_PPC64)
2538static void init_excp_970 (CPUPPCState *env)
2539{
2540#if !defined(CONFIG_USER_ONLY)
2541 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2542 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2543 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2544 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2545 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2546 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2547 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2548 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2549 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2550 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2551 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2552#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2553 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2554#endif
2555 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2556 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2557 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2558 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2559 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2560 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2561 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2562 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 2563 /* Hardware reset vector */
2564 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2565#endif
2566}
2567#endif
2568
a750fc0b
JM		 2569/*****************************************************************************/
2570/* PowerPC implementations definitions */
76a66253 2571
a750fc0b 2572/* PowerPC 40x instruction set */
d63001d1 2573#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
76a66253 2574
a750fc0b
JM		 2575/* PowerPC 401 */
2576#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2577 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2578 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2579#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2580#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2581#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2582#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 2583#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
76a66253 2584
a750fc0b
JM		 2585static void init_proc_401 (CPUPPCState *env)
2586{
2587 gen_spr_40x(env);
2588 gen_spr_401_403(env);
2589 gen_spr_401(env);
e1833e1f 2590 init_excp_4xx_real(env);
d63001d1
JM		 2591 env->dcache_line_size = 32;
2592 env->icache_line_size = 32;
4e290a0b
JM		 2593 /* Allocate hardware IRQ controller */
2594 ppc40x_irq_init(env);
a750fc0b 2595}
76a66253 2596
a750fc0b
JM		 2597/* PowerPC 401x2 */
2598#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2599 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2600 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2601 PPC_CACHE_DCBA | PPC_MFTB | \
2602 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2603#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2604#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2605#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2606#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 2607#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
a750fc0b
JM		 2608
2609static void init_proc_401x2 (CPUPPCState *env)
2610{
2611 gen_spr_40x(env);
2612 gen_spr_401_403(env);
2613 gen_spr_401x2(env);
2614 gen_spr_compress(env);
a750fc0b
JM		 2615 /* Memory management */
2616 env->nb_tlb = 64;
2617 env->nb_ways = 1;
2618 env->id_tlbs = 0;
e1833e1f 2619 init_excp_4xx_softmmu(env);
d63001d1
JM		 2620 env->dcache_line_size = 32;
2621 env->icache_line_size = 32;
4e290a0b
JM		 2622 /* Allocate hardware IRQ controller */
2623 ppc40x_irq_init(env);
76a66253
JM		 2624}
2625
a750fc0b 2626/* PowerPC 401x3 */
a750fc0b
JM		 2627#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2628 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2629 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2630 PPC_CACHE_DCBA | PPC_MFTB | \
2631 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2632#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2633#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2634#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2635#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 2636#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
a750fc0b 2637
578bb252 2638__attribute__ (( unused ))
e1833e1f 2639static void init_proc_401x3 (CPUPPCState *env)
76a66253 2640{
4e290a0b
JM		 2641 gen_spr_40x(env);
2642 gen_spr_401_403(env);
2643 gen_spr_401(env);
2644 gen_spr_401x2(env);
2645 gen_spr_compress(env);
e1833e1f 2646 init_excp_4xx_softmmu(env);
d63001d1
JM		 2647 env->dcache_line_size = 32;
2648 env->icache_line_size = 32;
4e290a0b
JM		 2649 /* Allocate hardware IRQ controller */
2650 ppc40x_irq_init(env);
3fc6c082 2651}
a750fc0b
JM		 2652
2653/* IOP480 */
2654#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2655 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2656 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2657 PPC_CACHE_DCBA | \
2658 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2659#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2660#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2661#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2662#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 2663#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
a750fc0b
JM		 2664
2665static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 2666{
a750fc0b
JM		 2667 gen_spr_40x(env);
2668 gen_spr_401_403(env);
2669 gen_spr_401x2(env);
2670 gen_spr_compress(env);
a750fc0b
JM		 2671 /* Memory management */
2672 env->nb_tlb = 64;
2673 env->nb_ways = 1;
2674 env->id_tlbs = 0;
e1833e1f 2675 init_excp_4xx_softmmu(env);
d63001d1
JM		 2676 env->dcache_line_size = 32;
2677 env->icache_line_size = 32;
4e290a0b
JM		 2678 /* Allocate hardware IRQ controller */
2679 ppc40x_irq_init(env);
3fc6c082
FB		 2680}
2681
a750fc0b
JM		 2682/* PowerPC 403 */
2683#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2684 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2685 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2686 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2687#define POWERPC_MSRM_403 (0x000000000007D00DULL)
2688#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2689#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2690#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 2691#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
a750fc0b
JM		 2692
2693static void init_proc_403 (CPUPPCState *env)
3fc6c082 2694{
a750fc0b
JM		 2695 gen_spr_40x(env);
2696 gen_spr_401_403(env);
2697 gen_spr_403(env);
2698 gen_spr_403_real(env);
e1833e1f 2699 init_excp_4xx_real(env);
d63001d1
JM		 2700 env->dcache_line_size = 32;
2701 env->icache_line_size = 32;
4e290a0b
JM		 2702 /* Allocate hardware IRQ controller */
2703 ppc40x_irq_init(env);
d63001d1
JM		 2704#if !defined(CONFIG_USER_ONLY)
2705 /* Hardware reset vector */
2706 env->hreset_vector = 0xFFFFFFFCUL;
2707#endif
3fc6c082
FB		 2708}
2709
a750fc0b
JM		 2710/* PowerPC 403 GCX */
2711#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2712 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2713 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2714 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2715#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2716#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2717#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2718#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 2719#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
a750fc0b
JM		 2720
2721static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 2722{
a750fc0b
JM		 2723 gen_spr_40x(env);
2724 gen_spr_401_403(env);
2725 gen_spr_403(env);
2726 gen_spr_403_real(env);
2727 gen_spr_403_mmu(env);
2728 /* Bus access control */
035feb88 2729 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2730 spr_register(env, SPR_40x_SGR, "SGR",
2731 SPR_NOACCESS, SPR_NOACCESS,
2732 &spr_read_generic, &spr_write_generic,
2733 0xFFFFFFFF);
035feb88 2734 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2735 spr_register(env, SPR_40x_DCWR, "DCWR",
2736 SPR_NOACCESS, SPR_NOACCESS,
2737 &spr_read_generic, &spr_write_generic,
2738 0x00000000);
2739 /* Memory management */
2740 env->nb_tlb = 64;
2741 env->nb_ways = 1;
2742 env->id_tlbs = 0;
e1833e1f 2743 init_excp_4xx_softmmu(env);
d63001d1
JM		 2744 env->dcache_line_size = 32;
2745 env->icache_line_size = 32;
4e290a0b
JM		 2746 /* Allocate hardware IRQ controller */
2747 ppc40x_irq_init(env);
3fc6c082
FB		 2748}
2749
a750fc0b
JM		 2750/* PowerPC 405 */
2751#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2752 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2753 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2754 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2755 PPC_405_MAC)
2756#define POWERPC_MSRM_405 (0x000000000006E630ULL)
2757#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2758#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2759#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
237c0af0 2760#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
a750fc0b
JM		 2761
2762static void init_proc_405 (CPUPPCState *env)
3fc6c082 2763{
a750fc0b
JM		 2764 /* Time base */
2765 gen_tbl(env);
2766 gen_spr_40x(env);
2767 gen_spr_405(env);
2768 /* Bus access control */
035feb88 2769 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2770 spr_register(env, SPR_40x_SGR, "SGR",
2771 SPR_NOACCESS, SPR_NOACCESS,
2772 &spr_read_generic, &spr_write_generic,
2773 0xFFFFFFFF);
035feb88 2774 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2775 spr_register(env, SPR_40x_DCWR, "DCWR",
2776 SPR_NOACCESS, SPR_NOACCESS,
2777 &spr_read_generic, &spr_write_generic,
2778 0x00000000);
2779 /* Memory management */
2780 env->nb_tlb = 64;
2781 env->nb_ways = 1;
2782 env->id_tlbs = 0;
e1833e1f 2783 init_excp_4xx_softmmu(env);
d63001d1
JM		 2784 env->dcache_line_size = 32;
2785 env->icache_line_size = 32;
a750fc0b 2786 /* Allocate hardware IRQ controller */
4e290a0b 2787 ppc40x_irq_init(env);
3fc6c082
FB		 2788}
2789
a750fc0b
JM		 2790/* PowerPC 440 EP */
2791#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2792 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2793 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2794 PPC_440_SPEC | PPC_RFMCI)
2795#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2796#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2797#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2798#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
237c0af0 2799#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
a750fc0b
JM		 2800
2801static void init_proc_440EP (CPUPPCState *env)
3fc6c082 2802{
a750fc0b
JM		 2803 /* Time base */
2804 gen_tbl(env);
2805 gen_spr_BookE(env);
2806 gen_spr_440(env);
578bb252 2807 /* XXX : not implemented */
a750fc0b
JM		 2808 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2809 SPR_NOACCESS, SPR_NOACCESS,
2810 &spr_read_generic, &spr_write_generic,
2811 0x00000000);
2812 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2813 SPR_NOACCESS, SPR_NOACCESS,
2814 &spr_read_generic, &spr_write_generic,
2815 0x00000000);
2816 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2817 SPR_NOACCESS, SPR_NOACCESS,
2818 &spr_read_generic, &spr_write_generic,
2819 0x00000000);
578bb252 2820 /* XXX : not implemented */
a750fc0b
JM		 2821 spr_register(env, SPR_440_CCR1, "CCR1",
2822 SPR_NOACCESS, SPR_NOACCESS,
2823 &spr_read_generic, &spr_write_generic,
2824 0x00000000);
2825 /* Memory management */
2826 env->nb_tlb = 64;
2827 env->nb_ways = 1;
2828 env->id_tlbs = 0;
e1833e1f 2829 init_excp_BookE(env);
d63001d1
JM		 2830 env->dcache_line_size = 32;
2831 env->icache_line_size = 32;
a750fc0b 2832 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2833}
2834
a750fc0b
JM		 2835/* PowerPC 440 GP */
2836#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2837 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2838 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2839 PPC_405_MAC | PPC_440_SPEC)
2840#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2841#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2842#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2843#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
237c0af0 2844#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
a750fc0b
JM		 2845
2846static void init_proc_440GP (CPUPPCState *env)
3fc6c082 2847{
a750fc0b
JM		 2848 /* Time base */
2849 gen_tbl(env);
2850 gen_spr_BookE(env);
2851 gen_spr_440(env);
2852 /* Memory management */
2853 env->nb_tlb = 64;
2854 env->nb_ways = 1;
2855 env->id_tlbs = 0;
e1833e1f 2856 init_excp_BookE(env);
d63001d1
JM		 2857 env->dcache_line_size = 32;
2858 env->icache_line_size = 32;
a750fc0b 2859 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2860}
2861
a750fc0b 2862/* PowerPC 440x4 */
a750fc0b
JM		 2863#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2864 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2865 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2866 PPC_440_SPEC)
2867#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2868#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2869#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2870#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
237c0af0 2871#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
a750fc0b 2872
578bb252 2873__attribute__ (( unused ))
a750fc0b 2874static void init_proc_440x4 (CPUPPCState *env)
3fc6c082 2875{
a750fc0b
JM		 2876 /* Time base */
2877 gen_tbl(env);
2878 gen_spr_BookE(env);
2879 gen_spr_440(env);
2880 /* Memory management */
2881 env->nb_tlb = 64;
2882 env->nb_ways = 1;
2883 env->id_tlbs = 0;
e1833e1f 2884 init_excp_BookE(env);
d63001d1
JM		 2885 env->dcache_line_size = 32;
2886 env->icache_line_size = 32;
a750fc0b 2887 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2888}
a750fc0b
JM		 2889
2890/* PowerPC 440x5 */
2891#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2892 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2893 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2894 PPC_440_SPEC | PPC_RFMCI)
2895#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2896#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2897#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2898#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
237c0af0 2899#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
a750fc0b
JM		 2900
2901static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 2902{
a750fc0b
JM		 2903 /* Time base */
2904 gen_tbl(env);
2905 gen_spr_BookE(env);
2906 gen_spr_440(env);
578bb252 2907 /* XXX : not implemented */
a750fc0b
JM		 2908 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2909 SPR_NOACCESS, SPR_NOACCESS,
2910 &spr_read_generic, &spr_write_generic,
2911 0x00000000);
2912 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2913 SPR_NOACCESS, SPR_NOACCESS,
2914 &spr_read_generic, &spr_write_generic,
2915 0x00000000);
2916 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2917 SPR_NOACCESS, SPR_NOACCESS,
2918 &spr_read_generic, &spr_write_generic,
2919 0x00000000);
578bb252 2920 /* XXX : not implemented */
a750fc0b
JM		 2921 spr_register(env, SPR_440_CCR1, "CCR1",
2922 SPR_NOACCESS, SPR_NOACCESS,
2923 &spr_read_generic, &spr_write_generic,
2924 0x00000000);
2925 /* Memory management */
2926 env->nb_tlb = 64;
2927 env->nb_ways = 1;
2928 env->id_tlbs = 0;
e1833e1f 2929 init_excp_BookE(env);
d63001d1
JM		 2930 env->dcache_line_size = 32;
2931 env->icache_line_size = 32;
a750fc0b 2932 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2933}
2934
a750fc0b 2935/* PowerPC 460 (guessed) */
578bb252 2936#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
a750fc0b
JM		 2937 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2938 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2939 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2940#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2941#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2942#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2943#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
237c0af0 2944#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
a750fc0b 2945
578bb252 2946__attribute__ (( unused ))
a750fc0b 2947static void init_proc_460 (CPUPPCState *env)
3fc6c082 2948{
e1833e1f
JM		 2949 /* Time base */
2950 gen_tbl(env);
2951 gen_spr_BookE(env);
2952 gen_spr_440(env);
578bb252 2953 /* XXX : not implemented */
e1833e1f
JM		 2954 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2955 SPR_NOACCESS, SPR_NOACCESS,
2956 &spr_read_generic, &spr_write_generic,
2957 0x00000000);
2958 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2959 SPR_NOACCESS, SPR_NOACCESS,
2960 &spr_read_generic, &spr_write_generic,
2961 0x00000000);
2962 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2963 SPR_NOACCESS, SPR_NOACCESS,
2964 &spr_read_generic, &spr_write_generic,
2965 0x00000000);
578bb252 2966 /* XXX : not implemented */
e1833e1f
JM		 2967 spr_register(env, SPR_440_CCR1, "CCR1",
2968 SPR_NOACCESS, SPR_NOACCESS,
2969 &spr_read_generic, &spr_write_generic,
2970 0x00000000);
578bb252 2971 /* XXX : not implemented */
e1833e1f
JM		 2972 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2973 &spr_read_generic, &spr_write_generic,
2974 &spr_read_generic, &spr_write_generic,
2975 0x00000000);
2976 /* Memory management */
2977 env->nb_tlb = 64;
2978 env->nb_ways = 1;
2979 env->id_tlbs = 0;
2980 init_excp_BookE(env);
d63001d1
JM		 2981 env->dcache_line_size = 32;
2982 env->icache_line_size = 32;
e1833e1f 2983 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2984}
a750fc0b
JM		 2985
2986/* PowerPC 460F (guessed) */
a750fc0b
JM		 2987#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2988 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2989 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
2990 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
2991 PPC_FLOAT_STFIWX | \
2992 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2993 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2994#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2995#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
2996#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
2997#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
237c0af0 2998#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
a750fc0b 2999
578bb252 3000__attribute__ (( unused ))
e1833e1f 3001static void init_proc_460F (CPUPPCState *env)
3fc6c082 3002{
a750fc0b
JM		 3003 /* Time base */
3004 gen_tbl(env);
3005 gen_spr_BookE(env);
3006 gen_spr_440(env);
578bb252 3007 /* XXX : not implemented */
a750fc0b
JM		 3008 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3009 SPR_NOACCESS, SPR_NOACCESS,
3010 &spr_read_generic, &spr_write_generic,
3011 0x00000000);
3012 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3013 SPR_NOACCESS, SPR_NOACCESS,
3014 &spr_read_generic, &spr_write_generic,
3015 0x00000000);
3016 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3017 SPR_NOACCESS, SPR_NOACCESS,
3018 &spr_read_generic, &spr_write_generic,
3019 0x00000000);
578bb252 3020 /* XXX : not implemented */
a750fc0b
JM		 3021 spr_register(env, SPR_440_CCR1, "CCR1",
3022 SPR_NOACCESS, SPR_NOACCESS,
3023 &spr_read_generic, &spr_write_generic,
3024 0x00000000);
578bb252 3025 /* XXX : not implemented */
a750fc0b
JM		 3026 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3027 &spr_read_generic, &spr_write_generic,
3028 &spr_read_generic, &spr_write_generic,
3029 0x00000000);
3030 /* Memory management */
3031 env->nb_tlb = 64;
3032 env->nb_ways = 1;
3033 env->id_tlbs = 0;
e1833e1f 3034 init_excp_BookE(env);
d63001d1
JM		 3035 env->dcache_line_size = 32;
3036 env->icache_line_size = 32;
a750fc0b 3037 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3038}
a750fc0b
JM		 3039
3040/* Generic BookE PowerPC */
a750fc0b
JM		 3041#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3042 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3043 PPC_CACHE_DCBA | \
3044 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3045 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3046 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3047 PPC_BOOKE)
3048#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3049#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3050#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3051#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
237c0af0 3052#define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
a750fc0b 3053
578bb252 3054__attribute__ (( unused ))
a750fc0b 3055static void init_proc_BookE (CPUPPCState *env)
3fc6c082 3056{
e1833e1f 3057 init_excp_BookE(env);
d63001d1
JM		 3058 env->dcache_line_size = 32;
3059 env->icache_line_size = 32;
3fc6c082 3060}
a750fc0b
JM		 3061
3062/* e200 core */
a750fc0b
JM		 3063
3064/* e300 core */
a750fc0b
JM		 3065
3066/* e500 core */
a750fc0b
JM		 3067#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3068 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3069 PPC_CACHE_DCBA | \
3070 PPC_BOOKE | PPC_E500_VECTOR)
3071#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3072#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3073#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
237c0af0 3074#define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
a750fc0b 3075
578bb252 3076__attribute__ (( unused ))
a750fc0b 3077static void init_proc_e500 (CPUPPCState *env)
3fc6c082 3078{
a750fc0b
JM		 3079 /* Time base */
3080 gen_tbl(env);
3081 gen_spr_BookE(env);
3082 /* Memory management */
3083 gen_spr_BookE_FSL(env);
3084 env->nb_tlb = 64;
3085 env->nb_ways = 1;
3086 env->id_tlbs = 0;
e1833e1f 3087 init_excp_BookE(env);
d63001d1
JM		 3088 env->dcache_line_size = 32;
3089 env->icache_line_size = 32;
a750fc0b 3090 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3091}
a750fc0b
JM		 3092
3093/* e600 core */
a750fc0b
JM		 3094
3095/* Non-embedded PowerPC */
3096/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3097#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
12de9a39 3098 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
a750fc0b
JM		 3099/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3100#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3101 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3102 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
12de9a39
JM		 3103 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3104 PPC_SEGMENT)
a750fc0b
JM		 3105
3106/* POWER : same as 601, without mfmsr, mfsr */
3107#if defined(TODO)
3108#define POWERPC_INSNS_POWER (XXX_TODO)
3109/* POWER RSC (from RAD6000) */
3110#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3111#endif /* TODO */
3112
3113/* PowerPC 601 */
d63001d1 3114#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
12de9a39 3115 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
a750fc0b
JM		 3116#define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3117//#define POWERPC_MMU_601 (POWERPC_MMU_601)
3118//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3119#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 3120#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
a750fc0b
JM		 3121
3122static void init_proc_601 (CPUPPCState *env)
3fc6c082 3123{
a750fc0b
JM		 3124 gen_spr_ne_601(env);
3125 gen_spr_601(env);
3126 /* Hardware implementation registers */
3127 /* XXX : not implemented */
3128 spr_register(env, SPR_HID0, "HID0",
3129 SPR_NOACCESS, SPR_NOACCESS,
3130 &spr_read_generic, &spr_write_generic,
3131 0x00000000);
3132 /* XXX : not implemented */
3133 spr_register(env, SPR_HID1, "HID1",
3134 SPR_NOACCESS, SPR_NOACCESS,
3135 &spr_read_generic, &spr_write_generic,
3136 0x00000000);
3137 /* XXX : not implemented */
3138 spr_register(env, SPR_601_HID2, "HID2",
3139 SPR_NOACCESS, SPR_NOACCESS,
3140 &spr_read_generic, &spr_write_generic,
3141 0x00000000);
3142 /* XXX : not implemented */
3143 spr_register(env, SPR_601_HID5, "HID5",
3144 SPR_NOACCESS, SPR_NOACCESS,
3145 &spr_read_generic, &spr_write_generic,
3146 0x00000000);
3147 /* XXX : not implemented */
3148 spr_register(env, SPR_601_HID15, "HID15",
3149 SPR_NOACCESS, SPR_NOACCESS,
3150 &spr_read_generic, &spr_write_generic,
3151 0x00000000);
3152 /* Memory management */
3153 env->nb_tlb = 64;
3154 env->nb_ways = 2;
3155 env->id_tlbs = 0;
3156 env->id_tlbs = 0;
e1833e1f 3157 init_excp_601(env);
d63001d1
JM		 3158 env->dcache_line_size = 64;
3159 env->icache_line_size = 64;
a750fc0b 3160 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3161}
3162
a750fc0b
JM		 3163/* PowerPC 602 */
3164#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3165 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3166 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
d63001d1 3167 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
12de9a39 3168 PPC_SEGMENT | PPC_602_SPEC)
a750fc0b
JM		 3169#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3170#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3171//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3172#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 3173#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
a750fc0b
JM		 3174
3175static void init_proc_602 (CPUPPCState *env)
3fc6c082 3176{
a750fc0b
JM		 3177 gen_spr_ne_601(env);
3178 gen_spr_602(env);
3179 /* Time base */
3180 gen_tbl(env);
3181 /* hardware implementation registers */
3182 /* XXX : not implemented */
3183 spr_register(env, SPR_HID0, "HID0",
3184 SPR_NOACCESS, SPR_NOACCESS,
3185 &spr_read_generic, &spr_write_generic,
3186 0x00000000);
3187 /* XXX : not implemented */
3188 spr_register(env, SPR_HID1, "HID1",
3189 SPR_NOACCESS, SPR_NOACCESS,
3190 &spr_read_generic, &spr_write_generic,
3191 0x00000000);
3192 /* Memory management */
3193 gen_low_BATs(env);
3194 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3195 init_excp_602(env);
d63001d1
JM		 3196 env->dcache_line_size = 32;
3197 env->icache_line_size = 32;
a750fc0b
JM		 3198 /* Allocate hardware IRQ controller */
3199 ppc6xx_irq_init(env);
3200}
3fc6c082 3201
a750fc0b
JM		 3202/* PowerPC 603 */
3203#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3204#define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3205#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3206//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3207#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 3208#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
a750fc0b
JM		 3209
3210static void init_proc_603 (CPUPPCState *env)
3211{
3212 gen_spr_ne_601(env);
3213 gen_spr_603(env);
3214 /* Time base */
3215 gen_tbl(env);
3216 /* hardware implementation registers */
3217 /* XXX : not implemented */
3218 spr_register(env, SPR_HID0, "HID0",
3219 SPR_NOACCESS, SPR_NOACCESS,
3220 &spr_read_generic, &spr_write_generic,
3221 0x00000000);
3222 /* XXX : not implemented */
3223 spr_register(env, SPR_HID1, "HID1",
3224 SPR_NOACCESS, SPR_NOACCESS,
3225 &spr_read_generic, &spr_write_generic,
3226 0x00000000);
3227 /* Memory management */
3228 gen_low_BATs(env);
3229 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3230 init_excp_603(env);
d63001d1
JM		 3231 env->dcache_line_size = 32;
3232 env->icache_line_size = 32;
a750fc0b
JM		 3233 /* Allocate hardware IRQ controller */
3234 ppc6xx_irq_init(env);
3fc6c082
FB		 3235}
3236
a750fc0b
JM		 3237/* PowerPC 603e */
3238#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3239#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3240#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3241//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3242#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 3243#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
a750fc0b
JM		 3244
3245static void init_proc_603E (CPUPPCState *env)
3246{
3247 gen_spr_ne_601(env);
3248 gen_spr_603(env);
3249 /* Time base */
3250 gen_tbl(env);
3251 /* hardware implementation registers */
3252 /* XXX : not implemented */
3253 spr_register(env, SPR_HID0, "HID0",
3254 SPR_NOACCESS, SPR_NOACCESS,
3255 &spr_read_generic, &spr_write_generic,
3256 0x00000000);
3257 /* XXX : not implemented */
3258 spr_register(env, SPR_HID1, "HID1",
3259 SPR_NOACCESS, SPR_NOACCESS,
3260 &spr_read_generic, &spr_write_generic,
3261 0x00000000);
3262 /* XXX : not implemented */
3263 spr_register(env, SPR_IABR, "IABR",
3264 SPR_NOACCESS, SPR_NOACCESS,
3265 &spr_read_generic, &spr_write_generic,
3266 0x00000000);
3267 /* Memory management */
3268 gen_low_BATs(env);
3269 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3270 init_excp_603(env);
d63001d1
JM		 3271 env->dcache_line_size = 32;
3272 env->icache_line_size = 32;
a750fc0b
JM		 3273 /* Allocate hardware IRQ controller */
3274 ppc6xx_irq_init(env);
3275}
3276
3277/* PowerPC G2 */
3278#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3279#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3280#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3281//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3282#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
237c0af0 3283#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
a750fc0b
JM		 3284
3285static void init_proc_G2 (CPUPPCState *env)
3286{
3287 gen_spr_ne_601(env);
3288 gen_spr_G2_755(env);
3289 gen_spr_G2(env);
3290 /* Time base */
3291 gen_tbl(env);
3292 /* Hardware implementation register */
3293 /* XXX : not implemented */
3294 spr_register(env, SPR_HID0, "HID0",
3295 SPR_NOACCESS, SPR_NOACCESS,
3296 &spr_read_generic, &spr_write_generic,
3297 0x00000000);
3298 /* XXX : not implemented */
3299 spr_register(env, SPR_HID1, "HID1",
3300 SPR_NOACCESS, SPR_NOACCESS,
3301 &spr_read_generic, &spr_write_generic,
3302 0x00000000);
3303 /* XXX : not implemented */
3304 spr_register(env, SPR_HID2, "HID2",
3305 SPR_NOACCESS, SPR_NOACCESS,
3306 &spr_read_generic, &spr_write_generic,
3307 0x00000000);
3308 /* Memory management */
3309 gen_low_BATs(env);
3310 gen_high_BATs(env);
3311 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3312 init_excp_G2(env);
d63001d1
JM		 3313 env->dcache_line_size = 32;
3314 env->icache_line_size = 32;
a750fc0b
JM		 3315 /* Allocate hardware IRQ controller */
3316 ppc6xx_irq_init(env);
3317}
3318
3319/* PowerPC G2LE */
3320#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3321#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3322#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3323#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3324#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
237c0af0 3325#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
a750fc0b
JM		 3326
3327static void init_proc_G2LE (CPUPPCState *env)
3328{
3329 gen_spr_ne_601(env);
3330 gen_spr_G2_755(env);
3331 gen_spr_G2(env);
3332 /* Time base */
3333 gen_tbl(env);
3334 /* Hardware implementation register */
3335 /* XXX : not implemented */
3336 spr_register(env, SPR_HID0, "HID0",
3337 SPR_NOACCESS, SPR_NOACCESS,
3338 &spr_read_generic, &spr_write_generic,
3339 0x00000000);
3340 /* XXX : not implemented */
3341 spr_register(env, SPR_HID1, "HID1",
3342 SPR_NOACCESS, SPR_NOACCESS,
3343 &spr_read_generic, &spr_write_generic,
3344 0x00000000);
3345 /* XXX : not implemented */
3346 spr_register(env, SPR_HID2, "HID2",
3347 SPR_NOACCESS, SPR_NOACCESS,
3348 &spr_read_generic, &spr_write_generic,
3349 0x00000000);
3350 /* Memory management */
3351 gen_low_BATs(env);
3352 gen_high_BATs(env);
3353 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3354 init_excp_G2(env);
d63001d1
JM		 3355 env->dcache_line_size = 32;
3356 env->icache_line_size = 32;
a750fc0b
JM		 3357 /* Allocate hardware IRQ controller */
3358 ppc6xx_irq_init(env);
3359}
3360
3361/* PowerPC 604 */
3362#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3363#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3364#define POWERPC_MMU_604 (POWERPC_MMU_32B)
3365//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3366#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 3367#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
a750fc0b
JM		 3368
3369static void init_proc_604 (CPUPPCState *env)
3370{
3371 gen_spr_ne_601(env);
3372 gen_spr_604(env);
3373 /* Time base */
3374 gen_tbl(env);
3375 /* Hardware implementation registers */
3376 /* XXX : not implemented */
3377 spr_register(env, SPR_HID0, "HID0",
3378 SPR_NOACCESS, SPR_NOACCESS,
3379 &spr_read_generic, &spr_write_generic,
3380 0x00000000);
3381 /* XXX : not implemented */
3382 spr_register(env, SPR_HID1, "HID1",
3383 SPR_NOACCESS, SPR_NOACCESS,
3384 &spr_read_generic, &spr_write_generic,
3385 0x00000000);
3386 /* Memory management */
3387 gen_low_BATs(env);
e1833e1f 3388 init_excp_604(env);
d63001d1
JM		 3389 env->dcache_line_size = 32;
3390 env->icache_line_size = 32;
a750fc0b
JM		 3391 /* Allocate hardware IRQ controller */
3392 ppc6xx_irq_init(env);
3393}
3394
3395/* PowerPC 740/750 (aka G3) */
3396#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3397#define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3398#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3399//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3400#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 3401#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
a750fc0b
JM		 3402
3403static void init_proc_7x0 (CPUPPCState *env)
3404{
3405 gen_spr_ne_601(env);
3406 gen_spr_7xx(env);
3407 /* Time base */
3408 gen_tbl(env);
3409 /* Thermal management */
3410 gen_spr_thrm(env);
3411 /* Hardware implementation registers */
3412 /* XXX : not implemented */
3413 spr_register(env, SPR_HID0, "HID0",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_generic,
3416 0x00000000);
3417 /* XXX : not implemented */
3418 spr_register(env, SPR_HID1, "HID1",
3419 SPR_NOACCESS, SPR_NOACCESS,
3420 &spr_read_generic, &spr_write_generic,
3421 0x00000000);
3422 /* Memory management */
3423 gen_low_BATs(env);
e1833e1f 3424 init_excp_7x0(env);
d63001d1
JM		 3425 env->dcache_line_size = 32;
3426 env->icache_line_size = 32;
a750fc0b
JM		 3427 /* Allocate hardware IRQ controller */
3428 ppc6xx_irq_init(env);
3429}
3430
3431/* PowerPC 750FX/GX */
3432#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3433#define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3434#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3435#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3436#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 3437#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
a750fc0b
JM		 3438
3439static void init_proc_750fx (CPUPPCState *env)
3440{
3441 gen_spr_ne_601(env);
3442 gen_spr_7xx(env);
3443 /* Time base */
3444 gen_tbl(env);
3445 /* Thermal management */
3446 gen_spr_thrm(env);
3447 /* Hardware implementation registers */
3448 /* XXX : not implemented */
3449 spr_register(env, SPR_HID0, "HID0",
3450 SPR_NOACCESS, SPR_NOACCESS,
3451 &spr_read_generic, &spr_write_generic,
3452 0x00000000);
3453 /* XXX : not implemented */
3454 spr_register(env, SPR_HID1, "HID1",
3455 SPR_NOACCESS, SPR_NOACCESS,
3456 &spr_read_generic, &spr_write_generic,
3457 0x00000000);
3458 /* XXX : not implemented */
3459 spr_register(env, SPR_750_HID2, "HID2",
3460 SPR_NOACCESS, SPR_NOACCESS,
3461 &spr_read_generic, &spr_write_generic,
3462 0x00000000);
3463 /* Memory management */
3464 gen_low_BATs(env);
3465 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3466 gen_high_BATs(env);
e1833e1f 3467 init_excp_750FX(env);
d63001d1
JM		 3468 env->dcache_line_size = 32;
3469 env->icache_line_size = 32;
a750fc0b
JM		 3470 /* Allocate hardware IRQ controller */
3471 ppc6xx_irq_init(env);
3472}
3473
3474/* PowerPC 745/755 */
3475#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3476#define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3477#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3478//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3479#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 3480#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
a750fc0b
JM		 3481
3482static void init_proc_7x5 (CPUPPCState *env)
3483{
3484 gen_spr_ne_601(env);
3485 gen_spr_G2_755(env);
3486 /* Time base */
3487 gen_tbl(env);
3488 /* L2 cache control */
3489 /* XXX : not implemented */
3490 spr_register(env, SPR_ICTC, "ICTC",
3491 SPR_NOACCESS, SPR_NOACCESS,
3492 &spr_read_generic, &spr_write_generic,
3493 0x00000000);
3494 /* XXX : not implemented */
3495 spr_register(env, SPR_L2PMCR, "L2PMCR",
3496 SPR_NOACCESS, SPR_NOACCESS,
3497 &spr_read_generic, &spr_write_generic,
3498 0x00000000);
3499 /* Hardware implementation registers */
3500 /* XXX : not implemented */
3501 spr_register(env, SPR_HID0, "HID0",
3502 SPR_NOACCESS, SPR_NOACCESS,
3503 &spr_read_generic, &spr_write_generic,
3504 0x00000000);
3505 /* XXX : not implemented */
3506 spr_register(env, SPR_HID1, "HID1",
3507 SPR_NOACCESS, SPR_NOACCESS,
3508 &spr_read_generic, &spr_write_generic,
3509 0x00000000);
3510 /* XXX : not implemented */
3511 spr_register(env, SPR_HID2, "HID2",
3512 SPR_NOACCESS, SPR_NOACCESS,
3513 &spr_read_generic, &spr_write_generic,
3514 0x00000000);
3515 /* Memory management */
3516 gen_low_BATs(env);
3517 gen_high_BATs(env);
3518 gen_6xx_7xx_soft_tlb(env, 64, 2);
1c27f8fb 3519 /* XXX: exception vectors ? */
d63001d1
JM		 3520 env->dcache_line_size = 32;
3521 env->icache_line_size = 32;
a750fc0b
JM		 3522 /* Allocate hardware IRQ controller */
3523 ppc6xx_irq_init(env);
d63001d1
JM		 3524#if !defined(CONFIG_USER_ONLY)
3525 /* Hardware reset vector */
3526 env->hreset_vector = 0xFFFFFFFCUL;
3527#endif
a750fc0b
JM		 3528}
3529
3530/* PowerPC 7400 (aka G4) */
3531#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3532 PPC_EXTERN | PPC_MEM_TLBIA | \
3533 PPC_ALTIVEC)
3534#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3535#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3536#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3537#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 3538#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
a750fc0b
JM		 3539
3540static void init_proc_7400 (CPUPPCState *env)
3541{
3542 gen_spr_ne_601(env);
3543 gen_spr_7xx(env);
3544 /* Time base */
3545 gen_tbl(env);
3546 /* 74xx specific SPR */
3547 gen_spr_74xx(env);
3548 /* Thermal management */
3549 gen_spr_thrm(env);
3550 /* Memory management */
3551 gen_low_BATs(env);
e1833e1f 3552 init_excp_7400(env);
d63001d1
JM		 3553 env->dcache_line_size = 32;
3554 env->icache_line_size = 32;
a750fc0b
JM		 3555 /* Allocate hardware IRQ controller */
3556 ppc6xx_irq_init(env);
3557}
3558
3559/* PowerPC 7410 (aka G4) */
3560#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3561 PPC_EXTERN | PPC_MEM_TLBIA | \
3562 PPC_ALTIVEC)
3563#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3564#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3565#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3566#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 3567#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
a750fc0b
JM		 3568
3569static void init_proc_7410 (CPUPPCState *env)
3570{
3571 gen_spr_ne_601(env);
3572 gen_spr_7xx(env);
3573 /* Time base */
3574 gen_tbl(env);
3575 /* 74xx specific SPR */
3576 gen_spr_74xx(env);
3577 /* Thermal management */
3578 gen_spr_thrm(env);
3579 /* L2PMCR */
3580 /* XXX : not implemented */
3581 spr_register(env, SPR_L2PMCR, "L2PMCR",
3582 SPR_NOACCESS, SPR_NOACCESS,
3583 &spr_read_generic, &spr_write_generic,
3584 0x00000000);
3585 /* LDSTDB */
3586 /* XXX : not implemented */
3587 spr_register(env, SPR_LDSTDB, "LDSTDB",
3588 SPR_NOACCESS, SPR_NOACCESS,
3589 &spr_read_generic, &spr_write_generic,
3590 0x00000000);
3591 /* Memory management */
3592 gen_low_BATs(env);
e1833e1f 3593 init_excp_7400(env);
d63001d1
JM		 3594 env->dcache_line_size = 32;
3595 env->icache_line_size = 32;
a750fc0b
JM		 3596 /* Allocate hardware IRQ controller */
3597 ppc6xx_irq_init(env);
3598}
3599
3600/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 3601#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3602 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3603 PPC_ALTIVEC)
3604#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3605#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3606#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3607#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 3608#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
a750fc0b 3609
578bb252 3610__attribute__ (( unused ))
a750fc0b
JM		 3611static void init_proc_7440 (CPUPPCState *env)
3612{
3613 gen_spr_ne_601(env);
3614 gen_spr_7xx(env);
3615 /* Time base */
3616 gen_tbl(env);
3617 /* 74xx specific SPR */
3618 gen_spr_74xx(env);
3619 /* LDSTCR */
3620 /* XXX : not implemented */
3621 spr_register(env, SPR_LDSTCR, "LDSTCR",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 /* ICTRL */
3626 /* XXX : not implemented */
3627 spr_register(env, SPR_ICTRL, "ICTRL",
3628 SPR_NOACCESS, SPR_NOACCESS,
3629 &spr_read_generic, &spr_write_generic,
3630 0x00000000);
3631 /* MSSSR0 */
578bb252 3632 /* XXX : not implemented */
a750fc0b
JM		 3633 spr_register(env, SPR_MSSSR0, "MSSSR0",
3634 SPR_NOACCESS, SPR_NOACCESS,
3635 &spr_read_generic, &spr_write_generic,
3636 0x00000000);
3637 /* PMC */
3638 /* XXX : not implemented */
3639 spr_register(env, SPR_PMC5, "PMC5",
3640 SPR_NOACCESS, SPR_NOACCESS,
3641 &spr_read_generic, &spr_write_generic,
3642 0x00000000);
578bb252 3643 /* XXX : not implemented */
a750fc0b
JM		 3644 spr_register(env, SPR_UPMC5, "UPMC5",
3645 &spr_read_ureg, SPR_NOACCESS,
3646 &spr_read_ureg, SPR_NOACCESS,
3647 0x00000000);
578bb252 3648 /* XXX : not implemented */
a750fc0b
JM		 3649 spr_register(env, SPR_PMC6, "PMC6",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
578bb252 3653 /* XXX : not implemented */
a750fc0b
JM		 3654 spr_register(env, SPR_UPMC6, "UPMC6",
3655 &spr_read_ureg, SPR_NOACCESS,
3656 &spr_read_ureg, SPR_NOACCESS,
3657 0x00000000);
3658 /* Memory management */
3659 gen_low_BATs(env);
578bb252 3660 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 3661 init_excp_7450(env);
d63001d1
JM		 3662 env->dcache_line_size = 32;
3663 env->icache_line_size = 32;
a750fc0b
JM		 3664 /* Allocate hardware IRQ controller */
3665 ppc6xx_irq_init(env);
3666}
a750fc0b
JM		 3667
3668/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 3669#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3670 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3671 PPC_ALTIVEC)
3672#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3673#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3674#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3675#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 3676#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
a750fc0b 3677
578bb252 3678__attribute__ (( unused ))
a750fc0b
JM		 3679static void init_proc_7450 (CPUPPCState *env)
3680{
3681 gen_spr_ne_601(env);
3682 gen_spr_7xx(env);
3683 /* Time base */
3684 gen_tbl(env);
3685 /* 74xx specific SPR */
3686 gen_spr_74xx(env);
3687 /* Level 3 cache control */
3688 gen_l3_ctrl(env);
3689 /* LDSTCR */
3690 /* XXX : not implemented */
3691 spr_register(env, SPR_LDSTCR, "LDSTCR",
3692 SPR_NOACCESS, SPR_NOACCESS,
3693 &spr_read_generic, &spr_write_generic,
3694 0x00000000);
3695 /* ICTRL */
3696 /* XXX : not implemented */
3697 spr_register(env, SPR_ICTRL, "ICTRL",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701 /* MSSSR0 */
578bb252 3702 /* XXX : not implemented */
a750fc0b
JM		 3703 spr_register(env, SPR_MSSSR0, "MSSSR0",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 /* PMC */
3708 /* XXX : not implemented */
3709 spr_register(env, SPR_PMC5, "PMC5",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
578bb252 3713 /* XXX : not implemented */
a750fc0b
JM		 3714 spr_register(env, SPR_UPMC5, "UPMC5",
3715 &spr_read_ureg, SPR_NOACCESS,
3716 &spr_read_ureg, SPR_NOACCESS,
3717 0x00000000);
578bb252 3718 /* XXX : not implemented */
a750fc0b
JM		 3719 spr_register(env, SPR_PMC6, "PMC6",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
578bb252 3723 /* XXX : not implemented */
a750fc0b
JM		 3724 spr_register(env, SPR_UPMC6, "UPMC6",
3725 &spr_read_ureg, SPR_NOACCESS,
3726 &spr_read_ureg, SPR_NOACCESS,
3727 0x00000000);
3728 /* Memory management */
3729 gen_low_BATs(env);
578bb252 3730 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3731 init_excp_7450(env);
d63001d1
JM		 3732 env->dcache_line_size = 32;
3733 env->icache_line_size = 32;
a750fc0b
JM		 3734 /* Allocate hardware IRQ controller */
3735 ppc6xx_irq_init(env);
3736}
a750fc0b
JM		 3737
3738/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 3739#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3740 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3741 PPC_ALTIVEC)
3742#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3743#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3744#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3745#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 3746#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
a750fc0b 3747
578bb252 3748__attribute__ (( unused ))
a750fc0b
JM		 3749static void init_proc_7445 (CPUPPCState *env)
3750{
3751 gen_spr_ne_601(env);
3752 gen_spr_7xx(env);
3753 /* Time base */
3754 gen_tbl(env);
3755 /* 74xx specific SPR */
3756 gen_spr_74xx(env);
3757 /* LDSTCR */
3758 /* XXX : not implemented */
3759 spr_register(env, SPR_LDSTCR, "LDSTCR",
3760 SPR_NOACCESS, SPR_NOACCESS,
3761 &spr_read_generic, &spr_write_generic,
3762 0x00000000);
3763 /* ICTRL */
3764 /* XXX : not implemented */
3765 spr_register(env, SPR_ICTRL, "ICTRL",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_generic,
3768 0x00000000);
3769 /* MSSSR0 */
578bb252 3770 /* XXX : not implemented */
a750fc0b
JM		 3771 spr_register(env, SPR_MSSSR0, "MSSSR0",
3772 SPR_NOACCESS, SPR_NOACCESS,
3773 &spr_read_generic, &spr_write_generic,
3774 0x00000000);
3775 /* PMC */
3776 /* XXX : not implemented */
3777 spr_register(env, SPR_PMC5, "PMC5",
3778 SPR_NOACCESS, SPR_NOACCESS,
3779 &spr_read_generic, &spr_write_generic,
3780 0x00000000);
578bb252 3781 /* XXX : not implemented */
a750fc0b
JM		 3782 spr_register(env, SPR_UPMC5, "UPMC5",
3783 &spr_read_ureg, SPR_NOACCESS,
3784 &spr_read_ureg, SPR_NOACCESS,
3785 0x00000000);
578bb252 3786 /* XXX : not implemented */
a750fc0b
JM		 3787 spr_register(env, SPR_PMC6, "PMC6",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
578bb252 3791 /* XXX : not implemented */
a750fc0b
JM		 3792 spr_register(env, SPR_UPMC6, "UPMC6",
3793 &spr_read_ureg, SPR_NOACCESS,
3794 &spr_read_ureg, SPR_NOACCESS,
3795 0x00000000);
3796 /* SPRGs */
3797 spr_register(env, SPR_SPRG4, "SPRG4",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_generic,
3800 0x00000000);
3801 spr_register(env, SPR_USPRG4, "USPRG4",
3802 &spr_read_ureg, SPR_NOACCESS,
3803 &spr_read_ureg, SPR_NOACCESS,
3804 0x00000000);
3805 spr_register(env, SPR_SPRG5, "SPRG5",
3806 SPR_NOACCESS, SPR_NOACCESS,
3807 &spr_read_generic, &spr_write_generic,
3808 0x00000000);
3809 spr_register(env, SPR_USPRG5, "USPRG5",
3810 &spr_read_ureg, SPR_NOACCESS,
3811 &spr_read_ureg, SPR_NOACCESS,
3812 0x00000000);
3813 spr_register(env, SPR_SPRG6, "SPRG6",
3814 SPR_NOACCESS, SPR_NOACCESS,
3815 &spr_read_generic, &spr_write_generic,
3816 0x00000000);
3817 spr_register(env, SPR_USPRG6, "USPRG6",
3818 &spr_read_ureg, SPR_NOACCESS,
3819 &spr_read_ureg, SPR_NOACCESS,
3820 0x00000000);
3821 spr_register(env, SPR_SPRG7, "SPRG7",
3822 SPR_NOACCESS, SPR_NOACCESS,
3823 &spr_read_generic, &spr_write_generic,
3824 0x00000000);
3825 spr_register(env, SPR_USPRG7, "USPRG7",
3826 &spr_read_ureg, SPR_NOACCESS,
3827 &spr_read_ureg, SPR_NOACCESS,
3828 0x00000000);
3829 /* Memory management */
3830 gen_low_BATs(env);
3831 gen_high_BATs(env);
578bb252 3832 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3833 init_excp_7450(env);
d63001d1
JM		 3834 env->dcache_line_size = 32;
3835 env->icache_line_size = 32;
a750fc0b
JM		 3836 /* Allocate hardware IRQ controller */
3837 ppc6xx_irq_init(env);
3838}
a750fc0b
JM		 3839
3840/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 3841#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3842 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3843 PPC_ALTIVEC)
3844#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3845#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3846#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3847#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 3848#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
a750fc0b 3849
578bb252 3850__attribute__ (( unused ))
a750fc0b
JM		 3851static void init_proc_7455 (CPUPPCState *env)
3852{
3853 gen_spr_ne_601(env);
3854 gen_spr_7xx(env);
3855 /* Time base */
3856 gen_tbl(env);
3857 /* 74xx specific SPR */
3858 gen_spr_74xx(env);
3859 /* Level 3 cache control */
3860 gen_l3_ctrl(env);
3861 /* LDSTCR */
3862 /* XXX : not implemented */
3863 spr_register(env, SPR_LDSTCR, "LDSTCR",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_generic,
3866 0x00000000);
3867 /* ICTRL */
3868 /* XXX : not implemented */
3869 spr_register(env, SPR_ICTRL, "ICTRL",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, &spr_write_generic,
3872 0x00000000);
3873 /* MSSSR0 */
578bb252 3874 /* XXX : not implemented */
a750fc0b
JM		 3875 spr_register(env, SPR_MSSSR0, "MSSSR0",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
3878 0x00000000);
3879 /* PMC */
3880 /* XXX : not implemented */
3881 spr_register(env, SPR_PMC5, "PMC5",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
578bb252 3885 /* XXX : not implemented */
a750fc0b
JM		 3886 spr_register(env, SPR_UPMC5, "UPMC5",
3887 &spr_read_ureg, SPR_NOACCESS,
3888 &spr_read_ureg, SPR_NOACCESS,
3889 0x00000000);
578bb252 3890 /* XXX : not implemented */
a750fc0b
JM		 3891 spr_register(env, SPR_PMC6, "PMC6",
3892 SPR_NOACCESS, SPR_NOACCESS,
3893 &spr_read_generic, &spr_write_generic,
3894 0x00000000);
578bb252 3895 /* XXX : not implemented */
a750fc0b
JM		 3896 spr_register(env, SPR_UPMC6, "UPMC6",
3897 &spr_read_ureg, SPR_NOACCESS,
3898 &spr_read_ureg, SPR_NOACCESS,
3899 0x00000000);
3900 /* SPRGs */
3901 spr_register(env, SPR_SPRG4, "SPRG4",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 spr_register(env, SPR_USPRG4, "USPRG4",
3906 &spr_read_ureg, SPR_NOACCESS,
3907 &spr_read_ureg, SPR_NOACCESS,
3908 0x00000000);
3909 spr_register(env, SPR_SPRG5, "SPRG5",
3910 SPR_NOACCESS, SPR_NOACCESS,
3911 &spr_read_generic, &spr_write_generic,
3912 0x00000000);
3913 spr_register(env, SPR_USPRG5, "USPRG5",
3914 &spr_read_ureg, SPR_NOACCESS,
3915 &spr_read_ureg, SPR_NOACCESS,
3916 0x00000000);
3917 spr_register(env, SPR_SPRG6, "SPRG6",
3918 SPR_NOACCESS, SPR_NOACCESS,
3919 &spr_read_generic, &spr_write_generic,
3920 0x00000000);
3921 spr_register(env, SPR_USPRG6, "USPRG6",
3922 &spr_read_ureg, SPR_NOACCESS,
3923 &spr_read_ureg, SPR_NOACCESS,
3924 0x00000000);
3925 spr_register(env, SPR_SPRG7, "SPRG7",
3926 SPR_NOACCESS, SPR_NOACCESS,
3927 &spr_read_generic, &spr_write_generic,
3928 0x00000000);
3929 spr_register(env, SPR_USPRG7, "USPRG7",
3930 &spr_read_ureg, SPR_NOACCESS,
3931 &spr_read_ureg, SPR_NOACCESS,
3932 0x00000000);
3933 /* Memory management */
3934 gen_low_BATs(env);
3935 gen_high_BATs(env);
578bb252 3936 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3937 init_excp_7450(env);
d63001d1
JM		 3938 env->dcache_line_size = 32;
3939 env->icache_line_size = 32;
a750fc0b
JM		 3940 /* Allocate hardware IRQ controller */
3941 ppc6xx_irq_init(env);
3942}
a750fc0b
JM		 3943
3944#if defined (TARGET_PPC64)
d63001d1 3945#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
12de9a39
JM		 3946 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3947 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3948 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
a750fc0b 3949/* PowerPC 970 */
d63001d1 3950#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 3951 PPC_64B | PPC_ALTIVEC | \
12de9a39 3952 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 3953#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 3954#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 3955//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3956#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 3957#define POWERPC_BFDM_970 (bfd_mach_ppc64)
a750fc0b
JM		 3958
3959static void init_proc_970 (CPUPPCState *env)
3960{
3961 gen_spr_ne_601(env);
3962 gen_spr_7xx(env);
3963 /* Time base */
3964 gen_tbl(env);
3965 /* Hardware implementation registers */
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_HID0, "HID0",
3968 SPR_NOACCESS, SPR_NOACCESS,
06403421 3969 &spr_read_generic, &spr_write_clear,
d63001d1 3970 0x60000000);
a750fc0b
JM		 3971 /* XXX : not implemented */
3972 spr_register(env, SPR_HID1, "HID1",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_generic,
3975 0x00000000);
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_750_HID2, "HID2",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
e57448f1
JM		 3981 /* XXX : not implemented */
3982 spr_register(env, SPR_970_HID5, "HID5",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985#if defined(CONFIG_USER_ONLY)
3986 0x00000080
3987#else
3988 0x00000000
3989#endif
3990 );
a750fc0b
JM		 3991 /* Memory management */
3992 /* XXX: not correct */
3993 gen_low_BATs(env);
12de9a39
JM		 3994 /* XXX : not implemented */
3995 spr_register(env, SPR_MMUCFG, "MMUCFG",
3996 SPR_NOACCESS, SPR_NOACCESS,
3997 &spr_read_generic, SPR_NOACCESS,
3998 0x00000000); /* TOFIX */
3999 /* XXX : not implemented */
4000 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4001 SPR_NOACCESS, SPR_NOACCESS,
4002 &spr_read_generic, &spr_write_generic,
4003 0x00000000); /* TOFIX */
4004 spr_register(env, SPR_HIOR, "SPR_HIOR",
4005 SPR_NOACCESS, SPR_NOACCESS,
4006 &spr_read_generic, &spr_write_generic,
4007 0xFFF00000); /* XXX: This is a hack */
4008#if !defined(CONFIG_USER_ONLY)
4009 env->excp_prefix = 0xFFF00000;
a750fc0b 4010#endif
12de9a39 4011 env->slb_nr = 32;
e1833e1f 4012 init_excp_970(env);
d63001d1
JM		 4013 env->dcache_line_size = 128;
4014 env->icache_line_size = 128;
a750fc0b
JM		 4015 /* Allocate hardware IRQ controller */
4016 ppc970_irq_init(env);
4017}
a750fc0b
JM		 4018
4019/* PowerPC 970FX (aka G5) */
d63001d1 4020#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4021 PPC_64B | PPC_ALTIVEC | \
12de9a39 4022 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4023#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 4024#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 4025#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4026#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 4027#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
a750fc0b
JM		 4028
4029static void init_proc_970FX (CPUPPCState *env)
4030{
4031 gen_spr_ne_601(env);
4032 gen_spr_7xx(env);
4033 /* Time base */
4034 gen_tbl(env);
4035 /* Hardware implementation registers */
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_HID0, "HID0",
4038 SPR_NOACCESS, SPR_NOACCESS,
06403421 4039 &spr_read_generic, &spr_write_clear,
d63001d1 4040 0x60000000);
a750fc0b
JM		 4041 /* XXX : not implemented */
4042 spr_register(env, SPR_HID1, "HID1",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_generic,
4045 0x00000000);
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_750_HID2, "HID2",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
d63001d1
JM		 4051 /* XXX : not implemented */
4052 spr_register(env, SPR_970_HID5, "HID5",
4053 SPR_NOACCESS, SPR_NOACCESS,
4054 &spr_read_generic, &spr_write_generic,
e57448f1
JM		 4055#if defined(CONFIG_USER_ONLY)
4056 0x00000080
4057#else
4058 0x00000000
4059#endif
4060 );
a750fc0b
JM		 4061 /* Memory management */
4062 /* XXX: not correct */
4063 gen_low_BATs(env);
12de9a39
JM		 4064 /* XXX : not implemented */
4065 spr_register(env, SPR_MMUCFG, "MMUCFG",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, SPR_NOACCESS,
4068 0x00000000); /* TOFIX */
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000); /* TOFIX */
4074 spr_register(env, SPR_HIOR, "SPR_HIOR",
4075 SPR_NOACCESS, SPR_NOACCESS,
4076 &spr_read_generic, &spr_write_generic,
4077 0xFFF00000); /* XXX: This is a hack */
4078#if !defined(CONFIG_USER_ONLY)
4079 env->excp_prefix = 0xFFF00000;
a750fc0b 4080#endif
12de9a39 4081 env->slb_nr = 32;
e1833e1f 4082 init_excp_970(env);
d63001d1
JM		 4083 env->dcache_line_size = 128;
4084 env->icache_line_size = 128;
a750fc0b
JM		 4085 /* Allocate hardware IRQ controller */
4086 ppc970_irq_init(env);
4087}
a750fc0b
JM		 4088
4089/* PowerPC 970 GX */
d63001d1 4090#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4091 PPC_64B | PPC_ALTIVEC | \
12de9a39 4092 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4093#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 4094#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 4095#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4096#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 4097#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
a750fc0b
JM		 4098
4099static void init_proc_970GX (CPUPPCState *env)
4100{
4101 gen_spr_ne_601(env);
4102 gen_spr_7xx(env);
4103 /* Time base */
4104 gen_tbl(env);
4105 /* Hardware implementation registers */
4106 /* XXX : not implemented */
4107 spr_register(env, SPR_HID0, "HID0",
4108 SPR_NOACCESS, SPR_NOACCESS,
06403421 4109 &spr_read_generic, &spr_write_clear,
d63001d1 4110 0x60000000);
a750fc0b
JM		 4111 /* XXX : not implemented */
4112 spr_register(env, SPR_HID1, "HID1",
4113 SPR_NOACCESS, SPR_NOACCESS,
4114 &spr_read_generic, &spr_write_generic,
4115 0x00000000);
4116 /* XXX : not implemented */
4117 spr_register(env, SPR_750_HID2, "HID2",
4118 SPR_NOACCESS, SPR_NOACCESS,
4119 &spr_read_generic, &spr_write_generic,
4120 0x00000000);
d63001d1
JM		 4121 /* XXX : not implemented */
4122 spr_register(env, SPR_970_HID5, "HID5",
4123 SPR_NOACCESS, SPR_NOACCESS,
4124 &spr_read_generic, &spr_write_generic,
e57448f1
JM		 4125#if defined(CONFIG_USER_ONLY)
4126 0x00000080
4127#else
4128 0x00000000
4129#endif
4130 );
a750fc0b
JM		 4131 /* Memory management */
4132 /* XXX: not correct */
4133 gen_low_BATs(env);
12de9a39
JM		 4134 /* XXX : not implemented */
4135 spr_register(env, SPR_MMUCFG, "MMUCFG",
4136 SPR_NOACCESS, SPR_NOACCESS,
4137 &spr_read_generic, SPR_NOACCESS,
4138 0x00000000); /* TOFIX */
4139 /* XXX : not implemented */
4140 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4141 SPR_NOACCESS, SPR_NOACCESS,
4142 &spr_read_generic, &spr_write_generic,
4143 0x00000000); /* TOFIX */
4144 spr_register(env, SPR_HIOR, "SPR_HIOR",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0xFFF00000); /* XXX: This is a hack */
4148#if !defined(CONFIG_USER_ONLY)
4149 env->excp_prefix = 0xFFF00000;
a750fc0b 4150#endif
12de9a39 4151 env->slb_nr = 32;
e1833e1f 4152 init_excp_970(env);
d63001d1
JM		 4153 env->dcache_line_size = 128;
4154 env->icache_line_size = 128;
a750fc0b
JM		 4155 /* Allocate hardware IRQ controller */
4156 ppc970_irq_init(env);
4157}
a750fc0b
JM		 4158
4159/* PowerPC 620 */
a750fc0b
JM		 4160#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4161 PPC_64B | PPC_SLBI)
4162#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4163#define POWERPC_MMU_620 (POWERPC_MMU_64B)
4164#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4165#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
237c0af0 4166#define POWERPC_BFDM_620 (bfd_mach_ppc64)
a750fc0b 4167
578bb252 4168__attribute__ (( unused ))
a750fc0b
JM		 4169static void init_proc_620 (CPUPPCState *env)
4170{
4171 gen_spr_ne_601(env);
4172 gen_spr_620(env);
4173 /* Time base */
4174 gen_tbl(env);
4175 /* Hardware implementation registers */
4176 /* XXX : not implemented */
4177 spr_register(env, SPR_HID0, "HID0",
4178 SPR_NOACCESS, SPR_NOACCESS,
4179 &spr_read_generic, &spr_write_generic,
4180 0x00000000);
4181 /* Memory management */
4182 gen_low_BATs(env);
4183 gen_high_BATs(env);
e1833e1f 4184 init_excp_620(env);
d63001d1
JM		 4185 env->dcache_line_size = 64;
4186 env->icache_line_size = 64;
a750fc0b
JM		 4187 /* XXX: TODO: initialize internal interrupt controller */
4188}
a750fc0b
JM		 4189#endif /* defined (TARGET_PPC64) */
4190
4191/* Default 32 bits PowerPC target will be 604 */
4192#define CPU_POWERPC_PPC32 CPU_POWERPC_604
4193#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4194#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4195#define POWERPC_MMU_PPC32 POWERPC_MMU_604
4196#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4197#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4198#define init_proc_PPC32 init_proc_604
237c0af0 4199#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
a750fc0b
JM		 4200
4201/* Default 64 bits PowerPC target will be 970 FX */
4202#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4203#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4204#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4205#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4206#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4207#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4208#define init_proc_PPC64 init_proc_970FX
237c0af0 4209#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
a750fc0b
JM		 4210
4211/* Default PowerPC target will be PowerPC 32 */
4212#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 4213#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4214#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4215#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4216#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4217#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4218#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4219#define init_proc_DEFAULT init_proc_PPC64
237c0af0 4220#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
a750fc0b 4221#else
d12f4c38
JM		 4222#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4223#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4224#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4225#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4226#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4227#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4228#define init_proc_DEFAULT init_proc_PPC32
237c0af0 4229#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
a750fc0b
JM		 4230#endif
4231
4232/*****************************************************************************/
4233/* PVR definitions for most known PowerPC */
4234enum {
4235 /* PowerPC 401 family */
4236 /* Generic PowerPC 401 */
4237#define CPU_POWERPC_401 CPU_POWERPC_401G2
4238 /* PowerPC 401 cores */
4239 CPU_POWERPC_401A1 = 0x00210000,
4240 CPU_POWERPC_401B2 = 0x00220000,
4241#if 0
4242 CPU_POWERPC_401B3 = xxx,
4243#endif
4244 CPU_POWERPC_401C2 = 0x00230000,
4245 CPU_POWERPC_401D2 = 0x00240000,
4246 CPU_POWERPC_401E2 = 0x00250000,
4247 CPU_POWERPC_401F2 = 0x00260000,
4248 CPU_POWERPC_401G2 = 0x00270000,
4249 /* PowerPC 401 microcontrolers */
4250#if 0
4251 CPU_POWERPC_401GF = xxx,
4252#endif
4253#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4254 /* IBM Processor for Network Resources */
4255 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4256#if 0
4257 CPU_POWERPC_XIPCHIP = xxx,
4258#endif
4259 /* PowerPC 403 family */
4260 /* Generic PowerPC 403 */
4261#define CPU_POWERPC_403 CPU_POWERPC_403GC
4262 /* PowerPC 403 microcontrollers */
4263 CPU_POWERPC_403GA = 0x00200011,
4264 CPU_POWERPC_403GB = 0x00200100,
4265 CPU_POWERPC_403GC = 0x00200200,
4266 CPU_POWERPC_403GCX = 0x00201400,
4267#if 0
4268 CPU_POWERPC_403GP = xxx,
4269#endif
4270 /* PowerPC 405 family */
4271 /* Generic PowerPC 405 */
4272#define CPU_POWERPC_405 CPU_POWERPC_405D4
4273 /* PowerPC 405 cores */
4274#if 0
4275 CPU_POWERPC_405A3 = xxx,
4276#endif
4277#if 0
4278 CPU_POWERPC_405A4 = xxx,
4279#endif
4280#if 0
4281 CPU_POWERPC_405B3 = xxx,
4282#endif
4283#if 0
4284 CPU_POWERPC_405B4 = xxx,
4285#endif
4286#if 0
4287 CPU_POWERPC_405C3 = xxx,
4288#endif
4289#if 0
4290 CPU_POWERPC_405C4 = xxx,
4291#endif
4292 CPU_POWERPC_405D2 = 0x20010000,
4293#if 0
4294 CPU_POWERPC_405D3 = xxx,
4295#endif
4296 CPU_POWERPC_405D4 = 0x41810000,
4297#if 0
4298 CPU_POWERPC_405D5 = xxx,
4299#endif
4300#if 0
4301 CPU_POWERPC_405E4 = xxx,
4302#endif
4303#if 0
4304 CPU_POWERPC_405F4 = xxx,
4305#endif
4306#if 0
4307 CPU_POWERPC_405F5 = xxx,
4308#endif
4309#if 0
4310 CPU_POWERPC_405F6 = xxx,
4311#endif
4312 /* PowerPC 405 microcontrolers */
4313 /* XXX: missing 0x200108a0 */
4314#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4315 CPU_POWERPC_405CRa = 0x40110041,
4316 CPU_POWERPC_405CRb = 0x401100C5,
4317 CPU_POWERPC_405CRc = 0x40110145,
4318 CPU_POWERPC_405EP = 0x51210950,
4319#if 0
4320 CPU_POWERPC_405EXr = xxx,
4321#endif
4322 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4323#if 0
4324 CPU_POWERPC_405FX = xxx,
4325#endif
4326#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4327 CPU_POWERPC_405GPa = 0x40110000,
4328 CPU_POWERPC_405GPb = 0x40110040,
4329 CPU_POWERPC_405GPc = 0x40110082,
4330 CPU_POWERPC_405GPd = 0x401100C4,
4331#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4332 CPU_POWERPC_405GPR = 0x50910951,
4333#if 0
4334 CPU_POWERPC_405H = xxx,
4335#endif
4336#if 0
4337 CPU_POWERPC_405L = xxx,
4338#endif
4339 CPU_POWERPC_405LP = 0x41F10000,
4340#if 0
4341 CPU_POWERPC_405PM = xxx,
4342#endif
4343#if 0
4344 CPU_POWERPC_405PS = xxx,
4345#endif
4346#if 0
4347 CPU_POWERPC_405S = xxx,
4348#endif
4349 /* IBM network processors */
4350 CPU_POWERPC_NPE405H = 0x414100C0,
4351 CPU_POWERPC_NPE405H2 = 0x41410140,
4352 CPU_POWERPC_NPE405L = 0x416100C0,
4353 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4354#if 0
4355 CPU_POWERPC_NPCxx1 = xxx,
4356#endif
4357#if 0
4358 CPU_POWERPC_NPR161 = xxx,
4359#endif
4360#if 0
4361 CPU_POWERPC_LC77700 = xxx,
4362#endif
4363 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4364#if 0
4365 CPU_POWERPC_STB01000 = xxx,
4366#endif
4367#if 0
4368 CPU_POWERPC_STB01010 = xxx,
4369#endif
4370#if 0
4371 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4372#endif
4373 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4374#if 0
4375 CPU_POWERPC_STB043 = xxx,
4376#endif
4377#if 0
4378 CPU_POWERPC_STB045 = xxx,
4379#endif
4380 CPU_POWERPC_STB04 = 0x41810000,
4381 CPU_POWERPC_STB25 = 0x51510950,
4382#if 0
4383 CPU_POWERPC_STB130 = xxx,
4384#endif
4385 /* Xilinx cores */
4386 CPU_POWERPC_X2VP4 = 0x20010820,
4387#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4388 CPU_POWERPC_X2VP20 = 0x20010860,
4389#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4390#if 0
4391 CPU_POWERPC_ZL10310 = xxx,
4392#endif
4393#if 0
4394 CPU_POWERPC_ZL10311 = xxx,
4395#endif
4396#if 0
4397 CPU_POWERPC_ZL10320 = xxx,
4398#endif
4399#if 0
4400 CPU_POWERPC_ZL10321 = xxx,
4401#endif
4402 /* PowerPC 440 family */
4403 /* Generic PowerPC 440 */
4404#define CPU_POWERPC_440 CPU_POWERPC_440GXf
4405 /* PowerPC 440 cores */
4406#if 0
4407 CPU_POWERPC_440A4 = xxx,
4408#endif
4409#if 0
4410 CPU_POWERPC_440A5 = xxx,
4411#endif
4412#if 0
4413 CPU_POWERPC_440B4 = xxx,
4414#endif
4415#if 0
4416 CPU_POWERPC_440F5 = xxx,
4417#endif
4418#if 0
4419 CPU_POWERPC_440G5 = xxx,
4420#endif
4421#if 0
4422 CPU_POWERPC_440H4 = xxx,
4423#endif
4424#if 0
4425 CPU_POWERPC_440H6 = xxx,
4426#endif
4427 /* PowerPC 440 microcontrolers */
4428#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4429 CPU_POWERPC_440EPa = 0x42221850,
4430 CPU_POWERPC_440EPb = 0x422218D3,
4431#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4432 CPU_POWERPC_440GPb = 0x40120440,
4433 CPU_POWERPC_440GPc = 0x40120481,
4434#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4435#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4436 CPU_POWERPC_440GRX = 0x200008D0,
4437#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4438#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4439 CPU_POWERPC_440GXa = 0x51B21850,
4440 CPU_POWERPC_440GXb = 0x51B21851,
4441 CPU_POWERPC_440GXc = 0x51B21892,
4442 CPU_POWERPC_440GXf = 0x51B21894,
4443#if 0
4444 CPU_POWERPC_440S = xxx,
4445#endif
4446 CPU_POWERPC_440SP = 0x53221850,
4447 CPU_POWERPC_440SP2 = 0x53221891,
4448 CPU_POWERPC_440SPE = 0x53421890,
4449 /* PowerPC 460 family */
4450#if 0
4451 /* Generic PowerPC 464 */
4452#define CPU_POWERPC_464 CPU_POWERPC_464H90
4453#endif
4454 /* PowerPC 464 microcontrolers */
4455#if 0
4456 CPU_POWERPC_464H90 = xxx,
4457#endif
4458#if 0
4459 CPU_POWERPC_464H90FP = xxx,
4460#endif
4461 /* Freescale embedded PowerPC cores */
4462 /* e200 family */
4463#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4464#if 0
4465 CPU_POWERPC_e200z0 = xxx,
4466#endif
4467#if 0
4468 CPU_POWERPC_e200z3 = xxx,
4469#endif
4470 CPU_POWERPC_e200z5 = 0x81000000,
4471 CPU_POWERPC_e200z6 = 0x81120000,
4472 /* e300 family */
4473#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4474 CPU_POWERPC_e300c1 = 0x00830000,
4475 CPU_POWERPC_e300c2 = 0x00840000,
4476 CPU_POWERPC_e300c3 = 0x00850000,
4477 /* e500 family */
4478#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4479 CPU_POWERPC_e500_v11 = 0x80200010,
4480 CPU_POWERPC_e500_v12 = 0x80200020,
4481 CPU_POWERPC_e500_v21 = 0x80210010,
4482 CPU_POWERPC_e500_v22 = 0x80210020,
4483#if 0
4484 CPU_POWERPC_e500mc = xxx,
4485#endif
4486 /* e600 family */
4487 CPU_POWERPC_e600 = 0x80040010,
4488 /* PowerPC MPC 5xx cores */
4489 CPU_POWERPC_5xx = 0x00020020,
4490 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4491 CPU_POWERPC_8xx = 0x00500000,
4492 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4493 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4494 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4495 CPU_POWERPC_827x = 0x80822013,
4496 /* PowerPC 6xx cores */
4497 CPU_POWERPC_601 = 0x00010001,
4498 CPU_POWERPC_601a = 0x00010002,
4499 CPU_POWERPC_602 = 0x00050100,
4500 CPU_POWERPC_603 = 0x00030100,
4501#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4502 CPU_POWERPC_603E_v11 = 0x00060101,
4503 CPU_POWERPC_603E_v12 = 0x00060102,
4504 CPU_POWERPC_603E_v13 = 0x00060103,
4505 CPU_POWERPC_603E_v14 = 0x00060104,
4506 CPU_POWERPC_603E_v22 = 0x00060202,
4507 CPU_POWERPC_603E_v3 = 0x00060300,
4508 CPU_POWERPC_603E_v4 = 0x00060400,
4509 CPU_POWERPC_603E_v41 = 0x00060401,
4510 CPU_POWERPC_603E7t = 0x00071201,
4511 CPU_POWERPC_603E7v = 0x00070100,
4512 CPU_POWERPC_603E7v1 = 0x00070101,
4513 CPU_POWERPC_603E7v2 = 0x00070201,
4514 CPU_POWERPC_603E7 = 0x00070200,
4515 CPU_POWERPC_603P = 0x00070000,
4516#define CPU_POWERPC_603R CPU_POWERPC_603E7t
4517 CPU_POWERPC_G2 = 0x00810011,
4518#if 0 // Linux pretends the MSB is zero...
4519 CPU_POWERPC_G2H4 = 0x80811010,
4520 CPU_POWERPC_G2gp = 0x80821010,
4521 CPU_POWERPC_G2ls = 0x90810010,
4522 CPU_POWERPC_G2LE = 0x80820010,
4523 CPU_POWERPC_G2LEgp = 0x80822010,
4524 CPU_POWERPC_G2LEls = 0xA0822010,
4525#else
4526 CPU_POWERPC_G2H4 = 0x00811010,
4527 CPU_POWERPC_G2gp = 0x00821010,
4528 CPU_POWERPC_G2ls = 0x10810010,
4529 CPU_POWERPC_G2LE = 0x00820010,
4530 CPU_POWERPC_G2LEgp = 0x00822010,
4531 CPU_POWERPC_G2LEls = 0x20822010,
4532#endif
4533 CPU_POWERPC_604 = 0x00040103,
4534#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4535 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4536 CPU_POWERPC_604E_v22 = 0x00090202,
4537 CPU_POWERPC_604E_v24 = 0x00090204,
4538 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4539#if 0
4540 CPU_POWERPC_604EV = xxx,
4541#endif
4542 /* PowerPC 740/750 cores (aka G3) */
4543 /* XXX: missing 0x00084202 */
4544#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4545 CPU_POWERPC_7x0_v20 = 0x00080200,
4546 CPU_POWERPC_7x0_v21 = 0x00080201,
4547 CPU_POWERPC_7x0_v22 = 0x00080202,
4548 CPU_POWERPC_7x0_v30 = 0x00080300,
4549 CPU_POWERPC_7x0_v31 = 0x00080301,
4550 CPU_POWERPC_740E = 0x00080100,
4551 CPU_POWERPC_7x0P = 0x10080000,
4552 /* XXX: missing 0x00087010 (CL ?) */
4553 CPU_POWERPC_750CL = 0x00087200,
4554#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4555 CPU_POWERPC_750CX_v21 = 0x00082201,
4556 CPU_POWERPC_750CX_v22 = 0x00082202,
4557#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4558 CPU_POWERPC_750CXE_v21 = 0x00082211,
4559 CPU_POWERPC_750CXE_v22 = 0x00082212,
4560 CPU_POWERPC_750CXE_v23 = 0x00082213,
4561 CPU_POWERPC_750CXE_v24 = 0x00082214,
4562 CPU_POWERPC_750CXE_v24b = 0x00083214,
4563 CPU_POWERPC_750CXE_v31 = 0x00083211,
4564 CPU_POWERPC_750CXE_v31b = 0x00083311,
4565 CPU_POWERPC_750CXR = 0x00083410,
4566 CPU_POWERPC_750E = 0x00080200,
4567 CPU_POWERPC_750FL = 0x700A0203,
4568#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4569 CPU_POWERPC_750FX_v10 = 0x70000100,
4570 CPU_POWERPC_750FX_v20 = 0x70000200,
4571 CPU_POWERPC_750FX_v21 = 0x70000201,
4572 CPU_POWERPC_750FX_v22 = 0x70000202,
4573 CPU_POWERPC_750FX_v23 = 0x70000203,
4574 CPU_POWERPC_750GL = 0x70020102,
4575#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4576 CPU_POWERPC_750GX_v10 = 0x70020100,
4577 CPU_POWERPC_750GX_v11 = 0x70020101,
4578 CPU_POWERPC_750GX_v12 = 0x70020102,
4579#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4580 CPU_POWERPC_750L_v22 = 0x00088202,
4581 CPU_POWERPC_750L_v30 = 0x00088300,
4582 CPU_POWERPC_750L_v32 = 0x00088302,
4583 /* PowerPC 745/755 cores */
4584#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4585 CPU_POWERPC_7x5_v10 = 0x00083100,
4586 CPU_POWERPC_7x5_v11 = 0x00083101,
4587 CPU_POWERPC_7x5_v20 = 0x00083200,
4588 CPU_POWERPC_7x5_v21 = 0x00083201,
4589 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4590 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4591 CPU_POWERPC_7x5_v24 = 0x00083204,
4592 CPU_POWERPC_7x5_v25 = 0x00083205,
4593 CPU_POWERPC_7x5_v26 = 0x00083206,
4594 CPU_POWERPC_7x5_v27 = 0x00083207,
4595 CPU_POWERPC_7x5_v28 = 0x00083208,
4596#if 0
4597 CPU_POWERPC_7x5P = xxx,
4598#endif
4599 /* PowerPC 74xx cores (aka G4) */
4600 /* XXX: missing 0x000C1101 */
4601#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4602 CPU_POWERPC_7400_v10 = 0x000C0100,
4603 CPU_POWERPC_7400_v11 = 0x000C0101,
4604 CPU_POWERPC_7400_v20 = 0x000C0200,
4605 CPU_POWERPC_7400_v22 = 0x000C0202,
4606 CPU_POWERPC_7400_v26 = 0x000C0206,
4607 CPU_POWERPC_7400_v27 = 0x000C0207,
4608 CPU_POWERPC_7400_v28 = 0x000C0208,
4609 CPU_POWERPC_7400_v29 = 0x000C0209,
4610#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4611 CPU_POWERPC_7410_v10 = 0x800C1100,
4612 CPU_POWERPC_7410_v11 = 0x800C1101,
4613 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4614 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4615 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4616#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4617 CPU_POWERPC_7448_v10 = 0x80040100,
4618 CPU_POWERPC_7448_v11 = 0x80040101,
4619 CPU_POWERPC_7448_v20 = 0x80040200,
4620 CPU_POWERPC_7448_v21 = 0x80040201,
4621#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4622 CPU_POWERPC_7450_v10 = 0x80000100,
4623 CPU_POWERPC_7450_v11 = 0x80000101,
4624 CPU_POWERPC_7450_v12 = 0x80000102,
4625 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4626 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4627 CPU_POWERPC_74x1 = 0x80000203,
4628 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4629 /* XXX: missing 0x80010200 */
4630#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4631 CPU_POWERPC_74x5_v10 = 0x80010100,
4632 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4633 CPU_POWERPC_74x5_v32 = 0x80010302,
4634 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4635 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4636#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4637 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4638 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4639 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4640 /* 64 bits PowerPC */
00af685f 4641#if defined(TARGET_PPC64)
a750fc0b
JM		 4642 CPU_POWERPC_620 = 0x00140000,
4643 CPU_POWERPC_630 = 0x00400000,
4644 CPU_POWERPC_631 = 0x00410104,
4645 CPU_POWERPC_POWER4 = 0x00350000,
4646 CPU_POWERPC_POWER4P = 0x00380000,
4647 CPU_POWERPC_POWER5 = 0x003A0203,
4648#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4649 CPU_POWERPC_POWER5P = 0x003B0000,
4650#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4651 CPU_POWERPC_POWER6 = 0x003E0000,
4652 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4653 CPU_POWERPC_POWER6A = 0x0F000002,
4654 CPU_POWERPC_970 = 0x00390202,
4655#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4656 CPU_POWERPC_970FX_v10 = 0x00391100,
4657 CPU_POWERPC_970FX_v20 = 0x003C0200,
4658 CPU_POWERPC_970FX_v21 = 0x003C0201,
4659 CPU_POWERPC_970FX_v30 = 0x003C0300,
4660 CPU_POWERPC_970FX_v31 = 0x003C0301,
4661 CPU_POWERPC_970GX = 0x00450000,
4662#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4663 CPU_POWERPC_970MP_v10 = 0x00440100,
4664 CPU_POWERPC_970MP_v11 = 0x00440101,
4665#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4666 CPU_POWERPC_CELL_v10 = 0x00700100,
4667 CPU_POWERPC_CELL_v20 = 0x00700400,
4668 CPU_POWERPC_CELL_v30 = 0x00700500,
4669 CPU_POWERPC_CELL_v31 = 0x00700501,
4670#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4671 CPU_POWERPC_RS64 = 0x00330000,
4672 CPU_POWERPC_RS64II = 0x00340000,
4673 CPU_POWERPC_RS64III = 0x00360000,
4674 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 4675#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 4676 /* Original POWER */
4677 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4678 * POWER2 (RIOS2) & RSC2 (P2SC) here
4679 */
4680#if 0
4681 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4682#endif
4683#if 0
4684 CPU_POWER2 = xxx, /* 0x40000 ? */
4685#endif
4686 /* PA Semi core */
4687 CPU_POWERPC_PA6T = 0x00900000,
4688};
4689
4690/* System version register (used on MPC 8xxx) */
4691enum {
4692 PPC_SVR_8540 = 0x80300000,
4693 PPC_SVR_8541E = 0x807A0010,
4694 PPC_SVR_8543v10 = 0x80320010,
4695 PPC_SVR_8543v11 = 0x80320011,
4696 PPC_SVR_8543v20 = 0x80320020,
4697 PPC_SVR_8543Ev10 = 0x803A0010,
4698 PPC_SVR_8543Ev11 = 0x803A0011,
4699 PPC_SVR_8543Ev20 = 0x803A0020,
4700 PPC_SVR_8545 = 0x80310220,
4701 PPC_SVR_8545E = 0x80390220,
4702 PPC_SVR_8547E = 0x80390120,
4703 PPC_SCR_8548v10 = 0x80310010,
4704 PPC_SCR_8548v11 = 0x80310011,
4705 PPC_SCR_8548v20 = 0x80310020,
4706 PPC_SVR_8548Ev10 = 0x80390010,
4707 PPC_SVR_8548Ev11 = 0x80390011,
4708 PPC_SVR_8548Ev20 = 0x80390020,
4709 PPC_SVR_8555E = 0x80790010,
4710 PPC_SVR_8560v10 = 0x80700010,
4711 PPC_SVR_8560v20 = 0x80700020,
4712};
4713
3fc6c082 4714/*****************************************************************************/
a750fc0b
JM		 4715/* PowerPC CPU definitions */
4716#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4717 { \
4718 .name = _name, \
4719 .pvr = _pvr, \
4720 .pvr_mask = _pvr_mask, \
4721 .insns_flags = glue(POWERPC_INSNS_,_type), \
4722 .msr_mask = glue(POWERPC_MSRM_,_type), \
4723 .mmu_model = glue(POWERPC_MMU_,_type), \
4724 .excp_model = glue(POWERPC_EXCP_,_type), \
4725 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 4726 .bfd_mach = glue(POWERPC_BFDM_,_type), \
a750fc0b
JM		 4727 .init_proc = &glue(init_proc_,_type), \
4728 }
4729
3a607854 4730static ppc_def_t ppc_defs[] = {
a750fc0b
JM		 4731 /* Embedded PowerPC */
4732 /* PowerPC 401 family */
2662a059 4733 /* Generic PowerPC 401 */
a750fc0b
JM		 4734 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4735 /* PowerPC 401 cores */
2662a059 4736 /* PowerPC 401A1 */
a750fc0b
JM		 4737 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4738 /* PowerPC 401B2 */
4739 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
2662a059 4740#if defined (TODO)
a750fc0b
JM		 4741 /* PowerPC 401B3 */
4742 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4743#endif
4744 /* PowerPC 401C2 */
4745 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4746 /* PowerPC 401D2 */
4747 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4748 /* PowerPC 401E2 */
4749 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4750 /* PowerPC 401F2 */
4751 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4752 /* PowerPC 401G2 */
4753 /* XXX: to be checked */
4754 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4755 /* PowerPC 401 microcontrolers */
2662a059 4756#if defined (TODO)
a750fc0b
JM		 4757 /* PowerPC 401GF */
4758 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
3fc6c082 4759#endif
a750fc0b
JM		 4760 /* IOP480 (401 microcontroler) */
4761 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4762 /* IBM Processor for Network Resources */
4763 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
3fc6c082 4764#if defined (TODO)
a750fc0b 4765 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
3fc6c082 4766#endif
a750fc0b
JM		 4767 /* PowerPC 403 family */
4768 /* Generic PowerPC 403 */
4769 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4770 /* PowerPC 403 microcontrolers */
4771 /* PowerPC 403 GA */
4772 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4773 /* PowerPC 403 GB */
4774 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4775 /* PowerPC 403 GC */
4776 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4777 /* PowerPC 403 GCX */
4778 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
3fc6c082 4779#if defined (TODO)
a750fc0b
JM		 4780 /* PowerPC 403 GP */
4781 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
3fc6c082 4782#endif
a750fc0b
JM		 4783 /* PowerPC 405 family */
4784 /* Generic PowerPC 405 */
4785 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4786 /* PowerPC 405 cores */
2662a059 4787#if defined (TODO)
a750fc0b
JM		 4788 /* PowerPC 405 A3 */
4789 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
3a607854 4790#endif
3a607854 4791#if defined (TODO)
a750fc0b
JM		 4792 /* PowerPC 405 A4 */
4793 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
3a607854 4794#endif
3a607854 4795#if defined (TODO)
a750fc0b
JM		 4796 /* PowerPC 405 B3 */
4797 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
3fc6c082
FB		 4798#endif
4799#if defined (TODO)
a750fc0b
JM		 4800 /* PowerPC 405 B4 */
4801 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4802#endif
4803#if defined (TODO)
4804 /* PowerPC 405 C3 */
4805 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4806#endif
4807#if defined (TODO)
4808 /* PowerPC 405 C4 */
4809 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4810#endif
4811 /* PowerPC 405 D2 */
4812 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4813#if defined (TODO)
4814 /* PowerPC 405 D3 */
4815 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4816#endif
4817 /* PowerPC 405 D4 */
4818 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4819#if defined (TODO)
4820 /* PowerPC 405 D5 */
4821 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4822#endif
4823#if defined (TODO)
4824 /* PowerPC 405 E4 */
4825 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4826#endif
4827#if defined (TODO)
4828 /* PowerPC 405 F4 */
4829 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4830#endif
4831#if defined (TODO)
4832 /* PowerPC 405 F5 */
4833 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4834#endif
4835#if defined (TODO)
4836 /* PowerPC 405 F6 */
4837 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4838#endif
4839 /* PowerPC 405 microcontrolers */
4840 /* PowerPC 405 CR */
4841 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4842 /* PowerPC 405 CRa */
4843 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4844 /* PowerPC 405 CRb */
4845 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4846 /* PowerPC 405 CRc */
4847 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4848 /* PowerPC 405 EP */
4849 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4850#if defined(TODO)
4851 /* PowerPC 405 EXr */
4852 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4853#endif
4854 /* PowerPC 405 EZ */
4855 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4856#if defined(TODO)
4857 /* PowerPC 405 FX */
4858 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4859#endif
4860 /* PowerPC 405 GP */
4861 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4862 /* PowerPC 405 GPa */
4863 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4864 /* PowerPC 405 GPb */
4865 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4866 /* PowerPC 405 GPc */
4867 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4868 /* PowerPC 405 GPd */
4869 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4870 /* PowerPC 405 GPe */
4871 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4872 /* PowerPC 405 GPR */
4873 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4874#if defined(TODO)
4875 /* PowerPC 405 H */
4876 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
4877#endif
4878#if defined(TODO)
4879 /* PowerPC 405 L */
4880 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
4881#endif
4882 /* PowerPC 405 LP */
4883 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
4884#if defined(TODO)
4885 /* PowerPC 405 PM */
4886 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
4887#endif
4888#if defined(TODO)
4889 /* PowerPC 405 PS */
4890 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
4891#endif
4892#if defined(TODO)
4893 /* PowerPC 405 S */
4894 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
4895#endif
4896 /* Npe405 H */
4897 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
4898 /* Npe405 H2 */
4899 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
4900 /* Npe405 L */
4901 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
4902 /* Npe4GS3 */
4903 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
4904#if defined (TODO)
4905 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
4906#endif
4907#if defined (TODO)
4908 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
4909#endif
4910#if defined (TODO)
4911 /* PowerPC LC77700 (Sanyo) */
4912 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
4913#endif
4914 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4915#if defined (TODO)
4916 /* STB010000 */
4917 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
4918#endif
4919#if defined (TODO)
4920 /* STB01010 */
4921 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
4922#endif
4923#if defined (TODO)
4924 /* STB0210 */
4925 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
4926#endif
4927 /* STB03xx */
4928 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
4929#if defined (TODO)
4930 /* STB043x */
4931 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
4932#endif
4933#if defined (TODO)
4934 /* STB045x */
4935 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
4936#endif
4937 /* STB04xx */
4938 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
4939 /* STB25xx */
4940 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
4941#if defined (TODO)
4942 /* STB130 */
4943 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
4944#endif
4945 /* Xilinx PowerPC 405 cores */
4946 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
4947 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
4948 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
4949 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
4950#if defined (TODO)
4951 /* Zarlink ZL10310 */
4952 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
4953#endif
4954#if defined (TODO)
4955 /* Zarlink ZL10311 */
4956 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
4957#endif
4958#if defined (TODO)
4959 /* Zarlink ZL10320 */
4960 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
4961#endif
4962#if defined (TODO)
4963 /* Zarlink ZL10321 */
4964 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
4965#endif
4966 /* PowerPC 440 family */
4967 /* Generic PowerPC 440 */
4968 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
4969 /* PowerPC 440 cores */
4970#if defined (TODO)
4971 /* PowerPC 440 A4 */
4972 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
4973#endif
4974#if defined (TODO)
4975 /* PowerPC 440 A5 */
4976 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
4977#endif
4978#if defined (TODO)
4979 /* PowerPC 440 B4 */
4980 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
4981#endif
4982#if defined (TODO)
4983 /* PowerPC 440 G4 */
4984 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
4985#endif
4986#if defined (TODO)
4987 /* PowerPC 440 F5 */
4988 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
4989#endif
4990#if defined (TODO)
4991 /* PowerPC 440 G5 */
4992 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
4993#endif
4994#if defined (TODO)
4995 /* PowerPC 440H4 */
4996 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
4997#endif
4998#if defined (TODO)
4999 /* PowerPC 440H6 */
5000 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5001#endif
5002 /* PowerPC 440 microcontrolers */
5003 /* PowerPC 440 EP */
5004 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5005 /* PowerPC 440 EPa */
5006 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5007 /* PowerPC 440 EPb */
5008 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5009 /* PowerPC 440 EPX */
5010 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5011 /* PowerPC 440 GP */
5012 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5013 /* PowerPC 440 GPb */
5014 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5015 /* PowerPC 440 GPc */
5016 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5017 /* PowerPC 440 GR */
5018 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5019 /* PowerPC 440 GRa */
5020 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5021 /* PowerPC 440 GRX */
5022 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5023 /* PowerPC 440 GX */
5024 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5025 /* PowerPC 440 GXa */
5026 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5027 /* PowerPC 440 GXb */
5028 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5029 /* PowerPC 440 GXc */
5030 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5031 /* PowerPC 440 GXf */
5032 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5033#if defined(TODO)
5034 /* PowerPC 440 S */
5035 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5036#endif
5037 /* PowerPC 440 SP */
5038 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5039 /* PowerPC 440 SP2 */
5040 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5041 /* PowerPC 440 SPE */
5042 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5043 /* PowerPC 460 family */
5044#if defined (TODO)
5045 /* Generic PowerPC 464 */
5046 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5047#endif
5048 /* PowerPC 464 microcontrolers */
5049#if defined (TODO)
5050 /* PowerPC 464H90 */
5051 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5052#endif
5053#if defined (TODO)
5054 /* PowerPC 464H90F */
5055 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5056#endif
5057 /* Freescale embedded PowerPC cores */
5058 /* e200 family */
5059#if defined (TODO)
5060 /* Generic PowerPC e200 core */
5061 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5062#endif
5063#if defined (TODO)
5064 /* PowerPC e200z5 core */
5065 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5066#endif
5067#if defined (TODO)
5068 /* PowerPC e200z6 core */
5069 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5070#endif
5071 /* e300 family */
5072#if defined (TODO)
5073 /* Generic PowerPC e300 core */
5074 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5075#endif
5076#if defined (TODO)
5077 /* PowerPC e300c1 core */
5078 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5079#endif
5080#if defined (TODO)
5081 /* PowerPC e300c2 core */
5082 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5083#endif
5084#if defined (TODO)
5085 /* PowerPC e300c3 core */
5086 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5087#endif
5088 /* e500 family */
5089#if defined (TODO)
5090 /* PowerPC e500 core */
5091 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5092#endif
5093#if defined (TODO)
5094 /* PowerPC e500 v1.1 core */
5095 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5096#endif
5097#if defined (TODO)
5098 /* PowerPC e500 v1.2 core */
5099 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5100#endif
5101#if defined (TODO)
5102 /* PowerPC e500 v2.1 core */
5103 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5104#endif
5105#if defined (TODO)
5106 /* PowerPC e500 v2.2 core */
5107 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5108#endif
5109 /* e600 family */
5110#if defined (TODO)
5111 /* PowerPC e600 core */
5112 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5113#endif
5114 /* PowerPC MPC 5xx cores */
5115#if defined (TODO)
5116 /* PowerPC MPC 5xx */
5117 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5118#endif
5119 /* PowerPC MPC 8xx cores */
5120#if defined (TODO)
5121 /* PowerPC MPC 8xx */
5122 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5123#endif
5124 /* PowerPC MPC 8xxx cores */
5125#if defined (TODO)
5126 /* PowerPC MPC 82xx HIP3 */
5127 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5128#endif
5129#if defined (TODO)
5130 /* PowerPC MPC 82xx HIP4 */
5131 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5132#endif
5133#if defined (TODO)
5134 /* PowerPC MPC 827x */
5135 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5136#endif
5137
5138 /* 32 bits "classic" PowerPC */
5139 /* PowerPC 6xx family */
5140 /* PowerPC 601 */
5141 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5142 /* PowerPC 601v2 */
5143 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5144 /* PowerPC 602 */
5145 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5146 /* PowerPC 603 */
5147 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5148 /* Code name for PowerPC 603 */
5149 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5150 /* PowerPC 603e */
5151 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5152 /* Code name for PowerPC 603e */
5153 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5154 /* PowerPC 603e v1.1 */
5155 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5156 /* PowerPC 603e v1.2 */
5157 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5158 /* PowerPC 603e v1.3 */
5159 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5160 /* PowerPC 603e v1.4 */
5161 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5162 /* PowerPC 603e v2.2 */
5163 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5164 /* PowerPC 603e v3 */
5165 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5166 /* PowerPC 603e v4 */
5167 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5168 /* PowerPC 603e v4.1 */
5169 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5170 /* PowerPC 603e */
5171 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5172 /* PowerPC 603e7t */
5173 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5174 /* PowerPC 603e7v */
5175 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5176 /* Code name for PowerPC 603ev */
5177 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5178 /* PowerPC 603e7v1 */
5179 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5180 /* PowerPC 603e7v2 */
5181 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5182 /* PowerPC 603p */
5183 /* to be checked */
5184 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5185 /* PowerPC 603r */
5186 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5187 /* Code name for PowerPC 603r */
5188 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5189 /* PowerPC G2 core */
5190 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5191 /* PowerPC G2 H4 */
5192 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5193 /* PowerPC G2 GP */
5194 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5195 /* PowerPC G2 LS */
5196 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5197 /* PowerPC G2LE */
5198 /* Same as G2, with little-endian mode support */
5199 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5200 /* PowerPC G2LE GP */
5201 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5202 /* PowerPC G2LE LS */
5203 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5204 /* PowerPC 604 */
5205 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5206 /* PowerPC 604e */
5207 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5208 /* PowerPC 604e v1.0 */
5209 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5210 /* PowerPC 604e v2.2 */
5211 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5212 /* PowerPC 604e v2.4 */
5213 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5214 /* PowerPC 604r */
5215 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5216#if defined(TODO)
5217 /* PowerPC 604ev */
5218 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5219#endif
5220 /* PowerPC 7xx family */
5221 /* Generic PowerPC 740 (G3) */
5222 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5223 /* Generic PowerPC 750 (G3) */
5224 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5225 /* Code name for generic PowerPC 740/750 (G3) */
5226 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5227 /* PowerPC 740/750 is also known as G3 */
5228 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5229 /* PowerPC 740 v2.0 (G3) */
5230 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5231 /* PowerPC 750 v2.0 (G3) */
5232 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5233 /* PowerPC 740 v2.1 (G3) */
5234 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5235 /* PowerPC 750 v2.1 (G3) */
5236 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5237 /* PowerPC 740 v2.2 (G3) */
5238 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5239 /* PowerPC 750 v2.2 (G3) */
5240 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5241 /* PowerPC 740 v3.0 (G3) */
5242 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5243 /* PowerPC 750 v3.0 (G3) */
5244 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5245 /* PowerPC 740 v3.1 (G3) */
5246 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5247 /* PowerPC 750 v3.1 (G3) */
5248 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5249 /* PowerPC 740E (G3) */
5250 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5251 /* PowerPC 740P (G3) */
5252 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5253 /* PowerPC 750P (G3) */
5254 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5255 /* Code name for PowerPC 740P/750P (G3) */
5256 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5257 /* PowerPC 750CL (G3 embedded) */
5258 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5259 /* PowerPC 750CX (G3 embedded) */
5260 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5261 /* PowerPC 750CX v2.1 (G3 embedded) */
5262 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5263 /* PowerPC 750CX v2.2 (G3 embedded) */
5264 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5265 /* PowerPC 750CXe (G3 embedded) */
5266 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5267 /* PowerPC 750CXe v2.1 (G3 embedded) */
5268 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5269 /* PowerPC 750CXe v2.2 (G3 embedded) */
5270 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5271 /* PowerPC 750CXe v2.3 (G3 embedded) */
5272 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5273 /* PowerPC 750CXe v2.4 (G3 embedded) */
5274 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5275 /* PowerPC 750CXe v2.4b (G3 embedded) */
5276 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5277 /* PowerPC 750CXe v3.1 (G3 embedded) */
5278 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5279 /* PowerPC 750CXe v3.1b (G3 embedded) */
5280 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5281 /* PowerPC 750CXr (G3 embedded) */
5282 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5283 /* PowerPC 750E (G3) */
5284 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5285 /* PowerPC 750FL (G3 embedded) */
d12f4c38 5286 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5287 /* PowerPC 750FX (G3 embedded) */
5288 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5289 /* PowerPC 750FX v1.0 (G3 embedded) */
5290 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5291 /* PowerPC 750FX v2.0 (G3 embedded) */
5292 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5293 /* PowerPC 750FX v2.1 (G3 embedded) */
5294 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5295 /* PowerPC 750FX v2.2 (G3 embedded) */
5296 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5297 /* PowerPC 750FX v2.3 (G3 embedded) */
5298 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5299 /* PowerPC 750GL (G3 embedded) */
d12f4c38 5300 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5301 /* PowerPC 750GX (G3 embedded) */
5302 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5303 /* PowerPC 750GX v1.0 (G3 embedded) */
5304 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5305 /* PowerPC 750GX v1.1 (G3 embedded) */
5306 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5307 /* PowerPC 750GX v1.2 (G3 embedded) */
5308 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5309 /* PowerPC 750L (G3 embedded) */
5310 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5311 /* Code name for PowerPC 750L (G3 embedded) */
5312 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5313 /* PowerPC 750L v2.2 (G3 embedded) */
5314 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5315 /* PowerPC 750L v3.0 (G3 embedded) */
5316 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5317 /* PowerPC 750L v3.2 (G3 embedded) */
5318 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5319 /* Generic PowerPC 745 */
5320 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5321 /* Generic PowerPC 755 */
5322 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5323 /* Code name for PowerPC 745/755 */
5324 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5325 /* PowerPC 745 v1.0 */
5326 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5327 /* PowerPC 755 v1.0 */
5328 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5329 /* PowerPC 745 v1.1 */
5330 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5331 /* PowerPC 755 v1.1 */
5332 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5333 /* PowerPC 745 v2.0 */
5334 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5335 /* PowerPC 755 v2.0 */
5336 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5337 /* PowerPC 745 v2.1 */
5338 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5339 /* PowerPC 755 v2.1 */
5340 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5341 /* PowerPC 745 v2.2 */
5342 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5343 /* PowerPC 755 v2.2 */
5344 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5345 /* PowerPC 745 v2.3 */
5346 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5347 /* PowerPC 755 v2.3 */
5348 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5349 /* PowerPC 745 v2.4 */
5350 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5351 /* PowerPC 755 v2.4 */
5352 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5353 /* PowerPC 745 v2.5 */
5354 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5355 /* PowerPC 755 v2.5 */
5356 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5357 /* PowerPC 745 v2.6 */
5358 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5359 /* PowerPC 755 v2.6 */
5360 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5361 /* PowerPC 745 v2.7 */
5362 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5363 /* PowerPC 755 v2.7 */
5364 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5365 /* PowerPC 745 v2.8 */
5366 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5367 /* PowerPC 755 v2.8 */
5368 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5369#if defined (TODO)
5370 /* PowerPC 745P (G3) */
5371 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5372 /* PowerPC 755P (G3) */
5373 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5374#endif
5375 /* PowerPC 74xx family */
5376 /* PowerPC 7400 (G4) */
5377 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5378 /* Code name for PowerPC 7400 */
5379 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5380 /* PowerPC 74xx is also well known as G4 */
5381 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5382 /* PowerPC 7400 v1.0 (G4) */
5383 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5384 /* PowerPC 7400 v1.1 (G4) */
5385 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5386 /* PowerPC 7400 v2.0 (G4) */
5387 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5388 /* PowerPC 7400 v2.2 (G4) */
5389 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5390 /* PowerPC 7400 v2.6 (G4) */
5391 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5392 /* PowerPC 7400 v2.7 (G4) */
5393 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5394 /* PowerPC 7400 v2.8 (G4) */
5395 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5396 /* PowerPC 7400 v2.9 (G4) */
5397 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5398 /* PowerPC 7410 (G4) */
5399 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5400 /* Code name for PowerPC 7410 */
5401 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5402 /* PowerPC 7410 v1.0 (G4) */
5403 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5404 /* PowerPC 7410 v1.1 (G4) */
5405 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5406 /* PowerPC 7410 v1.2 (G4) */
5407 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5408 /* PowerPC 7410 v1.3 (G4) */
5409 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5410 /* PowerPC 7410 v1.4 (G4) */
5411 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5412 /* PowerPC 7448 (G4) */
5413 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5414 /* PowerPC 7448 v1.0 (G4) */
5415 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5416 /* PowerPC 7448 v1.1 (G4) */
5417 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5418 /* PowerPC 7448 v2.0 (G4) */
5419 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5420 /* PowerPC 7448 v2.1 (G4) */
5421 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5422#if defined (TODO)
5423 /* PowerPC 7450 (G4) */
5424 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5425 /* Code name for PowerPC 7450 */
5426 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5427#endif
5428#if defined (TODO)
5429 /* PowerPC 7450 v1.0 (G4) */
5430 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5431#endif
5432#if defined (TODO)
5433 /* PowerPC 7450 v1.1 (G4) */
5434 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5435#endif
5436#if defined (TODO)
5437 /* PowerPC 7450 v1.2 (G4) */
5438 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5439#endif
5440#if defined (TODO)
5441 /* PowerPC 7450 v2.0 (G4) */
5442 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5443#endif
5444#if defined (TODO)
5445 /* PowerPC 7450 v2.1 (G4) */
5446 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5447#endif
5448#if defined (TODO)
5449 /* PowerPC 7441 (G4) */
5450 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5451 /* PowerPC 7451 (G4) */
5452 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5453#endif
3fc6c082 5454#if defined (TODO)
a750fc0b
JM		 5455 /* PowerPC 7441g (G4) */
5456 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5457 /* PowerPC 7451g (G4) */
5458 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
2662a059
JM		 5459#endif
5460#if defined (TODO)
a750fc0b
JM		 5461 /* PowerPC 7445 (G4) */
5462 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5463 /* PowerPC 7455 (G4) */
5464 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5465 /* Code name for PowerPC 7445/7455 */
5466 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
2662a059
JM		 5467#endif
5468#if defined (TODO)
a750fc0b
JM		 5469 /* PowerPC 7445 v1.0 (G4) */
5470 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5471 /* PowerPC 7455 v1.0 (G4) */
5472 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5473#endif
2662a059 5474#if defined (TODO)
a750fc0b
JM		 5475 /* PowerPC 7445 v2.1 (G4) */
5476 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5477 /* PowerPC 7455 v2.1 (G4) */
5478 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
2662a059
JM		 5479#endif
5480#if defined (TODO)
a750fc0b
JM		 5481 /* PowerPC 7445 v3.2 (G4) */
5482 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5483 /* PowerPC 7455 v3.2 (G4) */
5484 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
2662a059
JM		 5485#endif
5486#if defined (TODO)
a750fc0b
JM		 5487 /* PowerPC 7445 v3.3 (G4) */
5488 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5489 /* PowerPC 7455 v3.3 (G4) */
5490 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
3fc6c082
FB		 5491#endif
5492#if defined (TODO)
a750fc0b
JM		 5493 /* PowerPC 7445 v3.4 (G4) */
5494 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5495 /* PowerPC 7455 v3.4 (G4) */
5496 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
3a607854 5497#endif
04f20795 5498#if defined (TODO)
a750fc0b
JM		 5499 /* PowerPC 7447 (G4) */
5500 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5501 /* PowerPC 7457 (G4) */
5502 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5503 /* Code name for PowerPC 7447/7457 */
5504 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
3fc6c082
FB		 5505#endif
5506#if defined (TODO)
a750fc0b
JM		 5507 /* PowerPC 7447 v1.0 (G4) */
5508 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5509 /* PowerPC 7457 v1.0 (G4) */
5510 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5511 /* Code name for PowerPC 7447A/7457A */
5512 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
3a607854
JM		 5513#endif
5514#if defined (TODO)
a750fc0b
JM		 5515 /* PowerPC 7447 v1.1 (G4) */
5516 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5517 /* PowerPC 7457 v1.1 (G4) */
5518 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
3a607854
JM		 5519#endif
5520#if defined (TODO)
a750fc0b
JM		 5521 /* PowerPC 7447 v1.2 (G4) */
5522 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5523 /* PowerPC 7457 v1.2 (G4) */
5524 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5525#endif
5526 /* 64 bits PowerPC */
5527#if defined (TARGET_PPC64)
3fc6c082 5528#if defined (TODO)
a750fc0b
JM		 5529 /* PowerPC 620 */
5530 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5531#endif
3fc6c082 5532#if defined (TODO)
a750fc0b
JM		 5533 /* PowerPC 630 (POWER3) */
5534 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5535 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5536#endif
3a607854 5537#if defined (TODO)
a750fc0b
JM		 5538 /* PowerPC 631 (Power 3+) */
5539 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5540 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
3a607854
JM		 5541#endif
5542#if defined (TODO)
a750fc0b
JM		 5543 /* POWER4 */
5544 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5545#endif
3a607854 5546#if defined (TODO)
a750fc0b
JM		 5547 /* POWER4p */
5548 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5549#endif
2662a059 5550#if defined (TODO)
a750fc0b
JM		 5551 /* POWER5 */
5552 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5553 /* POWER5GR */
5554 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
2662a059 5555#endif
3a607854 5556#if defined (TODO)
a750fc0b
JM		 5557 /* POWER5+ */
5558 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5559 /* POWER5GS */
5560 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5561#endif
2662a059 5562#if defined (TODO)
a750fc0b
JM		 5563 /* POWER6 */
5564 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5565 /* POWER6 running in POWER5 mode */
5566 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5567 /* POWER6A */
5568 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
2662a059 5569#endif
a750fc0b
JM		 5570 /* PowerPC 970 */
5571 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
a750fc0b
JM		 5572 /* PowerPC 970FX (G5) */
5573 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5574 /* PowerPC 970FX v1.0 (G5) */
5575 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5576 /* PowerPC 970FX v2.0 (G5) */
5577 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5578 /* PowerPC 970FX v2.1 (G5) */
5579 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5580 /* PowerPC 970FX v3.0 (G5) */
5581 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5582 /* PowerPC 970FX v3.1 (G5) */
5583 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5584 /* PowerPC 970GX (G5) */
5585 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
a750fc0b
JM		 5586 /* PowerPC 970MP */
5587 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
a750fc0b
JM		 5588 /* PowerPC 970MP v1.0 */
5589 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
a750fc0b
JM		 5590 /* PowerPC 970MP v1.1 */
5591 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
3a607854 5592#if defined (TODO)
a750fc0b
JM		 5593 /* PowerPC Cell */
5594 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
2662a059
JM		 5595#endif
5596#if defined (TODO)
a750fc0b
JM		 5597 /* PowerPC Cell v1.0 */
5598 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
2662a059
JM		 5599#endif
5600#if defined (TODO)
a750fc0b
JM		 5601 /* PowerPC Cell v2.0 */
5602 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
2662a059
JM		 5603#endif
5604#if defined (TODO)
a750fc0b
JM		 5605 /* PowerPC Cell v3.0 */
5606 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
3a607854 5607#endif
3a607854 5608#if defined (TODO)
a750fc0b
JM		 5609 /* PowerPC Cell v3.1 */
5610 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
2662a059
JM		 5611#endif
5612#if defined (TODO)
a750fc0b
JM		 5613 /* PowerPC Cell v3.2 */
5614 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
2662a059
JM		 5615#endif
5616#if defined (TODO)
a750fc0b
JM		 5617 /* RS64 (Apache/A35) */
5618 /* This one seems to support the whole POWER2 instruction set
5619 * and the PowerPC 64 one.
5620 */
5621 /* What about A10 & A30 ? */
5622 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5623 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5624 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
3a607854
JM		 5625#endif
5626#if defined (TODO)
a750fc0b
JM		 5627 /* RS64-II (NorthStar/A50) */
5628 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5629 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5630 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
3a607854
JM		 5631#endif
5632#if defined (TODO)
a750fc0b
JM		 5633 /* RS64-III (Pulsar) */
5634 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5635 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
2662a059
JM		 5636#endif
5637#if defined (TODO)
a750fc0b
JM		 5638 /* RS64-IV (IceStar/IStar/SStar) */
5639 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5640 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5641 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5642 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
3a607854 5643#endif
a750fc0b
JM		 5644#endif /* defined (TARGET_PPC64) */
5645 /* POWER */
3fc6c082 5646#if defined (TODO)
a750fc0b
JM		 5647 /* Original POWER */
5648 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5649 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5650 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5651 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5652 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
76a66253
JM		 5653#endif
5654#if defined (TODO)
a750fc0b
JM		 5655 /* POWER2 */
5656 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5657 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5658 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5659#endif
5660 /* PA semi cores */
5661#if defined (TODO)
5662 /* PA PA6T */
5663 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5664#endif
5665 /* Generic PowerPCs */
5666#if defined (TARGET_PPC64)
5667#if defined (TODO)
5668 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5669#endif
5670#endif
5671 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
d12f4c38 5672 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b 5673 /* Fallback */
d12f4c38 5674 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b
JM		 5675};
5676
5677/*****************************************************************************/
5678/* Generic CPU instanciation routine */
5679static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5680{
5681#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 5682 int i;
5683
a750fc0b 5684 env->irq_inputs = NULL;
e1833e1f
JM		 5685 /* Set all exception vectors to an invalid address */
5686 for (i = 0; i < POWERPC_EXCP_NB; i++)
5687 env->excp_vectors[i] = (target_ulong)(-1ULL);
5688 env->excp_prefix = 0x00000000;
5689 env->ivor_mask = 0x00000000;
5690 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 5691#endif
5692 /* Default MMU definitions */
5693 env->nb_BATs = 0;
5694 env->nb_tlb = 0;
5695 env->nb_ways = 0;
5696 /* Register SPR common to all PowerPC implementations */
5697 gen_spr_generic(env);
5698 spr_register(env, SPR_PVR, "PVR",
5699 SPR_NOACCESS, SPR_NOACCESS,
5700 &spr_read_generic, SPR_NOACCESS,
5701 def->pvr);
5702 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5703 (*def->init_proc)(env);
5704 /* Allocate TLBs buffer when needed */
5705 if (env->nb_tlb != 0) {
5706 int nb_tlb = env->nb_tlb;
5707 if (env->id_tlbs != 0)
5708 nb_tlb *= 2;
5709 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5710 /* Pre-compute some useful values */
5711 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5712 }
5713#if !defined(CONFIG_USER_ONLY)
5714 if (env->irq_inputs == NULL) {
5715 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5716 " Attempt Qemu to crash very soon !\n");
5717 }
5718#endif
5719}
5720
5721#if defined(PPC_DUMP_CPU)
5722static void dump_ppc_sprs (CPUPPCState *env)
5723{
5724 ppc_spr_t *spr;
5725#if !defined(CONFIG_USER_ONLY)
5726 uint32_t sr, sw;
5727#endif
5728 uint32_t ur, uw;
5729 int i, j, n;
5730
5731 printf("Special purpose registers:\n");
5732 for (i = 0; i < 32; i++) {
5733 for (j = 0; j < 32; j++) {
5734 n = (i << 5) | j;
5735 spr = &env->spr_cb[n];
5736 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5737 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5738#if !defined(CONFIG_USER_ONLY)
5739 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5740 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5741 if (sw || sr || uw || ur) {
5742 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5743 (i << 5) | j, (i << 5) | j, spr->name,
5744 sw ? 'w' : '-', sr ? 'r' : '-',
5745 uw ? 'w' : '-', ur ? 'r' : '-');
5746 }
5747#else
5748 if (uw || ur) {
5749 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5750 (i << 5) | j, (i << 5) | j, spr->name,
5751 uw ? 'w' : '-', ur ? 'r' : '-');
5752 }
5753#endif
5754 }
5755 }
5756 fflush(stdout);
5757 fflush(stderr);
5758}
5759#endif
5760
5761/*****************************************************************************/
5762#include <stdlib.h>
5763#include <string.h>
5764
5765int fflush (FILE *stream);
5766
5767/* Opcode types */
5768enum {
5769 PPC_DIRECT = 0, /* Opcode routine */
5770 PPC_INDIRECT = 1, /* Indirect opcode table */
5771};
5772
5773static inline int is_indirect_opcode (void *handler)
5774{
5775 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5776}
5777
5778static inline opc_handler_t **ind_table(void *handler)
5779{
5780 return (opc_handler_t **)((unsigned long)handler & ~3);
5781}
5782
5783/* Instruction table creation */
5784/* Opcodes tables creation */
5785static void fill_new_table (opc_handler_t **table, int len)
5786{
5787 int i;
5788
5789 for (i = 0; i < len; i++)
5790 table[i] = &invalid_handler;
5791}
5792
5793static int create_new_table (opc_handler_t **table, unsigned char idx)
5794{
5795 opc_handler_t **tmp;
5796
5797 tmp = malloc(0x20 * sizeof(opc_handler_t));
5798 if (tmp == NULL)
5799 return -1;
5800 fill_new_table(tmp, 0x20);
5801 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
5802
5803 return 0;
5804}
5805
5806static int insert_in_table (opc_handler_t **table, unsigned char idx,
5807 opc_handler_t *handler)
5808{
5809 if (table[idx] != &invalid_handler)
5810 return -1;
5811 table[idx] = handler;
5812
5813 return 0;
5814}
5815
5816static int register_direct_insn (opc_handler_t **ppc_opcodes,
5817 unsigned char idx, opc_handler_t *handler)
5818{
5819 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
5820 printf("*** ERROR: opcode %02x already assigned in main "
5821 "opcode table\n", idx);
5822 return -1;
5823 }
5824
5825 return 0;
5826}
5827
5828static int register_ind_in_table (opc_handler_t **table,
5829 unsigned char idx1, unsigned char idx2,
5830 opc_handler_t *handler)
5831{
5832 if (table[idx1] == &invalid_handler) {
5833 if (create_new_table(table, idx1) < 0) {
5834 printf("*** ERROR: unable to create indirect table "
5835 "idx=%02x\n", idx1);
5836 return -1;
5837 }
5838 } else {
5839 if (!is_indirect_opcode(table[idx1])) {
5840 printf("*** ERROR: idx %02x already assigned to a direct "
5841 "opcode\n", idx1);
5842 return -1;
5843 }
3a607854 5844 }
a750fc0b
JM		 5845 if (handler != NULL &&
5846 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
5847 printf("*** ERROR: opcode %02x already assigned in "
5848 "opcode table %02x\n", idx2, idx1);
5849 return -1;
3a607854 5850 }
a750fc0b
JM		 5851
5852 return 0;
5853}
5854
5855static int register_ind_insn (opc_handler_t **ppc_opcodes,
5856 unsigned char idx1, unsigned char idx2,
5857 opc_handler_t *handler)
5858{
5859 int ret;
5860
5861 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
5862
5863 return ret;
5864}
5865
5866static int register_dblind_insn (opc_handler_t **ppc_opcodes,
5867 unsigned char idx1, unsigned char idx2,
5868 unsigned char idx3, opc_handler_t *handler)
5869{
5870 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
5871 printf("*** ERROR: unable to join indirect table idx "
5872 "[%02x-%02x]\n", idx1, idx2);
5873 return -1;
5874 }
5875 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
5876 handler) < 0) {
5877 printf("*** ERROR: unable to insert opcode "
5878 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
5879 return -1;
5880 }
5881
5882 return 0;
5883}
5884
5885static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
5886{
5887 if (insn->opc2 != 0xFF) {
5888 if (insn->opc3 != 0xFF) {
5889 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
5890 insn->opc3, &insn->handler) < 0)
5891 return -1;
5892 } else {
5893 if (register_ind_insn(ppc_opcodes, insn->opc1,
5894 insn->opc2, &insn->handler) < 0)
5895 return -1;
5896 }
5897 } else {
5898 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
5899 return -1;
5900 }
5901
5902 return 0;
5903}
5904
5905static int test_opcode_table (opc_handler_t **table, int len)
5906{
5907 int i, count, tmp;
5908
5909 for (i = 0, count = 0; i < len; i++) {
5910 /* Consistency fixup */
5911 if (table[i] == NULL)
5912 table[i] = &invalid_handler;
5913 if (table[i] != &invalid_handler) {
5914 if (is_indirect_opcode(table[i])) {
5915 tmp = test_opcode_table(ind_table(table[i]), 0x20);
5916 if (tmp == 0) {
5917 free(table[i]);
5918 table[i] = &invalid_handler;
5919 } else {
5920 count++;
5921 }
5922 } else {
5923 count++;
5924 }
5925 }
5926 }
5927
5928 return count;
5929}
5930
5931static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
5932{
5933 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
5934 printf("*** WARNING: no opcode defined !\n");
5935}
5936
5937/*****************************************************************************/
5938static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
5939{
5940 opcode_t *opc, *start, *end;
5941
5942 fill_new_table(env->opcodes, 0x40);
5943 if (&opc_start < &opc_end) {
5944 start = &opc_start;
5945 end = &opc_end;
5946 } else {
5947 start = &opc_end;
5948 end = &opc_start;
5949 }
5950 for (opc = start + 1; opc != end; opc++) {
5951 if ((opc->handler.type & def->insns_flags) != 0) {
5952 if (register_insn(env->opcodes, opc) < 0) {
5953 printf("*** ERROR initializing PowerPC instruction "
5954 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
5955 opc->opc3);
5956 return -1;
5957 }
5958 }
5959 }
5960 fix_opcode_tables(env->opcodes);
5961 fflush(stdout);
5962 fflush(stderr);
5963
5964 return 0;
5965}
5966
5967#if defined(PPC_DUMP_CPU)
5968static int dump_ppc_insns (CPUPPCState *env)
5969{
5970 opc_handler_t **table, *handler;
5971 uint8_t opc1, opc2, opc3;
5972
5973 printf("Instructions set:\n");
5974 /* opc1 is 6 bits long */
5975 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
5976 table = env->opcodes;
5977 handler = table[opc1];
5978 if (is_indirect_opcode(handler)) {
5979 /* opc2 is 5 bits long */
5980 for (opc2 = 0; opc2 < 0x20; opc2++) {
5981 table = env->opcodes;
5982 handler = env->opcodes[opc1];
5983 table = ind_table(handler);
5984 handler = table[opc2];
5985 if (is_indirect_opcode(handler)) {
5986 table = ind_table(handler);
5987 /* opc3 is 5 bits long */
5988 for (opc3 = 0; opc3 < 0x20; opc3++) {
5989 handler = table[opc3];
5990 if (handler->handler != &gen_invalid) {
5991 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
5992 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
5993 handler->oname);
5994 }
5995 }
5996 } else {
5997 if (handler->handler != &gen_invalid) {
5998 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
5999 opc1, opc2, opc1, opc2, handler->oname);
6000 }
6001 }
6002 }
6003 } else {
6004 if (handler->handler != &gen_invalid) {
6005 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6006 opc1, opc1, handler->oname);
6007 }
6008 }
6009 }
6010}
3a607854 6011#endif
a750fc0b
JM		 6012
6013int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6014{
6015 env->msr_mask = def->msr_mask;
6016 env->mmu_model = def->mmu_model;
6017 env->excp_model = def->excp_model;
6018 env->bus_model = def->bus_model;
237c0af0 6019 env->bfd_mach = def->bfd_mach;
a750fc0b
JM		 6020 if (create_ppc_opcodes(env, def) < 0)
6021 return -1;
6022 init_ppc_proc(env, def);
6023#if defined(PPC_DUMP_CPU)
3a607854 6024 {
a750fc0b
JM		 6025 const unsigned char *mmu_model, *excp_model, *bus_model;
6026 switch (env->mmu_model) {
6027 case POWERPC_MMU_32B:
6028 mmu_model = "PowerPC 32";
6029 break;
a750fc0b
JM		 6030 case POWERPC_MMU_601:
6031 mmu_model = "PowerPC 601";
6032 break;
6033 case POWERPC_MMU_SOFT_6xx:
6034 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6035 break;
6036 case POWERPC_MMU_SOFT_74xx:
6037 mmu_model = "PowerPC 74xx with software driven TLBs";
6038 break;
6039 case POWERPC_MMU_SOFT_4xx:
6040 mmu_model = "PowerPC 4xx with software driven TLBs";
6041 break;
6042 case POWERPC_MMU_SOFT_4xx_Z:
6043 mmu_model = "PowerPC 4xx with software driven TLBs "
6044 "and zones protections";
6045 break;
6046 case POWERPC_MMU_REAL_4xx:
6047 mmu_model = "PowerPC 4xx real mode only";
6048 break;
6049 case POWERPC_MMU_BOOKE:
6050 mmu_model = "PowerPC BookE";
6051 break;
6052 case POWERPC_MMU_BOOKE_FSL:
6053 mmu_model = "PowerPC BookE FSL";
6054 break;
00af685f
JM		 6055#if defined (TARGET_PPC64)
6056 case POWERPC_MMU_64B:
6057 mmu_model = "PowerPC 64";
6058 break;
00af685f 6059#endif
a750fc0b
JM		 6060 default:
6061 mmu_model = "Unknown or invalid";
6062 break;
6063 }
6064 switch (env->excp_model) {
6065 case POWERPC_EXCP_STD:
6066 excp_model = "PowerPC";
6067 break;
6068 case POWERPC_EXCP_40x:
6069 excp_model = "PowerPC 40x";
6070 break;
6071 case POWERPC_EXCP_601:
6072 excp_model = "PowerPC 601";
6073 break;
6074 case POWERPC_EXCP_602:
6075 excp_model = "PowerPC 602";
6076 break;
6077 case POWERPC_EXCP_603:
6078 excp_model = "PowerPC 603";
6079 break;
6080 case POWERPC_EXCP_603E:
6081 excp_model = "PowerPC 603e";
6082 break;
6083 case POWERPC_EXCP_604:
6084 excp_model = "PowerPC 604";
6085 break;
6086 case POWERPC_EXCP_7x0:
6087 excp_model = "PowerPC 740/750";
6088 break;
6089 case POWERPC_EXCP_7x5:
6090 excp_model = "PowerPC 745/755";
6091 break;
6092 case POWERPC_EXCP_74xx:
6093 excp_model = "PowerPC 74xx";
6094 break;
a750fc0b
JM		 6095 case POWERPC_EXCP_BOOKE:
6096 excp_model = "PowerPC BookE";
6097 break;
00af685f
JM		 6098#if defined (TARGET_PPC64)
6099 case POWERPC_EXCP_970:
6100 excp_model = "PowerPC 970";
6101 break;
6102#endif
a750fc0b
JM		 6103 default:
6104 excp_model = "Unknown or invalid";
6105 break;
6106 }
6107 switch (env->bus_model) {
6108 case PPC_FLAGS_INPUT_6xx:
6109 bus_model = "PowerPC 6xx";
6110 break;
6111 case PPC_FLAGS_INPUT_BookE:
6112 bus_model = "PowerPC BookE";
6113 break;
6114 case PPC_FLAGS_INPUT_405:
6115 bus_model = "PowerPC 405";
6116 break;
a750fc0b
JM		 6117 case PPC_FLAGS_INPUT_401:
6118 bus_model = "PowerPC 401/403";
6119 break;
00af685f
JM		 6120#if defined (TARGET_PPC64)
6121 case PPC_FLAGS_INPUT_970:
6122 bus_model = "PowerPC 970";
6123 break;
6124#endif
a750fc0b
JM		 6125 default:
6126 bus_model = "Unknown or invalid";
6127 break;
6128 }
6129 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6130 " MMU model : %s\n",
6131 def->name, def->pvr, def->msr_mask, mmu_model);
6132 if (env->tlb != NULL) {
6133 printf(" %d %s TLB in %d ways\n",
6134 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6135 env->nb_ways);
6136 }
6137 printf(" Exceptions model : %s\n"
6138 " Bus model : %s\n",
6139 excp_model, bus_model);
6140 }
6141 dump_ppc_insns(env);
6142 dump_ppc_sprs(env);
6143 fflush(stdout);
3a607854 6144#endif
a750fc0b
JM		 6145
6146 return 0;
6147}
3fc6c082
FB		 6148
6149int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6150{
068abdc8 6151 int i, max, ret;
3fc6c082
FB		 6152
6153 ret = -1;
6154 *def = NULL;
068abdc8
JM		 6155 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6156 for (i = 0; i < max; i++) {
3fc6c082
FB		 6157 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6158 *def = &ppc_defs[i];
6159 ret = 0;
6160 break;
6161 }
6162 }
6163
6164 return ret;
6165}
6166
6167int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6168{
068abdc8 6169 int i, max, ret;
3fc6c082
FB		 6170
6171 ret = -1;
6172 *def = NULL;
068abdc8
JM		 6173 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6174 for (i = 0; i < max; i++) {
3fc6c082
FB		 6175 if ((pvr & ppc_defs[i].pvr_mask) ==
6176 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6177 *def = &ppc_defs[i];
6178 ret = 0;
6179 break;
6180 }
6181 }
6182
6183 return ret;
6184}
6185
6186void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6187{
068abdc8 6188 int i, max;
3fc6c082 6189
068abdc8
JM		 6190 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6191 for (i = 0; i < max; i++) {
a750fc0b
JM		 6192 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6193 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 6194 }
6195}
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