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Add definitions for Freescale PowerPC implementations,
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
ee4e83ed 27#include "host-utils.h"
237c0af0 28
3fc6c082
FB		 29//#define PPC_DUMP_CPU
30//#define PPC_DEBUG_SPR
80d11f44
JM		 31//#define PPC_DUMP_SPR_ACCESSES
32#if defined(CONFIG_USER_ONLY)
33#define TODO_USER_ONLY 1
34#endif
3fc6c082
FB		 35
36struct ppc_def_t {
37 const unsigned char *name;
38 uint32_t pvr;
80d11f44 39 uint32_t svr;
0487d6a8 40 uint64_t insns_flags;
3fc6c082 41 uint64_t msr_mask;
7820dbf3
JM		 42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
d26bfc9a 45 uint32_t flags;
237c0af0 46 int bfd_mach;
a750fc0b 47 void (*init_proc)(CPUPPCState *env);
2f462816 48 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 49};
50
e9df014c
JM		 51/* For user-mode emulation, we don't emulate any IRQ controller */
52#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 53#define PPC_IRQ_INIT_FN(name) \
54static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55{ \
e9df014c
JM		 56}
57#else
a750fc0b 58#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 59void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60#endif
a750fc0b 61
4e290a0b 62PPC_IRQ_INIT_FN(40x);
e9df014c 63PPC_IRQ_INIT_FN(6xx);
d0dfae6e 64PPC_IRQ_INIT_FN(970);
e9df014c 65
3fc6c082
FB		 66/* Generic callbacks:
67 * do nothing but store/retrieve spr value
68 */
04f20795 69#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 70static void spr_read_generic (void *opaque, int sprn)
71{
04f20795 72 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 73}
74
75static void spr_write_generic (void *opaque, int sprn)
76{
04f20795 77 gen_op_store_dump_spr(sprn);
3fc6c082 78}
04f20795
JM		 79#else
80static void spr_read_generic (void *opaque, int sprn)
a496775f 81{
04f20795 82 gen_op_load_spr(sprn);
a496775f
JM		 83}
84
04f20795 85static void spr_write_generic (void *opaque, int sprn)
a496775f 86{
04f20795 87 gen_op_store_spr(sprn);
a496775f 88}
04f20795 89#endif
a496775f
JM		 90
91#if !defined(CONFIG_USER_ONLY)
92static void spr_write_clear (void *opaque, int sprn)
93{
94 gen_op_mask_spr(sprn);
95}
96#endif
97
76a66253 98/* SPR common to all PowerPC */
3fc6c082
FB		 99/* XER */
100static void spr_read_xer (void *opaque, int sprn)
101{
102 gen_op_load_xer();
103}
104
105static void spr_write_xer (void *opaque, int sprn)
106{
107 gen_op_store_xer();
108}
109
110/* LR */
111static void spr_read_lr (void *opaque, int sprn)
112{
113 gen_op_load_lr();
114}
115
116static void spr_write_lr (void *opaque, int sprn)
117{
118 gen_op_store_lr();
119}
120
121/* CTR */
122static void spr_read_ctr (void *opaque, int sprn)
123{
124 gen_op_load_ctr();
125}
126
127static void spr_write_ctr (void *opaque, int sprn)
128{
129 gen_op_store_ctr();
130}
131
132/* User read access to SPR */
133/* USPRx */
134/* UMMCRx */
135/* UPMCx */
136/* USIA */
137/* UDECR */
138static void spr_read_ureg (void *opaque, int sprn)
139{
140 gen_op_load_spr(sprn + 0x10);
141}
142
76a66253 143/* SPR common to all non-embedded PowerPC */
3fc6c082 144/* DECR */
76a66253 145#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 146static void spr_read_decr (void *opaque, int sprn)
147{
148 gen_op_load_decr();
149}
150
151static void spr_write_decr (void *opaque, int sprn)
152{
153 gen_op_store_decr();
154}
76a66253 155#endif
3fc6c082 156
76a66253 157/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 158/* Time base */
159static void spr_read_tbl (void *opaque, int sprn)
160{
161 gen_op_load_tbl();
162}
163
76a66253 164static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 165{
76a66253 166 gen_op_load_tbu();
3fc6c082
FB		 167}
168
a062e36c
JM		 169__attribute__ (( unused ))
170static void spr_read_atbl (void *opaque, int sprn)
171{
172 gen_op_load_atbl();
173}
174
175__attribute__ (( unused ))
176static void spr_read_atbu (void *opaque, int sprn)
177{
178 gen_op_load_atbu();
179}
180
76a66253
JM		 181#if !defined(CONFIG_USER_ONLY)
182static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 183{
76a66253 184 gen_op_store_tbl();
3fc6c082
FB		 185}
186
187static void spr_write_tbu (void *opaque, int sprn)
188{
189 gen_op_store_tbu();
190}
a062e36c
JM		 191
192__attribute__ (( unused ))
193static void spr_write_atbl (void *opaque, int sprn)
194{
195 gen_op_store_atbl();
196}
197
198__attribute__ (( unused ))
199static void spr_write_atbu (void *opaque, int sprn)
200{
201 gen_op_store_atbu();
202}
76a66253 203#endif
3fc6c082 204
76a66253 205#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 206/* IBAT0U...IBAT0U */
207/* IBAT0L...IBAT7L */
208static void spr_read_ibat (void *opaque, int sprn)
209{
210 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
211}
212
213static void spr_read_ibat_h (void *opaque, int sprn)
214{
215 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
216}
217
218static void spr_write_ibatu (void *opaque, int sprn)
219{
3fc6c082 220 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 221}
222
223static void spr_write_ibatu_h (void *opaque, int sprn)
224{
3fc6c082 225 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 226}
227
228static void spr_write_ibatl (void *opaque, int sprn)
229{
3fc6c082 230 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 231}
232
233static void spr_write_ibatl_h (void *opaque, int sprn)
234{
3fc6c082 235 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 236}
237
238/* DBAT0U...DBAT7U */
239/* DBAT0L...DBAT7L */
240static void spr_read_dbat (void *opaque, int sprn)
241{
242 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
243}
244
245static void spr_read_dbat_h (void *opaque, int sprn)
246{
2e13d23a 247 gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
3fc6c082
FB		 248}
249
250static void spr_write_dbatu (void *opaque, int sprn)
251{
3fc6c082 252 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 253}
254
255static void spr_write_dbatu_h (void *opaque, int sprn)
256{
2e13d23a 257 gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
3fc6c082
FB		 258}
259
260static void spr_write_dbatl (void *opaque, int sprn)
261{
3fc6c082 262 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 263}
264
265static void spr_write_dbatl_h (void *opaque, int sprn)
266{
2e13d23a 267 gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
3fc6c082
FB		 268}
269
270/* SDR1 */
271static void spr_read_sdr1 (void *opaque, int sprn)
272{
273 gen_op_load_sdr1();
274}
275
276static void spr_write_sdr1 (void *opaque, int sprn)
277{
3fc6c082 278 gen_op_store_sdr1();
3fc6c082
FB		 279}
280
76a66253
JM		 281/* 64 bits PowerPC specific SPRs */
282/* ASR */
578bb252
JM		 283#if defined(TARGET_PPC64)
284__attribute__ (( unused ))
76a66253
JM		 285static void spr_read_asr (void *opaque, int sprn)
286{
287 gen_op_load_asr();
288}
289
578bb252 290__attribute__ (( unused ))
76a66253
JM		 291static void spr_write_asr (void *opaque, int sprn)
292{
76a66253 293 gen_op_store_asr();
76a66253
JM		 294}
295#endif
a750fc0b 296#endif
76a66253
JM		 297
298/* PowerPC 601 specific registers */
299/* RTC */
300static void spr_read_601_rtcl (void *opaque, int sprn)
301{
302 gen_op_load_601_rtcl();
303}
304
305static void spr_read_601_rtcu (void *opaque, int sprn)
306{
307 gen_op_load_601_rtcu();
308}
309
310#if !defined(CONFIG_USER_ONLY)
311static void spr_write_601_rtcu (void *opaque, int sprn)
312{
313 gen_op_store_601_rtcu();
314}
315
316static void spr_write_601_rtcl (void *opaque, int sprn)
317{
318 gen_op_store_601_rtcl();
319}
056401ea
JM		 320
321static void spr_write_hid0_601 (void *opaque, int sprn)
322{
323 DisasContext *ctx = opaque;
324
325 gen_op_store_hid0_601();
326 /* Must stop the translation as endianness may have changed */
327 GEN_STOP(ctx);
328}
76a66253
JM		 329#endif
330
331/* Unified bats */
332#if !defined(CONFIG_USER_ONLY)
333static void spr_read_601_ubat (void *opaque, int sprn)
334{
335 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
336}
337
338static void spr_write_601_ubatu (void *opaque, int sprn)
339{
76a66253 340 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 341}
342
343static void spr_write_601_ubatl (void *opaque, int sprn)
344{
76a66253 345 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 346}
347#endif
348
349/* PowerPC 40x specific registers */
350#if !defined(CONFIG_USER_ONLY)
351static void spr_read_40x_pit (void *opaque, int sprn)
352{
353 gen_op_load_40x_pit();
354}
355
356static void spr_write_40x_pit (void *opaque, int sprn)
357{
358 gen_op_store_40x_pit();
359}
360
8ecc7913
JM		 361static void spr_write_40x_dbcr0 (void *opaque, int sprn)
362{
363 DisasContext *ctx = opaque;
364
365 gen_op_store_40x_dbcr0();
366 /* We must stop translation as we may have rebooted */
e1833e1f 367 GEN_STOP(ctx);
8ecc7913
JM		 368}
369
c294fc58
JM		 370static void spr_write_40x_sler (void *opaque, int sprn)
371{
c294fc58 372 gen_op_store_40x_sler();
c294fc58
JM		 373}
374
76a66253
JM		 375static void spr_write_booke_tcr (void *opaque, int sprn)
376{
377 gen_op_store_booke_tcr();
378}
379
380static void spr_write_booke_tsr (void *opaque, int sprn)
381{
382 gen_op_store_booke_tsr();
383}
384#endif
385
386/* PowerPC 403 specific registers */
387/* PBL1 / PBU1 / PBL2 / PBU2 */
388#if !defined(CONFIG_USER_ONLY)
389static void spr_read_403_pbr (void *opaque, int sprn)
390{
391 gen_op_load_403_pb(sprn - SPR_403_PBL1);
392}
393
394static void spr_write_403_pbr (void *opaque, int sprn)
395{
76a66253 396 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 397}
398
3fc6c082
FB		 399static void spr_write_pir (void *opaque, int sprn)
400{
401 gen_op_store_pir();
402}
76a66253 403#endif
3fc6c082 404
6f5d427d
JM		 405#if !defined(CONFIG_USER_ONLY)
406/* Callback used to write the exception vector base */
407static void spr_write_excp_prefix (void *opaque, int sprn)
408{
409 gen_op_store_excp_prefix();
410 gen_op_store_spr(sprn);
411}
412
413static void spr_write_excp_vector (void *opaque, int sprn)
414{
415 DisasContext *ctx = opaque;
416
417 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
418 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
419 gen_op_store_spr(sprn);
420 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
421 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
422 gen_op_store_spr(sprn);
423 } else {
424 printf("Trying to write an unknown exception vector %d %03x\n",
425 sprn, sprn);
426 GEN_EXCP_PRIVREG(ctx);
427 }
428}
429#endif
430
76a66253
JM		 431#if defined(CONFIG_USER_ONLY)
432#define spr_register(env, num, name, uea_read, uea_write, \
433 oea_read, oea_write, initial_value) \
434do { \
435 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
436} while (0)
437static inline void _spr_register (CPUPPCState *env, int num,
438 const unsigned char *name,
439 void (*uea_read)(void *opaque, int sprn),
440 void (*uea_write)(void *opaque, int sprn),
441 target_ulong initial_value)
442#else
3fc6c082
FB		 443static inline void spr_register (CPUPPCState *env, int num,
444 const unsigned char *name,
445 void (*uea_read)(void *opaque, int sprn),
446 void (*uea_write)(void *opaque, int sprn),
447 void (*oea_read)(void *opaque, int sprn),
448 void (*oea_write)(void *opaque, int sprn),
449 target_ulong initial_value)
76a66253 450#endif
3fc6c082
FB		 451{
452 ppc_spr_t *spr;
453
454 spr = &env->spr_cb[num];
455 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 456#if !defined(CONFIG_USER_ONLY)
457 spr->oea_read != NULL || spr->oea_write != NULL ||
458#endif
459 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 460 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
461 exit(1);
462 }
463#if defined(PPC_DEBUG_SPR)
1b9eb036 464 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 465 initial_value);
3fc6c082
FB		 466#endif
467 spr->name = name;
468 spr->uea_read = uea_read;
469 spr->uea_write = uea_write;
76a66253 470#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 471 spr->oea_read = oea_read;
472 spr->oea_write = oea_write;
76a66253 473#endif
3fc6c082
FB		 474 env->spr[num] = initial_value;
475}
476
477/* Generic PowerPC SPRs */
478static void gen_spr_generic (CPUPPCState *env)
479{
480 /* Integer processing */
481 spr_register(env, SPR_XER, "XER",
482 &spr_read_xer, &spr_write_xer,
483 &spr_read_xer, &spr_write_xer,
484 0x00000000);
485 /* Branch contol */
486 spr_register(env, SPR_LR, "LR",
487 &spr_read_lr, &spr_write_lr,
488 &spr_read_lr, &spr_write_lr,
489 0x00000000);
490 spr_register(env, SPR_CTR, "CTR",
491 &spr_read_ctr, &spr_write_ctr,
492 &spr_read_ctr, &spr_write_ctr,
493 0x00000000);
494 /* Interrupt processing */
495 spr_register(env, SPR_SRR0, "SRR0",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 spr_register(env, SPR_SRR1, "SRR1",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 /* Processor control */
504 spr_register(env, SPR_SPRG0, "SPRG0",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508 spr_register(env, SPR_SPRG1, "SPRG1",
509 SPR_NOACCESS, SPR_NOACCESS,
510 &spr_read_generic, &spr_write_generic,
511 0x00000000);
512 spr_register(env, SPR_SPRG2, "SPRG2",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516 spr_register(env, SPR_SPRG3, "SPRG3",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520}
521
522/* SPR common to all non-embedded PowerPC, including 601 */
523static void gen_spr_ne_601 (CPUPPCState *env)
524{
525 /* Exception processing */
526 spr_register(env, SPR_DSISR, "DSISR",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530 spr_register(env, SPR_DAR, "DAR",
531 SPR_NOACCESS, SPR_NOACCESS,
532 &spr_read_generic, &spr_write_generic,
533 0x00000000);
534 /* Timer */
535 spr_register(env, SPR_DECR, "DECR",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_decr, &spr_write_decr,
538 0x00000000);
539 /* Memory management */
540 spr_register(env, SPR_SDR1, "SDR1",
541 SPR_NOACCESS, SPR_NOACCESS,
542 &spr_read_sdr1, &spr_write_sdr1,
543 0x00000000);
544}
545
546/* BATs 0-3 */
547static void gen_low_BATs (CPUPPCState *env)
548{
f2e63a42 549#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 550 spr_register(env, SPR_IBAT0U, "IBAT0U",
551 SPR_NOACCESS, SPR_NOACCESS,
552 &spr_read_ibat, &spr_write_ibatu,
553 0x00000000);
554 spr_register(env, SPR_IBAT0L, "IBAT0L",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_ibat, &spr_write_ibatl,
557 0x00000000);
558 spr_register(env, SPR_IBAT1U, "IBAT1U",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_ibat, &spr_write_ibatu,
561 0x00000000);
562 spr_register(env, SPR_IBAT1L, "IBAT1L",
563 SPR_NOACCESS, SPR_NOACCESS,
564 &spr_read_ibat, &spr_write_ibatl,
565 0x00000000);
566 spr_register(env, SPR_IBAT2U, "IBAT2U",
567 SPR_NOACCESS, SPR_NOACCESS,
568 &spr_read_ibat, &spr_write_ibatu,
569 0x00000000);
570 spr_register(env, SPR_IBAT2L, "IBAT2L",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_ibat, &spr_write_ibatl,
573 0x00000000);
574 spr_register(env, SPR_IBAT3U, "IBAT3U",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_ibat, &spr_write_ibatu,
577 0x00000000);
578 spr_register(env, SPR_IBAT3L, "IBAT3L",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_ibat, &spr_write_ibatl,
581 0x00000000);
582 spr_register(env, SPR_DBAT0U, "DBAT0U",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_dbat, &spr_write_dbatu,
585 0x00000000);
586 spr_register(env, SPR_DBAT0L, "DBAT0L",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_dbat, &spr_write_dbatl,
589 0x00000000);
590 spr_register(env, SPR_DBAT1U, "DBAT1U",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_dbat, &spr_write_dbatu,
593 0x00000000);
594 spr_register(env, SPR_DBAT1L, "DBAT1L",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_dbat, &spr_write_dbatl,
597 0x00000000);
598 spr_register(env, SPR_DBAT2U, "DBAT2U",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_dbat, &spr_write_dbatu,
601 0x00000000);
602 spr_register(env, SPR_DBAT2L, "DBAT2L",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_dbat, &spr_write_dbatl,
605 0x00000000);
606 spr_register(env, SPR_DBAT3U, "DBAT3U",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_dbat, &spr_write_dbatu,
609 0x00000000);
610 spr_register(env, SPR_DBAT3L, "DBAT3L",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_dbat, &spr_write_dbatl,
613 0x00000000);
a750fc0b 614 env->nb_BATs += 4;
f2e63a42 615#endif
3fc6c082
FB		 616}
617
618/* BATs 4-7 */
619static void gen_high_BATs (CPUPPCState *env)
620{
f2e63a42 621#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 622 spr_register(env, SPR_IBAT4U, "IBAT4U",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatu_h,
625 0x00000000);
626 spr_register(env, SPR_IBAT4L, "IBAT4L",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatl_h,
629 0x00000000);
630 spr_register(env, SPR_IBAT5U, "IBAT5U",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat_h, &spr_write_ibatu_h,
633 0x00000000);
634 spr_register(env, SPR_IBAT5L, "IBAT5L",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_ibat_h, &spr_write_ibatl_h,
637 0x00000000);
638 spr_register(env, SPR_IBAT6U, "IBAT6U",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_ibat_h, &spr_write_ibatu_h,
641 0x00000000);
642 spr_register(env, SPR_IBAT6L, "IBAT6L",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_ibat_h, &spr_write_ibatl_h,
645 0x00000000);
646 spr_register(env, SPR_IBAT7U, "IBAT7U",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_ibat_h, &spr_write_ibatu_h,
649 0x00000000);
650 spr_register(env, SPR_IBAT7L, "IBAT7L",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_ibat_h, &spr_write_ibatl_h,
653 0x00000000);
654 spr_register(env, SPR_DBAT4U, "DBAT4U",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatu_h,
657 0x00000000);
658 spr_register(env, SPR_DBAT4L, "DBAT4L",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatl_h,
661 0x00000000);
662 spr_register(env, SPR_DBAT5U, "DBAT5U",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat_h, &spr_write_dbatu_h,
665 0x00000000);
666 spr_register(env, SPR_DBAT5L, "DBAT5L",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_dbat_h, &spr_write_dbatl_h,
669 0x00000000);
670 spr_register(env, SPR_DBAT6U, "DBAT6U",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_dbat_h, &spr_write_dbatu_h,
673 0x00000000);
674 spr_register(env, SPR_DBAT6L, "DBAT6L",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_dbat_h, &spr_write_dbatl_h,
677 0x00000000);
678 spr_register(env, SPR_DBAT7U, "DBAT7U",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_dbat_h, &spr_write_dbatu_h,
681 0x00000000);
682 spr_register(env, SPR_DBAT7L, "DBAT7L",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_dbat_h, &spr_write_dbatl_h,
685 0x00000000);
a750fc0b 686 env->nb_BATs += 4;
f2e63a42 687#endif
3fc6c082
FB		 688}
689
690/* Generic PowerPC time base */
691static void gen_tbl (CPUPPCState *env)
692{
693 spr_register(env, SPR_VTBL, "TBL",
694 &spr_read_tbl, SPR_NOACCESS,
695 &spr_read_tbl, SPR_NOACCESS,
696 0x00000000);
697 spr_register(env, SPR_TBL, "TBL",
698 SPR_NOACCESS, SPR_NOACCESS,
699 SPR_NOACCESS, &spr_write_tbl,
700 0x00000000);
701 spr_register(env, SPR_VTBU, "TBU",
702 &spr_read_tbu, SPR_NOACCESS,
703 &spr_read_tbu, SPR_NOACCESS,
704 0x00000000);
705 spr_register(env, SPR_TBU, "TBU",
706 SPR_NOACCESS, SPR_NOACCESS,
707 SPR_NOACCESS, &spr_write_tbu,
708 0x00000000);
709}
710
76a66253
JM		 711/* Softare table search registers */
712static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
713{
f2e63a42 714#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 715 env->nb_tlb = nb_tlbs;
716 env->nb_ways = nb_ways;
717 env->id_tlbs = 1;
718 spr_register(env, SPR_DMISS, "DMISS",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, SPR_NOACCESS,
721 0x00000000);
722 spr_register(env, SPR_DCMP, "DCMP",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, SPR_NOACCESS,
725 0x00000000);
726 spr_register(env, SPR_HASH1, "HASH1",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, SPR_NOACCESS,
729 0x00000000);
730 spr_register(env, SPR_HASH2, "HASH2",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, SPR_NOACCESS,
733 0x00000000);
734 spr_register(env, SPR_IMISS, "IMISS",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, SPR_NOACCESS,
737 0x00000000);
738 spr_register(env, SPR_ICMP, "ICMP",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, SPR_NOACCESS,
741 0x00000000);
742 spr_register(env, SPR_RPA, "RPA",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 0x00000000);
f2e63a42 746#endif
76a66253
JM		 747}
748
749/* SPR common to MPC755 and G2 */
750static void gen_spr_G2_755 (CPUPPCState *env)
751{
752 /* SGPRs */
753 spr_register(env, SPR_SPRG4, "SPRG4",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 spr_register(env, SPR_SPRG5, "SPRG5",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_SPRG6, "SPRG6",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 spr_register(env, SPR_SPRG7, "SPRG7",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
768 0x00000000);
769 /* External access control */
770 /* XXX : not implemented */
771 spr_register(env, SPR_EAR, "EAR",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_generic, &spr_write_generic,
774 0x00000000);
775}
776
3fc6c082
FB		 777/* SPR common to all 7xx PowerPC implementations */
778static void gen_spr_7xx (CPUPPCState *env)
779{
780 /* Breakpoints */
781 /* XXX : not implemented */
782 spr_register(env, SPR_DABR, "DABR",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, &spr_write_generic,
785 0x00000000);
786 /* XXX : not implemented */
787 spr_register(env, SPR_IABR, "IABR",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_generic, &spr_write_generic,
790 0x00000000);
791 /* Cache management */
792 /* XXX : not implemented */
793 spr_register(env, SPR_ICTC, "ICTC",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_generic, &spr_write_generic,
796 0x00000000);
76a66253
JM		 797 /* XXX : not implemented */
798 spr_register(env, SPR_L2CR, "L2CR",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
3fc6c082
FB		 802 /* Performance monitors */
803 /* XXX : not implemented */
804 spr_register(env, SPR_MMCR0, "MMCR0",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 /* XXX : not implemented */
809 spr_register(env, SPR_MMCR1, "MMCR1",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_generic, &spr_write_generic,
812 0x00000000);
813 /* XXX : not implemented */
814 spr_register(env, SPR_PMC1, "PMC1",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, &spr_write_generic,
817 0x00000000);
818 /* XXX : not implemented */
819 spr_register(env, SPR_PMC2, "PMC2",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_generic, &spr_write_generic,
822 0x00000000);
823 /* XXX : not implemented */
824 spr_register(env, SPR_PMC3, "PMC3",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828 /* XXX : not implemented */
829 spr_register(env, SPR_PMC4, "PMC4",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_generic, &spr_write_generic,
832 0x00000000);
833 /* XXX : not implemented */
a750fc0b 834 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, SPR_NOACCESS,
837 0x00000000);
578bb252 838 /* XXX : not implemented */
3fc6c082
FB		 839 spr_register(env, SPR_UMMCR0, "UMMCR0",
840 &spr_read_ureg, SPR_NOACCESS,
841 &spr_read_ureg, SPR_NOACCESS,
842 0x00000000);
578bb252 843 /* XXX : not implemented */
3fc6c082
FB		 844 spr_register(env, SPR_UMMCR1, "UMMCR1",
845 &spr_read_ureg, SPR_NOACCESS,
846 &spr_read_ureg, SPR_NOACCESS,
847 0x00000000);
578bb252 848 /* XXX : not implemented */
3fc6c082
FB		 849 spr_register(env, SPR_UPMC1, "UPMC1",
850 &spr_read_ureg, SPR_NOACCESS,
851 &spr_read_ureg, SPR_NOACCESS,
852 0x00000000);
578bb252 853 /* XXX : not implemented */
3fc6c082
FB		 854 spr_register(env, SPR_UPMC2, "UPMC2",
855 &spr_read_ureg, SPR_NOACCESS,
856 &spr_read_ureg, SPR_NOACCESS,
857 0x00000000);
578bb252 858 /* XXX : not implemented */
3fc6c082
FB		 859 spr_register(env, SPR_UPMC3, "UPMC3",
860 &spr_read_ureg, SPR_NOACCESS,
861 &spr_read_ureg, SPR_NOACCESS,
862 0x00000000);
578bb252 863 /* XXX : not implemented */
3fc6c082
FB		 864 spr_register(env, SPR_UPMC4, "UPMC4",
865 &spr_read_ureg, SPR_NOACCESS,
866 &spr_read_ureg, SPR_NOACCESS,
867 0x00000000);
578bb252 868 /* XXX : not implemented */
a750fc0b 869 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 870 &spr_read_ureg, SPR_NOACCESS,
871 &spr_read_ureg, SPR_NOACCESS,
872 0x00000000);
a750fc0b 873 /* External access control */
3fc6c082 874 /* XXX : not implemented */
a750fc0b 875 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, &spr_write_generic,
878 0x00000000);
a750fc0b
JM		 879}
880
881static void gen_spr_thrm (CPUPPCState *env)
882{
883 /* Thermal management */
3fc6c082 884 /* XXX : not implemented */
a750fc0b 885 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 /* XXX : not implemented */
a750fc0b 890 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
3fc6c082 894 /* XXX : not implemented */
a750fc0b 895 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899}
900
901/* SPR specific to PowerPC 604 implementation */
902static void gen_spr_604 (CPUPPCState *env)
903{
904 /* Processor identification */
905 spr_register(env, SPR_PIR, "PIR",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_pir,
908 0x00000000);
909 /* Breakpoints */
910 /* XXX : not implemented */
911 spr_register(env, SPR_IABR, "IABR",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* XXX : not implemented */
916 spr_register(env, SPR_DABR, "DABR",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 /* Performance counters */
921 /* XXX : not implemented */
922 spr_register(env, SPR_MMCR0, "MMCR0",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 /* XXX : not implemented */
927 spr_register(env, SPR_MMCR1, "MMCR1",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_PMC1, "PMC1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* XXX : not implemented */
937 spr_register(env, SPR_PMC2, "PMC2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_PMC3, "PMC3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* XXX : not implemented */
947 spr_register(env, SPR_PMC4, "PMC4",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 /* XXX : not implemented */
a750fc0b 952 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, SPR_NOACCESS,
955 0x00000000);
956 /* XXX : not implemented */
957 spr_register(env, SPR_SDA, "SDA",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, SPR_NOACCESS,
960 0x00000000);
961 /* External access control */
962 /* XXX : not implemented */
963 spr_register(env, SPR_EAR, "EAR",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967}
968
76a66253
JM		 969/* SPR specific to PowerPC 603 implementation */
970static void gen_spr_603 (CPUPPCState *env)
3fc6c082 971{
76a66253
JM		 972 /* External access control */
973 /* XXX : not implemented */
974 spr_register(env, SPR_EAR, "EAR",
3fc6c082 975 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
3fc6c082
FB		 978}
979
76a66253
JM		 980/* SPR specific to PowerPC G2 implementation */
981static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 982{
76a66253
JM		 983 /* Memory base address */
984 /* MBAR */
578bb252 985 /* XXX : not implemented */
76a66253
JM		 986 spr_register(env, SPR_MBAR, "MBAR",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
76a66253 990 /* Exception processing */
363be49c 991 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
363be49c 995 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 /* Breakpoints */
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_DABR, "DABR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_DABR2, "DABR2",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_IABR, "IABR",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_IABR2, "IABR2",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_IBCR, "IBCR",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_DBCR, "DBCR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030}
1031
1032/* SPR specific to PowerPC 602 implementation */
1033static void gen_spr_602 (CPUPPCState *env)
1034{
1035 /* ESA registers */
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_SER, "SER",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_SEBR, "SEBR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
a750fc0b 1047 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* Floating point status */
1052 /* XXX : not implemented */
1053 spr_register(env, SPR_SP, "SP",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, &spr_write_generic,
1056 0x00000000);
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_LT, "LT",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 /* Watchdog timer */
1063 /* XXX : not implemented */
1064 spr_register(env, SPR_TCR, "TCR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 /* Interrupt base */
1069 spr_register(env, SPR_IBR, "IBR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
a750fc0b
JM		 1073 /* XXX : not implemented */
1074 spr_register(env, SPR_IABR, "IABR",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
76a66253
JM		 1078}
1079
1080/* SPR specific to PowerPC 601 implementation */
1081static void gen_spr_601 (CPUPPCState *env)
1082{
1083 /* Multiplication/division register */
1084 /* MQ */
1085 spr_register(env, SPR_MQ, "MQ",
1086 &spr_read_generic, &spr_write_generic,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 /* RTC registers */
1090 spr_register(env, SPR_601_RTCU, "RTCU",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 SPR_NOACCESS, &spr_write_601_rtcu,
1093 0x00000000);
1094 spr_register(env, SPR_601_VRTCU, "RTCU",
1095 &spr_read_601_rtcu, SPR_NOACCESS,
1096 &spr_read_601_rtcu, SPR_NOACCESS,
1097 0x00000000);
1098 spr_register(env, SPR_601_RTCL, "RTCL",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 SPR_NOACCESS, &spr_write_601_rtcl,
1101 0x00000000);
1102 spr_register(env, SPR_601_VRTCL, "RTCL",
1103 &spr_read_601_rtcl, SPR_NOACCESS,
1104 &spr_read_601_rtcl, SPR_NOACCESS,
1105 0x00000000);
1106 /* Timer */
1107#if 0 /* ? */
1108 spr_register(env, SPR_601_UDECR, "UDECR",
1109 &spr_read_decr, SPR_NOACCESS,
1110 &spr_read_decr, SPR_NOACCESS,
1111 0x00000000);
1112#endif
1113 /* External access control */
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_EAR, "EAR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* Memory management */
f2e63a42 1120#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1121 spr_register(env, SPR_IBAT0U, "IBAT0U",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_601_ubat, &spr_write_601_ubatu,
1124 0x00000000);
1125 spr_register(env, SPR_IBAT0L, "IBAT0L",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_601_ubat, &spr_write_601_ubatl,
1128 0x00000000);
1129 spr_register(env, SPR_IBAT1U, "IBAT1U",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_601_ubat, &spr_write_601_ubatu,
1132 0x00000000);
1133 spr_register(env, SPR_IBAT1L, "IBAT1L",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_601_ubat, &spr_write_601_ubatl,
1136 0x00000000);
1137 spr_register(env, SPR_IBAT2U, "IBAT2U",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_601_ubat, &spr_write_601_ubatu,
1140 0x00000000);
1141 spr_register(env, SPR_IBAT2L, "IBAT2L",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_601_ubat, &spr_write_601_ubatl,
1144 0x00000000);
1145 spr_register(env, SPR_IBAT3U, "IBAT3U",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_601_ubat, &spr_write_601_ubatu,
1148 0x00000000);
1149 spr_register(env, SPR_IBAT3L, "IBAT3L",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_601_ubat, &spr_write_601_ubatl,
1152 0x00000000);
a750fc0b 1153 env->nb_BATs = 4;
f2e63a42 1154#endif
a750fc0b
JM		 1155}
1156
1157static void gen_spr_74xx (CPUPPCState *env)
1158{
1159 /* Processor identification */
1160 spr_register(env, SPR_PIR, "PIR",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_pir,
1163 0x00000000);
1164 /* XXX : not implemented */
1165 spr_register(env, SPR_MMCR2, "MMCR2",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
578bb252 1169 /* XXX : not implemented */
a750fc0b
JM		 1170 spr_register(env, SPR_UMMCR2, "UMMCR2",
1171 &spr_read_ureg, SPR_NOACCESS,
1172 &spr_read_ureg, SPR_NOACCESS,
1173 0x00000000);
1174 /* XXX: not implemented */
1175 spr_register(env, SPR_BAMR, "BAMR",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
578bb252 1179 /* XXX : not implemented */
a750fc0b
JM		 1180 spr_register(env, SPR_UBAMR, "UBAMR",
1181 &spr_read_ureg, SPR_NOACCESS,
1182 &spr_read_ureg, SPR_NOACCESS,
1183 0x00000000);
578bb252 1184 /* XXX : not implemented */
a750fc0b
JM		 1185 spr_register(env, SPR_MSSCR0, "MSSCR0",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Hardware implementation registers */
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_HID0, "HID0",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_HID1, "HID1",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* Altivec */
1201 spr_register(env, SPR_VRSAVE, "VRSAVE",
1202 &spr_read_generic, &spr_write_generic,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205}
1206
a750fc0b
JM		 1207static void gen_l3_ctrl (CPUPPCState *env)
1208{
1209 /* L3CR */
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_L3CR, "L3CR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* L3ITCR0 */
578bb252 1216 /* XXX : not implemented */
a750fc0b
JM		 1217 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* L3ITCR1 */
578bb252 1222 /* XXX : not implemented */
a750fc0b
JM		 1223 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* L3ITCR2 */
578bb252 1228 /* XXX : not implemented */
a750fc0b
JM		 1229 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* L3ITCR3 */
578bb252 1234 /* XXX : not implemented */
a750fc0b
JM		 1235 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 /* L3OHCR */
578bb252 1240 /* XXX : not implemented */
a750fc0b
JM		 1241 spr_register(env, SPR_L3OHCR, "L3OHCR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* L3PM */
578bb252 1246 /* XXX : not implemented */
a750fc0b
JM		 1247 spr_register(env, SPR_L3PM, "L3PM",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251}
a750fc0b 1252
578bb252 1253static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1254{
f2e63a42 1255#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1256 env->nb_tlb = nb_tlbs;
1257 env->nb_ways = nb_ways;
1258 env->id_tlbs = 1;
1259 /* XXX : not implemented */
a750fc0b
JM		 1260 spr_register(env, SPR_PTEHI, "PTEHI",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
578bb252 1264 /* XXX : not implemented */
a750fc0b
JM		 1265 spr_register(env, SPR_PTELO, "PTELO",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
578bb252 1269 /* XXX : not implemented */
a750fc0b
JM		 1270 spr_register(env, SPR_TLBMISS, "TLBMISS",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
f2e63a42 1274#endif
76a66253
JM		 1275}
1276
80d11f44 1277static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1278{
80d11f44
JM		 1279 spr_register(env, SPR_USPRG4, "USPRG4",
1280 &spr_read_ureg, SPR_NOACCESS,
1281 &spr_read_ureg, SPR_NOACCESS,
1282 0x00000000);
1283 spr_register(env, SPR_USPRG5, "USPRG5",
1284 &spr_read_ureg, SPR_NOACCESS,
1285 &spr_read_ureg, SPR_NOACCESS,
1286 0x00000000);
1287 spr_register(env, SPR_USPRG6, "USPRG6",
1288 &spr_read_ureg, SPR_NOACCESS,
1289 &spr_read_ureg, SPR_NOACCESS,
1290 0x00000000);
1291 spr_register(env, SPR_USPRG7, "USPRG7",
1292 &spr_read_ureg, SPR_NOACCESS,
1293 &spr_read_ureg, SPR_NOACCESS,
76a66253 1294 0x00000000);
80d11f44
JM		 1295}
1296
1297/* PowerPC BookE SPR */
1298static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1299{
1300 const unsigned char *ivor_names[64] = {
1301 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1302 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1303 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1304 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1305 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1306 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1307 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1308 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1309 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1310 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1311 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1312 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1313 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1314 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1315 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1316 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1317 };
1318#define SPR_BOOKE_IVORxx (-1)
1319 int ivor_sprn[64] = {
1320 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1321 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1322 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1323 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1324 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1325 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1326 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1327 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1328 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1329 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1330 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1331 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1332 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1333 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1334 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1335 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1336 };
1337 int i;
1338
76a66253 1339 /* Interrupt processing */
363be49c 1340 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
363be49c
JM		 1344 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
76a66253
JM		 1348 /* Debug */
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
76a66253
JM		 1360 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
76a66253
JM		 1370 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* XXX : not implemented */
1380 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 /* XXX : not implemented */
1385 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1386 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1387 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1388 0x00000000);
1389 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_ESR, "ESR",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
363be49c
JM		 1397 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1398 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1399 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1400 0x00000000);
1401 /* Exception vectors */
80d11f44
JM		 1402 for (i = 0; i < 64; i++) {
1403 if (ivor_mask & (1ULL << i)) {
1404 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1405 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1406 exit(1);
1407 }
1408 spr_register(env, ivor_sprn[i], ivor_names[i],
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_excp_vector,
1411 0x00000000);
1412 }
1413 }
76a66253
JM		 1414 spr_register(env, SPR_BOOKE_PID, "PID",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418 spr_register(env, SPR_BOOKE_TCR, "TCR",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_booke_tcr,
1421 0x00000000);
1422 spr_register(env, SPR_BOOKE_TSR, "TSR",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_booke_tsr,
1425 0x00000000);
1426 /* Timer */
1427 spr_register(env, SPR_DECR, "DECR",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_decr, &spr_write_decr,
1430 0x00000000);
1431 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 SPR_NOACCESS, &spr_write_generic,
1434 0x00000000);
1435 /* SPRGs */
1436 spr_register(env, SPR_USPRG0, "USPRG0",
1437 &spr_read_generic, &spr_write_generic,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440 spr_register(env, SPR_SPRG4, "SPRG4",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
76a66253
JM		 1444 spr_register(env, SPR_SPRG5, "SPRG5",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
76a66253
JM		 1448 spr_register(env, SPR_SPRG6, "SPRG6",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
76a66253
JM		 1452 spr_register(env, SPR_SPRG7, "SPRG7",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
76a66253
JM		 1456}
1457
363be49c 1458/* FSL storage control registers */
80d11f44 1459static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1460{
f2e63a42 1461#if !defined(CONFIG_USER_ONLY)
80d11f44
JM		 1462 const unsigned char *mas_names[8] = {
1463 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1464 };
1465 int mas_sprn[8] = {
1466 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1467 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1468 };
1469 int i;
1470
363be49c 1471 /* TLB assist registers */
578bb252 1472 /* XXX : not implemented */
80d11f44
JM		 1473 for (i = 0; i < 8; i++) {
1474 if (mas_mask & (1 << i)) {
1475 spr_register(env, mas_sprn[i], mas_names[i],
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 }
1480 }
363be49c 1481 if (env->nb_pids > 1) {
578bb252 1482 /* XXX : not implemented */
363be49c
JM		 1483 spr_register(env, SPR_BOOKE_PID1, "PID1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 }
1488 if (env->nb_pids > 2) {
578bb252 1489 /* XXX : not implemented */
363be49c
JM		 1490 spr_register(env, SPR_BOOKE_PID2, "PID2",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 }
578bb252 1495 /* XXX : not implemented */
65f9ee8d 1496 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, SPR_NOACCESS,
1499 0x00000000); /* TOFIX */
578bb252 1500 /* XXX : not implemented */
65f9ee8d 1501 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000); /* TOFIX */
1505 switch (env->nb_ways) {
1506 case 4:
578bb252 1507 /* XXX : not implemented */
363be49c
JM		 1508 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, SPR_NOACCESS,
1511 0x00000000); /* TOFIX */
1512 /* Fallthru */
1513 case 3:
578bb252 1514 /* XXX : not implemented */
363be49c
JM		 1515 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, SPR_NOACCESS,
1518 0x00000000); /* TOFIX */
1519 /* Fallthru */
1520 case 2:
578bb252 1521 /* XXX : not implemented */
363be49c
JM		 1522 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, SPR_NOACCESS,
1525 0x00000000); /* TOFIX */
1526 /* Fallthru */
1527 case 1:
578bb252 1528 /* XXX : not implemented */
363be49c
JM		 1529 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, SPR_NOACCESS,
1532 0x00000000); /* TOFIX */
1533 /* Fallthru */
1534 case 0:
1535 default:
1536 break;
1537 }
f2e63a42 1538#endif
363be49c
JM		 1539}
1540
76a66253
JM		 1541/* SPR specific to PowerPC 440 implementation */
1542static void gen_spr_440 (CPUPPCState *env)
1543{
1544 /* Cache control */
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_440_DNV0, "DNV0",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* XXX : not implemented */
1551 spr_register(env, SPR_440_DNV1, "DNV1",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_440_DNV2, "DNV2",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 /* XXX : not implemented */
1561 spr_register(env, SPR_440_DNV3, "DNV3",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 /* XXX : not implemented */
2662a059 1566 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 /* XXX : not implemented */
2662a059 1571 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 /* XXX : not implemented */
2662a059 1576 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580 /* XXX : not implemented */
2662a059 1581 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585 /* XXX : not implemented */
1586 spr_register(env, SPR_440_DVLIM, "DVLIM",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590 /* XXX : not implemented */
1591 spr_register(env, SPR_440_INV0, "INV0",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_440_INV1, "INV1",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600 /* XXX : not implemented */
1601 spr_register(env, SPR_440_INV2, "INV2",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605 /* XXX : not implemented */
1606 spr_register(env, SPR_440_INV3, "INV3",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, &spr_write_generic,
1609 0x00000000);
1610 /* XXX : not implemented */
2662a059 1611 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_generic,
1614 0x00000000);
1615 /* XXX : not implemented */
2662a059 1616 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_generic,
1619 0x00000000);
1620 /* XXX : not implemented */
2662a059 1621 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625 /* XXX : not implemented */
2662a059 1626 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630 /* XXX : not implemented */
1631 spr_register(env, SPR_440_IVLIM, "IVLIM",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, &spr_write_generic,
1634 0x00000000);
1635 /* Cache debug */
1636 /* XXX : not implemented */
2662a059 1637 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, SPR_NOACCESS,
1640 0x00000000);
1641 /* XXX : not implemented */
2662a059 1642 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, SPR_NOACCESS,
1645 0x00000000);
1646 /* XXX : not implemented */
2662a059 1647 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, SPR_NOACCESS,
1650 0x00000000);
1651 /* XXX : not implemented */
2662a059 1652 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
1655 0x00000000);
1656 /* XXX : not implemented */
2662a059 1657 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, SPR_NOACCESS,
1660 0x00000000);
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_440_DBDR, "DBDR",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* Processor control */
1667 spr_register(env, SPR_4xx_CCR0, "CCR0",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, SPR_NOACCESS,
1674 0x00000000);
1675 /* Storage control */
1676 spr_register(env, SPR_440_MMUCR, "MMUCR",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680}
1681
1682/* SPR shared between PowerPC 40x implementations */
1683static void gen_spr_40x (CPUPPCState *env)
1684{
1685 /* Cache */
035feb88 1686 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1687 spr_register(env, SPR_40x_DCCR, "DCCR",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
035feb88 1691 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1692 spr_register(env, SPR_40x_ICCR, "ICCR",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
578bb252 1696 /* not emulated, as Qemu do not emulate caches */
2662a059 1697 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, SPR_NOACCESS,
1700 0x00000000);
76a66253
JM		 1701 /* Exception */
1702 spr_register(env, SPR_40x_DEAR, "DEAR",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 spr_register(env, SPR_40x_ESR, "ESR",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 spr_register(env, SPR_40x_EVPR, "EVPR",
1711 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1712 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1713 0x00000000);
1714 spr_register(env, SPR_40x_SRR2, "SRR2",
1715 &spr_read_generic, &spr_write_generic,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 spr_register(env, SPR_40x_SRR3, "SRR3",
1719 &spr_read_generic, &spr_write_generic,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* Timers */
1723 spr_register(env, SPR_40x_PIT, "PIT",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_40x_pit, &spr_write_40x_pit,
1726 0x00000000);
1727 spr_register(env, SPR_40x_TCR, "TCR",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_generic, &spr_write_booke_tcr,
1730 0x00000000);
1731 spr_register(env, SPR_40x_TSR, "TSR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_booke_tsr,
1734 0x00000000);
2662a059
JM		 1735}
1736
1737/* SPR specific to PowerPC 405 implementation */
1738static void gen_spr_405 (CPUPPCState *env)
1739{
1740 /* MMU */
1741 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
2662a059 1745 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1748 0x00700000);
1749 /* Debug interface */
76a66253
JM		 1750 /* XXX : not implemented */
1751 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1752 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1753 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1754 0x00000000);
1755 /* XXX : not implemented */
2662a059
JM		 1756 spr_register(env, SPR_405_DBCR1, "DBCR1",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 /* XXX : not implemented */
76a66253
JM		 1761 spr_register(env, SPR_40x_DBSR, "DBSR",
1762 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1763 &spr_read_generic, &spr_write_clear,
1764 /* Last reset was system reset */
76a66253
JM		 1765 0x00000300);
1766 /* XXX : not implemented */
2662a059 1767 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
2662a059 1771 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_generic,
1774 0x00000000);
2662a059
JM		 1775 /* XXX : not implemented */
1776 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1777 SPR_NOACCESS, SPR_NOACCESS,
1778 &spr_read_generic, &spr_write_generic,
2662a059 1779 0x00000000);
76a66253 1780 /* XXX : not implemented */
2662a059 1781 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, &spr_write_generic,
1784 0x00000000);
1785 /* XXX : not implemented */
2662a059 1786 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
2662a059 1790 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_405_IAC3, "IAC3",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_405_IAC4, "IAC4",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Storage control */
035feb88 1805 /* XXX: TODO: not implemented */
76a66253
JM		 1806 spr_register(env, SPR_405_SLER, "SLER",
1807 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1808 &spr_read_generic, &spr_write_40x_sler,
76a66253 1809 0x00000000);
2662a059
JM		 1810 spr_register(env, SPR_40x_ZPR, "ZPR",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
76a66253
JM		 1814 /* XXX : not implemented */
1815 spr_register(env, SPR_405_SU0R, "SU0R",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 /* SPRG */
1820 spr_register(env, SPR_USPRG0, "USPRG0",
1821 &spr_read_ureg, SPR_NOACCESS,
1822 &spr_read_ureg, SPR_NOACCESS,
1823 0x00000000);
1824 spr_register(env, SPR_SPRG4, "SPRG4",
1825 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1826 &spr_read_generic, &spr_write_generic,
76a66253 1827 0x00000000);
76a66253
JM		 1828 spr_register(env, SPR_SPRG5, "SPRG5",
1829 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1830 spr_read_generic, &spr_write_generic,
76a66253 1831 0x00000000);
76a66253
JM		 1832 spr_register(env, SPR_SPRG6, "SPRG6",
1833 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1834 spr_read_generic, &spr_write_generic,
76a66253 1835 0x00000000);
76a66253
JM		 1836 spr_register(env, SPR_SPRG7, "SPRG7",
1837 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1838 spr_read_generic, &spr_write_generic,
76a66253 1839 0x00000000);
80d11f44 1840 gen_spr_usprgh(env);
76a66253
JM		 1841}
1842
1843/* SPR shared between PowerPC 401 & 403 implementations */
1844static void gen_spr_401_403 (CPUPPCState *env)
1845{
1846 /* Time base */
1847 spr_register(env, SPR_403_VTBL, "TBL",
1848 &spr_read_tbl, SPR_NOACCESS,
1849 &spr_read_tbl, SPR_NOACCESS,
1850 0x00000000);
1851 spr_register(env, SPR_403_TBL, "TBL",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 SPR_NOACCESS, &spr_write_tbl,
1854 0x00000000);
1855 spr_register(env, SPR_403_VTBU, "TBU",
1856 &spr_read_tbu, SPR_NOACCESS,
1857 &spr_read_tbu, SPR_NOACCESS,
1858 0x00000000);
1859 spr_register(env, SPR_403_TBU, "TBU",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 SPR_NOACCESS, &spr_write_tbu,
1862 0x00000000);
1863 /* Debug */
578bb252 1864 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1865 spr_register(env, SPR_403_CDBCR, "CDBCR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, &spr_write_generic,
1868 0x00000000);
1869}
1870
2662a059
JM		 1871/* SPR specific to PowerPC 401 implementation */
1872static void gen_spr_401 (CPUPPCState *env)
1873{
1874 /* Debug interface */
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_40x_DBCR0, "DBCR",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_40x_dbcr0,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_40x_DBSR, "DBSR",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_clear,
1884 /* Last reset was system reset */
1885 0x00000300);
1886 /* XXX : not implemented */
1887 spr_register(env, SPR_40x_DAC1, "DAC",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_40x_IAC1, "IAC",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 /* Storage control */
035feb88 1897 /* XXX: TODO: not implemented */
2662a059
JM		 1898 spr_register(env, SPR_405_SLER, "SLER",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_40x_sler,
1901 0x00000000);
035feb88
JM		 1902 /* not emulated, as Qemu never does speculative access */
1903 spr_register(env, SPR_40x_SGR, "SGR",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0xFFFFFFFF);
1907 /* not emulated, as Qemu do not emulate caches */
1908 spr_register(env, SPR_40x_DCWR, "DCWR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
2662a059
JM		 1912}
1913
a750fc0b
JM		 1914static void gen_spr_401x2 (CPUPPCState *env)
1915{
1916 gen_spr_401(env);
1917 spr_register(env, SPR_40x_PID, "PID",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_40x_ZPR, "ZPR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925}
1926
76a66253
JM		 1927/* SPR specific to PowerPC 403 implementation */
1928static void gen_spr_403 (CPUPPCState *env)
1929{
2662a059
JM		 1930 /* Debug interface */
1931 /* XXX : not implemented */
1932 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_40x_dbcr0,
1935 0x00000000);
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_40x_DBSR, "DBSR",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_clear,
1940 /* Last reset was system reset */
1941 0x00000300);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_40x_DAC1, "DAC1",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
578bb252 1947 /* XXX : not implemented */
2662a059
JM		 1948 spr_register(env, SPR_40x_DAC2, "DAC2",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_IAC1, "IAC1",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
578bb252 1957 /* XXX : not implemented */
2662a059
JM		 1958 spr_register(env, SPR_40x_IAC2, "IAC2",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
a750fc0b
JM		 1962}
1963
1964static void gen_spr_403_real (CPUPPCState *env)
1965{
76a66253
JM		 1966 spr_register(env, SPR_403_PBL1, "PBL1",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_403_pbr, &spr_write_403_pbr,
1969 0x00000000);
1970 spr_register(env, SPR_403_PBU1, "PBU1",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_403_pbr, &spr_write_403_pbr,
1973 0x00000000);
1974 spr_register(env, SPR_403_PBL2, "PBL2",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_403_pbr, &spr_write_403_pbr,
1977 0x00000000);
1978 spr_register(env, SPR_403_PBU2, "PBU2",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_403_pbr, &spr_write_403_pbr,
1981 0x00000000);
a750fc0b
JM		 1982}
1983
1984static void gen_spr_403_mmu (CPUPPCState *env)
1985{
1986 /* MMU */
1987 spr_register(env, SPR_40x_PID, "PID",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
2662a059 1991 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_generic,
1994 0x00000000);
1995}
1996
1997/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 1998static void gen_spr_compress (CPUPPCState *env)
1999{
578bb252 2000 /* XXX : not implemented */
76a66253
JM		 2001 spr_register(env, SPR_401_SKR, "SKR",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005}
a750fc0b
JM		 2006
2007#if defined (TARGET_PPC64)
a750fc0b
JM		 2008/* SPR specific to PowerPC 620 */
2009static void gen_spr_620 (CPUPPCState *env)
2010{
578bb252 2011 /* XXX : not implemented */
a750fc0b
JM		 2012 spr_register(env, SPR_620_PMR0, "PMR0",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
578bb252 2016 /* XXX : not implemented */
a750fc0b
JM		 2017 spr_register(env, SPR_620_PMR1, "PMR1",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
578bb252 2021 /* XXX : not implemented */
a750fc0b
JM		 2022 spr_register(env, SPR_620_PMR2, "PMR2",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0x00000000);
578bb252 2026 /* XXX : not implemented */
a750fc0b
JM		 2027 spr_register(env, SPR_620_PMR3, "PMR3",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
578bb252 2031 /* XXX : not implemented */
a750fc0b
JM		 2032 spr_register(env, SPR_620_PMR4, "PMR4",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2035 0x00000000);
578bb252 2036 /* XXX : not implemented */
a750fc0b
JM		 2037 spr_register(env, SPR_620_PMR5, "PMR5",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_generic,
2040 0x00000000);
578bb252 2041 /* XXX : not implemented */
a750fc0b
JM		 2042 spr_register(env, SPR_620_PMR6, "PMR6",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
578bb252 2046 /* XXX : not implemented */
a750fc0b
JM		 2047 spr_register(env, SPR_620_PMR7, "PMR7",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_generic,
2050 0x00000000);
578bb252 2051 /* XXX : not implemented */
a750fc0b
JM		 2052 spr_register(env, SPR_620_PMR8, "PMR8",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2055 0x00000000);
578bb252 2056 /* XXX : not implemented */
a750fc0b
JM		 2057 spr_register(env, SPR_620_PMR9, "PMR9",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_generic,
2060 0x00000000);
578bb252 2061 /* XXX : not implemented */
a750fc0b
JM		 2062 spr_register(env, SPR_620_PMRA, "PMR10",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_generic,
2065 0x00000000);
578bb252 2066 /* XXX : not implemented */
a750fc0b
JM		 2067 spr_register(env, SPR_620_PMRB, "PMR11",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
578bb252 2071 /* XXX : not implemented */
a750fc0b
JM		 2072 spr_register(env, SPR_620_PMRC, "PMR12",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
578bb252 2076 /* XXX : not implemented */
a750fc0b
JM		 2077 spr_register(env, SPR_620_PMRD, "PMR13",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, &spr_write_generic,
2080 0x00000000);
578bb252 2081 /* XXX : not implemented */
a750fc0b
JM		 2082 spr_register(env, SPR_620_PMRE, "PMR14",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_generic,
2085 0x00000000);
578bb252 2086 /* XXX : not implemented */
a750fc0b
JM		 2087 spr_register(env, SPR_620_PMRF, "PMR15",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
578bb252 2091 /* XXX : not implemented */
a750fc0b
JM		 2092 spr_register(env, SPR_620_HID8, "HID8",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
578bb252 2096 /* XXX : not implemented */
a750fc0b
JM		 2097 spr_register(env, SPR_620_HID9, "HID9",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101}
a750fc0b 2102#endif /* defined (TARGET_PPC64) */
76a66253 2103
80d11f44 2104static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2105{
80d11f44
JM		 2106 /* Exception processing */
2107 spr_register(env, SPR_DSISR, "DSISR",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 spr_register(env, SPR_DAR, "DAR",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 /* Timer */
2116 spr_register(env, SPR_DECR, "DECR",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_decr, &spr_write_decr,
2119 0x00000000);
2120 /* XXX : not implemented */
2121 spr_register(env, SPR_MPC_EIE, "EIE",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, &spr_write_generic,
2124 0x00000000);
2125 /* XXX : not implemented */
2126 spr_register(env, SPR_MPC_EID, "EID",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, &spr_write_generic,
2129 0x00000000);
2130 /* XXX : not implemented */
2131 spr_register(env, SPR_MPC_NRI, "NRI",
2132 SPR_NOACCESS, SPR_NOACCESS,
2133 &spr_read_generic, &spr_write_generic,
2134 0x00000000);
2135 /* XXX : not implemented */
2136 spr_register(env, SPR_MPC_CMPA, "CMPA",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 /* XXX : not implemented */
2141 spr_register(env, SPR_MPC_CMPB, "CMPB",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
2145 /* XXX : not implemented */
2146 spr_register(env, SPR_MPC_CMPC, "CMPC",
2147 SPR_NOACCESS, SPR_NOACCESS,
2148 &spr_read_generic, &spr_write_generic,
2149 0x00000000);
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_MPC_CMPD, "CMPD",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
2155 /* XXX : not implemented */
2156 spr_register(env, SPR_MPC_ECR, "ECR",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_generic, &spr_write_generic,
2159 0x00000000);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_MPC_DER, "DER",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, &spr_write_generic,
2164 0x00000000);
2165 /* XXX : not implemented */
2166 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2167 SPR_NOACCESS, SPR_NOACCESS,
2168 &spr_read_generic, &spr_write_generic,
2169 0x00000000);
2170 /* XXX : not implemented */
2171 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 /* XXX : not implemented */
2176 spr_register(env, SPR_MPC_CMPE, "CMPE",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, &spr_write_generic,
2179 0x00000000);
2180 /* XXX : not implemented */
2181 spr_register(env, SPR_MPC_CMPF, "CMPF",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_generic, &spr_write_generic,
2184 0x00000000);
2185 /* XXX : not implemented */
2186 spr_register(env, SPR_MPC_CMPG, "CMPG",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
2190 /* XXX : not implemented */
2191 spr_register(env, SPR_MPC_CMPH, "CMPH",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, &spr_write_generic,
2194 0x00000000);
2195 /* XXX : not implemented */
2196 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 0x00000000);
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205 /* XXX : not implemented */
2206 spr_register(env, SPR_MPC_BAR, "BAR",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 /* XXX : not implemented */
2211 spr_register(env, SPR_MPC_DPDR, "DPDR",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_MPC_IMMR, "IMMR",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220}
2221
2222static void gen_spr_5xx (CPUPPCState *env)
2223{
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329}
2330
2331static void gen_spr_8xx (CPUPPCState *env)
2332{
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433 /* XXX : not implemented */
2434 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2435 SPR_NOACCESS, SPR_NOACCESS,
2436 &spr_read_generic, &spr_write_generic,
2437 0x00000000);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458}
2459
2460// XXX: TODO
2461/*
2462 * AMR => SPR 29 (Power 2.04)
2463 * CTRL => SPR 136 (Power 2.04)
2464 * CTRL => SPR 152 (Power 2.04)
2465 * SCOMC => SPR 276 (64 bits ?)
2466 * SCOMD => SPR 277 (64 bits ?)
2467 * TBU40 => SPR 286 (Power 2.04 hypv)
2468 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2469 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2470 * HDSISR => SPR 306 (Power 2.04 hypv)
2471 * HDAR => SPR 307 (Power 2.04 hypv)
2472 * PURR => SPR 309 (Power 2.04 hypv)
2473 * HDEC => SPR 310 (Power 2.04 hypv)
2474 * HIOR => SPR 311 (hypv)
2475 * RMOR => SPR 312 (970)
2476 * HRMOR => SPR 313 (Power 2.04 hypv)
2477 * HSRR0 => SPR 314 (Power 2.04 hypv)
2478 * HSRR1 => SPR 315 (Power 2.04 hypv)
2479 * LPCR => SPR 316 (970)
2480 * LPIDR => SPR 317 (970)
2481 * SPEFSCR => SPR 512 (Power 2.04 emb)
2482 * EPR => SPR 702 (Power 2.04 emb)
2483 * perf => 768-783 (Power 2.04)
2484 * perf => 784-799 (Power 2.04)
2485 * PPR => SPR 896 (Power 2.04)
2486 * EPLC => SPR 947 (Power 2.04 emb)
2487 * EPSC => SPR 948 (Power 2.04 emb)
2488 * DABRX => 1015 (Power 2.04 hypv)
2489 * FPECR => SPR 1022 (?)
2490 * ... and more (thermal management, performance counters, ...)
2491 */
2492
2493/*****************************************************************************/
2494/* Exception vectors models */
2495static void init_excp_4xx_real (CPUPPCState *env)
2496{
2497#if !defined(CONFIG_USER_ONLY)
2498 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2499 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2500 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2501 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2502 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2503 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2504 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2505 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2506 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2507 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
faadf50e 2508 env->excp_prefix = 0x00000000UL;
80d11f44 2509 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2510 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2511 /* Hardware reset vector */
2512 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2513#endif
2514}
2515
80d11f44
JM		 2516static void init_excp_4xx_softmmu (CPUPPCState *env)
2517{
2518#if !defined(CONFIG_USER_ONLY)
2519 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2520 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2521 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2522 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2523 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2524 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2525 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2526 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2527 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2528 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2529 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2530 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2531 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2532 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2533 env->excp_prefix = 0x00000000UL;
2534 env->ivor_mask = 0x0000FFF0UL;
2535 env->ivpr_mask = 0xFFFF0000UL;
2536 /* Hardware reset vector */
2537 env->hreset_vector = 0xFFFFFFFCUL;
2538#endif
2539}
2540
2541static void init_excp_MPC5xx (CPUPPCState *env)
2542{
2543#if !defined(CONFIG_USER_ONLY)
2544 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2545 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2546 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2547 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2548 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2549 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2550 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2551 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2552 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2553 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2554 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2555 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2556 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2557 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2558 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2559 env->excp_prefix = 0x00000000UL;
2560 env->ivor_mask = 0x0000FFF0UL;
2561 env->ivpr_mask = 0xFFFF0000UL;
2562 /* Hardware reset vector */
2563 env->hreset_vector = 0xFFFFFFFCUL;
2564#endif
2565}
2566
2567static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2568{
2569#if !defined(CONFIG_USER_ONLY)
2570 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2571 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2572 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2573 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2574 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2575 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2576 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2577 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2578 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2579 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2580 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2581 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2582 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2583 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2584 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2585 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2586 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2587 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2588 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2589 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2590 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2591 env->excp_prefix = 0x00000000UL;
2592 env->ivor_mask = 0x0000FFF0UL;
2593 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2594 /* Hardware reset vector */
80d11f44 2595 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2596#endif
2597}
2598
80d11f44 2599static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2600{
2601#if !defined(CONFIG_USER_ONLY)
2602 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2603 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2604 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2605 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2606 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2607 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2608 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2609 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2610 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2611 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2612 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2613 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2614 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2615 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2616 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2617 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2618 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2619 env->excp_prefix = 0x00000000UL;
2620 /* Hardware reset vector */
2621 env->hreset_vector = 0xFFFFFFFCUL;
2622#endif
2623}
2624
2625static void init_excp_e200 (CPUPPCState *env)
2626{
2627#if !defined(CONFIG_USER_ONLY)
2628 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2629 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2630 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2631 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2632 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2633 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2634 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2635 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2636 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2637 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2638 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2639 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2640 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2641 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2642 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2643 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2644 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2645 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2646 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2647 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2648 env->excp_prefix = 0x00000000UL;
2649 env->ivor_mask = 0x0000FFF7UL;
2650 env->ivpr_mask = 0xFFFF0000UL;
2651 /* Hardware reset vector */
2652 env->hreset_vector = 0xFFFFFFFCUL;
2653#endif
2654}
2655
2656static void init_excp_BookE (CPUPPCState *env)
2657{
2658#if !defined(CONFIG_USER_ONLY)
2659 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2660 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2661 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2662 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2663 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2664 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2665 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2666 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2667 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2668 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2669 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2670 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2671 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2672 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2673 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2674 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2675 env->excp_prefix = 0x00000000UL;
2676 env->ivor_mask = 0x0000FFE0UL;
2677 env->ivpr_mask = 0xFFFF0000UL;
2678 /* Hardware reset vector */
2679 env->hreset_vector = 0xFFFFFFFCUL;
2680#endif
2681}
2682
2683static void init_excp_601 (CPUPPCState *env)
2684{
2685#if !defined(CONFIG_USER_ONLY)
2686 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2688 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2689 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2690 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2691 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2692 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2693 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2694 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2695 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2696 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2697 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
faadf50e 2698 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2699 /* Hardware reset vector */
80d11f44 2700 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2701#endif
2702}
2703
80d11f44 2704static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2705{
2706#if !defined(CONFIG_USER_ONLY)
2707 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2708 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2709 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2710 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2711 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2712 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2713 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2714 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2715 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2716 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2717 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
80d11f44 2718 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
e1833e1f
JM		 2719 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2720 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2721 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2722 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2723 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2724 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2725 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2726 env->excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2727 /* Hardware reset vector */
2728 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2729#endif
2730}
2731
80d11f44 2732static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2733{
2734#if !defined(CONFIG_USER_ONLY)
2735 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2736 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2737 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2738 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2739 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2740 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2741 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2742 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2743 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2744 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2745 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2746 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2747 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2748 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2749 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2750 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2751 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2754#endif
2755}
2756
2757static void init_excp_604 (CPUPPCState *env)
2758{
2759#if !defined(CONFIG_USER_ONLY)
2760 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2761 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2762 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2763 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2764 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2765 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2766 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2767 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2768 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2769 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2770 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2771 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2772 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2773 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2774 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2775 /* Hardware reset vector */
2776 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2777#endif
2778}
2779
578bb252 2780#if defined(TARGET_PPC64)
e1833e1f
JM		 2781static void init_excp_620 (CPUPPCState *env)
2782{
2783#if !defined(CONFIG_USER_ONLY)
2784 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
faadf50e 2787 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
e1833e1f 2788 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
faadf50e 2789 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
e1833e1f
JM		 2790 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2791 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2792 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2793 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2795 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2796 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2797 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2798 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2799 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2800 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2801 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2802 /* Hardware reset vector */
faadf50e 2803 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2804#endif
2805}
578bb252 2806#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2807
2808static void init_excp_7x0 (CPUPPCState *env)
2809{
2810#if !defined(CONFIG_USER_ONLY)
2811 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2819 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2820 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2821 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2822 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2823 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2824 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2825 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2826 /* Hardware reset vector */
2827 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2828#endif
2829}
2830
2831static void init_excp_750FX (CPUPPCState *env)
2832{
2833#if !defined(CONFIG_USER_ONLY)
2834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2835 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2836 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2837 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2838 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2839 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2840 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2841 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2842 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2844 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2845 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2846 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2847 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2848 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2849 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2850 /* Hardware reset vector */
2851 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2852#endif
2853}
2854
7a3a6927
JM		 2855/* XXX: Check if this is correct */
2856static void init_excp_7x5 (CPUPPCState *env)
2857{
2858#if !defined(CONFIG_USER_ONLY)
2859 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2860 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2861 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2862 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2863 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2864 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2865 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2866 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2867 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2868 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2869 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2870 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2871 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2872 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2873 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2874 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2875 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2876 env->excp_prefix = 0x00000000UL;
7a3a6927
JM		 2877 /* Hardware reset vector */
2878 env->hreset_vector = 0xFFFFFFFCUL;
2879#endif
2880}
2881
e1833e1f
JM		 2882static void init_excp_7400 (CPUPPCState *env)
2883{
2884#if !defined(CONFIG_USER_ONLY)
2885 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2886 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2887 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2888 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2889 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2890 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2891 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2892 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2893 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2894 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2895 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2896 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2897 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2900 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2901 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2902 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2903 /* Hardware reset vector */
2904 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2905#endif
2906}
2907
e1833e1f
JM		 2908static void init_excp_7450 (CPUPPCState *env)
2909{
2910#if !defined(CONFIG_USER_ONLY)
2911 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2912 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2913 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2914 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2915 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2916 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2917 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2918 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2920 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2921 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2922 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2923 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2924 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2925 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2926 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2927 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2928 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2929 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
faadf50e 2930 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2931 /* Hardware reset vector */
2932 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2933#endif
2934}
e1833e1f
JM		 2935
2936#if defined (TARGET_PPC64)
2937static void init_excp_970 (CPUPPCState *env)
2938{
2939#if !defined(CONFIG_USER_ONLY)
2940 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2941 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2942 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2943 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2951 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2955 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2956 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2957 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2958 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2959 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
faadf50e 2960 env->excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 2961 /* Hardware reset vector */
2962 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2963#endif
2964}
2965#endif
2966
2f462816
JM		 2967/*****************************************************************************/
2968/* Power management enable checks */
2969static int check_pow_none (CPUPPCState *env)
2970{
2971 return 0;
2972}
2973
2974static int check_pow_nocheck (CPUPPCState *env)
2975{
2976 return 1;
2977}
2978
2979static int check_pow_hid0 (CPUPPCState *env)
2980{
2981 if (env->spr[SPR_HID0] & 0x00E00000)
2982 return 1;
2983
2984 return 0;
2985}
2986
a750fc0b
JM		 2987/*****************************************************************************/
2988/* PowerPC implementations definitions */
76a66253 2989
a750fc0b 2990/* PowerPC 40x instruction set */
05332d70 2991#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \
1b413d55 2992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
76a66253 2993
a750fc0b 2994/* PowerPC 401 */
05332d70 2995#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 2996 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2997 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2998#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 2999#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3000#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3001#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3002#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
25ba3a68 3003#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3004#define check_pow_401 check_pow_nocheck
76a66253 3005
a750fc0b
JM		 3006static void init_proc_401 (CPUPPCState *env)
3007{
3008 gen_spr_40x(env);
3009 gen_spr_401_403(env);
3010 gen_spr_401(env);
e1833e1f 3011 init_excp_4xx_real(env);
d63001d1
JM		 3012 env->dcache_line_size = 32;
3013 env->icache_line_size = 32;
4e290a0b
JM		 3014 /* Allocate hardware IRQ controller */
3015 ppc40x_irq_init(env);
a750fc0b 3016}
76a66253 3017
a750fc0b 3018/* PowerPC 401x2 */
05332d70 3019#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3020 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3021 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3022 PPC_CACHE_DCBA | PPC_MFTB | \
3023 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3024#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3025#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3026#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3027#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3028#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
25ba3a68 3029#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3030#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3031
3032static void init_proc_401x2 (CPUPPCState *env)
3033{
3034 gen_spr_40x(env);
3035 gen_spr_401_403(env);
3036 gen_spr_401x2(env);
3037 gen_spr_compress(env);
a750fc0b 3038 /* Memory management */
f2e63a42 3039#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3040 env->nb_tlb = 64;
3041 env->nb_ways = 1;
3042 env->id_tlbs = 0;
f2e63a42 3043#endif
e1833e1f 3044 init_excp_4xx_softmmu(env);
d63001d1
JM		 3045 env->dcache_line_size = 32;
3046 env->icache_line_size = 32;
4e290a0b
JM		 3047 /* Allocate hardware IRQ controller */
3048 ppc40x_irq_init(env);
76a66253
JM		 3049}
3050
a750fc0b 3051/* PowerPC 401x3 */
05332d70 3052#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3053 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3054 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3055 PPC_CACHE_DCBA | PPC_MFTB | \
3056 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3057#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3058#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3059#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3060#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3061#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
25ba3a68 3062#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3063#define check_pow_401x3 check_pow_nocheck
a750fc0b 3064
578bb252 3065__attribute__ (( unused ))
e1833e1f 3066static void init_proc_401x3 (CPUPPCState *env)
76a66253 3067{
4e290a0b
JM		 3068 gen_spr_40x(env);
3069 gen_spr_401_403(env);
3070 gen_spr_401(env);
3071 gen_spr_401x2(env);
3072 gen_spr_compress(env);
e1833e1f 3073 init_excp_4xx_softmmu(env);
d63001d1
JM		 3074 env->dcache_line_size = 32;
3075 env->icache_line_size = 32;
4e290a0b
JM		 3076 /* Allocate hardware IRQ controller */
3077 ppc40x_irq_init(env);
3fc6c082 3078}
a750fc0b
JM		 3079
3080/* IOP480 */
05332d70 3081#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3082 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3083 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3084 PPC_CACHE_DCBA | \
3085 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3086#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3087#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3088#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3089#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3090#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
25ba3a68 3091#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 3092#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3093
3094static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3095{
a750fc0b
JM		 3096 gen_spr_40x(env);
3097 gen_spr_401_403(env);
3098 gen_spr_401x2(env);
3099 gen_spr_compress(env);
a750fc0b 3100 /* Memory management */
f2e63a42 3101#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3102 env->nb_tlb = 64;
3103 env->nb_ways = 1;
3104 env->id_tlbs = 0;
f2e63a42 3105#endif
e1833e1f 3106 init_excp_4xx_softmmu(env);
d63001d1
JM		 3107 env->dcache_line_size = 32;
3108 env->icache_line_size = 32;
4e290a0b
JM		 3109 /* Allocate hardware IRQ controller */
3110 ppc40x_irq_init(env);
3fc6c082
FB		 3111}
3112
a750fc0b 3113/* PowerPC 403 */
05332d70 3114#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b 3115 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
a750fc0b
JM		 3116 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3117#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3118#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3119#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3120#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3121#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
25ba3a68 3122#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2f462816 3123#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3124
3125static void init_proc_403 (CPUPPCState *env)
3fc6c082 3126{
a750fc0b
JM		 3127 gen_spr_40x(env);
3128 gen_spr_401_403(env);
3129 gen_spr_403(env);
3130 gen_spr_403_real(env);
e1833e1f 3131 init_excp_4xx_real(env);
d63001d1
JM		 3132 env->dcache_line_size = 32;
3133 env->icache_line_size = 32;
4e290a0b
JM		 3134 /* Allocate hardware IRQ controller */
3135 ppc40x_irq_init(env);
d63001d1
JM		 3136#if !defined(CONFIG_USER_ONLY)
3137 /* Hardware reset vector */
3138 env->hreset_vector = 0xFFFFFFFCUL;
3139#endif
3fc6c082
FB		 3140}
3141
a750fc0b 3142/* PowerPC 403 GCX */
05332d70 3143#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
a750fc0b
JM		 3144 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3145 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3146 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
3147#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3148#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3149#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3150#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3151#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
25ba3a68 3152#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2f462816 3153#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3154
3155static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3156{
a750fc0b
JM		 3157 gen_spr_40x(env);
3158 gen_spr_401_403(env);
3159 gen_spr_403(env);
3160 gen_spr_403_real(env);
3161 gen_spr_403_mmu(env);
3162 /* Bus access control */
035feb88 3163 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3164 spr_register(env, SPR_40x_SGR, "SGR",
3165 SPR_NOACCESS, SPR_NOACCESS,
3166 &spr_read_generic, &spr_write_generic,
3167 0xFFFFFFFF);
035feb88 3168 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3169 spr_register(env, SPR_40x_DCWR, "DCWR",
3170 SPR_NOACCESS, SPR_NOACCESS,
3171 &spr_read_generic, &spr_write_generic,
3172 0x00000000);
3173 /* Memory management */
f2e63a42 3174#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3175 env->nb_tlb = 64;
3176 env->nb_ways = 1;
3177 env->id_tlbs = 0;
f2e63a42 3178#endif
80d11f44
JM		 3179 init_excp_4xx_softmmu(env);
3180 env->dcache_line_size = 32;
3181 env->icache_line_size = 32;
3182 /* Allocate hardware IRQ controller */
3183 ppc40x_irq_init(env);
3184}
3185
3186/* PowerPC 405 */
3187#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3188 PPC_MFTB | \
3189 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
3190 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3191 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
3192 PPC_405_MAC)
3193#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3194#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3195#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3196#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3197#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3198#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3199 POWERPC_FLAG_DE)
3200#define check_pow_405 check_pow_nocheck
3201
3202static void init_proc_405 (CPUPPCState *env)
3203{
3204 /* Time base */
3205 gen_tbl(env);
3206 gen_spr_40x(env);
3207 gen_spr_405(env);
3208 /* Bus access control */
3209 /* not emulated, as Qemu never does speculative access */
3210 spr_register(env, SPR_40x_SGR, "SGR",
3211 SPR_NOACCESS, SPR_NOACCESS,
3212 &spr_read_generic, &spr_write_generic,
3213 0xFFFFFFFF);
3214 /* not emulated, as Qemu do not emulate caches */
3215 spr_register(env, SPR_40x_DCWR, "DCWR",
3216 SPR_NOACCESS, SPR_NOACCESS,
3217 &spr_read_generic, &spr_write_generic,
3218 0x00000000);
3219 /* Memory management */
3220#if !defined(CONFIG_USER_ONLY)
3221 env->nb_tlb = 64;
3222 env->nb_ways = 1;
3223 env->id_tlbs = 0;
3224#endif
3225 init_excp_4xx_softmmu(env);
3226 env->dcache_line_size = 32;
3227 env->icache_line_size = 32;
3228 /* Allocate hardware IRQ controller */
3229 ppc40x_irq_init(env);
3230}
3231
3232/* PowerPC 440 EP */
3233#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3234 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3235 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3236 PPC_440_SPEC | PPC_RFMCI)
3237#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3238#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3239#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3240#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3241#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3242#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3243 POWERPC_FLAG_DE)
3244#define check_pow_440EP check_pow_nocheck
3245
3246__attribute__ (( unused ))
3247static void init_proc_440EP (CPUPPCState *env)
3248{
3249 /* Time base */
3250 gen_tbl(env);
3251 gen_spr_BookE(env, 0x000000000000FFFFULL);
3252 gen_spr_440(env);
3253 gen_spr_usprgh(env);
3254 /* Processor identification */
3255 spr_register(env, SPR_BOOKE_PIR, "PIR",
3256 SPR_NOACCESS, SPR_NOACCESS,
3257 &spr_read_generic, &spr_write_pir,
3258 0x00000000);
3259 /* XXX : not implemented */
3260 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3261 SPR_NOACCESS, SPR_NOACCESS,
3262 &spr_read_generic, &spr_write_generic,
3263 0x00000000);
3264 /* XXX : not implemented */
3265 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3266 SPR_NOACCESS, SPR_NOACCESS,
3267 &spr_read_generic, &spr_write_generic,
3268 0x00000000);
3269 /* XXX : not implemented */
3270 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3271 SPR_NOACCESS, SPR_NOACCESS,
3272 &spr_read_generic, &spr_write_generic,
3273 0x00000000);
3274 /* XXX : not implemented */
3275 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3276 SPR_NOACCESS, SPR_NOACCESS,
3277 &spr_read_generic, &spr_write_generic,
3278 0x00000000);
3279 /* XXX : not implemented */
3280 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3281 SPR_NOACCESS, SPR_NOACCESS,
3282 &spr_read_generic, &spr_write_generic,
3283 0x00000000);
3284 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3285 SPR_NOACCESS, SPR_NOACCESS,
3286 &spr_read_generic, &spr_write_generic,
3287 0x00000000);
3288 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3289 SPR_NOACCESS, SPR_NOACCESS,
3290 &spr_read_generic, &spr_write_generic,
3291 0x00000000);
3292 /* XXX : not implemented */
3293 spr_register(env, SPR_440_CCR1, "CCR1",
3294 SPR_NOACCESS, SPR_NOACCESS,
3295 &spr_read_generic, &spr_write_generic,
3296 0x00000000);
3297 /* Memory management */
3298#if !defined(CONFIG_USER_ONLY)
3299 env->nb_tlb = 64;
3300 env->nb_ways = 1;
3301 env->id_tlbs = 0;
3302#endif
3303 init_excp_BookE(env);
3304 env->dcache_line_size = 32;
3305 env->icache_line_size = 32;
3306 /* XXX: TODO: allocate internal IRQ controller */
3307}
3308
3309/* PowerPC 440 GP */
3310#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \
3311 PPC_DCR | PPC_DCRX | \
3312 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3313 PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3314 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3315#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3316#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3317#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3318#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3319#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3320#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3321 POWERPC_FLAG_DE)
3322#define check_pow_440GP check_pow_nocheck
3323
3324__attribute__ (( unused ))
3325static void init_proc_440GP (CPUPPCState *env)
3326{
3327 /* Time base */
3328 gen_tbl(env);
3329 gen_spr_BookE(env, 0x000000000000FFFFULL);
3330 gen_spr_440(env);
3331 gen_spr_usprgh(env);
3332 /* Processor identification */
3333 spr_register(env, SPR_BOOKE_PIR, "PIR",
3334 SPR_NOACCESS, SPR_NOACCESS,
3335 &spr_read_generic, &spr_write_pir,
3336 0x00000000);
3337 /* XXX : not implemented */
3338 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3339 SPR_NOACCESS, SPR_NOACCESS,
3340 &spr_read_generic, &spr_write_generic,
3341 0x00000000);
3342 /* XXX : not implemented */
3343 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3344 SPR_NOACCESS, SPR_NOACCESS,
3345 &spr_read_generic, &spr_write_generic,
3346 0x00000000);
3347 /* XXX : not implemented */
3348 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3349 SPR_NOACCESS, SPR_NOACCESS,
3350 &spr_read_generic, &spr_write_generic,
3351 0x00000000);
3352 /* XXX : not implemented */
3353 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3354 SPR_NOACCESS, SPR_NOACCESS,
3355 &spr_read_generic, &spr_write_generic,
3356 0x00000000);
3357 /* Memory management */
3358#if !defined(CONFIG_USER_ONLY)
3359 env->nb_tlb = 64;
3360 env->nb_ways = 1;
3361 env->id_tlbs = 0;
3362#endif
3363 init_excp_BookE(env);
3364 env->dcache_line_size = 32;
3365 env->icache_line_size = 32;
3366 /* XXX: TODO: allocate internal IRQ controller */
3367}
3368
3369/* PowerPC 440x4 */
3370#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3371 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3372 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3373 PPC_440_SPEC)
3374#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3375#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3376#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3377#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3378#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3379#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3380 POWERPC_FLAG_DE)
3381#define check_pow_440x4 check_pow_nocheck
3382
3383__attribute__ (( unused ))
3384static void init_proc_440x4 (CPUPPCState *env)
3385{
3386 /* Time base */
3387 gen_tbl(env);
3388 gen_spr_BookE(env, 0x000000000000FFFFULL);
3389 gen_spr_440(env);
3390 gen_spr_usprgh(env);
3391 /* Processor identification */
3392 spr_register(env, SPR_BOOKE_PIR, "PIR",
3393 SPR_NOACCESS, SPR_NOACCESS,
3394 &spr_read_generic, &spr_write_pir,
3395 0x00000000);
3396 /* XXX : not implemented */
3397 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3398 SPR_NOACCESS, SPR_NOACCESS,
3399 &spr_read_generic, &spr_write_generic,
3400 0x00000000);
3401 /* XXX : not implemented */
3402 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3403 SPR_NOACCESS, SPR_NOACCESS,
3404 &spr_read_generic, &spr_write_generic,
3405 0x00000000);
3406 /* XXX : not implemented */
3407 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3408 SPR_NOACCESS, SPR_NOACCESS,
3409 &spr_read_generic, &spr_write_generic,
3410 0x00000000);
3411 /* XXX : not implemented */
3412 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3413 SPR_NOACCESS, SPR_NOACCESS,
3414 &spr_read_generic, &spr_write_generic,
3415 0x00000000);
3416 /* Memory management */
3417#if !defined(CONFIG_USER_ONLY)
3418 env->nb_tlb = 64;
3419 env->nb_ways = 1;
3420 env->id_tlbs = 0;
3421#endif
3422 init_excp_BookE(env);
d63001d1
JM		 3423 env->dcache_line_size = 32;
3424 env->icache_line_size = 32;
80d11f44 3425 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3426}
3427
80d11f44
JM		 3428/* PowerPC 440x5 */
3429#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3430 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3431 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3432 PPC_440_SPEC | PPC_RFMCI)
3433#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3434#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3435#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3436#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3437#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3438#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
25ba3a68 3439 POWERPC_FLAG_DE)
80d11f44 3440#define check_pow_440x5 check_pow_nocheck
a750fc0b 3441
80d11f44
JM		 3442__attribute__ (( unused ))
3443static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3444{
a750fc0b
JM		 3445 /* Time base */
3446 gen_tbl(env);
80d11f44
JM		 3447 gen_spr_BookE(env, 0x000000000000FFFFULL);
3448 gen_spr_440(env);
3449 gen_spr_usprgh(env);
3450 /* Processor identification */
3451 spr_register(env, SPR_BOOKE_PIR, "PIR",
3452 SPR_NOACCESS, SPR_NOACCESS,
3453 &spr_read_generic, &spr_write_pir,
3454 0x00000000);
3455 /* XXX : not implemented */
3456 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3457 SPR_NOACCESS, SPR_NOACCESS,
3458 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3459 0x00000000);
3460 /* XXX : not implemented */
3461 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3462 SPR_NOACCESS, SPR_NOACCESS,
3463 &spr_read_generic, &spr_write_generic,
3464 0x00000000);
3465 /* XXX : not implemented */
3466 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3467 SPR_NOACCESS, SPR_NOACCESS,
3468 &spr_read_generic, &spr_write_generic,
3469 0x00000000);
3470 /* XXX : not implemented */
3471 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3472 SPR_NOACCESS, SPR_NOACCESS,
3473 &spr_read_generic, &spr_write_generic,
3474 0x00000000);
3475 /* XXX : not implemented */
3476 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3477 SPR_NOACCESS, SPR_NOACCESS,
3478 &spr_read_generic, &spr_write_generic,
3479 0x00000000);
3480 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3481 SPR_NOACCESS, SPR_NOACCESS,
3482 &spr_read_generic, &spr_write_generic,
3483 0x00000000);
3484 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3485 SPR_NOACCESS, SPR_NOACCESS,
3486 &spr_read_generic, &spr_write_generic,
3487 0x00000000);
3488 /* XXX : not implemented */
3489 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3490 SPR_NOACCESS, SPR_NOACCESS,
3491 &spr_read_generic, &spr_write_generic,
3492 0x00000000);
3493 /* Memory management */
f2e63a42 3494#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3495 env->nb_tlb = 64;
3496 env->nb_ways = 1;
3497 env->id_tlbs = 0;
f2e63a42 3498#endif
80d11f44 3499 init_excp_BookE(env);
d63001d1
JM		 3500 env->dcache_line_size = 32;
3501 env->icache_line_size = 32;
80d11f44 3502 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3503}
3504
80d11f44
JM		 3505/* PowerPC 460 (guessed) */
3506#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \
3507 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
a750fc0b 3508 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
80d11f44
JM		 3509 PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3510 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3511#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3512#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3513#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3514#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3515#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3516#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
25ba3a68 3517 POWERPC_FLAG_DE)
80d11f44 3518#define check_pow_460 check_pow_nocheck
a750fc0b 3519
80d11f44
JM		 3520__attribute__ (( unused ))
3521static void init_proc_460 (CPUPPCState *env)
3fc6c082 3522{
a750fc0b
JM		 3523 /* Time base */
3524 gen_tbl(env);
80d11f44 3525 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3526 gen_spr_440(env);
80d11f44
JM		 3527 gen_spr_usprgh(env);
3528 /* Processor identification */
3529 spr_register(env, SPR_BOOKE_PIR, "PIR",
3530 SPR_NOACCESS, SPR_NOACCESS,
3531 &spr_read_generic, &spr_write_pir,
3532 0x00000000);
3533 /* XXX : not implemented */
3534 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3535 SPR_NOACCESS, SPR_NOACCESS,
3536 &spr_read_generic, &spr_write_generic,
3537 0x00000000);
3538 /* XXX : not implemented */
3539 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3540 SPR_NOACCESS, SPR_NOACCESS,
3541 &spr_read_generic, &spr_write_generic,
3542 0x00000000);
3543 /* XXX : not implemented */
3544 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3545 SPR_NOACCESS, SPR_NOACCESS,
3546 &spr_read_generic, &spr_write_generic,
3547 0x00000000);
3548 /* XXX : not implemented */
3549 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, &spr_write_generic,
3552 0x00000000);
578bb252 3553 /* XXX : not implemented */
a750fc0b
JM		 3554 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_generic,
3557 0x00000000);
3558 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3559 SPR_NOACCESS, SPR_NOACCESS,
3560 &spr_read_generic, &spr_write_generic,
3561 0x00000000);
3562 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
578bb252 3566 /* XXX : not implemented */
a750fc0b
JM		 3567 spr_register(env, SPR_440_CCR1, "CCR1",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
80d11f44
JM		 3571 /* XXX : not implemented */
3572 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3573 &spr_read_generic, &spr_write_generic,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
a750fc0b 3576 /* Memory management */
f2e63a42 3577#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3578 env->nb_tlb = 64;
3579 env->nb_ways = 1;
3580 env->id_tlbs = 0;
f2e63a42 3581#endif
e1833e1f 3582 init_excp_BookE(env);
d63001d1
JM		 3583 env->dcache_line_size = 32;
3584 env->icache_line_size = 32;
a750fc0b 3585 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3586}
3587
80d11f44
JM		 3588/* PowerPC 460F (guessed) */
3589#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \
3590 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
a750fc0b 3591 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
80d11f44
JM		 3592 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3593 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3594 PPC_FLOAT_STFIWX | \
05332d70
JM		 3595 PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3596 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
80d11f44
JM		 3597#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3598#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3599#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3600#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3601#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3602#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
25ba3a68 3603 POWERPC_FLAG_DE)
80d11f44 3604#define check_pow_460F check_pow_nocheck
a750fc0b 3605
80d11f44
JM		 3606__attribute__ (( unused ))
3607static void init_proc_460F (CPUPPCState *env)
3fc6c082 3608{
a750fc0b
JM		 3609 /* Time base */
3610 gen_tbl(env);
80d11f44 3611 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3612 gen_spr_440(env);
80d11f44
JM		 3613 gen_spr_usprgh(env);
3614 /* Processor identification */
3615 spr_register(env, SPR_BOOKE_PIR, "PIR",
3616 SPR_NOACCESS, SPR_NOACCESS,
3617 &spr_read_generic, &spr_write_pir,
3618 0x00000000);
3619 /* XXX : not implemented */
3620 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3621 SPR_NOACCESS, SPR_NOACCESS,
3622 &spr_read_generic, &spr_write_generic,
3623 0x00000000);
3624 /* XXX : not implemented */
3625 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 /* XXX : not implemented */
3630 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
3648 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3649 SPR_NOACCESS, SPR_NOACCESS,
3650 &spr_read_generic, &spr_write_generic,
3651 0x00000000);
3652 /* XXX : not implemented */
3653 spr_register(env, SPR_440_CCR1, "CCR1",
3654 SPR_NOACCESS, SPR_NOACCESS,
3655 &spr_read_generic, &spr_write_generic,
3656 0x00000000);
3657 /* XXX : not implemented */
3658 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3659 &spr_read_generic, &spr_write_generic,
3660 &spr_read_generic, &spr_write_generic,
3661 0x00000000);
a750fc0b 3662 /* Memory management */
f2e63a42 3663#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3664 env->nb_tlb = 64;
3665 env->nb_ways = 1;
3666 env->id_tlbs = 0;
f2e63a42 3667#endif
e1833e1f 3668 init_excp_BookE(env);
d63001d1
JM		 3669 env->dcache_line_size = 32;
3670 env->icache_line_size = 32;
a750fc0b 3671 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3672}
3673
80d11f44
JM		 3674/* Freescale 5xx cores (aka RCPU) */
3675#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3676 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3677 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3678 PPC_MFTB)
3679#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3680#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3681#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3682#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3683#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
3684#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
3685#define check_pow_MPC5xx check_pow_none
3686
3687__attribute__ (( unused ))
3688static void init_proc_MPC5xx (CPUPPCState *env)
3689{
3690 /* Time base */
3691 gen_tbl(env);
3692 gen_spr_5xx_8xx(env);
3693 gen_spr_5xx(env);
3694 init_excp_MPC5xx(env);
3695 env->dcache_line_size = 32;
3696 env->icache_line_size = 32;
3697 /* XXX: TODO: allocate internal IRQ controller */
3698}
3699
3700/* Freescale 8xx cores (aka PowerQUICC) */
3701#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3702 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3703 PPC_CACHE_ICBI | PPC_MFTB)
3704#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3705#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3706#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3707#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3708#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
3709#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
3710#define check_pow_MPC8xx check_pow_none
3711
3712__attribute__ (( unused ))
3713static void init_proc_MPC8xx (CPUPPCState *env)
3714{
3715 /* Time base */
3716 gen_tbl(env);
3717 gen_spr_5xx_8xx(env);
3718 gen_spr_8xx(env);
3719 init_excp_MPC8xx(env);
3720 env->dcache_line_size = 32;
3721 env->icache_line_size = 32;
3722 /* XXX: TODO: allocate internal IRQ controller */
3723}
3724
3725/* Freescale 82xx cores (aka PowerQUICC-II) */
3726/* PowerPC G2 */
3727#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3728#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3729#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3730//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3731#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3732#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3733#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3734 POWERPC_FLAG_BE)
3735#define check_pow_G2 check_pow_hid0
a750fc0b 3736
80d11f44 3737static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3738{
80d11f44
JM		 3739 gen_spr_ne_601(env);
3740 gen_spr_G2_755(env);
3741 gen_spr_G2(env);
a750fc0b
JM		 3742 /* Time base */
3743 gen_tbl(env);
80d11f44
JM		 3744 /* Hardware implementation register */
3745 /* XXX : not implemented */
3746 spr_register(env, SPR_HID0, "HID0",
3747 SPR_NOACCESS, SPR_NOACCESS,
3748 &spr_read_generic, &spr_write_generic,
3749 0x00000000);
3750 /* XXX : not implemented */
3751 spr_register(env, SPR_HID1, "HID1",
3752 SPR_NOACCESS, SPR_NOACCESS,
3753 &spr_read_generic, &spr_write_generic,
3754 0x00000000);
3755 /* XXX : not implemented */
3756 spr_register(env, SPR_HID2, "HID2",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
a750fc0b 3760 /* Memory management */
80d11f44
JM		 3761 gen_low_BATs(env);
3762 gen_high_BATs(env);
3763 gen_6xx_7xx_soft_tlb(env, 64, 2);
3764 init_excp_G2(env);
d63001d1
JM		 3765 env->dcache_line_size = 32;
3766 env->icache_line_size = 32;
80d11f44
JM		 3767 /* Allocate hardware IRQ controller */
3768 ppc6xx_irq_init(env);
3fc6c082 3769}
a750fc0b 3770
80d11f44
JM		 3771/* PowerPC G2LE */
3772#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3773#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3774#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3775#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3776#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3777#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3778#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3779 POWERPC_FLAG_BE)
3780#define check_pow_G2LE check_pow_hid0
a750fc0b 3781
80d11f44 3782static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3783{
80d11f44
JM		 3784 gen_spr_ne_601(env);
3785 gen_spr_G2_755(env);
3786 gen_spr_G2(env);
a750fc0b
JM		 3787 /* Time base */
3788 gen_tbl(env);
80d11f44 3789 /* Hardware implementation register */
578bb252 3790 /* XXX : not implemented */
80d11f44 3791 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
80d11f44
JM		 3795 /* XXX : not implemented */
3796 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
578bb252 3800 /* XXX : not implemented */
80d11f44 3801 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* Memory management */
80d11f44
JM		 3806 gen_low_BATs(env);
3807 gen_high_BATs(env);
3808 gen_6xx_7xx_soft_tlb(env, 64, 2);
3809 init_excp_G2(env);
d63001d1
JM		 3810 env->dcache_line_size = 32;
3811 env->icache_line_size = 32;
80d11f44
JM		 3812 /* Allocate hardware IRQ controller */
3813 ppc6xx_irq_init(env);
3fc6c082
FB		 3814}
3815
80d11f44
JM		 3816/* e200 core */
3817/* XXX: unimplemented instructions:
3818 * dcblc
3819 * dcbtlst
3820 * dcbtstls
3821 * icblc
3822 * icbtls
3823 * tlbivax
3824 * all SPE multiply-accumulate instructions
3825 */
3826#define POWERPC_INSNS_e200 (POWERPC_INSNS_EMB | PPC_ISEL | \
3827 PPC_SPE | PPC_SPEFPU | \
3828 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3829 PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
3830 PPC_BOOKE | PPC_RFDI)
3831#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3832#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3833#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3834#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3835#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3836#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
3837 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
3838#define check_pow_e200 check_pow_hid0
3839
a750fc0b 3840
578bb252 3841__attribute__ (( unused ))
80d11f44 3842static void init_proc_e200 (CPUPPCState *env)
3fc6c082 3843{
e1833e1f
JM		 3844 /* Time base */
3845 gen_tbl(env);
80d11f44 3846 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 3847 /* XXX : not implemented */
80d11f44 3848 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
e1833e1f
JM		 3849 SPR_NOACCESS, SPR_NOACCESS,
3850 &spr_read_generic, &spr_write_generic,
3851 0x00000000);
80d11f44
JM		 3852 /* Memory management */
3853 gen_spr_BookE_FSL(env, 0x0000005D);
3854 /* XXX : not implemented */
3855 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 3856 SPR_NOACCESS, SPR_NOACCESS,
3857 &spr_read_generic, &spr_write_generic,
3858 0x00000000);
80d11f44
JM		 3859 /* XXX : not implemented */
3860 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 3861 SPR_NOACCESS, SPR_NOACCESS,
3862 &spr_read_generic, &spr_write_generic,
3863 0x00000000);
578bb252 3864 /* XXX : not implemented */
80d11f44 3865 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 3866 SPR_NOACCESS, SPR_NOACCESS,
3867 &spr_read_generic, &spr_write_generic,
3868 0x00000000);
578bb252 3869 /* XXX : not implemented */
80d11f44
JM		 3870 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3871 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 3872 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3873 0x00000000);
3874 /* XXX : not implemented */
3875 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
3878 0x00000000);
3879 /* XXX : not implemented */
3880 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* XXX : not implemented */
3905 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 /* XXX : not implemented */
3910 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* XXX : not implemented */
3915 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3916 SPR_NOACCESS, SPR_NOACCESS,
3917 &spr_read_generic, &spr_write_generic,
3918 0x00000000);
3919 /* XXX : not implemented */
3920 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3921 SPR_NOACCESS, SPR_NOACCESS,
3922 &spr_read_generic, &spr_write_generic,
3923 0x00000000);
3924 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3925 SPR_NOACCESS, SPR_NOACCESS,
3926 &spr_read_generic, &spr_write_generic,
3927 0x00000000);
3928 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3929 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
f2e63a42 3932#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 3933 env->nb_tlb = 64;
3934 env->nb_ways = 1;
3935 env->id_tlbs = 0;
f2e63a42 3936#endif
80d11f44 3937 init_excp_e200(env);
d63001d1
JM		 3938 env->dcache_line_size = 32;
3939 env->icache_line_size = 32;
e1833e1f 3940 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3941}
a750fc0b 3942
80d11f44
JM		 3943/* e300 core */
3944#define POWERPC_INSNS_e300 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3945#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
3946#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
3947#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
3948#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
3949#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
3950#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3951 POWERPC_FLAG_BE)
3952#define check_pow_e300 check_pow_hid0
a750fc0b 3953
578bb252 3954__attribute__ (( unused ))
80d11f44 3955static void init_proc_e300 (CPUPPCState *env)
3fc6c082 3956{
80d11f44
JM		 3957 gen_spr_ne_601(env);
3958 gen_spr_603(env);
a750fc0b
JM		 3959 /* Time base */
3960 gen_tbl(env);
80d11f44
JM		 3961 /* hardware implementation registers */
3962 /* XXX : not implemented */
3963 spr_register(env, SPR_HID0, "HID0",
3964 SPR_NOACCESS, SPR_NOACCESS,
3965 &spr_read_generic, &spr_write_generic,
3966 0x00000000);
3967 /* XXX : not implemented */
3968 spr_register(env, SPR_HID1, "HID1",
3969 SPR_NOACCESS, SPR_NOACCESS,
3970 &spr_read_generic, &spr_write_generic,
3971 0x00000000);
3972 /* Memory management */
3973 gen_low_BATs(env);
3974 gen_6xx_7xx_soft_tlb(env, 64, 2);
3975 init_excp_603(env);
3976 env->dcache_line_size = 32;
3977 env->icache_line_size = 32;
3978 /* Allocate hardware IRQ controller */
3979 ppc6xx_irq_init(env);
3980}
3981
3982/* e500 core */
3983#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | PPC_ISEL | \
3984 PPC_SPE | PPC_SPEFPU | \
3985 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3986 PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
3987 PPC_BOOKE | PPC_RFDI)
3988#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
3989#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
3990#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
3991#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3992#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
3993#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
3994 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
3995#define check_pow_e500 check_pow_hid0
3996
3997__attribute__ (( unused ))
3998static void init_proc_e500 (CPUPPCState *env)
3999{
4000 /* Time base */
4001 gen_tbl(env);
4002 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4003 /* Processor identification */
4004 spr_register(env, SPR_BOOKE_PIR, "PIR",
4005 SPR_NOACCESS, SPR_NOACCESS,
4006 &spr_read_generic, &spr_write_pir,
4007 0x00000000);
4008 /* XXX : not implemented */
4009 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4010 SPR_NOACCESS, SPR_NOACCESS,
4011 &spr_read_generic, &spr_write_generic,
4012 0x00000000);
4013 /* Memory management */
4014#if !defined(CONFIG_USER_ONLY)
4015 env->nb_pids = 3;
4016#endif
4017 gen_spr_BookE_FSL(env, 0x0000005F);
4018 /* XXX : not implemented */
4019 spr_register(env, SPR_HID0, "HID0",
4020 SPR_NOACCESS, SPR_NOACCESS,
4021 &spr_read_generic, &spr_write_generic,
4022 0x00000000);
4023 /* XXX : not implemented */
4024 spr_register(env, SPR_HID1, "HID1",
4025 SPR_NOACCESS, SPR_NOACCESS,
4026 &spr_read_generic, &spr_write_generic,
4027 0x00000000);
4028 /* XXX : not implemented */
4029 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4030 SPR_NOACCESS, SPR_NOACCESS,
4031 &spr_read_generic, &spr_write_generic,
4032 0x00000000);
4033 /* XXX : not implemented */
4034 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4035 SPR_NOACCESS, SPR_NOACCESS,
4036 &spr_read_generic, &spr_write_generic,
4037 0x00000000);
4038 /* XXX : not implemented */
4039 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4040 SPR_NOACCESS, SPR_NOACCESS,
4041 &spr_read_generic, &spr_write_generic,
4042 0x00000000);
578bb252 4043 /* XXX : not implemented */
a750fc0b
JM		 4044 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4045 SPR_NOACCESS, SPR_NOACCESS,
4046 &spr_read_generic, &spr_write_generic,
4047 0x00000000);
80d11f44
JM		 4048 /* XXX : not implemented */
4049 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4050 SPR_NOACCESS, SPR_NOACCESS,
4051 &spr_read_generic, &spr_write_generic,
4052 0x00000000);
80d11f44
JM		 4053 /* XXX : not implemented */
4054 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4055 SPR_NOACCESS, SPR_NOACCESS,
4056 &spr_read_generic, &spr_write_generic,
4057 0x00000000);
578bb252 4058 /* XXX : not implemented */
80d11f44 4059 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4060 SPR_NOACCESS, SPR_NOACCESS,
4061 &spr_read_generic, &spr_write_generic,
4062 0x00000000);
578bb252 4063 /* XXX : not implemented */
80d11f44
JM		 4064 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4065 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4066 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4067 0x00000000);
4068 /* XXX : not implemented */
4069 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4070 SPR_NOACCESS, SPR_NOACCESS,
4071 &spr_read_generic, &spr_write_generic,
4072 0x00000000);
4073 /* XXX : not implemented */
4074 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4075 SPR_NOACCESS, SPR_NOACCESS,
4076 &spr_read_generic, &spr_write_generic,
4077 0x00000000);
4078 /* XXX : not implemented */
4079 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4080 SPR_NOACCESS, SPR_NOACCESS,
4081 &spr_read_generic, &spr_write_generic,
4082 0x00000000);
4083 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4084 SPR_NOACCESS, SPR_NOACCESS,
4085 &spr_read_generic, &spr_write_generic,
4086 0x00000000);
4087 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4088 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4089 &spr_read_generic, &spr_write_generic,
4090 0x00000000);
f2e63a42 4091#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4092 env->nb_tlb = 64;
4093 env->nb_ways = 1;
4094 env->id_tlbs = 0;
f2e63a42 4095#endif
80d11f44 4096 init_excp_e200(env);
d63001d1
JM		 4097 env->dcache_line_size = 32;
4098 env->icache_line_size = 32;
a750fc0b 4099 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4100}
a750fc0b 4101
a750fc0b
JM		 4102/* Non-embedded PowerPC */
4103/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
05332d70 4104#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | \
1b413d55
JM		 4105 PPC_CACHE | PPC_CACHE_ICBI | \
4106 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
a750fc0b
JM		 4107/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
4108#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4109 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4110 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
12de9a39
JM		 4111 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
4112 PPC_SEGMENT)
a750fc0b
JM		 4113
4114/* POWER : same as 601, without mfmsr, mfsr */
4115#if defined(TODO)
4116#define POWERPC_INSNS_POWER (XXX_TODO)
4117/* POWER RSC (from RAD6000) */
4118#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4119#endif /* TODO */
4120
4121/* PowerPC 601 */
d63001d1 4122#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
12de9a39 4123 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
25ba3a68 4124#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
faadf50e 4125//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4126//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4127#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4128#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
25ba3a68 4129#define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
2f462816 4130#define check_pow_601 check_pow_none
a750fc0b
JM		 4131
4132static void init_proc_601 (CPUPPCState *env)
3fc6c082 4133{
a750fc0b
JM		 4134 gen_spr_ne_601(env);
4135 gen_spr_601(env);
4136 /* Hardware implementation registers */
4137 /* XXX : not implemented */
4138 spr_register(env, SPR_HID0, "HID0",
4139 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4140 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4141 0x80010080);
a750fc0b
JM		 4142 /* XXX : not implemented */
4143 spr_register(env, SPR_HID1, "HID1",
4144 SPR_NOACCESS, SPR_NOACCESS,
4145 &spr_read_generic, &spr_write_generic,
4146 0x00000000);
4147 /* XXX : not implemented */
4148 spr_register(env, SPR_601_HID2, "HID2",
4149 SPR_NOACCESS, SPR_NOACCESS,
4150 &spr_read_generic, &spr_write_generic,
4151 0x00000000);
4152 /* XXX : not implemented */
4153 spr_register(env, SPR_601_HID5, "HID5",
4154 SPR_NOACCESS, SPR_NOACCESS,
4155 &spr_read_generic, &spr_write_generic,
4156 0x00000000);
4157 /* XXX : not implemented */
4158 spr_register(env, SPR_601_HID15, "HID15",
4159 SPR_NOACCESS, SPR_NOACCESS,
4160 &spr_read_generic, &spr_write_generic,
4161 0x00000000);
4162 /* Memory management */
f2e63a42 4163#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4164 env->nb_tlb = 64;
4165 env->nb_ways = 2;
4166 env->id_tlbs = 0;
f2e63a42 4167#endif
e1833e1f 4168 init_excp_601(env);
d63001d1
JM		 4169 env->dcache_line_size = 64;
4170 env->icache_line_size = 64;
faadf50e
JM		 4171 /* Allocate hardware IRQ controller */
4172 ppc6xx_irq_init(env);
3fc6c082
FB		 4173}
4174
a750fc0b
JM		 4175/* PowerPC 602 */
4176#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
4177 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4178 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
d63001d1 4179 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
12de9a39 4180 PPC_SEGMENT | PPC_602_SPEC)
a750fc0b
JM		 4181#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
4182#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4183//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4184#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4185#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68
JM		 4186#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4187 POWERPC_FLAG_BE)
2f462816 4188#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4189
4190static void init_proc_602 (CPUPPCState *env)
3fc6c082 4191{
a750fc0b
JM		 4192 gen_spr_ne_601(env);
4193 gen_spr_602(env);
4194 /* Time base */
4195 gen_tbl(env);
4196 /* hardware implementation registers */
4197 /* XXX : not implemented */
4198 spr_register(env, SPR_HID0, "HID0",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000);
4202 /* XXX : not implemented */
4203 spr_register(env, SPR_HID1, "HID1",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0x00000000);
4207 /* Memory management */
4208 gen_low_BATs(env);
4209 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4210 init_excp_602(env);
d63001d1
JM		 4211 env->dcache_line_size = 32;
4212 env->icache_line_size = 32;
a750fc0b
JM		 4213 /* Allocate hardware IRQ controller */
4214 ppc6xx_irq_init(env);
4215}
3fc6c082 4216
a750fc0b
JM		 4217/* PowerPC 603 */
4218#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
25ba3a68 4219#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4220#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4221//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4222#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4223#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68
JM		 4224#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4225 POWERPC_FLAG_BE)
2f462816 4226#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4227
4228static void init_proc_603 (CPUPPCState *env)
4229{
4230 gen_spr_ne_601(env);
4231 gen_spr_603(env);
4232 /* Time base */
4233 gen_tbl(env);
4234 /* hardware implementation registers */
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_HID0, "HID0",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_generic,
4239 0x00000000);
4240 /* XXX : not implemented */
4241 spr_register(env, SPR_HID1, "HID1",
4242 SPR_NOACCESS, SPR_NOACCESS,
4243 &spr_read_generic, &spr_write_generic,
4244 0x00000000);
4245 /* Memory management */
4246 gen_low_BATs(env);
4247 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4248 init_excp_603(env);
d63001d1
JM		 4249 env->dcache_line_size = 32;
4250 env->icache_line_size = 32;
a750fc0b
JM		 4251 /* Allocate hardware IRQ controller */
4252 ppc6xx_irq_init(env);
3fc6c082
FB		 4253}
4254
a750fc0b
JM		 4255/* PowerPC 603e */
4256#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
4257#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4258#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4259//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4260#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4261#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68
JM		 4262#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4263 POWERPC_FLAG_BE)
2f462816 4264#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4265
4266static void init_proc_603E (CPUPPCState *env)
4267{
4268 gen_spr_ne_601(env);
4269 gen_spr_603(env);
4270 /* Time base */
4271 gen_tbl(env);
4272 /* hardware implementation registers */
4273 /* XXX : not implemented */
4274 spr_register(env, SPR_HID0, "HID0",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* XXX : not implemented */
4279 spr_register(env, SPR_HID1, "HID1",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* XXX : not implemented */
4284 spr_register(env, SPR_IABR, "IABR",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* Memory management */
4289 gen_low_BATs(env);
4290 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4291 init_excp_603(env);
d63001d1
JM		 4292 env->dcache_line_size = 32;
4293 env->icache_line_size = 32;
a750fc0b
JM		 4294 /* Allocate hardware IRQ controller */
4295 ppc6xx_irq_init(env);
4296}
4297
a750fc0b
JM		 4298/* PowerPC 604 */
4299#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
4300#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4301#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4302//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4303#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4304#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68
JM		 4305#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4306 POWERPC_FLAG_PMM)
2f462816 4307#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4308
4309static void init_proc_604 (CPUPPCState *env)
4310{
4311 gen_spr_ne_601(env);
4312 gen_spr_604(env);
4313 /* Time base */
4314 gen_tbl(env);
4315 /* Hardware implementation registers */
4316 /* XXX : not implemented */
4317 spr_register(env, SPR_HID0, "HID0",
4318 SPR_NOACCESS, SPR_NOACCESS,
4319 &spr_read_generic, &spr_write_generic,
4320 0x00000000);
4321 /* XXX : not implemented */
4322 spr_register(env, SPR_HID1, "HID1",
4323 SPR_NOACCESS, SPR_NOACCESS,
4324 &spr_read_generic, &spr_write_generic,
4325 0x00000000);
4326 /* Memory management */
4327 gen_low_BATs(env);
e1833e1f 4328 init_excp_604(env);
d63001d1
JM		 4329 env->dcache_line_size = 32;
4330 env->icache_line_size = 32;
a750fc0b
JM		 4331 /* Allocate hardware IRQ controller */
4332 ppc6xx_irq_init(env);
4333}
4334
4335/* PowerPC 740/750 (aka G3) */
4336#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
25ba3a68 4337#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
a750fc0b
JM		 4338#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
4339//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
4340#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 4341#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
25ba3a68
JM		 4342#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4343 POWERPC_FLAG_PMM)
2f462816 4344#define check_pow_7x0 check_pow_hid0
a750fc0b
JM		 4345
4346static void init_proc_7x0 (CPUPPCState *env)
4347{
4348 gen_spr_ne_601(env);
4349 gen_spr_7xx(env);
4350 /* Time base */
4351 gen_tbl(env);
4352 /* Thermal management */
4353 gen_spr_thrm(env);
4354 /* Hardware implementation registers */
4355 /* XXX : not implemented */
4356 spr_register(env, SPR_HID0, "HID0",
4357 SPR_NOACCESS, SPR_NOACCESS,
4358 &spr_read_generic, &spr_write_generic,
4359 0x00000000);
4360 /* XXX : not implemented */
4361 spr_register(env, SPR_HID1, "HID1",
4362 SPR_NOACCESS, SPR_NOACCESS,
4363 &spr_read_generic, &spr_write_generic,
4364 0x00000000);
4365 /* Memory management */
4366 gen_low_BATs(env);
e1833e1f 4367 init_excp_7x0(env);
d63001d1
JM		 4368 env->dcache_line_size = 32;
4369 env->icache_line_size = 32;
a750fc0b
JM		 4370 /* Allocate hardware IRQ controller */
4371 ppc6xx_irq_init(env);
4372}
4373
4374/* PowerPC 750FX/GX */
4375#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
25ba3a68 4376#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4377#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4378#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4379#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4380#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68
JM		 4381#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4382 POWERPC_FLAG_PMM)
2f462816 4383#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4384
4385static void init_proc_750fx (CPUPPCState *env)
4386{
4387 gen_spr_ne_601(env);
4388 gen_spr_7xx(env);
4389 /* Time base */
4390 gen_tbl(env);
4391 /* Thermal management */
4392 gen_spr_thrm(env);
4393 /* Hardware implementation registers */
4394 /* XXX : not implemented */
4395 spr_register(env, SPR_HID0, "HID0",
4396 SPR_NOACCESS, SPR_NOACCESS,
4397 &spr_read_generic, &spr_write_generic,
4398 0x00000000);
4399 /* XXX : not implemented */
4400 spr_register(env, SPR_HID1, "HID1",
4401 SPR_NOACCESS, SPR_NOACCESS,
4402 &spr_read_generic, &spr_write_generic,
4403 0x00000000);
4404 /* XXX : not implemented */
4405 spr_register(env, SPR_750_HID2, "HID2",
4406 SPR_NOACCESS, SPR_NOACCESS,
4407 &spr_read_generic, &spr_write_generic,
4408 0x00000000);
4409 /* Memory management */
4410 gen_low_BATs(env);
4411 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4412 gen_high_BATs(env);
e1833e1f 4413 init_excp_750FX(env);
d63001d1
JM		 4414 env->dcache_line_size = 32;
4415 env->icache_line_size = 32;
a750fc0b
JM		 4416 /* Allocate hardware IRQ controller */
4417 ppc6xx_irq_init(env);
4418}
4419
4420/* PowerPC 745/755 */
4421#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
25ba3a68 4422#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
a750fc0b
JM		 4423#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
4424//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
4425#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 4426#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
25ba3a68
JM		 4427#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4428 POWERPC_FLAG_PMM)
2f462816 4429#define check_pow_7x5 check_pow_hid0
a750fc0b
JM		 4430
4431static void init_proc_7x5 (CPUPPCState *env)
4432{
4433 gen_spr_ne_601(env);
4434 gen_spr_G2_755(env);
4435 /* Time base */
4436 gen_tbl(env);
4437 /* L2 cache control */
4438 /* XXX : not implemented */
4439 spr_register(env, SPR_ICTC, "ICTC",
4440 SPR_NOACCESS, SPR_NOACCESS,
4441 &spr_read_generic, &spr_write_generic,
4442 0x00000000);
4443 /* XXX : not implemented */
4444 spr_register(env, SPR_L2PMCR, "L2PMCR",
4445 SPR_NOACCESS, SPR_NOACCESS,
4446 &spr_read_generic, &spr_write_generic,
4447 0x00000000);
4448 /* Hardware implementation registers */
4449 /* XXX : not implemented */
4450 spr_register(env, SPR_HID0, "HID0",
4451 SPR_NOACCESS, SPR_NOACCESS,
4452 &spr_read_generic, &spr_write_generic,
4453 0x00000000);
4454 /* XXX : not implemented */
4455 spr_register(env, SPR_HID1, "HID1",
4456 SPR_NOACCESS, SPR_NOACCESS,
4457 &spr_read_generic, &spr_write_generic,
4458 0x00000000);
4459 /* XXX : not implemented */
4460 spr_register(env, SPR_HID2, "HID2",
4461 SPR_NOACCESS, SPR_NOACCESS,
4462 &spr_read_generic, &spr_write_generic,
4463 0x00000000);
4464 /* Memory management */
4465 gen_low_BATs(env);
4466 gen_high_BATs(env);
4467 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 4468 init_excp_7x5(env);
d63001d1
JM		 4469 env->dcache_line_size = 32;
4470 env->icache_line_size = 32;
a750fc0b
JM		 4471 /* Allocate hardware IRQ controller */
4472 ppc6xx_irq_init(env);
d63001d1
JM		 4473#if !defined(CONFIG_USER_ONLY)
4474 /* Hardware reset vector */
4475 env->hreset_vector = 0xFFFFFFFCUL;
4476#endif
a750fc0b
JM		 4477}
4478
4479/* PowerPC 7400 (aka G4) */
4480#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4481 PPC_EXTERN | PPC_MEM_TLBIA | \
4482 PPC_ALTIVEC)
4483#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
4484#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
4485#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
4486#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 4487#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68
JM		 4488#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4489 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4490#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 4491
4492static void init_proc_7400 (CPUPPCState *env)
4493{
4494 gen_spr_ne_601(env);
4495 gen_spr_7xx(env);
4496 /* Time base */
4497 gen_tbl(env);
4498 /* 74xx specific SPR */
4499 gen_spr_74xx(env);
4500 /* Thermal management */
4501 gen_spr_thrm(env);
4502 /* Memory management */
4503 gen_low_BATs(env);
e1833e1f 4504 init_excp_7400(env);
d63001d1
JM		 4505 env->dcache_line_size = 32;
4506 env->icache_line_size = 32;
a750fc0b
JM		 4507 /* Allocate hardware IRQ controller */
4508 ppc6xx_irq_init(env);
4509}
4510
4511/* PowerPC 7410 (aka G4) */
4512#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4513 PPC_EXTERN | PPC_MEM_TLBIA | \
4514 PPC_ALTIVEC)
4515#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
4516#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
4517#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
4518#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 4519#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68
JM		 4520#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4521 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4522#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 4523
4524static void init_proc_7410 (CPUPPCState *env)
4525{
4526 gen_spr_ne_601(env);
4527 gen_spr_7xx(env);
4528 /* Time base */
4529 gen_tbl(env);
4530 /* 74xx specific SPR */
4531 gen_spr_74xx(env);
4532 /* Thermal management */
4533 gen_spr_thrm(env);
4534 /* L2PMCR */
4535 /* XXX : not implemented */
4536 spr_register(env, SPR_L2PMCR, "L2PMCR",
4537 SPR_NOACCESS, SPR_NOACCESS,
4538 &spr_read_generic, &spr_write_generic,
4539 0x00000000);
4540 /* LDSTDB */
4541 /* XXX : not implemented */
4542 spr_register(env, SPR_LDSTDB, "LDSTDB",
4543 SPR_NOACCESS, SPR_NOACCESS,
4544 &spr_read_generic, &spr_write_generic,
4545 0x00000000);
4546 /* Memory management */
4547 gen_low_BATs(env);
e1833e1f 4548 init_excp_7400(env);
d63001d1
JM		 4549 env->dcache_line_size = 32;
4550 env->icache_line_size = 32;
a750fc0b
JM		 4551 /* Allocate hardware IRQ controller */
4552 ppc6xx_irq_init(env);
4553}
4554
4555/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 4556#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4557 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4558 PPC_ALTIVEC)
4559#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
4560#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
4561#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
4562#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 4563#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68
JM		 4564#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4565 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4566#define check_pow_7440 check_pow_hid0
a750fc0b 4567
578bb252 4568__attribute__ (( unused ))
a750fc0b
JM		 4569static void init_proc_7440 (CPUPPCState *env)
4570{
4571 gen_spr_ne_601(env);
4572 gen_spr_7xx(env);
4573 /* Time base */
4574 gen_tbl(env);
4575 /* 74xx specific SPR */
4576 gen_spr_74xx(env);
4577 /* LDSTCR */
4578 /* XXX : not implemented */
4579 spr_register(env, SPR_LDSTCR, "LDSTCR",
4580 SPR_NOACCESS, SPR_NOACCESS,
4581 &spr_read_generic, &spr_write_generic,
4582 0x00000000);
4583 /* ICTRL */
4584 /* XXX : not implemented */
4585 spr_register(env, SPR_ICTRL, "ICTRL",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_generic, &spr_write_generic,
4588 0x00000000);
4589 /* MSSSR0 */
578bb252 4590 /* XXX : not implemented */
a750fc0b
JM		 4591 spr_register(env, SPR_MSSSR0, "MSSSR0",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* PMC */
4596 /* XXX : not implemented */
4597 spr_register(env, SPR_PMC5, "PMC5",
4598 SPR_NOACCESS, SPR_NOACCESS,
4599 &spr_read_generic, &spr_write_generic,
4600 0x00000000);
578bb252 4601 /* XXX : not implemented */
a750fc0b
JM		 4602 spr_register(env, SPR_UPMC5, "UPMC5",
4603 &spr_read_ureg, SPR_NOACCESS,
4604 &spr_read_ureg, SPR_NOACCESS,
4605 0x00000000);
578bb252 4606 /* XXX : not implemented */
a750fc0b
JM		 4607 spr_register(env, SPR_PMC6, "PMC6",
4608 SPR_NOACCESS, SPR_NOACCESS,
4609 &spr_read_generic, &spr_write_generic,
4610 0x00000000);
578bb252 4611 /* XXX : not implemented */
a750fc0b
JM		 4612 spr_register(env, SPR_UPMC6, "UPMC6",
4613 &spr_read_ureg, SPR_NOACCESS,
4614 &spr_read_ureg, SPR_NOACCESS,
4615 0x00000000);
4616 /* Memory management */
4617 gen_low_BATs(env);
578bb252 4618 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 4619 init_excp_7450(env);
d63001d1
JM		 4620 env->dcache_line_size = 32;
4621 env->icache_line_size = 32;
a750fc0b
JM		 4622 /* Allocate hardware IRQ controller */
4623 ppc6xx_irq_init(env);
4624}
a750fc0b
JM		 4625
4626/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 4627#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4628 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4629 PPC_ALTIVEC)
4630#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
4631#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
4632#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
4633#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 4634#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68
JM		 4635#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4636 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4637#define check_pow_7450 check_pow_hid0
a750fc0b 4638
578bb252 4639__attribute__ (( unused ))
a750fc0b
JM		 4640static void init_proc_7450 (CPUPPCState *env)
4641{
4642 gen_spr_ne_601(env);
4643 gen_spr_7xx(env);
4644 /* Time base */
4645 gen_tbl(env);
4646 /* 74xx specific SPR */
4647 gen_spr_74xx(env);
4648 /* Level 3 cache control */
4649 gen_l3_ctrl(env);
4650 /* LDSTCR */
4651 /* XXX : not implemented */
4652 spr_register(env, SPR_LDSTCR, "LDSTCR",
4653 SPR_NOACCESS, SPR_NOACCESS,
4654 &spr_read_generic, &spr_write_generic,
4655 0x00000000);
4656 /* ICTRL */
4657 /* XXX : not implemented */
4658 spr_register(env, SPR_ICTRL, "ICTRL",
4659 SPR_NOACCESS, SPR_NOACCESS,
4660 &spr_read_generic, &spr_write_generic,
4661 0x00000000);
4662 /* MSSSR0 */
578bb252 4663 /* XXX : not implemented */
a750fc0b
JM		 4664 spr_register(env, SPR_MSSSR0, "MSSSR0",
4665 SPR_NOACCESS, SPR_NOACCESS,
4666 &spr_read_generic, &spr_write_generic,
4667 0x00000000);
4668 /* PMC */
4669 /* XXX : not implemented */
4670 spr_register(env, SPR_PMC5, "PMC5",
4671 SPR_NOACCESS, SPR_NOACCESS,
4672 &spr_read_generic, &spr_write_generic,
4673 0x00000000);
578bb252 4674 /* XXX : not implemented */
a750fc0b
JM		 4675 spr_register(env, SPR_UPMC5, "UPMC5",
4676 &spr_read_ureg, SPR_NOACCESS,
4677 &spr_read_ureg, SPR_NOACCESS,
4678 0x00000000);
578bb252 4679 /* XXX : not implemented */
a750fc0b
JM		 4680 spr_register(env, SPR_PMC6, "PMC6",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_generic,
4683 0x00000000);
578bb252 4684 /* XXX : not implemented */
a750fc0b
JM		 4685 spr_register(env, SPR_UPMC6, "UPMC6",
4686 &spr_read_ureg, SPR_NOACCESS,
4687 &spr_read_ureg, SPR_NOACCESS,
4688 0x00000000);
4689 /* Memory management */
4690 gen_low_BATs(env);
578bb252 4691 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4692 init_excp_7450(env);
d63001d1
JM		 4693 env->dcache_line_size = 32;
4694 env->icache_line_size = 32;
a750fc0b
JM		 4695 /* Allocate hardware IRQ controller */
4696 ppc6xx_irq_init(env);
4697}
a750fc0b
JM		 4698
4699/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 4700#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4701 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4702 PPC_ALTIVEC)
4703#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
4704#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
4705#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
4706#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 4707#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68
JM		 4708#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4709 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4710#define check_pow_7445 check_pow_hid0
a750fc0b 4711
578bb252 4712__attribute__ (( unused ))
a750fc0b
JM		 4713static void init_proc_7445 (CPUPPCState *env)
4714{
4715 gen_spr_ne_601(env);
4716 gen_spr_7xx(env);
4717 /* Time base */
4718 gen_tbl(env);
4719 /* 74xx specific SPR */
4720 gen_spr_74xx(env);
4721 /* LDSTCR */
4722 /* XXX : not implemented */
4723 spr_register(env, SPR_LDSTCR, "LDSTCR",
4724 SPR_NOACCESS, SPR_NOACCESS,
4725 &spr_read_generic, &spr_write_generic,
4726 0x00000000);
4727 /* ICTRL */
4728 /* XXX : not implemented */
4729 spr_register(env, SPR_ICTRL, "ICTRL",
4730 SPR_NOACCESS, SPR_NOACCESS,
4731 &spr_read_generic, &spr_write_generic,
4732 0x00000000);
4733 /* MSSSR0 */
578bb252 4734 /* XXX : not implemented */
a750fc0b
JM		 4735 spr_register(env, SPR_MSSSR0, "MSSSR0",
4736 SPR_NOACCESS, SPR_NOACCESS,
4737 &spr_read_generic, &spr_write_generic,
4738 0x00000000);
4739 /* PMC */
4740 /* XXX : not implemented */
4741 spr_register(env, SPR_PMC5, "PMC5",
4742 SPR_NOACCESS, SPR_NOACCESS,
4743 &spr_read_generic, &spr_write_generic,
4744 0x00000000);
578bb252 4745 /* XXX : not implemented */
a750fc0b
JM		 4746 spr_register(env, SPR_UPMC5, "UPMC5",
4747 &spr_read_ureg, SPR_NOACCESS,
4748 &spr_read_ureg, SPR_NOACCESS,
4749 0x00000000);
578bb252 4750 /* XXX : not implemented */
a750fc0b
JM		 4751 spr_register(env, SPR_PMC6, "PMC6",
4752 SPR_NOACCESS, SPR_NOACCESS,
4753 &spr_read_generic, &spr_write_generic,
4754 0x00000000);
578bb252 4755 /* XXX : not implemented */
a750fc0b
JM		 4756 spr_register(env, SPR_UPMC6, "UPMC6",
4757 &spr_read_ureg, SPR_NOACCESS,
4758 &spr_read_ureg, SPR_NOACCESS,
4759 0x00000000);
4760 /* SPRGs */
4761 spr_register(env, SPR_SPRG4, "SPRG4",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 spr_register(env, SPR_USPRG4, "USPRG4",
4766 &spr_read_ureg, SPR_NOACCESS,
4767 &spr_read_ureg, SPR_NOACCESS,
4768 0x00000000);
4769 spr_register(env, SPR_SPRG5, "SPRG5",
4770 SPR_NOACCESS, SPR_NOACCESS,
4771 &spr_read_generic, &spr_write_generic,
4772 0x00000000);
4773 spr_register(env, SPR_USPRG5, "USPRG5",
4774 &spr_read_ureg, SPR_NOACCESS,
4775 &spr_read_ureg, SPR_NOACCESS,
4776 0x00000000);
4777 spr_register(env, SPR_SPRG6, "SPRG6",
4778 SPR_NOACCESS, SPR_NOACCESS,
4779 &spr_read_generic, &spr_write_generic,
4780 0x00000000);
4781 spr_register(env, SPR_USPRG6, "USPRG6",
4782 &spr_read_ureg, SPR_NOACCESS,
4783 &spr_read_ureg, SPR_NOACCESS,
4784 0x00000000);
4785 spr_register(env, SPR_SPRG7, "SPRG7",
4786 SPR_NOACCESS, SPR_NOACCESS,
4787 &spr_read_generic, &spr_write_generic,
4788 0x00000000);
4789 spr_register(env, SPR_USPRG7, "USPRG7",
4790 &spr_read_ureg, SPR_NOACCESS,
4791 &spr_read_ureg, SPR_NOACCESS,
4792 0x00000000);
4793 /* Memory management */
4794 gen_low_BATs(env);
4795 gen_high_BATs(env);
578bb252 4796 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4797 init_excp_7450(env);
d63001d1
JM		 4798 env->dcache_line_size = 32;
4799 env->icache_line_size = 32;
a750fc0b
JM		 4800 /* Allocate hardware IRQ controller */
4801 ppc6xx_irq_init(env);
4802}
a750fc0b
JM		 4803
4804/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 4805#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4806 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4807 PPC_ALTIVEC)
4808#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4809#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4810#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4811#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 4812#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68
JM		 4813#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4814 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4815#define check_pow_7455 check_pow_hid0
a750fc0b 4816
578bb252 4817__attribute__ (( unused ))
a750fc0b
JM		 4818static void init_proc_7455 (CPUPPCState *env)
4819{
4820 gen_spr_ne_601(env);
4821 gen_spr_7xx(env);
4822 /* Time base */
4823 gen_tbl(env);
4824 /* 74xx specific SPR */
4825 gen_spr_74xx(env);
4826 /* Level 3 cache control */
4827 gen_l3_ctrl(env);
4828 /* LDSTCR */
4829 /* XXX : not implemented */
4830 spr_register(env, SPR_LDSTCR, "LDSTCR",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* ICTRL */
4835 /* XXX : not implemented */
4836 spr_register(env, SPR_ICTRL, "ICTRL",
4837 SPR_NOACCESS, SPR_NOACCESS,
4838 &spr_read_generic, &spr_write_generic,
4839 0x00000000);
4840 /* MSSSR0 */
578bb252 4841 /* XXX : not implemented */
a750fc0b
JM		 4842 spr_register(env, SPR_MSSSR0, "MSSSR0",
4843 SPR_NOACCESS, SPR_NOACCESS,
4844 &spr_read_generic, &spr_write_generic,
4845 0x00000000);
4846 /* PMC */
4847 /* XXX : not implemented */
4848 spr_register(env, SPR_PMC5, "PMC5",
4849 SPR_NOACCESS, SPR_NOACCESS,
4850 &spr_read_generic, &spr_write_generic,
4851 0x00000000);
578bb252 4852 /* XXX : not implemented */
a750fc0b
JM		 4853 spr_register(env, SPR_UPMC5, "UPMC5",
4854 &spr_read_ureg, SPR_NOACCESS,
4855 &spr_read_ureg, SPR_NOACCESS,
4856 0x00000000);
578bb252 4857 /* XXX : not implemented */
a750fc0b
JM		 4858 spr_register(env, SPR_PMC6, "PMC6",
4859 SPR_NOACCESS, SPR_NOACCESS,
4860 &spr_read_generic, &spr_write_generic,
4861 0x00000000);
578bb252 4862 /* XXX : not implemented */
a750fc0b
JM		 4863 spr_register(env, SPR_UPMC6, "UPMC6",
4864 &spr_read_ureg, SPR_NOACCESS,
4865 &spr_read_ureg, SPR_NOACCESS,
4866 0x00000000);
4867 /* SPRGs */
4868 spr_register(env, SPR_SPRG4, "SPRG4",
4869 SPR_NOACCESS, SPR_NOACCESS,
4870 &spr_read_generic, &spr_write_generic,
4871 0x00000000);
4872 spr_register(env, SPR_USPRG4, "USPRG4",
4873 &spr_read_ureg, SPR_NOACCESS,
4874 &spr_read_ureg, SPR_NOACCESS,
4875 0x00000000);
4876 spr_register(env, SPR_SPRG5, "SPRG5",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 spr_register(env, SPR_USPRG5, "USPRG5",
4881 &spr_read_ureg, SPR_NOACCESS,
4882 &spr_read_ureg, SPR_NOACCESS,
4883 0x00000000);
4884 spr_register(env, SPR_SPRG6, "SPRG6",
4885 SPR_NOACCESS, SPR_NOACCESS,
4886 &spr_read_generic, &spr_write_generic,
4887 0x00000000);
4888 spr_register(env, SPR_USPRG6, "USPRG6",
4889 &spr_read_ureg, SPR_NOACCESS,
4890 &spr_read_ureg, SPR_NOACCESS,
4891 0x00000000);
4892 spr_register(env, SPR_SPRG7, "SPRG7",
4893 SPR_NOACCESS, SPR_NOACCESS,
4894 &spr_read_generic, &spr_write_generic,
4895 0x00000000);
4896 spr_register(env, SPR_USPRG7, "USPRG7",
4897 &spr_read_ureg, SPR_NOACCESS,
4898 &spr_read_ureg, SPR_NOACCESS,
4899 0x00000000);
4900 /* Memory management */
4901 gen_low_BATs(env);
4902 gen_high_BATs(env);
578bb252 4903 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4904 init_excp_7450(env);
d63001d1
JM		 4905 env->dcache_line_size = 32;
4906 env->icache_line_size = 32;
a750fc0b
JM		 4907 /* Allocate hardware IRQ controller */
4908 ppc6xx_irq_init(env);
4909}
a750fc0b
JM		 4910
4911#if defined (TARGET_PPC64)
d63001d1 4912#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
12de9a39
JM		 4913 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4914 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4915 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
a750fc0b 4916/* PowerPC 970 */
d63001d1 4917#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4918 PPC_64B | PPC_ALTIVEC | \
12de9a39 4919 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4920#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 4921#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 4922//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4923#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 4924#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68
JM		 4925#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4926 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 4927
417bf010
JM		 4928#if defined(CONFIG_USER_ONLY)
4929#define POWERPC970_HID5_INIT 0x00000080
4930#else
4931#define POWERPC970_HID5_INIT 0x00000000
4932#endif
4933
2f462816
JM		 4934static int check_pow_970 (CPUPPCState *env)
4935{
4936 if (env->spr[SPR_HID0] & 0x00600000)
4937 return 1;
4938
4939 return 0;
4940}
4941
a750fc0b
JM		 4942static void init_proc_970 (CPUPPCState *env)
4943{
4944 gen_spr_ne_601(env);
4945 gen_spr_7xx(env);
4946 /* Time base */
4947 gen_tbl(env);
4948 /* Hardware implementation registers */
4949 /* XXX : not implemented */
4950 spr_register(env, SPR_HID0, "HID0",
4951 SPR_NOACCESS, SPR_NOACCESS,
06403421 4952 &spr_read_generic, &spr_write_clear,
d63001d1 4953 0x60000000);
a750fc0b
JM		 4954 /* XXX : not implemented */
4955 spr_register(env, SPR_HID1, "HID1",
4956 SPR_NOACCESS, SPR_NOACCESS,
4957 &spr_read_generic, &spr_write_generic,
4958 0x00000000);
4959 /* XXX : not implemented */
4960 spr_register(env, SPR_750_HID2, "HID2",
4961 SPR_NOACCESS, SPR_NOACCESS,
4962 &spr_read_generic, &spr_write_generic,
4963 0x00000000);
e57448f1
JM		 4964 /* XXX : not implemented */
4965 spr_register(env, SPR_970_HID5, "HID5",
4966 SPR_NOACCESS, SPR_NOACCESS,
4967 &spr_read_generic, &spr_write_generic,
417bf010 4968 POWERPC970_HID5_INIT);
a750fc0b
JM		 4969 /* Memory management */
4970 /* XXX: not correct */
4971 gen_low_BATs(env);
12de9a39
JM		 4972 /* XXX : not implemented */
4973 spr_register(env, SPR_MMUCFG, "MMUCFG",
4974 SPR_NOACCESS, SPR_NOACCESS,
4975 &spr_read_generic, SPR_NOACCESS,
4976 0x00000000); /* TOFIX */
4977 /* XXX : not implemented */
4978 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4979 SPR_NOACCESS, SPR_NOACCESS,
4980 &spr_read_generic, &spr_write_generic,
4981 0x00000000); /* TOFIX */
4982 spr_register(env, SPR_HIOR, "SPR_HIOR",
4983 SPR_NOACCESS, SPR_NOACCESS,
4984 &spr_read_generic, &spr_write_generic,
4985 0xFFF00000); /* XXX: This is a hack */
f2e63a42 4986#if !defined(CONFIG_USER_ONLY)
12de9a39 4987 env->slb_nr = 32;
f2e63a42 4988#endif
e1833e1f 4989 init_excp_970(env);
d63001d1
JM		 4990 env->dcache_line_size = 128;
4991 env->icache_line_size = 128;
a750fc0b
JM		 4992 /* Allocate hardware IRQ controller */
4993 ppc970_irq_init(env);
4994}
a750fc0b
JM		 4995
4996/* PowerPC 970FX (aka G5) */
d63001d1 4997#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4998 PPC_64B | PPC_ALTIVEC | \
12de9a39 4999 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5000#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 5001#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 5002#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5003#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 5004#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68
JM		 5005#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5006 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 5007
2f462816
JM		 5008static int check_pow_970FX (CPUPPCState *env)
5009{
5010 if (env->spr[SPR_HID0] & 0x00600000)
5011 return 1;
5012
5013 return 0;
5014}
5015
a750fc0b
JM		 5016static void init_proc_970FX (CPUPPCState *env)
5017{
5018 gen_spr_ne_601(env);
5019 gen_spr_7xx(env);
5020 /* Time base */
5021 gen_tbl(env);
5022 /* Hardware implementation registers */
5023 /* XXX : not implemented */
5024 spr_register(env, SPR_HID0, "HID0",
5025 SPR_NOACCESS, SPR_NOACCESS,
06403421 5026 &spr_read_generic, &spr_write_clear,
d63001d1 5027 0x60000000);
a750fc0b
JM		 5028 /* XXX : not implemented */
5029 spr_register(env, SPR_HID1, "HID1",
5030 SPR_NOACCESS, SPR_NOACCESS,
5031 &spr_read_generic, &spr_write_generic,
5032 0x00000000);
5033 /* XXX : not implemented */
5034 spr_register(env, SPR_750_HID2, "HID2",
5035 SPR_NOACCESS, SPR_NOACCESS,
5036 &spr_read_generic, &spr_write_generic,
5037 0x00000000);
d63001d1
JM		 5038 /* XXX : not implemented */
5039 spr_register(env, SPR_970_HID5, "HID5",
5040 SPR_NOACCESS, SPR_NOACCESS,
5041 &spr_read_generic, &spr_write_generic,
417bf010 5042 POWERPC970_HID5_INIT);
a750fc0b
JM		 5043 /* Memory management */
5044 /* XXX: not correct */
5045 gen_low_BATs(env);
12de9a39
JM		 5046 /* XXX : not implemented */
5047 spr_register(env, SPR_MMUCFG, "MMUCFG",
5048 SPR_NOACCESS, SPR_NOACCESS,
5049 &spr_read_generic, SPR_NOACCESS,
5050 0x00000000); /* TOFIX */
5051 /* XXX : not implemented */
5052 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5053 SPR_NOACCESS, SPR_NOACCESS,
5054 &spr_read_generic, &spr_write_generic,
5055 0x00000000); /* TOFIX */
5056 spr_register(env, SPR_HIOR, "SPR_HIOR",
5057 SPR_NOACCESS, SPR_NOACCESS,
5058 &spr_read_generic, &spr_write_generic,
5059 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5060#if !defined(CONFIG_USER_ONLY)
12de9a39 5061 env->slb_nr = 32;
f2e63a42 5062#endif
e1833e1f 5063 init_excp_970(env);
d63001d1
JM		 5064 env->dcache_line_size = 128;
5065 env->icache_line_size = 128;
a750fc0b
JM		 5066 /* Allocate hardware IRQ controller */
5067 ppc970_irq_init(env);
5068}
a750fc0b
JM		 5069
5070/* PowerPC 970 GX */
d63001d1 5071#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 5072 PPC_64B | PPC_ALTIVEC | \
12de9a39 5073 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5074#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 5075#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 5076#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
5077#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 5078#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68
JM		 5079#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5080 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 5081
2f462816
JM		 5082static int check_pow_970GX (CPUPPCState *env)
5083{
5084 if (env->spr[SPR_HID0] & 0x00600000)
5085 return 1;
5086
5087 return 0;
5088}
5089
a750fc0b
JM		 5090static void init_proc_970GX (CPUPPCState *env)
5091{
5092 gen_spr_ne_601(env);
5093 gen_spr_7xx(env);
5094 /* Time base */
5095 gen_tbl(env);
5096 /* Hardware implementation registers */
5097 /* XXX : not implemented */
5098 spr_register(env, SPR_HID0, "HID0",
5099 SPR_NOACCESS, SPR_NOACCESS,
06403421 5100 &spr_read_generic, &spr_write_clear,
d63001d1 5101 0x60000000);
a750fc0b
JM		 5102 /* XXX : not implemented */
5103 spr_register(env, SPR_HID1, "HID1",
5104 SPR_NOACCESS, SPR_NOACCESS,
5105 &spr_read_generic, &spr_write_generic,
5106 0x00000000);
5107 /* XXX : not implemented */
5108 spr_register(env, SPR_750_HID2, "HID2",
5109 SPR_NOACCESS, SPR_NOACCESS,
5110 &spr_read_generic, &spr_write_generic,
5111 0x00000000);
d63001d1
JM		 5112 /* XXX : not implemented */
5113 spr_register(env, SPR_970_HID5, "HID5",
5114 SPR_NOACCESS, SPR_NOACCESS,
5115 &spr_read_generic, &spr_write_generic,
417bf010 5116 POWERPC970_HID5_INIT);
a750fc0b
JM		 5117 /* Memory management */
5118 /* XXX: not correct */
5119 gen_low_BATs(env);
12de9a39
JM		 5120 /* XXX : not implemented */
5121 spr_register(env, SPR_MMUCFG, "MMUCFG",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, SPR_NOACCESS,
5124 0x00000000); /* TOFIX */
5125 /* XXX : not implemented */
5126 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 &spr_read_generic, &spr_write_generic,
5129 0x00000000); /* TOFIX */
5130 spr_register(env, SPR_HIOR, "SPR_HIOR",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, &spr_write_generic,
5133 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5134#if !defined(CONFIG_USER_ONLY)
12de9a39 5135 env->slb_nr = 32;
f2e63a42 5136#endif
e1833e1f 5137 init_excp_970(env);
d63001d1
JM		 5138 env->dcache_line_size = 128;
5139 env->icache_line_size = 128;
a750fc0b
JM		 5140 /* Allocate hardware IRQ controller */
5141 ppc970_irq_init(env);
5142}
a750fc0b 5143
2f462816
JM		 5144/* PowerPC 970 MP */
5145#define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
5146 PPC_64B | PPC_ALTIVEC | \
5147 PPC_SEGMENT_64B | PPC_SLBI)
5148#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
5149#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
5150#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
5151#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
5152#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
5153#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5154 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
5155
5156static int check_pow_970MP (CPUPPCState *env)
5157{
5158 if (env->spr[SPR_HID0] & 0x01C00000)
5159 return 1;
5160
5161 return 0;
5162}
5163
5164static void init_proc_970MP (CPUPPCState *env)
5165{
5166 gen_spr_ne_601(env);
5167 gen_spr_7xx(env);
5168 /* Time base */
5169 gen_tbl(env);
5170 /* Hardware implementation registers */
5171 /* XXX : not implemented */
5172 spr_register(env, SPR_HID0, "HID0",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_generic, &spr_write_clear,
5175 0x60000000);
5176 /* XXX : not implemented */
5177 spr_register(env, SPR_HID1, "HID1",
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 &spr_read_generic, &spr_write_generic,
5180 0x00000000);
5181 /* XXX : not implemented */
5182 spr_register(env, SPR_750_HID2, "HID2",
5183 SPR_NOACCESS, SPR_NOACCESS,
5184 &spr_read_generic, &spr_write_generic,
5185 0x00000000);
5186 /* XXX : not implemented */
5187 spr_register(env, SPR_970_HID5, "HID5",
5188 SPR_NOACCESS, SPR_NOACCESS,
5189 &spr_read_generic, &spr_write_generic,
5190 POWERPC970_HID5_INIT);
5191 /* Memory management */
5192 /* XXX: not correct */
5193 gen_low_BATs(env);
5194 /* XXX : not implemented */
5195 spr_register(env, SPR_MMUCFG, "MMUCFG",
5196 SPR_NOACCESS, SPR_NOACCESS,
5197 &spr_read_generic, SPR_NOACCESS,
5198 0x00000000); /* TOFIX */
5199 /* XXX : not implemented */
5200 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5201 SPR_NOACCESS, SPR_NOACCESS,
5202 &spr_read_generic, &spr_write_generic,
5203 0x00000000); /* TOFIX */
5204 spr_register(env, SPR_HIOR, "SPR_HIOR",
5205 SPR_NOACCESS, SPR_NOACCESS,
5206 &spr_read_generic, &spr_write_generic,
5207 0xFFF00000); /* XXX: This is a hack */
2f462816
JM		 5208#if !defined(CONFIG_USER_ONLY)
5209 env->slb_nr = 32;
5210#endif
5211 init_excp_970(env);
5212 env->dcache_line_size = 128;
5213 env->icache_line_size = 128;
5214 /* Allocate hardware IRQ controller */
5215 ppc970_irq_init(env);
5216}
5217
a750fc0b 5218/* PowerPC 620 */
a750fc0b
JM		 5219#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
5220 PPC_64B | PPC_SLBI)
5221#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
5222#define POWERPC_MMU_620 (POWERPC_MMU_64B)
5223#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 5224#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 5225#define POWERPC_BFDM_620 (bfd_mach_ppc64)
25ba3a68 5226#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
2f462816 5227#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 5228
578bb252 5229__attribute__ (( unused ))
a750fc0b
JM		 5230static void init_proc_620 (CPUPPCState *env)
5231{
5232 gen_spr_ne_601(env);
5233 gen_spr_620(env);
5234 /* Time base */
5235 gen_tbl(env);
5236 /* Hardware implementation registers */
5237 /* XXX : not implemented */
5238 spr_register(env, SPR_HID0, "HID0",
5239 SPR_NOACCESS, SPR_NOACCESS,
5240 &spr_read_generic, &spr_write_generic,
5241 0x00000000);
5242 /* Memory management */
5243 gen_low_BATs(env);
5244 gen_high_BATs(env);
e1833e1f 5245 init_excp_620(env);
d63001d1
JM		 5246 env->dcache_line_size = 64;
5247 env->icache_line_size = 64;
faadf50e
JM		 5248 /* Allocate hardware IRQ controller */
5249 ppc6xx_irq_init(env);
a750fc0b 5250}
a750fc0b
JM		 5251#endif /* defined (TARGET_PPC64) */
5252
5253/* Default 32 bits PowerPC target will be 604 */
5254#define CPU_POWERPC_PPC32 CPU_POWERPC_604
5255#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
5256#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
5257#define POWERPC_MMU_PPC32 POWERPC_MMU_604
5258#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
5259#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 5260#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 5261#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 5262#define check_pow_PPC32 check_pow_604
5263#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 5264
5265/* Default 64 bits PowerPC target will be 970 FX */
5266#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
5267#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
5268#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
5269#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
5270#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
5271#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 5272#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 5273#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 5274#define check_pow_PPC64 check_pow_970FX
5275#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 5276
5277/* Default PowerPC target will be PowerPC 32 */
5278#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 5279#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
5280#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
5281#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
5282#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
5283#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
5284#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 5285#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 5286#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 5287#define check_pow_DEFAULT check_pow_PPC64
5288#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 5289#else
d12f4c38
JM		 5290#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
5291#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
5292#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
5293#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
5294#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
5295#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 5296#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 5297#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 5298#define check_pow_DEFAULT check_pow_PPC32
5299#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 5300#endif
5301
5302/*****************************************************************************/
5303/* PVR definitions for most known PowerPC */
5304enum {
5305 /* PowerPC 401 family */
5306 /* Generic PowerPC 401 */
80d11f44 5307#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 5308 /* PowerPC 401 cores */
80d11f44
JM		 5309 CPU_POWERPC_401A1 = 0x00210000,
5310 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 5311#if 0
80d11f44 5312 CPU_POWERPC_401B3 = xxx,
a750fc0b 5313#endif
80d11f44
JM		 5314 CPU_POWERPC_401C2 = 0x00230000,
5315 CPU_POWERPC_401D2 = 0x00240000,
5316 CPU_POWERPC_401E2 = 0x00250000,
5317 CPU_POWERPC_401F2 = 0x00260000,
5318 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 5319 /* PowerPC 401 microcontrolers */
5320#if 0
80d11f44 5321 CPU_POWERPC_401GF = xxx,
a750fc0b 5322#endif
80d11f44 5323#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 5324 /* IBM Processor for Network Resources */
80d11f44 5325 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 5326#if 0
80d11f44 5327 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 5328#endif
5329 /* PowerPC 403 family */
5330 /* Generic PowerPC 403 */
80d11f44 5331#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 5332 /* PowerPC 403 microcontrollers */
80d11f44
JM		 5333 CPU_POWERPC_403GA = 0x00200011,
5334 CPU_POWERPC_403GB = 0x00200100,
5335 CPU_POWERPC_403GC = 0x00200200,
5336 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 5337#if 0
80d11f44 5338 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 5339#endif
5340 /* PowerPC 405 family */
5341 /* Generic PowerPC 405 */
80d11f44 5342#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 5343 /* PowerPC 405 cores */
5344#if 0
80d11f44 5345 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 5346#endif
5347#if 0
80d11f44 5348 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 5349#endif
5350#if 0
80d11f44 5351 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 5352#endif
5353#if 0
80d11f44 5354 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 5355#endif
5356#if 0
80d11f44 5357 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 5358#endif
5359#if 0
80d11f44 5360 CPU_POWERPC_405C4 = xxx,
a750fc0b 5361#endif
80d11f44 5362 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 5363#if 0
80d11f44 5364 CPU_POWERPC_405D3 = xxx,
a750fc0b 5365#endif
80d11f44 5366 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 5367#if 0
80d11f44 5368 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 5369#endif
5370#if 0
80d11f44 5371 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 5372#endif
5373#if 0
80d11f44 5374 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 5375#endif
5376#if 0
80d11f44 5377 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 5378#endif
5379#if 0
80d11f44 5380 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 5381#endif
5382 /* PowerPC 405 microcontrolers */
5383 /* XXX: missing 0x200108a0 */
80d11f44
JM		 5384#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
5385 CPU_POWERPC_405CRa = 0x40110041,
5386 CPU_POWERPC_405CRb = 0x401100C5,
5387 CPU_POWERPC_405CRc = 0x40110145,
5388 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 5389#if 0
80d11f44 5390 CPU_POWERPC_405EXr = xxx,
a750fc0b 5391#endif
80d11f44 5392 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 5393#if 0
80d11f44
JM		 5394 CPU_POWERPC_405FX = xxx,
5395#endif
5396#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
5397 CPU_POWERPC_405GPa = 0x40110000,
5398 CPU_POWERPC_405GPb = 0x40110040,
5399 CPU_POWERPC_405GPc = 0x40110082,
5400 CPU_POWERPC_405GPd = 0x401100C4,
5401#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
5402 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 5403#if 0
80d11f44 5404 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 5405#endif
5406#if 0
80d11f44 5407 CPU_POWERPC_405L = xxx,
a750fc0b 5408#endif
80d11f44 5409 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 5410#if 0
80d11f44 5411 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 5412#endif
5413#if 0
80d11f44 5414 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 5415#endif
5416#if 0
80d11f44 5417 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 5418#endif
5419 /* IBM network processors */
80d11f44
JM		 5420 CPU_POWERPC_NPE405H = 0x414100C0,
5421 CPU_POWERPC_NPE405H2 = 0x41410140,
5422 CPU_POWERPC_NPE405L = 0x416100C0,
5423 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 5424#if 0
80d11f44 5425 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 5426#endif
5427#if 0
80d11f44 5428 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 5429#endif
5430#if 0
80d11f44 5431 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 5432#endif
5433 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
5434#if 0
80d11f44 5435 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 5436#endif
5437#if 0
80d11f44 5438 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 5439#endif
5440#if 0
80d11f44 5441 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 5442#endif
80d11f44 5443 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 5444#if 0
80d11f44 5445 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 5446#endif
5447#if 0
80d11f44 5448 CPU_POWERPC_STB045 = xxx,
a750fc0b 5449#endif
80d11f44
JM		 5450 CPU_POWERPC_STB04 = 0x41810000,
5451 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 5452#if 0
80d11f44 5453 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 5454#endif
5455 /* Xilinx cores */
80d11f44
JM		 5456 CPU_POWERPC_X2VP4 = 0x20010820,
5457#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
5458 CPU_POWERPC_X2VP20 = 0x20010860,
5459#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 5460#if 0
80d11f44 5461 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 5462#endif
5463#if 0
80d11f44 5464 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 5465#endif
5466#if 0
80d11f44 5467 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 5468#endif
5469#if 0
80d11f44 5470 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 5471#endif
5472 /* PowerPC 440 family */
5473 /* Generic PowerPC 440 */
80d11f44 5474#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 5475 /* PowerPC 440 cores */
5476#if 0
80d11f44 5477 CPU_POWERPC_440A4 = xxx,
a750fc0b
JM		 5478#endif
5479#if 0
80d11f44 5480 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 5481#endif
5482#if 0
80d11f44 5483 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 5484#endif
5485#if 0
80d11f44 5486 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 5487#endif
5488#if 0
80d11f44 5489 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 5490#endif
5491#if 0
80d11f44 5492 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 5493#endif
5494#if 0
80d11f44 5495 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 5496#endif
5497 /* PowerPC 440 microcontrolers */
80d11f44
JM		 5498#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
5499 CPU_POWERPC_440EPa = 0x42221850,
5500 CPU_POWERPC_440EPb = 0x422218D3,
5501#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
5502 CPU_POWERPC_440GPb = 0x40120440,
5503 CPU_POWERPC_440GPc = 0x40120481,
5504#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
5505#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
5506 CPU_POWERPC_440GRX = 0x200008D0,
5507#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
5508#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
5509 CPU_POWERPC_440GXa = 0x51B21850,
5510 CPU_POWERPC_440GXb = 0x51B21851,
5511 CPU_POWERPC_440GXc = 0x51B21892,
5512 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 5513#if 0
80d11f44 5514 CPU_POWERPC_440S = xxx,
a750fc0b 5515#endif
80d11f44
JM		 5516 CPU_POWERPC_440SP = 0x53221850,
5517 CPU_POWERPC_440SP2 = 0x53221891,
5518 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 5519 /* PowerPC 460 family */
5520#if 0
5521 /* Generic PowerPC 464 */
80d11f44 5522#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 5523#endif
5524 /* PowerPC 464 microcontrolers */
5525#if 0
80d11f44 5526 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 5527#endif
5528#if 0
80d11f44 5529 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 5530#endif
5531 /* Freescale embedded PowerPC cores */
c3e36823 5532 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 5533 CPU_POWERPC_MPC5xx = 0x00020020,
5534#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
5535#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
5536#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
5537#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
5538#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
5539#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
5540#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
5541#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
5542#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
5543#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
5544#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
5545#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
5546#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 5547 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 5548 CPU_POWERPC_MPC8xx = 0x00500000,
5549#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
5550#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
5551#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
5552#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
5553#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
5554#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
5555#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
5556#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
5557#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
5558#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
5559#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
5560#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
5561#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
5562#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
5563#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 5564 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 5565 CPU_POWERPC_G2 = 0x00810011,
5566 CPU_POWERPC_G2H4 = 0x80811010,
5567 CPU_POWERPC_G2gp = 0x80821010,
5568 CPU_POWERPC_G2ls = 0x90810010,
5569 CPU_POWERPC_MPC603 = 0x00810100,
5570 CPU_POWERPC_G2_HIP3 = 0x00810101,
5571 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 5572 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 5573 CPU_POWERPC_G2LE = 0x80820010,
5574 CPU_POWERPC_G2LEgp = 0x80822010,
5575 CPU_POWERPC_G2LEls = 0xA0822010,
5576 CPU_POWERPC_G2LEgp1 = 0x80822011,
5577 CPU_POWERPC_G2LEgp3 = 0x80822013,
5578 /* MPC52xx microcontrollers */
c3e36823 5579 /* XXX: MPC 5121 ? */
80d11f44
JM		 5580#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
5581#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
5582#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
5583#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
5584#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
5585#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
5586#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
5587#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
5588 /* MPC82xx microcontrollers */
5589#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
5590#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
5591#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
5592#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
5593#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
5594#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
5595#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
5596#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
5597#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
5598#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
5599#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
5600#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
5601#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
5602#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
5603#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
5604#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
5605#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
5606#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
5607#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
5608#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
5609#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
5610#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
5611#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
5612#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
5613#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
5614#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
5615#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
5616#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
5617#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 5618 /* e200 family */
80d11f44
JM		 5619 /* e200 cores */
5620#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 5621#if 0
80d11f44 5622 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 5623#endif
5624#if 0
80d11f44 5625 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 5626#endif
5627#if 0 /* ? */
80d11f44
JM		 5628 CPU_POWERPC_e200z3 = 0x81120000,
5629#endif
5630 CPU_POWERPC_e200z5 = 0x81000000,
5631 CPU_POWERPC_e200z6 = 0x81120000,
5632 /* MPC55xx microcontrollers */
5633#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
5634#if 0
5635#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
5636#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
5637#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
5638#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
5639#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
5640#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
5641#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
5642#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
5643#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
5644#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
5645#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
5646#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
5647#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
5648#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
5649#endif
5650#if 0
5651#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
5652#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
5653#endif
5654#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
5655#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
5656#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
5657#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
5658#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
5659#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 5660 /* e300 family */
80d11f44
JM		 5661 /* e300 cores */
5662#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
5663 CPU_POWERPC_e300c1 = 0x00830010,
5664 CPU_POWERPC_e300c2 = 0x00840010,
5665 CPU_POWERPC_e300c3 = 0x00850010,
5666 CPU_POWERPC_e300c4 = 0x00860010,
5667 /* MPC83xx microcontrollers */
5668#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
5669#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
5670#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
5671#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
5672#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
5673#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
5674#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
5675#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
5676#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
5677#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
5678#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
5679#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
5680#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
5681#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
5682#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
5683#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
5684#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
5685#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
5686#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
5687#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
5688#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
5689#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
5690#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
5691#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
5692#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
5693#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
5694#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
5695#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
5696#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
5697#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
a750fc0b 5698 /* e500 family */
80d11f44
JM		 5699 /* e500 cores */
5700#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
5701#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
5702 CPU_POWERPC_e500_v10 = 0x80200010,
5703 CPU_POWERPC_e500_v20 = 0x80200020,
5704 CPU_POWERPC_e500v2_v10 = 0x80210010,
5705 CPU_POWERPC_e500v2_v11 = 0x80210011,
5706 CPU_POWERPC_e500v2_v20 = 0x80210020,
5707 CPU_POWERPC_e500v2_v21 = 0x80210021,
5708 CPU_POWERPC_e500v2_v22 = 0x80210022,
5709 CPU_POWERPC_e500v2_v30 = 0x80210030,
5710 /* MPC85xx microcontrollers */
5711#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
5712#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
5713#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
5714#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
5715#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
5716#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
5717#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
5718#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
5719#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
5720#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
5721#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
5722#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
5723#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
5724#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
5725#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
5726#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
5727#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
5728#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
5729#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
5730#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
5731#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
5732#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
5733#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
5734#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
5735#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
5736#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
5737#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
5738#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
5739#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
5740#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
5741#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
5742#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
5743#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
5744#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
5745#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
5746#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
5747#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
5748#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
5749#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
5750#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
5751#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
5752#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
5753#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
5754#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
5755#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
5756#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
5757#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
5758#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
5759#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
5760#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
5761#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
5762#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
5763#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
5764#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
5765#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
5766#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
5767#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
5768#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
5769#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
5770#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
5771#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
5772#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
5773#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
5774#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
5775#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
5776#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
5777#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
5778#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
5779#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
5780#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 5781 /* e600 family */
80d11f44
JM		 5782 /* e600 cores */
5783 CPU_POWERPC_e600 = 0x80040010,
5784 /* MPC86xx microcontrollers */
5785#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
5786#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
5787#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 5788 /* PowerPC 6xx cores */
80d11f44
JM		 5789#define CPU_POWERPC_601 CPU_POWERPC_601_v2
5790 CPU_POWERPC_601_v0 = 0x00010001,
5791 CPU_POWERPC_601_v1 = 0x00010001,
5792 CPU_POWERPC_601_v2 = 0x00010002,
5793 CPU_POWERPC_602 = 0x00050100,
5794 CPU_POWERPC_603 = 0x00030100,
5795#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
5796 CPU_POWERPC_603E_v11 = 0x00060101,
5797 CPU_POWERPC_603E_v12 = 0x00060102,
5798 CPU_POWERPC_603E_v13 = 0x00060103,
5799 CPU_POWERPC_603E_v14 = 0x00060104,
5800 CPU_POWERPC_603E_v22 = 0x00060202,
5801 CPU_POWERPC_603E_v3 = 0x00060300,
5802 CPU_POWERPC_603E_v4 = 0x00060400,
5803 CPU_POWERPC_603E_v41 = 0x00060401,
5804 CPU_POWERPC_603E7t = 0x00071201,
5805 CPU_POWERPC_603E7v = 0x00070100,
5806 CPU_POWERPC_603E7v1 = 0x00070101,
5807 CPU_POWERPC_603E7v2 = 0x00070201,
5808 CPU_POWERPC_603E7 = 0x00070200,
5809 CPU_POWERPC_603P = 0x00070000,
5810#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 5811 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 5812 CPU_POWERPC_604 = 0x00040103,
5813#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 5814 /* XXX: missing 0x00091203 */
5815 /* XXX: missing 0x00092110 */
5816 /* XXX: missing 0x00092120 */
80d11f44
JM		 5817 CPU_POWERPC_604E_v10 = 0x00090100,
5818 CPU_POWERPC_604E_v22 = 0x00090202,
5819 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 5820 /* XXX: missing 0x000a0100 */
5821 /* XXX: missing 0x00093102 */
80d11f44 5822 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 5823#if 0
80d11f44 5824 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 5825#endif
5826 /* PowerPC 740/750 cores (aka G3) */
5827 /* XXX: missing 0x00084202 */
80d11f44
JM		 5828#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
5829 CPU_POWERPC_7x0_v20 = 0x00080200,
5830 CPU_POWERPC_7x0_v21 = 0x00080201,
5831 CPU_POWERPC_7x0_v22 = 0x00080202,
5832 CPU_POWERPC_7x0_v30 = 0x00080300,
5833 CPU_POWERPC_7x0_v31 = 0x00080301,
5834 CPU_POWERPC_740E = 0x00080100,
5835 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 5836 /* XXX: missing 0x00087010 (CL ?) */
80d11f44
JM		 5837 CPU_POWERPC_750CL = 0x00087200,
5838#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
5839 CPU_POWERPC_750CX_v21 = 0x00082201,
5840 CPU_POWERPC_750CX_v22 = 0x00082202,
5841#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
5842 CPU_POWERPC_750CXE_v21 = 0x00082211,
5843 CPU_POWERPC_750CXE_v22 = 0x00082212,
5844 CPU_POWERPC_750CXE_v23 = 0x00082213,
5845 CPU_POWERPC_750CXE_v24 = 0x00082214,
5846 CPU_POWERPC_750CXE_v24b = 0x00083214,
5847 CPU_POWERPC_750CXE_v31 = 0x00083211,
5848 CPU_POWERPC_750CXE_v31b = 0x00083311,
5849 CPU_POWERPC_750CXR = 0x00083410,
5850 CPU_POWERPC_750E = 0x00080200,
5851 CPU_POWERPC_750FL = 0x700A0203,
5852#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
5853 CPU_POWERPC_750FX_v10 = 0x70000100,
5854 CPU_POWERPC_750FX_v20 = 0x70000200,
5855 CPU_POWERPC_750FX_v21 = 0x70000201,
5856 CPU_POWERPC_750FX_v22 = 0x70000202,
5857 CPU_POWERPC_750FX_v23 = 0x70000203,
5858 CPU_POWERPC_750GL = 0x70020102,
5859#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
5860 CPU_POWERPC_750GX_v10 = 0x70020100,
5861 CPU_POWERPC_750GX_v11 = 0x70020101,
5862 CPU_POWERPC_750GX_v12 = 0x70020102,
5863#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
5864 CPU_POWERPC_750L_v22 = 0x00088202,
5865 CPU_POWERPC_750L_v30 = 0x00088300,
5866 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 5867 /* PowerPC 745/755 cores */
80d11f44
JM		 5868#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
5869 CPU_POWERPC_7x5_v10 = 0x00083100,
5870 CPU_POWERPC_7x5_v11 = 0x00083101,
5871 CPU_POWERPC_7x5_v20 = 0x00083200,
5872 CPU_POWERPC_7x5_v21 = 0x00083201,
5873 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
5874 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
5875 CPU_POWERPC_7x5_v24 = 0x00083204,
5876 CPU_POWERPC_7x5_v25 = 0x00083205,
5877 CPU_POWERPC_7x5_v26 = 0x00083206,
5878 CPU_POWERPC_7x5_v27 = 0x00083207,
5879 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 5880#if 0
80d11f44 5881 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 5882#endif
5883 /* PowerPC 74xx cores (aka G4) */
5884 /* XXX: missing 0x000C1101 */
80d11f44
JM		 5885#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
5886 CPU_POWERPC_7400_v10 = 0x000C0100,
5887 CPU_POWERPC_7400_v11 = 0x000C0101,
5888 CPU_POWERPC_7400_v20 = 0x000C0200,
5889 CPU_POWERPC_7400_v22 = 0x000C0202,
5890 CPU_POWERPC_7400_v26 = 0x000C0206,
5891 CPU_POWERPC_7400_v27 = 0x000C0207,
5892 CPU_POWERPC_7400_v28 = 0x000C0208,
5893 CPU_POWERPC_7400_v29 = 0x000C0209,
5894#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
5895 CPU_POWERPC_7410_v10 = 0x800C1100,
5896 CPU_POWERPC_7410_v11 = 0x800C1101,
5897 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
5898 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
5899 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
5900#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
5901 CPU_POWERPC_7448_v10 = 0x80040100,
5902 CPU_POWERPC_7448_v11 = 0x80040101,
5903 CPU_POWERPC_7448_v20 = 0x80040200,
5904 CPU_POWERPC_7448_v21 = 0x80040201,
5905#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
5906 CPU_POWERPC_7450_v10 = 0x80000100,
5907 CPU_POWERPC_7450_v11 = 0x80000101,
5908 CPU_POWERPC_7450_v12 = 0x80000102,
5909 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
5910 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
5911 CPU_POWERPC_74x1 = 0x80000203,
5912 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
5913#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
5914 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 5915 /* XXX: missing 0x80010200 */
80d11f44
JM		 5916 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
5917 CPU_POWERPC_74x5_v32 = 0x80010302,
5918 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
5919 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
5920#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
c3e36823
JM		 5921 /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
5922 /* XXX: missing 0x80030102 */
5923 /* XXX: missing 0x80020101 */
80d11f44
JM		 5924 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
5925 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
5926 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
a750fc0b 5927 /* 64 bits PowerPC */
00af685f 5928#if defined(TARGET_PPC64)
80d11f44
JM		 5929 CPU_POWERPC_620 = 0x00140000,
5930 CPU_POWERPC_630 = 0x00400000,
5931 CPU_POWERPC_631 = 0x00410104,
5932 CPU_POWERPC_POWER4 = 0x00350000,
5933 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 5934 /* XXX: missing 0x003A0201 */
80d11f44
JM		 5935 CPU_POWERPC_POWER5 = 0x003A0203,
5936#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
5937 CPU_POWERPC_POWER5P = 0x003B0000,
5938#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
5939 CPU_POWERPC_POWER6 = 0x003E0000,
5940 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
5941 CPU_POWERPC_POWER6A = 0x0F000002,
5942 CPU_POWERPC_970 = 0x00390202,
5943#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
5944 CPU_POWERPC_970FX_v10 = 0x00391100,
5945 CPU_POWERPC_970FX_v20 = 0x003C0200,
5946 CPU_POWERPC_970FX_v21 = 0x003C0201,
5947 CPU_POWERPC_970FX_v30 = 0x003C0300,
5948 CPU_POWERPC_970FX_v31 = 0x003C0301,
5949 CPU_POWERPC_970GX = 0x00450000,
5950#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
5951 CPU_POWERPC_970MP_v10 = 0x00440100,
5952 CPU_POWERPC_970MP_v11 = 0x00440101,
5953#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
5954 CPU_POWERPC_CELL_v10 = 0x00700100,
5955 CPU_POWERPC_CELL_v20 = 0x00700400,
5956 CPU_POWERPC_CELL_v30 = 0x00700500,
5957 CPU_POWERPC_CELL_v31 = 0x00700501,
5958#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
5959 CPU_POWERPC_RS64 = 0x00330000,
5960 CPU_POWERPC_RS64II = 0x00340000,
5961 CPU_POWERPC_RS64III = 0x00360000,
5962 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 5963#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 5964 /* Original POWER */
5965 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
5966 * POWER2 (RIOS2) & RSC2 (P2SC) here
5967 */
5968#if 0
80d11f44 5969 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 5970#endif
5971#if 0
80d11f44 5972 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 5973#endif
5974 /* PA Semi core */
80d11f44 5975 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 5976};
5977
5978/* System version register (used on MPC 8xxx) */
5979enum {
80d11f44
JM		 5980 POWERPC_SVR_NONE = 0x00000000,
5981#define POWERPC_SVR_52xx POWERPC_SVR_5200
5982#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
5983 POWERPC_SVR_5200_v10 = 0x80110010,
5984 POWERPC_SVR_5200_v11 = 0x80110011,
5985 POWERPC_SVR_5200_v12 = 0x80110012,
5986#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
5987 POWERPC_SVR_5200B_v20 = 0x80110020,
5988 POWERPC_SVR_5200B_v21 = 0x80110021,
5989#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 5990#if 0
80d11f44 5991 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 5992#endif
5993#if 0
80d11f44 5994 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 5995#endif
5996#if 0
80d11f44 5997 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 5998#endif
5999#if 0
80d11f44 6000 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 6001#endif
6002#if 0
80d11f44 6003 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 6004#endif
6005#if 0
80d11f44 6006 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 6007#endif
6008#if 0
80d11f44 6009 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 6010#endif
6011#if 0
80d11f44 6012 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 6013#endif
6014#if 0
80d11f44 6015 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 6016#endif
6017#if 0
80d11f44 6018 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 6019#endif
6020#if 0
80d11f44 6021 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 6022#endif
6023#if 0
80d11f44 6024 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 6025#endif
6026#if 0
80d11f44 6027 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 6028#endif
6029#if 0
80d11f44 6030 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 6031#endif
6032#if 0
80d11f44 6033 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 6034#endif
6035#if 0
80d11f44 6036 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 6037#endif
6038#if 0
80d11f44 6039 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 6040#endif
6041#if 0
80d11f44
JM		 6042 POWERPC_SVR_8323E = xxx,
6043#endif
6044 POWERPC_SVR_8343A = 0x80570030,
6045 POWERPC_SVR_8343EA = 0x80560030,
6046#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
6047 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
6048 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
6049#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
6050 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
6051 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
6052 POWERPC_SVR_8349 = 0x80510010,
6053 POWERPC_SVR_8349A = 0x80510030,
6054 POWERPC_SVR_8349E = 0x80500010,
6055 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 6056#if 0
80d11f44 6057 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 6058#endif
6059#if 0
80d11f44
JM		 6060 POWERPC_SVR_8360E = xxx,
6061#endif
6062#define POWERPC_SVR_E500 0x40000000
6063 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
6064 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
6065 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
6066 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
6067 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
6068 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
6069#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
6070 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
6071 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
6072#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
6073 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
6074 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
6075#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
6076 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
6077 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
6078 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
6079#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
6080 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
6081 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
6082#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
6083 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
6084 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
6085#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
6086 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
6087 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
6088 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
6089 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
6090#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
6091 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
6092 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
6093 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
6094 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
6095#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
6096 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
6097 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
6098#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
6099 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
6100 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
6101#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
6102 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
6103 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
6104#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
6105 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
6106 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
6107#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
6108 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
6109 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
6110#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
6111 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
6112 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
6113 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
6114 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
6115#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
6116 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
6117 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
6118 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
6119 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
6120#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
6121 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
6122 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
6123#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
6124 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
6125 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
6126#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
6127 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
6128 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
6129 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
6130 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
6131 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
6132 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
6133 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
6134 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
6135 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 6136#if 0
80d11f44 6137 POWERPC_SVR_8610 = xxx,
c3e36823 6138#endif
80d11f44
JM		 6139 POWERPC_SVR_8641 = 0x80900021,
6140 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 6141};
6142
3fc6c082 6143/*****************************************************************************/
a750fc0b 6144/* PowerPC CPU definitions */
80d11f44 6145#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 6146 { \
6147 .name = _name, \
6148 .pvr = _pvr, \
80d11f44 6149 .svr = _svr, \
a750fc0b
JM		 6150 .insns_flags = glue(POWERPC_INSNS_,_type), \
6151 .msr_mask = glue(POWERPC_MSRM_,_type), \
6152 .mmu_model = glue(POWERPC_MMU_,_type), \
6153 .excp_model = glue(POWERPC_EXCP_,_type), \
6154 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 6155 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 6156 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 6157 .init_proc = &glue(init_proc_,_type), \
2f462816 6158 .check_pow = &glue(check_pow_,_type), \
a750fc0b 6159 }
80d11f44
JM		 6160#define POWERPC_DEF(_name, _pvr, _type) \
6161POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 6162
ee4e83ed 6163static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 6164 /* Embedded PowerPC */
6165 /* PowerPC 401 family */
2662a059 6166 /* Generic PowerPC 401 */
80d11f44 6167 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 6168 /* PowerPC 401 cores */
2662a059 6169 /* PowerPC 401A1 */
80d11f44 6170 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 6171 /* PowerPC 401B2 */
80d11f44 6172 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 6173#if defined (TODO)
a750fc0b 6174 /* PowerPC 401B3 */
80d11f44 6175 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 6176#endif
6177 /* PowerPC 401C2 */
80d11f44 6178 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 6179 /* PowerPC 401D2 */
80d11f44 6180 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 6181 /* PowerPC 401E2 */
80d11f44 6182 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 6183 /* PowerPC 401F2 */
80d11f44 6184 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 6185 /* PowerPC 401G2 */
6186 /* XXX: to be checked */
80d11f44 6187 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 6188 /* PowerPC 401 microcontrolers */
2662a059 6189#if defined (TODO)
a750fc0b 6190 /* PowerPC 401GF */
80d11f44 6191 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 6192#endif
a750fc0b 6193 /* IOP480 (401 microcontroler) */
80d11f44 6194 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 6195 /* IBM Processor for Network Resources */
80d11f44 6196 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 6197#if defined (TODO)
80d11f44 6198 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 6199#endif
a750fc0b
JM		 6200 /* PowerPC 403 family */
6201 /* Generic PowerPC 403 */
80d11f44 6202 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 6203 /* PowerPC 403 microcontrolers */
6204 /* PowerPC 403 GA */
80d11f44 6205 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 6206 /* PowerPC 403 GB */
80d11f44 6207 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 6208 /* PowerPC 403 GC */
80d11f44 6209 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 6210 /* PowerPC 403 GCX */
80d11f44 6211 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 6212#if defined (TODO)
a750fc0b 6213 /* PowerPC 403 GP */
80d11f44 6214 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 6215#endif
a750fc0b
JM		 6216 /* PowerPC 405 family */
6217 /* Generic PowerPC 405 */
80d11f44 6218 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 6219 /* PowerPC 405 cores */
2662a059 6220#if defined (TODO)
a750fc0b 6221 /* PowerPC 405 A3 */
80d11f44 6222 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 6223#endif
3a607854 6224#if defined (TODO)
a750fc0b 6225 /* PowerPC 405 A4 */
80d11f44 6226 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 6227#endif
3a607854 6228#if defined (TODO)
a750fc0b 6229 /* PowerPC 405 B3 */
80d11f44 6230 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 6231#endif
6232#if defined (TODO)
a750fc0b 6233 /* PowerPC 405 B4 */
80d11f44 6234 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 6235#endif
6236#if defined (TODO)
6237 /* PowerPC 405 C3 */
80d11f44 6238 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 6239#endif
6240#if defined (TODO)
6241 /* PowerPC 405 C4 */
80d11f44 6242 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 6243#endif
6244 /* PowerPC 405 D2 */
80d11f44 6245 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 6246#if defined (TODO)
6247 /* PowerPC 405 D3 */
80d11f44 6248 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 6249#endif
6250 /* PowerPC 405 D4 */
80d11f44 6251 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 6252#if defined (TODO)
6253 /* PowerPC 405 D5 */
80d11f44 6254 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 6255#endif
6256#if defined (TODO)
6257 /* PowerPC 405 E4 */
80d11f44 6258 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 6259#endif
6260#if defined (TODO)
6261 /* PowerPC 405 F4 */
80d11f44 6262 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 6263#endif
6264#if defined (TODO)
6265 /* PowerPC 405 F5 */
80d11f44 6266 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 6267#endif
6268#if defined (TODO)
6269 /* PowerPC 405 F6 */
80d11f44 6270 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 6271#endif
6272 /* PowerPC 405 microcontrolers */
6273 /* PowerPC 405 CR */
80d11f44 6274 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 6275 /* PowerPC 405 CRa */
80d11f44 6276 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 6277 /* PowerPC 405 CRb */
80d11f44 6278 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 6279 /* PowerPC 405 CRc */
80d11f44 6280 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 6281 /* PowerPC 405 EP */
80d11f44 6282 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 6283#if defined(TODO)
6284 /* PowerPC 405 EXr */
80d11f44 6285 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 6286#endif
6287 /* PowerPC 405 EZ */
80d11f44 6288 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 6289#if defined(TODO)
6290 /* PowerPC 405 FX */
80d11f44 6291 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 6292#endif
6293 /* PowerPC 405 GP */
80d11f44 6294 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 6295 /* PowerPC 405 GPa */
80d11f44 6296 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 6297 /* PowerPC 405 GPb */
80d11f44 6298 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 6299 /* PowerPC 405 GPc */
80d11f44 6300 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 6301 /* PowerPC 405 GPd */
80d11f44 6302 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 6303 /* PowerPC 405 GPe */
80d11f44 6304 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 6305 /* PowerPC 405 GPR */
80d11f44 6306 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 6307#if defined(TODO)
6308 /* PowerPC 405 H */
80d11f44 6309 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 6310#endif
6311#if defined(TODO)
6312 /* PowerPC 405 L */
80d11f44 6313 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 6314#endif
6315 /* PowerPC 405 LP */
80d11f44 6316 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 6317#if defined(TODO)
6318 /* PowerPC 405 PM */
80d11f44 6319 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 6320#endif
6321#if defined(TODO)
6322 /* PowerPC 405 PS */
80d11f44 6323 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 6324#endif
6325#if defined(TODO)
6326 /* PowerPC 405 S */
80d11f44 6327 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 6328#endif
6329 /* Npe405 H */
80d11f44 6330 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 6331 /* Npe405 H2 */
80d11f44 6332 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 6333 /* Npe405 L */
80d11f44 6334 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 6335 /* Npe4GS3 */
80d11f44 6336 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 6337#if defined (TODO)
80d11f44 6338 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 6339#endif
6340#if defined (TODO)
80d11f44 6341 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 6342#endif
6343#if defined (TODO)
6344 /* PowerPC LC77700 (Sanyo) */
80d11f44 6345 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 6346#endif
6347 /* PowerPC 401/403/405 based set-top-box microcontrolers */
6348#if defined (TODO)
6349 /* STB010000 */
80d11f44 6350 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 6351#endif
6352#if defined (TODO)
6353 /* STB01010 */
80d11f44 6354 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 6355#endif
6356#if defined (TODO)
6357 /* STB0210 */
80d11f44 6358 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 6359#endif
6360 /* STB03xx */
80d11f44 6361 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 6362#if defined (TODO)
6363 /* STB043x */
80d11f44 6364 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 6365#endif
6366#if defined (TODO)
6367 /* STB045x */
80d11f44 6368 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 6369#endif
6370 /* STB04xx */
80d11f44 6371 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 6372 /* STB25xx */
80d11f44 6373 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 6374#if defined (TODO)
6375 /* STB130 */
80d11f44 6376 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 6377#endif
6378 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 6379 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
6380 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
6381 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
6382 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 6383#if defined (TODO)
6384 /* Zarlink ZL10310 */
80d11f44 6385 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 6386#endif
6387#if defined (TODO)
6388 /* Zarlink ZL10311 */
80d11f44 6389 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 6390#endif
6391#if defined (TODO)
6392 /* Zarlink ZL10320 */
80d11f44 6393 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 6394#endif
6395#if defined (TODO)
6396 /* Zarlink ZL10321 */
80d11f44 6397 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 6398#endif
6399 /* PowerPC 440 family */
80d11f44 6400#if defined(TODO_USER_ONLY)
a750fc0b 6401 /* Generic PowerPC 440 */
80d11f44
JM		 6402 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
6403#endif
a750fc0b
JM		 6404 /* PowerPC 440 cores */
6405#if defined (TODO)
6406 /* PowerPC 440 A4 */
80d11f44 6407 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b
JM		 6408#endif
6409#if defined (TODO)
6410 /* PowerPC 440 A5 */
80d11f44 6411 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 6412#endif
6413#if defined (TODO)
6414 /* PowerPC 440 B4 */
80d11f44 6415 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 6416#endif
6417#if defined (TODO)
6418 /* PowerPC 440 G4 */
80d11f44 6419 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 6420#endif
6421#if defined (TODO)
6422 /* PowerPC 440 F5 */
80d11f44 6423 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 6424#endif
6425#if defined (TODO)
6426 /* PowerPC 440 G5 */
80d11f44 6427 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 6428#endif
6429#if defined (TODO)
6430 /* PowerPC 440H4 */
80d11f44 6431 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 6432#endif
6433#if defined (TODO)
6434 /* PowerPC 440H6 */
80d11f44 6435 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 6436#endif
6437 /* PowerPC 440 microcontrolers */
80d11f44 6438#if defined(TODO_USER_ONLY)
a750fc0b 6439 /* PowerPC 440 EP */
80d11f44
JM		 6440 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
6441#endif
6442#if defined(TODO_USER_ONLY)
a750fc0b 6443 /* PowerPC 440 EPa */
80d11f44
JM		 6444 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
6445#endif
6446#if defined(TODO_USER_ONLY)
a750fc0b 6447 /* PowerPC 440 EPb */
80d11f44
JM		 6448 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
6449#endif
6450#if defined(TODO_USER_ONLY)
a750fc0b 6451 /* PowerPC 440 EPX */
80d11f44
JM		 6452 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
6453#endif
6454#if defined(TODO_USER_ONLY)
a750fc0b 6455 /* PowerPC 440 GP */
80d11f44
JM		 6456 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
6457#endif
6458#if defined(TODO_USER_ONLY)
a750fc0b 6459 /* PowerPC 440 GPb */
80d11f44
JM		 6460 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
6461#endif
6462#if defined(TODO_USER_ONLY)
a750fc0b 6463 /* PowerPC 440 GPc */
80d11f44
JM		 6464 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
6465#endif
6466#if defined(TODO_USER_ONLY)
a750fc0b 6467 /* PowerPC 440 GR */
80d11f44
JM		 6468 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
6469#endif
6470#if defined(TODO_USER_ONLY)
a750fc0b 6471 /* PowerPC 440 GRa */
80d11f44
JM		 6472 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
6473#endif
6474#if defined(TODO_USER_ONLY)
a750fc0b 6475 /* PowerPC 440 GRX */
80d11f44
JM		 6476 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
6477#endif
6478#if defined(TODO_USER_ONLY)
a750fc0b 6479 /* PowerPC 440 GX */
80d11f44
JM		 6480 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
6481#endif
6482#if defined(TODO_USER_ONLY)
a750fc0b 6483 /* PowerPC 440 GXa */
80d11f44
JM		 6484 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
6485#endif
6486#if defined(TODO_USER_ONLY)
a750fc0b 6487 /* PowerPC 440 GXb */
80d11f44
JM		 6488 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
6489#endif
6490#if defined(TODO_USER_ONLY)
a750fc0b 6491 /* PowerPC 440 GXc */
80d11f44
JM		 6492 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
6493#endif
6494#if defined(TODO_USER_ONLY)
a750fc0b 6495 /* PowerPC 440 GXf */
80d11f44
JM		 6496 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
6497#endif
a750fc0b
JM		 6498#if defined(TODO)
6499 /* PowerPC 440 S */
80d11f44 6500 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 6501#endif
80d11f44 6502#if defined(TODO_USER_ONLY)
a750fc0b 6503 /* PowerPC 440 SP */
80d11f44
JM		 6504 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
6505#endif
6506#if defined(TODO_USER_ONLY)
a750fc0b 6507 /* PowerPC 440 SP2 */
80d11f44
JM		 6508 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
6509#endif
6510#if defined(TODO_USER_ONLY)
a750fc0b 6511 /* PowerPC 440 SPE */
80d11f44
JM		 6512 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
6513#endif
a750fc0b
JM		 6514 /* PowerPC 460 family */
6515#if defined (TODO)
6516 /* Generic PowerPC 464 */
80d11f44 6517 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 6518#endif
6519 /* PowerPC 464 microcontrolers */
6520#if defined (TODO)
6521 /* PowerPC 464H90 */
80d11f44 6522 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 6523#endif
6524#if defined (TODO)
6525 /* PowerPC 464H90F */
80d11f44 6526 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 6527#endif
6528 /* Freescale embedded PowerPC cores */
80d11f44
JM		 6529 /* MPC5xx family (aka RCPU) */
6530#if defined(TODO_USER_ONLY)
6531 /* Generic MPC5xx core */
6532 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
6533#endif
6534#if defined(TODO_USER_ONLY)
6535 /* Codename for MPC5xx core */
6536 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
6537#endif
6538 /* MPC5xx microcontrollers */
6539#if defined(TODO_USER_ONLY)
6540 /* MGT560 */
6541 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
6542#endif
6543#if defined(TODO_USER_ONLY)
6544 /* MPC509 */
6545 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
6546#endif
6547#if defined(TODO_USER_ONLY)
6548 /* MPC533 */
6549 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
6550#endif
6551#if defined(TODO_USER_ONLY)
6552 /* MPC534 */
6553 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
6554#endif
6555#if defined(TODO_USER_ONLY)
6556 /* MPC555 */
6557 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
6558#endif
6559#if defined(TODO_USER_ONLY)
6560 /* MPC556 */
6561 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
6562#endif
6563#if defined(TODO_USER_ONLY)
6564 /* MPC560 */
6565 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
6566#endif
6567#if defined(TODO_USER_ONLY)
6568 /* MPC561 */
6569 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
6570#endif
6571#if defined(TODO_USER_ONLY)
6572 /* MPC562 */
6573 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
6574#endif
6575#if defined(TODO_USER_ONLY)
6576 /* MPC563 */
6577 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
6578#endif
6579#if defined(TODO_USER_ONLY)
6580 /* MPC564 */
6581 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
6582#endif
6583#if defined(TODO_USER_ONLY)
6584 /* MPC565 */
6585 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
6586#endif
6587#if defined(TODO_USER_ONLY)
6588 /* MPC566 */
6589 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
6590#endif
6591 /* MPC8xx family (aka PowerQUICC) */
6592#if defined(TODO_USER_ONLY)
6593 /* Generic MPC8xx core */
6594 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
6595#endif
6596#if defined(TODO_USER_ONLY)
6597 /* Codename for MPC8xx core */
6598 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
6599#endif
6600 /* MPC8xx microcontrollers */
6601#if defined(TODO_USER_ONLY)
6602 /* MGT823 */
6603 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
6604#endif
6605#if defined(TODO_USER_ONLY)
6606 /* MPC821 */
6607 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
6608#endif
6609#if defined(TODO_USER_ONLY)
6610 /* MPC823 */
6611 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
6612#endif
6613#if defined(TODO_USER_ONLY)
6614 /* MPC850 */
6615 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
6616#endif
6617#if defined(TODO_USER_ONLY)
6618 /* MPC852T */
6619 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
6620#endif
6621#if defined(TODO_USER_ONLY)
6622 /* MPC855T */
6623 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
6624#endif
6625#if defined(TODO_USER_ONLY)
6626 /* MPC857 */
6627 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
6628#endif
6629#if defined(TODO_USER_ONLY)
6630 /* MPC859 */
6631 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
6632#endif
6633#if defined(TODO_USER_ONLY)
6634 /* MPC860 */
6635 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
6636#endif
6637#if defined(TODO_USER_ONLY)
6638 /* MPC862 */
6639 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
6640#endif
6641#if defined(TODO_USER_ONLY)
6642 /* MPC866 */
6643 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
6644#endif
6645#if defined(TODO_USER_ONLY)
6646 /* MPC870 */
6647 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
6648#endif
6649#if defined(TODO_USER_ONLY)
6650 /* MPC875 */
6651 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
6652#endif
6653#if defined(TODO_USER_ONLY)
6654 /* MPC880 */
6655 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
6656#endif
6657#if defined(TODO_USER_ONLY)
6658 /* MPC885 */
6659 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
6660#endif
6661 /* MPC82xx family (aka PowerQUICC-II) */
6662 /* Generic MPC52xx core */
6663 POWERPC_DEF_SVR("MPC52xx",
6664 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
6665 /* Generic MPC82xx core */
6666 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
6667 /* Codename for MPC82xx */
6668 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
6669 /* PowerPC G2 core */
6670 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
6671 /* PowerPC G2 H4 core */
6672 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
6673 /* PowerPC G2 GP core */
6674 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
6675 /* PowerPC G2 LS core */
6676 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
6677 /* PowerPC G2 HiP3 core */
6678 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
6679 /* PowerPC G2 HiP4 core */
6680 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
6681 /* PowerPC MPC603 core */
6682 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
6683 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
6684 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
6685 /* PowerPC G2LE GP core */
6686 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
6687 /* PowerPC G2LE LS core */
6688 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
6689 /* PowerPC G2LE GP1 core */
6690 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
6691 /* PowerPC G2LE GP3 core */
6692 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
6693 /* PowerPC MPC603 microcontrollers */
6694 /* MPC8240 */
6695 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
6696 /* PowerPC G2 microcontrollers */
6697#if 0
6698 /* MPC5121 */
6699 POWERPC_DEF_SVR("MPC5121",
6700 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
6701#endif
6702 /* MPC5200 */
6703 POWERPC_DEF_SVR("MPC5200",
6704 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
6705 /* MPC5200 v1.0 */
6706 POWERPC_DEF_SVR("MPC5200_v10",
6707 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
6708 /* MPC5200 v1.1 */
6709 POWERPC_DEF_SVR("MPC5200_v11",
6710 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
6711 /* MPC5200 v1.2 */
6712 POWERPC_DEF_SVR("MPC5200_v12",
6713 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
6714 /* MPC5200B */
6715 POWERPC_DEF_SVR("MPC5200B",
6716 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
6717 /* MPC5200B v2.0 */
6718 POWERPC_DEF_SVR("MPC5200B_v20",
6719 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
6720 /* MPC5200B v2.1 */
6721 POWERPC_DEF_SVR("MPC5200B_v21",
6722 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
6723 /* MPC8241 */
6724 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
6725 /* MPC8245 */
6726 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
6727 /* MPC8247 */
6728 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
6729 /* MPC8248 */
6730 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
6731 /* MPC8250 */
6732 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
6733 /* MPC8250 HiP3 */
6734 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
6735 /* MPC8250 HiP4 */
6736 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
6737 /* MPC8255 */
6738 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
6739 /* MPC8255 HiP3 */
6740 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
6741 /* MPC8255 HiP4 */
6742 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
6743 /* MPC8260 */
6744 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
6745 /* MPC8260 HiP3 */
6746 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
6747 /* MPC8260 HiP4 */
6748 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
6749 /* MPC8264 */
6750 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
6751 /* MPC8264 HiP3 */
6752 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
6753 /* MPC8264 HiP4 */
6754 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
6755 /* MPC8265 */
6756 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
6757 /* MPC8265 HiP3 */
6758 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
6759 /* MPC8265 HiP4 */
6760 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
6761 /* MPC8266 */
6762 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
6763 /* MPC8266 HiP3 */
6764 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
6765 /* MPC8266 HiP4 */
6766 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
6767 /* MPC8270 */
6768 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
6769 /* MPC8271 */
6770 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
6771 /* MPC8272 */
6772 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
6773 /* MPC8275 */
6774 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
6775 /* MPC8280 */
6776 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 6777 /* e200 family */
a750fc0b 6778 /* Generic PowerPC e200 core */
80d11f44
JM		 6779 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
6780 /* Generic MPC55xx core */
6781#if defined (TODO)
6782 POWERPC_DEF_SVR("MPC55xx",
6783 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 6784#endif
6785#if defined (TODO)
80d11f44
JM		 6786 /* PowerPC e200z0 core */
6787 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 6788#endif
6789#if defined (TODO)
80d11f44
JM		 6790 /* PowerPC e200z1 core */
6791 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
6792#endif
6793#if defined (TODO)
6794 /* PowerPC e200z3 core */
6795 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
6796#endif
6797 /* PowerPC e200z5 core */
6798 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 6799 /* PowerPC e200z6 core */
80d11f44
JM		 6800 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
6801 /* PowerPC e200 microcontrollers */
6802#if defined (TODO)
6803 /* MPC5514E */
6804 POWERPC_DEF_SVR("MPC5514E",
6805 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 6806#endif
a750fc0b 6807#if defined (TODO)
80d11f44
JM		 6808 /* MPC5514E v0 */
6809 POWERPC_DEF_SVR("MPC5514E_v0",
6810 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 6811#endif
6812#if defined (TODO)
80d11f44
JM		 6813 /* MPC5514E v1 */
6814 POWERPC_DEF_SVR("MPC5514E_v1",
6815 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 6816#endif
6817#if defined (TODO)
80d11f44
JM		 6818 /* MPC5514G */
6819 POWERPC_DEF_SVR("MPC5514G",
6820 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 6821#endif
6822#if defined (TODO)
80d11f44
JM		 6823 /* MPC5514G v0 */
6824 POWERPC_DEF_SVR("MPC5514G_v0",
6825 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 6826#endif
a750fc0b 6827#if defined (TODO)
80d11f44
JM		 6828 /* MPC5514G v1 */
6829 POWERPC_DEF_SVR("MPC5514G_v1",
6830 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 6831#endif
6832#if defined (TODO)
80d11f44
JM		 6833 /* MPC5515S */
6834 POWERPC_DEF_SVR("MPC5515S",
6835 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 6836#endif
6837#if defined (TODO)
80d11f44
JM		 6838 /* MPC5516E */
6839 POWERPC_DEF_SVR("MPC5516E",
6840 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 6841#endif
6842#if defined (TODO)
80d11f44
JM		 6843 /* MPC5516E v0 */
6844 POWERPC_DEF_SVR("MPC5516E_v0",
6845 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 6846#endif
6847#if defined (TODO)
80d11f44
JM		 6848 /* MPC5516E v1 */
6849 POWERPC_DEF_SVR("MPC5516E_v1",
6850 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 6851#endif
a750fc0b 6852#if defined (TODO)
80d11f44
JM		 6853 /* MPC5516G */
6854 POWERPC_DEF_SVR("MPC5516G",
6855 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 6856#endif
a750fc0b 6857#if defined (TODO)
80d11f44
JM		 6858 /* MPC5516G v0 */
6859 POWERPC_DEF_SVR("MPC5516G_v0",
6860 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 6861#endif
a750fc0b 6862#if defined (TODO)
80d11f44
JM		 6863 /* MPC5516G v1 */
6864 POWERPC_DEF_SVR("MPC5516G_v1",
6865 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 6866#endif
a750fc0b 6867#if defined (TODO)
80d11f44
JM		 6868 /* MPC5516S */
6869 POWERPC_DEF_SVR("MPC5516S",
6870 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 6871#endif
6872#if defined (TODO)
80d11f44
JM		 6873 /* MPC5533 */
6874 POWERPC_DEF_SVR("MPC5533",
6875 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 6876#endif
6877#if defined (TODO)
80d11f44
JM		 6878 /* MPC5534 */
6879 POWERPC_DEF_SVR("MPC5534",
6880 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 6881#endif
80d11f44
JM		 6882#if defined (TODO)
6883 /* MPC5553 */
6884 POWERPC_DEF_SVR("MPC5553",
6885 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
6886#endif
6887#if defined (TODO)
6888 /* MPC5554 */
6889 POWERPC_DEF_SVR("MPC5554",
6890 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
6891#endif
6892#if defined (TODO)
6893 /* MPC5561 */
6894 POWERPC_DEF_SVR("MPC5561",
6895 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
6896#endif
6897#if defined (TODO)
6898 /* MPC5565 */
6899 POWERPC_DEF_SVR("MPC5565",
6900 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
6901#endif
6902#if defined (TODO)
6903 /* MPC5566 */
6904 POWERPC_DEF_SVR("MPC5566",
6905 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
6906#endif
6907#if defined (TODO)
6908 /* MPC5567 */
6909 POWERPC_DEF_SVR("MPC5567",
6910 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
6911#endif
6912 /* e300 family */
6913 /* Generic PowerPC e300 core */
6914 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
6915 /* PowerPC e300c1 core */
6916 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
6917 /* PowerPC e300c2 core */
6918 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
6919 /* PowerPC e300c3 core */
6920 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
6921 /* PowerPC e300c4 core */
6922 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
6923 /* PowerPC e300 microcontrollers */
6924#if defined (TODO)
6925 /* MPC8313 */
6926 POWERPC_DEF_SVR("MPC8313",
6927 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
6928#endif
6929#if defined (TODO)
6930 /* MPC8313E */
6931 POWERPC_DEF_SVR("MPC8313E",
6932 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
6933#endif
6934#if defined (TODO)
6935 /* MPC8314 */
6936 POWERPC_DEF_SVR("MPC8314",
6937 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
6938#endif
6939#if defined (TODO)
6940 /* MPC8314E */
6941 POWERPC_DEF_SVR("MPC8314E",
6942 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
6943#endif
6944#if defined (TODO)
6945 /* MPC8315 */
6946 POWERPC_DEF_SVR("MPC8315",
6947 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
6948#endif
6949#if defined (TODO)
6950 /* MPC8315E */
6951 POWERPC_DEF_SVR("MPC8315E",
6952 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
6953#endif
6954#if defined (TODO)
6955 /* MPC8321 */
6956 POWERPC_DEF_SVR("MPC8321",
6957 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
6958#endif
6959#if defined (TODO)
6960 /* MPC8321E */
6961 POWERPC_DEF_SVR("MPC8321E",
6962 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
6963#endif
6964#if defined (TODO)
6965 /* MPC8323 */
6966 POWERPC_DEF_SVR("MPC8323",
6967 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
6968#endif
6969#if defined (TODO)
6970 /* MPC8323E */
6971 POWERPC_DEF_SVR("MPC8323E",
6972 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
6973#endif
6974 /* MPC8343A */
6975 POWERPC_DEF_SVR("MPC8343A",
6976 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
6977 /* MPC8343EA */
6978 POWERPC_DEF_SVR("MPC8343EA",
6979 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
6980 /* MPC8347A */
6981 POWERPC_DEF_SVR("MPC8347A",
6982 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
6983 /* MPC8347AT */
6984 POWERPC_DEF_SVR("MPC8347AT",
6985 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
6986 /* MPC8347AP */
6987 POWERPC_DEF_SVR("MPC8347AP",
6988 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
6989 /* MPC8347EA */
6990 POWERPC_DEF_SVR("MPC8347EA",
6991 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
6992 /* MPC8347EAT */
6993 POWERPC_DEF_SVR("MPC8347EAT",
6994 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
6995 /* MPC8343EAP */
6996 POWERPC_DEF_SVR("MPC8347EAP",
6997 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
6998 /* MPC8349 */
6999 POWERPC_DEF_SVR("MPC8349",
7000 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
7001 /* MPC8349A */
7002 POWERPC_DEF_SVR("MPC8349A",
7003 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
7004 /* MPC8349E */
7005 POWERPC_DEF_SVR("MPC8349E",
7006 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
7007 /* MPC8349EA */
7008 POWERPC_DEF_SVR("MPC8349EA",
7009 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
7010#if defined (TODO)
7011 /* MPC8358E */
7012 POWERPC_DEF_SVR("MPC8358E",
7013 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
7014#endif
7015#if defined (TODO)
7016 /* MPC8360E */
7017 POWERPC_DEF_SVR("MPC8360E",
7018 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
7019#endif
7020 /* MPC8377 */
7021 POWERPC_DEF_SVR("MPC8377",
7022 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
7023 /* MPC8377E */
7024 POWERPC_DEF_SVR("MPC8377E",
7025 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
7026 /* MPC8378 */
7027 POWERPC_DEF_SVR("MPC8378",
7028 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
7029 /* MPC8378E */
7030 POWERPC_DEF_SVR("MPC8378E",
7031 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
7032 /* MPC8379 */
7033 POWERPC_DEF_SVR("MPC8379",
7034 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
7035 /* MPC8379E */
7036 POWERPC_DEF_SVR("MPC8379E",
7037 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
7038 /* e500 family */
7039 /* PowerPC e500 core */
7040 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
7041 /* PowerPC e500 v1.0 core */
7042 POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
7043 /* PowerPC e500 v2.0 core */
7044 POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
7045 /* PowerPC e500v2 core */
7046 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
7047 /* PowerPC e500v2 v1.0 core */
7048 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
7049 /* PowerPC e500v2 v2.0 core */
7050 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
7051 /* PowerPC e500v2 v2.1 core */
7052 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
7053 /* PowerPC e500v2 v2.2 core */
7054 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
7055 /* PowerPC e500v2 v3.0 core */
7056 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
7057 /* PowerPC e500 microcontrollers */
7058 /* MPC8533 */
7059 POWERPC_DEF_SVR("MPC8533",
7060 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
7061 /* MPC8533 v1.0 */
7062 POWERPC_DEF_SVR("MPC8533_v10",
7063 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
7064 /* MPC8533 v1.1 */
7065 POWERPC_DEF_SVR("MPC8533_v11",
7066 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
7067 /* MPC8533E */
7068 POWERPC_DEF_SVR("MPC8533E",
7069 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
7070 /* MPC8533E v1.0 */
7071 POWERPC_DEF_SVR("MPC8533E_v10",
7072 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
7073 POWERPC_DEF_SVR("MPC8533E_v11",
7074 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
7075 /* MPC8540 */
7076 POWERPC_DEF_SVR("MPC8540",
7077 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
7078 /* MPC8540 v1.0 */
7079 POWERPC_DEF_SVR("MPC8540_v10",
7080 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
7081 /* MPC8540 v2.0 */
7082 POWERPC_DEF_SVR("MPC8540_v20",
7083 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
7084 /* MPC8540 v2.1 */
7085 POWERPC_DEF_SVR("MPC8540_v21",
7086 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
7087 /* MPC8541 */
7088 POWERPC_DEF_SVR("MPC8541",
7089 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
7090 /* MPC8541 v1.0 */
7091 POWERPC_DEF_SVR("MPC8541_v10",
7092 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
7093 /* MPC8541 v1.1 */
7094 POWERPC_DEF_SVR("MPC8541_v11",
7095 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
7096 /* MPC8541E */
7097 POWERPC_DEF_SVR("MPC8541E",
7098 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
7099 /* MPC8541E v1.0 */
7100 POWERPC_DEF_SVR("MPC8541E_v10",
7101 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
7102 /* MPC8541E v1.1 */
7103 POWERPC_DEF_SVR("MPC8541E_v11",
7104 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
7105 /* MPC8543 */
7106 POWERPC_DEF_SVR("MPC8543",
7107 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
7108 /* MPC8543 v1.0 */
7109 POWERPC_DEF_SVR("MPC8543_v10",
7110 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
7111 /* MPC8543 v1.1 */
7112 POWERPC_DEF_SVR("MPC8543_v11",
7113 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
7114 /* MPC8543 v2.0 */
7115 POWERPC_DEF_SVR("MPC8543_v20",
7116 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
7117 /* MPC8543 v2.1 */
7118 POWERPC_DEF_SVR("MPC8543_v21",
7119 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
7120 /* MPC8543E */
7121 POWERPC_DEF_SVR("MPC8543E",
7122 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
7123 /* MPC8543E v1.0 */
7124 POWERPC_DEF_SVR("MPC8543E_v10",
7125 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
7126 /* MPC8543E v1.1 */
7127 POWERPC_DEF_SVR("MPC8543E_v11",
7128 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
7129 /* MPC8543E v2.0 */
7130 POWERPC_DEF_SVR("MPC8543E_v20",
7131 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
7132 /* MPC8543E v2.1 */
7133 POWERPC_DEF_SVR("MPC8543E_v21",
7134 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
7135 /* MPC8544 */
7136 POWERPC_DEF_SVR("MPC8544",
7137 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
7138 /* MPC8544 v1.0 */
7139 POWERPC_DEF_SVR("MPC8544_v10",
7140 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
7141 /* MPC8544 v1.1 */
7142 POWERPC_DEF_SVR("MPC8544_v11",
7143 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
7144 /* MPC8544E */
7145 POWERPC_DEF_SVR("MPC8544E",
7146 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
7147 /* MPC8544E v1.0 */
7148 POWERPC_DEF_SVR("MPC8544E_v10",
7149 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
7150 /* MPC8544E v1.1 */
7151 POWERPC_DEF_SVR("MPC8544E_v11",
7152 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
7153 /* MPC8545 */
7154 POWERPC_DEF_SVR("MPC8545",
7155 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
7156 /* MPC8545 v2.0 */
7157 POWERPC_DEF_SVR("MPC8545_v20",
7158 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
7159 /* MPC8545 v2.1 */
7160 POWERPC_DEF_SVR("MPC8545_v21",
7161 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
7162 /* MPC8545E */
7163 POWERPC_DEF_SVR("MPC8545E",
7164 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
7165 /* MPC8545E v2.0 */
7166 POWERPC_DEF_SVR("MPC8545E_v20",
7167 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
7168 /* MPC8545E v2.1 */
7169 POWERPC_DEF_SVR("MPC8545E_v21",
7170 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
7171 /* MPC8547E */
7172 POWERPC_DEF_SVR("MPC8547E",
7173 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
7174 /* MPC8547E v2.0 */
7175 POWERPC_DEF_SVR("MPC8547E_v20",
7176 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
7177 /* MPC8547E v2.1 */
7178 POWERPC_DEF_SVR("MPC8547E_v21",
7179 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
7180 /* MPC8548 */
7181 POWERPC_DEF_SVR("MPC8548",
7182 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
7183 /* MPC8548 v1.0 */
7184 POWERPC_DEF_SVR("MPC8548_v10",
7185 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
7186 /* MPC8548 v1.1 */
7187 POWERPC_DEF_SVR("MPC8548_v11",
7188 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
7189 /* MPC8548 v2.0 */
7190 POWERPC_DEF_SVR("MPC8548_v20",
7191 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
7192 /* MPC8548 v2.1 */
7193 POWERPC_DEF_SVR("MPC8548_v21",
7194 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
7195 /* MPC8548E */
7196 POWERPC_DEF_SVR("MPC8548E",
7197 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
7198 /* MPC8548E v1.0 */
7199 POWERPC_DEF_SVR("MPC8548E_v10",
7200 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
7201 /* MPC8548E v1.1 */
7202 POWERPC_DEF_SVR("MPC8548E_v11",
7203 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
7204 /* MPC8548E v2.0 */
7205 POWERPC_DEF_SVR("MPC8548E_v20",
7206 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
7207 /* MPC8548E v2.1 */
7208 POWERPC_DEF_SVR("MPC8548E_v21",
7209 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
7210 /* MPC8555 */
7211 POWERPC_DEF_SVR("MPC8555",
7212 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
7213 /* MPC8555 v1.0 */
7214 POWERPC_DEF_SVR("MPC8555_v10",
7215 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
7216 /* MPC8555 v1.1 */
7217 POWERPC_DEF_SVR("MPC8555_v11",
7218 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
7219 /* MPC8555E */
7220 POWERPC_DEF_SVR("MPC8555E",
7221 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
7222 /* MPC8555E v1.0 */
7223 POWERPC_DEF_SVR("MPC8555E_v10",
7224 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
7225 /* MPC8555E v1.1 */
7226 POWERPC_DEF_SVR("MPC8555E_v11",
7227 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
7228 /* MPC8560 */
7229 POWERPC_DEF_SVR("MPC8560",
7230 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
7231 /* MPC8560 v1.0 */
7232 POWERPC_DEF_SVR("MPC8560_v10",
7233 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
7234 /* MPC8560 v2.0 */
7235 POWERPC_DEF_SVR("MPC8560_v20",
7236 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
7237 /* MPC8560 v2.1 */
7238 POWERPC_DEF_SVR("MPC8560_v21",
7239 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
7240 /* MPC8567 */
7241 POWERPC_DEF_SVR("MPC8567",
7242 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
7243 /* MPC8567E */
7244 POWERPC_DEF_SVR("MPC8567E",
7245 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
7246 /* MPC8568 */
7247 POWERPC_DEF_SVR("MPC8568",
7248 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
7249 /* MPC8568E */
7250 POWERPC_DEF_SVR("MPC8568E",
7251 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
7252 /* MPC8572 */
7253 POWERPC_DEF_SVR("MPC8572",
7254 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
7255 /* MPC8572E */
7256 POWERPC_DEF_SVR("MPC8572E",
7257 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
7258 /* e600 family */
7259 /* PowerPC e600 core */
7260 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
7261 /* PowerPC e600 microcontrollers */
7262#if defined (TODO)
7263 /* MPC8610 */
7264 POWERPC_DEF_SVR("MPC8610",
7265 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
7266#endif
7267 /* MPC8641 */
7268 POWERPC_DEF_SVR("MPC8641",
7269 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
7270 /* MPC8641D */
7271 POWERPC_DEF_SVR("MPC8641D",
7272 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 7273 /* 32 bits "classic" PowerPC */
7274 /* PowerPC 6xx family */
7275 /* PowerPC 601 */
80d11f44 7276 POWERPC_DEF("601", CPU_POWERPC_601, 601),
c3e36823 7277 /* PowerPC 601v0 */
80d11f44 7278 POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
c3e36823 7279 /* PowerPC 601v1 */
80d11f44 7280 POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
a750fc0b 7281 /* PowerPC 601v2 */
80d11f44 7282 POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
a750fc0b 7283 /* PowerPC 602 */
80d11f44 7284 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 7285 /* PowerPC 603 */
80d11f44 7286 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 7287 /* Code name for PowerPC 603 */
80d11f44 7288 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
a750fc0b 7289 /* PowerPC 603e */
80d11f44 7290 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 7291 /* Code name for PowerPC 603e */
80d11f44 7292 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 7293 /* PowerPC 603e v1.1 */
80d11f44 7294 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 7295 /* PowerPC 603e v1.2 */
80d11f44 7296 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 7297 /* PowerPC 603e v1.3 */
80d11f44 7298 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 7299 /* PowerPC 603e v1.4 */
80d11f44 7300 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 7301 /* PowerPC 603e v2.2 */
80d11f44 7302 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 7303 /* PowerPC 603e v3 */
80d11f44 7304 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 7305 /* PowerPC 603e v4 */
80d11f44 7306 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 7307 /* PowerPC 603e v4.1 */
80d11f44 7308 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
a750fc0b 7309 /* PowerPC 603e */
80d11f44 7310 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 7311 /* PowerPC 603e7t */
80d11f44 7312 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 7313 /* PowerPC 603e7v */
80d11f44 7314 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 7315 /* Code name for PowerPC 603ev */
80d11f44 7316 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 7317 /* PowerPC 603e7v1 */
80d11f44 7318 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 7319 /* PowerPC 603e7v2 */
80d11f44 7320 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
a750fc0b
JM		 7321 /* PowerPC 603p */
7322 /* to be checked */
80d11f44 7323 POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
a750fc0b 7324 /* PowerPC 603r */
80d11f44 7325 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 7326 /* Code name for PowerPC 603r */
80d11f44 7327 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 7328 /* PowerPC 604 */
80d11f44 7329 POWERPC_DEF("604", CPU_POWERPC_604, 604),
a750fc0b 7330 /* PowerPC 604e */
ee4e83ed 7331 /* XXX: code names "Sirocco" "Mach 5" */
80d11f44 7332 POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
a750fc0b 7333 /* PowerPC 604e v1.0 */
80d11f44 7334 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604),
a750fc0b 7335 /* PowerPC 604e v2.2 */
80d11f44 7336 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604),
a750fc0b 7337 /* PowerPC 604e v2.4 */
80d11f44 7338 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604),
a750fc0b 7339 /* PowerPC 604r */
80d11f44 7340 POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
a750fc0b
JM		 7341#if defined(TODO)
7342 /* PowerPC 604ev */
80d11f44 7343 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
a750fc0b
JM		 7344#endif
7345 /* PowerPC 7xx family */
7346 /* Generic PowerPC 740 (G3) */
80d11f44 7347 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
a750fc0b 7348 /* Generic PowerPC 750 (G3) */
80d11f44 7349 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
a750fc0b 7350 /* Code name for generic PowerPC 740/750 (G3) */
80d11f44 7351 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
ee4e83ed 7352 /* XXX: 750 codename "Typhoon" */
a750fc0b 7353 /* PowerPC 740/750 is also known as G3 */
80d11f44 7354 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
a750fc0b 7355 /* PowerPC 740 v2.0 (G3) */
80d11f44 7356 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0),
a750fc0b 7357 /* PowerPC 750 v2.0 (G3) */
80d11f44 7358 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0),
a750fc0b 7359 /* PowerPC 740 v2.1 (G3) */
80d11f44 7360 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0),
a750fc0b 7361 /* PowerPC 750 v2.1 (G3) */
80d11f44 7362 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0),
a750fc0b 7363 /* PowerPC 740 v2.2 (G3) */
80d11f44 7364 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0),
a750fc0b 7365 /* PowerPC 750 v2.2 (G3) */
80d11f44 7366 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0),
a750fc0b 7367 /* PowerPC 740 v3.0 (G3) */
80d11f44 7368 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0),
a750fc0b 7369 /* PowerPC 750 v3.0 (G3) */
80d11f44 7370 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0),
a750fc0b 7371 /* PowerPC 740 v3.1 (G3) */
80d11f44 7372 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0),
a750fc0b 7373 /* PowerPC 750 v3.1 (G3) */
80d11f44 7374 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0),
a750fc0b 7375 /* PowerPC 740E (G3) */
80d11f44 7376 POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
a750fc0b 7377 /* PowerPC 740P (G3) */
80d11f44 7378 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7379 /* PowerPC 750P (G3) */
80d11f44 7380 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7381 /* Code name for PowerPC 740P/750P (G3) */
80d11f44 7382 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
a750fc0b 7383 /* PowerPC 750CL (G3 embedded) */
80d11f44 7384 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
a750fc0b 7385 /* PowerPC 750CX (G3 embedded) */
80d11f44 7386 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
a750fc0b 7387 /* PowerPC 750CX v2.1 (G3 embedded) */
80d11f44 7388 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0),
a750fc0b 7389 /* PowerPC 750CX v2.2 (G3 embedded) */
80d11f44 7390 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0),
a750fc0b 7391 /* PowerPC 750CXe (G3 embedded) */
80d11f44 7392 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
a750fc0b 7393 /* PowerPC 750CXe v2.1 (G3 embedded) */
80d11f44 7394 POWERPC_DEF("750cxe_v21", CPU_POWERPC_750CXE_v21, 7x0),
a750fc0b 7395 /* PowerPC 750CXe v2.2 (G3 embedded) */
80d11f44 7396 POWERPC_DEF("750cxe_v22", CPU_POWERPC_750CXE_v22, 7x0),
a750fc0b 7397 /* PowerPC 750CXe v2.3 (G3 embedded) */
80d11f44 7398 POWERPC_DEF("750cxe_v23", CPU_POWERPC_750CXE_v23, 7x0),
a750fc0b 7399 /* PowerPC 750CXe v2.4 (G3 embedded) */
80d11f44 7400 POWERPC_DEF("750cxe_v24", CPU_POWERPC_750CXE_v24, 7x0),
a750fc0b 7401 /* PowerPC 750CXe v2.4b (G3 embedded) */
80d11f44 7402 POWERPC_DEF("750cxe_v24b", CPU_POWERPC_750CXE_v24b, 7x0),
a750fc0b 7403 /* PowerPC 750CXe v3.1 (G3 embedded) */
80d11f44 7404 POWERPC_DEF("750cxe_v31", CPU_POWERPC_750CXE_v31, 7x0),
a750fc0b 7405 /* PowerPC 750CXe v3.1b (G3 embedded) */
80d11f44 7406 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
a750fc0b 7407 /* PowerPC 750CXr (G3 embedded) */
80d11f44 7408 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
a750fc0b 7409 /* PowerPC 750E (G3) */
80d11f44 7410 POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
a750fc0b 7411 /* PowerPC 750FL (G3 embedded) */
80d11f44 7412 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 7413 /* PowerPC 750FX (G3 embedded) */
80d11f44 7414 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 7415 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 7416 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 7417 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 7418 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 7419 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 7420 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 7421 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 7422 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 7423 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 7424 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 7425 /* PowerPC 750GL (G3 embedded) */
80d11f44 7426 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
a750fc0b 7427 /* PowerPC 750GX (G3 embedded) */
80d11f44 7428 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
a750fc0b 7429 /* PowerPC 750GX v1.0 (G3 embedded) */
80d11f44 7430 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx),
a750fc0b 7431 /* PowerPC 750GX v1.1 (G3 embedded) */
80d11f44 7432 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx),
a750fc0b 7433 /* PowerPC 750GX v1.2 (G3 embedded) */
80d11f44 7434 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx),
a750fc0b 7435 /* PowerPC 750L (G3 embedded) */
80d11f44 7436 POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
a750fc0b 7437 /* Code name for PowerPC 750L (G3 embedded) */
80d11f44 7438 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
a750fc0b 7439 /* PowerPC 750L v2.2 (G3 embedded) */
80d11f44 7440 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0),
a750fc0b 7441 /* PowerPC 750L v3.0 (G3 embedded) */
80d11f44 7442 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0),
a750fc0b 7443 /* PowerPC 750L v3.2 (G3 embedded) */
80d11f44 7444 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0),
a750fc0b 7445 /* Generic PowerPC 745 */
80d11f44 7446 POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
a750fc0b 7447 /* Generic PowerPC 755 */
80d11f44 7448 POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
a750fc0b 7449 /* Code name for PowerPC 745/755 */
80d11f44 7450 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
a750fc0b 7451 /* PowerPC 745 v1.0 */
80d11f44 7452 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5),
a750fc0b 7453 /* PowerPC 755 v1.0 */
80d11f44 7454 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5),
a750fc0b 7455 /* PowerPC 745 v1.1 */
80d11f44 7456 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5),
a750fc0b 7457 /* PowerPC 755 v1.1 */
80d11f44 7458 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5),
a750fc0b 7459 /* PowerPC 745 v2.0 */
80d11f44 7460 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5),
a750fc0b 7461 /* PowerPC 755 v2.0 */
80d11f44 7462 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5),
a750fc0b 7463 /* PowerPC 745 v2.1 */
80d11f44 7464 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5),
a750fc0b 7465 /* PowerPC 755 v2.1 */
80d11f44 7466 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5),
a750fc0b 7467 /* PowerPC 745 v2.2 */
80d11f44 7468 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5),
a750fc0b 7469 /* PowerPC 755 v2.2 */
80d11f44 7470 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5),
a750fc0b 7471 /* PowerPC 745 v2.3 */
80d11f44 7472 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5),
a750fc0b 7473 /* PowerPC 755 v2.3 */
80d11f44 7474 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5),
a750fc0b 7475 /* PowerPC 745 v2.4 */
80d11f44 7476 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5),
a750fc0b 7477 /* PowerPC 755 v2.4 */
80d11f44 7478 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5),
a750fc0b 7479 /* PowerPC 745 v2.5 */
80d11f44 7480 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5),
a750fc0b 7481 /* PowerPC 755 v2.5 */
80d11f44 7482 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5),
a750fc0b 7483 /* PowerPC 745 v2.6 */
80d11f44 7484 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5),
a750fc0b 7485 /* PowerPC 755 v2.6 */
80d11f44 7486 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5),
a750fc0b 7487 /* PowerPC 745 v2.7 */
80d11f44 7488 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5),
a750fc0b 7489 /* PowerPC 755 v2.7 */
80d11f44 7490 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5),
a750fc0b 7491 /* PowerPC 745 v2.8 */
80d11f44 7492 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5),
a750fc0b 7493 /* PowerPC 755 v2.8 */
80d11f44 7494 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5),
a750fc0b
JM		 7495#if defined (TODO)
7496 /* PowerPC 745P (G3) */
80d11f44 7497 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
a750fc0b 7498 /* PowerPC 755P (G3) */
80d11f44 7499 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
a750fc0b
JM		 7500#endif
7501 /* PowerPC 74xx family */
7502 /* PowerPC 7400 (G4) */
80d11f44 7503 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 7504 /* Code name for PowerPC 7400 */
80d11f44 7505 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 7506 /* PowerPC 74xx is also well known as G4 */
80d11f44 7507 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 7508 /* PowerPC 7400 v1.0 (G4) */
80d11f44 7509 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 7510 /* PowerPC 7400 v1.1 (G4) */
80d11f44 7511 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 7512 /* PowerPC 7400 v2.0 (G4) */
80d11f44 7513 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
a750fc0b 7514 /* PowerPC 7400 v2.2 (G4) */
80d11f44 7515 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 7516 /* PowerPC 7400 v2.6 (G4) */
80d11f44 7517 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 7518 /* PowerPC 7400 v2.7 (G4) */
80d11f44 7519 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 7520 /* PowerPC 7400 v2.8 (G4) */
80d11f44 7521 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 7522 /* PowerPC 7400 v2.9 (G4) */
80d11f44 7523 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 7524 /* PowerPC 7410 (G4) */
80d11f44 7525 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 7526 /* Code name for PowerPC 7410 */
80d11f44 7527 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 7528 /* PowerPC 7410 v1.0 (G4) */
80d11f44 7529 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 7530 /* PowerPC 7410 v1.1 (G4) */
80d11f44 7531 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 7532 /* PowerPC 7410 v1.2 (G4) */
80d11f44 7533 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 7534 /* PowerPC 7410 v1.3 (G4) */
80d11f44 7535 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 7536 /* PowerPC 7410 v1.4 (G4) */
80d11f44 7537 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 7538 /* PowerPC 7448 (G4) */
80d11f44 7539 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 7540 /* PowerPC 7448 v1.0 (G4) */
80d11f44 7541 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 7542 /* PowerPC 7448 v1.1 (G4) */
80d11f44 7543 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 7544 /* PowerPC 7448 v2.0 (G4) */
80d11f44 7545 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 7546 /* PowerPC 7448 v2.1 (G4) */
80d11f44 7547 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 7548 /* PowerPC 7450 (G4) */
80d11f44 7549 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 7550 /* Code name for PowerPC 7450 */
80d11f44 7551 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 7552 /* PowerPC 7450 v1.0 (G4) */
80d11f44 7553 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 7554 /* PowerPC 7450 v1.1 (G4) */
80d11f44 7555 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 7556 /* PowerPC 7450 v1.2 (G4) */
80d11f44 7557 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 7558 /* PowerPC 7450 v2.0 (G4) */
80d11f44 7559 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 7560 /* PowerPC 7450 v2.1 (G4) */
80d11f44 7561 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 7562 /* PowerPC 7441 (G4) */
80d11f44 7563 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 7564 /* PowerPC 7451 (G4) */
80d11f44 7565 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
a750fc0b 7566 /* PowerPC 7441g (G4) */
80d11f44 7567 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
a750fc0b 7568 /* PowerPC 7451g (G4) */
80d11f44 7569 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
a750fc0b 7570 /* PowerPC 7445 (G4) */
80d11f44 7571 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 7572 /* PowerPC 7455 (G4) */
80d11f44 7573 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 7574 /* Code name for PowerPC 7445/7455 */
80d11f44 7575 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 7576 /* PowerPC 7445 v1.0 (G4) */
80d11f44 7577 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 7578 /* PowerPC 7455 v1.0 (G4) */
80d11f44 7579 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 7580 /* PowerPC 7445 v2.1 (G4) */
80d11f44 7581 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 7582 /* PowerPC 7455 v2.1 (G4) */
80d11f44 7583 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 7584 /* PowerPC 7445 v3.2 (G4) */
80d11f44 7585 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 7586 /* PowerPC 7455 v3.2 (G4) */
80d11f44 7587 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 7588 /* PowerPC 7445 v3.3 (G4) */
80d11f44 7589 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 7590 /* PowerPC 7455 v3.3 (G4) */
80d11f44 7591 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 7592 /* PowerPC 7445 v3.4 (G4) */
80d11f44 7593 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 7594 /* PowerPC 7455 v3.4 (G4) */
80d11f44 7595 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 7596 /* PowerPC 7447 (G4) */
80d11f44 7597 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 7598 /* PowerPC 7457 (G4) */
80d11f44 7599 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 7600 /* Code name for PowerPC 7447/7457 */
80d11f44 7601 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 7602 /* PowerPC 7447 v1.0 (G4) */
80d11f44 7603 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 7604 /* PowerPC 7457 v1.0 (G4) */
80d11f44 7605 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 7606 /* Code name for PowerPC 7447A/7457A */
80d11f44 7607 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 7608 /* PowerPC 7447 v1.1 (G4) */
80d11f44 7609 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 7610 /* PowerPC 7457 v1.1 (G4) */
80d11f44 7611 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 7612 /* PowerPC 7447 v1.2 (G4) */
80d11f44 7613 POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
a750fc0b 7614 /* PowerPC 7457 v1.2 (G4) */
80d11f44 7615 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
a750fc0b
JM		 7616 /* 64 bits PowerPC */
7617#if defined (TARGET_PPC64)
a750fc0b 7618 /* PowerPC 620 */
ee4e83ed 7619 /* XXX: code name "Trident" */
80d11f44 7620 POWERPC_DEF("620", CPU_POWERPC_620, 620),
3fc6c082 7621#if defined (TODO)
a750fc0b 7622 /* PowerPC 630 (POWER3) */
ee4e83ed 7623 /* XXX: code names: "Boxer" "Dino" */
80d11f44
JM		 7624 POWERPC_DEF("630", CPU_POWERPC_630, 630),
7625 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
a750fc0b 7626#endif
3a607854 7627#if defined (TODO)
a750fc0b 7628 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 7629 POWERPC_DEF("631", CPU_POWERPC_631, 631),
7630 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 7631#endif
7632#if defined (TODO)
a750fc0b 7633 /* POWER4 */
80d11f44 7634 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 7635#endif
3a607854 7636#if defined (TODO)
a750fc0b 7637 /* POWER4p */
80d11f44 7638 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 7639#endif
2662a059 7640#if defined (TODO)
a750fc0b 7641 /* POWER5 */
80d11f44 7642 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 7643 /* POWER5GR */
80d11f44 7644 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 7645#endif
3a607854 7646#if defined (TODO)
a750fc0b 7647 /* POWER5+ */
80d11f44 7648 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 7649 /* POWER5GS */
80d11f44 7650 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 7651#endif
2662a059 7652#if defined (TODO)
a750fc0b 7653 /* POWER6 */
80d11f44 7654 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 7655 /* POWER6 running in POWER5 mode */
80d11f44 7656 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 7657 /* POWER6A */
80d11f44 7658 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 7659#endif
a750fc0b 7660 /* PowerPC 970 */
80d11f44 7661 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 7662 /* PowerPC 970FX (G5) */
80d11f44 7663 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 7664 /* PowerPC 970FX v1.0 (G5) */
80d11f44 7665 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 7666 /* PowerPC 970FX v2.0 (G5) */
80d11f44 7667 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 7668 /* PowerPC 970FX v2.1 (G5) */
80d11f44 7669 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 7670 /* PowerPC 970FX v3.0 (G5) */
80d11f44 7671 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 7672 /* PowerPC 970FX v3.1 (G5) */
80d11f44 7673 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 7674 /* PowerPC 970GX (G5) */
80d11f44 7675 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 7676 /* PowerPC 970MP */
80d11f44 7677 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 7678 /* PowerPC 970MP v1.0 */
80d11f44 7679 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 7680 /* PowerPC 970MP v1.1 */
80d11f44 7681 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 7682#if defined (TODO)
a750fc0b 7683 /* PowerPC Cell */
80d11f44 7684 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 7685#endif
7686#if defined (TODO)
a750fc0b 7687 /* PowerPC Cell v1.0 */
80d11f44 7688 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 7689#endif
7690#if defined (TODO)
a750fc0b 7691 /* PowerPC Cell v2.0 */
80d11f44 7692 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 7693#endif
7694#if defined (TODO)
a750fc0b 7695 /* PowerPC Cell v3.0 */
80d11f44 7696 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 7697#endif
3a607854 7698#if defined (TODO)
a750fc0b 7699 /* PowerPC Cell v3.1 */
80d11f44 7700 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 7701#endif
7702#if defined (TODO)
a750fc0b 7703 /* PowerPC Cell v3.2 */
80d11f44 7704 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 7705#endif
7706#if defined (TODO)
a750fc0b
JM		 7707 /* RS64 (Apache/A35) */
7708 /* This one seems to support the whole POWER2 instruction set
7709 * and the PowerPC 64 one.
7710 */
7711 /* What about A10 & A30 ? */
80d11f44
JM		 7712 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
7713 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
7714 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 7715#endif
7716#if defined (TODO)
a750fc0b 7717 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 7718 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
7719 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
7720 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 7721#endif
7722#if defined (TODO)
a750fc0b 7723 /* RS64-III (Pulsar) */
80d11f44
JM		 7724 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
7725 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 7726#endif
7727#if defined (TODO)
a750fc0b 7728 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 7729 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
7730 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
7731 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
7732 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 7733#endif
a750fc0b
JM		 7734#endif /* defined (TARGET_PPC64) */
7735 /* POWER */
3fc6c082 7736#if defined (TODO)
a750fc0b 7737 /* Original POWER */
80d11f44
JM		 7738 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
7739 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
7740 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
7741 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
7742 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 7743#endif
7744#if defined (TODO)
a750fc0b 7745 /* POWER2 */
80d11f44
JM		 7746 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
7747 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
7748 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 7749#endif
7750 /* PA semi cores */
7751#if defined (TODO)
7752 /* PA PA6T */
80d11f44 7753 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 7754#endif
7755 /* Generic PowerPCs */
7756#if defined (TARGET_PPC64)
80d11f44 7757 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 7758#endif
80d11f44
JM		 7759 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
7760 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 7761 /* Fallback */
80d11f44 7762 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 7763};
7764
7765/*****************************************************************************/
7766/* Generic CPU instanciation routine */
aaed909a 7767static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 7768{
7769#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 7770 int i;
7771
a750fc0b 7772 env->irq_inputs = NULL;
e1833e1f
JM		 7773 /* Set all exception vectors to an invalid address */
7774 for (i = 0; i < POWERPC_EXCP_NB; i++)
7775 env->excp_vectors[i] = (target_ulong)(-1ULL);
7776 env->excp_prefix = 0x00000000;
7777 env->ivor_mask = 0x00000000;
7778 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 7779 /* Default MMU definitions */
7780 env->nb_BATs = 0;
7781 env->nb_tlb = 0;
7782 env->nb_ways = 0;
f2e63a42 7783#endif
a750fc0b
JM		 7784 /* Register SPR common to all PowerPC implementations */
7785 gen_spr_generic(env);
7786 spr_register(env, SPR_PVR, "PVR",
7787 SPR_NOACCESS, SPR_NOACCESS,
7788 &spr_read_generic, SPR_NOACCESS,
7789 def->pvr);
80d11f44
JM		 7790 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7791 if (def->svr != POWERPC_SVR_NONE) {
7792 if (def->svr & POWERPC_SVR_E500) {
7793 spr_register(env, SPR_E500_SVR, "SVR",
7794 SPR_NOACCESS, SPR_NOACCESS,
7795 &spr_read_generic, SPR_NOACCESS,
7796 def->svr & ~POWERPC_SVR_E500);
7797 } else {
7798 spr_register(env, SPR_SVR, "SVR",
7799 SPR_NOACCESS, SPR_NOACCESS,
7800 &spr_read_generic, SPR_NOACCESS,
7801 def->svr);
7802 }
7803 }
a750fc0b
JM		 7804 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7805 (*def->init_proc)(env);
25ba3a68
JM		 7806 /* MSR bits & flags consistency checks */
7807 if (env->msr_mask & (1 << 25)) {
7808 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7809 case POWERPC_FLAG_SPE:
7810 case POWERPC_FLAG_VRE:
7811 break;
7812 default:
7813 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7814 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7815 exit(1);
7816 }
7817 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7818 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7819 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7820 exit(1);
7821 }
7822 if (env->msr_mask & (1 << 17)) {
7823 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7824 case POWERPC_FLAG_TGPR:
7825 case POWERPC_FLAG_CE:
7826 break;
7827 default:
7828 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7829 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7830 exit(1);
7831 }
7832 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7833 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7834 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7835 exit(1);
7836 }
7837 if (env->msr_mask & (1 << 10)) {
7838 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7839 POWERPC_FLAG_UBLE)) {
7840 case POWERPC_FLAG_SE:
7841 case POWERPC_FLAG_DWE:
7842 case POWERPC_FLAG_UBLE:
7843 break;
7844 default:
7845 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7846 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7847 "POWERPC_FLAG_UBLE\n");
7848 exit(1);
7849 }
7850 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7851 POWERPC_FLAG_UBLE)) {
7852 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7853 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7854 "POWERPC_FLAG_UBLE\n");
7855 exit(1);
7856 }
7857 if (env->msr_mask & (1 << 9)) {
7858 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7859 case POWERPC_FLAG_BE:
7860 case POWERPC_FLAG_DE:
7861 break;
7862 default:
7863 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7864 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7865 exit(1);
7866 }
7867 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7868 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7869 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7870 exit(1);
7871 }
7872 if (env->msr_mask & (1 << 2)) {
7873 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7874 case POWERPC_FLAG_PX:
7875 case POWERPC_FLAG_PMM:
7876 break;
7877 default:
7878 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7879 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7880 exit(1);
7881 }
7882 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7883 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7884 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7885 exit(1);
7886 }
a750fc0b 7887 /* Allocate TLBs buffer when needed */
f2e63a42 7888#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 7889 if (env->nb_tlb != 0) {
7890 int nb_tlb = env->nb_tlb;
7891 if (env->id_tlbs != 0)
7892 nb_tlb *= 2;
7893 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
7894 /* Pre-compute some useful values */
7895 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7896 }
a750fc0b
JM		 7897 if (env->irq_inputs == NULL) {
7898 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7899 " Attempt Qemu to crash very soon !\n");
7900 }
7901#endif
2f462816
JM		 7902 if (env->check_pow == NULL) {
7903 fprintf(stderr, "WARNING: no power management check handler "
7904 "registered.\n"
7905 " Attempt Qemu to crash very soon !\n");
7906 }
a750fc0b
JM		 7907}
7908
7909#if defined(PPC_DUMP_CPU)
7910static void dump_ppc_sprs (CPUPPCState *env)
7911{
7912 ppc_spr_t *spr;
7913#if !defined(CONFIG_USER_ONLY)
7914 uint32_t sr, sw;
7915#endif
7916 uint32_t ur, uw;
7917 int i, j, n;
7918
7919 printf("Special purpose registers:\n");
7920 for (i = 0; i < 32; i++) {
7921 for (j = 0; j < 32; j++) {
7922 n = (i << 5) | j;
7923 spr = &env->spr_cb[n];
7924 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7925 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7926#if !defined(CONFIG_USER_ONLY)
7927 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7928 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7929 if (sw || sr || uw || ur) {
7930 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7931 (i << 5) | j, (i << 5) | j, spr->name,
7932 sw ? 'w' : '-', sr ? 'r' : '-',
7933 uw ? 'w' : '-', ur ? 'r' : '-');
7934 }
7935#else
7936 if (uw || ur) {
7937 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7938 (i << 5) | j, (i << 5) | j, spr->name,
7939 uw ? 'w' : '-', ur ? 'r' : '-');
7940 }
7941#endif
7942 }
7943 }
7944 fflush(stdout);
7945 fflush(stderr);
7946}
7947#endif
7948
7949/*****************************************************************************/
7950#include <stdlib.h>
7951#include <string.h>
7952
7953int fflush (FILE *stream);
7954
7955/* Opcode types */
7956enum {
7957 PPC_DIRECT = 0, /* Opcode routine */
7958 PPC_INDIRECT = 1, /* Indirect opcode table */
7959};
7960
7961static inline int is_indirect_opcode (void *handler)
7962{
7963 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
7964}
7965
7966static inline opc_handler_t **ind_table(void *handler)
7967{
7968 return (opc_handler_t **)((unsigned long)handler & ~3);
7969}
7970
7971/* Instruction table creation */
7972/* Opcodes tables creation */
7973static void fill_new_table (opc_handler_t **table, int len)
7974{
7975 int i;
7976
7977 for (i = 0; i < len; i++)
7978 table[i] = &invalid_handler;
7979}
7980
7981static int create_new_table (opc_handler_t **table, unsigned char idx)
7982{
7983 opc_handler_t **tmp;
7984
7985 tmp = malloc(0x20 * sizeof(opc_handler_t));
7986 if (tmp == NULL)
7987 return -1;
7988 fill_new_table(tmp, 0x20);
7989 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
7990
7991 return 0;
7992}
7993
7994static int insert_in_table (opc_handler_t **table, unsigned char idx,
7995 opc_handler_t *handler)
7996{
7997 if (table[idx] != &invalid_handler)
7998 return -1;
7999 table[idx] = handler;
8000
8001 return 0;
8002}
8003
8004static int register_direct_insn (opc_handler_t **ppc_opcodes,
8005 unsigned char idx, opc_handler_t *handler)
8006{
8007 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8008 printf("*** ERROR: opcode %02x already assigned in main "
8009 "opcode table\n", idx);
8010 return -1;
8011 }
8012
8013 return 0;
8014}
8015
8016static int register_ind_in_table (opc_handler_t **table,
8017 unsigned char idx1, unsigned char idx2,
8018 opc_handler_t *handler)
8019{
8020 if (table[idx1] == &invalid_handler) {
8021 if (create_new_table(table, idx1) < 0) {
8022 printf("*** ERROR: unable to create indirect table "
8023 "idx=%02x\n", idx1);
8024 return -1;
8025 }
8026 } else {
8027 if (!is_indirect_opcode(table[idx1])) {
8028 printf("*** ERROR: idx %02x already assigned to a direct "
8029 "opcode\n", idx1);
8030 return -1;
8031 }
3a607854 8032 }
a750fc0b
JM		 8033 if (handler != NULL &&
8034 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8035 printf("*** ERROR: opcode %02x already assigned in "
8036 "opcode table %02x\n", idx2, idx1);
8037 return -1;
3a607854 8038 }
a750fc0b
JM		 8039
8040 return 0;
8041}
8042
8043static int register_ind_insn (opc_handler_t **ppc_opcodes,
8044 unsigned char idx1, unsigned char idx2,
8045 opc_handler_t *handler)
8046{
8047 int ret;
8048
8049 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8050
8051 return ret;
8052}
8053
8054static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8055 unsigned char idx1, unsigned char idx2,
8056 unsigned char idx3, opc_handler_t *handler)
8057{
8058 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8059 printf("*** ERROR: unable to join indirect table idx "
8060 "[%02x-%02x]\n", idx1, idx2);
8061 return -1;
8062 }
8063 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8064 handler) < 0) {
8065 printf("*** ERROR: unable to insert opcode "
8066 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8067 return -1;
8068 }
8069
8070 return 0;
8071}
8072
8073static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8074{
8075 if (insn->opc2 != 0xFF) {
8076 if (insn->opc3 != 0xFF) {
8077 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8078 insn->opc3, &insn->handler) < 0)
8079 return -1;
8080 } else {
8081 if (register_ind_insn(ppc_opcodes, insn->opc1,
8082 insn->opc2, &insn->handler) < 0)
8083 return -1;
8084 }
8085 } else {
8086 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8087 return -1;
8088 }
8089
8090 return 0;
8091}
8092
8093static int test_opcode_table (opc_handler_t **table, int len)
8094{
8095 int i, count, tmp;
8096
8097 for (i = 0, count = 0; i < len; i++) {
8098 /* Consistency fixup */
8099 if (table[i] == NULL)
8100 table[i] = &invalid_handler;
8101 if (table[i] != &invalid_handler) {
8102 if (is_indirect_opcode(table[i])) {
8103 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8104 if (tmp == 0) {
8105 free(table[i]);
8106 table[i] = &invalid_handler;
8107 } else {
8108 count++;
8109 }
8110 } else {
8111 count++;
8112 }
8113 }
8114 }
8115
8116 return count;
8117}
8118
8119static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8120{
8121 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8122 printf("*** WARNING: no opcode defined !\n");
8123}
8124
8125/*****************************************************************************/
aaed909a 8126static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8127{
8128 opcode_t *opc, *start, *end;
8129
8130 fill_new_table(env->opcodes, 0x40);
8131 if (&opc_start < &opc_end) {
8132 start = &opc_start;
8133 end = &opc_end;
8134 } else {
8135 start = &opc_end;
8136 end = &opc_start;
8137 }
8138 for (opc = start + 1; opc != end; opc++) {
8139 if ((opc->handler.type & def->insns_flags) != 0) {
8140 if (register_insn(env->opcodes, opc) < 0) {
8141 printf("*** ERROR initializing PowerPC instruction "
8142 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
8143 opc->opc3);
8144 return -1;
8145 }
8146 }
8147 }
8148 fix_opcode_tables(env->opcodes);
8149 fflush(stdout);
8150 fflush(stderr);
8151
8152 return 0;
8153}
8154
8155#if defined(PPC_DUMP_CPU)
25ba3a68 8156static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 8157{
8158 opc_handler_t **table, *handler;
8159 uint8_t opc1, opc2, opc3;
8160
8161 printf("Instructions set:\n");
8162 /* opc1 is 6 bits long */
8163 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8164 table = env->opcodes;
8165 handler = table[opc1];
8166 if (is_indirect_opcode(handler)) {
8167 /* opc2 is 5 bits long */
8168 for (opc2 = 0; opc2 < 0x20; opc2++) {
8169 table = env->opcodes;
8170 handler = env->opcodes[opc1];
8171 table = ind_table(handler);
8172 handler = table[opc2];
8173 if (is_indirect_opcode(handler)) {
8174 table = ind_table(handler);
8175 /* opc3 is 5 bits long */
8176 for (opc3 = 0; opc3 < 0x20; opc3++) {
8177 handler = table[opc3];
8178 if (handler->handler != &gen_invalid) {
8179 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
8180 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
8181 handler->oname);
8182 }
8183 }
8184 } else {
8185 if (handler->handler != &gen_invalid) {
8186 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8187 opc1, opc2, opc1, opc2, handler->oname);
8188 }
8189 }
8190 }
8191 } else {
8192 if (handler->handler != &gen_invalid) {
8193 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8194 opc1, opc1, handler->oname);
8195 }
8196 }
8197 }
8198}
3a607854 8199#endif
a750fc0b 8200
aaed909a 8201int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8202{
8203 env->msr_mask = def->msr_mask;
8204 env->mmu_model = def->mmu_model;
8205 env->excp_model = def->excp_model;
8206 env->bus_model = def->bus_model;
d26bfc9a 8207 env->flags = def->flags;
237c0af0 8208 env->bfd_mach = def->bfd_mach;
2f462816 8209 env->check_pow = def->check_pow;
a750fc0b
JM		 8210 if (create_ppc_opcodes(env, def) < 0)
8211 return -1;
8212 init_ppc_proc(env, def);
8213#if defined(PPC_DUMP_CPU)
3a607854 8214 {
a750fc0b
JM		 8215 const unsigned char *mmu_model, *excp_model, *bus_model;
8216 switch (env->mmu_model) {
8217 case POWERPC_MMU_32B:
8218 mmu_model = "PowerPC 32";
8219 break;
a750fc0b
JM		 8220 case POWERPC_MMU_SOFT_6xx:
8221 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8222 break;
8223 case POWERPC_MMU_SOFT_74xx:
8224 mmu_model = "PowerPC 74xx with software driven TLBs";
8225 break;
8226 case POWERPC_MMU_SOFT_4xx:
8227 mmu_model = "PowerPC 4xx with software driven TLBs";
8228 break;
8229 case POWERPC_MMU_SOFT_4xx_Z:
8230 mmu_model = "PowerPC 4xx with software driven TLBs "
8231 "and zones protections";
8232 break;
b4095fed
JM		 8233 case POWERPC_MMU_REAL:
8234 mmu_model = "PowerPC real mode only";
8235 break;
8236 case POWERPC_MMU_MPC8xx:
8237 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 8238 break;
8239 case POWERPC_MMU_BOOKE:
8240 mmu_model = "PowerPC BookE";
8241 break;
8242 case POWERPC_MMU_BOOKE_FSL:
8243 mmu_model = "PowerPC BookE FSL";
8244 break;
b4095fed
JM		 8245 case POWERPC_MMU_601:
8246 mmu_model = "PowerPC 601";
8247 break;
00af685f
JM		 8248#if defined (TARGET_PPC64)
8249 case POWERPC_MMU_64B:
8250 mmu_model = "PowerPC 64";
8251 break;
00af685f 8252#endif
a750fc0b
JM		 8253 default:
8254 mmu_model = "Unknown or invalid";
8255 break;
8256 }
8257 switch (env->excp_model) {
8258 case POWERPC_EXCP_STD:
8259 excp_model = "PowerPC";
8260 break;
8261 case POWERPC_EXCP_40x:
8262 excp_model = "PowerPC 40x";
8263 break;
8264 case POWERPC_EXCP_601:
8265 excp_model = "PowerPC 601";
8266 break;
8267 case POWERPC_EXCP_602:
8268 excp_model = "PowerPC 602";
8269 break;
8270 case POWERPC_EXCP_603:
8271 excp_model = "PowerPC 603";
8272 break;
8273 case POWERPC_EXCP_603E:
8274 excp_model = "PowerPC 603e";
8275 break;
8276 case POWERPC_EXCP_604:
8277 excp_model = "PowerPC 604";
8278 break;
8279 case POWERPC_EXCP_7x0:
8280 excp_model = "PowerPC 740/750";
8281 break;
8282 case POWERPC_EXCP_7x5:
8283 excp_model = "PowerPC 745/755";
8284 break;
8285 case POWERPC_EXCP_74xx:
8286 excp_model = "PowerPC 74xx";
8287 break;
a750fc0b
JM		 8288 case POWERPC_EXCP_BOOKE:
8289 excp_model = "PowerPC BookE";
8290 break;
00af685f
JM		 8291#if defined (TARGET_PPC64)
8292 case POWERPC_EXCP_970:
8293 excp_model = "PowerPC 970";
8294 break;
8295#endif
a750fc0b
JM		 8296 default:
8297 excp_model = "Unknown or invalid";
8298 break;
8299 }
8300 switch (env->bus_model) {
8301 case PPC_FLAGS_INPUT_6xx:
8302 bus_model = "PowerPC 6xx";
8303 break;
8304 case PPC_FLAGS_INPUT_BookE:
8305 bus_model = "PowerPC BookE";
8306 break;
8307 case PPC_FLAGS_INPUT_405:
8308 bus_model = "PowerPC 405";
8309 break;
a750fc0b
JM		 8310 case PPC_FLAGS_INPUT_401:
8311 bus_model = "PowerPC 401/403";
8312 break;
b4095fed
JM		 8313 case PPC_FLAGS_INPUT_RCPU:
8314 bus_model = "RCPU / MPC8xx";
8315 break;
00af685f
JM		 8316#if defined (TARGET_PPC64)
8317 case PPC_FLAGS_INPUT_970:
8318 bus_model = "PowerPC 970";
8319 break;
8320#endif
a750fc0b
JM		 8321 default:
8322 bus_model = "Unknown or invalid";
8323 break;
8324 }
8325 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8326 " MMU model : %s\n",
8327 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 8328#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8329 if (env->tlb != NULL) {
8330 printf(" %d %s TLB in %d ways\n",
8331 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8332 env->nb_ways);
8333 }
f2e63a42 8334#endif
a750fc0b
JM		 8335 printf(" Exceptions model : %s\n"
8336 " Bus model : %s\n",
8337 excp_model, bus_model);
25ba3a68
JM		 8338 printf(" MSR features :\n");
8339 if (env->flags & POWERPC_FLAG_SPE)
8340 printf(" signal processing engine enable"
8341 "\n");
8342 else if (env->flags & POWERPC_FLAG_VRE)
8343 printf(" vector processor enable\n");
8344 if (env->flags & POWERPC_FLAG_TGPR)
8345 printf(" temporary GPRs\n");
8346 else if (env->flags & POWERPC_FLAG_CE)
8347 printf(" critical input enable\n");
8348 if (env->flags & POWERPC_FLAG_SE)
8349 printf(" single-step trace mode\n");
8350 else if (env->flags & POWERPC_FLAG_DWE)
8351 printf(" debug wait enable\n");
8352 else if (env->flags & POWERPC_FLAG_UBLE)
8353 printf(" user BTB lock enable\n");
8354 if (env->flags & POWERPC_FLAG_BE)
8355 printf(" branch-step trace mode\n");
8356 else if (env->flags & POWERPC_FLAG_DE)
8357 printf(" debug interrupt enable\n");
8358 if (env->flags & POWERPC_FLAG_PX)
8359 printf(" inclusive protection\n");
8360 else if (env->flags & POWERPC_FLAG_PMM)
8361 printf(" performance monitor mark\n");
8362 if (env->flags == POWERPC_FLAG_NONE)
8363 printf(" none\n");
a750fc0b
JM		 8364 }
8365 dump_ppc_insns(env);
8366 dump_ppc_sprs(env);
8367 fflush(stdout);
3a607854 8368#endif
a750fc0b
JM		 8369
8370 return 0;
8371}
3fc6c082 8372
ee4e83ed 8373static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 8374{
ee4e83ed
JM		 8375 const ppc_def_t *ret;
8376 uint32_t pvr_rev;
8377 int i, best, match, best_match, max;
3fc6c082 8378
ee4e83ed 8379 ret = NULL;
068abdc8 8380 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
ee4e83ed
JM		 8381 best = -1;
8382 pvr_rev = pvr & 0xFFFF;
8383 /* We want all specified bits to match */
8384 best_match = 32 - ctz32(pvr_rev);
068abdc8 8385 for (i = 0; i < max; i++) {
ee4e83ed
JM		 8386 /* We check that the 16 higher bits are the same to ensure the CPU
8387 * model will be the choosen one.
8388 */
8389 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
8390 /* We want as much as possible of the low-level 16 bits
8391 * to be the same but we allow inexact matches.
8392 */
8393 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
8394 /* We check '>=' instead of '>' because the PPC_defs table
8395 * is ordered by increasing revision.
8396 * Then, we will match the higher revision compatible
8397 * with the requested PVR
8398 */
8399 if (match >= best_match) {
8400 best = i;
8401 best_match = match;
8402 }
3fc6c082
FB		 8403 }
8404 }
ee4e83ed
JM		 8405 if (best != -1)
8406 ret = &ppc_defs[best];
8407
8408 return ret;
3fc6c082
FB		 8409}
8410
ee4e83ed 8411#include <ctype.h>
3fc6c082 8412
ee4e83ed
JM		 8413const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
8414{
8415 const ppc_def_t *ret;
8416 const unsigned char *p;
8417 int i, max, len;
8418
8419 /* Check if the given name is a PVR */
8420 len = strlen(name);
8421 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8422 p = name + 2;
8423 goto check_pvr;
8424 } else if (len == 8) {
8425 p = name;
8426 check_pvr:
8427 for (i = 0; i < 8; i++) {
8428 if (!isxdigit(*p++))
8429 break;
8430 }
8431 if (i == 8)
8432 return ppc_find_by_pvr(strtoul(name, NULL, 16));
8433 }
8434 ret = NULL;
068abdc8
JM		 8435 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
8436 for (i = 0; i < max; i++) {
ee4e83ed
JM		 8437 if (strcasecmp(name, ppc_defs[i].name) == 0) {
8438 ret = &ppc_defs[i];
8439 break;
3fc6c082
FB		 8440 }
8441 }
ee4e83ed
JM		 8442
8443 return ret;
3fc6c082
FB		 8444}
8445
8446void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
8447{
068abdc8 8448 int i, max;
3fc6c082 8449
068abdc8
JM		 8450 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
8451 for (i = 0; i < max; i++) {
a750fc0b
JM		 8452 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
8453 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 8454 }
8455}
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