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Commit | Line | Data |
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3fc6c082 FB |
1 | /* |
2 | * PowerPC CPU initialization for qemu. | |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
3fc6c082 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
3fc6c082 FB |
18 | */ |
19 | ||
20 | /* A lot of PowerPC definition have been included here. | |
21 | * Most of them are not usable for now but have been kept | |
22 | * inside "#if defined(TODO) ... #endif" statements to make tests easier. | |
23 | */ | |
24 | ||
237c0af0 | 25 | #include "dis-asm.h" |
4e47ea67 | 26 | #include "gdbstub.h" |
237c0af0 | 27 | |
3fc6c082 FB |
28 | //#define PPC_DUMP_CPU |
29 | //#define PPC_DEBUG_SPR | |
80d11f44 JM |
30 | //#define PPC_DUMP_SPR_ACCESSES |
31 | #if defined(CONFIG_USER_ONLY) | |
32 | #define TODO_USER_ONLY 1 | |
33 | #endif | |
3fc6c082 FB |
34 | |
35 | struct ppc_def_t { | |
b55266b5 | 36 | const char *name; |
3fc6c082 | 37 | uint32_t pvr; |
80d11f44 | 38 | uint32_t svr; |
0487d6a8 | 39 | uint64_t insns_flags; |
3fc6c082 | 40 | uint64_t msr_mask; |
7820dbf3 JM |
41 | powerpc_mmu_t mmu_model; |
42 | powerpc_excp_t excp_model; | |
43 | powerpc_input_t bus_model; | |
d26bfc9a | 44 | uint32_t flags; |
237c0af0 | 45 | int bfd_mach; |
a750fc0b | 46 | void (*init_proc)(CPUPPCState *env); |
4c1b1bfe | 47 | int (*check_pow)(CPUPPCState *env); |
3fc6c082 FB |
48 | }; |
49 | ||
e9df014c JM |
50 | /* For user-mode emulation, we don't emulate any IRQ controller */ |
51 | #if defined(CONFIG_USER_ONLY) | |
a750fc0b JM |
52 | #define PPC_IRQ_INIT_FN(name) \ |
53 | static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ | |
54 | { \ | |
e9df014c JM |
55 | } |
56 | #else | |
a750fc0b | 57 | #define PPC_IRQ_INIT_FN(name) \ |
e9df014c JM |
58 | void glue(glue(ppc, name),_irq_init) (CPUPPCState *env); |
59 | #endif | |
a750fc0b | 60 | |
4e290a0b | 61 | PPC_IRQ_INIT_FN(40x); |
e9df014c | 62 | PPC_IRQ_INIT_FN(6xx); |
d0dfae6e | 63 | PPC_IRQ_INIT_FN(970); |
9fdc60bf | 64 | PPC_IRQ_INIT_FN(e500); |
e9df014c | 65 | |
3fc6c082 FB |
66 | /* Generic callbacks: |
67 | * do nothing but store/retrieve spr value | |
68 | */ | |
45d827d2 | 69 | static void spr_read_generic (void *opaque, int gprn, int sprn) |
a496775f | 70 | { |
45d827d2 AJ |
71 | gen_load_spr(cpu_gpr[gprn], sprn); |
72 | #ifdef PPC_DUMP_SPR_ACCESSES | |
73 | { | |
74 | TCGv t0 = tcg_const_i32(sprn); | |
75 | gen_helper_load_dump_spr(t0); | |
76 | tcg_temp_free_i32(t0); | |
77 | } | |
78 | #endif | |
a496775f JM |
79 | } |
80 | ||
45d827d2 | 81 | static void spr_write_generic (void *opaque, int sprn, int gprn) |
a496775f | 82 | { |
45d827d2 AJ |
83 | gen_store_spr(sprn, cpu_gpr[gprn]); |
84 | #ifdef PPC_DUMP_SPR_ACCESSES | |
85 | { | |
86 | TCGv t0 = tcg_const_i32(sprn); | |
87 | gen_helper_store_dump_spr(t0); | |
88 | tcg_temp_free_i32(t0); | |
89 | } | |
04f20795 | 90 | #endif |
45d827d2 | 91 | } |
a496775f JM |
92 | |
93 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 94 | static void spr_write_clear (void *opaque, int sprn, int gprn) |
a496775f | 95 | { |
45d827d2 AJ |
96 | TCGv t0 = tcg_temp_new(); |
97 | TCGv t1 = tcg_temp_new(); | |
98 | gen_load_spr(t0, sprn); | |
99 | tcg_gen_neg_tl(t1, cpu_gpr[gprn]); | |
100 | tcg_gen_and_tl(t0, t0, t1); | |
101 | gen_store_spr(sprn, t0); | |
102 | tcg_temp_free(t0); | |
103 | tcg_temp_free(t1); | |
a496775f JM |
104 | } |
105 | #endif | |
106 | ||
76a66253 | 107 | /* SPR common to all PowerPC */ |
3fc6c082 | 108 | /* XER */ |
45d827d2 | 109 | static void spr_read_xer (void *opaque, int gprn, int sprn) |
3fc6c082 | 110 | { |
45d827d2 | 111 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer); |
3fc6c082 FB |
112 | } |
113 | ||
45d827d2 | 114 | static void spr_write_xer (void *opaque, int sprn, int gprn) |
3fc6c082 | 115 | { |
45d827d2 | 116 | tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]); |
3fc6c082 FB |
117 | } |
118 | ||
119 | /* LR */ | |
45d827d2 | 120 | static void spr_read_lr (void *opaque, int gprn, int sprn) |
3fc6c082 | 121 | { |
45d827d2 | 122 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); |
3fc6c082 FB |
123 | } |
124 | ||
45d827d2 | 125 | static void spr_write_lr (void *opaque, int sprn, int gprn) |
3fc6c082 | 126 | { |
45d827d2 | 127 | tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); |
3fc6c082 FB |
128 | } |
129 | ||
130 | /* CTR */ | |
45d827d2 | 131 | static void spr_read_ctr (void *opaque, int gprn, int sprn) |
3fc6c082 | 132 | { |
45d827d2 | 133 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); |
3fc6c082 FB |
134 | } |
135 | ||
45d827d2 | 136 | static void spr_write_ctr (void *opaque, int sprn, int gprn) |
3fc6c082 | 137 | { |
45d827d2 | 138 | tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); |
3fc6c082 FB |
139 | } |
140 | ||
141 | /* User read access to SPR */ | |
142 | /* USPRx */ | |
143 | /* UMMCRx */ | |
144 | /* UPMCx */ | |
145 | /* USIA */ | |
146 | /* UDECR */ | |
45d827d2 | 147 | static void spr_read_ureg (void *opaque, int gprn, int sprn) |
3fc6c082 | 148 | { |
45d827d2 | 149 | gen_load_spr(cpu_gpr[gprn], sprn + 0x10); |
3fc6c082 FB |
150 | } |
151 | ||
76a66253 | 152 | /* SPR common to all non-embedded PowerPC */ |
3fc6c082 | 153 | /* DECR */ |
76a66253 | 154 | #if !defined(CONFIG_USER_ONLY) |
45d827d2 | 155 | static void spr_read_decr (void *opaque, int gprn, int sprn) |
3fc6c082 | 156 | { |
45d827d2 | 157 | gen_helper_load_decr(cpu_gpr[gprn]); |
3fc6c082 FB |
158 | } |
159 | ||
45d827d2 | 160 | static void spr_write_decr (void *opaque, int sprn, int gprn) |
3fc6c082 | 161 | { |
45d827d2 | 162 | gen_helper_store_decr(cpu_gpr[gprn]); |
3fc6c082 | 163 | } |
76a66253 | 164 | #endif |
3fc6c082 | 165 | |
76a66253 | 166 | /* SPR common to all non-embedded PowerPC, except 601 */ |
3fc6c082 | 167 | /* Time base */ |
45d827d2 | 168 | static void spr_read_tbl (void *opaque, int gprn, int sprn) |
3fc6c082 | 169 | { |
45d827d2 | 170 | gen_helper_load_tbl(cpu_gpr[gprn]); |
3fc6c082 FB |
171 | } |
172 | ||
45d827d2 | 173 | static void spr_read_tbu (void *opaque, int gprn, int sprn) |
3fc6c082 | 174 | { |
45d827d2 | 175 | gen_helper_load_tbu(cpu_gpr[gprn]); |
3fc6c082 FB |
176 | } |
177 | ||
a062e36c | 178 | __attribute__ (( unused )) |
45d827d2 | 179 | static void spr_read_atbl (void *opaque, int gprn, int sprn) |
a062e36c | 180 | { |
45d827d2 | 181 | gen_helper_load_atbl(cpu_gpr[gprn]); |
a062e36c JM |
182 | } |
183 | ||
184 | __attribute__ (( unused )) | |
45d827d2 | 185 | static void spr_read_atbu (void *opaque, int gprn, int sprn) |
a062e36c | 186 | { |
45d827d2 | 187 | gen_helper_load_atbu(cpu_gpr[gprn]); |
a062e36c JM |
188 | } |
189 | ||
76a66253 | 190 | #if !defined(CONFIG_USER_ONLY) |
45d827d2 | 191 | static void spr_write_tbl (void *opaque, int sprn, int gprn) |
3fc6c082 | 192 | { |
45d827d2 | 193 | gen_helper_store_tbl(cpu_gpr[gprn]); |
3fc6c082 FB |
194 | } |
195 | ||
45d827d2 | 196 | static void spr_write_tbu (void *opaque, int sprn, int gprn) |
3fc6c082 | 197 | { |
45d827d2 | 198 | gen_helper_store_tbu(cpu_gpr[gprn]); |
3fc6c082 | 199 | } |
a062e36c JM |
200 | |
201 | __attribute__ (( unused )) | |
45d827d2 | 202 | static void spr_write_atbl (void *opaque, int sprn, int gprn) |
a062e36c | 203 | { |
45d827d2 | 204 | gen_helper_store_atbl(cpu_gpr[gprn]); |
a062e36c JM |
205 | } |
206 | ||
207 | __attribute__ (( unused )) | |
45d827d2 | 208 | static void spr_write_atbu (void *opaque, int sprn, int gprn) |
a062e36c | 209 | { |
45d827d2 | 210 | gen_helper_store_atbu(cpu_gpr[gprn]); |
a062e36c | 211 | } |
76a66253 | 212 | #endif |
3fc6c082 | 213 | |
76a66253 | 214 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
215 | /* IBAT0U...IBAT0U */ |
216 | /* IBAT0L...IBAT7L */ | |
45d827d2 | 217 | static void spr_read_ibat (void *opaque, int gprn, int sprn) |
3fc6c082 | 218 | { |
45d827d2 | 219 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
3fc6c082 FB |
220 | } |
221 | ||
45d827d2 | 222 | static void spr_read_ibat_h (void *opaque, int gprn, int sprn) |
3fc6c082 | 223 | { |
45d827d2 | 224 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2])); |
3fc6c082 FB |
225 | } |
226 | ||
45d827d2 | 227 | static void spr_write_ibatu (void *opaque, int sprn, int gprn) |
3fc6c082 | 228 | { |
45d827d2 AJ |
229 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
230 | gen_helper_store_ibatu(t0, cpu_gpr[gprn]); | |
231 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
232 | } |
233 | ||
45d827d2 | 234 | static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 235 | { |
45d827d2 AJ |
236 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2); |
237 | gen_helper_store_ibatu(t0, cpu_gpr[gprn]); | |
238 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
239 | } |
240 | ||
45d827d2 | 241 | static void spr_write_ibatl (void *opaque, int sprn, int gprn) |
3fc6c082 | 242 | { |
45d827d2 AJ |
243 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); |
244 | gen_helper_store_ibatl(t0, cpu_gpr[gprn]); | |
245 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
246 | } |
247 | ||
45d827d2 | 248 | static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 249 | { |
45d827d2 AJ |
250 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2); |
251 | gen_helper_store_ibatl(t0, cpu_gpr[gprn]); | |
252 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
253 | } |
254 | ||
255 | /* DBAT0U...DBAT7U */ | |
256 | /* DBAT0L...DBAT7L */ | |
45d827d2 | 257 | static void spr_read_dbat (void *opaque, int gprn, int sprn) |
3fc6c082 | 258 | { |
45d827d2 | 259 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); |
3fc6c082 FB |
260 | } |
261 | ||
45d827d2 | 262 | static void spr_read_dbat_h (void *opaque, int gprn, int sprn) |
3fc6c082 | 263 | { |
45d827d2 | 264 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); |
3fc6c082 FB |
265 | } |
266 | ||
45d827d2 | 267 | static void spr_write_dbatu (void *opaque, int sprn, int gprn) |
3fc6c082 | 268 | { |
45d827d2 AJ |
269 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); |
270 | gen_helper_store_dbatu(t0, cpu_gpr[gprn]); | |
271 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
272 | } |
273 | ||
45d827d2 | 274 | static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 275 | { |
45d827d2 AJ |
276 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
277 | gen_helper_store_dbatu(t0, cpu_gpr[gprn]); | |
278 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
279 | } |
280 | ||
45d827d2 | 281 | static void spr_write_dbatl (void *opaque, int sprn, int gprn) |
3fc6c082 | 282 | { |
45d827d2 AJ |
283 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); |
284 | gen_helper_store_dbatl(t0, cpu_gpr[gprn]); | |
285 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
286 | } |
287 | ||
45d827d2 | 288 | static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 289 | { |
45d827d2 AJ |
290 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
291 | gen_helper_store_dbatl(t0, cpu_gpr[gprn]); | |
292 | tcg_temp_free_i32(t0); | |
3fc6c082 FB |
293 | } |
294 | ||
295 | /* SDR1 */ | |
45d827d2 | 296 | static void spr_read_sdr1 (void *opaque, int gprn, int sprn) |
3fc6c082 | 297 | { |
45d827d2 | 298 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1)); |
3fc6c082 FB |
299 | } |
300 | ||
45d827d2 | 301 | static void spr_write_sdr1 (void *opaque, int sprn, int gprn) |
3fc6c082 | 302 | { |
45d827d2 | 303 | gen_helper_store_sdr1(cpu_gpr[gprn]); |
3fc6c082 FB |
304 | } |
305 | ||
76a66253 JM |
306 | /* 64 bits PowerPC specific SPRs */ |
307 | /* ASR */ | |
578bb252 | 308 | #if defined(TARGET_PPC64) |
2adab7d6 BS |
309 | static void spr_read_hior (void *opaque, int gprn, int sprn) |
310 | { | |
311 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix)); | |
312 | } | |
313 | ||
314 | static void spr_write_hior (void *opaque, int sprn, int gprn) | |
315 | { | |
316 | TCGv t0 = tcg_temp_new(); | |
317 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); | |
318 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix)); | |
319 | tcg_temp_free(t0); | |
320 | } | |
321 | ||
45d827d2 | 322 | static void spr_read_asr (void *opaque, int gprn, int sprn) |
76a66253 | 323 | { |
45d827d2 | 324 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr)); |
76a66253 JM |
325 | } |
326 | ||
45d827d2 | 327 | static void spr_write_asr (void *opaque, int sprn, int gprn) |
76a66253 | 328 | { |
45d827d2 | 329 | gen_helper_store_asr(cpu_gpr[gprn]); |
76a66253 JM |
330 | } |
331 | #endif | |
a750fc0b | 332 | #endif |
76a66253 JM |
333 | |
334 | /* PowerPC 601 specific registers */ | |
335 | /* RTC */ | |
45d827d2 | 336 | static void spr_read_601_rtcl (void *opaque, int gprn, int sprn) |
76a66253 | 337 | { |
45d827d2 | 338 | gen_helper_load_601_rtcl(cpu_gpr[gprn]); |
76a66253 JM |
339 | } |
340 | ||
45d827d2 | 341 | static void spr_read_601_rtcu (void *opaque, int gprn, int sprn) |
76a66253 | 342 | { |
45d827d2 | 343 | gen_helper_load_601_rtcu(cpu_gpr[gprn]); |
76a66253 JM |
344 | } |
345 | ||
346 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 347 | static void spr_write_601_rtcu (void *opaque, int sprn, int gprn) |
76a66253 | 348 | { |
45d827d2 | 349 | gen_helper_store_601_rtcu(cpu_gpr[gprn]); |
76a66253 JM |
350 | } |
351 | ||
45d827d2 | 352 | static void spr_write_601_rtcl (void *opaque, int sprn, int gprn) |
76a66253 | 353 | { |
45d827d2 | 354 | gen_helper_store_601_rtcl(cpu_gpr[gprn]); |
76a66253 | 355 | } |
056401ea | 356 | |
45d827d2 | 357 | static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) |
056401ea JM |
358 | { |
359 | DisasContext *ctx = opaque; | |
360 | ||
45d827d2 | 361 | gen_helper_store_hid0_601(cpu_gpr[gprn]); |
056401ea | 362 | /* Must stop the translation as endianness may have changed */ |
e06fcd75 | 363 | gen_stop_exception(ctx); |
056401ea | 364 | } |
76a66253 JM |
365 | #endif |
366 | ||
367 | /* Unified bats */ | |
368 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 369 | static void spr_read_601_ubat (void *opaque, int gprn, int sprn) |
76a66253 | 370 | { |
45d827d2 | 371 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
76a66253 JM |
372 | } |
373 | ||
45d827d2 | 374 | static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) |
76a66253 | 375 | { |
45d827d2 AJ |
376 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
377 | gen_helper_store_601_batl(t0, cpu_gpr[gprn]); | |
378 | tcg_temp_free_i32(t0); | |
76a66253 JM |
379 | } |
380 | ||
45d827d2 | 381 | static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) |
76a66253 | 382 | { |
45d827d2 AJ |
383 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
384 | gen_helper_store_601_batu(t0, cpu_gpr[gprn]); | |
385 | tcg_temp_free_i32(t0); | |
76a66253 JM |
386 | } |
387 | #endif | |
388 | ||
389 | /* PowerPC 40x specific registers */ | |
390 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 391 | static void spr_read_40x_pit (void *opaque, int gprn, int sprn) |
76a66253 | 392 | { |
45d827d2 | 393 | gen_helper_load_40x_pit(cpu_gpr[gprn]); |
76a66253 JM |
394 | } |
395 | ||
45d827d2 | 396 | static void spr_write_40x_pit (void *opaque, int sprn, int gprn) |
76a66253 | 397 | { |
45d827d2 | 398 | gen_helper_store_40x_pit(cpu_gpr[gprn]); |
76a66253 JM |
399 | } |
400 | ||
45d827d2 | 401 | static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) |
8ecc7913 JM |
402 | { |
403 | DisasContext *ctx = opaque; | |
404 | ||
45d827d2 | 405 | gen_helper_store_40x_dbcr0(cpu_gpr[gprn]); |
8ecc7913 | 406 | /* We must stop translation as we may have rebooted */ |
e06fcd75 | 407 | gen_stop_exception(ctx); |
8ecc7913 JM |
408 | } |
409 | ||
45d827d2 | 410 | static void spr_write_40x_sler (void *opaque, int sprn, int gprn) |
c294fc58 | 411 | { |
45d827d2 | 412 | gen_helper_store_40x_sler(cpu_gpr[gprn]); |
c294fc58 JM |
413 | } |
414 | ||
45d827d2 | 415 | static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) |
76a66253 | 416 | { |
45d827d2 | 417 | gen_helper_store_booke_tcr(cpu_gpr[gprn]); |
76a66253 JM |
418 | } |
419 | ||
45d827d2 | 420 | static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) |
76a66253 | 421 | { |
45d827d2 | 422 | gen_helper_store_booke_tsr(cpu_gpr[gprn]); |
76a66253 JM |
423 | } |
424 | #endif | |
425 | ||
426 | /* PowerPC 403 specific registers */ | |
427 | /* PBL1 / PBU1 / PBL2 / PBU2 */ | |
428 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 429 | static void spr_read_403_pbr (void *opaque, int gprn, int sprn) |
76a66253 | 430 | { |
45d827d2 | 431 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1])); |
76a66253 JM |
432 | } |
433 | ||
45d827d2 | 434 | static void spr_write_403_pbr (void *opaque, int sprn, int gprn) |
76a66253 | 435 | { |
45d827d2 AJ |
436 | TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); |
437 | gen_helper_store_403_pbr(t0, cpu_gpr[gprn]); | |
438 | tcg_temp_free_i32(t0); | |
76a66253 JM |
439 | } |
440 | ||
45d827d2 | 441 | static void spr_write_pir (void *opaque, int sprn, int gprn) |
3fc6c082 | 442 | { |
45d827d2 AJ |
443 | TCGv t0 = tcg_temp_new(); |
444 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); | |
445 | gen_store_spr(SPR_PIR, t0); | |
446 | tcg_temp_free(t0); | |
3fc6c082 | 447 | } |
76a66253 | 448 | #endif |
3fc6c082 | 449 | |
d34defbc AJ |
450 | /* SPE specific registers */ |
451 | static void spr_read_spefscr (void *opaque, int gprn, int sprn) | |
452 | { | |
453 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
515e2f7e | 454 | tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr)); |
d34defbc AJ |
455 | tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); |
456 | tcg_temp_free_i32(t0); | |
457 | } | |
458 | ||
459 | static void spr_write_spefscr (void *opaque, int sprn, int gprn) | |
460 | { | |
461 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
462 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); | |
515e2f7e | 463 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr)); |
d34defbc AJ |
464 | tcg_temp_free_i32(t0); |
465 | } | |
466 | ||
6f5d427d JM |
467 | #if !defined(CONFIG_USER_ONLY) |
468 | /* Callback used to write the exception vector base */ | |
45d827d2 | 469 | static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) |
6f5d427d | 470 | { |
45d827d2 AJ |
471 | TCGv t0 = tcg_temp_new(); |
472 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask)); | |
473 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
474 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix)); | |
475 | gen_store_spr(sprn, t0); | |
69bd5820 | 476 | tcg_temp_free(t0); |
6f5d427d JM |
477 | } |
478 | ||
45d827d2 | 479 | static void spr_write_excp_vector (void *opaque, int sprn, int gprn) |
6f5d427d JM |
480 | { |
481 | DisasContext *ctx = opaque; | |
482 | ||
483 | if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { | |
45d827d2 AJ |
484 | TCGv t0 = tcg_temp_new(); |
485 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); | |
486 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
487 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0])); | |
488 | gen_store_spr(sprn, t0); | |
489 | tcg_temp_free(t0); | |
6f5d427d | 490 | } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { |
45d827d2 AJ |
491 | TCGv t0 = tcg_temp_new(); |
492 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask)); | |
493 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
494 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32])); | |
495 | gen_store_spr(sprn, t0); | |
496 | tcg_temp_free(t0); | |
6f5d427d JM |
497 | } else { |
498 | printf("Trying to write an unknown exception vector %d %03x\n", | |
499 | sprn, sprn); | |
e06fcd75 | 500 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
6f5d427d JM |
501 | } |
502 | } | |
503 | #endif | |
504 | ||
cf8358c8 AJ |
505 | static inline void vscr_init (CPUPPCState *env, uint32_t val) |
506 | { | |
507 | env->vscr = val; | |
508 | /* Altivec always uses round-to-nearest */ | |
509 | set_float_rounding_mode(float_round_nearest_even, &env->vec_status); | |
510 | set_flush_to_zero(vscr_nj, &env->vec_status); | |
511 | } | |
512 | ||
76a66253 JM |
513 | #if defined(CONFIG_USER_ONLY) |
514 | #define spr_register(env, num, name, uea_read, uea_write, \ | |
515 | oea_read, oea_write, initial_value) \ | |
516 | do { \ | |
517 | _spr_register(env, num, name, uea_read, uea_write, initial_value); \ | |
518 | } while (0) | |
519 | static inline void _spr_register (CPUPPCState *env, int num, | |
b55266b5 | 520 | const char *name, |
45d827d2 AJ |
521 | void (*uea_read)(void *opaque, int gprn, int sprn), |
522 | void (*uea_write)(void *opaque, int sprn, int gprn), | |
76a66253 JM |
523 | target_ulong initial_value) |
524 | #else | |
3fc6c082 | 525 | static inline void spr_register (CPUPPCState *env, int num, |
b55266b5 | 526 | const char *name, |
45d827d2 AJ |
527 | void (*uea_read)(void *opaque, int gprn, int sprn), |
528 | void (*uea_write)(void *opaque, int sprn, int gprn), | |
529 | void (*oea_read)(void *opaque, int gprn, int sprn), | |
530 | void (*oea_write)(void *opaque, int sprn, int gprn), | |
3fc6c082 | 531 | target_ulong initial_value) |
76a66253 | 532 | #endif |
3fc6c082 FB |
533 | { |
534 | ppc_spr_t *spr; | |
535 | ||
536 | spr = &env->spr_cb[num]; | |
537 | if (spr->name != NULL ||env-> spr[num] != 0x00000000 || | |
76a66253 JM |
538 | #if !defined(CONFIG_USER_ONLY) |
539 | spr->oea_read != NULL || spr->oea_write != NULL || | |
540 | #endif | |
541 | spr->uea_read != NULL || spr->uea_write != NULL) { | |
3fc6c082 FB |
542 | printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); |
543 | exit(1); | |
544 | } | |
545 | #if defined(PPC_DEBUG_SPR) | |
1b9eb036 | 546 | printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name, |
76a66253 | 547 | initial_value); |
3fc6c082 FB |
548 | #endif |
549 | spr->name = name; | |
550 | spr->uea_read = uea_read; | |
551 | spr->uea_write = uea_write; | |
76a66253 | 552 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
553 | spr->oea_read = oea_read; |
554 | spr->oea_write = oea_write; | |
76a66253 | 555 | #endif |
3fc6c082 FB |
556 | env->spr[num] = initial_value; |
557 | } | |
558 | ||
559 | /* Generic PowerPC SPRs */ | |
560 | static void gen_spr_generic (CPUPPCState *env) | |
561 | { | |
562 | /* Integer processing */ | |
563 | spr_register(env, SPR_XER, "XER", | |
564 | &spr_read_xer, &spr_write_xer, | |
565 | &spr_read_xer, &spr_write_xer, | |
566 | 0x00000000); | |
567 | /* Branch contol */ | |
568 | spr_register(env, SPR_LR, "LR", | |
569 | &spr_read_lr, &spr_write_lr, | |
570 | &spr_read_lr, &spr_write_lr, | |
571 | 0x00000000); | |
572 | spr_register(env, SPR_CTR, "CTR", | |
573 | &spr_read_ctr, &spr_write_ctr, | |
574 | &spr_read_ctr, &spr_write_ctr, | |
575 | 0x00000000); | |
576 | /* Interrupt processing */ | |
577 | spr_register(env, SPR_SRR0, "SRR0", | |
578 | SPR_NOACCESS, SPR_NOACCESS, | |
579 | &spr_read_generic, &spr_write_generic, | |
580 | 0x00000000); | |
581 | spr_register(env, SPR_SRR1, "SRR1", | |
582 | SPR_NOACCESS, SPR_NOACCESS, | |
583 | &spr_read_generic, &spr_write_generic, | |
584 | 0x00000000); | |
585 | /* Processor control */ | |
586 | spr_register(env, SPR_SPRG0, "SPRG0", | |
587 | SPR_NOACCESS, SPR_NOACCESS, | |
588 | &spr_read_generic, &spr_write_generic, | |
589 | 0x00000000); | |
590 | spr_register(env, SPR_SPRG1, "SPRG1", | |
591 | SPR_NOACCESS, SPR_NOACCESS, | |
592 | &spr_read_generic, &spr_write_generic, | |
593 | 0x00000000); | |
594 | spr_register(env, SPR_SPRG2, "SPRG2", | |
595 | SPR_NOACCESS, SPR_NOACCESS, | |
596 | &spr_read_generic, &spr_write_generic, | |
597 | 0x00000000); | |
598 | spr_register(env, SPR_SPRG3, "SPRG3", | |
599 | SPR_NOACCESS, SPR_NOACCESS, | |
600 | &spr_read_generic, &spr_write_generic, | |
601 | 0x00000000); | |
602 | } | |
603 | ||
604 | /* SPR common to all non-embedded PowerPC, including 601 */ | |
605 | static void gen_spr_ne_601 (CPUPPCState *env) | |
606 | { | |
607 | /* Exception processing */ | |
608 | spr_register(env, SPR_DSISR, "DSISR", | |
609 | SPR_NOACCESS, SPR_NOACCESS, | |
610 | &spr_read_generic, &spr_write_generic, | |
611 | 0x00000000); | |
612 | spr_register(env, SPR_DAR, "DAR", | |
613 | SPR_NOACCESS, SPR_NOACCESS, | |
614 | &spr_read_generic, &spr_write_generic, | |
615 | 0x00000000); | |
616 | /* Timer */ | |
617 | spr_register(env, SPR_DECR, "DECR", | |
618 | SPR_NOACCESS, SPR_NOACCESS, | |
619 | &spr_read_decr, &spr_write_decr, | |
620 | 0x00000000); | |
621 | /* Memory management */ | |
622 | spr_register(env, SPR_SDR1, "SDR1", | |
623 | SPR_NOACCESS, SPR_NOACCESS, | |
624 | &spr_read_sdr1, &spr_write_sdr1, | |
625 | 0x00000000); | |
626 | } | |
627 | ||
628 | /* BATs 0-3 */ | |
629 | static void gen_low_BATs (CPUPPCState *env) | |
630 | { | |
f2e63a42 | 631 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
632 | spr_register(env, SPR_IBAT0U, "IBAT0U", |
633 | SPR_NOACCESS, SPR_NOACCESS, | |
634 | &spr_read_ibat, &spr_write_ibatu, | |
635 | 0x00000000); | |
636 | spr_register(env, SPR_IBAT0L, "IBAT0L", | |
637 | SPR_NOACCESS, SPR_NOACCESS, | |
638 | &spr_read_ibat, &spr_write_ibatl, | |
639 | 0x00000000); | |
640 | spr_register(env, SPR_IBAT1U, "IBAT1U", | |
641 | SPR_NOACCESS, SPR_NOACCESS, | |
642 | &spr_read_ibat, &spr_write_ibatu, | |
643 | 0x00000000); | |
644 | spr_register(env, SPR_IBAT1L, "IBAT1L", | |
645 | SPR_NOACCESS, SPR_NOACCESS, | |
646 | &spr_read_ibat, &spr_write_ibatl, | |
647 | 0x00000000); | |
648 | spr_register(env, SPR_IBAT2U, "IBAT2U", | |
649 | SPR_NOACCESS, SPR_NOACCESS, | |
650 | &spr_read_ibat, &spr_write_ibatu, | |
651 | 0x00000000); | |
652 | spr_register(env, SPR_IBAT2L, "IBAT2L", | |
653 | SPR_NOACCESS, SPR_NOACCESS, | |
654 | &spr_read_ibat, &spr_write_ibatl, | |
655 | 0x00000000); | |
656 | spr_register(env, SPR_IBAT3U, "IBAT3U", | |
657 | SPR_NOACCESS, SPR_NOACCESS, | |
658 | &spr_read_ibat, &spr_write_ibatu, | |
659 | 0x00000000); | |
660 | spr_register(env, SPR_IBAT3L, "IBAT3L", | |
661 | SPR_NOACCESS, SPR_NOACCESS, | |
662 | &spr_read_ibat, &spr_write_ibatl, | |
663 | 0x00000000); | |
664 | spr_register(env, SPR_DBAT0U, "DBAT0U", | |
665 | SPR_NOACCESS, SPR_NOACCESS, | |
666 | &spr_read_dbat, &spr_write_dbatu, | |
667 | 0x00000000); | |
668 | spr_register(env, SPR_DBAT0L, "DBAT0L", | |
669 | SPR_NOACCESS, SPR_NOACCESS, | |
670 | &spr_read_dbat, &spr_write_dbatl, | |
671 | 0x00000000); | |
672 | spr_register(env, SPR_DBAT1U, "DBAT1U", | |
673 | SPR_NOACCESS, SPR_NOACCESS, | |
674 | &spr_read_dbat, &spr_write_dbatu, | |
675 | 0x00000000); | |
676 | spr_register(env, SPR_DBAT1L, "DBAT1L", | |
677 | SPR_NOACCESS, SPR_NOACCESS, | |
678 | &spr_read_dbat, &spr_write_dbatl, | |
679 | 0x00000000); | |
680 | spr_register(env, SPR_DBAT2U, "DBAT2U", | |
681 | SPR_NOACCESS, SPR_NOACCESS, | |
682 | &spr_read_dbat, &spr_write_dbatu, | |
683 | 0x00000000); | |
684 | spr_register(env, SPR_DBAT2L, "DBAT2L", | |
685 | SPR_NOACCESS, SPR_NOACCESS, | |
686 | &spr_read_dbat, &spr_write_dbatl, | |
687 | 0x00000000); | |
688 | spr_register(env, SPR_DBAT3U, "DBAT3U", | |
689 | SPR_NOACCESS, SPR_NOACCESS, | |
690 | &spr_read_dbat, &spr_write_dbatu, | |
691 | 0x00000000); | |
692 | spr_register(env, SPR_DBAT3L, "DBAT3L", | |
693 | SPR_NOACCESS, SPR_NOACCESS, | |
694 | &spr_read_dbat, &spr_write_dbatl, | |
695 | 0x00000000); | |
a750fc0b | 696 | env->nb_BATs += 4; |
f2e63a42 | 697 | #endif |
3fc6c082 FB |
698 | } |
699 | ||
700 | /* BATs 4-7 */ | |
701 | static void gen_high_BATs (CPUPPCState *env) | |
702 | { | |
f2e63a42 | 703 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
704 | spr_register(env, SPR_IBAT4U, "IBAT4U", |
705 | SPR_NOACCESS, SPR_NOACCESS, | |
706 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
707 | 0x00000000); | |
708 | spr_register(env, SPR_IBAT4L, "IBAT4L", | |
709 | SPR_NOACCESS, SPR_NOACCESS, | |
710 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
711 | 0x00000000); | |
712 | spr_register(env, SPR_IBAT5U, "IBAT5U", | |
713 | SPR_NOACCESS, SPR_NOACCESS, | |
714 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
715 | 0x00000000); | |
716 | spr_register(env, SPR_IBAT5L, "IBAT5L", | |
717 | SPR_NOACCESS, SPR_NOACCESS, | |
718 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
719 | 0x00000000); | |
720 | spr_register(env, SPR_IBAT6U, "IBAT6U", | |
721 | SPR_NOACCESS, SPR_NOACCESS, | |
722 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
723 | 0x00000000); | |
724 | spr_register(env, SPR_IBAT6L, "IBAT6L", | |
725 | SPR_NOACCESS, SPR_NOACCESS, | |
726 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
727 | 0x00000000); | |
728 | spr_register(env, SPR_IBAT7U, "IBAT7U", | |
729 | SPR_NOACCESS, SPR_NOACCESS, | |
730 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
731 | 0x00000000); | |
732 | spr_register(env, SPR_IBAT7L, "IBAT7L", | |
733 | SPR_NOACCESS, SPR_NOACCESS, | |
734 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
735 | 0x00000000); | |
736 | spr_register(env, SPR_DBAT4U, "DBAT4U", | |
737 | SPR_NOACCESS, SPR_NOACCESS, | |
738 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
739 | 0x00000000); | |
740 | spr_register(env, SPR_DBAT4L, "DBAT4L", | |
741 | SPR_NOACCESS, SPR_NOACCESS, | |
742 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
743 | 0x00000000); | |
744 | spr_register(env, SPR_DBAT5U, "DBAT5U", | |
745 | SPR_NOACCESS, SPR_NOACCESS, | |
746 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
747 | 0x00000000); | |
748 | spr_register(env, SPR_DBAT5L, "DBAT5L", | |
749 | SPR_NOACCESS, SPR_NOACCESS, | |
750 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
751 | 0x00000000); | |
752 | spr_register(env, SPR_DBAT6U, "DBAT6U", | |
753 | SPR_NOACCESS, SPR_NOACCESS, | |
754 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
755 | 0x00000000); | |
756 | spr_register(env, SPR_DBAT6L, "DBAT6L", | |
757 | SPR_NOACCESS, SPR_NOACCESS, | |
758 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
759 | 0x00000000); | |
760 | spr_register(env, SPR_DBAT7U, "DBAT7U", | |
761 | SPR_NOACCESS, SPR_NOACCESS, | |
762 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
763 | 0x00000000); | |
764 | spr_register(env, SPR_DBAT7L, "DBAT7L", | |
765 | SPR_NOACCESS, SPR_NOACCESS, | |
766 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
767 | 0x00000000); | |
a750fc0b | 768 | env->nb_BATs += 4; |
f2e63a42 | 769 | #endif |
3fc6c082 FB |
770 | } |
771 | ||
772 | /* Generic PowerPC time base */ | |
773 | static void gen_tbl (CPUPPCState *env) | |
774 | { | |
775 | spr_register(env, SPR_VTBL, "TBL", | |
776 | &spr_read_tbl, SPR_NOACCESS, | |
777 | &spr_read_tbl, SPR_NOACCESS, | |
778 | 0x00000000); | |
779 | spr_register(env, SPR_TBL, "TBL", | |
780 | SPR_NOACCESS, SPR_NOACCESS, | |
781 | SPR_NOACCESS, &spr_write_tbl, | |
782 | 0x00000000); | |
783 | spr_register(env, SPR_VTBU, "TBU", | |
784 | &spr_read_tbu, SPR_NOACCESS, | |
785 | &spr_read_tbu, SPR_NOACCESS, | |
786 | 0x00000000); | |
787 | spr_register(env, SPR_TBU, "TBU", | |
788 | SPR_NOACCESS, SPR_NOACCESS, | |
789 | SPR_NOACCESS, &spr_write_tbu, | |
790 | 0x00000000); | |
791 | } | |
792 | ||
76a66253 JM |
793 | /* Softare table search registers */ |
794 | static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) | |
795 | { | |
f2e63a42 | 796 | #if !defined(CONFIG_USER_ONLY) |
76a66253 JM |
797 | env->nb_tlb = nb_tlbs; |
798 | env->nb_ways = nb_ways; | |
799 | env->id_tlbs = 1; | |
800 | spr_register(env, SPR_DMISS, "DMISS", | |
801 | SPR_NOACCESS, SPR_NOACCESS, | |
802 | &spr_read_generic, SPR_NOACCESS, | |
803 | 0x00000000); | |
804 | spr_register(env, SPR_DCMP, "DCMP", | |
805 | SPR_NOACCESS, SPR_NOACCESS, | |
806 | &spr_read_generic, SPR_NOACCESS, | |
807 | 0x00000000); | |
808 | spr_register(env, SPR_HASH1, "HASH1", | |
809 | SPR_NOACCESS, SPR_NOACCESS, | |
810 | &spr_read_generic, SPR_NOACCESS, | |
811 | 0x00000000); | |
812 | spr_register(env, SPR_HASH2, "HASH2", | |
813 | SPR_NOACCESS, SPR_NOACCESS, | |
814 | &spr_read_generic, SPR_NOACCESS, | |
815 | 0x00000000); | |
816 | spr_register(env, SPR_IMISS, "IMISS", | |
817 | SPR_NOACCESS, SPR_NOACCESS, | |
818 | &spr_read_generic, SPR_NOACCESS, | |
819 | 0x00000000); | |
820 | spr_register(env, SPR_ICMP, "ICMP", | |
821 | SPR_NOACCESS, SPR_NOACCESS, | |
822 | &spr_read_generic, SPR_NOACCESS, | |
823 | 0x00000000); | |
824 | spr_register(env, SPR_RPA, "RPA", | |
825 | SPR_NOACCESS, SPR_NOACCESS, | |
826 | &spr_read_generic, &spr_write_generic, | |
827 | 0x00000000); | |
f2e63a42 | 828 | #endif |
76a66253 JM |
829 | } |
830 | ||
831 | /* SPR common to MPC755 and G2 */ | |
832 | static void gen_spr_G2_755 (CPUPPCState *env) | |
833 | { | |
834 | /* SGPRs */ | |
835 | spr_register(env, SPR_SPRG4, "SPRG4", | |
836 | SPR_NOACCESS, SPR_NOACCESS, | |
837 | &spr_read_generic, &spr_write_generic, | |
838 | 0x00000000); | |
839 | spr_register(env, SPR_SPRG5, "SPRG5", | |
840 | SPR_NOACCESS, SPR_NOACCESS, | |
841 | &spr_read_generic, &spr_write_generic, | |
842 | 0x00000000); | |
843 | spr_register(env, SPR_SPRG6, "SPRG6", | |
844 | SPR_NOACCESS, SPR_NOACCESS, | |
845 | &spr_read_generic, &spr_write_generic, | |
846 | 0x00000000); | |
847 | spr_register(env, SPR_SPRG7, "SPRG7", | |
848 | SPR_NOACCESS, SPR_NOACCESS, | |
849 | &spr_read_generic, &spr_write_generic, | |
850 | 0x00000000); | |
76a66253 JM |
851 | } |
852 | ||
3fc6c082 FB |
853 | /* SPR common to all 7xx PowerPC implementations */ |
854 | static void gen_spr_7xx (CPUPPCState *env) | |
855 | { | |
856 | /* Breakpoints */ | |
857 | /* XXX : not implemented */ | |
858 | spr_register(env, SPR_DABR, "DABR", | |
859 | SPR_NOACCESS, SPR_NOACCESS, | |
860 | &spr_read_generic, &spr_write_generic, | |
861 | 0x00000000); | |
862 | /* XXX : not implemented */ | |
863 | spr_register(env, SPR_IABR, "IABR", | |
864 | SPR_NOACCESS, SPR_NOACCESS, | |
865 | &spr_read_generic, &spr_write_generic, | |
866 | 0x00000000); | |
867 | /* Cache management */ | |
868 | /* XXX : not implemented */ | |
869 | spr_register(env, SPR_ICTC, "ICTC", | |
870 | SPR_NOACCESS, SPR_NOACCESS, | |
871 | &spr_read_generic, &spr_write_generic, | |
872 | 0x00000000); | |
873 | /* Performance monitors */ | |
874 | /* XXX : not implemented */ | |
875 | spr_register(env, SPR_MMCR0, "MMCR0", | |
876 | SPR_NOACCESS, SPR_NOACCESS, | |
877 | &spr_read_generic, &spr_write_generic, | |
878 | 0x00000000); | |
879 | /* XXX : not implemented */ | |
880 | spr_register(env, SPR_MMCR1, "MMCR1", | |
881 | SPR_NOACCESS, SPR_NOACCESS, | |
882 | &spr_read_generic, &spr_write_generic, | |
883 | 0x00000000); | |
884 | /* XXX : not implemented */ | |
885 | spr_register(env, SPR_PMC1, "PMC1", | |
886 | SPR_NOACCESS, SPR_NOACCESS, | |
887 | &spr_read_generic, &spr_write_generic, | |
888 | 0x00000000); | |
889 | /* XXX : not implemented */ | |
890 | spr_register(env, SPR_PMC2, "PMC2", | |
891 | SPR_NOACCESS, SPR_NOACCESS, | |
892 | &spr_read_generic, &spr_write_generic, | |
893 | 0x00000000); | |
894 | /* XXX : not implemented */ | |
895 | spr_register(env, SPR_PMC3, "PMC3", | |
896 | SPR_NOACCESS, SPR_NOACCESS, | |
897 | &spr_read_generic, &spr_write_generic, | |
898 | 0x00000000); | |
899 | /* XXX : not implemented */ | |
900 | spr_register(env, SPR_PMC4, "PMC4", | |
901 | SPR_NOACCESS, SPR_NOACCESS, | |
902 | &spr_read_generic, &spr_write_generic, | |
903 | 0x00000000); | |
904 | /* XXX : not implemented */ | |
a750fc0b | 905 | spr_register(env, SPR_SIAR, "SIAR", |
3fc6c082 FB |
906 | SPR_NOACCESS, SPR_NOACCESS, |
907 | &spr_read_generic, SPR_NOACCESS, | |
908 | 0x00000000); | |
578bb252 | 909 | /* XXX : not implemented */ |
3fc6c082 FB |
910 | spr_register(env, SPR_UMMCR0, "UMMCR0", |
911 | &spr_read_ureg, SPR_NOACCESS, | |
912 | &spr_read_ureg, SPR_NOACCESS, | |
913 | 0x00000000); | |
578bb252 | 914 | /* XXX : not implemented */ |
3fc6c082 FB |
915 | spr_register(env, SPR_UMMCR1, "UMMCR1", |
916 | &spr_read_ureg, SPR_NOACCESS, | |
917 | &spr_read_ureg, SPR_NOACCESS, | |
918 | 0x00000000); | |
578bb252 | 919 | /* XXX : not implemented */ |
3fc6c082 FB |
920 | spr_register(env, SPR_UPMC1, "UPMC1", |
921 | &spr_read_ureg, SPR_NOACCESS, | |
922 | &spr_read_ureg, SPR_NOACCESS, | |
923 | 0x00000000); | |
578bb252 | 924 | /* XXX : not implemented */ |
3fc6c082 FB |
925 | spr_register(env, SPR_UPMC2, "UPMC2", |
926 | &spr_read_ureg, SPR_NOACCESS, | |
927 | &spr_read_ureg, SPR_NOACCESS, | |
928 | 0x00000000); | |
578bb252 | 929 | /* XXX : not implemented */ |
3fc6c082 FB |
930 | spr_register(env, SPR_UPMC3, "UPMC3", |
931 | &spr_read_ureg, SPR_NOACCESS, | |
932 | &spr_read_ureg, SPR_NOACCESS, | |
933 | 0x00000000); | |
578bb252 | 934 | /* XXX : not implemented */ |
3fc6c082 FB |
935 | spr_register(env, SPR_UPMC4, "UPMC4", |
936 | &spr_read_ureg, SPR_NOACCESS, | |
937 | &spr_read_ureg, SPR_NOACCESS, | |
938 | 0x00000000); | |
578bb252 | 939 | /* XXX : not implemented */ |
a750fc0b | 940 | spr_register(env, SPR_USIAR, "USIAR", |
3fc6c082 FB |
941 | &spr_read_ureg, SPR_NOACCESS, |
942 | &spr_read_ureg, SPR_NOACCESS, | |
943 | 0x00000000); | |
a750fc0b | 944 | /* External access control */ |
3fc6c082 | 945 | /* XXX : not implemented */ |
a750fc0b | 946 | spr_register(env, SPR_EAR, "EAR", |
3fc6c082 FB |
947 | SPR_NOACCESS, SPR_NOACCESS, |
948 | &spr_read_generic, &spr_write_generic, | |
949 | 0x00000000); | |
a750fc0b JM |
950 | } |
951 | ||
952 | static void gen_spr_thrm (CPUPPCState *env) | |
953 | { | |
954 | /* Thermal management */ | |
3fc6c082 | 955 | /* XXX : not implemented */ |
a750fc0b | 956 | spr_register(env, SPR_THRM1, "THRM1", |
3fc6c082 FB |
957 | SPR_NOACCESS, SPR_NOACCESS, |
958 | &spr_read_generic, &spr_write_generic, | |
959 | 0x00000000); | |
960 | /* XXX : not implemented */ | |
a750fc0b | 961 | spr_register(env, SPR_THRM2, "THRM2", |
3fc6c082 FB |
962 | SPR_NOACCESS, SPR_NOACCESS, |
963 | &spr_read_generic, &spr_write_generic, | |
964 | 0x00000000); | |
3fc6c082 | 965 | /* XXX : not implemented */ |
a750fc0b | 966 | spr_register(env, SPR_THRM3, "THRM3", |
3fc6c082 FB |
967 | SPR_NOACCESS, SPR_NOACCESS, |
968 | &spr_read_generic, &spr_write_generic, | |
969 | 0x00000000); | |
970 | } | |
971 | ||
972 | /* SPR specific to PowerPC 604 implementation */ | |
973 | static void gen_spr_604 (CPUPPCState *env) | |
974 | { | |
975 | /* Processor identification */ | |
976 | spr_register(env, SPR_PIR, "PIR", | |
977 | SPR_NOACCESS, SPR_NOACCESS, | |
978 | &spr_read_generic, &spr_write_pir, | |
979 | 0x00000000); | |
980 | /* Breakpoints */ | |
981 | /* XXX : not implemented */ | |
982 | spr_register(env, SPR_IABR, "IABR", | |
983 | SPR_NOACCESS, SPR_NOACCESS, | |
984 | &spr_read_generic, &spr_write_generic, | |
985 | 0x00000000); | |
986 | /* XXX : not implemented */ | |
987 | spr_register(env, SPR_DABR, "DABR", | |
988 | SPR_NOACCESS, SPR_NOACCESS, | |
989 | &spr_read_generic, &spr_write_generic, | |
990 | 0x00000000); | |
991 | /* Performance counters */ | |
992 | /* XXX : not implemented */ | |
993 | spr_register(env, SPR_MMCR0, "MMCR0", | |
994 | SPR_NOACCESS, SPR_NOACCESS, | |
995 | &spr_read_generic, &spr_write_generic, | |
996 | 0x00000000); | |
997 | /* XXX : not implemented */ | |
3fc6c082 FB |
998 | spr_register(env, SPR_PMC1, "PMC1", |
999 | SPR_NOACCESS, SPR_NOACCESS, | |
1000 | &spr_read_generic, &spr_write_generic, | |
1001 | 0x00000000); | |
1002 | /* XXX : not implemented */ | |
1003 | spr_register(env, SPR_PMC2, "PMC2", | |
1004 | SPR_NOACCESS, SPR_NOACCESS, | |
1005 | &spr_read_generic, &spr_write_generic, | |
1006 | 0x00000000); | |
1007 | /* XXX : not implemented */ | |
a750fc0b | 1008 | spr_register(env, SPR_SIAR, "SIAR", |
3fc6c082 FB |
1009 | SPR_NOACCESS, SPR_NOACCESS, |
1010 | &spr_read_generic, SPR_NOACCESS, | |
1011 | 0x00000000); | |
1012 | /* XXX : not implemented */ | |
1013 | spr_register(env, SPR_SDA, "SDA", | |
1014 | SPR_NOACCESS, SPR_NOACCESS, | |
1015 | &spr_read_generic, SPR_NOACCESS, | |
1016 | 0x00000000); | |
1017 | /* External access control */ | |
1018 | /* XXX : not implemented */ | |
1019 | spr_register(env, SPR_EAR, "EAR", | |
1020 | SPR_NOACCESS, SPR_NOACCESS, | |
1021 | &spr_read_generic, &spr_write_generic, | |
1022 | 0x00000000); | |
1023 | } | |
1024 | ||
76a66253 JM |
1025 | /* SPR specific to PowerPC 603 implementation */ |
1026 | static void gen_spr_603 (CPUPPCState *env) | |
3fc6c082 | 1027 | { |
76a66253 JM |
1028 | /* External access control */ |
1029 | /* XXX : not implemented */ | |
1030 | spr_register(env, SPR_EAR, "EAR", | |
3fc6c082 | 1031 | SPR_NOACCESS, SPR_NOACCESS, |
76a66253 JM |
1032 | &spr_read_generic, &spr_write_generic, |
1033 | 0x00000000); | |
3fc6c082 FB |
1034 | } |
1035 | ||
76a66253 JM |
1036 | /* SPR specific to PowerPC G2 implementation */ |
1037 | static void gen_spr_G2 (CPUPPCState *env) | |
3fc6c082 | 1038 | { |
76a66253 JM |
1039 | /* Memory base address */ |
1040 | /* MBAR */ | |
578bb252 | 1041 | /* XXX : not implemented */ |
76a66253 JM |
1042 | spr_register(env, SPR_MBAR, "MBAR", |
1043 | SPR_NOACCESS, SPR_NOACCESS, | |
1044 | &spr_read_generic, &spr_write_generic, | |
1045 | 0x00000000); | |
76a66253 | 1046 | /* Exception processing */ |
363be49c | 1047 | spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
76a66253 JM |
1048 | SPR_NOACCESS, SPR_NOACCESS, |
1049 | &spr_read_generic, &spr_write_generic, | |
1050 | 0x00000000); | |
363be49c | 1051 | spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
76a66253 JM |
1052 | SPR_NOACCESS, SPR_NOACCESS, |
1053 | &spr_read_generic, &spr_write_generic, | |
1054 | 0x00000000); | |
1055 | /* Breakpoints */ | |
1056 | /* XXX : not implemented */ | |
1057 | spr_register(env, SPR_DABR, "DABR", | |
1058 | SPR_NOACCESS, SPR_NOACCESS, | |
1059 | &spr_read_generic, &spr_write_generic, | |
1060 | 0x00000000); | |
1061 | /* XXX : not implemented */ | |
1062 | spr_register(env, SPR_DABR2, "DABR2", | |
1063 | SPR_NOACCESS, SPR_NOACCESS, | |
1064 | &spr_read_generic, &spr_write_generic, | |
1065 | 0x00000000); | |
1066 | /* XXX : not implemented */ | |
1067 | spr_register(env, SPR_IABR, "IABR", | |
1068 | SPR_NOACCESS, SPR_NOACCESS, | |
1069 | &spr_read_generic, &spr_write_generic, | |
1070 | 0x00000000); | |
1071 | /* XXX : not implemented */ | |
1072 | spr_register(env, SPR_IABR2, "IABR2", | |
1073 | SPR_NOACCESS, SPR_NOACCESS, | |
1074 | &spr_read_generic, &spr_write_generic, | |
1075 | 0x00000000); | |
1076 | /* XXX : not implemented */ | |
1077 | spr_register(env, SPR_IBCR, "IBCR", | |
1078 | SPR_NOACCESS, SPR_NOACCESS, | |
1079 | &spr_read_generic, &spr_write_generic, | |
1080 | 0x00000000); | |
1081 | /* XXX : not implemented */ | |
1082 | spr_register(env, SPR_DBCR, "DBCR", | |
1083 | SPR_NOACCESS, SPR_NOACCESS, | |
1084 | &spr_read_generic, &spr_write_generic, | |
1085 | 0x00000000); | |
1086 | } | |
1087 | ||
1088 | /* SPR specific to PowerPC 602 implementation */ | |
1089 | static void gen_spr_602 (CPUPPCState *env) | |
1090 | { | |
1091 | /* ESA registers */ | |
1092 | /* XXX : not implemented */ | |
1093 | spr_register(env, SPR_SER, "SER", | |
1094 | SPR_NOACCESS, SPR_NOACCESS, | |
1095 | &spr_read_generic, &spr_write_generic, | |
1096 | 0x00000000); | |
1097 | /* XXX : not implemented */ | |
1098 | spr_register(env, SPR_SEBR, "SEBR", | |
1099 | SPR_NOACCESS, SPR_NOACCESS, | |
1100 | &spr_read_generic, &spr_write_generic, | |
1101 | 0x00000000); | |
1102 | /* XXX : not implemented */ | |
a750fc0b | 1103 | spr_register(env, SPR_ESASRR, "ESASRR", |
76a66253 JM |
1104 | SPR_NOACCESS, SPR_NOACCESS, |
1105 | &spr_read_generic, &spr_write_generic, | |
1106 | 0x00000000); | |
1107 | /* Floating point status */ | |
1108 | /* XXX : not implemented */ | |
1109 | spr_register(env, SPR_SP, "SP", | |
1110 | SPR_NOACCESS, SPR_NOACCESS, | |
1111 | &spr_read_generic, &spr_write_generic, | |
1112 | 0x00000000); | |
1113 | /* XXX : not implemented */ | |
1114 | spr_register(env, SPR_LT, "LT", | |
1115 | SPR_NOACCESS, SPR_NOACCESS, | |
1116 | &spr_read_generic, &spr_write_generic, | |
1117 | 0x00000000); | |
1118 | /* Watchdog timer */ | |
1119 | /* XXX : not implemented */ | |
1120 | spr_register(env, SPR_TCR, "TCR", | |
1121 | SPR_NOACCESS, SPR_NOACCESS, | |
1122 | &spr_read_generic, &spr_write_generic, | |
1123 | 0x00000000); | |
1124 | /* Interrupt base */ | |
1125 | spr_register(env, SPR_IBR, "IBR", | |
1126 | SPR_NOACCESS, SPR_NOACCESS, | |
1127 | &spr_read_generic, &spr_write_generic, | |
1128 | 0x00000000); | |
a750fc0b JM |
1129 | /* XXX : not implemented */ |
1130 | spr_register(env, SPR_IABR, "IABR", | |
1131 | SPR_NOACCESS, SPR_NOACCESS, | |
1132 | &spr_read_generic, &spr_write_generic, | |
1133 | 0x00000000); | |
76a66253 JM |
1134 | } |
1135 | ||
1136 | /* SPR specific to PowerPC 601 implementation */ | |
1137 | static void gen_spr_601 (CPUPPCState *env) | |
1138 | { | |
1139 | /* Multiplication/division register */ | |
1140 | /* MQ */ | |
1141 | spr_register(env, SPR_MQ, "MQ", | |
1142 | &spr_read_generic, &spr_write_generic, | |
1143 | &spr_read_generic, &spr_write_generic, | |
1144 | 0x00000000); | |
1145 | /* RTC registers */ | |
1146 | spr_register(env, SPR_601_RTCU, "RTCU", | |
1147 | SPR_NOACCESS, SPR_NOACCESS, | |
1148 | SPR_NOACCESS, &spr_write_601_rtcu, | |
1149 | 0x00000000); | |
1150 | spr_register(env, SPR_601_VRTCU, "RTCU", | |
1151 | &spr_read_601_rtcu, SPR_NOACCESS, | |
1152 | &spr_read_601_rtcu, SPR_NOACCESS, | |
1153 | 0x00000000); | |
1154 | spr_register(env, SPR_601_RTCL, "RTCL", | |
1155 | SPR_NOACCESS, SPR_NOACCESS, | |
1156 | SPR_NOACCESS, &spr_write_601_rtcl, | |
1157 | 0x00000000); | |
1158 | spr_register(env, SPR_601_VRTCL, "RTCL", | |
1159 | &spr_read_601_rtcl, SPR_NOACCESS, | |
1160 | &spr_read_601_rtcl, SPR_NOACCESS, | |
1161 | 0x00000000); | |
1162 | /* Timer */ | |
1163 | #if 0 /* ? */ | |
1164 | spr_register(env, SPR_601_UDECR, "UDECR", | |
1165 | &spr_read_decr, SPR_NOACCESS, | |
1166 | &spr_read_decr, SPR_NOACCESS, | |
1167 | 0x00000000); | |
1168 | #endif | |
1169 | /* External access control */ | |
1170 | /* XXX : not implemented */ | |
1171 | spr_register(env, SPR_EAR, "EAR", | |
1172 | SPR_NOACCESS, SPR_NOACCESS, | |
1173 | &spr_read_generic, &spr_write_generic, | |
1174 | 0x00000000); | |
1175 | /* Memory management */ | |
f2e63a42 | 1176 | #if !defined(CONFIG_USER_ONLY) |
76a66253 JM |
1177 | spr_register(env, SPR_IBAT0U, "IBAT0U", |
1178 | SPR_NOACCESS, SPR_NOACCESS, | |
1179 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1180 | 0x00000000); | |
1181 | spr_register(env, SPR_IBAT0L, "IBAT0L", | |
1182 | SPR_NOACCESS, SPR_NOACCESS, | |
1183 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1184 | 0x00000000); | |
1185 | spr_register(env, SPR_IBAT1U, "IBAT1U", | |
1186 | SPR_NOACCESS, SPR_NOACCESS, | |
1187 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1188 | 0x00000000); | |
1189 | spr_register(env, SPR_IBAT1L, "IBAT1L", | |
1190 | SPR_NOACCESS, SPR_NOACCESS, | |
1191 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1192 | 0x00000000); | |
1193 | spr_register(env, SPR_IBAT2U, "IBAT2U", | |
1194 | SPR_NOACCESS, SPR_NOACCESS, | |
1195 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1196 | 0x00000000); | |
1197 | spr_register(env, SPR_IBAT2L, "IBAT2L", | |
1198 | SPR_NOACCESS, SPR_NOACCESS, | |
1199 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1200 | 0x00000000); | |
1201 | spr_register(env, SPR_IBAT3U, "IBAT3U", | |
1202 | SPR_NOACCESS, SPR_NOACCESS, | |
1203 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1204 | 0x00000000); | |
1205 | spr_register(env, SPR_IBAT3L, "IBAT3L", | |
1206 | SPR_NOACCESS, SPR_NOACCESS, | |
1207 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1208 | 0x00000000); | |
a750fc0b | 1209 | env->nb_BATs = 4; |
f2e63a42 | 1210 | #endif |
a750fc0b JM |
1211 | } |
1212 | ||
1213 | static void gen_spr_74xx (CPUPPCState *env) | |
1214 | { | |
1215 | /* Processor identification */ | |
1216 | spr_register(env, SPR_PIR, "PIR", | |
1217 | SPR_NOACCESS, SPR_NOACCESS, | |
1218 | &spr_read_generic, &spr_write_pir, | |
1219 | 0x00000000); | |
1220 | /* XXX : not implemented */ | |
1221 | spr_register(env, SPR_MMCR2, "MMCR2", | |
1222 | SPR_NOACCESS, SPR_NOACCESS, | |
1223 | &spr_read_generic, &spr_write_generic, | |
1224 | 0x00000000); | |
578bb252 | 1225 | /* XXX : not implemented */ |
a750fc0b JM |
1226 | spr_register(env, SPR_UMMCR2, "UMMCR2", |
1227 | &spr_read_ureg, SPR_NOACCESS, | |
1228 | &spr_read_ureg, SPR_NOACCESS, | |
1229 | 0x00000000); | |
1230 | /* XXX: not implemented */ | |
1231 | spr_register(env, SPR_BAMR, "BAMR", | |
1232 | SPR_NOACCESS, SPR_NOACCESS, | |
1233 | &spr_read_generic, &spr_write_generic, | |
1234 | 0x00000000); | |
578bb252 | 1235 | /* XXX : not implemented */ |
a750fc0b JM |
1236 | spr_register(env, SPR_MSSCR0, "MSSCR0", |
1237 | SPR_NOACCESS, SPR_NOACCESS, | |
1238 | &spr_read_generic, &spr_write_generic, | |
1239 | 0x00000000); | |
1240 | /* Hardware implementation registers */ | |
1241 | /* XXX : not implemented */ | |
1242 | spr_register(env, SPR_HID0, "HID0", | |
1243 | SPR_NOACCESS, SPR_NOACCESS, | |
1244 | &spr_read_generic, &spr_write_generic, | |
1245 | 0x00000000); | |
1246 | /* XXX : not implemented */ | |
1247 | spr_register(env, SPR_HID1, "HID1", | |
1248 | SPR_NOACCESS, SPR_NOACCESS, | |
1249 | &spr_read_generic, &spr_write_generic, | |
1250 | 0x00000000); | |
1251 | /* Altivec */ | |
1252 | spr_register(env, SPR_VRSAVE, "VRSAVE", | |
1253 | &spr_read_generic, &spr_write_generic, | |
1254 | &spr_read_generic, &spr_write_generic, | |
1255 | 0x00000000); | |
bd928eba JM |
1256 | /* XXX : not implemented */ |
1257 | spr_register(env, SPR_L2CR, "L2CR", | |
1258 | SPR_NOACCESS, SPR_NOACCESS, | |
1259 | &spr_read_generic, &spr_write_generic, | |
1260 | 0x00000000); | |
cf8358c8 AJ |
1261 | /* Not strictly an SPR */ |
1262 | vscr_init(env, 0x00010000); | |
a750fc0b JM |
1263 | } |
1264 | ||
a750fc0b JM |
1265 | static void gen_l3_ctrl (CPUPPCState *env) |
1266 | { | |
1267 | /* L3CR */ | |
1268 | /* XXX : not implemented */ | |
1269 | spr_register(env, SPR_L3CR, "L3CR", | |
1270 | SPR_NOACCESS, SPR_NOACCESS, | |
1271 | &spr_read_generic, &spr_write_generic, | |
1272 | 0x00000000); | |
1273 | /* L3ITCR0 */ | |
578bb252 | 1274 | /* XXX : not implemented */ |
a750fc0b JM |
1275 | spr_register(env, SPR_L3ITCR0, "L3ITCR0", |
1276 | SPR_NOACCESS, SPR_NOACCESS, | |
1277 | &spr_read_generic, &spr_write_generic, | |
1278 | 0x00000000); | |
a750fc0b | 1279 | /* L3PM */ |
578bb252 | 1280 | /* XXX : not implemented */ |
a750fc0b JM |
1281 | spr_register(env, SPR_L3PM, "L3PM", |
1282 | SPR_NOACCESS, SPR_NOACCESS, | |
1283 | &spr_read_generic, &spr_write_generic, | |
1284 | 0x00000000); | |
1285 | } | |
a750fc0b | 1286 | |
578bb252 | 1287 | static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
a750fc0b | 1288 | { |
f2e63a42 | 1289 | #if !defined(CONFIG_USER_ONLY) |
578bb252 JM |
1290 | env->nb_tlb = nb_tlbs; |
1291 | env->nb_ways = nb_ways; | |
1292 | env->id_tlbs = 1; | |
1293 | /* XXX : not implemented */ | |
a750fc0b JM |
1294 | spr_register(env, SPR_PTEHI, "PTEHI", |
1295 | SPR_NOACCESS, SPR_NOACCESS, | |
1296 | &spr_read_generic, &spr_write_generic, | |
1297 | 0x00000000); | |
578bb252 | 1298 | /* XXX : not implemented */ |
a750fc0b JM |
1299 | spr_register(env, SPR_PTELO, "PTELO", |
1300 | SPR_NOACCESS, SPR_NOACCESS, | |
1301 | &spr_read_generic, &spr_write_generic, | |
1302 | 0x00000000); | |
578bb252 | 1303 | /* XXX : not implemented */ |
a750fc0b JM |
1304 | spr_register(env, SPR_TLBMISS, "TLBMISS", |
1305 | SPR_NOACCESS, SPR_NOACCESS, | |
1306 | &spr_read_generic, &spr_write_generic, | |
1307 | 0x00000000); | |
f2e63a42 | 1308 | #endif |
76a66253 JM |
1309 | } |
1310 | ||
80d11f44 | 1311 | static void gen_spr_usprgh (CPUPPCState *env) |
76a66253 | 1312 | { |
80d11f44 JM |
1313 | spr_register(env, SPR_USPRG4, "USPRG4", |
1314 | &spr_read_ureg, SPR_NOACCESS, | |
1315 | &spr_read_ureg, SPR_NOACCESS, | |
1316 | 0x00000000); | |
1317 | spr_register(env, SPR_USPRG5, "USPRG5", | |
1318 | &spr_read_ureg, SPR_NOACCESS, | |
1319 | &spr_read_ureg, SPR_NOACCESS, | |
1320 | 0x00000000); | |
1321 | spr_register(env, SPR_USPRG6, "USPRG6", | |
1322 | &spr_read_ureg, SPR_NOACCESS, | |
1323 | &spr_read_ureg, SPR_NOACCESS, | |
1324 | 0x00000000); | |
1325 | spr_register(env, SPR_USPRG7, "USPRG7", | |
1326 | &spr_read_ureg, SPR_NOACCESS, | |
1327 | &spr_read_ureg, SPR_NOACCESS, | |
76a66253 | 1328 | 0x00000000); |
80d11f44 JM |
1329 | } |
1330 | ||
1331 | /* PowerPC BookE SPR */ | |
1332 | static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) | |
1333 | { | |
b55266b5 | 1334 | const char *ivor_names[64] = { |
80d11f44 JM |
1335 | "IVOR0", "IVOR1", "IVOR2", "IVOR3", |
1336 | "IVOR4", "IVOR5", "IVOR6", "IVOR7", | |
1337 | "IVOR8", "IVOR9", "IVOR10", "IVOR11", | |
1338 | "IVOR12", "IVOR13", "IVOR14", "IVOR15", | |
1339 | "IVOR16", "IVOR17", "IVOR18", "IVOR19", | |
1340 | "IVOR20", "IVOR21", "IVOR22", "IVOR23", | |
1341 | "IVOR24", "IVOR25", "IVOR26", "IVOR27", | |
1342 | "IVOR28", "IVOR29", "IVOR30", "IVOR31", | |
1343 | "IVOR32", "IVOR33", "IVOR34", "IVOR35", | |
1344 | "IVOR36", "IVOR37", "IVOR38", "IVOR39", | |
1345 | "IVOR40", "IVOR41", "IVOR42", "IVOR43", | |
1346 | "IVOR44", "IVOR45", "IVOR46", "IVOR47", | |
1347 | "IVOR48", "IVOR49", "IVOR50", "IVOR51", | |
1348 | "IVOR52", "IVOR53", "IVOR54", "IVOR55", | |
1349 | "IVOR56", "IVOR57", "IVOR58", "IVOR59", | |
1350 | "IVOR60", "IVOR61", "IVOR62", "IVOR63", | |
1351 | }; | |
1352 | #define SPR_BOOKE_IVORxx (-1) | |
1353 | int ivor_sprn[64] = { | |
1354 | SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, | |
1355 | SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, | |
1356 | SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, | |
1357 | SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, | |
1358 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1359 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1360 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1361 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1362 | SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, | |
1363 | SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1364 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1365 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1366 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1367 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1368 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1369 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1370 | }; | |
1371 | int i; | |
1372 | ||
76a66253 | 1373 | /* Interrupt processing */ |
363be49c | 1374 | spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
76a66253 JM |
1375 | SPR_NOACCESS, SPR_NOACCESS, |
1376 | &spr_read_generic, &spr_write_generic, | |
1377 | 0x00000000); | |
363be49c JM |
1378 | spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
1379 | SPR_NOACCESS, SPR_NOACCESS, | |
1380 | &spr_read_generic, &spr_write_generic, | |
1381 | 0x00000000); | |
76a66253 JM |
1382 | /* Debug */ |
1383 | /* XXX : not implemented */ | |
1384 | spr_register(env, SPR_BOOKE_IAC1, "IAC1", | |
1385 | SPR_NOACCESS, SPR_NOACCESS, | |
1386 | &spr_read_generic, &spr_write_generic, | |
1387 | 0x00000000); | |
1388 | /* XXX : not implemented */ | |
1389 | spr_register(env, SPR_BOOKE_IAC2, "IAC2", | |
1390 | SPR_NOACCESS, SPR_NOACCESS, | |
1391 | &spr_read_generic, &spr_write_generic, | |
1392 | 0x00000000); | |
1393 | /* XXX : not implemented */ | |
76a66253 JM |
1394 | spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
1395 | SPR_NOACCESS, SPR_NOACCESS, | |
1396 | &spr_read_generic, &spr_write_generic, | |
1397 | 0x00000000); | |
1398 | /* XXX : not implemented */ | |
1399 | spr_register(env, SPR_BOOKE_DAC2, "DAC2", | |
1400 | SPR_NOACCESS, SPR_NOACCESS, | |
1401 | &spr_read_generic, &spr_write_generic, | |
1402 | 0x00000000); | |
1403 | /* XXX : not implemented */ | |
76a66253 JM |
1404 | spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
1405 | SPR_NOACCESS, SPR_NOACCESS, | |
1406 | &spr_read_generic, &spr_write_generic, | |
1407 | 0x00000000); | |
1408 | /* XXX : not implemented */ | |
1409 | spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", | |
1410 | SPR_NOACCESS, SPR_NOACCESS, | |
1411 | &spr_read_generic, &spr_write_generic, | |
1412 | 0x00000000); | |
1413 | /* XXX : not implemented */ | |
1414 | spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", | |
1415 | SPR_NOACCESS, SPR_NOACCESS, | |
1416 | &spr_read_generic, &spr_write_generic, | |
1417 | 0x00000000); | |
1418 | /* XXX : not implemented */ | |
1419 | spr_register(env, SPR_BOOKE_DBSR, "DBSR", | |
1420 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 | 1421 | &spr_read_generic, &spr_write_clear, |
76a66253 JM |
1422 | 0x00000000); |
1423 | spr_register(env, SPR_BOOKE_DEAR, "DEAR", | |
1424 | SPR_NOACCESS, SPR_NOACCESS, | |
1425 | &spr_read_generic, &spr_write_generic, | |
1426 | 0x00000000); | |
1427 | spr_register(env, SPR_BOOKE_ESR, "ESR", | |
1428 | SPR_NOACCESS, SPR_NOACCESS, | |
1429 | &spr_read_generic, &spr_write_generic, | |
1430 | 0x00000000); | |
363be49c JM |
1431 | spr_register(env, SPR_BOOKE_IVPR, "IVPR", |
1432 | SPR_NOACCESS, SPR_NOACCESS, | |
6f5d427d | 1433 | &spr_read_generic, &spr_write_excp_prefix, |
363be49c JM |
1434 | 0x00000000); |
1435 | /* Exception vectors */ | |
80d11f44 JM |
1436 | for (i = 0; i < 64; i++) { |
1437 | if (ivor_mask & (1ULL << i)) { | |
1438 | if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { | |
1439 | fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); | |
1440 | exit(1); | |
1441 | } | |
1442 | spr_register(env, ivor_sprn[i], ivor_names[i], | |
1443 | SPR_NOACCESS, SPR_NOACCESS, | |
1444 | &spr_read_generic, &spr_write_excp_vector, | |
1445 | 0x00000000); | |
1446 | } | |
1447 | } | |
76a66253 JM |
1448 | spr_register(env, SPR_BOOKE_PID, "PID", |
1449 | SPR_NOACCESS, SPR_NOACCESS, | |
1450 | &spr_read_generic, &spr_write_generic, | |
1451 | 0x00000000); | |
1452 | spr_register(env, SPR_BOOKE_TCR, "TCR", | |
1453 | SPR_NOACCESS, SPR_NOACCESS, | |
1454 | &spr_read_generic, &spr_write_booke_tcr, | |
1455 | 0x00000000); | |
1456 | spr_register(env, SPR_BOOKE_TSR, "TSR", | |
1457 | SPR_NOACCESS, SPR_NOACCESS, | |
1458 | &spr_read_generic, &spr_write_booke_tsr, | |
1459 | 0x00000000); | |
1460 | /* Timer */ | |
1461 | spr_register(env, SPR_DECR, "DECR", | |
1462 | SPR_NOACCESS, SPR_NOACCESS, | |
1463 | &spr_read_decr, &spr_write_decr, | |
1464 | 0x00000000); | |
1465 | spr_register(env, SPR_BOOKE_DECAR, "DECAR", | |
1466 | SPR_NOACCESS, SPR_NOACCESS, | |
1467 | SPR_NOACCESS, &spr_write_generic, | |
1468 | 0x00000000); | |
1469 | /* SPRGs */ | |
1470 | spr_register(env, SPR_USPRG0, "USPRG0", | |
1471 | &spr_read_generic, &spr_write_generic, | |
1472 | &spr_read_generic, &spr_write_generic, | |
1473 | 0x00000000); | |
1474 | spr_register(env, SPR_SPRG4, "SPRG4", | |
1475 | SPR_NOACCESS, SPR_NOACCESS, | |
1476 | &spr_read_generic, &spr_write_generic, | |
1477 | 0x00000000); | |
76a66253 JM |
1478 | spr_register(env, SPR_SPRG5, "SPRG5", |
1479 | SPR_NOACCESS, SPR_NOACCESS, | |
1480 | &spr_read_generic, &spr_write_generic, | |
1481 | 0x00000000); | |
76a66253 JM |
1482 | spr_register(env, SPR_SPRG6, "SPRG6", |
1483 | SPR_NOACCESS, SPR_NOACCESS, | |
1484 | &spr_read_generic, &spr_write_generic, | |
1485 | 0x00000000); | |
76a66253 JM |
1486 | spr_register(env, SPR_SPRG7, "SPRG7", |
1487 | SPR_NOACCESS, SPR_NOACCESS, | |
1488 | &spr_read_generic, &spr_write_generic, | |
1489 | 0x00000000); | |
76a66253 JM |
1490 | } |
1491 | ||
363be49c | 1492 | /* FSL storage control registers */ |
80d11f44 | 1493 | static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask) |
363be49c | 1494 | { |
f2e63a42 | 1495 | #if !defined(CONFIG_USER_ONLY) |
b55266b5 | 1496 | const char *mas_names[8] = { |
80d11f44 JM |
1497 | "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
1498 | }; | |
1499 | int mas_sprn[8] = { | |
1500 | SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, | |
1501 | SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, | |
1502 | }; | |
1503 | int i; | |
1504 | ||
363be49c | 1505 | /* TLB assist registers */ |
578bb252 | 1506 | /* XXX : not implemented */ |
80d11f44 JM |
1507 | for (i = 0; i < 8; i++) { |
1508 | if (mas_mask & (1 << i)) { | |
1509 | spr_register(env, mas_sprn[i], mas_names[i], | |
1510 | SPR_NOACCESS, SPR_NOACCESS, | |
1511 | &spr_read_generic, &spr_write_generic, | |
1512 | 0x00000000); | |
1513 | } | |
1514 | } | |
363be49c | 1515 | if (env->nb_pids > 1) { |
578bb252 | 1516 | /* XXX : not implemented */ |
363be49c JM |
1517 | spr_register(env, SPR_BOOKE_PID1, "PID1", |
1518 | SPR_NOACCESS, SPR_NOACCESS, | |
1519 | &spr_read_generic, &spr_write_generic, | |
1520 | 0x00000000); | |
1521 | } | |
1522 | if (env->nb_pids > 2) { | |
578bb252 | 1523 | /* XXX : not implemented */ |
363be49c JM |
1524 | spr_register(env, SPR_BOOKE_PID2, "PID2", |
1525 | SPR_NOACCESS, SPR_NOACCESS, | |
1526 | &spr_read_generic, &spr_write_generic, | |
1527 | 0x00000000); | |
1528 | } | |
578bb252 | 1529 | /* XXX : not implemented */ |
65f9ee8d | 1530 | spr_register(env, SPR_MMUCFG, "MMUCFG", |
363be49c JM |
1531 | SPR_NOACCESS, SPR_NOACCESS, |
1532 | &spr_read_generic, SPR_NOACCESS, | |
1533 | 0x00000000); /* TOFIX */ | |
578bb252 | 1534 | /* XXX : not implemented */ |
65f9ee8d | 1535 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", |
363be49c JM |
1536 | SPR_NOACCESS, SPR_NOACCESS, |
1537 | &spr_read_generic, &spr_write_generic, | |
1538 | 0x00000000); /* TOFIX */ | |
1539 | switch (env->nb_ways) { | |
1540 | case 4: | |
578bb252 | 1541 | /* XXX : not implemented */ |
363be49c JM |
1542 | spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", |
1543 | SPR_NOACCESS, SPR_NOACCESS, | |
1544 | &spr_read_generic, SPR_NOACCESS, | |
1545 | 0x00000000); /* TOFIX */ | |
1546 | /* Fallthru */ | |
1547 | case 3: | |
578bb252 | 1548 | /* XXX : not implemented */ |
363be49c JM |
1549 | spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", |
1550 | SPR_NOACCESS, SPR_NOACCESS, | |
1551 | &spr_read_generic, SPR_NOACCESS, | |
1552 | 0x00000000); /* TOFIX */ | |
1553 | /* Fallthru */ | |
1554 | case 2: | |
578bb252 | 1555 | /* XXX : not implemented */ |
363be49c JM |
1556 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", |
1557 | SPR_NOACCESS, SPR_NOACCESS, | |
1558 | &spr_read_generic, SPR_NOACCESS, | |
1559 | 0x00000000); /* TOFIX */ | |
1560 | /* Fallthru */ | |
1561 | case 1: | |
578bb252 | 1562 | /* XXX : not implemented */ |
363be49c JM |
1563 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", |
1564 | SPR_NOACCESS, SPR_NOACCESS, | |
1565 | &spr_read_generic, SPR_NOACCESS, | |
1566 | 0x00000000); /* TOFIX */ | |
1567 | /* Fallthru */ | |
1568 | case 0: | |
1569 | default: | |
1570 | break; | |
1571 | } | |
f2e63a42 | 1572 | #endif |
363be49c JM |
1573 | } |
1574 | ||
76a66253 JM |
1575 | /* SPR specific to PowerPC 440 implementation */ |
1576 | static void gen_spr_440 (CPUPPCState *env) | |
1577 | { | |
1578 | /* Cache control */ | |
1579 | /* XXX : not implemented */ | |
1580 | spr_register(env, SPR_440_DNV0, "DNV0", | |
1581 | SPR_NOACCESS, SPR_NOACCESS, | |
1582 | &spr_read_generic, &spr_write_generic, | |
1583 | 0x00000000); | |
1584 | /* XXX : not implemented */ | |
1585 | spr_register(env, SPR_440_DNV1, "DNV1", | |
1586 | SPR_NOACCESS, SPR_NOACCESS, | |
1587 | &spr_read_generic, &spr_write_generic, | |
1588 | 0x00000000); | |
1589 | /* XXX : not implemented */ | |
1590 | spr_register(env, SPR_440_DNV2, "DNV2", | |
1591 | SPR_NOACCESS, SPR_NOACCESS, | |
1592 | &spr_read_generic, &spr_write_generic, | |
1593 | 0x00000000); | |
1594 | /* XXX : not implemented */ | |
1595 | spr_register(env, SPR_440_DNV3, "DNV3", | |
1596 | SPR_NOACCESS, SPR_NOACCESS, | |
1597 | &spr_read_generic, &spr_write_generic, | |
1598 | 0x00000000); | |
1599 | /* XXX : not implemented */ | |
2662a059 | 1600 | spr_register(env, SPR_440_DTV0, "DTV0", |
76a66253 JM |
1601 | SPR_NOACCESS, SPR_NOACCESS, |
1602 | &spr_read_generic, &spr_write_generic, | |
1603 | 0x00000000); | |
1604 | /* XXX : not implemented */ | |
2662a059 | 1605 | spr_register(env, SPR_440_DTV1, "DTV1", |
76a66253 JM |
1606 | SPR_NOACCESS, SPR_NOACCESS, |
1607 | &spr_read_generic, &spr_write_generic, | |
1608 | 0x00000000); | |
1609 | /* XXX : not implemented */ | |
2662a059 | 1610 | spr_register(env, SPR_440_DTV2, "DTV2", |
76a66253 JM |
1611 | SPR_NOACCESS, SPR_NOACCESS, |
1612 | &spr_read_generic, &spr_write_generic, | |
1613 | 0x00000000); | |
1614 | /* XXX : not implemented */ | |
2662a059 | 1615 | spr_register(env, SPR_440_DTV3, "DTV3", |
76a66253 JM |
1616 | SPR_NOACCESS, SPR_NOACCESS, |
1617 | &spr_read_generic, &spr_write_generic, | |
1618 | 0x00000000); | |
1619 | /* XXX : not implemented */ | |
1620 | spr_register(env, SPR_440_DVLIM, "DVLIM", | |
1621 | SPR_NOACCESS, SPR_NOACCESS, | |
1622 | &spr_read_generic, &spr_write_generic, | |
1623 | 0x00000000); | |
1624 | /* XXX : not implemented */ | |
1625 | spr_register(env, SPR_440_INV0, "INV0", | |
1626 | SPR_NOACCESS, SPR_NOACCESS, | |
1627 | &spr_read_generic, &spr_write_generic, | |
1628 | 0x00000000); | |
1629 | /* XXX : not implemented */ | |
1630 | spr_register(env, SPR_440_INV1, "INV1", | |
1631 | SPR_NOACCESS, SPR_NOACCESS, | |
1632 | &spr_read_generic, &spr_write_generic, | |
1633 | 0x00000000); | |
1634 | /* XXX : not implemented */ | |
1635 | spr_register(env, SPR_440_INV2, "INV2", | |
1636 | SPR_NOACCESS, SPR_NOACCESS, | |
1637 | &spr_read_generic, &spr_write_generic, | |
1638 | 0x00000000); | |
1639 | /* XXX : not implemented */ | |
1640 | spr_register(env, SPR_440_INV3, "INV3", | |
1641 | SPR_NOACCESS, SPR_NOACCESS, | |
1642 | &spr_read_generic, &spr_write_generic, | |
1643 | 0x00000000); | |
1644 | /* XXX : not implemented */ | |
2662a059 | 1645 | spr_register(env, SPR_440_ITV0, "ITV0", |
76a66253 JM |
1646 | SPR_NOACCESS, SPR_NOACCESS, |
1647 | &spr_read_generic, &spr_write_generic, | |
1648 | 0x00000000); | |
1649 | /* XXX : not implemented */ | |
2662a059 | 1650 | spr_register(env, SPR_440_ITV1, "ITV1", |
76a66253 JM |
1651 | SPR_NOACCESS, SPR_NOACCESS, |
1652 | &spr_read_generic, &spr_write_generic, | |
1653 | 0x00000000); | |
1654 | /* XXX : not implemented */ | |
2662a059 | 1655 | spr_register(env, SPR_440_ITV2, "ITV2", |
76a66253 JM |
1656 | SPR_NOACCESS, SPR_NOACCESS, |
1657 | &spr_read_generic, &spr_write_generic, | |
1658 | 0x00000000); | |
1659 | /* XXX : not implemented */ | |
2662a059 | 1660 | spr_register(env, SPR_440_ITV3, "ITV3", |
76a66253 JM |
1661 | SPR_NOACCESS, SPR_NOACCESS, |
1662 | &spr_read_generic, &spr_write_generic, | |
1663 | 0x00000000); | |
1664 | /* XXX : not implemented */ | |
1665 | spr_register(env, SPR_440_IVLIM, "IVLIM", | |
1666 | SPR_NOACCESS, SPR_NOACCESS, | |
1667 | &spr_read_generic, &spr_write_generic, | |
1668 | 0x00000000); | |
1669 | /* Cache debug */ | |
1670 | /* XXX : not implemented */ | |
2662a059 | 1671 | spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", |
76a66253 JM |
1672 | SPR_NOACCESS, SPR_NOACCESS, |
1673 | &spr_read_generic, SPR_NOACCESS, | |
1674 | 0x00000000); | |
1675 | /* XXX : not implemented */ | |
2662a059 | 1676 | spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", |
76a66253 JM |
1677 | SPR_NOACCESS, SPR_NOACCESS, |
1678 | &spr_read_generic, SPR_NOACCESS, | |
1679 | 0x00000000); | |
1680 | /* XXX : not implemented */ | |
2662a059 | 1681 | spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
76a66253 JM |
1682 | SPR_NOACCESS, SPR_NOACCESS, |
1683 | &spr_read_generic, SPR_NOACCESS, | |
1684 | 0x00000000); | |
1685 | /* XXX : not implemented */ | |
2662a059 | 1686 | spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", |
76a66253 JM |
1687 | SPR_NOACCESS, SPR_NOACCESS, |
1688 | &spr_read_generic, SPR_NOACCESS, | |
1689 | 0x00000000); | |
1690 | /* XXX : not implemented */ | |
2662a059 | 1691 | spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", |
76a66253 JM |
1692 | SPR_NOACCESS, SPR_NOACCESS, |
1693 | &spr_read_generic, SPR_NOACCESS, | |
1694 | 0x00000000); | |
1695 | /* XXX : not implemented */ | |
1696 | spr_register(env, SPR_440_DBDR, "DBDR", | |
1697 | SPR_NOACCESS, SPR_NOACCESS, | |
1698 | &spr_read_generic, &spr_write_generic, | |
1699 | 0x00000000); | |
1700 | /* Processor control */ | |
1701 | spr_register(env, SPR_4xx_CCR0, "CCR0", | |
1702 | SPR_NOACCESS, SPR_NOACCESS, | |
1703 | &spr_read_generic, &spr_write_generic, | |
1704 | 0x00000000); | |
1705 | spr_register(env, SPR_440_RSTCFG, "RSTCFG", | |
1706 | SPR_NOACCESS, SPR_NOACCESS, | |
1707 | &spr_read_generic, SPR_NOACCESS, | |
1708 | 0x00000000); | |
1709 | /* Storage control */ | |
1710 | spr_register(env, SPR_440_MMUCR, "MMUCR", | |
1711 | SPR_NOACCESS, SPR_NOACCESS, | |
1712 | &spr_read_generic, &spr_write_generic, | |
1713 | 0x00000000); | |
1714 | } | |
1715 | ||
1716 | /* SPR shared between PowerPC 40x implementations */ | |
1717 | static void gen_spr_40x (CPUPPCState *env) | |
1718 | { | |
1719 | /* Cache */ | |
035feb88 | 1720 | /* not emulated, as Qemu do not emulate caches */ |
76a66253 JM |
1721 | spr_register(env, SPR_40x_DCCR, "DCCR", |
1722 | SPR_NOACCESS, SPR_NOACCESS, | |
1723 | &spr_read_generic, &spr_write_generic, | |
1724 | 0x00000000); | |
035feb88 | 1725 | /* not emulated, as Qemu do not emulate caches */ |
76a66253 JM |
1726 | spr_register(env, SPR_40x_ICCR, "ICCR", |
1727 | SPR_NOACCESS, SPR_NOACCESS, | |
1728 | &spr_read_generic, &spr_write_generic, | |
1729 | 0x00000000); | |
578bb252 | 1730 | /* not emulated, as Qemu do not emulate caches */ |
2662a059 | 1731 | spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
76a66253 JM |
1732 | SPR_NOACCESS, SPR_NOACCESS, |
1733 | &spr_read_generic, SPR_NOACCESS, | |
1734 | 0x00000000); | |
76a66253 JM |
1735 | /* Exception */ |
1736 | spr_register(env, SPR_40x_DEAR, "DEAR", | |
1737 | SPR_NOACCESS, SPR_NOACCESS, | |
1738 | &spr_read_generic, &spr_write_generic, | |
1739 | 0x00000000); | |
1740 | spr_register(env, SPR_40x_ESR, "ESR", | |
1741 | SPR_NOACCESS, SPR_NOACCESS, | |
1742 | &spr_read_generic, &spr_write_generic, | |
1743 | 0x00000000); | |
1744 | spr_register(env, SPR_40x_EVPR, "EVPR", | |
1745 | SPR_NOACCESS, SPR_NOACCESS, | |
6f5d427d | 1746 | &spr_read_generic, &spr_write_excp_prefix, |
76a66253 JM |
1747 | 0x00000000); |
1748 | spr_register(env, SPR_40x_SRR2, "SRR2", | |
1749 | &spr_read_generic, &spr_write_generic, | |
1750 | &spr_read_generic, &spr_write_generic, | |
1751 | 0x00000000); | |
1752 | spr_register(env, SPR_40x_SRR3, "SRR3", | |
1753 | &spr_read_generic, &spr_write_generic, | |
1754 | &spr_read_generic, &spr_write_generic, | |
1755 | 0x00000000); | |
1756 | /* Timers */ | |
1757 | spr_register(env, SPR_40x_PIT, "PIT", | |
1758 | SPR_NOACCESS, SPR_NOACCESS, | |
1759 | &spr_read_40x_pit, &spr_write_40x_pit, | |
1760 | 0x00000000); | |
1761 | spr_register(env, SPR_40x_TCR, "TCR", | |
1762 | SPR_NOACCESS, SPR_NOACCESS, | |
1763 | &spr_read_generic, &spr_write_booke_tcr, | |
1764 | 0x00000000); | |
1765 | spr_register(env, SPR_40x_TSR, "TSR", | |
1766 | SPR_NOACCESS, SPR_NOACCESS, | |
1767 | &spr_read_generic, &spr_write_booke_tsr, | |
1768 | 0x00000000); | |
2662a059 JM |
1769 | } |
1770 | ||
1771 | /* SPR specific to PowerPC 405 implementation */ | |
1772 | static void gen_spr_405 (CPUPPCState *env) | |
1773 | { | |
1774 | /* MMU */ | |
1775 | spr_register(env, SPR_40x_PID, "PID", | |
76a66253 JM |
1776 | SPR_NOACCESS, SPR_NOACCESS, |
1777 | &spr_read_generic, &spr_write_generic, | |
1778 | 0x00000000); | |
2662a059 | 1779 | spr_register(env, SPR_4xx_CCR0, "CCR0", |
76a66253 JM |
1780 | SPR_NOACCESS, SPR_NOACCESS, |
1781 | &spr_read_generic, &spr_write_generic, | |
2662a059 JM |
1782 | 0x00700000); |
1783 | /* Debug interface */ | |
76a66253 JM |
1784 | /* XXX : not implemented */ |
1785 | spr_register(env, SPR_40x_DBCR0, "DBCR0", | |
1786 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 | 1787 | &spr_read_generic, &spr_write_40x_dbcr0, |
76a66253 JM |
1788 | 0x00000000); |
1789 | /* XXX : not implemented */ | |
2662a059 JM |
1790 | spr_register(env, SPR_405_DBCR1, "DBCR1", |
1791 | SPR_NOACCESS, SPR_NOACCESS, | |
1792 | &spr_read_generic, &spr_write_generic, | |
1793 | 0x00000000); | |
1794 | /* XXX : not implemented */ | |
76a66253 JM |
1795 | spr_register(env, SPR_40x_DBSR, "DBSR", |
1796 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 JM |
1797 | &spr_read_generic, &spr_write_clear, |
1798 | /* Last reset was system reset */ | |
76a66253 JM |
1799 | 0x00000300); |
1800 | /* XXX : not implemented */ | |
2662a059 | 1801 | spr_register(env, SPR_40x_DAC1, "DAC1", |
76a66253 JM |
1802 | SPR_NOACCESS, SPR_NOACCESS, |
1803 | &spr_read_generic, &spr_write_generic, | |
1804 | 0x00000000); | |
2662a059 | 1805 | spr_register(env, SPR_40x_DAC2, "DAC2", |
76a66253 JM |
1806 | SPR_NOACCESS, SPR_NOACCESS, |
1807 | &spr_read_generic, &spr_write_generic, | |
1808 | 0x00000000); | |
2662a059 JM |
1809 | /* XXX : not implemented */ |
1810 | spr_register(env, SPR_405_DVC1, "DVC1", | |
76a66253 JM |
1811 | SPR_NOACCESS, SPR_NOACCESS, |
1812 | &spr_read_generic, &spr_write_generic, | |
2662a059 | 1813 | 0x00000000); |
76a66253 | 1814 | /* XXX : not implemented */ |
2662a059 | 1815 | spr_register(env, SPR_405_DVC2, "DVC2", |
76a66253 JM |
1816 | SPR_NOACCESS, SPR_NOACCESS, |
1817 | &spr_read_generic, &spr_write_generic, | |
1818 | 0x00000000); | |
1819 | /* XXX : not implemented */ | |
2662a059 | 1820 | spr_register(env, SPR_40x_IAC1, "IAC1", |
76a66253 JM |
1821 | SPR_NOACCESS, SPR_NOACCESS, |
1822 | &spr_read_generic, &spr_write_generic, | |
1823 | 0x00000000); | |
2662a059 | 1824 | spr_register(env, SPR_40x_IAC2, "IAC2", |
76a66253 JM |
1825 | SPR_NOACCESS, SPR_NOACCESS, |
1826 | &spr_read_generic, &spr_write_generic, | |
1827 | 0x00000000); | |
1828 | /* XXX : not implemented */ | |
1829 | spr_register(env, SPR_405_IAC3, "IAC3", | |
1830 | SPR_NOACCESS, SPR_NOACCESS, | |
1831 | &spr_read_generic, &spr_write_generic, | |
1832 | 0x00000000); | |
1833 | /* XXX : not implemented */ | |
1834 | spr_register(env, SPR_405_IAC4, "IAC4", | |
1835 | SPR_NOACCESS, SPR_NOACCESS, | |
1836 | &spr_read_generic, &spr_write_generic, | |
1837 | 0x00000000); | |
1838 | /* Storage control */ | |
035feb88 | 1839 | /* XXX: TODO: not implemented */ |
76a66253 JM |
1840 | spr_register(env, SPR_405_SLER, "SLER", |
1841 | SPR_NOACCESS, SPR_NOACCESS, | |
c294fc58 | 1842 | &spr_read_generic, &spr_write_40x_sler, |
76a66253 | 1843 | 0x00000000); |
2662a059 JM |
1844 | spr_register(env, SPR_40x_ZPR, "ZPR", |
1845 | SPR_NOACCESS, SPR_NOACCESS, | |
1846 | &spr_read_generic, &spr_write_generic, | |
1847 | 0x00000000); | |
76a66253 JM |
1848 | /* XXX : not implemented */ |
1849 | spr_register(env, SPR_405_SU0R, "SU0R", | |
1850 | SPR_NOACCESS, SPR_NOACCESS, | |
1851 | &spr_read_generic, &spr_write_generic, | |
1852 | 0x00000000); | |
1853 | /* SPRG */ | |
1854 | spr_register(env, SPR_USPRG0, "USPRG0", | |
1855 | &spr_read_ureg, SPR_NOACCESS, | |
1856 | &spr_read_ureg, SPR_NOACCESS, | |
1857 | 0x00000000); | |
1858 | spr_register(env, SPR_SPRG4, "SPRG4", | |
1859 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 1860 | &spr_read_generic, &spr_write_generic, |
76a66253 | 1861 | 0x00000000); |
76a66253 JM |
1862 | spr_register(env, SPR_SPRG5, "SPRG5", |
1863 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 1864 | spr_read_generic, &spr_write_generic, |
76a66253 | 1865 | 0x00000000); |
76a66253 JM |
1866 | spr_register(env, SPR_SPRG6, "SPRG6", |
1867 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 1868 | spr_read_generic, &spr_write_generic, |
76a66253 | 1869 | 0x00000000); |
76a66253 JM |
1870 | spr_register(env, SPR_SPRG7, "SPRG7", |
1871 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 1872 | spr_read_generic, &spr_write_generic, |
76a66253 | 1873 | 0x00000000); |
80d11f44 | 1874 | gen_spr_usprgh(env); |
76a66253 JM |
1875 | } |
1876 | ||
1877 | /* SPR shared between PowerPC 401 & 403 implementations */ | |
1878 | static void gen_spr_401_403 (CPUPPCState *env) | |
1879 | { | |
1880 | /* Time base */ | |
1881 | spr_register(env, SPR_403_VTBL, "TBL", | |
1882 | &spr_read_tbl, SPR_NOACCESS, | |
1883 | &spr_read_tbl, SPR_NOACCESS, | |
1884 | 0x00000000); | |
1885 | spr_register(env, SPR_403_TBL, "TBL", | |
1886 | SPR_NOACCESS, SPR_NOACCESS, | |
1887 | SPR_NOACCESS, &spr_write_tbl, | |
1888 | 0x00000000); | |
1889 | spr_register(env, SPR_403_VTBU, "TBU", | |
1890 | &spr_read_tbu, SPR_NOACCESS, | |
1891 | &spr_read_tbu, SPR_NOACCESS, | |
1892 | 0x00000000); | |
1893 | spr_register(env, SPR_403_TBU, "TBU", | |
1894 | SPR_NOACCESS, SPR_NOACCESS, | |
1895 | SPR_NOACCESS, &spr_write_tbu, | |
1896 | 0x00000000); | |
1897 | /* Debug */ | |
578bb252 | 1898 | /* not emulated, as Qemu do not emulate caches */ |
76a66253 JM |
1899 | spr_register(env, SPR_403_CDBCR, "CDBCR", |
1900 | SPR_NOACCESS, SPR_NOACCESS, | |
1901 | &spr_read_generic, &spr_write_generic, | |
1902 | 0x00000000); | |
1903 | } | |
1904 | ||
2662a059 JM |
1905 | /* SPR specific to PowerPC 401 implementation */ |
1906 | static void gen_spr_401 (CPUPPCState *env) | |
1907 | { | |
1908 | /* Debug interface */ | |
1909 | /* XXX : not implemented */ | |
1910 | spr_register(env, SPR_40x_DBCR0, "DBCR", | |
1911 | SPR_NOACCESS, SPR_NOACCESS, | |
1912 | &spr_read_generic, &spr_write_40x_dbcr0, | |
1913 | 0x00000000); | |
1914 | /* XXX : not implemented */ | |
1915 | spr_register(env, SPR_40x_DBSR, "DBSR", | |
1916 | SPR_NOACCESS, SPR_NOACCESS, | |
1917 | &spr_read_generic, &spr_write_clear, | |
1918 | /* Last reset was system reset */ | |
1919 | 0x00000300); | |
1920 | /* XXX : not implemented */ | |
1921 | spr_register(env, SPR_40x_DAC1, "DAC", | |
1922 | SPR_NOACCESS, SPR_NOACCESS, | |
1923 | &spr_read_generic, &spr_write_generic, | |
1924 | 0x00000000); | |
1925 | /* XXX : not implemented */ | |
1926 | spr_register(env, SPR_40x_IAC1, "IAC", | |
1927 | SPR_NOACCESS, SPR_NOACCESS, | |
1928 | &spr_read_generic, &spr_write_generic, | |
1929 | 0x00000000); | |
1930 | /* Storage control */ | |
035feb88 | 1931 | /* XXX: TODO: not implemented */ |
2662a059 JM |
1932 | spr_register(env, SPR_405_SLER, "SLER", |
1933 | SPR_NOACCESS, SPR_NOACCESS, | |
1934 | &spr_read_generic, &spr_write_40x_sler, | |
1935 | 0x00000000); | |
035feb88 JM |
1936 | /* not emulated, as Qemu never does speculative access */ |
1937 | spr_register(env, SPR_40x_SGR, "SGR", | |
1938 | SPR_NOACCESS, SPR_NOACCESS, | |
1939 | &spr_read_generic, &spr_write_generic, | |
1940 | 0xFFFFFFFF); | |
1941 | /* not emulated, as Qemu do not emulate caches */ | |
1942 | spr_register(env, SPR_40x_DCWR, "DCWR", | |
1943 | SPR_NOACCESS, SPR_NOACCESS, | |
1944 | &spr_read_generic, &spr_write_generic, | |
1945 | 0x00000000); | |
2662a059 JM |
1946 | } |
1947 | ||
a750fc0b JM |
1948 | static void gen_spr_401x2 (CPUPPCState *env) |
1949 | { | |
1950 | gen_spr_401(env); | |
1951 | spr_register(env, SPR_40x_PID, "PID", | |
1952 | SPR_NOACCESS, SPR_NOACCESS, | |
1953 | &spr_read_generic, &spr_write_generic, | |
1954 | 0x00000000); | |
1955 | spr_register(env, SPR_40x_ZPR, "ZPR", | |
1956 | SPR_NOACCESS, SPR_NOACCESS, | |
1957 | &spr_read_generic, &spr_write_generic, | |
1958 | 0x00000000); | |
1959 | } | |
1960 | ||
76a66253 JM |
1961 | /* SPR specific to PowerPC 403 implementation */ |
1962 | static void gen_spr_403 (CPUPPCState *env) | |
1963 | { | |
2662a059 JM |
1964 | /* Debug interface */ |
1965 | /* XXX : not implemented */ | |
1966 | spr_register(env, SPR_40x_DBCR0, "DBCR0", | |
1967 | SPR_NOACCESS, SPR_NOACCESS, | |
1968 | &spr_read_generic, &spr_write_40x_dbcr0, | |
1969 | 0x00000000); | |
1970 | /* XXX : not implemented */ | |
1971 | spr_register(env, SPR_40x_DBSR, "DBSR", | |
1972 | SPR_NOACCESS, SPR_NOACCESS, | |
1973 | &spr_read_generic, &spr_write_clear, | |
1974 | /* Last reset was system reset */ | |
1975 | 0x00000300); | |
1976 | /* XXX : not implemented */ | |
1977 | spr_register(env, SPR_40x_DAC1, "DAC1", | |
1978 | SPR_NOACCESS, SPR_NOACCESS, | |
1979 | &spr_read_generic, &spr_write_generic, | |
1980 | 0x00000000); | |
578bb252 | 1981 | /* XXX : not implemented */ |
2662a059 JM |
1982 | spr_register(env, SPR_40x_DAC2, "DAC2", |
1983 | SPR_NOACCESS, SPR_NOACCESS, | |
1984 | &spr_read_generic, &spr_write_generic, | |
1985 | 0x00000000); | |
1986 | /* XXX : not implemented */ | |
1987 | spr_register(env, SPR_40x_IAC1, "IAC1", | |
1988 | SPR_NOACCESS, SPR_NOACCESS, | |
1989 | &spr_read_generic, &spr_write_generic, | |
1990 | 0x00000000); | |
578bb252 | 1991 | /* XXX : not implemented */ |
2662a059 JM |
1992 | spr_register(env, SPR_40x_IAC2, "IAC2", |
1993 | SPR_NOACCESS, SPR_NOACCESS, | |
1994 | &spr_read_generic, &spr_write_generic, | |
1995 | 0x00000000); | |
a750fc0b JM |
1996 | } |
1997 | ||
1998 | static void gen_spr_403_real (CPUPPCState *env) | |
1999 | { | |
76a66253 JM |
2000 | spr_register(env, SPR_403_PBL1, "PBL1", |
2001 | SPR_NOACCESS, SPR_NOACCESS, | |
2002 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2003 | 0x00000000); | |
2004 | spr_register(env, SPR_403_PBU1, "PBU1", | |
2005 | SPR_NOACCESS, SPR_NOACCESS, | |
2006 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2007 | 0x00000000); | |
2008 | spr_register(env, SPR_403_PBL2, "PBL2", | |
2009 | SPR_NOACCESS, SPR_NOACCESS, | |
2010 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2011 | 0x00000000); | |
2012 | spr_register(env, SPR_403_PBU2, "PBU2", | |
2013 | SPR_NOACCESS, SPR_NOACCESS, | |
2014 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2015 | 0x00000000); | |
a750fc0b JM |
2016 | } |
2017 | ||
2018 | static void gen_spr_403_mmu (CPUPPCState *env) | |
2019 | { | |
2020 | /* MMU */ | |
2021 | spr_register(env, SPR_40x_PID, "PID", | |
2022 | SPR_NOACCESS, SPR_NOACCESS, | |
2023 | &spr_read_generic, &spr_write_generic, | |
2024 | 0x00000000); | |
2662a059 | 2025 | spr_register(env, SPR_40x_ZPR, "ZPR", |
76a66253 JM |
2026 | SPR_NOACCESS, SPR_NOACCESS, |
2027 | &spr_read_generic, &spr_write_generic, | |
2028 | 0x00000000); | |
2029 | } | |
2030 | ||
2031 | /* SPR specific to PowerPC compression coprocessor extension */ | |
76a66253 JM |
2032 | static void gen_spr_compress (CPUPPCState *env) |
2033 | { | |
578bb252 | 2034 | /* XXX : not implemented */ |
76a66253 JM |
2035 | spr_register(env, SPR_401_SKR, "SKR", |
2036 | SPR_NOACCESS, SPR_NOACCESS, | |
2037 | &spr_read_generic, &spr_write_generic, | |
2038 | 0x00000000); | |
2039 | } | |
a750fc0b JM |
2040 | |
2041 | #if defined (TARGET_PPC64) | |
a750fc0b JM |
2042 | /* SPR specific to PowerPC 620 */ |
2043 | static void gen_spr_620 (CPUPPCState *env) | |
2044 | { | |
082c6681 JM |
2045 | /* Processor identification */ |
2046 | spr_register(env, SPR_PIR, "PIR", | |
2047 | SPR_NOACCESS, SPR_NOACCESS, | |
2048 | &spr_read_generic, &spr_write_pir, | |
2049 | 0x00000000); | |
2050 | spr_register(env, SPR_ASR, "ASR", | |
2051 | SPR_NOACCESS, SPR_NOACCESS, | |
2052 | &spr_read_asr, &spr_write_asr, | |
2053 | 0x00000000); | |
2054 | /* Breakpoints */ | |
2055 | /* XXX : not implemented */ | |
2056 | spr_register(env, SPR_IABR, "IABR", | |
2057 | SPR_NOACCESS, SPR_NOACCESS, | |
2058 | &spr_read_generic, &spr_write_generic, | |
2059 | 0x00000000); | |
2060 | /* XXX : not implemented */ | |
2061 | spr_register(env, SPR_DABR, "DABR", | |
2062 | SPR_NOACCESS, SPR_NOACCESS, | |
2063 | &spr_read_generic, &spr_write_generic, | |
2064 | 0x00000000); | |
2065 | /* XXX : not implemented */ | |
2066 | spr_register(env, SPR_SIAR, "SIAR", | |
2067 | SPR_NOACCESS, SPR_NOACCESS, | |
2068 | &spr_read_generic, SPR_NOACCESS, | |
2069 | 0x00000000); | |
2070 | /* XXX : not implemented */ | |
2071 | spr_register(env, SPR_SDA, "SDA", | |
2072 | SPR_NOACCESS, SPR_NOACCESS, | |
2073 | &spr_read_generic, SPR_NOACCESS, | |
2074 | 0x00000000); | |
2075 | /* XXX : not implemented */ | |
2076 | spr_register(env, SPR_620_PMC1R, "PMC1", | |
2077 | SPR_NOACCESS, SPR_NOACCESS, | |
2078 | &spr_read_generic, SPR_NOACCESS, | |
2079 | 0x00000000); | |
2080 | spr_register(env, SPR_620_PMC1W, "PMC1", | |
2081 | SPR_NOACCESS, SPR_NOACCESS, | |
2082 | SPR_NOACCESS, &spr_write_generic, | |
2083 | 0x00000000); | |
2084 | /* XXX : not implemented */ | |
2085 | spr_register(env, SPR_620_PMC2R, "PMC2", | |
2086 | SPR_NOACCESS, SPR_NOACCESS, | |
2087 | &spr_read_generic, SPR_NOACCESS, | |
2088 | 0x00000000); | |
2089 | spr_register(env, SPR_620_PMC2W, "PMC2", | |
2090 | SPR_NOACCESS, SPR_NOACCESS, | |
2091 | SPR_NOACCESS, &spr_write_generic, | |
2092 | 0x00000000); | |
2093 | /* XXX : not implemented */ | |
2094 | spr_register(env, SPR_620_MMCR0R, "MMCR0", | |
2095 | SPR_NOACCESS, SPR_NOACCESS, | |
2096 | &spr_read_generic, SPR_NOACCESS, | |
2097 | 0x00000000); | |
2098 | spr_register(env, SPR_620_MMCR0W, "MMCR0", | |
2099 | SPR_NOACCESS, SPR_NOACCESS, | |
2100 | SPR_NOACCESS, &spr_write_generic, | |
2101 | 0x00000000); | |
2102 | /* External access control */ | |
2103 | /* XXX : not implemented */ | |
2104 | spr_register(env, SPR_EAR, "EAR", | |
2105 | SPR_NOACCESS, SPR_NOACCESS, | |
2106 | &spr_read_generic, &spr_write_generic, | |
2107 | 0x00000000); | |
2108 | #if 0 // XXX: check this | |
578bb252 | 2109 | /* XXX : not implemented */ |
a750fc0b JM |
2110 | spr_register(env, SPR_620_PMR0, "PMR0", |
2111 | SPR_NOACCESS, SPR_NOACCESS, | |
2112 | &spr_read_generic, &spr_write_generic, | |
2113 | 0x00000000); | |
578bb252 | 2114 | /* XXX : not implemented */ |
a750fc0b JM |
2115 | spr_register(env, SPR_620_PMR1, "PMR1", |
2116 | SPR_NOACCESS, SPR_NOACCESS, | |
2117 | &spr_read_generic, &spr_write_generic, | |
2118 | 0x00000000); | |
578bb252 | 2119 | /* XXX : not implemented */ |
a750fc0b JM |
2120 | spr_register(env, SPR_620_PMR2, "PMR2", |
2121 | SPR_NOACCESS, SPR_NOACCESS, | |
2122 | &spr_read_generic, &spr_write_generic, | |
2123 | 0x00000000); | |
578bb252 | 2124 | /* XXX : not implemented */ |
a750fc0b JM |
2125 | spr_register(env, SPR_620_PMR3, "PMR3", |
2126 | SPR_NOACCESS, SPR_NOACCESS, | |
2127 | &spr_read_generic, &spr_write_generic, | |
2128 | 0x00000000); | |
578bb252 | 2129 | /* XXX : not implemented */ |
a750fc0b JM |
2130 | spr_register(env, SPR_620_PMR4, "PMR4", |
2131 | SPR_NOACCESS, SPR_NOACCESS, | |
2132 | &spr_read_generic, &spr_write_generic, | |
2133 | 0x00000000); | |
578bb252 | 2134 | /* XXX : not implemented */ |
a750fc0b JM |
2135 | spr_register(env, SPR_620_PMR5, "PMR5", |
2136 | SPR_NOACCESS, SPR_NOACCESS, | |
2137 | &spr_read_generic, &spr_write_generic, | |
2138 | 0x00000000); | |
578bb252 | 2139 | /* XXX : not implemented */ |
a750fc0b JM |
2140 | spr_register(env, SPR_620_PMR6, "PMR6", |
2141 | SPR_NOACCESS, SPR_NOACCESS, | |
2142 | &spr_read_generic, &spr_write_generic, | |
2143 | 0x00000000); | |
578bb252 | 2144 | /* XXX : not implemented */ |
a750fc0b JM |
2145 | spr_register(env, SPR_620_PMR7, "PMR7", |
2146 | SPR_NOACCESS, SPR_NOACCESS, | |
2147 | &spr_read_generic, &spr_write_generic, | |
2148 | 0x00000000); | |
578bb252 | 2149 | /* XXX : not implemented */ |
a750fc0b JM |
2150 | spr_register(env, SPR_620_PMR8, "PMR8", |
2151 | SPR_NOACCESS, SPR_NOACCESS, | |
2152 | &spr_read_generic, &spr_write_generic, | |
2153 | 0x00000000); | |
578bb252 | 2154 | /* XXX : not implemented */ |
a750fc0b JM |
2155 | spr_register(env, SPR_620_PMR9, "PMR9", |
2156 | SPR_NOACCESS, SPR_NOACCESS, | |
2157 | &spr_read_generic, &spr_write_generic, | |
2158 | 0x00000000); | |
578bb252 | 2159 | /* XXX : not implemented */ |
a750fc0b JM |
2160 | spr_register(env, SPR_620_PMRA, "PMR10", |
2161 | SPR_NOACCESS, SPR_NOACCESS, | |
2162 | &spr_read_generic, &spr_write_generic, | |
2163 | 0x00000000); | |
578bb252 | 2164 | /* XXX : not implemented */ |
a750fc0b JM |
2165 | spr_register(env, SPR_620_PMRB, "PMR11", |
2166 | SPR_NOACCESS, SPR_NOACCESS, | |
2167 | &spr_read_generic, &spr_write_generic, | |
2168 | 0x00000000); | |
578bb252 | 2169 | /* XXX : not implemented */ |
a750fc0b JM |
2170 | spr_register(env, SPR_620_PMRC, "PMR12", |
2171 | SPR_NOACCESS, SPR_NOACCESS, | |
2172 | &spr_read_generic, &spr_write_generic, | |
2173 | 0x00000000); | |
578bb252 | 2174 | /* XXX : not implemented */ |
a750fc0b JM |
2175 | spr_register(env, SPR_620_PMRD, "PMR13", |
2176 | SPR_NOACCESS, SPR_NOACCESS, | |
2177 | &spr_read_generic, &spr_write_generic, | |
2178 | 0x00000000); | |
578bb252 | 2179 | /* XXX : not implemented */ |
a750fc0b JM |
2180 | spr_register(env, SPR_620_PMRE, "PMR14", |
2181 | SPR_NOACCESS, SPR_NOACCESS, | |
2182 | &spr_read_generic, &spr_write_generic, | |
2183 | 0x00000000); | |
578bb252 | 2184 | /* XXX : not implemented */ |
a750fc0b JM |
2185 | spr_register(env, SPR_620_PMRF, "PMR15", |
2186 | SPR_NOACCESS, SPR_NOACCESS, | |
2187 | &spr_read_generic, &spr_write_generic, | |
2188 | 0x00000000); | |
082c6681 | 2189 | #endif |
578bb252 | 2190 | /* XXX : not implemented */ |
082c6681 | 2191 | spr_register(env, SPR_620_BUSCSR, "BUSCSR", |
a750fc0b JM |
2192 | SPR_NOACCESS, SPR_NOACCESS, |
2193 | &spr_read_generic, &spr_write_generic, | |
2194 | 0x00000000); | |
578bb252 | 2195 | /* XXX : not implemented */ |
082c6681 JM |
2196 | spr_register(env, SPR_620_L2CR, "L2CR", |
2197 | SPR_NOACCESS, SPR_NOACCESS, | |
2198 | &spr_read_generic, &spr_write_generic, | |
2199 | 0x00000000); | |
2200 | /* XXX : not implemented */ | |
2201 | spr_register(env, SPR_620_L2SR, "L2SR", | |
a750fc0b JM |
2202 | SPR_NOACCESS, SPR_NOACCESS, |
2203 | &spr_read_generic, &spr_write_generic, | |
2204 | 0x00000000); | |
2205 | } | |
a750fc0b | 2206 | #endif /* defined (TARGET_PPC64) */ |
76a66253 | 2207 | |
80d11f44 | 2208 | static void gen_spr_5xx_8xx (CPUPPCState *env) |
e1833e1f | 2209 | { |
80d11f44 JM |
2210 | /* Exception processing */ |
2211 | spr_register(env, SPR_DSISR, "DSISR", | |
2212 | SPR_NOACCESS, SPR_NOACCESS, | |
2213 | &spr_read_generic, &spr_write_generic, | |
2214 | 0x00000000); | |
2215 | spr_register(env, SPR_DAR, "DAR", | |
2216 | SPR_NOACCESS, SPR_NOACCESS, | |
2217 | &spr_read_generic, &spr_write_generic, | |
2218 | 0x00000000); | |
2219 | /* Timer */ | |
2220 | spr_register(env, SPR_DECR, "DECR", | |
2221 | SPR_NOACCESS, SPR_NOACCESS, | |
2222 | &spr_read_decr, &spr_write_decr, | |
2223 | 0x00000000); | |
2224 | /* XXX : not implemented */ | |
2225 | spr_register(env, SPR_MPC_EIE, "EIE", | |
2226 | SPR_NOACCESS, SPR_NOACCESS, | |
2227 | &spr_read_generic, &spr_write_generic, | |
2228 | 0x00000000); | |
2229 | /* XXX : not implemented */ | |
2230 | spr_register(env, SPR_MPC_EID, "EID", | |
2231 | SPR_NOACCESS, SPR_NOACCESS, | |
2232 | &spr_read_generic, &spr_write_generic, | |
2233 | 0x00000000); | |
2234 | /* XXX : not implemented */ | |
2235 | spr_register(env, SPR_MPC_NRI, "NRI", | |
2236 | SPR_NOACCESS, SPR_NOACCESS, | |
2237 | &spr_read_generic, &spr_write_generic, | |
2238 | 0x00000000); | |
2239 | /* XXX : not implemented */ | |
2240 | spr_register(env, SPR_MPC_CMPA, "CMPA", | |
2241 | SPR_NOACCESS, SPR_NOACCESS, | |
2242 | &spr_read_generic, &spr_write_generic, | |
2243 | 0x00000000); | |
2244 | /* XXX : not implemented */ | |
2245 | spr_register(env, SPR_MPC_CMPB, "CMPB", | |
2246 | SPR_NOACCESS, SPR_NOACCESS, | |
2247 | &spr_read_generic, &spr_write_generic, | |
2248 | 0x00000000); | |
2249 | /* XXX : not implemented */ | |
2250 | spr_register(env, SPR_MPC_CMPC, "CMPC", | |
2251 | SPR_NOACCESS, SPR_NOACCESS, | |
2252 | &spr_read_generic, &spr_write_generic, | |
2253 | 0x00000000); | |
2254 | /* XXX : not implemented */ | |
2255 | spr_register(env, SPR_MPC_CMPD, "CMPD", | |
2256 | SPR_NOACCESS, SPR_NOACCESS, | |
2257 | &spr_read_generic, &spr_write_generic, | |
2258 | 0x00000000); | |
2259 | /* XXX : not implemented */ | |
2260 | spr_register(env, SPR_MPC_ECR, "ECR", | |
2261 | SPR_NOACCESS, SPR_NOACCESS, | |
2262 | &spr_read_generic, &spr_write_generic, | |
2263 | 0x00000000); | |
2264 | /* XXX : not implemented */ | |
2265 | spr_register(env, SPR_MPC_DER, "DER", | |
2266 | SPR_NOACCESS, SPR_NOACCESS, | |
2267 | &spr_read_generic, &spr_write_generic, | |
2268 | 0x00000000); | |
2269 | /* XXX : not implemented */ | |
2270 | spr_register(env, SPR_MPC_COUNTA, "COUNTA", | |
2271 | SPR_NOACCESS, SPR_NOACCESS, | |
2272 | &spr_read_generic, &spr_write_generic, | |
2273 | 0x00000000); | |
2274 | /* XXX : not implemented */ | |
2275 | spr_register(env, SPR_MPC_COUNTB, "COUNTB", | |
2276 | SPR_NOACCESS, SPR_NOACCESS, | |
2277 | &spr_read_generic, &spr_write_generic, | |
2278 | 0x00000000); | |
2279 | /* XXX : not implemented */ | |
2280 | spr_register(env, SPR_MPC_CMPE, "CMPE", | |
2281 | SPR_NOACCESS, SPR_NOACCESS, | |
2282 | &spr_read_generic, &spr_write_generic, | |
2283 | 0x00000000); | |
2284 | /* XXX : not implemented */ | |
2285 | spr_register(env, SPR_MPC_CMPF, "CMPF", | |
2286 | SPR_NOACCESS, SPR_NOACCESS, | |
2287 | &spr_read_generic, &spr_write_generic, | |
2288 | 0x00000000); | |
2289 | /* XXX : not implemented */ | |
2290 | spr_register(env, SPR_MPC_CMPG, "CMPG", | |
2291 | SPR_NOACCESS, SPR_NOACCESS, | |
2292 | &spr_read_generic, &spr_write_generic, | |
2293 | 0x00000000); | |
2294 | /* XXX : not implemented */ | |
2295 | spr_register(env, SPR_MPC_CMPH, "CMPH", | |
2296 | SPR_NOACCESS, SPR_NOACCESS, | |
2297 | &spr_read_generic, &spr_write_generic, | |
2298 | 0x00000000); | |
2299 | /* XXX : not implemented */ | |
2300 | spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", | |
2301 | SPR_NOACCESS, SPR_NOACCESS, | |
2302 | &spr_read_generic, &spr_write_generic, | |
2303 | 0x00000000); | |
2304 | /* XXX : not implemented */ | |
2305 | spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", | |
2306 | SPR_NOACCESS, SPR_NOACCESS, | |
2307 | &spr_read_generic, &spr_write_generic, | |
2308 | 0x00000000); | |
2309 | /* XXX : not implemented */ | |
2310 | spr_register(env, SPR_MPC_BAR, "BAR", | |
2311 | SPR_NOACCESS, SPR_NOACCESS, | |
2312 | &spr_read_generic, &spr_write_generic, | |
2313 | 0x00000000); | |
2314 | /* XXX : not implemented */ | |
2315 | spr_register(env, SPR_MPC_DPDR, "DPDR", | |
2316 | SPR_NOACCESS, SPR_NOACCESS, | |
2317 | &spr_read_generic, &spr_write_generic, | |
2318 | 0x00000000); | |
2319 | /* XXX : not implemented */ | |
2320 | spr_register(env, SPR_MPC_IMMR, "IMMR", | |
2321 | SPR_NOACCESS, SPR_NOACCESS, | |
2322 | &spr_read_generic, &spr_write_generic, | |
2323 | 0x00000000); | |
2324 | } | |
2325 | ||
2326 | static void gen_spr_5xx (CPUPPCState *env) | |
2327 | { | |
2328 | /* XXX : not implemented */ | |
2329 | spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", | |
2330 | SPR_NOACCESS, SPR_NOACCESS, | |
2331 | &spr_read_generic, &spr_write_generic, | |
2332 | 0x00000000); | |
2333 | /* XXX : not implemented */ | |
2334 | spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", | |
2335 | SPR_NOACCESS, SPR_NOACCESS, | |
2336 | &spr_read_generic, &spr_write_generic, | |
2337 | 0x00000000); | |
2338 | /* XXX : not implemented */ | |
2339 | spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", | |
2340 | SPR_NOACCESS, SPR_NOACCESS, | |
2341 | &spr_read_generic, &spr_write_generic, | |
2342 | 0x00000000); | |
2343 | /* XXX : not implemented */ | |
2344 | spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", | |
2345 | SPR_NOACCESS, SPR_NOACCESS, | |
2346 | &spr_read_generic, &spr_write_generic, | |
2347 | 0x00000000); | |
2348 | /* XXX : not implemented */ | |
2349 | spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", | |
2350 | SPR_NOACCESS, SPR_NOACCESS, | |
2351 | &spr_read_generic, &spr_write_generic, | |
2352 | 0x00000000); | |
2353 | /* XXX : not implemented */ | |
2354 | spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", | |
2355 | SPR_NOACCESS, SPR_NOACCESS, | |
2356 | &spr_read_generic, &spr_write_generic, | |
2357 | 0x00000000); | |
2358 | /* XXX : not implemented */ | |
2359 | spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", | |
2360 | SPR_NOACCESS, SPR_NOACCESS, | |
2361 | &spr_read_generic, &spr_write_generic, | |
2362 | 0x00000000); | |
2363 | /* XXX : not implemented */ | |
2364 | spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", | |
2365 | SPR_NOACCESS, SPR_NOACCESS, | |
2366 | &spr_read_generic, &spr_write_generic, | |
2367 | 0x00000000); | |
2368 | /* XXX : not implemented */ | |
2369 | spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", | |
2370 | SPR_NOACCESS, SPR_NOACCESS, | |
2371 | &spr_read_generic, &spr_write_generic, | |
2372 | 0x00000000); | |
2373 | /* XXX : not implemented */ | |
2374 | spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", | |
2375 | SPR_NOACCESS, SPR_NOACCESS, | |
2376 | &spr_read_generic, &spr_write_generic, | |
2377 | 0x00000000); | |
2378 | /* XXX : not implemented */ | |
2379 | spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", | |
2380 | SPR_NOACCESS, SPR_NOACCESS, | |
2381 | &spr_read_generic, &spr_write_generic, | |
2382 | 0x00000000); | |
2383 | /* XXX : not implemented */ | |
2384 | spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", | |
2385 | SPR_NOACCESS, SPR_NOACCESS, | |
2386 | &spr_read_generic, &spr_write_generic, | |
2387 | 0x00000000); | |
2388 | /* XXX : not implemented */ | |
2389 | spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", | |
2390 | SPR_NOACCESS, SPR_NOACCESS, | |
2391 | &spr_read_generic, &spr_write_generic, | |
2392 | 0x00000000); | |
2393 | /* XXX : not implemented */ | |
2394 | spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", | |
2395 | SPR_NOACCESS, SPR_NOACCESS, | |
2396 | &spr_read_generic, &spr_write_generic, | |
2397 | 0x00000000); | |
2398 | /* XXX : not implemented */ | |
2399 | spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", | |
2400 | SPR_NOACCESS, SPR_NOACCESS, | |
2401 | &spr_read_generic, &spr_write_generic, | |
2402 | 0x00000000); | |
2403 | /* XXX : not implemented */ | |
2404 | spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", | |
2405 | SPR_NOACCESS, SPR_NOACCESS, | |
2406 | &spr_read_generic, &spr_write_generic, | |
2407 | 0x00000000); | |
2408 | /* XXX : not implemented */ | |
2409 | spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", | |
2410 | SPR_NOACCESS, SPR_NOACCESS, | |
2411 | &spr_read_generic, &spr_write_generic, | |
2412 | 0x00000000); | |
2413 | /* XXX : not implemented */ | |
2414 | spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", | |
2415 | SPR_NOACCESS, SPR_NOACCESS, | |
2416 | &spr_read_generic, &spr_write_generic, | |
2417 | 0x00000000); | |
2418 | /* XXX : not implemented */ | |
2419 | spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", | |
2420 | SPR_NOACCESS, SPR_NOACCESS, | |
2421 | &spr_read_generic, &spr_write_generic, | |
2422 | 0x00000000); | |
2423 | /* XXX : not implemented */ | |
2424 | spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", | |
2425 | SPR_NOACCESS, SPR_NOACCESS, | |
2426 | &spr_read_generic, &spr_write_generic, | |
2427 | 0x00000000); | |
2428 | /* XXX : not implemented */ | |
2429 | spr_register(env, SPR_RCPU_FPECR, "FPECR", | |
2430 | SPR_NOACCESS, SPR_NOACCESS, | |
2431 | &spr_read_generic, &spr_write_generic, | |
2432 | 0x00000000); | |
2433 | } | |
2434 | ||
2435 | static void gen_spr_8xx (CPUPPCState *env) | |
2436 | { | |
2437 | /* XXX : not implemented */ | |
2438 | spr_register(env, SPR_MPC_IC_CST, "IC_CST", | |
2439 | SPR_NOACCESS, SPR_NOACCESS, | |
2440 | &spr_read_generic, &spr_write_generic, | |
2441 | 0x00000000); | |
2442 | /* XXX : not implemented */ | |
2443 | spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", | |
2444 | SPR_NOACCESS, SPR_NOACCESS, | |
2445 | &spr_read_generic, &spr_write_generic, | |
2446 | 0x00000000); | |
2447 | /* XXX : not implemented */ | |
2448 | spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", | |
2449 | SPR_NOACCESS, SPR_NOACCESS, | |
2450 | &spr_read_generic, &spr_write_generic, | |
2451 | 0x00000000); | |
2452 | /* XXX : not implemented */ | |
2453 | spr_register(env, SPR_MPC_DC_CST, "DC_CST", | |
2454 | SPR_NOACCESS, SPR_NOACCESS, | |
2455 | &spr_read_generic, &spr_write_generic, | |
2456 | 0x00000000); | |
2457 | /* XXX : not implemented */ | |
2458 | spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", | |
2459 | SPR_NOACCESS, SPR_NOACCESS, | |
2460 | &spr_read_generic, &spr_write_generic, | |
2461 | 0x00000000); | |
2462 | /* XXX : not implemented */ | |
2463 | spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", | |
2464 | SPR_NOACCESS, SPR_NOACCESS, | |
2465 | &spr_read_generic, &spr_write_generic, | |
2466 | 0x00000000); | |
2467 | /* XXX : not implemented */ | |
2468 | spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", | |
2469 | SPR_NOACCESS, SPR_NOACCESS, | |
2470 | &spr_read_generic, &spr_write_generic, | |
2471 | 0x00000000); | |
2472 | /* XXX : not implemented */ | |
2473 | spr_register(env, SPR_MPC_MI_AP, "MI_AP", | |
2474 | SPR_NOACCESS, SPR_NOACCESS, | |
2475 | &spr_read_generic, &spr_write_generic, | |
2476 | 0x00000000); | |
2477 | /* XXX : not implemented */ | |
2478 | spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", | |
2479 | SPR_NOACCESS, SPR_NOACCESS, | |
2480 | &spr_read_generic, &spr_write_generic, | |
2481 | 0x00000000); | |
2482 | /* XXX : not implemented */ | |
2483 | spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", | |
2484 | SPR_NOACCESS, SPR_NOACCESS, | |
2485 | &spr_read_generic, &spr_write_generic, | |
2486 | 0x00000000); | |
2487 | /* XXX : not implemented */ | |
2488 | spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", | |
2489 | SPR_NOACCESS, SPR_NOACCESS, | |
2490 | &spr_read_generic, &spr_write_generic, | |
2491 | 0x00000000); | |
2492 | /* XXX : not implemented */ | |
2493 | spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", | |
2494 | SPR_NOACCESS, SPR_NOACCESS, | |
2495 | &spr_read_generic, &spr_write_generic, | |
2496 | 0x00000000); | |
2497 | /* XXX : not implemented */ | |
2498 | spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", | |
2499 | SPR_NOACCESS, SPR_NOACCESS, | |
2500 | &spr_read_generic, &spr_write_generic, | |
2501 | 0x00000000); | |
2502 | /* XXX : not implemented */ | |
2503 | spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", | |
2504 | SPR_NOACCESS, SPR_NOACCESS, | |
2505 | &spr_read_generic, &spr_write_generic, | |
2506 | 0x00000000); | |
2507 | /* XXX : not implemented */ | |
2508 | spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", | |
2509 | SPR_NOACCESS, SPR_NOACCESS, | |
2510 | &spr_read_generic, &spr_write_generic, | |
2511 | 0x00000000); | |
2512 | /* XXX : not implemented */ | |
2513 | spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", | |
2514 | SPR_NOACCESS, SPR_NOACCESS, | |
2515 | &spr_read_generic, &spr_write_generic, | |
2516 | 0x00000000); | |
2517 | /* XXX : not implemented */ | |
2518 | spr_register(env, SPR_MPC_MD_AP, "MD_AP", | |
2519 | SPR_NOACCESS, SPR_NOACCESS, | |
2520 | &spr_read_generic, &spr_write_generic, | |
2521 | 0x00000000); | |
2522 | /* XXX : not implemented */ | |
2523 | spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", | |
2524 | SPR_NOACCESS, SPR_NOACCESS, | |
2525 | &spr_read_generic, &spr_write_generic, | |
2526 | 0x00000000); | |
2527 | /* XXX : not implemented */ | |
2528 | spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", | |
2529 | SPR_NOACCESS, SPR_NOACCESS, | |
2530 | &spr_read_generic, &spr_write_generic, | |
2531 | 0x00000000); | |
2532 | /* XXX : not implemented */ | |
2533 | spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", | |
2534 | SPR_NOACCESS, SPR_NOACCESS, | |
2535 | &spr_read_generic, &spr_write_generic, | |
2536 | 0x00000000); | |
2537 | /* XXX : not implemented */ | |
2538 | spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", | |
2539 | SPR_NOACCESS, SPR_NOACCESS, | |
2540 | &spr_read_generic, &spr_write_generic, | |
2541 | 0x00000000); | |
2542 | /* XXX : not implemented */ | |
2543 | spr_register(env, SPR_MPC_MD_TW, "MD_TW", | |
2544 | SPR_NOACCESS, SPR_NOACCESS, | |
2545 | &spr_read_generic, &spr_write_generic, | |
2546 | 0x00000000); | |
2547 | /* XXX : not implemented */ | |
2548 | spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", | |
2549 | SPR_NOACCESS, SPR_NOACCESS, | |
2550 | &spr_read_generic, &spr_write_generic, | |
2551 | 0x00000000); | |
2552 | /* XXX : not implemented */ | |
2553 | spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", | |
2554 | SPR_NOACCESS, SPR_NOACCESS, | |
2555 | &spr_read_generic, &spr_write_generic, | |
2556 | 0x00000000); | |
2557 | /* XXX : not implemented */ | |
2558 | spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", | |
2559 | SPR_NOACCESS, SPR_NOACCESS, | |
2560 | &spr_read_generic, &spr_write_generic, | |
2561 | 0x00000000); | |
2562 | } | |
2563 | ||
2564 | // XXX: TODO | |
2565 | /* | |
2566 | * AMR => SPR 29 (Power 2.04) | |
2567 | * CTRL => SPR 136 (Power 2.04) | |
2568 | * CTRL => SPR 152 (Power 2.04) | |
2569 | * SCOMC => SPR 276 (64 bits ?) | |
2570 | * SCOMD => SPR 277 (64 bits ?) | |
2571 | * TBU40 => SPR 286 (Power 2.04 hypv) | |
2572 | * HSPRG0 => SPR 304 (Power 2.04 hypv) | |
2573 | * HSPRG1 => SPR 305 (Power 2.04 hypv) | |
2574 | * HDSISR => SPR 306 (Power 2.04 hypv) | |
2575 | * HDAR => SPR 307 (Power 2.04 hypv) | |
2576 | * PURR => SPR 309 (Power 2.04 hypv) | |
2577 | * HDEC => SPR 310 (Power 2.04 hypv) | |
2578 | * HIOR => SPR 311 (hypv) | |
2579 | * RMOR => SPR 312 (970) | |
2580 | * HRMOR => SPR 313 (Power 2.04 hypv) | |
2581 | * HSRR0 => SPR 314 (Power 2.04 hypv) | |
2582 | * HSRR1 => SPR 315 (Power 2.04 hypv) | |
2583 | * LPCR => SPR 316 (970) | |
2584 | * LPIDR => SPR 317 (970) | |
80d11f44 JM |
2585 | * EPR => SPR 702 (Power 2.04 emb) |
2586 | * perf => 768-783 (Power 2.04) | |
2587 | * perf => 784-799 (Power 2.04) | |
2588 | * PPR => SPR 896 (Power 2.04) | |
2589 | * EPLC => SPR 947 (Power 2.04 emb) | |
2590 | * EPSC => SPR 948 (Power 2.04 emb) | |
2591 | * DABRX => 1015 (Power 2.04 hypv) | |
2592 | * FPECR => SPR 1022 (?) | |
2593 | * ... and more (thermal management, performance counters, ...) | |
2594 | */ | |
2595 | ||
2596 | /*****************************************************************************/ | |
2597 | /* Exception vectors models */ | |
2598 | static void init_excp_4xx_real (CPUPPCState *env) | |
2599 | { | |
2600 | #if !defined(CONFIG_USER_ONLY) | |
2601 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; | |
2602 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2603 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2604 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2605 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2606 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2607 | env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; | |
2608 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; | |
2609 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; | |
2610 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; | |
fc1c67bc | 2611 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 | 2612 | env->ivor_mask = 0x0000FFF0UL; |
faadf50e | 2613 | env->ivpr_mask = 0xFFFF0000UL; |
1c27f8fb JM |
2614 | /* Hardware reset vector */ |
2615 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2616 | #endif |
2617 | } | |
2618 | ||
80d11f44 JM |
2619 | static void init_excp_4xx_softmmu (CPUPPCState *env) |
2620 | { | |
2621 | #if !defined(CONFIG_USER_ONLY) | |
2622 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; | |
2623 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2624 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2625 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2626 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2627 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2628 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2629 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2630 | env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; | |
2631 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; | |
2632 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; | |
2633 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; | |
2634 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; | |
2635 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; | |
fc1c67bc | 2636 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 JM |
2637 | env->ivor_mask = 0x0000FFF0UL; |
2638 | env->ivpr_mask = 0xFFFF0000UL; | |
2639 | /* Hardware reset vector */ | |
2640 | env->hreset_vector = 0xFFFFFFFCUL; | |
2641 | #endif | |
2642 | } | |
2643 | ||
2644 | static void init_excp_MPC5xx (CPUPPCState *env) | |
2645 | { | |
2646 | #if !defined(CONFIG_USER_ONLY) | |
2647 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2648 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2649 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2650 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2651 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2652 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; | |
2653 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2654 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2655 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2656 | env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; | |
2657 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; | |
2658 | env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; | |
2659 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; | |
2660 | env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; | |
2661 | env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; | |
fc1c67bc | 2662 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 JM |
2663 | env->ivor_mask = 0x0000FFF0UL; |
2664 | env->ivpr_mask = 0xFFFF0000UL; | |
2665 | /* Hardware reset vector */ | |
2666 | env->hreset_vector = 0xFFFFFFFCUL; | |
2667 | #endif | |
2668 | } | |
2669 | ||
2670 | static void init_excp_MPC8xx (CPUPPCState *env) | |
e1833e1f JM |
2671 | { |
2672 | #if !defined(CONFIG_USER_ONLY) | |
2673 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2674 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2675 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2676 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2677 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2678 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2679 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
80d11f44 | 2680 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
e1833e1f | 2681 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
e1833e1f | 2682 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
80d11f44 JM |
2683 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
2684 | env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; | |
2685 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; | |
2686 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; | |
2687 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; | |
2688 | env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; | |
2689 | env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; | |
2690 | env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; | |
2691 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; | |
2692 | env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; | |
2693 | env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; | |
fc1c67bc | 2694 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 JM |
2695 | env->ivor_mask = 0x0000FFF0UL; |
2696 | env->ivpr_mask = 0xFFFF0000UL; | |
1c27f8fb | 2697 | /* Hardware reset vector */ |
80d11f44 | 2698 | env->hreset_vector = 0xFFFFFFFCUL; |
e1833e1f JM |
2699 | #endif |
2700 | } | |
2701 | ||
80d11f44 | 2702 | static void init_excp_G2 (CPUPPCState *env) |
e1833e1f JM |
2703 | { |
2704 | #if !defined(CONFIG_USER_ONLY) | |
2705 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2706 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2707 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2708 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2709 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2710 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2711 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2712 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2713 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
80d11f44 | 2714 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; |
e1833e1f JM |
2715 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
2716 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
e1833e1f JM |
2717 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
2718 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2719 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2720 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2721 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
fc1c67bc | 2722 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 JM |
2723 | /* Hardware reset vector */ |
2724 | env->hreset_vector = 0xFFFFFFFCUL; | |
2725 | #endif | |
2726 | } | |
2727 | ||
2728 | static void init_excp_e200 (CPUPPCState *env) | |
2729 | { | |
2730 | #if !defined(CONFIG_USER_ONLY) | |
2731 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; | |
2732 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; | |
2733 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; | |
2734 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; | |
2735 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; | |
2736 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; | |
2737 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; | |
2738 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; | |
2739 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; | |
2740 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; | |
2741 | env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; | |
2742 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; | |
2743 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; | |
2744 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; | |
2745 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; | |
2746 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; | |
2747 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; | |
2748 | env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; | |
2749 | env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; | |
2750 | env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; | |
fc1c67bc | 2751 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 JM |
2752 | env->ivor_mask = 0x0000FFF7UL; |
2753 | env->ivpr_mask = 0xFFFF0000UL; | |
2754 | /* Hardware reset vector */ | |
2755 | env->hreset_vector = 0xFFFFFFFCUL; | |
2756 | #endif | |
2757 | } | |
2758 | ||
2759 | static void init_excp_BookE (CPUPPCState *env) | |
2760 | { | |
2761 | #if !defined(CONFIG_USER_ONLY) | |
2762 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; | |
2763 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; | |
2764 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; | |
2765 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; | |
2766 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; | |
2767 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; | |
2768 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; | |
2769 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; | |
2770 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; | |
2771 | env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; | |
2772 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; | |
2773 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; | |
2774 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; | |
2775 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; | |
2776 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; | |
2777 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; | |
fc1c67bc | 2778 | env->hreset_excp_prefix = 0x00000000UL; |
80d11f44 JM |
2779 | env->ivor_mask = 0x0000FFE0UL; |
2780 | env->ivpr_mask = 0xFFFF0000UL; | |
2781 | /* Hardware reset vector */ | |
2782 | env->hreset_vector = 0xFFFFFFFCUL; | |
2783 | #endif | |
2784 | } | |
2785 | ||
2786 | static void init_excp_601 (CPUPPCState *env) | |
2787 | { | |
2788 | #if !defined(CONFIG_USER_ONLY) | |
2789 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2790 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2791 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2792 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2793 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2794 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2795 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2796 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2797 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2798 | env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; | |
2799 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2800 | env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; | |
fc1c67bc | 2801 | env->hreset_excp_prefix = 0xFFF00000UL; |
1c27f8fb | 2802 | /* Hardware reset vector */ |
80d11f44 | 2803 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2804 | #endif |
2805 | } | |
2806 | ||
80d11f44 | 2807 | static void init_excp_602 (CPUPPCState *env) |
e1833e1f JM |
2808 | { |
2809 | #if !defined(CONFIG_USER_ONLY) | |
082c6681 | 2810 | /* XXX: exception prefix has a special behavior on 602 */ |
e1833e1f JM |
2811 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
2812 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2813 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2814 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2815 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2816 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2817 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2818 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2819 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2820 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2821 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2822 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
2823 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2824 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2825 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2826 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
80d11f44 JM |
2827 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; |
2828 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; | |
fc1c67bc | 2829 | env->hreset_excp_prefix = 0xFFF00000UL; |
1c27f8fb JM |
2830 | /* Hardware reset vector */ |
2831 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2832 | #endif |
2833 | } | |
2834 | ||
80d11f44 | 2835 | static void init_excp_603 (CPUPPCState *env) |
e1833e1f JM |
2836 | { |
2837 | #if !defined(CONFIG_USER_ONLY) | |
2838 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2839 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2840 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2841 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2842 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2843 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2844 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2845 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2846 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
e1833e1f JM |
2847 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
2848 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2849 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
2850 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2851 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2852 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2853 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
fc1c67bc | 2854 | env->hreset_excp_prefix = 0x00000000UL; |
1c27f8fb JM |
2855 | /* Hardware reset vector */ |
2856 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2857 | #endif |
2858 | } | |
2859 | ||
2860 | static void init_excp_604 (CPUPPCState *env) | |
2861 | { | |
2862 | #if !defined(CONFIG_USER_ONLY) | |
2863 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2864 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2865 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2866 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2867 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2868 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2869 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2870 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2871 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2872 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2873 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2874 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2875 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2876 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
2d3eb7bf | 2877 | env->hreset_excp_prefix = 0xFFF00000UL; |
1c27f8fb | 2878 | /* Hardware reset vector */ |
2d3eb7bf | 2879 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2880 | #endif |
2881 | } | |
2882 | ||
578bb252 | 2883 | #if defined(TARGET_PPC64) |
e1833e1f JM |
2884 | static void init_excp_620 (CPUPPCState *env) |
2885 | { | |
2886 | #if !defined(CONFIG_USER_ONLY) | |
2887 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2888 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2889 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2890 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2891 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2892 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2893 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2894 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2895 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2896 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2897 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
e1833e1f JM |
2898 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
2899 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2900 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
fc1c67bc | 2901 | env->hreset_excp_prefix = 0xFFF00000UL; |
1c27f8fb | 2902 | /* Hardware reset vector */ |
faadf50e | 2903 | env->hreset_vector = 0x0000000000000100ULL; |
e1833e1f JM |
2904 | #endif |
2905 | } | |
578bb252 | 2906 | #endif /* defined(TARGET_PPC64) */ |
e1833e1f JM |
2907 | |
2908 | static void init_excp_7x0 (CPUPPCState *env) | |
2909 | { | |
2910 | #if !defined(CONFIG_USER_ONLY) | |
2911 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2912 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2913 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2914 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2915 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2916 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2917 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2918 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2919 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2920 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2921 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2922 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2923 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
bd928eba | 2924 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
e1833e1f | 2925 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
fc1c67bc | 2926 | env->hreset_excp_prefix = 0x00000000UL; |
1c27f8fb JM |
2927 | /* Hardware reset vector */ |
2928 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2929 | #endif |
2930 | } | |
2931 | ||
bd928eba | 2932 | static void init_excp_750cl (CPUPPCState *env) |
e1833e1f JM |
2933 | { |
2934 | #if !defined(CONFIG_USER_ONLY) | |
2935 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2936 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2937 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2938 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2939 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2940 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2941 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2942 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2943 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2944 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2945 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2946 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2947 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2948 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
fc1c67bc | 2949 | env->hreset_excp_prefix = 0x00000000UL; |
bd928eba JM |
2950 | /* Hardware reset vector */ |
2951 | env->hreset_vector = 0xFFFFFFFCUL; | |
2952 | #endif | |
2953 | } | |
2954 | ||
2955 | static void init_excp_750cx (CPUPPCState *env) | |
2956 | { | |
2957 | #if !defined(CONFIG_USER_ONLY) | |
2958 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2959 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2960 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2961 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2962 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2963 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2964 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2965 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2966 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2967 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2968 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2969 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2970 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
e1833e1f | 2971 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
fc1c67bc | 2972 | env->hreset_excp_prefix = 0x00000000UL; |
1c27f8fb JM |
2973 | /* Hardware reset vector */ |
2974 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2975 | #endif |
2976 | } | |
2977 | ||
7a3a6927 JM |
2978 | /* XXX: Check if this is correct */ |
2979 | static void init_excp_7x5 (CPUPPCState *env) | |
2980 | { | |
2981 | #if !defined(CONFIG_USER_ONLY) | |
2982 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2983 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2984 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2985 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2986 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2987 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2988 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2989 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2990 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2991 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2992 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
bd928eba | 2993 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
7a3a6927 JM |
2994 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
2995 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2996 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
7a3a6927 JM |
2997 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
2998 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
bd928eba | 2999 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
fc1c67bc | 3000 | env->hreset_excp_prefix = 0x00000000UL; |
7a3a6927 JM |
3001 | /* Hardware reset vector */ |
3002 | env->hreset_vector = 0xFFFFFFFCUL; | |
3003 | #endif | |
3004 | } | |
3005 | ||
e1833e1f JM |
3006 | static void init_excp_7400 (CPUPPCState *env) |
3007 | { | |
3008 | #if !defined(CONFIG_USER_ONLY) | |
3009 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3010 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3011 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3012 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3013 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3014 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3015 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3016 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3017 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3018 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3019 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3020 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3021 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3022 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3023 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
3024 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; | |
3025 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; | |
fc1c67bc | 3026 | env->hreset_excp_prefix = 0x00000000UL; |
1c27f8fb JM |
3027 | /* Hardware reset vector */ |
3028 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
3029 | #endif |
3030 | } | |
3031 | ||
e1833e1f JM |
3032 | static void init_excp_7450 (CPUPPCState *env) |
3033 | { | |
3034 | #if !defined(CONFIG_USER_ONLY) | |
3035 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3036 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3037 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3038 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3039 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3040 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3041 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3042 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3043 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3044 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3045 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3046 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3047 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3048 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
3049 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
3050 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
3051 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3052 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
3053 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; | |
fc1c67bc | 3054 | env->hreset_excp_prefix = 0x00000000UL; |
1c27f8fb JM |
3055 | /* Hardware reset vector */ |
3056 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
3057 | #endif |
3058 | } | |
e1833e1f JM |
3059 | |
3060 | #if defined (TARGET_PPC64) | |
3061 | static void init_excp_970 (CPUPPCState *env) | |
3062 | { | |
3063 | #if !defined(CONFIG_USER_ONLY) | |
3064 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3065 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3066 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3067 | env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; | |
3068 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3069 | env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; | |
3070 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3071 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3072 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3073 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3074 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
e1833e1f | 3075 | env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; |
e1833e1f JM |
3076 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
3077 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3078 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3079 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3080 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3081 | env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; | |
3082 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; | |
3083 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; | |
fc1c67bc | 3084 | env->hreset_excp_prefix = 0x00000000FFF00000ULL; |
1c27f8fb JM |
3085 | /* Hardware reset vector */ |
3086 | env->hreset_vector = 0x0000000000000100ULL; | |
e1833e1f JM |
3087 | #endif |
3088 | } | |
3089 | #endif | |
3090 | ||
2f462816 JM |
3091 | /*****************************************************************************/ |
3092 | /* Power management enable checks */ | |
3093 | static int check_pow_none (CPUPPCState *env) | |
3094 | { | |
3095 | return 0; | |
3096 | } | |
3097 | ||
3098 | static int check_pow_nocheck (CPUPPCState *env) | |
3099 | { | |
3100 | return 1; | |
3101 | } | |
3102 | ||
3103 | static int check_pow_hid0 (CPUPPCState *env) | |
3104 | { | |
3105 | if (env->spr[SPR_HID0] & 0x00E00000) | |
3106 | return 1; | |
3107 | ||
3108 | return 0; | |
3109 | } | |
3110 | ||
4e777442 JM |
3111 | static int check_pow_hid0_74xx (CPUPPCState *env) |
3112 | { | |
3113 | if (env->spr[SPR_HID0] & 0x00600000) | |
3114 | return 1; | |
3115 | ||
3116 | return 0; | |
3117 | } | |
3118 | ||
a750fc0b JM |
3119 | /*****************************************************************************/ |
3120 | /* PowerPC implementations definitions */ | |
76a66253 | 3121 | |
a750fc0b | 3122 | /* PowerPC 401 */ |
082c6681 JM |
3123 | #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \ |
3124 | PPC_WRTEE | PPC_DCR | \ | |
3125 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3126 | PPC_CACHE_DCBZ | \ | |
a750fc0b | 3127 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
082c6681 | 3128 | PPC_4xx_COMMON | PPC_40x_EXCP) |
a750fc0b | 3129 | #define POWERPC_MSRM_401 (0x00000000000FD201ULL) |
b4095fed | 3130 | #define POWERPC_MMU_401 (POWERPC_MMU_REAL) |
a750fc0b JM |
3131 | #define POWERPC_EXCP_401 (POWERPC_EXCP_40x) |
3132 | #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401) | |
237c0af0 | 3133 | #define POWERPC_BFDM_401 (bfd_mach_ppc_403) |
4018bae9 JM |
3134 | #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \ |
3135 | POWERPC_FLAG_BUS_CLK) | |
2f462816 | 3136 | #define check_pow_401 check_pow_nocheck |
76a66253 | 3137 | |
a750fc0b JM |
3138 | static void init_proc_401 (CPUPPCState *env) |
3139 | { | |
3140 | gen_spr_40x(env); | |
3141 | gen_spr_401_403(env); | |
3142 | gen_spr_401(env); | |
e1833e1f | 3143 | init_excp_4xx_real(env); |
d63001d1 JM |
3144 | env->dcache_line_size = 32; |
3145 | env->icache_line_size = 32; | |
4e290a0b JM |
3146 | /* Allocate hardware IRQ controller */ |
3147 | ppc40x_irq_init(env); | |
a750fc0b | 3148 | } |
76a66253 | 3149 | |
a750fc0b | 3150 | /* PowerPC 401x2 */ |
082c6681 JM |
3151 | #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
3152 | PPC_DCR | PPC_WRTEE | \ | |
3153 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3154 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
a750fc0b JM |
3155 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3156 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ | |
082c6681 | 3157 | PPC_4xx_COMMON | PPC_40x_EXCP) |
a750fc0b JM |
3158 | #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL) |
3159 | #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z) | |
3160 | #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x) | |
3161 | #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401) | |
237c0af0 | 3162 | #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403) |
4018bae9 JM |
3163 | #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \ |
3164 | POWERPC_FLAG_BUS_CLK) | |
2f462816 | 3165 | #define check_pow_401x2 check_pow_nocheck |
a750fc0b JM |
3166 | |
3167 | static void init_proc_401x2 (CPUPPCState *env) | |
3168 | { | |
3169 | gen_spr_40x(env); | |
3170 | gen_spr_401_403(env); | |
3171 | gen_spr_401x2(env); | |
3172 | gen_spr_compress(env); | |
a750fc0b | 3173 | /* Memory management */ |
f2e63a42 | 3174 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3175 | env->nb_tlb = 64; |
3176 | env->nb_ways = 1; | |
3177 | env->id_tlbs = 0; | |
f2e63a42 | 3178 | #endif |
e1833e1f | 3179 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3180 | env->dcache_line_size = 32; |
3181 | env->icache_line_size = 32; | |
4e290a0b JM |
3182 | /* Allocate hardware IRQ controller */ |
3183 | ppc40x_irq_init(env); | |
76a66253 JM |
3184 | } |
3185 | ||
a750fc0b | 3186 | /* PowerPC 401x3 */ |
082c6681 JM |
3187 | #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
3188 | PPC_DCR | PPC_WRTEE | \ | |
3189 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3190 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
a750fc0b JM |
3191 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3192 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ | |
082c6681 | 3193 | PPC_4xx_COMMON | PPC_40x_EXCP) |
a750fc0b JM |
3194 | #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL) |
3195 | #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z) | |
3196 | #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x) | |
3197 | #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401) | |
237c0af0 | 3198 | #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403) |
4018bae9 JM |
3199 | #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \ |
3200 | POWERPC_FLAG_BUS_CLK) | |
2f462816 | 3201 | #define check_pow_401x3 check_pow_nocheck |
a750fc0b | 3202 | |
578bb252 | 3203 | __attribute__ (( unused )) |
e1833e1f | 3204 | static void init_proc_401x3 (CPUPPCState *env) |
76a66253 | 3205 | { |
4e290a0b JM |
3206 | gen_spr_40x(env); |
3207 | gen_spr_401_403(env); | |
3208 | gen_spr_401(env); | |
3209 | gen_spr_401x2(env); | |
3210 | gen_spr_compress(env); | |
e1833e1f | 3211 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3212 | env->dcache_line_size = 32; |
3213 | env->icache_line_size = 32; | |
4e290a0b JM |
3214 | /* Allocate hardware IRQ controller */ |
3215 | ppc40x_irq_init(env); | |
3fc6c082 | 3216 | } |
a750fc0b JM |
3217 | |
3218 | /* IOP480 */ | |
082c6681 JM |
3219 | #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \ |
3220 | PPC_DCR | PPC_WRTEE | \ | |
3221 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3222 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
a750fc0b JM |
3223 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3224 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ | |
082c6681 | 3225 | PPC_4xx_COMMON | PPC_40x_EXCP) |
a750fc0b JM |
3226 | #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL) |
3227 | #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z) | |
3228 | #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x) | |
3229 | #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401) | |
237c0af0 | 3230 | #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403) |
4018bae9 JM |
3231 | #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \ |
3232 | POWERPC_FLAG_BUS_CLK) | |
2f462816 | 3233 | #define check_pow_IOP480 check_pow_nocheck |
a750fc0b JM |
3234 | |
3235 | static void init_proc_IOP480 (CPUPPCState *env) | |
3fc6c082 | 3236 | { |
a750fc0b JM |
3237 | gen_spr_40x(env); |
3238 | gen_spr_401_403(env); | |
3239 | gen_spr_401x2(env); | |
3240 | gen_spr_compress(env); | |
a750fc0b | 3241 | /* Memory management */ |
f2e63a42 | 3242 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3243 | env->nb_tlb = 64; |
3244 | env->nb_ways = 1; | |
3245 | env->id_tlbs = 0; | |
f2e63a42 | 3246 | #endif |
e1833e1f | 3247 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3248 | env->dcache_line_size = 32; |
3249 | env->icache_line_size = 32; | |
4e290a0b JM |
3250 | /* Allocate hardware IRQ controller */ |
3251 | ppc40x_irq_init(env); | |
3fc6c082 FB |
3252 | } |
3253 | ||
a750fc0b | 3254 | /* PowerPC 403 */ |
082c6681 JM |
3255 | #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \ |
3256 | PPC_DCR | PPC_WRTEE | \ | |
3257 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3258 | PPC_CACHE_DCBZ | \ | |
a750fc0b | 3259 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
082c6681 | 3260 | PPC_4xx_COMMON | PPC_40x_EXCP) |
a750fc0b | 3261 | #define POWERPC_MSRM_403 (0x000000000007D00DULL) |
b4095fed | 3262 | #define POWERPC_MMU_403 (POWERPC_MMU_REAL) |
a750fc0b JM |
3263 | #define POWERPC_EXCP_403 (POWERPC_EXCP_40x) |
3264 | #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401) | |
237c0af0 | 3265 | #define POWERPC_BFDM_403 (bfd_mach_ppc_403) |
4018bae9 JM |
3266 | #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \ |
3267 | POWERPC_FLAG_BUS_CLK) | |
2f462816 | 3268 | #define check_pow_403 check_pow_nocheck |
a750fc0b JM |
3269 | |
3270 | static void init_proc_403 (CPUPPCState *env) | |
3fc6c082 | 3271 | { |
a750fc0b JM |
3272 | gen_spr_40x(env); |
3273 | gen_spr_401_403(env); | |
3274 | gen_spr_403(env); | |
3275 | gen_spr_403_real(env); | |
e1833e1f | 3276 | init_excp_4xx_real(env); |
d63001d1 JM |
3277 | env->dcache_line_size = 32; |
3278 | env->icache_line_size = 32; | |
4e290a0b JM |
3279 | /* Allocate hardware IRQ controller */ |
3280 | ppc40x_irq_init(env); | |
3fc6c082 FB |
3281 | } |
3282 | ||
a750fc0b | 3283 | /* PowerPC 403 GCX */ |
082c6681 JM |
3284 | #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \ |
3285 | PPC_DCR | PPC_WRTEE | \ | |
3286 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3287 | PPC_CACHE_DCBZ | \ | |
a750fc0b JM |
3288 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
3289 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ | |
082c6681 | 3290 | PPC_4xx_COMMON | PPC_40x_EXCP) |
a750fc0b JM |
3291 | #define POWERPC_MSRM_403GCX (0x000000000007D00DULL) |
3292 | #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z) | |
3293 | #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x) | |
3294 | #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401) | |
237c0af0 | 3295 | #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403) |
4018bae9 JM |
3296 | #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \ |
3297 | POWERPC_FLAG_BUS_CLK) | |
2f462816 | 3298 | #define check_pow_403GCX check_pow_nocheck |
a750fc0b JM |
3299 | |
3300 | static void init_proc_403GCX (CPUPPCState *env) | |
3fc6c082 | 3301 | { |
a750fc0b JM |
3302 | gen_spr_40x(env); |
3303 | gen_spr_401_403(env); | |
3304 | gen_spr_403(env); | |
3305 | gen_spr_403_real(env); | |
3306 | gen_spr_403_mmu(env); | |
3307 | /* Bus access control */ | |
035feb88 | 3308 | /* not emulated, as Qemu never does speculative access */ |
a750fc0b JM |
3309 | spr_register(env, SPR_40x_SGR, "SGR", |
3310 | SPR_NOACCESS, SPR_NOACCESS, | |
3311 | &spr_read_generic, &spr_write_generic, | |
3312 | 0xFFFFFFFF); | |
035feb88 | 3313 | /* not emulated, as Qemu do not emulate caches */ |
a750fc0b JM |
3314 | spr_register(env, SPR_40x_DCWR, "DCWR", |
3315 | SPR_NOACCESS, SPR_NOACCESS, | |
3316 | &spr_read_generic, &spr_write_generic, | |
3317 | 0x00000000); | |
3318 | /* Memory management */ | |
f2e63a42 | 3319 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3320 | env->nb_tlb = 64; |
3321 | env->nb_ways = 1; | |
3322 | env->id_tlbs = 0; | |
f2e63a42 | 3323 | #endif |
80d11f44 JM |
3324 | init_excp_4xx_softmmu(env); |
3325 | env->dcache_line_size = 32; | |
3326 | env->icache_line_size = 32; | |
3327 | /* Allocate hardware IRQ controller */ | |
3328 | ppc40x_irq_init(env); | |
3329 | } | |
3330 | ||
3331 | /* PowerPC 405 */ | |
082c6681 JM |
3332 | #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
3333 | PPC_DCR | PPC_WRTEE | \ | |
3334 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \ | |
3335 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
3336 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
80d11f44 | 3337 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ |
082c6681 | 3338 | PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP) |
80d11f44 JM |
3339 | #define POWERPC_MSRM_405 (0x000000000006E630ULL) |
3340 | #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx) | |
3341 | #define POWERPC_EXCP_405 (POWERPC_EXCP_40x) | |
3342 | #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405) | |
3343 | #define POWERPC_BFDM_405 (bfd_mach_ppc_403) | |
3344 | #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3345 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 JM |
3346 | #define check_pow_405 check_pow_nocheck |
3347 | ||
3348 | static void init_proc_405 (CPUPPCState *env) | |
3349 | { | |
3350 | /* Time base */ | |
3351 | gen_tbl(env); | |
3352 | gen_spr_40x(env); | |
3353 | gen_spr_405(env); | |
3354 | /* Bus access control */ | |
3355 | /* not emulated, as Qemu never does speculative access */ | |
3356 | spr_register(env, SPR_40x_SGR, "SGR", | |
3357 | SPR_NOACCESS, SPR_NOACCESS, | |
3358 | &spr_read_generic, &spr_write_generic, | |
3359 | 0xFFFFFFFF); | |
3360 | /* not emulated, as Qemu do not emulate caches */ | |
3361 | spr_register(env, SPR_40x_DCWR, "DCWR", | |
3362 | SPR_NOACCESS, SPR_NOACCESS, | |
3363 | &spr_read_generic, &spr_write_generic, | |
3364 | 0x00000000); | |
3365 | /* Memory management */ | |
3366 | #if !defined(CONFIG_USER_ONLY) | |
3367 | env->nb_tlb = 64; | |
3368 | env->nb_ways = 1; | |
3369 | env->id_tlbs = 0; | |
3370 | #endif | |
3371 | init_excp_4xx_softmmu(env); | |
3372 | env->dcache_line_size = 32; | |
3373 | env->icache_line_size = 32; | |
3374 | /* Allocate hardware IRQ controller */ | |
3375 | ppc40x_irq_init(env); | |
3376 | } | |
3377 | ||
3378 | /* PowerPC 440 EP */ | |
082c6681 JM |
3379 | #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \ |
3380 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | \ | |
3381 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
3382 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
f4078236 | 3383 | PPC_MEM_TLBSYNC | PPC_MFTB | \ |
80d11f44 | 3384 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
082c6681 | 3385 | PPC_440_SPEC) |
80d11f44 JM |
3386 | #define POWERPC_MSRM_440EP (0x000000000006D630ULL) |
3387 | #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE) | |
3388 | #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE) | |
3389 | #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE) | |
3390 | #define POWERPC_BFDM_440EP (bfd_mach_ppc_403) | |
3391 | #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3392 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 JM |
3393 | #define check_pow_440EP check_pow_nocheck |
3394 | ||
3395 | __attribute__ (( unused )) | |
3396 | static void init_proc_440EP (CPUPPCState *env) | |
3397 | { | |
3398 | /* Time base */ | |
3399 | gen_tbl(env); | |
3400 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3401 | gen_spr_440(env); | |
3402 | gen_spr_usprgh(env); | |
3403 | /* Processor identification */ | |
3404 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3405 | SPR_NOACCESS, SPR_NOACCESS, | |
3406 | &spr_read_generic, &spr_write_pir, | |
3407 | 0x00000000); | |
3408 | /* XXX : not implemented */ | |
3409 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3410 | SPR_NOACCESS, SPR_NOACCESS, | |
3411 | &spr_read_generic, &spr_write_generic, | |
3412 | 0x00000000); | |
3413 | /* XXX : not implemented */ | |
3414 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3415 | SPR_NOACCESS, SPR_NOACCESS, | |
3416 | &spr_read_generic, &spr_write_generic, | |
3417 | 0x00000000); | |
3418 | /* XXX : not implemented */ | |
3419 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3420 | SPR_NOACCESS, SPR_NOACCESS, | |
3421 | &spr_read_generic, &spr_write_generic, | |
3422 | 0x00000000); | |
3423 | /* XXX : not implemented */ | |
3424 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3425 | SPR_NOACCESS, SPR_NOACCESS, | |
3426 | &spr_read_generic, &spr_write_generic, | |
3427 | 0x00000000); | |
3428 | /* XXX : not implemented */ | |
3429 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3430 | SPR_NOACCESS, SPR_NOACCESS, | |
3431 | &spr_read_generic, &spr_write_generic, | |
3432 | 0x00000000); | |
3433 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3434 | SPR_NOACCESS, SPR_NOACCESS, | |
3435 | &spr_read_generic, &spr_write_generic, | |
3436 | 0x00000000); | |
3437 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3438 | SPR_NOACCESS, SPR_NOACCESS, | |
3439 | &spr_read_generic, &spr_write_generic, | |
3440 | 0x00000000); | |
3441 | /* XXX : not implemented */ | |
3442 | spr_register(env, SPR_440_CCR1, "CCR1", | |
3443 | SPR_NOACCESS, SPR_NOACCESS, | |
3444 | &spr_read_generic, &spr_write_generic, | |
3445 | 0x00000000); | |
3446 | /* Memory management */ | |
3447 | #if !defined(CONFIG_USER_ONLY) | |
3448 | env->nb_tlb = 64; | |
3449 | env->nb_ways = 1; | |
3450 | env->id_tlbs = 0; | |
3451 | #endif | |
3452 | init_excp_BookE(env); | |
3453 | env->dcache_line_size = 32; | |
3454 | env->icache_line_size = 32; | |
3455 | /* XXX: TODO: allocate internal IRQ controller */ | |
3456 | } | |
3457 | ||
3458 | /* PowerPC 440 GP */ | |
082c6681 JM |
3459 | #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \ |
3460 | PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \ | |
3461 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
3462 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
f4078236 | 3463 | PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \ |
082c6681 JM |
3464 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3465 | PPC_440_SPEC) | |
80d11f44 JM |
3466 | #define POWERPC_MSRM_440GP (0x000000000006FF30ULL) |
3467 | #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE) | |
3468 | #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE) | |
3469 | #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE) | |
3470 | #define POWERPC_BFDM_440GP (bfd_mach_ppc_403) | |
3471 | #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3472 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 JM |
3473 | #define check_pow_440GP check_pow_nocheck |
3474 | ||
3475 | __attribute__ (( unused )) | |
3476 | static void init_proc_440GP (CPUPPCState *env) | |
3477 | { | |
3478 | /* Time base */ | |
3479 | gen_tbl(env); | |
3480 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3481 | gen_spr_440(env); | |
3482 | gen_spr_usprgh(env); | |
3483 | /* Processor identification */ | |
3484 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3485 | SPR_NOACCESS, SPR_NOACCESS, | |
3486 | &spr_read_generic, &spr_write_pir, | |
3487 | 0x00000000); | |
3488 | /* XXX : not implemented */ | |
3489 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3490 | SPR_NOACCESS, SPR_NOACCESS, | |
3491 | &spr_read_generic, &spr_write_generic, | |
3492 | 0x00000000); | |
3493 | /* XXX : not implemented */ | |
3494 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3495 | SPR_NOACCESS, SPR_NOACCESS, | |
3496 | &spr_read_generic, &spr_write_generic, | |
3497 | 0x00000000); | |
3498 | /* XXX : not implemented */ | |
3499 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3500 | SPR_NOACCESS, SPR_NOACCESS, | |
3501 | &spr_read_generic, &spr_write_generic, | |
3502 | 0x00000000); | |
3503 | /* XXX : not implemented */ | |
3504 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3505 | SPR_NOACCESS, SPR_NOACCESS, | |
3506 | &spr_read_generic, &spr_write_generic, | |
3507 | 0x00000000); | |
3508 | /* Memory management */ | |
3509 | #if !defined(CONFIG_USER_ONLY) | |
3510 | env->nb_tlb = 64; | |
3511 | env->nb_ways = 1; | |
3512 | env->id_tlbs = 0; | |
3513 | #endif | |
3514 | init_excp_BookE(env); | |
3515 | env->dcache_line_size = 32; | |
3516 | env->icache_line_size = 32; | |
3517 | /* XXX: TODO: allocate internal IRQ controller */ | |
3518 | } | |
3519 | ||
3520 | /* PowerPC 440x4 */ | |
082c6681 JM |
3521 | #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \ |
3522 | PPC_DCR | PPC_WRTEE | \ | |
3523 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
3524 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
f4078236 | 3525 | PPC_MEM_TLBSYNC | PPC_MFTB | \ |
80d11f44 JM |
3526 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
3527 | PPC_440_SPEC) | |
3528 | #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL) | |
3529 | #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE) | |
3530 | #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE) | |
3531 | #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE) | |
3532 | #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403) | |
3533 | #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3534 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 JM |
3535 | #define check_pow_440x4 check_pow_nocheck |
3536 | ||
3537 | __attribute__ (( unused )) | |
3538 | static void init_proc_440x4 (CPUPPCState *env) | |
3539 | { | |
3540 | /* Time base */ | |
3541 | gen_tbl(env); | |
3542 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3543 | gen_spr_440(env); | |
3544 | gen_spr_usprgh(env); | |
3545 | /* Processor identification */ | |
3546 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3547 | SPR_NOACCESS, SPR_NOACCESS, | |
3548 | &spr_read_generic, &spr_write_pir, | |
3549 | 0x00000000); | |
3550 | /* XXX : not implemented */ | |
3551 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3552 | SPR_NOACCESS, SPR_NOACCESS, | |
3553 | &spr_read_generic, &spr_write_generic, | |
3554 | 0x00000000); | |
3555 | /* XXX : not implemented */ | |
3556 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3557 | SPR_NOACCESS, SPR_NOACCESS, | |
3558 | &spr_read_generic, &spr_write_generic, | |
3559 | 0x00000000); | |
3560 | /* XXX : not implemented */ | |
3561 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3562 | SPR_NOACCESS, SPR_NOACCESS, | |
3563 | &spr_read_generic, &spr_write_generic, | |
3564 | 0x00000000); | |
3565 | /* XXX : not implemented */ | |
3566 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3567 | SPR_NOACCESS, SPR_NOACCESS, | |
3568 | &spr_read_generic, &spr_write_generic, | |
3569 | 0x00000000); | |
3570 | /* Memory management */ | |
3571 | #if !defined(CONFIG_USER_ONLY) | |
3572 | env->nb_tlb = 64; | |
3573 | env->nb_ways = 1; | |
3574 | env->id_tlbs = 0; | |
3575 | #endif | |
3576 | init_excp_BookE(env); | |
d63001d1 JM |
3577 | env->dcache_line_size = 32; |
3578 | env->icache_line_size = 32; | |
80d11f44 | 3579 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 FB |
3580 | } |
3581 | ||
80d11f44 | 3582 | /* PowerPC 440x5 */ |
082c6681 JM |
3583 | #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \ |
3584 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | \ | |
3585 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
3586 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
f4078236 | 3587 | PPC_MEM_TLBSYNC | PPC_MFTB | \ |
80d11f44 | 3588 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ |
082c6681 | 3589 | PPC_440_SPEC) |
80d11f44 JM |
3590 | #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL) |
3591 | #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE) | |
3592 | #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE) | |
3593 | #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE) | |
3594 | #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403) | |
3595 | #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3596 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 | 3597 | #define check_pow_440x5 check_pow_nocheck |
a750fc0b | 3598 | |
80d11f44 JM |
3599 | __attribute__ (( unused )) |
3600 | static void init_proc_440x5 (CPUPPCState *env) | |
3fc6c082 | 3601 | { |
a750fc0b JM |
3602 | /* Time base */ |
3603 | gen_tbl(env); | |
80d11f44 JM |
3604 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
3605 | gen_spr_440(env); | |
3606 | gen_spr_usprgh(env); | |
3607 | /* Processor identification */ | |
3608 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3609 | SPR_NOACCESS, SPR_NOACCESS, | |
3610 | &spr_read_generic, &spr_write_pir, | |
3611 | 0x00000000); | |
3612 | /* XXX : not implemented */ | |
3613 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
a750fc0b JM |
3614 | SPR_NOACCESS, SPR_NOACCESS, |
3615 | &spr_read_generic, &spr_write_generic, | |
80d11f44 JM |
3616 | 0x00000000); |
3617 | /* XXX : not implemented */ | |
3618 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3619 | SPR_NOACCESS, SPR_NOACCESS, | |
3620 | &spr_read_generic, &spr_write_generic, | |
3621 | 0x00000000); | |
3622 | /* XXX : not implemented */ | |
3623 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3624 | SPR_NOACCESS, SPR_NOACCESS, | |
3625 | &spr_read_generic, &spr_write_generic, | |
3626 | 0x00000000); | |
3627 | /* XXX : not implemented */ | |
3628 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3629 | SPR_NOACCESS, SPR_NOACCESS, | |
3630 | &spr_read_generic, &spr_write_generic, | |
3631 | 0x00000000); | |
3632 | /* XXX : not implemented */ | |
3633 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3634 | SPR_NOACCESS, SPR_NOACCESS, | |
3635 | &spr_read_generic, &spr_write_generic, | |
3636 | 0x00000000); | |
3637 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3638 | SPR_NOACCESS, SPR_NOACCESS, | |
3639 | &spr_read_generic, &spr_write_generic, | |
3640 | 0x00000000); | |
3641 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3642 | SPR_NOACCESS, SPR_NOACCESS, | |
3643 | &spr_read_generic, &spr_write_generic, | |
3644 | 0x00000000); | |
3645 | /* XXX : not implemented */ | |
3646 | spr_register(env, SPR_440_CCR1, "CCR1", | |
a750fc0b JM |
3647 | SPR_NOACCESS, SPR_NOACCESS, |
3648 | &spr_read_generic, &spr_write_generic, | |
3649 | 0x00000000); | |
3650 | /* Memory management */ | |
f2e63a42 | 3651 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3652 | env->nb_tlb = 64; |
3653 | env->nb_ways = 1; | |
3654 | env->id_tlbs = 0; | |
f2e63a42 | 3655 | #endif |
80d11f44 | 3656 | init_excp_BookE(env); |
d63001d1 JM |
3657 | env->dcache_line_size = 32; |
3658 | env->icache_line_size = 32; | |
80d11f44 | 3659 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 FB |
3660 | } |
3661 | ||
80d11f44 | 3662 | /* PowerPC 460 (guessed) */ |
082c6681 | 3663 | #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \ |
80d11f44 | 3664 | PPC_DCR | PPC_DCRX | PPC_DCRUX | \ |
f4078236 | 3665 | PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \ |
082c6681 JM |
3666 | PPC_CACHE | PPC_CACHE_ICBI | \ |
3667 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
3668 | PPC_MEM_TLBSYNC | PPC_TLBIVA | \ | |
3669 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ | |
3670 | PPC_440_SPEC) | |
80d11f44 JM |
3671 | #define POWERPC_MSRM_460 (0x000000000006FF30ULL) |
3672 | #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE) | |
3673 | #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE) | |
3674 | #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE) | |
3675 | #define POWERPC_BFDM_460 (bfd_mach_ppc_403) | |
3676 | #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3677 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 | 3678 | #define check_pow_460 check_pow_nocheck |
a750fc0b | 3679 | |
80d11f44 JM |
3680 | __attribute__ (( unused )) |
3681 | static void init_proc_460 (CPUPPCState *env) | |
3fc6c082 | 3682 | { |
a750fc0b JM |
3683 | /* Time base */ |
3684 | gen_tbl(env); | |
80d11f44 | 3685 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
a750fc0b | 3686 | gen_spr_440(env); |
80d11f44 JM |
3687 | gen_spr_usprgh(env); |
3688 | /* Processor identification */ | |
3689 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3690 | SPR_NOACCESS, SPR_NOACCESS, | |
3691 | &spr_read_generic, &spr_write_pir, | |
3692 | 0x00000000); | |
3693 | /* XXX : not implemented */ | |
3694 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3695 | SPR_NOACCESS, SPR_NOACCESS, | |
3696 | &spr_read_generic, &spr_write_generic, | |
3697 | 0x00000000); | |
3698 | /* XXX : not implemented */ | |
3699 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3700 | SPR_NOACCESS, SPR_NOACCESS, | |
3701 | &spr_read_generic, &spr_write_generic, | |
3702 | 0x00000000); | |
3703 | /* XXX : not implemented */ | |
3704 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3705 | SPR_NOACCESS, SPR_NOACCESS, | |
3706 | &spr_read_generic, &spr_write_generic, | |
3707 | 0x00000000); | |
3708 | /* XXX : not implemented */ | |
3709 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3710 | SPR_NOACCESS, SPR_NOACCESS, | |
3711 | &spr_read_generic, &spr_write_generic, | |
3712 | 0x00000000); | |
578bb252 | 3713 | /* XXX : not implemented */ |
a750fc0b JM |
3714 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
3715 | SPR_NOACCESS, SPR_NOACCESS, | |
3716 | &spr_read_generic, &spr_write_generic, | |
3717 | 0x00000000); | |
3718 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3719 | SPR_NOACCESS, SPR_NOACCESS, | |
3720 | &spr_read_generic, &spr_write_generic, | |
3721 | 0x00000000); | |
3722 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3723 | SPR_NOACCESS, SPR_NOACCESS, | |
3724 | &spr_read_generic, &spr_write_generic, | |
3725 | 0x00000000); | |
578bb252 | 3726 | /* XXX : not implemented */ |
a750fc0b JM |
3727 | spr_register(env, SPR_440_CCR1, "CCR1", |
3728 | SPR_NOACCESS, SPR_NOACCESS, | |
3729 | &spr_read_generic, &spr_write_generic, | |
3730 | 0x00000000); | |
80d11f44 JM |
3731 | /* XXX : not implemented */ |
3732 | spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", | |
3733 | &spr_read_generic, &spr_write_generic, | |
3734 | &spr_read_generic, &spr_write_generic, | |
3735 | 0x00000000); | |
a750fc0b | 3736 | /* Memory management */ |
f2e63a42 | 3737 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3738 | env->nb_tlb = 64; |
3739 | env->nb_ways = 1; | |
3740 | env->id_tlbs = 0; | |
f2e63a42 | 3741 | #endif |
e1833e1f | 3742 | init_excp_BookE(env); |
d63001d1 JM |
3743 | env->dcache_line_size = 32; |
3744 | env->icache_line_size = 32; | |
a750fc0b | 3745 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 FB |
3746 | } |
3747 | ||
80d11f44 | 3748 | /* PowerPC 460F (guessed) */ |
082c6681 JM |
3749 | #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \ |
3750 | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \ | |
3751 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
f4078236 | 3752 | PPC_FLOAT_STFIWX | PPC_MFTB | \ |
082c6681 JM |
3753 | PPC_DCR | PPC_DCRX | PPC_DCRUX | \ |
3754 | PPC_WRTEE | PPC_MFAPIDI | \ | |
3755 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
3756 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
3757 | PPC_MEM_TLBSYNC | PPC_TLBIVA | \ | |
3758 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \ | |
3759 | PPC_440_SPEC) | |
80d11f44 JM |
3760 | #define POWERPC_MSRM_460 (0x000000000006FF30ULL) |
3761 | #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE) | |
3762 | #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE) | |
3763 | #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE) | |
3764 | #define POWERPC_BFDM_460F (bfd_mach_ppc_403) | |
3765 | #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \ | |
4018bae9 | 3766 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK) |
80d11f44 | 3767 | #define check_pow_460F check_pow_nocheck |
a750fc0b | 3768 | |
80d11f44 JM |
3769 | __attribute__ (( unused )) |
3770 | static void init_proc_460F (CPUPPCState *env) | |
3fc6c082 | 3771 | { |
a750fc0b JM |
3772 | /* Time base */ |
3773 | gen_tbl(env); | |
80d11f44 | 3774 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
a750fc0b | 3775 | gen_spr_440(env); |
80d11f44 JM |
3776 | gen_spr_usprgh(env); |
3777 | /* Processor identification */ | |
3778 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3779 | SPR_NOACCESS, SPR_NOACCESS, | |
3780 | &spr_read_generic, &spr_write_pir, | |
3781 | 0x00000000); | |
3782 | /* XXX : not implemented */ | |
3783 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3784 | SPR_NOACCESS, SPR_NOACCESS, | |
3785 | &spr_read_generic, &spr_write_generic, | |
3786 | 0x00000000); | |
3787 | /* XXX : not implemented */ | |
3788 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3789 | SPR_NOACCESS, SPR_NOACCESS, | |
3790 | &spr_read_generic, &spr_write_generic, | |
3791 | 0x00000000); | |
3792 | /* XXX : not implemented */ | |
3793 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3794 | SPR_NOACCESS, SPR_NOACCESS, | |
3795 | &spr_read_generic, &spr_write_generic, | |
3796 | 0x00000000); | |
3797 | /* XXX : not implemented */ | |
3798 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3799 | SPR_NOACCESS, SPR_NOACCESS, | |
3800 | &spr_read_generic, &spr_write_generic, | |
3801 | 0x00000000); | |
3802 | /* XXX : not implemented */ | |
3803 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3804 | SPR_NOACCESS, SPR_NOACCESS, | |
3805 | &spr_read_generic, &spr_write_generic, | |
3806 | 0x00000000); | |
3807 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3808 | SPR_NOACCESS, SPR_NOACCESS, | |
3809 | &spr_read_generic, &spr_write_generic, | |
3810 | 0x00000000); | |
3811 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3812 | SPR_NOACCESS, SPR_NOACCESS, | |
3813 | &spr_read_generic, &spr_write_generic, | |
3814 | 0x00000000); | |
3815 | /* XXX : not implemented */ | |
3816 | spr_register(env, SPR_440_CCR1, "CCR1", | |
3817 | SPR_NOACCESS, SPR_NOACCESS, | |
3818 | &spr_read_generic, &spr_write_generic, | |
3819 | 0x00000000); | |
3820 | /* XXX : not implemented */ | |
3821 | spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", | |
3822 | &spr_read_generic, &spr_write_generic, | |
3823 | &spr_read_generic, &spr_write_generic, | |
3824 | 0x00000000); | |
a750fc0b | 3825 | /* Memory management */ |
f2e63a42 | 3826 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3827 | env->nb_tlb = 64; |
3828 | env->nb_ways = 1; | |
3829 | env->id_tlbs = 0; | |
f2e63a42 | 3830 | #endif |
e1833e1f | 3831 | init_excp_BookE(env); |
d63001d1 JM |
3832 | env->dcache_line_size = 32; |
3833 | env->icache_line_size = 32; | |
a750fc0b | 3834 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 FB |
3835 | } |
3836 | ||
80d11f44 JM |
3837 | /* Freescale 5xx cores (aka RCPU) */ |
3838 | #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \ | |
3839 | PPC_MEM_EIEIO | PPC_MEM_SYNC | \ | |
3840 | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \ | |
3841 | PPC_MFTB) | |
3842 | #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL) | |
3843 | #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL) | |
3844 | #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603) | |
3845 | #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU) | |
3846 | #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505) | |
4018bae9 JM |
3847 | #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ |
3848 | POWERPC_FLAG_BUS_CLK) | |
80d11f44 JM |
3849 | #define check_pow_MPC5xx check_pow_none |
3850 | ||
3851 | __attribute__ (( unused )) | |
3852 | static void init_proc_MPC5xx (CPUPPCState *env) | |
3853 | { | |
3854 | /* Time base */ | |
3855 | gen_tbl(env); | |
3856 | gen_spr_5xx_8xx(env); | |
3857 | gen_spr_5xx(env); | |
3858 | init_excp_MPC5xx(env); | |
3859 | env->dcache_line_size = 32; | |
3860 | env->icache_line_size = 32; | |
3861 | /* XXX: TODO: allocate internal IRQ controller */ | |
3862 | } | |
3863 | ||
3864 | /* Freescale 8xx cores (aka PowerQUICC) */ | |
3865 | #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \ | |
3866 | PPC_MEM_EIEIO | PPC_MEM_SYNC | \ | |
3867 | PPC_CACHE_ICBI | PPC_MFTB) | |
3868 | #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL) | |
3869 | #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx) | |
3870 | #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603) | |
3871 | #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU) | |
3872 | #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860) | |
4018bae9 JM |
3873 | #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ |
3874 | POWERPC_FLAG_BUS_CLK) | |
80d11f44 JM |
3875 | #define check_pow_MPC8xx check_pow_none |
3876 | ||
3877 | __attribute__ (( unused )) | |
3878 | static void init_proc_MPC8xx (CPUPPCState *env) | |
3879 | { | |
3880 | /* Time base */ | |
3881 | gen_tbl(env); | |
3882 | gen_spr_5xx_8xx(env); | |
3883 | gen_spr_8xx(env); | |
3884 | init_excp_MPC8xx(env); | |
3885 | env->dcache_line_size = 32; | |
3886 | env->icache_line_size = 32; | |
3887 | /* XXX: TODO: allocate internal IRQ controller */ | |
3888 | } | |
3889 | ||
3890 | /* Freescale 82xx cores (aka PowerQUICC-II) */ | |
3891 | /* PowerPC G2 */ | |
082c6681 JM |
3892 | #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
3893 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
3894 | PPC_FLOAT_STFIWX | \ | |
3895 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
3896 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
3897 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
3898 | PPC_SEGMENT | PPC_EXTERN) | |
80d11f44 JM |
3899 | #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL) |
3900 | #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx) | |
3901 | //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2) | |
3902 | #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx) | |
3903 | #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e) | |
3904 | #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \ | |
4018bae9 | 3905 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
80d11f44 | 3906 | #define check_pow_G2 check_pow_hid0 |
a750fc0b | 3907 | |
80d11f44 | 3908 | static void init_proc_G2 (CPUPPCState *env) |
3fc6c082 | 3909 | { |
80d11f44 JM |
3910 | gen_spr_ne_601(env); |
3911 | gen_spr_G2_755(env); | |
3912 | gen_spr_G2(env); | |
a750fc0b JM |
3913 | /* Time base */ |
3914 | gen_tbl(env); | |
bd928eba JM |
3915 | /* External access control */ |
3916 | /* XXX : not implemented */ | |
3917 | spr_register(env, SPR_EAR, "EAR", | |
3918 | SPR_NOACCESS, SPR_NOACCESS, | |
3919 | &spr_read_generic, &spr_write_generic, | |
3920 | 0x00000000); | |
80d11f44 JM |
3921 | /* Hardware implementation register */ |
3922 | /* XXX : not implemented */ | |
3923 | spr_register(env, SPR_HID0, "HID0", | |
3924 | SPR_NOACCESS, SPR_NOACCESS, | |
3925 | &spr_read_generic, &spr_write_generic, | |
3926 | 0x00000000); | |
3927 | /* XXX : not implemented */ | |
3928 | spr_register(env, SPR_HID1, "HID1", | |
3929 | SPR_NOACCESS, SPR_NOACCESS, | |
3930 | &spr_read_generic, &spr_write_generic, | |
3931 | 0x00000000); | |
3932 | /* XXX : not implemented */ | |
3933 | spr_register(env, SPR_HID2, "HID2", | |
3934 | SPR_NOACCESS, SPR_NOACCESS, | |
3935 | &spr_read_generic, &spr_write_generic, | |
3936 | 0x00000000); | |
a750fc0b | 3937 | /* Memory management */ |
80d11f44 JM |
3938 | gen_low_BATs(env); |
3939 | gen_high_BATs(env); | |
3940 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
3941 | init_excp_G2(env); | |
d63001d1 JM |
3942 | env->dcache_line_size = 32; |
3943 | env->icache_line_size = 32; | |
80d11f44 JM |
3944 | /* Allocate hardware IRQ controller */ |
3945 | ppc6xx_irq_init(env); | |
3fc6c082 | 3946 | } |
a750fc0b | 3947 | |
80d11f44 | 3948 | /* PowerPC G2LE */ |
082c6681 JM |
3949 | #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
3950 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
3951 | PPC_FLOAT_STFIWX | \ | |
3952 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
3953 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
3954 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
3955 | PPC_SEGMENT | PPC_EXTERN) | |
80d11f44 JM |
3956 | #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL) |
3957 | #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx) | |
3958 | #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2) | |
3959 | #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx) | |
3960 | #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e) | |
3961 | #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \ | |
4018bae9 | 3962 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
80d11f44 | 3963 | #define check_pow_G2LE check_pow_hid0 |
a750fc0b | 3964 | |
80d11f44 | 3965 | static void init_proc_G2LE (CPUPPCState *env) |
3fc6c082 | 3966 | { |
80d11f44 JM |
3967 | gen_spr_ne_601(env); |
3968 | gen_spr_G2_755(env); | |
3969 | gen_spr_G2(env); | |
a750fc0b JM |
3970 | /* Time base */ |
3971 | gen_tbl(env); | |
bd928eba JM |
3972 | /* External access control */ |
3973 | /* XXX : not implemented */ | |
3974 | spr_register(env, SPR_EAR, "EAR", | |
3975 | SPR_NOACCESS, SPR_NOACCESS, | |
3976 | &spr_read_generic, &spr_write_generic, | |
3977 | 0x00000000); | |
80d11f44 | 3978 | /* Hardware implementation register */ |
578bb252 | 3979 | /* XXX : not implemented */ |
80d11f44 | 3980 | spr_register(env, SPR_HID0, "HID0", |
a750fc0b JM |
3981 | SPR_NOACCESS, SPR_NOACCESS, |
3982 | &spr_read_generic, &spr_write_generic, | |
3983 | 0x00000000); | |
80d11f44 JM |
3984 | /* XXX : not implemented */ |
3985 | spr_register(env, SPR_HID1, "HID1", | |
a750fc0b JM |
3986 | SPR_NOACCESS, SPR_NOACCESS, |
3987 | &spr_read_generic, &spr_write_generic, | |
3988 | 0x00000000); | |
578bb252 | 3989 | /* XXX : not implemented */ |
80d11f44 | 3990 | spr_register(env, SPR_HID2, "HID2", |
a750fc0b JM |
3991 | SPR_NOACCESS, SPR_NOACCESS, |
3992 | &spr_read_generic, &spr_write_generic, | |
3993 | 0x00000000); | |
3994 | /* Memory management */ | |
80d11f44 JM |
3995 | gen_low_BATs(env); |
3996 | gen_high_BATs(env); | |
3997 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
3998 | init_excp_G2(env); | |
d63001d1 JM |
3999 | env->dcache_line_size = 32; |
4000 | env->icache_line_size = 32; | |
80d11f44 JM |
4001 | /* Allocate hardware IRQ controller */ |
4002 | ppc6xx_irq_init(env); | |
3fc6c082 FB |
4003 | } |
4004 | ||
80d11f44 JM |
4005 | /* e200 core */ |
4006 | /* XXX: unimplemented instructions: | |
4007 | * dcblc | |
4008 | * dcbtlst | |
4009 | * dcbtstls | |
4010 | * icblc | |
4011 | * icbtls | |
4012 | * tlbivax | |
4013 | * all SPE multiply-accumulate instructions | |
4014 | */ | |
082c6681 | 4015 | #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \ |
40569b7e | 4016 | PPC_SPE | PPC_SPE_SINGLE | \ |
082c6681 JM |
4017 | PPC_WRTEE | PPC_RFDI | \ |
4018 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ | |
4019 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
80d11f44 | 4020 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ |
082c6681 | 4021 | PPC_BOOKE) |
80d11f44 JM |
4022 | #define POWERPC_MSRM_e200 (0x000000000606FF30ULL) |
4023 | #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL) | |
4024 | #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE) | |
4025 | #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE) | |
4026 | #define POWERPC_BFDM_e200 (bfd_mach_ppc_860) | |
4027 | #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \ | |
4018bae9 JM |
4028 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \ |
4029 | POWERPC_FLAG_BUS_CLK) | |
80d11f44 JM |
4030 | #define check_pow_e200 check_pow_hid0 |
4031 | ||
578bb252 | 4032 | __attribute__ (( unused )) |
80d11f44 | 4033 | static void init_proc_e200 (CPUPPCState *env) |
3fc6c082 | 4034 | { |
e1833e1f JM |
4035 | /* Time base */ |
4036 | gen_tbl(env); | |
80d11f44 | 4037 | gen_spr_BookE(env, 0x000000070000FFFFULL); |
578bb252 | 4038 | /* XXX : not implemented */ |
80d11f44 | 4039 | spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", |
d34defbc AJ |
4040 | &spr_read_spefscr, &spr_write_spefscr, |
4041 | &spr_read_spefscr, &spr_write_spefscr, | |
e1833e1f | 4042 | 0x00000000); |
80d11f44 JM |
4043 | /* Memory management */ |
4044 | gen_spr_BookE_FSL(env, 0x0000005D); | |
4045 | /* XXX : not implemented */ | |
4046 | spr_register(env, SPR_HID0, "HID0", | |
e1833e1f JM |
4047 | SPR_NOACCESS, SPR_NOACCESS, |
4048 | &spr_read_generic, &spr_write_generic, | |
4049 | 0x00000000); | |
80d11f44 JM |
4050 | /* XXX : not implemented */ |
4051 | spr_register(env, SPR_HID1, "HID1", | |
e1833e1f JM |
4052 | SPR_NOACCESS, SPR_NOACCESS, |
4053 | &spr_read_generic, &spr_write_generic, | |
4054 | 0x00000000); | |
578bb252 | 4055 | /* XXX : not implemented */ |
80d11f44 | 4056 | spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", |
e1833e1f JM |
4057 | SPR_NOACCESS, SPR_NOACCESS, |
4058 | &spr_read_generic, &spr_write_generic, | |
4059 | 0x00000000); | |
578bb252 | 4060 | /* XXX : not implemented */ |
80d11f44 JM |
4061 | spr_register(env, SPR_Exxx_BUCSR, "BUCSR", |
4062 | SPR_NOACCESS, SPR_NOACCESS, | |
e1833e1f | 4063 | &spr_read_generic, &spr_write_generic, |
80d11f44 JM |
4064 | 0x00000000); |
4065 | /* XXX : not implemented */ | |
4066 | spr_register(env, SPR_Exxx_CTXCR, "CTXCR", | |
4067 | SPR_NOACCESS, SPR_NOACCESS, | |
4068 | &spr_read_generic, &spr_write_generic, | |
4069 | 0x00000000); | |
4070 | /* XXX : not implemented */ | |
4071 | spr_register(env, SPR_Exxx_DBCNT, "DBCNT", | |
4072 | SPR_NOACCESS, SPR_NOACCESS, | |
4073 | &spr_read_generic, &spr_write_generic, | |
4074 | 0x00000000); | |
4075 | /* XXX : not implemented */ | |
4076 | spr_register(env, SPR_Exxx_DBCR3, "DBCR3", | |
4077 | SPR_NOACCESS, SPR_NOACCESS, | |
4078 | &spr_read_generic, &spr_write_generic, | |
4079 | 0x00000000); | |
4080 | /* XXX : not implemented */ | |
4081 | spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", | |
4082 | SPR_NOACCESS, SPR_NOACCESS, | |
4083 | &spr_read_generic, &spr_write_generic, | |
4084 | 0x00000000); | |
4085 | /* XXX : not implemented */ | |
4086 | spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", | |
4087 | SPR_NOACCESS, SPR_NOACCESS, | |
4088 | &spr_read_generic, &spr_write_generic, | |
4089 | 0x00000000); | |
4090 | /* XXX : not implemented */ | |
4091 | spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", | |
4092 | SPR_NOACCESS, SPR_NOACCESS, | |
4093 | &spr_read_generic, &spr_write_generic, | |
4094 | 0x00000000); | |
4095 | /* XXX : not implemented */ | |
4096 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", | |
4097 | SPR_NOACCESS, SPR_NOACCESS, | |
4098 | &spr_read_generic, &spr_write_generic, | |
4099 | 0x00000000); | |
4100 | /* XXX : not implemented */ | |
4101 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", | |
4102 | SPR_NOACCESS, SPR_NOACCESS, | |
4103 | &spr_read_generic, &spr_write_generic, | |
4104 | 0x00000000); | |
4105 | /* XXX : not implemented */ | |
4106 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
4107 | SPR_NOACCESS, SPR_NOACCESS, | |
4108 | &spr_read_generic, &spr_write_generic, | |
4109 | 0x00000000); | |
4110 | /* XXX : not implemented */ | |
4111 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
4112 | SPR_NOACCESS, SPR_NOACCESS, | |
4113 | &spr_read_generic, &spr_write_generic, | |
4114 | 0x00000000); | |
4115 | spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", | |
4116 | SPR_NOACCESS, SPR_NOACCESS, | |
4117 | &spr_read_generic, &spr_write_generic, | |
4118 | 0x00000000); | |
4119 | spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", | |
4120 | SPR_NOACCESS, SPR_NOACCESS, | |
e1833e1f JM |
4121 | &spr_read_generic, &spr_write_generic, |
4122 | 0x00000000); | |
f2e63a42 | 4123 | #if !defined(CONFIG_USER_ONLY) |
e1833e1f JM |
4124 | env->nb_tlb = 64; |
4125 | env->nb_ways = 1; | |
4126 | env->id_tlbs = 0; | |
f2e63a42 | 4127 | #endif |
80d11f44 | 4128 | init_excp_e200(env); |
d63001d1 JM |
4129 | env->dcache_line_size = 32; |
4130 | env->icache_line_size = 32; | |
e1833e1f | 4131 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 | 4132 | } |
a750fc0b | 4133 | |
80d11f44 | 4134 | /* e300 core */ |
082c6681 JM |
4135 | #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4136 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4137 | PPC_FLOAT_STFIWX | \ | |
4138 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4139 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4140 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
4141 | PPC_SEGMENT | PPC_EXTERN) | |
80d11f44 JM |
4142 | #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL) |
4143 | #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx) | |
4144 | #define POWERPC_EXCP_e300 (POWERPC_EXCP_603) | |
4145 | #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx) | |
4146 | #define POWERPC_BFDM_e300 (bfd_mach_ppc_603) | |
4147 | #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \ | |
4018bae9 | 4148 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
80d11f44 | 4149 | #define check_pow_e300 check_pow_hid0 |
a750fc0b | 4150 | |
578bb252 | 4151 | __attribute__ (( unused )) |
80d11f44 | 4152 | static void init_proc_e300 (CPUPPCState *env) |
3fc6c082 | 4153 | { |
80d11f44 JM |
4154 | gen_spr_ne_601(env); |
4155 | gen_spr_603(env); | |
a750fc0b JM |
4156 | /* Time base */ |
4157 | gen_tbl(env); | |
80d11f44 JM |
4158 | /* hardware implementation registers */ |
4159 | /* XXX : not implemented */ | |
4160 | spr_register(env, SPR_HID0, "HID0", | |
4161 | SPR_NOACCESS, SPR_NOACCESS, | |
4162 | &spr_read_generic, &spr_write_generic, | |
4163 | 0x00000000); | |
4164 | /* XXX : not implemented */ | |
4165 | spr_register(env, SPR_HID1, "HID1", | |
4166 | SPR_NOACCESS, SPR_NOACCESS, | |
4167 | &spr_read_generic, &spr_write_generic, | |
4168 | 0x00000000); | |
4169 | /* Memory management */ | |
4170 | gen_low_BATs(env); | |
4171 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
4172 | init_excp_603(env); | |
4173 | env->dcache_line_size = 32; | |
4174 | env->icache_line_size = 32; | |
4175 | /* Allocate hardware IRQ controller */ | |
4176 | ppc6xx_irq_init(env); | |
4177 | } | |
4178 | ||
bd5ea513 AJ |
4179 | /* e500v1 core */ |
4180 | #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \ | |
4181 | PPC_SPE | PPC_SPE_SINGLE | \ | |
4182 | PPC_WRTEE | PPC_RFDI | \ | |
4183 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ | |
4184 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
4185 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ | |
4186 | PPC_BOOKE) | |
4187 | #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL) | |
4188 | #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL) | |
4189 | #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE) | |
4190 | #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE) | |
4191 | #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860) | |
4192 | #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \ | |
4193 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \ | |
4194 | POWERPC_FLAG_BUS_CLK) | |
4195 | #define check_pow_e500v1 check_pow_hid0 | |
4196 | #define init_proc_e500v1 init_proc_e500 | |
4197 | ||
4198 | /* e500v2 core */ | |
4199 | #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \ | |
4200 | PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \ | |
4201 | PPC_WRTEE | PPC_RFDI | \ | |
4202 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ | |
4203 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ | |
4204 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ | |
4205 | PPC_BOOKE) | |
4206 | #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL) | |
4207 | #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL) | |
4208 | #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE) | |
4209 | #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE) | |
4210 | #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860) | |
4211 | #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \ | |
4212 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \ | |
4213 | POWERPC_FLAG_BUS_CLK) | |
4214 | #define check_pow_e500v2 check_pow_hid0 | |
4215 | #define init_proc_e500v2 init_proc_e500 | |
80d11f44 | 4216 | |
80d11f44 JM |
4217 | static void init_proc_e500 (CPUPPCState *env) |
4218 | { | |
4219 | /* Time base */ | |
4220 | gen_tbl(env); | |
4221 | gen_spr_BookE(env, 0x0000000F0000FD7FULL); | |
4222 | /* Processor identification */ | |
4223 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
4224 | SPR_NOACCESS, SPR_NOACCESS, | |
4225 | &spr_read_generic, &spr_write_pir, | |
4226 | 0x00000000); | |
4227 | /* XXX : not implemented */ | |
4228 | spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", | |
d34defbc AJ |
4229 | &spr_read_spefscr, &spr_write_spefscr, |
4230 | &spr_read_spefscr, &spr_write_spefscr, | |
80d11f44 JM |
4231 | 0x00000000); |
4232 | /* Memory management */ | |
4233 | #if !defined(CONFIG_USER_ONLY) | |
4234 | env->nb_pids = 3; | |
4235 | #endif | |
4236 | gen_spr_BookE_FSL(env, 0x0000005F); | |
4237 | /* XXX : not implemented */ | |
4238 | spr_register(env, SPR_HID0, "HID0", | |
4239 | SPR_NOACCESS, SPR_NOACCESS, | |
4240 | &spr_read_generic, &spr_write_generic, | |
4241 | 0x00000000); | |
4242 | /* XXX : not implemented */ | |
4243 | spr_register(env, SPR_HID1, "HID1", | |
4244 | SPR_NOACCESS, SPR_NOACCESS, | |
4245 | &spr_read_generic, &spr_write_generic, | |
4246 | 0x00000000); | |
4247 | /* XXX : not implemented */ | |
4248 | spr_register(env, SPR_Exxx_BBEAR, "BBEAR", | |
4249 | SPR_NOACCESS, SPR_NOACCESS, | |
4250 | &spr_read_generic, &spr_write_generic, | |
4251 | 0x00000000); | |
4252 | /* XXX : not implemented */ | |
4253 | spr_register(env, SPR_Exxx_BBTAR, "BBTAR", | |
4254 | SPR_NOACCESS, SPR_NOACCESS, | |
4255 | &spr_read_generic, &spr_write_generic, | |
4256 | 0x00000000); | |
4257 | /* XXX : not implemented */ | |
4258 | spr_register(env, SPR_Exxx_MCAR, "MCAR", | |
4259 | SPR_NOACCESS, SPR_NOACCESS, | |
4260 | &spr_read_generic, &spr_write_generic, | |
4261 | 0x00000000); | |
578bb252 | 4262 | /* XXX : not implemented */ |
a750fc0b JM |
4263 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
4264 | SPR_NOACCESS, SPR_NOACCESS, | |
4265 | &spr_read_generic, &spr_write_generic, | |
4266 | 0x00000000); | |
80d11f44 JM |
4267 | /* XXX : not implemented */ |
4268 | spr_register(env, SPR_Exxx_NPIDR, "NPIDR", | |
a750fc0b JM |
4269 | SPR_NOACCESS, SPR_NOACCESS, |
4270 | &spr_read_generic, &spr_write_generic, | |
4271 | 0x00000000); | |
80d11f44 JM |
4272 | /* XXX : not implemented */ |
4273 | spr_register(env, SPR_Exxx_BUCSR, "BUCSR", | |
a750fc0b JM |
4274 | SPR_NOACCESS, SPR_NOACCESS, |
4275 | &spr_read_generic, &spr_write_generic, | |
4276 | 0x00000000); | |
578bb252 | 4277 | /* XXX : not implemented */ |
80d11f44 | 4278 | spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", |
a750fc0b JM |
4279 | SPR_NOACCESS, SPR_NOACCESS, |
4280 | &spr_read_generic, &spr_write_generic, | |
4281 | 0x00000000); | |
578bb252 | 4282 | /* XXX : not implemented */ |
80d11f44 JM |
4283 | spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", |
4284 | SPR_NOACCESS, SPR_NOACCESS, | |
a750fc0b | 4285 | &spr_read_generic, &spr_write_generic, |
80d11f44 JM |
4286 | 0x00000000); |
4287 | /* XXX : not implemented */ | |
4288 | spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", | |
4289 | SPR_NOACCESS, SPR_NOACCESS, | |
4290 | &spr_read_generic, &spr_write_generic, | |
4291 | 0x00000000); | |
4292 | /* XXX : not implemented */ | |
4293 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", | |
4294 | SPR_NOACCESS, SPR_NOACCESS, | |
4295 | &spr_read_generic, &spr_write_generic, | |
4296 | 0x00000000); | |
4297 | /* XXX : not implemented */ | |
4298 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", | |
4299 | SPR_NOACCESS, SPR_NOACCESS, | |
4300 | &spr_read_generic, &spr_write_generic, | |
4301 | 0x00000000); | |
4302 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
4303 | SPR_NOACCESS, SPR_NOACCESS, | |
4304 | &spr_read_generic, &spr_write_generic, | |
4305 | 0x00000000); | |
4306 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
4307 | SPR_NOACCESS, SPR_NOACCESS, | |
a750fc0b JM |
4308 | &spr_read_generic, &spr_write_generic, |
4309 | 0x00000000); | |
f2e63a42 | 4310 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
4311 | env->nb_tlb = 64; |
4312 | env->nb_ways = 1; | |
4313 | env->id_tlbs = 0; | |
f2e63a42 | 4314 | #endif |
80d11f44 | 4315 | init_excp_e200(env); |
d63001d1 JM |
4316 | env->dcache_line_size = 32; |
4317 | env->icache_line_size = 32; | |
9fdc60bf AJ |
4318 | /* Allocate hardware IRQ controller */ |
4319 | ppce500_irq_init(env); | |
3fc6c082 | 4320 | } |
a750fc0b | 4321 | |
a750fc0b | 4322 | /* Non-embedded PowerPC */ |
a750fc0b JM |
4323 | |
4324 | /* POWER : same as 601, without mfmsr, mfsr */ | |
4325 | #if defined(TODO) | |
4326 | #define POWERPC_INSNS_POWER (XXX_TODO) | |
4327 | /* POWER RSC (from RAD6000) */ | |
4328 | #define POWERPC_MSRM_POWER (0x00000000FEF0ULL) | |
4329 | #endif /* TODO */ | |
4330 | ||
4331 | /* PowerPC 601 */ | |
082c6681 JM |
4332 | #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \ |
4333 | PPC_FLOAT | \ | |
4334 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4335 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ | |
4336 | PPC_SEGMENT | PPC_EXTERN) | |
25ba3a68 | 4337 | #define POWERPC_MSRM_601 (0x000000000000FD70ULL) |
082c6681 | 4338 | #define POWERPC_MSRR_601 (0x0000000000001040ULL) |
faadf50e | 4339 | //#define POWERPC_MMU_601 (POWERPC_MMU_601) |
a750fc0b JM |
4340 | //#define POWERPC_EXCP_601 (POWERPC_EXCP_601) |
4341 | #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 4342 | #define POWERPC_BFDM_601 (bfd_mach_ppc_601) |
4018bae9 | 4343 | #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK) |
2f462816 | 4344 | #define check_pow_601 check_pow_none |
a750fc0b JM |
4345 | |
4346 | static void init_proc_601 (CPUPPCState *env) | |
3fc6c082 | 4347 | { |
a750fc0b JM |
4348 | gen_spr_ne_601(env); |
4349 | gen_spr_601(env); | |
4350 | /* Hardware implementation registers */ | |
4351 | /* XXX : not implemented */ | |
4352 | spr_register(env, SPR_HID0, "HID0", | |
4353 | SPR_NOACCESS, SPR_NOACCESS, | |
056401ea | 4354 | &spr_read_generic, &spr_write_hid0_601, |
faadf50e | 4355 | 0x80010080); |
a750fc0b JM |
4356 | /* XXX : not implemented */ |
4357 | spr_register(env, SPR_HID1, "HID1", | |
4358 | SPR_NOACCESS, SPR_NOACCESS, | |
4359 | &spr_read_generic, &spr_write_generic, | |
4360 | 0x00000000); | |
4361 | /* XXX : not implemented */ | |
4362 | spr_register(env, SPR_601_HID2, "HID2", | |
4363 | SPR_NOACCESS, SPR_NOACCESS, | |
4364 | &spr_read_generic, &spr_write_generic, | |
4365 | 0x00000000); | |
4366 | /* XXX : not implemented */ | |
4367 | spr_register(env, SPR_601_HID5, "HID5", | |
4368 | SPR_NOACCESS, SPR_NOACCESS, | |
4369 | &spr_read_generic, &spr_write_generic, | |
4370 | 0x00000000); | |
a750fc0b | 4371 | /* Memory management */ |
e1833e1f | 4372 | init_excp_601(env); |
082c6681 JM |
4373 | /* XXX: beware that dcache line size is 64 |
4374 | * but dcbz uses 32 bytes "sectors" | |
4375 | * XXX: this breaks clcs instruction ! | |
4376 | */ | |
4377 | env->dcache_line_size = 32; | |
d63001d1 | 4378 | env->icache_line_size = 64; |
faadf50e JM |
4379 | /* Allocate hardware IRQ controller */ |
4380 | ppc6xx_irq_init(env); | |
3fc6c082 FB |
4381 | } |
4382 | ||
082c6681 JM |
4383 | /* PowerPC 601v */ |
4384 | #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \ | |
4385 | PPC_FLOAT | \ | |
4386 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4387 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ | |
4388 | PPC_SEGMENT | PPC_EXTERN) | |
4389 | #define POWERPC_MSRM_601v (0x000000000000FD70ULL) | |
4390 | #define POWERPC_MSRR_601v (0x0000000000001040ULL) | |
4391 | #define POWERPC_MMU_601v (POWERPC_MMU_601) | |
4392 | #define POWERPC_EXCP_601v (POWERPC_EXCP_601) | |
4393 | #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx) | |
4394 | #define POWERPC_BFDM_601v (bfd_mach_ppc_601) | |
4395 | #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK) | |
4396 | #define check_pow_601v check_pow_none | |
4397 | ||
4398 | static void init_proc_601v (CPUPPCState *env) | |
4399 | { | |
4400 | init_proc_601(env); | |
4401 | /* XXX : not implemented */ | |
4402 | spr_register(env, SPR_601_HID15, "HID15", | |
4403 | SPR_NOACCESS, SPR_NOACCESS, | |
4404 | &spr_read_generic, &spr_write_generic, | |
4405 | 0x00000000); | |
4406 | } | |
4407 | ||
a750fc0b | 4408 | /* PowerPC 602 */ |
082c6681 JM |
4409 | #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4410 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4411 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4412 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4413 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4414 | PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \ | |
12de9a39 | 4415 | PPC_SEGMENT | PPC_602_SPEC) |
082c6681 JM |
4416 | #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL) |
4417 | /* XXX: 602 MMU is quite specific. Should add a special case */ | |
a750fc0b JM |
4418 | #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx) |
4419 | //#define POWERPC_EXCP_602 (POWERPC_EXCP_602) | |
4420 | #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 4421 | #define POWERPC_BFDM_602 (bfd_mach_ppc_602) |
25ba3a68 | 4422 | #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \ |
4018bae9 | 4423 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
2f462816 | 4424 | #define check_pow_602 check_pow_hid0 |
a750fc0b JM |
4425 | |
4426 | static void init_proc_602 (CPUPPCState *env) | |
3fc6c082 | 4427 | { |
a750fc0b JM |
4428 | gen_spr_ne_601(env); |
4429 | gen_spr_602(env); | |
4430 | /* Time base */ | |
4431 | gen_tbl(env); | |
4432 | /* hardware implementation registers */ | |
4433 | /* XXX : not implemented */ | |
4434 | spr_register(env, SPR_HID0, "HID0", | |
4435 | SPR_NOACCESS, SPR_NOACCESS, | |
4436 | &spr_read_generic, &spr_write_generic, | |
4437 | 0x00000000); | |
4438 | /* XXX : not implemented */ | |
4439 | spr_register(env, SPR_HID1, "HID1", | |
4440 | SPR_NOACCESS, SPR_NOACCESS, | |
4441 | &spr_read_generic, &spr_write_generic, | |
4442 | 0x00000000); | |
4443 | /* Memory management */ | |
4444 | gen_low_BATs(env); | |
4445 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 4446 | init_excp_602(env); |
d63001d1 JM |
4447 | env->dcache_line_size = 32; |
4448 | env->icache_line_size = 32; | |
a750fc0b JM |
4449 | /* Allocate hardware IRQ controller */ |
4450 | ppc6xx_irq_init(env); | |
4451 | } | |
3fc6c082 | 4452 | |
a750fc0b | 4453 | /* PowerPC 603 */ |
082c6681 JM |
4454 | #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4455 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4456 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4457 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4458 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4459 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
4460 | PPC_SEGMENT | PPC_EXTERN) | |
25ba3a68 | 4461 | #define POWERPC_MSRM_603 (0x000000000007FF73ULL) |
a750fc0b JM |
4462 | #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx) |
4463 | //#define POWERPC_EXCP_603 (POWERPC_EXCP_603) | |
4464 | #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 4465 | #define POWERPC_BFDM_603 (bfd_mach_ppc_603) |
25ba3a68 | 4466 | #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \ |
4018bae9 | 4467 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
2f462816 | 4468 | #define check_pow_603 check_pow_hid0 |
a750fc0b JM |
4469 | |
4470 | static void init_proc_603 (CPUPPCState *env) | |
4471 | { | |
4472 | gen_spr_ne_601(env); | |
4473 | gen_spr_603(env); | |
4474 | /* Time base */ | |
4475 | gen_tbl(env); | |
4476 | /* hardware implementation registers */ | |
4477 | /* XXX : not implemented */ | |
4478 | spr_register(env, SPR_HID0, "HID0", | |
4479 | SPR_NOACCESS, SPR_NOACCESS, | |
4480 | &spr_read_generic, &spr_write_generic, | |
4481 | 0x00000000); | |
4482 | /* XXX : not implemented */ | |
4483 | spr_register(env, SPR_HID1, "HID1", | |
4484 | SPR_NOACCESS, SPR_NOACCESS, | |
4485 | &spr_read_generic, &spr_write_generic, | |
4486 | 0x00000000); | |
4487 | /* Memory management */ | |
4488 | gen_low_BATs(env); | |
4489 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 4490 | init_excp_603(env); |
d63001d1 JM |
4491 | env->dcache_line_size = 32; |
4492 | env->icache_line_size = 32; | |
a750fc0b JM |
4493 | /* Allocate hardware IRQ controller */ |
4494 | ppc6xx_irq_init(env); | |
3fc6c082 FB |
4495 | } |
4496 | ||
a750fc0b | 4497 | /* PowerPC 603e */ |
082c6681 JM |
4498 | #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4499 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4500 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4501 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4502 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4503 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
4504 | PPC_SEGMENT | PPC_EXTERN) | |
a750fc0b JM |
4505 | #define POWERPC_MSRM_603E (0x000000000007FF73ULL) |
4506 | #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx) | |
4507 | //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E) | |
4508 | #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 4509 | #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e) |
25ba3a68 | 4510 | #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \ |
4018bae9 | 4511 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK) |
2f462816 | 4512 | #define check_pow_603E check_pow_hid0 |
a750fc0b JM |
4513 | |
4514 | static void init_proc_603E (CPUPPCState *env) | |
4515 | { | |
4516 | gen_spr_ne_601(env); | |
4517 | gen_spr_603(env); | |
4518 | /* Time base */ | |
4519 | gen_tbl(env); | |
4520 | /* hardware implementation registers */ | |
4521 | /* XXX : not implemented */ | |
4522 | spr_register(env, SPR_HID0, "HID0", | |
4523 | SPR_NOACCESS, SPR_NOACCESS, | |
4524 | &spr_read_generic, &spr_write_generic, | |
4525 | 0x00000000); | |
4526 | /* XXX : not implemented */ | |
4527 | spr_register(env, SPR_HID1, "HID1", | |
4528 | SPR_NOACCESS, SPR_NOACCESS, | |
4529 | &spr_read_generic, &spr_write_generic, | |
4530 | 0x00000000); | |
4531 | /* XXX : not implemented */ | |
4532 | spr_register(env, SPR_IABR, "IABR", | |
4533 | SPR_NOACCESS, SPR_NOACCESS, | |
4534 | &spr_read_generic, &spr_write_generic, | |
4535 | 0x00000000); | |
4536 | /* Memory management */ | |
4537 | gen_low_BATs(env); | |
4538 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 4539 | init_excp_603(env); |
d63001d1 JM |
4540 | env->dcache_line_size = 32; |
4541 | env->icache_line_size = 32; | |
a750fc0b JM |
4542 | /* Allocate hardware IRQ controller */ |
4543 | ppc6xx_irq_init(env); | |
4544 | } | |
4545 | ||
a750fc0b | 4546 | /* PowerPC 604 */ |
082c6681 JM |
4547 | #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4548 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4549 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4550 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4551 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4552 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4553 | PPC_SEGMENT | PPC_EXTERN) | |
a750fc0b JM |
4554 | #define POWERPC_MSRM_604 (0x000000000005FF77ULL) |
4555 | #define POWERPC_MMU_604 (POWERPC_MMU_32B) | |
4556 | //#define POWERPC_EXCP_604 (POWERPC_EXCP_604) | |
4557 | #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 4558 | #define POWERPC_BFDM_604 (bfd_mach_ppc_604) |
25ba3a68 | 4559 | #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ |
4018bae9 | 4560 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
2f462816 | 4561 | #define check_pow_604 check_pow_nocheck |
a750fc0b JM |
4562 | |
4563 | static void init_proc_604 (CPUPPCState *env) | |
4564 | { | |
4565 | gen_spr_ne_601(env); | |
4566 | gen_spr_604(env); | |
4567 | /* Time base */ | |
4568 | gen_tbl(env); | |
4569 | /* Hardware implementation registers */ | |
4570 | /* XXX : not implemented */ | |
082c6681 JM |
4571 | spr_register(env, SPR_HID0, "HID0", |
4572 | SPR_NOACCESS, SPR_NOACCESS, | |
4573 | &spr_read_generic, &spr_write_generic, | |
4574 | 0x00000000); | |
4575 | /* Memory management */ | |
4576 | gen_low_BATs(env); | |
4577 | init_excp_604(env); | |
4578 | env->dcache_line_size = 32; | |
4579 | env->icache_line_size = 32; | |
4580 | /* Allocate hardware IRQ controller */ | |
4581 | ppc6xx_irq_init(env); | |
4582 | } | |
4583 | ||
4584 | /* PowerPC 604E */ | |
4585 | #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
4586 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4587 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4588 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4589 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4590 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4591 | PPC_SEGMENT | PPC_EXTERN) | |
4592 | #define POWERPC_MSRM_604E (0x000000000005FF77ULL) | |
4593 | #define POWERPC_MMU_604E (POWERPC_MMU_32B) | |
4594 | #define POWERPC_EXCP_604E (POWERPC_EXCP_604) | |
4595 | #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx) | |
4596 | #define POWERPC_BFDM_604E (bfd_mach_ppc_604) | |
4597 | #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
4598 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) | |
4599 | #define check_pow_604E check_pow_nocheck | |
4600 | ||
4601 | static void init_proc_604E (CPUPPCState *env) | |
4602 | { | |
4603 | gen_spr_ne_601(env); | |
4604 | gen_spr_604(env); | |
4605 | /* XXX : not implemented */ | |
4606 | spr_register(env, SPR_MMCR1, "MMCR1", | |
4607 | SPR_NOACCESS, SPR_NOACCESS, | |
4608 | &spr_read_generic, &spr_write_generic, | |
4609 | 0x00000000); | |
4610 | /* XXX : not implemented */ | |
4611 | spr_register(env, SPR_PMC3, "PMC3", | |
4612 | SPR_NOACCESS, SPR_NOACCESS, | |
4613 | &spr_read_generic, &spr_write_generic, | |
4614 | 0x00000000); | |
4615 | /* XXX : not implemented */ | |
4616 | spr_register(env, SPR_PMC4, "PMC4", | |
4617 | SPR_NOACCESS, SPR_NOACCESS, | |
4618 | &spr_read_generic, &spr_write_generic, | |
4619 | 0x00000000); | |
4620 | /* Time base */ | |
4621 | gen_tbl(env); | |
4622 | /* Hardware implementation registers */ | |
4623 | /* XXX : not implemented */ | |
a750fc0b JM |
4624 | spr_register(env, SPR_HID0, "HID0", |
4625 | SPR_NOACCESS, SPR_NOACCESS, | |
4626 | &spr_read_generic, &spr_write_generic, | |
4627 | 0x00000000); | |
4628 | /* XXX : not implemented */ | |
4629 | spr_register(env, SPR_HID1, "HID1", | |
4630 | SPR_NOACCESS, SPR_NOACCESS, | |
4631 | &spr_read_generic, &spr_write_generic, | |
4632 | 0x00000000); | |
4633 | /* Memory management */ | |
4634 | gen_low_BATs(env); | |
e1833e1f | 4635 | init_excp_604(env); |
d63001d1 JM |
4636 | env->dcache_line_size = 32; |
4637 | env->icache_line_size = 32; | |
a750fc0b JM |
4638 | /* Allocate hardware IRQ controller */ |
4639 | ppc6xx_irq_init(env); | |
4640 | } | |
4641 | ||
bd928eba JM |
4642 | /* PowerPC 740 */ |
4643 | #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
082c6681 | 4644 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
bd928eba | 4645 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
082c6681 JM |
4646 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4647 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4648 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4649 | PPC_SEGMENT | PPC_EXTERN) | |
bd928eba JM |
4650 | #define POWERPC_MSRM_740 (0x000000000005FF77ULL) |
4651 | #define POWERPC_MMU_740 (POWERPC_MMU_32B) | |
4652 | #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0) | |
4653 | #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx) | |
4654 | #define POWERPC_BFDM_740 (bfd_mach_ppc_750) | |
4655 | #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
4018bae9 | 4656 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
bd928eba | 4657 | #define check_pow_740 check_pow_hid0 |
a750fc0b | 4658 | |
bd928eba | 4659 | static void init_proc_740 (CPUPPCState *env) |
a750fc0b JM |
4660 | { |
4661 | gen_spr_ne_601(env); | |
4662 | gen_spr_7xx(env); | |
4663 | /* Time base */ | |
4664 | gen_tbl(env); | |
4665 | /* Thermal management */ | |
4666 | gen_spr_thrm(env); | |
4667 | /* Hardware implementation registers */ | |
4668 | /* XXX : not implemented */ | |
4669 | spr_register(env, SPR_HID0, "HID0", | |
4670 | SPR_NOACCESS, SPR_NOACCESS, | |
4671 | &spr_read_generic, &spr_write_generic, | |
4672 | 0x00000000); | |
4673 | /* XXX : not implemented */ | |
4674 | spr_register(env, SPR_HID1, "HID1", | |
4675 | SPR_NOACCESS, SPR_NOACCESS, | |
4676 | &spr_read_generic, &spr_write_generic, | |
4677 | 0x00000000); | |
4678 | /* Memory management */ | |
4679 | gen_low_BATs(env); | |
e1833e1f | 4680 | init_excp_7x0(env); |
d63001d1 JM |
4681 | env->dcache_line_size = 32; |
4682 | env->icache_line_size = 32; | |
a750fc0b JM |
4683 | /* Allocate hardware IRQ controller */ |
4684 | ppc6xx_irq_init(env); | |
4685 | } | |
4686 | ||
bd928eba JM |
4687 | /* PowerPC 750 */ |
4688 | #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
4689 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4690 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4691 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4692 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4693 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4694 | PPC_SEGMENT | PPC_EXTERN) | |
4695 | #define POWERPC_MSRM_750 (0x000000000005FF77ULL) | |
4696 | #define POWERPC_MMU_750 (POWERPC_MMU_32B) | |
4697 | #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0) | |
4698 | #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx) | |
4699 | #define POWERPC_BFDM_750 (bfd_mach_ppc_750) | |
4700 | #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
4701 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) | |
4702 | #define check_pow_750 check_pow_hid0 | |
4703 | ||
4704 | static void init_proc_750 (CPUPPCState *env) | |
4705 | { | |
4706 | gen_spr_ne_601(env); | |
4707 | gen_spr_7xx(env); | |
4708 | /* XXX : not implemented */ | |
4709 | spr_register(env, SPR_L2CR, "L2CR", | |
4710 | SPR_NOACCESS, SPR_NOACCESS, | |
4711 | &spr_read_generic, &spr_write_generic, | |
4712 | 0x00000000); | |
4713 | /* Time base */ | |
4714 | gen_tbl(env); | |
4715 | /* Thermal management */ | |
4716 | gen_spr_thrm(env); | |
4717 | /* Hardware implementation registers */ | |
4718 | /* XXX : not implemented */ | |
4719 | spr_register(env, SPR_HID0, "HID0", | |
4720 | SPR_NOACCESS, SPR_NOACCESS, | |
4721 | &spr_read_generic, &spr_write_generic, | |
4722 | 0x00000000); | |
4723 | /* XXX : not implemented */ | |
4724 | spr_register(env, SPR_HID1, "HID1", | |
4725 | SPR_NOACCESS, SPR_NOACCESS, | |
4726 | &spr_read_generic, &spr_write_generic, | |
4727 | 0x00000000); | |
4728 | /* Memory management */ | |
4729 | gen_low_BATs(env); | |
4730 | /* XXX: high BATs are also present but are known to be bugged on | |
4731 | * die version 1.x | |
4732 | */ | |
4733 | init_excp_7x0(env); | |
4734 | env->dcache_line_size = 32; | |
4735 | env->icache_line_size = 32; | |
4736 | /* Allocate hardware IRQ controller */ | |
4737 | ppc6xx_irq_init(env); | |
4738 | } | |
4739 | ||
4740 | /* PowerPC 750 CL */ | |
4741 | /* XXX: not implemented: | |
4742 | * cache lock instructions: | |
4743 | * dcbz_l | |
4744 | * floating point paired instructions | |
4745 | * psq_lux | |
4746 | * psq_lx | |
4747 | * psq_stux | |
4748 | * psq_stx | |
4749 | * ps_abs | |
4750 | * ps_add | |
4751 | * ps_cmpo0 | |
4752 | * ps_cmpo1 | |
4753 | * ps_cmpu0 | |
4754 | * ps_cmpu1 | |
4755 | * ps_div | |
4756 | * ps_madd | |
4757 | * ps_madds0 | |
4758 | * ps_madds1 | |
4759 | * ps_merge00 | |
4760 | * ps_merge01 | |
4761 | * ps_merge10 | |
4762 | * ps_merge11 | |
4763 | * ps_mr | |
4764 | * ps_msub | |
4765 | * ps_mul | |
4766 | * ps_muls0 | |
4767 | * ps_muls1 | |
4768 | * ps_nabs | |
4769 | * ps_neg | |
4770 | * ps_nmadd | |
4771 | * ps_nmsub | |
4772 | * ps_res | |
4773 | * ps_rsqrte | |
4774 | * ps_sel | |
4775 | * ps_sub | |
4776 | * ps_sum0 | |
4777 | * ps_sum1 | |
4778 | */ | |
4779 | #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
4780 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4781 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4782 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4783 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4784 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4785 | PPC_SEGMENT | PPC_EXTERN) | |
4786 | #define POWERPC_MSRM_750cl (0x000000000005FF77ULL) | |
4787 | #define POWERPC_MMU_750cl (POWERPC_MMU_32B) | |
4788 | #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0) | |
4789 | #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx) | |
4790 | #define POWERPC_BFDM_750cl (bfd_mach_ppc_750) | |
4791 | #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
4792 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) | |
4793 | #define check_pow_750cl check_pow_hid0 | |
4794 | ||
4795 | static void init_proc_750cl (CPUPPCState *env) | |
4796 | { | |
4797 | gen_spr_ne_601(env); | |
4798 | gen_spr_7xx(env); | |
4799 | /* XXX : not implemented */ | |
4800 | spr_register(env, SPR_L2CR, "L2CR", | |
4801 | SPR_NOACCESS, SPR_NOACCESS, | |
4802 | &spr_read_generic, &spr_write_generic, | |
4803 | 0x00000000); | |
4804 | /* Time base */ | |
4805 | gen_tbl(env); | |
4806 | /* Thermal management */ | |
4807 | /* Those registers are fake on 750CL */ | |
4808 | spr_register(env, SPR_THRM1, "THRM1", | |
4809 | SPR_NOACCESS, SPR_NOACCESS, | |
4810 | &spr_read_generic, &spr_write_generic, | |
4811 | 0x00000000); | |
4812 | spr_register(env, SPR_THRM2, "THRM2", | |
4813 | SPR_NOACCESS, SPR_NOACCESS, | |
4814 | &spr_read_generic, &spr_write_generic, | |
4815 | 0x00000000); | |
4816 | spr_register(env, SPR_THRM3, "THRM3", | |
4817 | SPR_NOACCESS, SPR_NOACCESS, | |
4818 | &spr_read_generic, &spr_write_generic, | |
4819 | 0x00000000); | |
4820 | /* XXX: not implemented */ | |
4821 | spr_register(env, SPR_750_TDCL, "TDCL", | |
4822 | SPR_NOACCESS, SPR_NOACCESS, | |
4823 | &spr_read_generic, &spr_write_generic, | |
4824 | 0x00000000); | |
4825 | spr_register(env, SPR_750_TDCH, "TDCH", | |
4826 | SPR_NOACCESS, SPR_NOACCESS, | |
4827 | &spr_read_generic, &spr_write_generic, | |
4828 | 0x00000000); | |
4829 | /* DMA */ | |
4830 | /* XXX : not implemented */ | |
4831 | spr_register(env, SPR_750_WPAR, "WPAR", | |
4832 | SPR_NOACCESS, SPR_NOACCESS, | |
4833 | &spr_read_generic, &spr_write_generic, | |
4834 | 0x00000000); | |
4835 | spr_register(env, SPR_750_DMAL, "DMAL", | |
4836 | SPR_NOACCESS, SPR_NOACCESS, | |
4837 | &spr_read_generic, &spr_write_generic, | |
4838 | 0x00000000); | |
4839 | spr_register(env, SPR_750_DMAU, "DMAU", | |
4840 | SPR_NOACCESS, SPR_NOACCESS, | |
4841 | &spr_read_generic, &spr_write_generic, | |
4842 | 0x00000000); | |
4843 | /* Hardware implementation registers */ | |
4844 | /* XXX : not implemented */ | |
4845 | spr_register(env, SPR_HID0, "HID0", | |
4846 | SPR_NOACCESS, SPR_NOACCESS, | |
4847 | &spr_read_generic, &spr_write_generic, | |
4848 | 0x00000000); | |
4849 | /* XXX : not implemented */ | |
4850 | spr_register(env, SPR_HID1, "HID1", | |
4851 | SPR_NOACCESS, SPR_NOACCESS, | |
4852 | &spr_read_generic, &spr_write_generic, | |
4853 | 0x00000000); | |
4854 | /* XXX : not implemented */ | |
4855 | spr_register(env, SPR_750CL_HID2, "HID2", | |
4856 | SPR_NOACCESS, SPR_NOACCESS, | |
4857 | &spr_read_generic, &spr_write_generic, | |
4858 | 0x00000000); | |
4859 | /* XXX : not implemented */ | |
4860 | spr_register(env, SPR_750CL_HID4, "HID4", | |
4861 | SPR_NOACCESS, SPR_NOACCESS, | |
4862 | &spr_read_generic, &spr_write_generic, | |
4863 | 0x00000000); | |
4864 | /* Quantization registers */ | |
4865 | /* XXX : not implemented */ | |
4866 | spr_register(env, SPR_750_GQR0, "GQR0", | |
4867 | SPR_NOACCESS, SPR_NOACCESS, | |
4868 | &spr_read_generic, &spr_write_generic, | |
4869 | 0x00000000); | |
4870 | /* XXX : not implemented */ | |
4871 | spr_register(env, SPR_750_GQR1, "GQR1", | |
4872 | SPR_NOACCESS, SPR_NOACCESS, | |
4873 | &spr_read_generic, &spr_write_generic, | |
4874 | 0x00000000); | |
4875 | /* XXX : not implemented */ | |
4876 | spr_register(env, SPR_750_GQR2, "GQR2", | |
4877 | SPR_NOACCESS, SPR_NOACCESS, | |
4878 | &spr_read_generic, &spr_write_generic, | |
4879 | 0x00000000); | |
4880 | /* XXX : not implemented */ | |
4881 | spr_register(env, SPR_750_GQR3, "GQR3", | |
4882 | SPR_NOACCESS, SPR_NOACCESS, | |
4883 | &spr_read_generic, &spr_write_generic, | |
4884 | 0x00000000); | |
4885 | /* XXX : not implemented */ | |
4886 | spr_register(env, SPR_750_GQR4, "GQR4", | |
4887 | SPR_NOACCESS, SPR_NOACCESS, | |
4888 | &spr_read_generic, &spr_write_generic, | |
4889 | 0x00000000); | |
4890 | /* XXX : not implemented */ | |
4891 | spr_register(env, SPR_750_GQR5, "GQR5", | |
4892 | SPR_NOACCESS, SPR_NOACCESS, | |
4893 | &spr_read_generic, &spr_write_generic, | |
4894 | 0x00000000); | |
4895 | /* XXX : not implemented */ | |
4896 | spr_register(env, SPR_750_GQR6, "GQR6", | |
4897 | SPR_NOACCESS, SPR_NOACCESS, | |
4898 | &spr_read_generic, &spr_write_generic, | |
4899 | 0x00000000); | |
4900 | /* XXX : not implemented */ | |
4901 | spr_register(env, SPR_750_GQR7, "GQR7", | |
4902 | SPR_NOACCESS, SPR_NOACCESS, | |
4903 | &spr_read_generic, &spr_write_generic, | |
4904 | 0x00000000); | |
4905 | /* Memory management */ | |
4906 | gen_low_BATs(env); | |
4907 | /* PowerPC 750cl has 8 DBATs and 8 IBATs */ | |
4908 | gen_high_BATs(env); | |
4909 | init_excp_750cl(env); | |
4910 | env->dcache_line_size = 32; | |
4911 | env->icache_line_size = 32; | |
4912 | /* Allocate hardware IRQ controller */ | |
4913 | ppc6xx_irq_init(env); | |
4914 | } | |
4915 | ||
4e777442 | 4916 | /* PowerPC 750CX */ |
bd928eba JM |
4917 | #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4918 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
4919 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
4920 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
4921 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4922 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4923 | PPC_SEGMENT | PPC_EXTERN) | |
4924 | #define POWERPC_MSRM_750cx (0x000000000005FF77ULL) | |
4925 | #define POWERPC_MMU_750cx (POWERPC_MMU_32B) | |
4926 | #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0) | |
4927 | #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx) | |
4928 | #define POWERPC_BFDM_750cx (bfd_mach_ppc_750) | |
4929 | #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
4930 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) | |
4931 | #define check_pow_750cx check_pow_hid0 | |
4932 | ||
4933 | static void init_proc_750cx (CPUPPCState *env) | |
4934 | { | |
4935 | gen_spr_ne_601(env); | |
4936 | gen_spr_7xx(env); | |
4937 | /* XXX : not implemented */ | |
4938 | spr_register(env, SPR_L2CR, "L2CR", | |
4939 | SPR_NOACCESS, SPR_NOACCESS, | |
4940 | &spr_read_generic, &spr_write_generic, | |
4941 | 0x00000000); | |
4942 | /* Time base */ | |
4943 | gen_tbl(env); | |
4944 | /* Thermal management */ | |
4945 | gen_spr_thrm(env); | |
4946 | /* This register is not implemented but is present for compatibility */ | |
4947 | spr_register(env, SPR_SDA, "SDA", | |
4948 | SPR_NOACCESS, SPR_NOACCESS, | |
4949 | &spr_read_generic, &spr_write_generic, | |
4950 | 0x00000000); | |
4951 | /* Hardware implementation registers */ | |
4952 | /* XXX : not implemented */ | |
4953 | spr_register(env, SPR_HID0, "HID0", | |
4954 | SPR_NOACCESS, SPR_NOACCESS, | |
4955 | &spr_read_generic, &spr_write_generic, | |
4956 | 0x00000000); | |
4957 | /* XXX : not implemented */ | |
4958 | spr_register(env, SPR_HID1, "HID1", | |
4959 | SPR_NOACCESS, SPR_NOACCESS, | |
4960 | &spr_read_generic, &spr_write_generic, | |
4961 | 0x00000000); | |
4962 | /* Memory management */ | |
4963 | gen_low_BATs(env); | |
4e777442 JM |
4964 | /* PowerPC 750cx has 8 DBATs and 8 IBATs */ |
4965 | gen_high_BATs(env); | |
bd928eba JM |
4966 | init_excp_750cx(env); |
4967 | env->dcache_line_size = 32; | |
4968 | env->icache_line_size = 32; | |
4969 | /* Allocate hardware IRQ controller */ | |
4970 | ppc6xx_irq_init(env); | |
4971 | } | |
4972 | ||
4973 | /* PowerPC 750FX */ | |
082c6681 JM |
4974 | #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
4975 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
bd928eba | 4976 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
082c6681 JM |
4977 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
4978 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
4979 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
4980 | PPC_SEGMENT | PPC_EXTERN) | |
25ba3a68 | 4981 | #define POWERPC_MSRM_750fx (0x000000000005FF77ULL) |
a750fc0b JM |
4982 | #define POWERPC_MMU_750fx (POWERPC_MMU_32B) |
4983 | #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0) | |
4984 | #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 4985 | #define POWERPC_BFDM_750fx (bfd_mach_ppc_750) |
25ba3a68 | 4986 | #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ |
4018bae9 | 4987 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
2f462816 | 4988 | #define check_pow_750fx check_pow_hid0 |
a750fc0b JM |
4989 | |
4990 | static void init_proc_750fx (CPUPPCState *env) | |
4991 | { | |
4992 | gen_spr_ne_601(env); | |
4993 | gen_spr_7xx(env); | |
bd928eba JM |
4994 | /* XXX : not implemented */ |
4995 | spr_register(env, SPR_L2CR, "L2CR", | |
4996 | SPR_NOACCESS, SPR_NOACCESS, | |
4997 | &spr_read_generic, &spr_write_generic, | |
4998 | 0x00000000); | |
a750fc0b JM |
4999 | /* Time base */ |
5000 | gen_tbl(env); | |
5001 | /* Thermal management */ | |
5002 | gen_spr_thrm(env); | |
bd928eba JM |
5003 | /* XXX : not implemented */ |
5004 | spr_register(env, SPR_750_THRM4, "THRM4", | |
5005 | SPR_NOACCESS, SPR_NOACCESS, | |
5006 | &spr_read_generic, &spr_write_generic, | |
5007 | 0x00000000); | |
a750fc0b JM |
5008 | /* Hardware implementation registers */ |
5009 | /* XXX : not implemented */ | |
5010 | spr_register(env, SPR_HID0, "HID0", | |
5011 | SPR_NOACCESS, SPR_NOACCESS, | |
5012 | &spr_read_generic, &spr_write_generic, | |
5013 | 0x00000000); | |
5014 | /* XXX : not implemented */ | |
5015 | spr_register(env, SPR_HID1, "HID1", | |
5016 | SPR_NOACCESS, SPR_NOACCESS, | |
5017 | &spr_read_generic, &spr_write_generic, | |
5018 | 0x00000000); | |
5019 | /* XXX : not implemented */ | |
bd928eba | 5020 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
5021 | SPR_NOACCESS, SPR_NOACCESS, |
5022 | &spr_read_generic, &spr_write_generic, | |
5023 | 0x00000000); | |
5024 | /* Memory management */ | |
5025 | gen_low_BATs(env); | |
5026 | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ | |
5027 | gen_high_BATs(env); | |
bd928eba | 5028 | init_excp_7x0(env); |
d63001d1 JM |
5029 | env->dcache_line_size = 32; |
5030 | env->icache_line_size = 32; | |
a750fc0b JM |
5031 | /* Allocate hardware IRQ controller */ |
5032 | ppc6xx_irq_init(env); | |
5033 | } | |
5034 | ||
bd928eba JM |
5035 | /* PowerPC 750GX */ |
5036 | #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
082c6681 | 5037 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ |
bd928eba JM |
5038 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ |
5039 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
5040 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5041 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5042 | PPC_SEGMENT | PPC_EXTERN) | |
5043 | #define POWERPC_MSRM_750gx (0x000000000005FF77ULL) | |
5044 | #define POWERPC_MMU_750gx (POWERPC_MMU_32B) | |
5045 | #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0) | |
5046 | #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx) | |
5047 | #define POWERPC_BFDM_750gx (bfd_mach_ppc_750) | |
5048 | #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
5049 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) | |
5050 | #define check_pow_750gx check_pow_hid0 | |
5051 | ||
5052 | static void init_proc_750gx (CPUPPCState *env) | |
5053 | { | |
5054 | gen_spr_ne_601(env); | |
5055 | gen_spr_7xx(env); | |
5056 | /* XXX : not implemented (XXX: different from 750fx) */ | |
5057 | spr_register(env, SPR_L2CR, "L2CR", | |
5058 | SPR_NOACCESS, SPR_NOACCESS, | |
5059 | &spr_read_generic, &spr_write_generic, | |
5060 | 0x00000000); | |
5061 | /* Time base */ | |
5062 | gen_tbl(env); | |
5063 | /* Thermal management */ | |
5064 | gen_spr_thrm(env); | |
5065 | /* XXX : not implemented */ | |
5066 | spr_register(env, SPR_750_THRM4, "THRM4", | |
5067 | SPR_NOACCESS, SPR_NOACCESS, | |
5068 | &spr_read_generic, &spr_write_generic, | |
5069 | 0x00000000); | |
5070 | /* Hardware implementation registers */ | |
5071 | /* XXX : not implemented (XXX: different from 750fx) */ | |
5072 | spr_register(env, SPR_HID0, "HID0", | |
5073 | SPR_NOACCESS, SPR_NOACCESS, | |
5074 | &spr_read_generic, &spr_write_generic, | |
5075 | 0x00000000); | |
5076 | /* XXX : not implemented */ | |
5077 | spr_register(env, SPR_HID1, "HID1", | |
5078 | SPR_NOACCESS, SPR_NOACCESS, | |
5079 | &spr_read_generic, &spr_write_generic, | |
5080 | 0x00000000); | |
5081 | /* XXX : not implemented (XXX: different from 750fx) */ | |
5082 | spr_register(env, SPR_750FX_HID2, "HID2", | |
5083 | SPR_NOACCESS, SPR_NOACCESS, | |
5084 | &spr_read_generic, &spr_write_generic, | |
5085 | 0x00000000); | |
5086 | /* Memory management */ | |
5087 | gen_low_BATs(env); | |
5088 | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ | |
5089 | gen_high_BATs(env); | |
5090 | init_excp_7x0(env); | |
5091 | env->dcache_line_size = 32; | |
5092 | env->icache_line_size = 32; | |
5093 | /* Allocate hardware IRQ controller */ | |
5094 | ppc6xx_irq_init(env); | |
5095 | } | |
5096 | ||
5097 | /* PowerPC 745 */ | |
5098 | #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
5099 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5100 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
5101 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
5102 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5103 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
5104 | PPC_SEGMENT | PPC_EXTERN) | |
5105 | #define POWERPC_MSRM_745 (0x000000000005FF77ULL) | |
5106 | #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx) | |
5107 | #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5) | |
5108 | #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx) | |
5109 | #define POWERPC_BFDM_745 (bfd_mach_ppc_750) | |
5110 | #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
5111 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) | |
5112 | #define check_pow_745 check_pow_hid0 | |
5113 | ||
5114 | static void init_proc_745 (CPUPPCState *env) | |
5115 | { | |
5116 | gen_spr_ne_601(env); | |
5117 | gen_spr_7xx(env); | |
5118 | gen_spr_G2_755(env); | |
5119 | /* Time base */ | |
5120 | gen_tbl(env); | |
5121 | /* Thermal management */ | |
5122 | gen_spr_thrm(env); | |
5123 | /* Hardware implementation registers */ | |
5124 | /* XXX : not implemented */ | |
5125 | spr_register(env, SPR_HID0, "HID0", | |
5126 | SPR_NOACCESS, SPR_NOACCESS, | |
5127 | &spr_read_generic, &spr_write_generic, | |
5128 | 0x00000000); | |
5129 | /* XXX : not implemented */ | |
5130 | spr_register(env, SPR_HID1, "HID1", | |
5131 | SPR_NOACCESS, SPR_NOACCESS, | |
5132 | &spr_read_generic, &spr_write_generic, | |
5133 | 0x00000000); | |
5134 | /* XXX : not implemented */ | |
5135 | spr_register(env, SPR_HID2, "HID2", | |
5136 | SPR_NOACCESS, SPR_NOACCESS, | |
5137 | &spr_read_generic, &spr_write_generic, | |
5138 | 0x00000000); | |
5139 | /* Memory management */ | |
5140 | gen_low_BATs(env); | |
5141 | gen_high_BATs(env); | |
5142 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
5143 | init_excp_7x5(env); | |
5144 | env->dcache_line_size = 32; | |
5145 | env->icache_line_size = 32; | |
5146 | /* Allocate hardware IRQ controller */ | |
5147 | ppc6xx_irq_init(env); | |
5148 | } | |
5149 | ||
5150 | /* PowerPC 755 */ | |
5151 | #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
5152 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5153 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \ | |
082c6681 JM |
5154 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ |
5155 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5156 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \ | |
5157 | PPC_SEGMENT | PPC_EXTERN) | |
bd928eba JM |
5158 | #define POWERPC_MSRM_755 (0x000000000005FF77ULL) |
5159 | #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx) | |
5160 | #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5) | |
5161 | #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx) | |
5162 | #define POWERPC_BFDM_755 (bfd_mach_ppc_750) | |
5163 | #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ | |
4018bae9 | 5164 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
bd928eba | 5165 | #define check_pow_755 check_pow_hid0 |
a750fc0b | 5166 | |
bd928eba | 5167 | static void init_proc_755 (CPUPPCState *env) |
a750fc0b JM |
5168 | { |
5169 | gen_spr_ne_601(env); | |
bd928eba | 5170 | gen_spr_7xx(env); |
a750fc0b JM |
5171 | gen_spr_G2_755(env); |
5172 | /* Time base */ | |
5173 | gen_tbl(env); | |
5174 | /* L2 cache control */ | |
5175 | /* XXX : not implemented */ | |
bd928eba | 5176 | spr_register(env, SPR_L2CR, "L2CR", |
a750fc0b JM |
5177 | SPR_NOACCESS, SPR_NOACCESS, |
5178 | &spr_read_generic, &spr_write_generic, | |
5179 | 0x00000000); | |
5180 | /* XXX : not implemented */ | |
5181 | spr_register(env, SPR_L2PMCR, "L2PMCR", | |
5182 | SPR_NOACCESS, SPR_NOACCESS, | |
5183 | &spr_read_generic, &spr_write_generic, | |
5184 | 0x00000000); | |
bd928eba JM |
5185 | /* Thermal management */ |
5186 | gen_spr_thrm(env); | |
a750fc0b JM |
5187 | /* Hardware implementation registers */ |
5188 | /* XXX : not implemented */ | |
5189 | spr_register(env, SPR_HID0, "HID0", | |
5190 | SPR_NOACCESS, SPR_NOACCESS, | |
5191 | &spr_read_generic, &spr_write_generic, | |
5192 | 0x00000000); | |
5193 | /* XXX : not implemented */ | |
5194 | spr_register(env, SPR_HID1, "HID1", | |
5195 | SPR_NOACCESS, SPR_NOACCESS, | |
5196 | &spr_read_generic, &spr_write_generic, | |
5197 | 0x00000000); | |
5198 | /* XXX : not implemented */ | |
5199 | spr_register(env, SPR_HID2, "HID2", | |
5200 | SPR_NOACCESS, SPR_NOACCESS, | |
5201 | &spr_read_generic, &spr_write_generic, | |
5202 | 0x00000000); | |
5203 | /* Memory management */ | |
5204 | gen_low_BATs(env); | |
5205 | gen_high_BATs(env); | |
5206 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
7a3a6927 | 5207 | init_excp_7x5(env); |
d63001d1 JM |
5208 | env->dcache_line_size = 32; |
5209 | env->icache_line_size = 32; | |
a750fc0b JM |
5210 | /* Allocate hardware IRQ controller */ |
5211 | ppc6xx_irq_init(env); | |
5212 | } | |
5213 | ||
5214 | /* PowerPC 7400 (aka G4) */ | |
082c6681 JM |
5215 | #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5216 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5217 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5218 | PPC_FLOAT_STFIWX | \ | |
5219 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5220 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5221 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5222 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5223 | PPC_MEM_TLBIA | \ | |
5224 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b JM |
5225 | PPC_ALTIVEC) |
5226 | #define POWERPC_MSRM_7400 (0x000000000205FF77ULL) | |
5227 | #define POWERPC_MMU_7400 (POWERPC_MMU_32B) | |
5228 | #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx) | |
5229 | #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 5230 | #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400) |
25ba3a68 | 5231 | #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5232 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5233 | POWERPC_FLAG_BUS_CLK) | |
4e777442 | 5234 | #define check_pow_7400 check_pow_hid0_74xx |
a750fc0b JM |
5235 | |
5236 | static void init_proc_7400 (CPUPPCState *env) | |
5237 | { | |
5238 | gen_spr_ne_601(env); | |
5239 | gen_spr_7xx(env); | |
5240 | /* Time base */ | |
5241 | gen_tbl(env); | |
5242 | /* 74xx specific SPR */ | |
5243 | gen_spr_74xx(env); | |
4e777442 JM |
5244 | /* XXX : not implemented */ |
5245 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5246 | &spr_read_ureg, SPR_NOACCESS, | |
5247 | &spr_read_ureg, SPR_NOACCESS, | |
5248 | 0x00000000); | |
5249 | /* XXX: this seems not implemented on all revisions. */ | |
5250 | /* XXX : not implemented */ | |
5251 | spr_register(env, SPR_MSSCR1, "MSSCR1", | |
5252 | SPR_NOACCESS, SPR_NOACCESS, | |
5253 | &spr_read_generic, &spr_write_generic, | |
5254 | 0x00000000); | |
a750fc0b JM |
5255 | /* Thermal management */ |
5256 | gen_spr_thrm(env); | |
5257 | /* Memory management */ | |
5258 | gen_low_BATs(env); | |
e1833e1f | 5259 | init_excp_7400(env); |
d63001d1 JM |
5260 | env->dcache_line_size = 32; |
5261 | env->icache_line_size = 32; | |
a750fc0b JM |
5262 | /* Allocate hardware IRQ controller */ |
5263 | ppc6xx_irq_init(env); | |
5264 | } | |
5265 | ||
5266 | /* PowerPC 7410 (aka G4) */ | |
082c6681 JM |
5267 | #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5268 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5269 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5270 | PPC_FLOAT_STFIWX | \ | |
5271 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5272 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5273 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5274 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5275 | PPC_MEM_TLBIA | \ | |
5276 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b JM |
5277 | PPC_ALTIVEC) |
5278 | #define POWERPC_MSRM_7410 (0x000000000205FF77ULL) | |
5279 | #define POWERPC_MMU_7410 (POWERPC_MMU_32B) | |
5280 | #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx) | |
5281 | #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 5282 | #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400) |
25ba3a68 | 5283 | #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5284 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5285 | POWERPC_FLAG_BUS_CLK) | |
4e777442 | 5286 | #define check_pow_7410 check_pow_hid0_74xx |
a750fc0b JM |
5287 | |
5288 | static void init_proc_7410 (CPUPPCState *env) | |
5289 | { | |
5290 | gen_spr_ne_601(env); | |
5291 | gen_spr_7xx(env); | |
5292 | /* Time base */ | |
5293 | gen_tbl(env); | |
5294 | /* 74xx specific SPR */ | |
5295 | gen_spr_74xx(env); | |
4e777442 JM |
5296 | /* XXX : not implemented */ |
5297 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5298 | &spr_read_ureg, SPR_NOACCESS, | |
5299 | &spr_read_ureg, SPR_NOACCESS, | |
5300 | 0x00000000); | |
a750fc0b JM |
5301 | /* Thermal management */ |
5302 | gen_spr_thrm(env); | |
5303 | /* L2PMCR */ | |
5304 | /* XXX : not implemented */ | |
5305 | spr_register(env, SPR_L2PMCR, "L2PMCR", | |
5306 | SPR_NOACCESS, SPR_NOACCESS, | |
5307 | &spr_read_generic, &spr_write_generic, | |
5308 | 0x00000000); | |
5309 | /* LDSTDB */ | |
5310 | /* XXX : not implemented */ | |
5311 | spr_register(env, SPR_LDSTDB, "LDSTDB", | |
5312 | SPR_NOACCESS, SPR_NOACCESS, | |
5313 | &spr_read_generic, &spr_write_generic, | |
5314 | 0x00000000); | |
5315 | /* Memory management */ | |
5316 | gen_low_BATs(env); | |
e1833e1f | 5317 | init_excp_7400(env); |
d63001d1 JM |
5318 | env->dcache_line_size = 32; |
5319 | env->icache_line_size = 32; | |
a750fc0b JM |
5320 | /* Allocate hardware IRQ controller */ |
5321 | ppc6xx_irq_init(env); | |
5322 | } | |
5323 | ||
5324 | /* PowerPC 7440 (aka G4) */ | |
082c6681 JM |
5325 | #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5326 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5327 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5328 | PPC_FLOAT_STFIWX | \ | |
5329 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5330 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5331 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5332 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5333 | PPC_MEM_TLBIA | PPC_74xx_TLB | \ | |
5334 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b JM |
5335 | PPC_ALTIVEC) |
5336 | #define POWERPC_MSRM_7440 (0x000000000205FF77ULL) | |
5337 | #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx) | |
5338 | #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx) | |
5339 | #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 5340 | #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400) |
25ba3a68 | 5341 | #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5342 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5343 | POWERPC_FLAG_BUS_CLK) | |
4e777442 | 5344 | #define check_pow_7440 check_pow_hid0_74xx |
a750fc0b | 5345 | |
578bb252 | 5346 | __attribute__ (( unused )) |
a750fc0b JM |
5347 | static void init_proc_7440 (CPUPPCState *env) |
5348 | { | |
5349 | gen_spr_ne_601(env); | |
5350 | gen_spr_7xx(env); | |
5351 | /* Time base */ | |
5352 | gen_tbl(env); | |
5353 | /* 74xx specific SPR */ | |
5354 | gen_spr_74xx(env); | |
4e777442 JM |
5355 | /* XXX : not implemented */ |
5356 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5357 | &spr_read_ureg, SPR_NOACCESS, | |
5358 | &spr_read_ureg, SPR_NOACCESS, | |
5359 | 0x00000000); | |
a750fc0b JM |
5360 | /* LDSTCR */ |
5361 | /* XXX : not implemented */ | |
5362 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
5363 | SPR_NOACCESS, SPR_NOACCESS, | |
5364 | &spr_read_generic, &spr_write_generic, | |
5365 | 0x00000000); | |
5366 | /* ICTRL */ | |
5367 | /* XXX : not implemented */ | |
5368 | spr_register(env, SPR_ICTRL, "ICTRL", | |
5369 | SPR_NOACCESS, SPR_NOACCESS, | |
5370 | &spr_read_generic, &spr_write_generic, | |
5371 | 0x00000000); | |
5372 | /* MSSSR0 */ | |
578bb252 | 5373 | /* XXX : not implemented */ |
a750fc0b JM |
5374 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
5375 | SPR_NOACCESS, SPR_NOACCESS, | |
5376 | &spr_read_generic, &spr_write_generic, | |
5377 | 0x00000000); | |
5378 | /* PMC */ | |
5379 | /* XXX : not implemented */ | |
5380 | spr_register(env, SPR_PMC5, "PMC5", | |
5381 | SPR_NOACCESS, SPR_NOACCESS, | |
5382 | &spr_read_generic, &spr_write_generic, | |
5383 | 0x00000000); | |
578bb252 | 5384 | /* XXX : not implemented */ |
a750fc0b JM |
5385 | spr_register(env, SPR_UPMC5, "UPMC5", |
5386 | &spr_read_ureg, SPR_NOACCESS, | |
5387 | &spr_read_ureg, SPR_NOACCESS, | |
5388 | 0x00000000); | |
578bb252 | 5389 | /* XXX : not implemented */ |
a750fc0b JM |
5390 | spr_register(env, SPR_PMC6, "PMC6", |
5391 | SPR_NOACCESS, SPR_NOACCESS, | |
5392 | &spr_read_generic, &spr_write_generic, | |
5393 | 0x00000000); | |
578bb252 | 5394 | /* XXX : not implemented */ |
a750fc0b JM |
5395 | spr_register(env, SPR_UPMC6, "UPMC6", |
5396 | &spr_read_ureg, SPR_NOACCESS, | |
5397 | &spr_read_ureg, SPR_NOACCESS, | |
5398 | 0x00000000); | |
5399 | /* Memory management */ | |
5400 | gen_low_BATs(env); | |
578bb252 | 5401 | gen_74xx_soft_tlb(env, 128, 2); |
1c27f8fb | 5402 | init_excp_7450(env); |
d63001d1 JM |
5403 | env->dcache_line_size = 32; |
5404 | env->icache_line_size = 32; | |
a750fc0b JM |
5405 | /* Allocate hardware IRQ controller */ |
5406 | ppc6xx_irq_init(env); | |
5407 | } | |
a750fc0b JM |
5408 | |
5409 | /* PowerPC 7450 (aka G4) */ | |
082c6681 JM |
5410 | #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5411 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5412 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5413 | PPC_FLOAT_STFIWX | \ | |
5414 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5415 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5416 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5417 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5418 | PPC_MEM_TLBIA | PPC_74xx_TLB | \ | |
5419 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b JM |
5420 | PPC_ALTIVEC) |
5421 | #define POWERPC_MSRM_7450 (0x000000000205FF77ULL) | |
5422 | #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx) | |
5423 | #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx) | |
5424 | #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 5425 | #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400) |
25ba3a68 | 5426 | #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5427 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5428 | POWERPC_FLAG_BUS_CLK) | |
4e777442 | 5429 | #define check_pow_7450 check_pow_hid0_74xx |
a750fc0b | 5430 | |
578bb252 | 5431 | __attribute__ (( unused )) |
a750fc0b JM |
5432 | static void init_proc_7450 (CPUPPCState *env) |
5433 | { | |
5434 | gen_spr_ne_601(env); | |
5435 | gen_spr_7xx(env); | |
5436 | /* Time base */ | |
5437 | gen_tbl(env); | |
5438 | /* 74xx specific SPR */ | |
5439 | gen_spr_74xx(env); | |
5440 | /* Level 3 cache control */ | |
5441 | gen_l3_ctrl(env); | |
4e777442 JM |
5442 | /* L3ITCR1 */ |
5443 | /* XXX : not implemented */ | |
5444 | spr_register(env, SPR_L3ITCR1, "L3ITCR1", | |
5445 | SPR_NOACCESS, SPR_NOACCESS, | |
5446 | &spr_read_generic, &spr_write_generic, | |
5447 | 0x00000000); | |
5448 | /* L3ITCR2 */ | |
5449 | /* XXX : not implemented */ | |
5450 | spr_register(env, SPR_L3ITCR2, "L3ITCR2", | |
5451 | SPR_NOACCESS, SPR_NOACCESS, | |
5452 | &spr_read_generic, &spr_write_generic, | |
5453 | 0x00000000); | |
5454 | /* L3ITCR3 */ | |
5455 | /* XXX : not implemented */ | |
5456 | spr_register(env, SPR_L3ITCR3, "L3ITCR3", | |
5457 | SPR_NOACCESS, SPR_NOACCESS, | |
5458 | &spr_read_generic, &spr_write_generic, | |
5459 | 0x00000000); | |
5460 | /* L3OHCR */ | |
5461 | /* XXX : not implemented */ | |
5462 | spr_register(env, SPR_L3OHCR, "L3OHCR", | |
5463 | SPR_NOACCESS, SPR_NOACCESS, | |
5464 | &spr_read_generic, &spr_write_generic, | |
5465 | 0x00000000); | |
5466 | /* XXX : not implemented */ | |
5467 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5468 | &spr_read_ureg, SPR_NOACCESS, | |
5469 | &spr_read_ureg, SPR_NOACCESS, | |
5470 | 0x00000000); | |
a750fc0b JM |
5471 | /* LDSTCR */ |
5472 | /* XXX : not implemented */ | |
5473 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
5474 | SPR_NOACCESS, SPR_NOACCESS, | |
5475 | &spr_read_generic, &spr_write_generic, | |
5476 | 0x00000000); | |
5477 | /* ICTRL */ | |
5478 | /* XXX : not implemented */ | |
5479 | spr_register(env, SPR_ICTRL, "ICTRL", | |
5480 | SPR_NOACCESS, SPR_NOACCESS, | |
5481 | &spr_read_generic, &spr_write_generic, | |
5482 | 0x00000000); | |
5483 | /* MSSSR0 */ | |
578bb252 | 5484 | /* XXX : not implemented */ |
a750fc0b JM |
5485 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
5486 | SPR_NOACCESS, SPR_NOACCESS, | |
5487 | &spr_read_generic, &spr_write_generic, | |
5488 | 0x00000000); | |
5489 | /* PMC */ | |
5490 | /* XXX : not implemented */ | |
5491 | spr_register(env, SPR_PMC5, "PMC5", | |
5492 | SPR_NOACCESS, SPR_NOACCESS, | |
5493 | &spr_read_generic, &spr_write_generic, | |
5494 | 0x00000000); | |
578bb252 | 5495 | /* XXX : not implemented */ |
a750fc0b JM |
5496 | spr_register(env, SPR_UPMC5, "UPMC5", |
5497 | &spr_read_ureg, SPR_NOACCESS, | |
5498 | &spr_read_ureg, SPR_NOACCESS, | |
5499 | 0x00000000); | |
578bb252 | 5500 | /* XXX : not implemented */ |
a750fc0b JM |
5501 | spr_register(env, SPR_PMC6, "PMC6", |
5502 | SPR_NOACCESS, SPR_NOACCESS, | |
5503 | &spr_read_generic, &spr_write_generic, | |
5504 | 0x00000000); | |
578bb252 | 5505 | /* XXX : not implemented */ |
a750fc0b JM |
5506 | spr_register(env, SPR_UPMC6, "UPMC6", |
5507 | &spr_read_ureg, SPR_NOACCESS, | |
5508 | &spr_read_ureg, SPR_NOACCESS, | |
5509 | 0x00000000); | |
5510 | /* Memory management */ | |
5511 | gen_low_BATs(env); | |
578bb252 | 5512 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 5513 | init_excp_7450(env); |
d63001d1 JM |
5514 | env->dcache_line_size = 32; |
5515 | env->icache_line_size = 32; | |
a750fc0b JM |
5516 | /* Allocate hardware IRQ controller */ |
5517 | ppc6xx_irq_init(env); | |
5518 | } | |
a750fc0b JM |
5519 | |
5520 | /* PowerPC 7445 (aka G4) */ | |
082c6681 JM |
5521 | #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5522 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5523 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5524 | PPC_FLOAT_STFIWX | \ | |
5525 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5526 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5527 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5528 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5529 | PPC_MEM_TLBIA | PPC_74xx_TLB | \ | |
5530 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b JM |
5531 | PPC_ALTIVEC) |
5532 | #define POWERPC_MSRM_7445 (0x000000000205FF77ULL) | |
5533 | #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx) | |
5534 | #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx) | |
5535 | #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 5536 | #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400) |
25ba3a68 | 5537 | #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5538 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5539 | POWERPC_FLAG_BUS_CLK) | |
4e777442 | 5540 | #define check_pow_7445 check_pow_hid0_74xx |
a750fc0b | 5541 | |
578bb252 | 5542 | __attribute__ (( unused )) |
a750fc0b JM |
5543 | static void init_proc_7445 (CPUPPCState *env) |
5544 | { | |
5545 | gen_spr_ne_601(env); | |
5546 | gen_spr_7xx(env); | |
5547 | /* Time base */ | |
5548 | gen_tbl(env); | |
5549 | /* 74xx specific SPR */ | |
5550 | gen_spr_74xx(env); | |
5551 | /* LDSTCR */ | |
5552 | /* XXX : not implemented */ | |
5553 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
5554 | SPR_NOACCESS, SPR_NOACCESS, | |
5555 | &spr_read_generic, &spr_write_generic, | |
5556 | 0x00000000); | |
5557 | /* ICTRL */ | |
5558 | /* XXX : not implemented */ | |
5559 | spr_register(env, SPR_ICTRL, "ICTRL", | |
5560 | SPR_NOACCESS, SPR_NOACCESS, | |
5561 | &spr_read_generic, &spr_write_generic, | |
5562 | 0x00000000); | |
5563 | /* MSSSR0 */ | |
578bb252 | 5564 | /* XXX : not implemented */ |
a750fc0b JM |
5565 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
5566 | SPR_NOACCESS, SPR_NOACCESS, | |
5567 | &spr_read_generic, &spr_write_generic, | |
5568 | 0x00000000); | |
5569 | /* PMC */ | |
5570 | /* XXX : not implemented */ | |
5571 | spr_register(env, SPR_PMC5, "PMC5", | |
5572 | SPR_NOACCESS, SPR_NOACCESS, | |
5573 | &spr_read_generic, &spr_write_generic, | |
5574 | 0x00000000); | |
578bb252 | 5575 | /* XXX : not implemented */ |
a750fc0b JM |
5576 | spr_register(env, SPR_UPMC5, "UPMC5", |
5577 | &spr_read_ureg, SPR_NOACCESS, | |
5578 | &spr_read_ureg, SPR_NOACCESS, | |
5579 | 0x00000000); | |
578bb252 | 5580 | /* XXX : not implemented */ |
a750fc0b JM |
5581 | spr_register(env, SPR_PMC6, "PMC6", |
5582 | SPR_NOACCESS, SPR_NOACCESS, | |
5583 | &spr_read_generic, &spr_write_generic, | |
5584 | 0x00000000); | |
578bb252 | 5585 | /* XXX : not implemented */ |
a750fc0b JM |
5586 | spr_register(env, SPR_UPMC6, "UPMC6", |
5587 | &spr_read_ureg, SPR_NOACCESS, | |
5588 | &spr_read_ureg, SPR_NOACCESS, | |
5589 | 0x00000000); | |
5590 | /* SPRGs */ | |
5591 | spr_register(env, SPR_SPRG4, "SPRG4", | |
5592 | SPR_NOACCESS, SPR_NOACCESS, | |
5593 | &spr_read_generic, &spr_write_generic, | |
5594 | 0x00000000); | |
5595 | spr_register(env, SPR_USPRG4, "USPRG4", | |
5596 | &spr_read_ureg, SPR_NOACCESS, | |
5597 | &spr_read_ureg, SPR_NOACCESS, | |
5598 | 0x00000000); | |
5599 | spr_register(env, SPR_SPRG5, "SPRG5", | |
5600 | SPR_NOACCESS, SPR_NOACCESS, | |
5601 | &spr_read_generic, &spr_write_generic, | |
5602 | 0x00000000); | |
5603 | spr_register(env, SPR_USPRG5, "USPRG5", | |
5604 | &spr_read_ureg, SPR_NOACCESS, | |
5605 | &spr_read_ureg, SPR_NOACCESS, | |
5606 | 0x00000000); | |
5607 | spr_register(env, SPR_SPRG6, "SPRG6", | |
5608 | SPR_NOACCESS, SPR_NOACCESS, | |
5609 | &spr_read_generic, &spr_write_generic, | |
5610 | 0x00000000); | |
5611 | spr_register(env, SPR_USPRG6, "USPRG6", | |
5612 | &spr_read_ureg, SPR_NOACCESS, | |
5613 | &spr_read_ureg, SPR_NOACCESS, | |
5614 | 0x00000000); | |
5615 | spr_register(env, SPR_SPRG7, "SPRG7", | |
5616 | SPR_NOACCESS, SPR_NOACCESS, | |
5617 | &spr_read_generic, &spr_write_generic, | |
5618 | 0x00000000); | |
5619 | spr_register(env, SPR_USPRG7, "USPRG7", | |
5620 | &spr_read_ureg, SPR_NOACCESS, | |
5621 | &spr_read_ureg, SPR_NOACCESS, | |
5622 | 0x00000000); | |
5623 | /* Memory management */ | |
5624 | gen_low_BATs(env); | |
5625 | gen_high_BATs(env); | |
578bb252 | 5626 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 5627 | init_excp_7450(env); |
d63001d1 JM |
5628 | env->dcache_line_size = 32; |
5629 | env->icache_line_size = 32; | |
a750fc0b JM |
5630 | /* Allocate hardware IRQ controller */ |
5631 | ppc6xx_irq_init(env); | |
5632 | } | |
a750fc0b JM |
5633 | |
5634 | /* PowerPC 7455 (aka G4) */ | |
082c6681 JM |
5635 | #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5636 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5637 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5638 | PPC_FLOAT_STFIWX | \ | |
5639 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5640 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5641 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5642 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5643 | PPC_MEM_TLBIA | PPC_74xx_TLB | \ | |
5644 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b JM |
5645 | PPC_ALTIVEC) |
5646 | #define POWERPC_MSRM_7455 (0x000000000205FF77ULL) | |
5647 | #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx) | |
5648 | #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx) | |
5649 | #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx) | |
237c0af0 | 5650 | #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400) |
25ba3a68 | 5651 | #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5652 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5653 | POWERPC_FLAG_BUS_CLK) | |
4e777442 | 5654 | #define check_pow_7455 check_pow_hid0_74xx |
a750fc0b | 5655 | |
578bb252 | 5656 | __attribute__ (( unused )) |
a750fc0b JM |
5657 | static void init_proc_7455 (CPUPPCState *env) |
5658 | { | |
5659 | gen_spr_ne_601(env); | |
5660 | gen_spr_7xx(env); | |
5661 | /* Time base */ | |
5662 | gen_tbl(env); | |
5663 | /* 74xx specific SPR */ | |
5664 | gen_spr_74xx(env); | |
5665 | /* Level 3 cache control */ | |
5666 | gen_l3_ctrl(env); | |
5667 | /* LDSTCR */ | |
5668 | /* XXX : not implemented */ | |
5669 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
5670 | SPR_NOACCESS, SPR_NOACCESS, | |
5671 | &spr_read_generic, &spr_write_generic, | |
5672 | 0x00000000); | |
5673 | /* ICTRL */ | |
5674 | /* XXX : not implemented */ | |
5675 | spr_register(env, SPR_ICTRL, "ICTRL", | |
5676 | SPR_NOACCESS, SPR_NOACCESS, | |
5677 | &spr_read_generic, &spr_write_generic, | |
5678 | 0x00000000); | |
5679 | /* MSSSR0 */ | |
578bb252 | 5680 | /* XXX : not implemented */ |
a750fc0b JM |
5681 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
5682 | SPR_NOACCESS, SPR_NOACCESS, | |
5683 | &spr_read_generic, &spr_write_generic, | |
5684 | 0x00000000); | |
5685 | /* PMC */ | |
5686 | /* XXX : not implemented */ | |
5687 | spr_register(env, SPR_PMC5, "PMC5", | |
5688 | SPR_NOACCESS, SPR_NOACCESS, | |
5689 | &spr_read_generic, &spr_write_generic, | |
5690 | 0x00000000); | |
578bb252 | 5691 | /* XXX : not implemented */ |
a750fc0b JM |
5692 | spr_register(env, SPR_UPMC5, "UPMC5", |
5693 | &spr_read_ureg, SPR_NOACCESS, | |
5694 | &spr_read_ureg, SPR_NOACCESS, | |
5695 | 0x00000000); | |
578bb252 | 5696 | /* XXX : not implemented */ |
a750fc0b JM |
5697 | spr_register(env, SPR_PMC6, "PMC6", |
5698 | SPR_NOACCESS, SPR_NOACCESS, | |
5699 | &spr_read_generic, &spr_write_generic, | |
5700 | 0x00000000); | |
578bb252 | 5701 | /* XXX : not implemented */ |
a750fc0b JM |
5702 | spr_register(env, SPR_UPMC6, "UPMC6", |
5703 | &spr_read_ureg, SPR_NOACCESS, | |
5704 | &spr_read_ureg, SPR_NOACCESS, | |
5705 | 0x00000000); | |
5706 | /* SPRGs */ | |
5707 | spr_register(env, SPR_SPRG4, "SPRG4", | |
5708 | SPR_NOACCESS, SPR_NOACCESS, | |
5709 | &spr_read_generic, &spr_write_generic, | |
5710 | 0x00000000); | |
5711 | spr_register(env, SPR_USPRG4, "USPRG4", | |
5712 | &spr_read_ureg, SPR_NOACCESS, | |
5713 | &spr_read_ureg, SPR_NOACCESS, | |
5714 | 0x00000000); | |
5715 | spr_register(env, SPR_SPRG5, "SPRG5", | |
5716 | SPR_NOACCESS, SPR_NOACCESS, | |
5717 | &spr_read_generic, &spr_write_generic, | |
5718 | 0x00000000); | |
5719 | spr_register(env, SPR_USPRG5, "USPRG5", | |
5720 | &spr_read_ureg, SPR_NOACCESS, | |
5721 | &spr_read_ureg, SPR_NOACCESS, | |
5722 | 0x00000000); | |
5723 | spr_register(env, SPR_SPRG6, "SPRG6", | |
5724 | SPR_NOACCESS, SPR_NOACCESS, | |
5725 | &spr_read_generic, &spr_write_generic, | |
5726 | 0x00000000); | |
5727 | spr_register(env, SPR_USPRG6, "USPRG6", | |
5728 | &spr_read_ureg, SPR_NOACCESS, | |
5729 | &spr_read_ureg, SPR_NOACCESS, | |
5730 | 0x00000000); | |
5731 | spr_register(env, SPR_SPRG7, "SPRG7", | |
5732 | SPR_NOACCESS, SPR_NOACCESS, | |
5733 | &spr_read_generic, &spr_write_generic, | |
5734 | 0x00000000); | |
5735 | spr_register(env, SPR_USPRG7, "USPRG7", | |
5736 | &spr_read_ureg, SPR_NOACCESS, | |
5737 | &spr_read_ureg, SPR_NOACCESS, | |
5738 | 0x00000000); | |
5739 | /* Memory management */ | |
5740 | gen_low_BATs(env); | |
5741 | gen_high_BATs(env); | |
578bb252 | 5742 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 5743 | init_excp_7450(env); |
d63001d1 JM |
5744 | env->dcache_line_size = 32; |
5745 | env->icache_line_size = 32; | |
a750fc0b JM |
5746 | /* Allocate hardware IRQ controller */ |
5747 | ppc6xx_irq_init(env); | |
5748 | } | |
a750fc0b | 5749 | |
4e777442 JM |
5750 | /* PowerPC 7457 (aka G4) */ |
5751 | #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ | |
5752 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5753 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5754 | PPC_FLOAT_STFIWX | \ | |
5755 | PPC_CACHE | PPC_CACHE_ICBI | \ | |
5756 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \ | |
5757 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5758 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
5759 | PPC_MEM_TLBIA | PPC_74xx_TLB | \ | |
5760 | PPC_SEGMENT | PPC_EXTERN | \ | |
5761 | PPC_ALTIVEC) | |
5762 | #define POWERPC_MSRM_7457 (0x000000000205FF77ULL) | |
5763 | #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx) | |
5764 | #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx) | |
5765 | #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx) | |
5766 | #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400) | |
5767 | #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ | |
5768 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ | |
5769 | POWERPC_FLAG_BUS_CLK) | |
5770 | #define check_pow_7457 check_pow_hid0_74xx | |
5771 | ||
5772 | __attribute__ (( unused )) | |
5773 | static void init_proc_7457 (CPUPPCState *env) | |
5774 | { | |
5775 | gen_spr_ne_601(env); | |
5776 | gen_spr_7xx(env); | |
5777 | /* Time base */ | |
5778 | gen_tbl(env); | |
5779 | /* 74xx specific SPR */ | |
5780 | gen_spr_74xx(env); | |
5781 | /* Level 3 cache control */ | |
5782 | gen_l3_ctrl(env); | |
5783 | /* L3ITCR1 */ | |
5784 | /* XXX : not implemented */ | |
5785 | spr_register(env, SPR_L3ITCR1, "L3ITCR1", | |
5786 | SPR_NOACCESS, SPR_NOACCESS, | |
5787 | &spr_read_generic, &spr_write_generic, | |
5788 | 0x00000000); | |
5789 | /* L3ITCR2 */ | |
5790 | /* XXX : not implemented */ | |
5791 | spr_register(env, SPR_L3ITCR2, "L3ITCR2", | |
5792 | SPR_NOACCESS, SPR_NOACCESS, | |
5793 | &spr_read_generic, &spr_write_generic, | |
5794 | 0x00000000); | |
5795 | /* L3ITCR3 */ | |
5796 | /* XXX : not implemented */ | |
5797 | spr_register(env, SPR_L3ITCR3, "L3ITCR3", | |
5798 | SPR_NOACCESS, SPR_NOACCESS, | |
5799 | &spr_read_generic, &spr_write_generic, | |
5800 | 0x00000000); | |
5801 | /* L3OHCR */ | |
5802 | /* XXX : not implemented */ | |
5803 | spr_register(env, SPR_L3OHCR, "L3OHCR", | |
5804 | SPR_NOACCESS, SPR_NOACCESS, | |
5805 | &spr_read_generic, &spr_write_generic, | |
5806 | 0x00000000); | |
5807 | /* LDSTCR */ | |
5808 | /* XXX : not implemented */ | |
5809 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
5810 | SPR_NOACCESS, SPR_NOACCESS, | |
5811 | &spr_read_generic, &spr_write_generic, | |
5812 | 0x00000000); | |
5813 | /* ICTRL */ | |
5814 | /* XXX : not implemented */ | |
5815 | spr_register(env, SPR_ICTRL, "ICTRL", | |
5816 | SPR_NOACCESS, SPR_NOACCESS, | |
5817 | &spr_read_generic, &spr_write_generic, | |
5818 | 0x00000000); | |
5819 | /* MSSSR0 */ | |
5820 | /* XXX : not implemented */ | |
5821 | spr_register(env, SPR_MSSSR0, "MSSSR0", | |
5822 | SPR_NOACCESS, SPR_NOACCESS, | |
5823 | &spr_read_generic, &spr_write_generic, | |
5824 | 0x00000000); | |
5825 | /* PMC */ | |
5826 | /* XXX : not implemented */ | |
5827 | spr_register(env, SPR_PMC5, "PMC5", | |
5828 | SPR_NOACCESS, SPR_NOACCESS, | |
5829 | &spr_read_generic, &spr_write_generic, | |
5830 | 0x00000000); | |
5831 | /* XXX : not implemented */ | |
5832 | spr_register(env, SPR_UPMC5, "UPMC5", | |
5833 | &spr_read_ureg, SPR_NOACCESS, | |
5834 | &spr_read_ureg, SPR_NOACCESS, | |
5835 | 0x00000000); | |
5836 | /* XXX : not implemented */ | |
5837 | spr_register(env, SPR_PMC6, "PMC6", | |
5838 | SPR_NOACCESS, SPR_NOACCESS, | |
5839 | &spr_read_generic, &spr_write_generic, | |
5840 | 0x00000000); | |
5841 | /* XXX : not implemented */ | |
5842 | spr_register(env, SPR_UPMC6, "UPMC6", | |
5843 | &spr_read_ureg, SPR_NOACCESS, | |
5844 | &spr_read_ureg, SPR_NOACCESS, | |
5845 | 0x00000000); | |
5846 | /* SPRGs */ | |
5847 | spr_register(env, SPR_SPRG4, "SPRG4", | |
5848 | SPR_NOACCESS, SPR_NOACCESS, | |
5849 | &spr_read_generic, &spr_write_generic, | |
5850 | 0x00000000); | |
5851 | spr_register(env, SPR_USPRG4, "USPRG4", | |
5852 | &spr_read_ureg, SPR_NOACCESS, | |
5853 | &spr_read_ureg, SPR_NOACCESS, | |
5854 | 0x00000000); | |
5855 | spr_register(env, SPR_SPRG5, "SPRG5", | |
5856 | SPR_NOACCESS, SPR_NOACCESS, | |
5857 | &spr_read_generic, &spr_write_generic, | |
5858 | 0x00000000); | |
5859 | spr_register(env, SPR_USPRG5, "USPRG5", | |
5860 | &spr_read_ureg, SPR_NOACCESS, | |
5861 | &spr_read_ureg, SPR_NOACCESS, | |
5862 | 0x00000000); | |
5863 | spr_register(env, SPR_SPRG6, "SPRG6", | |
5864 | SPR_NOACCESS, SPR_NOACCESS, | |
5865 | &spr_read_generic, &spr_write_generic, | |
5866 | 0x00000000); | |
5867 | spr_register(env, SPR_USPRG6, "USPRG6", | |
5868 | &spr_read_ureg, SPR_NOACCESS, | |
5869 | &spr_read_ureg, SPR_NOACCESS, | |
5870 | 0x00000000); | |
5871 | spr_register(env, SPR_SPRG7, "SPRG7", | |
5872 | SPR_NOACCESS, SPR_NOACCESS, | |
5873 | &spr_read_generic, &spr_write_generic, | |
5874 | 0x00000000); | |
5875 | spr_register(env, SPR_USPRG7, "USPRG7", | |
5876 | &spr_read_ureg, SPR_NOACCESS, | |
5877 | &spr_read_ureg, SPR_NOACCESS, | |
5878 | 0x00000000); | |
5879 | /* Memory management */ | |
5880 | gen_low_BATs(env); | |
5881 | gen_high_BATs(env); | |
5882 | gen_74xx_soft_tlb(env, 128, 2); | |
5883 | init_excp_7450(env); | |
5884 | env->dcache_line_size = 32; | |
5885 | env->icache_line_size = 32; | |
5886 | /* Allocate hardware IRQ controller */ | |
5887 | ppc6xx_irq_init(env); | |
5888 | } | |
5889 | ||
a750fc0b JM |
5890 | #if defined (TARGET_PPC64) |
5891 | /* PowerPC 970 */ | |
082c6681 JM |
5892 | #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5893 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5894 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5895 | PPC_FLOAT_STFIWX | \ | |
5896 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ | |
5897 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5898 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
a750fc0b | 5899 | PPC_64B | PPC_ALTIVEC | \ |
12de9a39 | 5900 | PPC_SEGMENT_64B | PPC_SLBI) |
a750fc0b | 5901 | #define POWERPC_MSRM_970 (0x900000000204FF36ULL) |
12de9a39 | 5902 | #define POWERPC_MMU_970 (POWERPC_MMU_64B) |
a750fc0b JM |
5903 | //#define POWERPC_EXCP_970 (POWERPC_EXCP_970) |
5904 | #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970) | |
237c0af0 | 5905 | #define POWERPC_BFDM_970 (bfd_mach_ppc64) |
25ba3a68 | 5906 | #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
5907 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
5908 | POWERPC_FLAG_BUS_CLK) | |
a750fc0b | 5909 | |
417bf010 JM |
5910 | #if defined(CONFIG_USER_ONLY) |
5911 | #define POWERPC970_HID5_INIT 0x00000080 | |
5912 | #else | |
5913 | #define POWERPC970_HID5_INIT 0x00000000 | |
5914 | #endif | |
5915 | ||
2f462816 JM |
5916 | static int check_pow_970 (CPUPPCState *env) |
5917 | { | |
5918 | if (env->spr[SPR_HID0] & 0x00600000) | |
5919 | return 1; | |
5920 | ||
5921 | return 0; | |
5922 | } | |
5923 | ||
a750fc0b JM |
5924 | static void init_proc_970 (CPUPPCState *env) |
5925 | { | |
5926 | gen_spr_ne_601(env); | |
5927 | gen_spr_7xx(env); | |
5928 | /* Time base */ | |
5929 | gen_tbl(env); | |
5930 | /* Hardware implementation registers */ | |
5931 | /* XXX : not implemented */ | |
5932 | spr_register(env, SPR_HID0, "HID0", | |
5933 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 5934 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 5935 | 0x60000000); |
a750fc0b JM |
5936 | /* XXX : not implemented */ |
5937 | spr_register(env, SPR_HID1, "HID1", | |
5938 | SPR_NOACCESS, SPR_NOACCESS, | |
5939 | &spr_read_generic, &spr_write_generic, | |
5940 | 0x00000000); | |
5941 | /* XXX : not implemented */ | |
bd928eba | 5942 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
5943 | SPR_NOACCESS, SPR_NOACCESS, |
5944 | &spr_read_generic, &spr_write_generic, | |
5945 | 0x00000000); | |
e57448f1 JM |
5946 | /* XXX : not implemented */ |
5947 | spr_register(env, SPR_970_HID5, "HID5", | |
5948 | SPR_NOACCESS, SPR_NOACCESS, | |
5949 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 5950 | POWERPC970_HID5_INIT); |
bd928eba JM |
5951 | /* XXX : not implemented */ |
5952 | spr_register(env, SPR_L2CR, "L2CR", | |
5953 | SPR_NOACCESS, SPR_NOACCESS, | |
5954 | &spr_read_generic, &spr_write_generic, | |
5955 | 0x00000000); | |
a750fc0b JM |
5956 | /* Memory management */ |
5957 | /* XXX: not correct */ | |
5958 | gen_low_BATs(env); | |
12de9a39 JM |
5959 | /* XXX : not implemented */ |
5960 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
5961 | SPR_NOACCESS, SPR_NOACCESS, | |
5962 | &spr_read_generic, SPR_NOACCESS, | |
5963 | 0x00000000); /* TOFIX */ | |
5964 | /* XXX : not implemented */ | |
5965 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
5966 | SPR_NOACCESS, SPR_NOACCESS, | |
5967 | &spr_read_generic, &spr_write_generic, | |
5968 | 0x00000000); /* TOFIX */ | |
5969 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
5970 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
5971 | &spr_read_hior, &spr_write_hior, |
5972 | 0x00000000); | |
f2e63a42 | 5973 | #if !defined(CONFIG_USER_ONLY) |
12de9a39 | 5974 | env->slb_nr = 32; |
f2e63a42 | 5975 | #endif |
e1833e1f | 5976 | init_excp_970(env); |
d63001d1 JM |
5977 | env->dcache_line_size = 128; |
5978 | env->icache_line_size = 128; | |
a750fc0b JM |
5979 | /* Allocate hardware IRQ controller */ |
5980 | ppc970_irq_init(env); | |
cf8358c8 AJ |
5981 | /* Can't find information on what this should be on reset. This |
5982 | * value is the one used by 74xx processors. */ | |
5983 | vscr_init(env, 0x00010000); | |
a750fc0b | 5984 | } |
a750fc0b JM |
5985 | |
5986 | /* PowerPC 970FX (aka G5) */ | |
082c6681 JM |
5987 | #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
5988 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
5989 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
5990 | PPC_FLOAT_STFIWX | \ | |
5991 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ | |
5992 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
5993 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
a750fc0b | 5994 | PPC_64B | PPC_ALTIVEC | \ |
12de9a39 | 5995 | PPC_SEGMENT_64B | PPC_SLBI) |
a750fc0b | 5996 | #define POWERPC_MSRM_970FX (0x800000000204FF36ULL) |
12de9a39 | 5997 | #define POWERPC_MMU_970FX (POWERPC_MMU_64B) |
a750fc0b JM |
5998 | #define POWERPC_EXCP_970FX (POWERPC_EXCP_970) |
5999 | #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970) | |
237c0af0 | 6000 | #define POWERPC_BFDM_970FX (bfd_mach_ppc64) |
25ba3a68 | 6001 | #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
6002 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6003 | POWERPC_FLAG_BUS_CLK) | |
a750fc0b | 6004 | |
2f462816 JM |
6005 | static int check_pow_970FX (CPUPPCState *env) |
6006 | { | |
6007 | if (env->spr[SPR_HID0] & 0x00600000) | |
6008 | return 1; | |
6009 | ||
6010 | return 0; | |
6011 | } | |
6012 | ||
a750fc0b JM |
6013 | static void init_proc_970FX (CPUPPCState *env) |
6014 | { | |
6015 | gen_spr_ne_601(env); | |
6016 | gen_spr_7xx(env); | |
6017 | /* Time base */ | |
6018 | gen_tbl(env); | |
6019 | /* Hardware implementation registers */ | |
6020 | /* XXX : not implemented */ | |
6021 | spr_register(env, SPR_HID0, "HID0", | |
6022 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 6023 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 6024 | 0x60000000); |
a750fc0b JM |
6025 | /* XXX : not implemented */ |
6026 | spr_register(env, SPR_HID1, "HID1", | |
6027 | SPR_NOACCESS, SPR_NOACCESS, | |
6028 | &spr_read_generic, &spr_write_generic, | |
6029 | 0x00000000); | |
6030 | /* XXX : not implemented */ | |
bd928eba | 6031 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
6032 | SPR_NOACCESS, SPR_NOACCESS, |
6033 | &spr_read_generic, &spr_write_generic, | |
6034 | 0x00000000); | |
d63001d1 JM |
6035 | /* XXX : not implemented */ |
6036 | spr_register(env, SPR_970_HID5, "HID5", | |
6037 | SPR_NOACCESS, SPR_NOACCESS, | |
6038 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 6039 | POWERPC970_HID5_INIT); |
bd928eba JM |
6040 | /* XXX : not implemented */ |
6041 | spr_register(env, SPR_L2CR, "L2CR", | |
6042 | SPR_NOACCESS, SPR_NOACCESS, | |
6043 | &spr_read_generic, &spr_write_generic, | |
6044 | 0x00000000); | |
a750fc0b JM |
6045 | /* Memory management */ |
6046 | /* XXX: not correct */ | |
6047 | gen_low_BATs(env); | |
12de9a39 JM |
6048 | /* XXX : not implemented */ |
6049 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6050 | SPR_NOACCESS, SPR_NOACCESS, | |
6051 | &spr_read_generic, SPR_NOACCESS, | |
6052 | 0x00000000); /* TOFIX */ | |
6053 | /* XXX : not implemented */ | |
6054 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6055 | SPR_NOACCESS, SPR_NOACCESS, | |
6056 | &spr_read_generic, &spr_write_generic, | |
6057 | 0x00000000); /* TOFIX */ | |
6058 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6059 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6060 | &spr_read_hior, &spr_write_hior, |
6061 | 0x00000000); | |
4e98d8cf BS |
6062 | spr_register(env, SPR_CTRL, "SPR_CTRL", |
6063 | SPR_NOACCESS, SPR_NOACCESS, | |
6064 | &spr_read_generic, &spr_write_generic, | |
6065 | 0x00000000); | |
6066 | spr_register(env, SPR_UCTRL, "SPR_UCTRL", | |
6067 | SPR_NOACCESS, SPR_NOACCESS, | |
6068 | &spr_read_generic, &spr_write_generic, | |
6069 | 0x00000000); | |
6070 | spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", | |
6071 | &spr_read_generic, &spr_write_generic, | |
6072 | &spr_read_generic, &spr_write_generic, | |
6073 | 0x00000000); | |
f2e63a42 | 6074 | #if !defined(CONFIG_USER_ONLY) |
8eee0af9 | 6075 | env->slb_nr = 64; |
f2e63a42 | 6076 | #endif |
e1833e1f | 6077 | init_excp_970(env); |
d63001d1 JM |
6078 | env->dcache_line_size = 128; |
6079 | env->icache_line_size = 128; | |
a750fc0b JM |
6080 | /* Allocate hardware IRQ controller */ |
6081 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6082 | /* Can't find information on what this should be on reset. This |
6083 | * value is the one used by 74xx processors. */ | |
6084 | vscr_init(env, 0x00010000); | |
a750fc0b | 6085 | } |
a750fc0b JM |
6086 | |
6087 | /* PowerPC 970 GX */ | |
082c6681 JM |
6088 | #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
6089 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
6090 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
6091 | PPC_FLOAT_STFIWX | \ | |
6092 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ | |
6093 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
6094 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
a750fc0b | 6095 | PPC_64B | PPC_ALTIVEC | \ |
12de9a39 | 6096 | PPC_SEGMENT_64B | PPC_SLBI) |
a750fc0b | 6097 | #define POWERPC_MSRM_970GX (0x800000000204FF36ULL) |
12de9a39 | 6098 | #define POWERPC_MMU_970GX (POWERPC_MMU_64B) |
a750fc0b JM |
6099 | #define POWERPC_EXCP_970GX (POWERPC_EXCP_970) |
6100 | #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970) | |
237c0af0 | 6101 | #define POWERPC_BFDM_970GX (bfd_mach_ppc64) |
25ba3a68 | 6102 | #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ |
4018bae9 JM |
6103 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6104 | POWERPC_FLAG_BUS_CLK) | |
a750fc0b | 6105 | |
2f462816 JM |
6106 | static int check_pow_970GX (CPUPPCState *env) |
6107 | { | |
6108 | if (env->spr[SPR_HID0] & 0x00600000) | |
6109 | return 1; | |
6110 | ||
6111 | return 0; | |
6112 | } | |
6113 | ||
a750fc0b JM |
6114 | static void init_proc_970GX (CPUPPCState *env) |
6115 | { | |
6116 | gen_spr_ne_601(env); | |
6117 | gen_spr_7xx(env); | |
6118 | /* Time base */ | |
6119 | gen_tbl(env); | |
6120 | /* Hardware implementation registers */ | |
6121 | /* XXX : not implemented */ | |
6122 | spr_register(env, SPR_HID0, "HID0", | |
6123 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 6124 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 6125 | 0x60000000); |
a750fc0b JM |
6126 | /* XXX : not implemented */ |
6127 | spr_register(env, SPR_HID1, "HID1", | |
6128 | SPR_NOACCESS, SPR_NOACCESS, | |
6129 | &spr_read_generic, &spr_write_generic, | |
6130 | 0x00000000); | |
6131 | /* XXX : not implemented */ | |
bd928eba | 6132 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
6133 | SPR_NOACCESS, SPR_NOACCESS, |
6134 | &spr_read_generic, &spr_write_generic, | |
6135 | 0x00000000); | |
d63001d1 JM |
6136 | /* XXX : not implemented */ |
6137 | spr_register(env, SPR_970_HID5, "HID5", | |
6138 | SPR_NOACCESS, SPR_NOACCESS, | |
6139 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 6140 | POWERPC970_HID5_INIT); |
bd928eba JM |
6141 | /* XXX : not implemented */ |
6142 | spr_register(env, SPR_L2CR, "L2CR", | |
6143 | SPR_NOACCESS, SPR_NOACCESS, | |
6144 | &spr_read_generic, &spr_write_generic, | |
6145 | 0x00000000); | |
a750fc0b JM |
6146 | /* Memory management */ |
6147 | /* XXX: not correct */ | |
6148 | gen_low_BATs(env); | |
12de9a39 JM |
6149 | /* XXX : not implemented */ |
6150 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6151 | SPR_NOACCESS, SPR_NOACCESS, | |
6152 | &spr_read_generic, SPR_NOACCESS, | |
6153 | 0x00000000); /* TOFIX */ | |
6154 | /* XXX : not implemented */ | |
6155 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6156 | SPR_NOACCESS, SPR_NOACCESS, | |
6157 | &spr_read_generic, &spr_write_generic, | |
6158 | 0x00000000); /* TOFIX */ | |
6159 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6160 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6161 | &spr_read_hior, &spr_write_hior, |
6162 | 0x00000000); | |
f2e63a42 | 6163 | #if !defined(CONFIG_USER_ONLY) |
12de9a39 | 6164 | env->slb_nr = 32; |
f2e63a42 | 6165 | #endif |
e1833e1f | 6166 | init_excp_970(env); |
d63001d1 JM |
6167 | env->dcache_line_size = 128; |
6168 | env->icache_line_size = 128; | |
a750fc0b JM |
6169 | /* Allocate hardware IRQ controller */ |
6170 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6171 | /* Can't find information on what this should be on reset. This |
6172 | * value is the one used by 74xx processors. */ | |
6173 | vscr_init(env, 0x00010000); | |
a750fc0b | 6174 | } |
a750fc0b | 6175 | |
2f462816 | 6176 | /* PowerPC 970 MP */ |
082c6681 JM |
6177 | #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
6178 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
6179 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
6180 | PPC_FLOAT_STFIWX | \ | |
6181 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ | |
6182 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
6183 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
2f462816 JM |
6184 | PPC_64B | PPC_ALTIVEC | \ |
6185 | PPC_SEGMENT_64B | PPC_SLBI) | |
6186 | #define POWERPC_MSRM_970MP (0x900000000204FF36ULL) | |
6187 | #define POWERPC_MMU_970MP (POWERPC_MMU_64B) | |
6188 | #define POWERPC_EXCP_970MP (POWERPC_EXCP_970) | |
6189 | #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970) | |
6190 | #define POWERPC_BFDM_970MP (bfd_mach_ppc64) | |
6191 | #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \ | |
4018bae9 JM |
6192 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \ |
6193 | POWERPC_FLAG_BUS_CLK) | |
2f462816 JM |
6194 | |
6195 | static int check_pow_970MP (CPUPPCState *env) | |
6196 | { | |
6197 | if (env->spr[SPR_HID0] & 0x01C00000) | |
6198 | return 1; | |
6199 | ||
6200 | return 0; | |
6201 | } | |
6202 | ||
6203 | static void init_proc_970MP (CPUPPCState *env) | |
6204 | { | |
6205 | gen_spr_ne_601(env); | |
6206 | gen_spr_7xx(env); | |
6207 | /* Time base */ | |
6208 | gen_tbl(env); | |
6209 | /* Hardware implementation registers */ | |
6210 | /* XXX : not implemented */ | |
6211 | spr_register(env, SPR_HID0, "HID0", | |
6212 | SPR_NOACCESS, SPR_NOACCESS, | |
6213 | &spr_read_generic, &spr_write_clear, | |
6214 | 0x60000000); | |
6215 | /* XXX : not implemented */ | |
6216 | spr_register(env, SPR_HID1, "HID1", | |
6217 | SPR_NOACCESS, SPR_NOACCESS, | |
6218 | &spr_read_generic, &spr_write_generic, | |
6219 | 0x00000000); | |
6220 | /* XXX : not implemented */ | |
bd928eba | 6221 | spr_register(env, SPR_750FX_HID2, "HID2", |
2f462816 JM |
6222 | SPR_NOACCESS, SPR_NOACCESS, |
6223 | &spr_read_generic, &spr_write_generic, | |
6224 | 0x00000000); | |
6225 | /* XXX : not implemented */ | |
6226 | spr_register(env, SPR_970_HID5, "HID5", | |
6227 | SPR_NOACCESS, SPR_NOACCESS, | |
6228 | &spr_read_generic, &spr_write_generic, | |
6229 | POWERPC970_HID5_INIT); | |
bd928eba JM |
6230 | /* XXX : not implemented */ |
6231 | spr_register(env, SPR_L2CR, "L2CR", | |
6232 | SPR_NOACCESS, SPR_NOACCESS, | |
6233 | &spr_read_generic, &spr_write_generic, | |
6234 | 0x00000000); | |
2f462816 JM |
6235 | /* Memory management */ |
6236 | /* XXX: not correct */ | |
6237 | gen_low_BATs(env); | |
6238 | /* XXX : not implemented */ | |
6239 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6240 | SPR_NOACCESS, SPR_NOACCESS, | |
6241 | &spr_read_generic, SPR_NOACCESS, | |
6242 | 0x00000000); /* TOFIX */ | |
6243 | /* XXX : not implemented */ | |
6244 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6245 | SPR_NOACCESS, SPR_NOACCESS, | |
6246 | &spr_read_generic, &spr_write_generic, | |
6247 | 0x00000000); /* TOFIX */ | |
6248 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6249 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6250 | &spr_read_hior, &spr_write_hior, |
6251 | 0x00000000); | |
2f462816 JM |
6252 | #if !defined(CONFIG_USER_ONLY) |
6253 | env->slb_nr = 32; | |
6254 | #endif | |
6255 | init_excp_970(env); | |
6256 | env->dcache_line_size = 128; | |
6257 | env->icache_line_size = 128; | |
6258 | /* Allocate hardware IRQ controller */ | |
6259 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6260 | /* Can't find information on what this should be on reset. This |
6261 | * value is the one used by 74xx processors. */ | |
6262 | vscr_init(env, 0x00010000); | |
2f462816 JM |
6263 | } |
6264 | ||
a750fc0b | 6265 | /* PowerPC 620 */ |
082c6681 JM |
6266 | #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ |
6267 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ | |
6268 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ | |
6269 | PPC_FLOAT_STFIWX | \ | |
6270 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ | |
6271 | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ | |
6272 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ | |
6273 | PPC_SEGMENT | PPC_EXTERN | \ | |
a750fc0b | 6274 | PPC_64B | PPC_SLBI) |
add78955 JM |
6275 | #define POWERPC_MSRM_620 (0x800000000005FF77ULL) |
6276 | //#define POWERPC_MMU_620 (POWERPC_MMU_620) | |
a750fc0b | 6277 | #define POWERPC_EXCP_620 (POWERPC_EXCP_970) |
faadf50e | 6278 | #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx) |
237c0af0 | 6279 | #define POWERPC_BFDM_620 (bfd_mach_ppc64) |
4018bae9 | 6280 | #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ |
add78955 | 6281 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) |
2f462816 | 6282 | #define check_pow_620 check_pow_nocheck /* Check this */ |
a750fc0b | 6283 | |
578bb252 | 6284 | __attribute__ (( unused )) |
a750fc0b JM |
6285 | static void init_proc_620 (CPUPPCState *env) |
6286 | { | |
6287 | gen_spr_ne_601(env); | |
6288 | gen_spr_620(env); | |
6289 | /* Time base */ | |
6290 | gen_tbl(env); | |
6291 | /* Hardware implementation registers */ | |
6292 | /* XXX : not implemented */ | |
6293 | spr_register(env, SPR_HID0, "HID0", | |
6294 | SPR_NOACCESS, SPR_NOACCESS, | |
6295 | &spr_read_generic, &spr_write_generic, | |
6296 | 0x00000000); | |
6297 | /* Memory management */ | |
6298 | gen_low_BATs(env); | |
e1833e1f | 6299 | init_excp_620(env); |
d63001d1 JM |
6300 | env->dcache_line_size = 64; |
6301 | env->icache_line_size = 64; | |
faadf50e JM |
6302 | /* Allocate hardware IRQ controller */ |
6303 | ppc6xx_irq_init(env); | |
a750fc0b | 6304 | } |
a750fc0b JM |
6305 | #endif /* defined (TARGET_PPC64) */ |
6306 | ||
6307 | /* Default 32 bits PowerPC target will be 604 */ | |
6308 | #define CPU_POWERPC_PPC32 CPU_POWERPC_604 | |
6309 | #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604 | |
6310 | #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604 | |
6311 | #define POWERPC_MMU_PPC32 POWERPC_MMU_604 | |
6312 | #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604 | |
6313 | #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604 | |
237c0af0 | 6314 | #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604 |
d26bfc9a | 6315 | #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604 |
2f462816 JM |
6316 | #define check_pow_PPC32 check_pow_604 |
6317 | #define init_proc_PPC32 init_proc_604 | |
a750fc0b JM |
6318 | |
6319 | /* Default 64 bits PowerPC target will be 970 FX */ | |
6320 | #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX | |
6321 | #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX | |
6322 | #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX | |
6323 | #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX | |
6324 | #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX | |
6325 | #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX | |
237c0af0 | 6326 | #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX |
d26bfc9a | 6327 | #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX |
2f462816 JM |
6328 | #define check_pow_PPC64 check_pow_970FX |
6329 | #define init_proc_PPC64 init_proc_970FX | |
a750fc0b JM |
6330 | |
6331 | /* Default PowerPC target will be PowerPC 32 */ | |
6332 | #if defined (TARGET_PPC64) && 0 // XXX: TODO | |
d12f4c38 JM |
6333 | #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64 |
6334 | #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64 | |
6335 | #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64 | |
6336 | #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64 | |
6337 | #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64 | |
6338 | #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64 | |
237c0af0 | 6339 | #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64 |
d26bfc9a | 6340 | #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64 |
2f462816 JM |
6341 | #define check_pow_DEFAULT check_pow_PPC64 |
6342 | #define init_proc_DEFAULT init_proc_PPC64 | |
a750fc0b | 6343 | #else |
d12f4c38 JM |
6344 | #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32 |
6345 | #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32 | |
6346 | #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32 | |
6347 | #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32 | |
6348 | #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32 | |
6349 | #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32 | |
237c0af0 | 6350 | #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32 |
d26bfc9a | 6351 | #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32 |
2f462816 JM |
6352 | #define check_pow_DEFAULT check_pow_PPC32 |
6353 | #define init_proc_DEFAULT init_proc_PPC32 | |
a750fc0b JM |
6354 | #endif |
6355 | ||
6356 | /*****************************************************************************/ | |
6357 | /* PVR definitions for most known PowerPC */ | |
6358 | enum { | |
6359 | /* PowerPC 401 family */ | |
6360 | /* Generic PowerPC 401 */ | |
80d11f44 | 6361 | #define CPU_POWERPC_401 CPU_POWERPC_401G2 |
a750fc0b | 6362 | /* PowerPC 401 cores */ |
80d11f44 JM |
6363 | CPU_POWERPC_401A1 = 0x00210000, |
6364 | CPU_POWERPC_401B2 = 0x00220000, | |
a750fc0b | 6365 | #if 0 |
80d11f44 | 6366 | CPU_POWERPC_401B3 = xxx, |
a750fc0b | 6367 | #endif |
80d11f44 JM |
6368 | CPU_POWERPC_401C2 = 0x00230000, |
6369 | CPU_POWERPC_401D2 = 0x00240000, | |
6370 | CPU_POWERPC_401E2 = 0x00250000, | |
6371 | CPU_POWERPC_401F2 = 0x00260000, | |
6372 | CPU_POWERPC_401G2 = 0x00270000, | |
a750fc0b JM |
6373 | /* PowerPC 401 microcontrolers */ |
6374 | #if 0 | |
80d11f44 | 6375 | CPU_POWERPC_401GF = xxx, |
a750fc0b | 6376 | #endif |
80d11f44 | 6377 | #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2 |
a750fc0b | 6378 | /* IBM Processor for Network Resources */ |
80d11f44 | 6379 | CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */ |
a750fc0b | 6380 | #if 0 |
80d11f44 | 6381 | CPU_POWERPC_XIPCHIP = xxx, |
a750fc0b JM |
6382 | #endif |
6383 | /* PowerPC 403 family */ | |
6384 | /* Generic PowerPC 403 */ | |
80d11f44 | 6385 | #define CPU_POWERPC_403 CPU_POWERPC_403GC |
a750fc0b | 6386 | /* PowerPC 403 microcontrollers */ |
80d11f44 JM |
6387 | CPU_POWERPC_403GA = 0x00200011, |
6388 | CPU_POWERPC_403GB = 0x00200100, | |
6389 | CPU_POWERPC_403GC = 0x00200200, | |
6390 | CPU_POWERPC_403GCX = 0x00201400, | |
a750fc0b | 6391 | #if 0 |
80d11f44 | 6392 | CPU_POWERPC_403GP = xxx, |
a750fc0b JM |
6393 | #endif |
6394 | /* PowerPC 405 family */ | |
6395 | /* Generic PowerPC 405 */ | |
80d11f44 | 6396 | #define CPU_POWERPC_405 CPU_POWERPC_405D4 |
a750fc0b JM |
6397 | /* PowerPC 405 cores */ |
6398 | #if 0 | |
80d11f44 | 6399 | CPU_POWERPC_405A3 = xxx, |
a750fc0b JM |
6400 | #endif |
6401 | #if 0 | |
80d11f44 | 6402 | CPU_POWERPC_405A4 = xxx, |
a750fc0b JM |
6403 | #endif |
6404 | #if 0 | |
80d11f44 | 6405 | CPU_POWERPC_405B3 = xxx, |
a750fc0b JM |
6406 | #endif |
6407 | #if 0 | |
80d11f44 | 6408 | CPU_POWERPC_405B4 = xxx, |
a750fc0b JM |
6409 | #endif |
6410 | #if 0 | |
80d11f44 | 6411 | CPU_POWERPC_405C3 = xxx, |
a750fc0b JM |
6412 | #endif |
6413 | #if 0 | |
80d11f44 | 6414 | CPU_POWERPC_405C4 = xxx, |
a750fc0b | 6415 | #endif |
80d11f44 | 6416 | CPU_POWERPC_405D2 = 0x20010000, |
a750fc0b | 6417 | #if 0 |
80d11f44 | 6418 | CPU_POWERPC_405D3 = xxx, |
a750fc0b | 6419 | #endif |
80d11f44 | 6420 | CPU_POWERPC_405D4 = 0x41810000, |
a750fc0b | 6421 | #if 0 |
80d11f44 | 6422 | CPU_POWERPC_405D5 = xxx, |
a750fc0b JM |
6423 | #endif |
6424 | #if 0 | |
80d11f44 | 6425 | CPU_POWERPC_405E4 = xxx, |
a750fc0b JM |
6426 | #endif |
6427 | #if 0 | |
80d11f44 | 6428 | CPU_POWERPC_405F4 = xxx, |
a750fc0b JM |
6429 | #endif |
6430 | #if 0 | |
80d11f44 | 6431 | CPU_POWERPC_405F5 = xxx, |
a750fc0b JM |
6432 | #endif |
6433 | #if 0 | |
80d11f44 | 6434 | CPU_POWERPC_405F6 = xxx, |
a750fc0b JM |
6435 | #endif |
6436 | /* PowerPC 405 microcontrolers */ | |
6437 | /* XXX: missing 0x200108a0 */ | |
80d11f44 JM |
6438 | #define CPU_POWERPC_405CR CPU_POWERPC_405CRc |
6439 | CPU_POWERPC_405CRa = 0x40110041, | |
6440 | CPU_POWERPC_405CRb = 0x401100C5, | |
6441 | CPU_POWERPC_405CRc = 0x40110145, | |
6442 | CPU_POWERPC_405EP = 0x51210950, | |
a750fc0b | 6443 | #if 0 |
80d11f44 | 6444 | CPU_POWERPC_405EXr = xxx, |
a750fc0b | 6445 | #endif |
80d11f44 | 6446 | CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */ |
a750fc0b | 6447 | #if 0 |
80d11f44 JM |
6448 | CPU_POWERPC_405FX = xxx, |
6449 | #endif | |
6450 | #define CPU_POWERPC_405GP CPU_POWERPC_405GPd | |
6451 | CPU_POWERPC_405GPa = 0x40110000, | |
6452 | CPU_POWERPC_405GPb = 0x40110040, | |
6453 | CPU_POWERPC_405GPc = 0x40110082, | |
6454 | CPU_POWERPC_405GPd = 0x401100C4, | |
6455 | #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc | |
6456 | CPU_POWERPC_405GPR = 0x50910951, | |
a750fc0b | 6457 | #if 0 |
80d11f44 | 6458 | CPU_POWERPC_405H = xxx, |
a750fc0b JM |
6459 | #endif |
6460 | #if 0 | |
80d11f44 | 6461 | CPU_POWERPC_405L = xxx, |
a750fc0b | 6462 | #endif |
80d11f44 | 6463 | CPU_POWERPC_405LP = 0x41F10000, |
a750fc0b | 6464 | #if 0 |
80d11f44 | 6465 | CPU_POWERPC_405PM = xxx, |
a750fc0b JM |
6466 | #endif |
6467 | #if 0 | |
80d11f44 | 6468 | CPU_POWERPC_405PS = xxx, |
a750fc0b JM |
6469 | #endif |
6470 | #if 0 | |
80d11f44 | 6471 | CPU_POWERPC_405S = xxx, |
a750fc0b JM |
6472 | #endif |
6473 | /* IBM network processors */ | |
80d11f44 JM |
6474 | CPU_POWERPC_NPE405H = 0x414100C0, |
6475 | CPU_POWERPC_NPE405H2 = 0x41410140, | |
6476 | CPU_POWERPC_NPE405L = 0x416100C0, | |
6477 | CPU_POWERPC_NPE4GS3 = 0x40B10000, | |
a750fc0b | 6478 | #if 0 |
80d11f44 | 6479 | CPU_POWERPC_NPCxx1 = xxx, |
a750fc0b JM |
6480 | #endif |
6481 | #if 0 | |
80d11f44 | 6482 | CPU_POWERPC_NPR161 = xxx, |
a750fc0b JM |
6483 | #endif |
6484 | #if 0 | |
80d11f44 | 6485 | CPU_POWERPC_LC77700 = xxx, |
a750fc0b JM |
6486 | #endif |
6487 | /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ | |
6488 | #if 0 | |
80d11f44 | 6489 | CPU_POWERPC_STB01000 = xxx, |
a750fc0b JM |
6490 | #endif |
6491 | #if 0 | |
80d11f44 | 6492 | CPU_POWERPC_STB01010 = xxx, |
a750fc0b JM |
6493 | #endif |
6494 | #if 0 | |
80d11f44 | 6495 | CPU_POWERPC_STB0210 = xxx, /* 401B3 */ |
a750fc0b | 6496 | #endif |
80d11f44 | 6497 | CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */ |
a750fc0b | 6498 | #if 0 |
80d11f44 | 6499 | CPU_POWERPC_STB043 = xxx, |
a750fc0b JM |
6500 | #endif |
6501 | #if 0 | |
80d11f44 | 6502 | CPU_POWERPC_STB045 = xxx, |
a750fc0b | 6503 | #endif |
80d11f44 JM |
6504 | CPU_POWERPC_STB04 = 0x41810000, |
6505 | CPU_POWERPC_STB25 = 0x51510950, | |
a750fc0b | 6506 | #if 0 |
80d11f44 | 6507 | CPU_POWERPC_STB130 = xxx, |
a750fc0b JM |
6508 | #endif |
6509 | /* Xilinx cores */ | |
80d11f44 JM |
6510 | CPU_POWERPC_X2VP4 = 0x20010820, |
6511 | #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4 | |
6512 | CPU_POWERPC_X2VP20 = 0x20010860, | |
6513 | #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20 | |
a750fc0b | 6514 | #if 0 |
80d11f44 | 6515 | CPU_POWERPC_ZL10310 = xxx, |
a750fc0b JM |
6516 | #endif |
6517 | #if 0 | |
80d11f44 | 6518 | CPU_POWERPC_ZL10311 = xxx, |
a750fc0b JM |
6519 | #endif |
6520 | #if 0 | |
80d11f44 | 6521 | CPU_POWERPC_ZL10320 = xxx, |
a750fc0b JM |
6522 | #endif |
6523 | #if 0 | |
80d11f44 | 6524 | CPU_POWERPC_ZL10321 = xxx, |
a750fc0b JM |
6525 | #endif |
6526 | /* PowerPC 440 family */ | |
6527 | /* Generic PowerPC 440 */ | |
80d11f44 | 6528 | #define CPU_POWERPC_440 CPU_POWERPC_440GXf |
a750fc0b JM |
6529 | /* PowerPC 440 cores */ |
6530 | #if 0 | |
80d11f44 | 6531 | CPU_POWERPC_440A4 = xxx, |
a750fc0b JM |
6532 | #endif |
6533 | #if 0 | |
80d11f44 | 6534 | CPU_POWERPC_440A5 = xxx, |
a750fc0b JM |
6535 | #endif |
6536 | #if 0 | |
80d11f44 | 6537 | CPU_POWERPC_440B4 = xxx, |
a750fc0b JM |
6538 | #endif |
6539 | #if 0 | |
80d11f44 | 6540 | CPU_POWERPC_440F5 = xxx, |
a750fc0b JM |
6541 | #endif |
6542 | #if 0 | |
80d11f44 | 6543 | CPU_POWERPC_440G5 = xxx, |
a750fc0b JM |
6544 | #endif |
6545 | #if 0 | |
80d11f44 | 6546 | CPU_POWERPC_440H4 = xxx, |
a750fc0b JM |
6547 | #endif |
6548 | #if 0 | |
80d11f44 | 6549 | CPU_POWERPC_440H6 = xxx, |
a750fc0b JM |
6550 | #endif |
6551 | /* PowerPC 440 microcontrolers */ | |
80d11f44 JM |
6552 | #define CPU_POWERPC_440EP CPU_POWERPC_440EPb |
6553 | CPU_POWERPC_440EPa = 0x42221850, | |
6554 | CPU_POWERPC_440EPb = 0x422218D3, | |
6555 | #define CPU_POWERPC_440GP CPU_POWERPC_440GPc | |
6556 | CPU_POWERPC_440GPb = 0x40120440, | |
6557 | CPU_POWERPC_440GPc = 0x40120481, | |
6558 | #define CPU_POWERPC_440GR CPU_POWERPC_440GRa | |
6559 | #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb | |
6560 | CPU_POWERPC_440GRX = 0x200008D0, | |
6561 | #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX | |
6562 | #define CPU_POWERPC_440GX CPU_POWERPC_440GXf | |
6563 | CPU_POWERPC_440GXa = 0x51B21850, | |
6564 | CPU_POWERPC_440GXb = 0x51B21851, | |
6565 | CPU_POWERPC_440GXc = 0x51B21892, | |
6566 | CPU_POWERPC_440GXf = 0x51B21894, | |
a750fc0b | 6567 | #if 0 |
80d11f44 | 6568 | CPU_POWERPC_440S = xxx, |
a750fc0b | 6569 | #endif |
80d11f44 JM |
6570 | CPU_POWERPC_440SP = 0x53221850, |
6571 | CPU_POWERPC_440SP2 = 0x53221891, | |
6572 | CPU_POWERPC_440SPE = 0x53421890, | |
a750fc0b JM |
6573 | /* PowerPC 460 family */ |
6574 | #if 0 | |
6575 | /* Generic PowerPC 464 */ | |
80d11f44 | 6576 | #define CPU_POWERPC_464 CPU_POWERPC_464H90 |
a750fc0b JM |
6577 | #endif |
6578 | /* PowerPC 464 microcontrolers */ | |
6579 | #if 0 | |
80d11f44 | 6580 | CPU_POWERPC_464H90 = xxx, |
a750fc0b JM |
6581 | #endif |
6582 | #if 0 | |
80d11f44 | 6583 | CPU_POWERPC_464H90FP = xxx, |
a750fc0b JM |
6584 | #endif |
6585 | /* Freescale embedded PowerPC cores */ | |
c3e36823 | 6586 | /* PowerPC MPC 5xx cores (aka RCPU) */ |
80d11f44 JM |
6587 | CPU_POWERPC_MPC5xx = 0x00020020, |
6588 | #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx | |
6589 | #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx | |
6590 | #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx | |
6591 | #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx | |
6592 | #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx | |
6593 | #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx | |
6594 | #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx | |
6595 | #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx | |
6596 | #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx | |
6597 | #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx | |
6598 | #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx | |
6599 | #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx | |
6600 | #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx | |
c3e36823 | 6601 | /* PowerPC MPC 8xx cores (aka PowerQUICC) */ |
80d11f44 JM |
6602 | CPU_POWERPC_MPC8xx = 0x00500000, |
6603 | #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx | |
6604 | #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx | |
6605 | #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx | |
6606 | #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx | |
6607 | #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx | |
6608 | #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx | |
6609 | #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx | |
6610 | #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx | |
6611 | #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx | |
6612 | #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx | |
6613 | #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx | |
6614 | #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx | |
6615 | #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx | |
6616 | #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx | |
6617 | #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx | |
c3e36823 | 6618 | /* G2 cores (aka PowerQUICC-II) */ |
80d11f44 JM |
6619 | CPU_POWERPC_G2 = 0x00810011, |
6620 | CPU_POWERPC_G2H4 = 0x80811010, | |
6621 | CPU_POWERPC_G2gp = 0x80821010, | |
6622 | CPU_POWERPC_G2ls = 0x90810010, | |
6623 | CPU_POWERPC_MPC603 = 0x00810100, | |
6624 | CPU_POWERPC_G2_HIP3 = 0x00810101, | |
6625 | CPU_POWERPC_G2_HIP4 = 0x80811014, | |
c3e36823 | 6626 | /* G2_LE core (aka PowerQUICC-II) */ |
80d11f44 JM |
6627 | CPU_POWERPC_G2LE = 0x80820010, |
6628 | CPU_POWERPC_G2LEgp = 0x80822010, | |
6629 | CPU_POWERPC_G2LEls = 0xA0822010, | |
6630 | CPU_POWERPC_G2LEgp1 = 0x80822011, | |
6631 | CPU_POWERPC_G2LEgp3 = 0x80822013, | |
6632 | /* MPC52xx microcontrollers */ | |
c3e36823 | 6633 | /* XXX: MPC 5121 ? */ |
80d11f44 JM |
6634 | #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200 |
6635 | #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12 | |
6636 | #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1 | |
6637 | #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1 | |
6638 | #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1 | |
6639 | #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21 | |
6640 | #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1 | |
6641 | #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1 | |
6642 | /* MPC82xx microcontrollers */ | |
6643 | #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280 | |
6644 | #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603 | |
6645 | #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4 | |
6646 | #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4 | |
6647 | #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3 | |
6648 | #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3 | |
6649 | #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4 | |
6650 | #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3 | |
6651 | #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4 | |
6652 | #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4 | |
6653 | #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3 | |
6654 | #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4 | |
6655 | #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4 | |
6656 | #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3 | |
6657 | #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4 | |
6658 | #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4 | |
6659 | #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3 | |
6660 | #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4 | |
6661 | #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4 | |
6662 | #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3 | |
6663 | #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4 | |
6664 | #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4 | |
6665 | #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3 | |
6666 | #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4 | |
6667 | #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3 | |
6668 | #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3 | |
6669 | #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3 | |
6670 | #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3 | |
6671 | #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3 | |
a750fc0b | 6672 | /* e200 family */ |
80d11f44 JM |
6673 | /* e200 cores */ |
6674 | #define CPU_POWERPC_e200 CPU_POWERPC_e200z6 | |
a750fc0b | 6675 | #if 0 |
80d11f44 | 6676 | CPU_POWERPC_e200z0 = xxx, |
a750fc0b JM |
6677 | #endif |
6678 | #if 0 | |
80d11f44 | 6679 | CPU_POWERPC_e200z1 = xxx, |
c3e36823 JM |
6680 | #endif |
6681 | #if 0 /* ? */ | |
80d11f44 JM |
6682 | CPU_POWERPC_e200z3 = 0x81120000, |
6683 | #endif | |
6684 | CPU_POWERPC_e200z5 = 0x81000000, | |
6685 | CPU_POWERPC_e200z6 = 0x81120000, | |
6686 | /* MPC55xx microcontrollers */ | |
6687 | #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567 | |
6688 | #if 0 | |
6689 | #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1 | |
6690 | #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0 | |
6691 | #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1 | |
6692 | #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1 | |
6693 | #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0 | |
6694 | #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1 | |
6695 | #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1 | |
6696 | #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1 | |
6697 | #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0 | |
6698 | #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1 | |
6699 | #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1 | |
6700 | #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0 | |
6701 | #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1 | |
6702 | #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1 | |
6703 | #endif | |
6704 | #if 0 | |
6705 | #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3 | |
6706 | #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3 | |
6707 | #endif | |
6708 | #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6 | |
6709 | #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6 | |
6710 | #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6 | |
6711 | #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6 | |
6712 | #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6 | |
6713 | #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6 | |
a750fc0b | 6714 | /* e300 family */ |
80d11f44 JM |
6715 | /* e300 cores */ |
6716 | #define CPU_POWERPC_e300 CPU_POWERPC_e300c3 | |
6717 | CPU_POWERPC_e300c1 = 0x00830010, | |
6718 | CPU_POWERPC_e300c2 = 0x00840010, | |
6719 | CPU_POWERPC_e300c3 = 0x00850010, | |
6720 | CPU_POWERPC_e300c4 = 0x00860010, | |
6721 | /* MPC83xx microcontrollers */ | |
6722 | #define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3 | |
6723 | #define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3 | |
6724 | #define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3 | |
6725 | #define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3 | |
6726 | #define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3 | |
6727 | #define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3 | |
6728 | #define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2 | |
6729 | #define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2 | |
6730 | #define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2 | |
6731 | #define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2 | |
6732 | #define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1 | |
6733 | #define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1 | |
6734 | #define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1 | |
6735 | #define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1 | |
6736 | #define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1 | |
6737 | #define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1 | |
6738 | #define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1 | |
6739 | #define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1 | |
6740 | #define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1 | |
6741 | #define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1 | |
6742 | #define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1 | |
6743 | #define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1 | |
6744 | #define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1 | |
6745 | #define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1 | |
6746 | #define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4 | |
6747 | #define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4 | |
6748 | #define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4 | |
6749 | #define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4 | |
6750 | #define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4 | |
6751 | #define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4 | |
a750fc0b | 6752 | /* e500 family */ |
80d11f44 JM |
6753 | /* e500 cores */ |
6754 | #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22 | |
bd5ea513 | 6755 | #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20 |
80d11f44 | 6756 | #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22 |
bd5ea513 AJ |
6757 | CPU_POWERPC_e500v1_v10 = 0x80200010, |
6758 | CPU_POWERPC_e500v1_v20 = 0x80200020, | |
80d11f44 JM |
6759 | CPU_POWERPC_e500v2_v10 = 0x80210010, |
6760 | CPU_POWERPC_e500v2_v11 = 0x80210011, | |
6761 | CPU_POWERPC_e500v2_v20 = 0x80210020, | |
6762 | CPU_POWERPC_e500v2_v21 = 0x80210021, | |
6763 | CPU_POWERPC_e500v2_v22 = 0x80210022, | |
6764 | CPU_POWERPC_e500v2_v30 = 0x80210030, | |
6765 | /* MPC85xx microcontrollers */ | |
6766 | #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11 | |
6767 | #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21 | |
6768 | #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22 | |
6769 | #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11 | |
6770 | #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21 | |
6771 | #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22 | |
6772 | #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21 | |
bd5ea513 AJ |
6773 | #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10 |
6774 | #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20 | |
6775 | #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20 | |
80d11f44 | 6776 | #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11 |
bd5ea513 AJ |
6777 | #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20 |
6778 | #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20 | |
80d11f44 | 6779 | #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11 |
bd5ea513 AJ |
6780 | #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20 |
6781 | #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20 | |
80d11f44 JM |
6782 | #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21 |
6783 | #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10 | |
6784 | #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11 | |
6785 | #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20 | |
6786 | #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21 | |
6787 | #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21 | |
6788 | #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10 | |
6789 | #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11 | |
6790 | #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20 | |
6791 | #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21 | |
6792 | #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11 | |
6793 | #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21 | |
6794 | #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22 | |
6795 | #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22 | |
6796 | #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11 | |
6797 | #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21 | |
6798 | #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21 | |
6799 | #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10 | |
6800 | #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20 | |
6801 | #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21 | |
6802 | #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21 | |
6803 | #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10 | |
6804 | #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20 | |
6805 | #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21 | |
6806 | #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21 | |
6807 | #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10 | |
6808 | #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20 | |
6809 | #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21 | |
6810 | #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21 | |
6811 | #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10 | |
6812 | #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11 | |
6813 | #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20 | |
6814 | #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21 | |
6815 | #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21 | |
6816 | #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10 | |
6817 | #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11 | |
6818 | #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20 | |
6819 | #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21 | |
6820 | #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11 | |
6821 | #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10 | |
6822 | #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11 | |
6823 | #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11 | |
6824 | #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10 | |
6825 | #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11 | |
6826 | #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21 | |
6827 | #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10 | |
6828 | #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20 | |
6829 | #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21 | |
6830 | #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22 | |
6831 | #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22 | |
6832 | #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22 | |
6833 | #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22 | |
6834 | #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30 | |
6835 | #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30 | |
a750fc0b | 6836 | /* e600 family */ |
80d11f44 JM |
6837 | /* e600 cores */ |
6838 | CPU_POWERPC_e600 = 0x80040010, | |
6839 | /* MPC86xx microcontrollers */ | |
6840 | #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600 | |
6841 | #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600 | |
6842 | #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600 | |
a750fc0b | 6843 | /* PowerPC 6xx cores */ |
80d11f44 JM |
6844 | #define CPU_POWERPC_601 CPU_POWERPC_601_v2 |
6845 | CPU_POWERPC_601_v0 = 0x00010001, | |
6846 | CPU_POWERPC_601_v1 = 0x00010001, | |
bd928eba | 6847 | #define CPU_POWERPC_601v CPU_POWERPC_601_v2 |
80d11f44 JM |
6848 | CPU_POWERPC_601_v2 = 0x00010002, |
6849 | CPU_POWERPC_602 = 0x00050100, | |
6850 | CPU_POWERPC_603 = 0x00030100, | |
6851 | #define CPU_POWERPC_603E CPU_POWERPC_603E_v41 | |
6852 | CPU_POWERPC_603E_v11 = 0x00060101, | |
6853 | CPU_POWERPC_603E_v12 = 0x00060102, | |
6854 | CPU_POWERPC_603E_v13 = 0x00060103, | |
6855 | CPU_POWERPC_603E_v14 = 0x00060104, | |
6856 | CPU_POWERPC_603E_v22 = 0x00060202, | |
6857 | CPU_POWERPC_603E_v3 = 0x00060300, | |
6858 | CPU_POWERPC_603E_v4 = 0x00060400, | |
6859 | CPU_POWERPC_603E_v41 = 0x00060401, | |
6860 | CPU_POWERPC_603E7t = 0x00071201, | |
6861 | CPU_POWERPC_603E7v = 0x00070100, | |
6862 | CPU_POWERPC_603E7v1 = 0x00070101, | |
6863 | CPU_POWERPC_603E7v2 = 0x00070201, | |
6864 | CPU_POWERPC_603E7 = 0x00070200, | |
6865 | CPU_POWERPC_603P = 0x00070000, | |
6866 | #define CPU_POWERPC_603R CPU_POWERPC_603E7t | |
c3e36823 | 6867 | /* XXX: missing 0x00040303 (604) */ |
80d11f44 JM |
6868 | CPU_POWERPC_604 = 0x00040103, |
6869 | #define CPU_POWERPC_604E CPU_POWERPC_604E_v24 | |
c3e36823 JM |
6870 | /* XXX: missing 0x00091203 */ |
6871 | /* XXX: missing 0x00092110 */ | |
6872 | /* XXX: missing 0x00092120 */ | |
80d11f44 JM |
6873 | CPU_POWERPC_604E_v10 = 0x00090100, |
6874 | CPU_POWERPC_604E_v22 = 0x00090202, | |
6875 | CPU_POWERPC_604E_v24 = 0x00090204, | |
c3e36823 JM |
6876 | /* XXX: missing 0x000a0100 */ |
6877 | /* XXX: missing 0x00093102 */ | |
80d11f44 | 6878 | CPU_POWERPC_604R = 0x000a0101, |
a750fc0b | 6879 | #if 0 |
80d11f44 | 6880 | CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */ |
a750fc0b JM |
6881 | #endif |
6882 | /* PowerPC 740/750 cores (aka G3) */ | |
6883 | /* XXX: missing 0x00084202 */ | |
80d11f44 | 6884 | #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31 |
bd928eba | 6885 | CPU_POWERPC_7x0_v10 = 0x00080100, |
80d11f44 JM |
6886 | CPU_POWERPC_7x0_v20 = 0x00080200, |
6887 | CPU_POWERPC_7x0_v21 = 0x00080201, | |
6888 | CPU_POWERPC_7x0_v22 = 0x00080202, | |
6889 | CPU_POWERPC_7x0_v30 = 0x00080300, | |
6890 | CPU_POWERPC_7x0_v31 = 0x00080301, | |
6891 | CPU_POWERPC_740E = 0x00080100, | |
bd928eba | 6892 | CPU_POWERPC_750E = 0x00080200, |
80d11f44 | 6893 | CPU_POWERPC_7x0P = 0x10080000, |
a750fc0b | 6894 | /* XXX: missing 0x00087010 (CL ?) */ |
bd928eba JM |
6895 | #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20 |
6896 | CPU_POWERPC_750CL_v10 = 0x00087200, | |
6897 | CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */ | |
80d11f44 | 6898 | #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22 |
bd928eba JM |
6899 | CPU_POWERPC_750CX_v10 = 0x00082100, |
6900 | CPU_POWERPC_750CX_v20 = 0x00082200, | |
80d11f44 JM |
6901 | CPU_POWERPC_750CX_v21 = 0x00082201, |
6902 | CPU_POWERPC_750CX_v22 = 0x00082202, | |
6903 | #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b | |
6904 | CPU_POWERPC_750CXE_v21 = 0x00082211, | |
6905 | CPU_POWERPC_750CXE_v22 = 0x00082212, | |
6906 | CPU_POWERPC_750CXE_v23 = 0x00082213, | |
6907 | CPU_POWERPC_750CXE_v24 = 0x00082214, | |
6908 | CPU_POWERPC_750CXE_v24b = 0x00083214, | |
bd928eba JM |
6909 | CPU_POWERPC_750CXE_v30 = 0x00082310, |
6910 | CPU_POWERPC_750CXE_v31 = 0x00082311, | |
80d11f44 JM |
6911 | CPU_POWERPC_750CXE_v31b = 0x00083311, |
6912 | CPU_POWERPC_750CXR = 0x00083410, | |
bd928eba | 6913 | CPU_POWERPC_750FL = 0x70000203, |
80d11f44 JM |
6914 | #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23 |
6915 | CPU_POWERPC_750FX_v10 = 0x70000100, | |
6916 | CPU_POWERPC_750FX_v20 = 0x70000200, | |
6917 | CPU_POWERPC_750FX_v21 = 0x70000201, | |
6918 | CPU_POWERPC_750FX_v22 = 0x70000202, | |
6919 | CPU_POWERPC_750FX_v23 = 0x70000203, | |
6920 | CPU_POWERPC_750GL = 0x70020102, | |
6921 | #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12 | |
6922 | CPU_POWERPC_750GX_v10 = 0x70020100, | |
6923 | CPU_POWERPC_750GX_v11 = 0x70020101, | |
6924 | CPU_POWERPC_750GX_v12 = 0x70020102, | |
6925 | #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */ | |
bd928eba JM |
6926 | CPU_POWERPC_750L_v20 = 0x00088200, |
6927 | CPU_POWERPC_750L_v21 = 0x00088201, | |
80d11f44 JM |
6928 | CPU_POWERPC_750L_v22 = 0x00088202, |
6929 | CPU_POWERPC_750L_v30 = 0x00088300, | |
6930 | CPU_POWERPC_750L_v32 = 0x00088302, | |
a750fc0b | 6931 | /* PowerPC 745/755 cores */ |
80d11f44 JM |
6932 | #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28 |
6933 | CPU_POWERPC_7x5_v10 = 0x00083100, | |
6934 | CPU_POWERPC_7x5_v11 = 0x00083101, | |
6935 | CPU_POWERPC_7x5_v20 = 0x00083200, | |
6936 | CPU_POWERPC_7x5_v21 = 0x00083201, | |
6937 | CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */ | |
6938 | CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */ | |
6939 | CPU_POWERPC_7x5_v24 = 0x00083204, | |
6940 | CPU_POWERPC_7x5_v25 = 0x00083205, | |
6941 | CPU_POWERPC_7x5_v26 = 0x00083206, | |
6942 | CPU_POWERPC_7x5_v27 = 0x00083207, | |
6943 | CPU_POWERPC_7x5_v28 = 0x00083208, | |
a750fc0b | 6944 | #if 0 |
80d11f44 | 6945 | CPU_POWERPC_7x5P = xxx, |
a750fc0b JM |
6946 | #endif |
6947 | /* PowerPC 74xx cores (aka G4) */ | |
6948 | /* XXX: missing 0x000C1101 */ | |
80d11f44 JM |
6949 | #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29 |
6950 | CPU_POWERPC_7400_v10 = 0x000C0100, | |
6951 | CPU_POWERPC_7400_v11 = 0x000C0101, | |
6952 | CPU_POWERPC_7400_v20 = 0x000C0200, | |
4e777442 | 6953 | CPU_POWERPC_7400_v21 = 0x000C0201, |
80d11f44 JM |
6954 | CPU_POWERPC_7400_v22 = 0x000C0202, |
6955 | CPU_POWERPC_7400_v26 = 0x000C0206, | |
6956 | CPU_POWERPC_7400_v27 = 0x000C0207, | |
6957 | CPU_POWERPC_7400_v28 = 0x000C0208, | |
6958 | CPU_POWERPC_7400_v29 = 0x000C0209, | |
6959 | #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14 | |
6960 | CPU_POWERPC_7410_v10 = 0x800C1100, | |
6961 | CPU_POWERPC_7410_v11 = 0x800C1101, | |
6962 | CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */ | |
6963 | CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */ | |
6964 | CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */ | |
6965 | #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21 | |
6966 | CPU_POWERPC_7448_v10 = 0x80040100, | |
6967 | CPU_POWERPC_7448_v11 = 0x80040101, | |
6968 | CPU_POWERPC_7448_v20 = 0x80040200, | |
6969 | CPU_POWERPC_7448_v21 = 0x80040201, | |
6970 | #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21 | |
6971 | CPU_POWERPC_7450_v10 = 0x80000100, | |
6972 | CPU_POWERPC_7450_v11 = 0x80000101, | |
6973 | CPU_POWERPC_7450_v12 = 0x80000102, | |
4e777442 | 6974 | CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */ |
80d11f44 | 6975 | CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */ |
4e777442 JM |
6976 | #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23 |
6977 | CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */ | |
6978 | /* XXX: this entry might be a bug in some documentation */ | |
6979 | CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */ | |
80d11f44 JM |
6980 | #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32 |
6981 | CPU_POWERPC_74x5_v10 = 0x80010100, | |
c3e36823 | 6982 | /* XXX: missing 0x80010200 */ |
80d11f44 JM |
6983 | CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */ |
6984 | CPU_POWERPC_74x5_v32 = 0x80010302, | |
6985 | CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */ | |
6986 | CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */ | |
6987 | #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12 | |
80d11f44 | 6988 | CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */ |
082c6681 | 6989 | CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */ |
80d11f44 | 6990 | CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */ |
082c6681 JM |
6991 | #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12 |
6992 | CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */ | |
6993 | CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */ | |
6994 | CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */ | |
a750fc0b | 6995 | /* 64 bits PowerPC */ |
00af685f | 6996 | #if defined(TARGET_PPC64) |
80d11f44 JM |
6997 | CPU_POWERPC_620 = 0x00140000, |
6998 | CPU_POWERPC_630 = 0x00400000, | |
6999 | CPU_POWERPC_631 = 0x00410104, | |
7000 | CPU_POWERPC_POWER4 = 0x00350000, | |
7001 | CPU_POWERPC_POWER4P = 0x00380000, | |
c3e36823 | 7002 | /* XXX: missing 0x003A0201 */ |
80d11f44 JM |
7003 | CPU_POWERPC_POWER5 = 0x003A0203, |
7004 | #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5 | |
7005 | CPU_POWERPC_POWER5P = 0x003B0000, | |
7006 | #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P | |
7007 | CPU_POWERPC_POWER6 = 0x003E0000, | |
7008 | CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */ | |
7009 | CPU_POWERPC_POWER6A = 0x0F000002, | |
7010 | CPU_POWERPC_970 = 0x00390202, | |
7011 | #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31 | |
7012 | CPU_POWERPC_970FX_v10 = 0x00391100, | |
7013 | CPU_POWERPC_970FX_v20 = 0x003C0200, | |
7014 | CPU_POWERPC_970FX_v21 = 0x003C0201, | |
7015 | CPU_POWERPC_970FX_v30 = 0x003C0300, | |
7016 | CPU_POWERPC_970FX_v31 = 0x003C0301, | |
7017 | CPU_POWERPC_970GX = 0x00450000, | |
7018 | #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11 | |
7019 | CPU_POWERPC_970MP_v10 = 0x00440100, | |
7020 | CPU_POWERPC_970MP_v11 = 0x00440101, | |
7021 | #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32 | |
7022 | CPU_POWERPC_CELL_v10 = 0x00700100, | |
7023 | CPU_POWERPC_CELL_v20 = 0x00700400, | |
7024 | CPU_POWERPC_CELL_v30 = 0x00700500, | |
7025 | CPU_POWERPC_CELL_v31 = 0x00700501, | |
7026 | #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31 | |
7027 | CPU_POWERPC_RS64 = 0x00330000, | |
7028 | CPU_POWERPC_RS64II = 0x00340000, | |
7029 | CPU_POWERPC_RS64III = 0x00360000, | |
7030 | CPU_POWERPC_RS64IV = 0x00370000, | |
00af685f | 7031 | #endif /* defined(TARGET_PPC64) */ |
a750fc0b JM |
7032 | /* Original POWER */ |
7033 | /* XXX: should be POWER (RIOS), RSC3308, RSC4608, | |
7034 | * POWER2 (RIOS2) & RSC2 (P2SC) here | |
7035 | */ | |
7036 | #if 0 | |
80d11f44 | 7037 | CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */ |
a750fc0b JM |
7038 | #endif |
7039 | #if 0 | |
80d11f44 | 7040 | CPU_POWER2 = xxx, /* 0x40000 ? */ |
a750fc0b JM |
7041 | #endif |
7042 | /* PA Semi core */ | |
80d11f44 | 7043 | CPU_POWERPC_PA6T = 0x00900000, |
a750fc0b JM |
7044 | }; |
7045 | ||
7046 | /* System version register (used on MPC 8xxx) */ | |
7047 | enum { | |
80d11f44 JM |
7048 | POWERPC_SVR_NONE = 0x00000000, |
7049 | #define POWERPC_SVR_52xx POWERPC_SVR_5200 | |
7050 | #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12 | |
7051 | POWERPC_SVR_5200_v10 = 0x80110010, | |
7052 | POWERPC_SVR_5200_v11 = 0x80110011, | |
7053 | POWERPC_SVR_5200_v12 = 0x80110012, | |
7054 | #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21 | |
7055 | POWERPC_SVR_5200B_v20 = 0x80110020, | |
7056 | POWERPC_SVR_5200B_v21 = 0x80110021, | |
7057 | #define POWERPC_SVR_55xx POWERPC_SVR_5567 | |
c3e36823 | 7058 | #if 0 |
80d11f44 | 7059 | POWERPC_SVR_5533 = xxx, |
c3e36823 JM |
7060 | #endif |
7061 | #if 0 | |
80d11f44 | 7062 | POWERPC_SVR_5534 = xxx, |
c3e36823 JM |
7063 | #endif |
7064 | #if 0 | |
80d11f44 | 7065 | POWERPC_SVR_5553 = xxx, |
c3e36823 JM |
7066 | #endif |
7067 | #if 0 | |
80d11f44 | 7068 | POWERPC_SVR_5554 = xxx, |
c3e36823 JM |
7069 | #endif |
7070 | #if 0 | |
80d11f44 | 7071 | POWERPC_SVR_5561 = xxx, |
c3e36823 JM |
7072 | #endif |
7073 | #if 0 | |
80d11f44 | 7074 | POWERPC_SVR_5565 = xxx, |
c3e36823 JM |
7075 | #endif |
7076 | #if 0 | |
80d11f44 | 7077 | POWERPC_SVR_5566 = xxx, |
c3e36823 JM |
7078 | #endif |
7079 | #if 0 | |
80d11f44 | 7080 | POWERPC_SVR_5567 = xxx, |
c3e36823 JM |
7081 | #endif |
7082 | #if 0 | |
80d11f44 | 7083 | POWERPC_SVR_8313 = xxx, |
c3e36823 JM |
7084 | #endif |
7085 | #if 0 | |
80d11f44 | 7086 | POWERPC_SVR_8313E = xxx, |
c3e36823 JM |
7087 | #endif |
7088 | #if 0 | |
80d11f44 | 7089 | POWERPC_SVR_8314 = xxx, |
c3e36823 JM |
7090 | #endif |
7091 | #if 0 | |
80d11f44 | 7092 | POWERPC_SVR_8314E = xxx, |
c3e36823 JM |
7093 | #endif |
7094 | #if 0 | |
80d11f44 | 7095 | POWERPC_SVR_8315 = xxx, |
c3e36823 JM |
7096 | #endif |
7097 | #if 0 | |
80d11f44 | 7098 | POWERPC_SVR_8315E = xxx, |
c3e36823 JM |
7099 | #endif |
7100 | #if 0 | |
80d11f44 | 7101 | POWERPC_SVR_8321 = xxx, |
c3e36823 JM |
7102 | #endif |
7103 | #if 0 | |
80d11f44 | 7104 | POWERPC_SVR_8321E = xxx, |
c3e36823 JM |
7105 | #endif |
7106 | #if 0 | |
80d11f44 | 7107 | POWERPC_SVR_8323 = xxx, |
c3e36823 JM |
7108 | #endif |
7109 | #if 0 | |
80d11f44 JM |
7110 | POWERPC_SVR_8323E = xxx, |
7111 | #endif | |
7112 | POWERPC_SVR_8343A = 0x80570030, | |
7113 | POWERPC_SVR_8343EA = 0x80560030, | |
7114 | #define POWERPC_SVR_8347A POWERPC_SVR_8347AT | |
7115 | POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */ | |
7116 | POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */ | |
7117 | #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT | |
7118 | POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */ | |
7119 | POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */ | |
7120 | POWERPC_SVR_8349 = 0x80510010, | |
7121 | POWERPC_SVR_8349A = 0x80510030, | |
7122 | POWERPC_SVR_8349E = 0x80500010, | |
7123 | POWERPC_SVR_8349EA = 0x80500030, | |
c3e36823 | 7124 | #if 0 |
80d11f44 | 7125 | POWERPC_SVR_8358E = xxx, |
c3e36823 JM |
7126 | #endif |
7127 | #if 0 | |
80d11f44 JM |
7128 | POWERPC_SVR_8360E = xxx, |
7129 | #endif | |
7130 | #define POWERPC_SVR_E500 0x40000000 | |
7131 | POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500, | |
7132 | POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500, | |
7133 | POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500, | |
7134 | POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500, | |
7135 | POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500, | |
7136 | POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500, | |
7137 | #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11 | |
7138 | POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500, | |
7139 | POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500, | |
7140 | #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11 | |
7141 | POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500, | |
7142 | POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500, | |
7143 | #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21 | |
7144 | POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500, | |
7145 | POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500, | |
7146 | POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500, | |
7147 | #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11 | |
7148 | POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500, | |
7149 | POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500, | |
7150 | #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11 | |
7151 | POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500, | |
7152 | POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500, | |
7153 | #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21 | |
7154 | POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500, | |
7155 | POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500, | |
7156 | POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500, | |
7157 | POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500, | |
7158 | #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21 | |
7159 | POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500, | |
7160 | POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500, | |
7161 | POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500, | |
7162 | POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500, | |
7163 | #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11 | |
7164 | POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500, | |
7165 | POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500, | |
7166 | #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11 | |
7167 | POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500, | |
7168 | POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500, | |
7169 | #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21 | |
7170 | POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500, | |
7171 | POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500, | |
7172 | #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21 | |
7173 | POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500, | |
7174 | POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500, | |
7175 | #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21 | |
7176 | POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500, | |
7177 | POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500, | |
7178 | #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21 | |
7179 | POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500, | |
7180 | POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500, | |
7181 | POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500, | |
7182 | POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500, | |
7183 | #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21 | |
7184 | POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500, | |
7185 | POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500, | |
7186 | POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500, | |
7187 | POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500, | |
7188 | #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11 | |
7189 | POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500, | |
7190 | POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500, | |
7191 | #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11 | |
7192 | POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500, | |
7193 | POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500, | |
7194 | #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21 | |
7195 | POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500, | |
7196 | POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500, | |
7197 | POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500, | |
7198 | POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500, | |
7199 | POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500, | |
7200 | POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500, | |
7201 | POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500, | |
7202 | POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500, | |
7203 | POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500, | |
c3e36823 | 7204 | #if 0 |
80d11f44 | 7205 | POWERPC_SVR_8610 = xxx, |
c3e36823 | 7206 | #endif |
80d11f44 JM |
7207 | POWERPC_SVR_8641 = 0x80900021, |
7208 | POWERPC_SVR_8641D = 0x80900121, | |
a750fc0b JM |
7209 | }; |
7210 | ||
3fc6c082 | 7211 | /*****************************************************************************/ |
a750fc0b | 7212 | /* PowerPC CPU definitions */ |
80d11f44 | 7213 | #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \ |
a750fc0b JM |
7214 | { \ |
7215 | .name = _name, \ | |
7216 | .pvr = _pvr, \ | |
80d11f44 | 7217 | .svr = _svr, \ |
a750fc0b JM |
7218 | .insns_flags = glue(POWERPC_INSNS_,_type), \ |
7219 | .msr_mask = glue(POWERPC_MSRM_,_type), \ | |
7220 | .mmu_model = glue(POWERPC_MMU_,_type), \ | |
7221 | .excp_model = glue(POWERPC_EXCP_,_type), \ | |
7222 | .bus_model = glue(POWERPC_INPUT_,_type), \ | |
237c0af0 | 7223 | .bfd_mach = glue(POWERPC_BFDM_,_type), \ |
d26bfc9a | 7224 | .flags = glue(POWERPC_FLAG_,_type), \ |
a750fc0b | 7225 | .init_proc = &glue(init_proc_,_type), \ |
2f462816 | 7226 | .check_pow = &glue(check_pow_,_type), \ |
a750fc0b | 7227 | } |
80d11f44 JM |
7228 | #define POWERPC_DEF(_name, _pvr, _type) \ |
7229 | POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type) | |
a750fc0b | 7230 | |
ee4e83ed | 7231 | static const ppc_def_t ppc_defs[] = { |
a750fc0b JM |
7232 | /* Embedded PowerPC */ |
7233 | /* PowerPC 401 family */ | |
2662a059 | 7234 | /* Generic PowerPC 401 */ |
80d11f44 | 7235 | POWERPC_DEF("401", CPU_POWERPC_401, 401), |
a750fc0b | 7236 | /* PowerPC 401 cores */ |
2662a059 | 7237 | /* PowerPC 401A1 */ |
80d11f44 | 7238 | POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401), |
a750fc0b | 7239 | /* PowerPC 401B2 */ |
80d11f44 | 7240 | POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2), |
2662a059 | 7241 | #if defined (TODO) |
a750fc0b | 7242 | /* PowerPC 401B3 */ |
80d11f44 | 7243 | POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3), |
a750fc0b JM |
7244 | #endif |
7245 | /* PowerPC 401C2 */ | |
80d11f44 | 7246 | POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2), |
a750fc0b | 7247 | /* PowerPC 401D2 */ |
80d11f44 | 7248 | POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2), |
a750fc0b | 7249 | /* PowerPC 401E2 */ |
80d11f44 | 7250 | POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2), |
a750fc0b | 7251 | /* PowerPC 401F2 */ |
80d11f44 | 7252 | POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2), |
a750fc0b JM |
7253 | /* PowerPC 401G2 */ |
7254 | /* XXX: to be checked */ | |
80d11f44 | 7255 | POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2), |
a750fc0b | 7256 | /* PowerPC 401 microcontrolers */ |
2662a059 | 7257 | #if defined (TODO) |
a750fc0b | 7258 | /* PowerPC 401GF */ |
80d11f44 | 7259 | POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401), |
3fc6c082 | 7260 | #endif |
a750fc0b | 7261 | /* IOP480 (401 microcontroler) */ |
80d11f44 | 7262 | POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480), |
a750fc0b | 7263 | /* IBM Processor for Network Resources */ |
80d11f44 | 7264 | POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401), |
3fc6c082 | 7265 | #if defined (TODO) |
80d11f44 | 7266 | POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401), |
3fc6c082 | 7267 | #endif |
a750fc0b JM |
7268 | /* PowerPC 403 family */ |
7269 | /* Generic PowerPC 403 */ | |
80d11f44 | 7270 | POWERPC_DEF("403", CPU_POWERPC_403, 403), |
a750fc0b JM |
7271 | /* PowerPC 403 microcontrolers */ |
7272 | /* PowerPC 403 GA */ | |
80d11f44 | 7273 | POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403), |
a750fc0b | 7274 | /* PowerPC 403 GB */ |
80d11f44 | 7275 | POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403), |
a750fc0b | 7276 | /* PowerPC 403 GC */ |
80d11f44 | 7277 | POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403), |
a750fc0b | 7278 | /* PowerPC 403 GCX */ |
80d11f44 | 7279 | POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX), |
3fc6c082 | 7280 | #if defined (TODO) |
a750fc0b | 7281 | /* PowerPC 403 GP */ |
80d11f44 | 7282 | POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403), |
3fc6c082 | 7283 | #endif |
a750fc0b JM |
7284 | /* PowerPC 405 family */ |
7285 | /* Generic PowerPC 405 */ | |
80d11f44 | 7286 | POWERPC_DEF("405", CPU_POWERPC_405, 405), |
a750fc0b | 7287 | /* PowerPC 405 cores */ |
2662a059 | 7288 | #if defined (TODO) |
a750fc0b | 7289 | /* PowerPC 405 A3 */ |
80d11f44 | 7290 | POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405), |
3a607854 | 7291 | #endif |
3a607854 | 7292 | #if defined (TODO) |
a750fc0b | 7293 | /* PowerPC 405 A4 */ |
80d11f44 | 7294 | POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405), |
3a607854 | 7295 | #endif |
3a607854 | 7296 | #if defined (TODO) |
a750fc0b | 7297 | /* PowerPC 405 B3 */ |
80d11f44 | 7298 | POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405), |
3fc6c082 FB |
7299 | #endif |
7300 | #if defined (TODO) | |
a750fc0b | 7301 | /* PowerPC 405 B4 */ |
80d11f44 | 7302 | POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405), |
a750fc0b JM |
7303 | #endif |
7304 | #if defined (TODO) | |
7305 | /* PowerPC 405 C3 */ | |
80d11f44 | 7306 | POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405), |
a750fc0b JM |
7307 | #endif |
7308 | #if defined (TODO) | |
7309 | /* PowerPC 405 C4 */ | |
80d11f44 | 7310 | POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405), |
a750fc0b JM |
7311 | #endif |
7312 | /* PowerPC 405 D2 */ | |
80d11f44 | 7313 | POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405), |
a750fc0b JM |
7314 | #if defined (TODO) |
7315 | /* PowerPC 405 D3 */ | |
80d11f44 | 7316 | POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405), |
a750fc0b JM |
7317 | #endif |
7318 | /* PowerPC 405 D4 */ | |
80d11f44 | 7319 | POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405), |
a750fc0b JM |
7320 | #if defined (TODO) |
7321 | /* PowerPC 405 D5 */ | |
80d11f44 | 7322 | POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405), |
a750fc0b JM |
7323 | #endif |
7324 | #if defined (TODO) | |
7325 | /* PowerPC 405 E4 */ | |
80d11f44 | 7326 | POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405), |
a750fc0b JM |
7327 | #endif |
7328 | #if defined (TODO) | |
7329 | /* PowerPC 405 F4 */ | |
80d11f44 | 7330 | POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405), |
a750fc0b JM |
7331 | #endif |
7332 | #if defined (TODO) | |
7333 | /* PowerPC 405 F5 */ | |
80d11f44 | 7334 | POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405), |
a750fc0b JM |
7335 | #endif |
7336 | #if defined (TODO) | |
7337 | /* PowerPC 405 F6 */ | |
80d11f44 | 7338 | POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405), |
a750fc0b JM |
7339 | #endif |
7340 | /* PowerPC 405 microcontrolers */ | |
7341 | /* PowerPC 405 CR */ | |
80d11f44 | 7342 | POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405), |
a750fc0b | 7343 | /* PowerPC 405 CRa */ |
80d11f44 | 7344 | POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405), |
a750fc0b | 7345 | /* PowerPC 405 CRb */ |
80d11f44 | 7346 | POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405), |
a750fc0b | 7347 | /* PowerPC 405 CRc */ |
80d11f44 | 7348 | POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405), |
a750fc0b | 7349 | /* PowerPC 405 EP */ |
80d11f44 | 7350 | POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405), |
a750fc0b JM |
7351 | #if defined(TODO) |
7352 | /* PowerPC 405 EXr */ | |
80d11f44 | 7353 | POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405), |
a750fc0b JM |
7354 | #endif |
7355 | /* PowerPC 405 EZ */ | |
80d11f44 | 7356 | POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405), |
a750fc0b JM |
7357 | #if defined(TODO) |
7358 | /* PowerPC 405 FX */ | |
80d11f44 | 7359 | POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405), |
a750fc0b JM |
7360 | #endif |
7361 | /* PowerPC 405 GP */ | |
80d11f44 | 7362 | POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405), |
a750fc0b | 7363 | /* PowerPC 405 GPa */ |
80d11f44 | 7364 | POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405), |
a750fc0b | 7365 | /* PowerPC 405 GPb */ |
80d11f44 | 7366 | POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405), |
a750fc0b | 7367 | /* PowerPC 405 GPc */ |
80d11f44 | 7368 | POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405), |
a750fc0b | 7369 | /* PowerPC 405 GPd */ |
80d11f44 | 7370 | POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405), |
a750fc0b | 7371 | /* PowerPC 405 GPe */ |
80d11f44 | 7372 | POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405), |
a750fc0b | 7373 | /* PowerPC 405 GPR */ |
80d11f44 | 7374 | POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405), |
a750fc0b JM |
7375 | #if defined(TODO) |
7376 | /* PowerPC 405 H */ | |
80d11f44 | 7377 | POWERPC_DEF("405H", CPU_POWERPC_405H, 405), |
a750fc0b JM |
7378 | #endif |
7379 | #if defined(TODO) | |
7380 | /* PowerPC 405 L */ | |
80d11f44 | 7381 | POWERPC_DEF("405L", CPU_POWERPC_405L, 405), |
a750fc0b JM |
7382 | #endif |
7383 | /* PowerPC 405 LP */ | |
80d11f44 | 7384 | POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405), |
a750fc0b JM |
7385 | #if defined(TODO) |
7386 | /* PowerPC 405 PM */ | |
80d11f44 | 7387 | POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405), |
a750fc0b JM |
7388 | #endif |
7389 | #if defined(TODO) | |
7390 | /* PowerPC 405 PS */ | |
80d11f44 | 7391 | POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405), |
a750fc0b JM |
7392 | #endif |
7393 | #if defined(TODO) | |
7394 | /* PowerPC 405 S */ | |
80d11f44 | 7395 | POWERPC_DEF("405S", CPU_POWERPC_405S, 405), |
a750fc0b JM |
7396 | #endif |
7397 | /* Npe405 H */ | |
80d11f44 | 7398 | POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405), |
a750fc0b | 7399 | /* Npe405 H2 */ |
80d11f44 | 7400 | POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405), |
a750fc0b | 7401 | /* Npe405 L */ |
80d11f44 | 7402 | POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405), |
a750fc0b | 7403 | /* Npe4GS3 */ |
80d11f44 | 7404 | POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405), |
a750fc0b | 7405 | #if defined (TODO) |
80d11f44 | 7406 | POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405), |
a750fc0b JM |
7407 | #endif |
7408 | #if defined (TODO) | |
80d11f44 | 7409 | POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405), |
a750fc0b JM |
7410 | #endif |
7411 | #if defined (TODO) | |
7412 | /* PowerPC LC77700 (Sanyo) */ | |
80d11f44 | 7413 | POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405), |
a750fc0b JM |
7414 | #endif |
7415 | /* PowerPC 401/403/405 based set-top-box microcontrolers */ | |
7416 | #if defined (TODO) | |
7417 | /* STB010000 */ | |
80d11f44 | 7418 | POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2), |
a750fc0b JM |
7419 | #endif |
7420 | #if defined (TODO) | |
7421 | /* STB01010 */ | |
80d11f44 | 7422 | POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2), |
a750fc0b JM |
7423 | #endif |
7424 | #if defined (TODO) | |
7425 | /* STB0210 */ | |
80d11f44 | 7426 | POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3), |
a750fc0b JM |
7427 | #endif |
7428 | /* STB03xx */ | |
80d11f44 | 7429 | POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405), |
a750fc0b JM |
7430 | #if defined (TODO) |
7431 | /* STB043x */ | |
80d11f44 | 7432 | POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405), |
a750fc0b JM |
7433 | #endif |
7434 | #if defined (TODO) | |
7435 | /* STB045x */ | |
80d11f44 | 7436 | POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405), |
a750fc0b JM |
7437 | #endif |
7438 | /* STB04xx */ | |
80d11f44 | 7439 | POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405), |
a750fc0b | 7440 | /* STB25xx */ |
80d11f44 | 7441 | POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405), |
a750fc0b JM |
7442 | #if defined (TODO) |
7443 | /* STB130 */ | |
80d11f44 | 7444 | POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405), |
a750fc0b JM |
7445 | #endif |
7446 | /* Xilinx PowerPC 405 cores */ | |
80d11f44 JM |
7447 | POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405), |
7448 | POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405), | |
7449 | POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405), | |
7450 | POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405), | |
a750fc0b JM |
7451 | #if defined (TODO) |
7452 | /* Zarlink ZL10310 */ | |
80d11f44 | 7453 | POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405), |
a750fc0b JM |
7454 | #endif |
7455 | #if defined (TODO) | |
7456 | /* Zarlink ZL10311 */ | |
80d11f44 | 7457 | POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405), |
a750fc0b JM |
7458 | #endif |
7459 | #if defined (TODO) | |
7460 | /* Zarlink ZL10320 */ | |
80d11f44 | 7461 | POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405), |
a750fc0b JM |
7462 | #endif |
7463 | #if defined (TODO) | |
7464 | /* Zarlink ZL10321 */ | |
80d11f44 | 7465 | POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405), |
a750fc0b JM |
7466 | #endif |
7467 | /* PowerPC 440 family */ | |
80d11f44 | 7468 | #if defined(TODO_USER_ONLY) |
a750fc0b | 7469 | /* Generic PowerPC 440 */ |
80d11f44 JM |
7470 | POWERPC_DEF("440", CPU_POWERPC_440, 440GP), |
7471 | #endif | |
a750fc0b JM |
7472 | /* PowerPC 440 cores */ |
7473 | #if defined (TODO) | |
7474 | /* PowerPC 440 A4 */ | |
80d11f44 | 7475 | POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4), |
a750fc0b JM |
7476 | #endif |
7477 | #if defined (TODO) | |
7478 | /* PowerPC 440 A5 */ | |
80d11f44 | 7479 | POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5), |
a750fc0b JM |
7480 | #endif |
7481 | #if defined (TODO) | |
7482 | /* PowerPC 440 B4 */ | |
80d11f44 | 7483 | POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4), |
a750fc0b JM |
7484 | #endif |
7485 | #if defined (TODO) | |
7486 | /* PowerPC 440 G4 */ | |
80d11f44 | 7487 | POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4), |
a750fc0b JM |
7488 | #endif |
7489 | #if defined (TODO) | |
7490 | /* PowerPC 440 F5 */ | |
80d11f44 | 7491 | POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5), |
a750fc0b JM |
7492 | #endif |
7493 | #if defined (TODO) | |
7494 | /* PowerPC 440 G5 */ | |
80d11f44 | 7495 | POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5), |
a750fc0b JM |
7496 | #endif |
7497 | #if defined (TODO) | |
7498 | /* PowerPC 440H4 */ | |
80d11f44 | 7499 | POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4), |
a750fc0b JM |
7500 | #endif |
7501 | #if defined (TODO) | |
7502 | /* PowerPC 440H6 */ | |
80d11f44 | 7503 | POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5), |
a750fc0b JM |
7504 | #endif |
7505 | /* PowerPC 440 microcontrolers */ | |
80d11f44 | 7506 | #if defined(TODO_USER_ONLY) |
a750fc0b | 7507 | /* PowerPC 440 EP */ |
80d11f44 JM |
7508 | POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP), |
7509 | #endif | |
7510 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7511 | /* PowerPC 440 EPa */ |
80d11f44 JM |
7512 | POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP), |
7513 | #endif | |
7514 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7515 | /* PowerPC 440 EPb */ |
80d11f44 JM |
7516 | POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP), |
7517 | #endif | |
7518 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7519 | /* PowerPC 440 EPX */ |
80d11f44 JM |
7520 | POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP), |
7521 | #endif | |
7522 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7523 | /* PowerPC 440 GP */ |
80d11f44 JM |
7524 | POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP), |
7525 | #endif | |
7526 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7527 | /* PowerPC 440 GPb */ |
80d11f44 JM |
7528 | POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP), |
7529 | #endif | |
7530 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7531 | /* PowerPC 440 GPc */ |
80d11f44 JM |
7532 | POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP), |
7533 | #endif | |
7534 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7535 | /* PowerPC 440 GR */ |
80d11f44 JM |
7536 | POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5), |
7537 | #endif | |
7538 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7539 | /* PowerPC 440 GRa */ |
80d11f44 JM |
7540 | POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5), |
7541 | #endif | |
7542 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7543 | /* PowerPC 440 GRX */ |
80d11f44 JM |
7544 | POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5), |
7545 | #endif | |
7546 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7547 | /* PowerPC 440 GX */ |
80d11f44 JM |
7548 | POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP), |
7549 | #endif | |
7550 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7551 | /* PowerPC 440 GXa */ |
80d11f44 JM |
7552 | POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP), |
7553 | #endif | |
7554 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7555 | /* PowerPC 440 GXb */ |
80d11f44 JM |
7556 | POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP), |
7557 | #endif | |
7558 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7559 | /* PowerPC 440 GXc */ |
80d11f44 JM |
7560 | POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP), |
7561 | #endif | |
7562 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7563 | /* PowerPC 440 GXf */ |
80d11f44 JM |
7564 | POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP), |
7565 | #endif | |
a750fc0b JM |
7566 | #if defined(TODO) |
7567 | /* PowerPC 440 S */ | |
80d11f44 | 7568 | POWERPC_DEF("440S", CPU_POWERPC_440S, 440), |
a750fc0b | 7569 | #endif |
80d11f44 | 7570 | #if defined(TODO_USER_ONLY) |
a750fc0b | 7571 | /* PowerPC 440 SP */ |
80d11f44 JM |
7572 | POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP), |
7573 | #endif | |
7574 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7575 | /* PowerPC 440 SP2 */ |
80d11f44 JM |
7576 | POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP), |
7577 | #endif | |
7578 | #if defined(TODO_USER_ONLY) | |
a750fc0b | 7579 | /* PowerPC 440 SPE */ |
80d11f44 JM |
7580 | POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP), |
7581 | #endif | |
a750fc0b JM |
7582 | /* PowerPC 460 family */ |
7583 | #if defined (TODO) | |
7584 | /* Generic PowerPC 464 */ | |
80d11f44 | 7585 | POWERPC_DEF("464", CPU_POWERPC_464, 460), |
a750fc0b JM |
7586 | #endif |
7587 | /* PowerPC 464 microcontrolers */ | |
7588 | #if defined (TODO) | |
7589 | /* PowerPC 464H90 */ | |
80d11f44 | 7590 | POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460), |
a750fc0b JM |
7591 | #endif |
7592 | #if defined (TODO) | |
7593 | /* PowerPC 464H90F */ | |
80d11f44 | 7594 | POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F), |
a750fc0b JM |
7595 | #endif |
7596 | /* Freescale embedded PowerPC cores */ | |
80d11f44 JM |
7597 | /* MPC5xx family (aka RCPU) */ |
7598 | #if defined(TODO_USER_ONLY) | |
7599 | /* Generic MPC5xx core */ | |
7600 | POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx), | |
7601 | #endif | |
7602 | #if defined(TODO_USER_ONLY) | |
7603 | /* Codename for MPC5xx core */ | |
7604 | POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx), | |
7605 | #endif | |
7606 | /* MPC5xx microcontrollers */ | |
7607 | #if defined(TODO_USER_ONLY) | |
7608 | /* MGT560 */ | |
7609 | POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx), | |
7610 | #endif | |
7611 | #if defined(TODO_USER_ONLY) | |
7612 | /* MPC509 */ | |
7613 | POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx), | |
7614 | #endif | |
7615 | #if defined(TODO_USER_ONLY) | |
7616 | /* MPC533 */ | |
7617 | POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx), | |
7618 | #endif | |
7619 | #if defined(TODO_USER_ONLY) | |
7620 | /* MPC534 */ | |
7621 | POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx), | |
7622 | #endif | |
7623 | #if defined(TODO_USER_ONLY) | |
7624 | /* MPC555 */ | |
7625 | POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx), | |
7626 | #endif | |
7627 | #if defined(TODO_USER_ONLY) | |
7628 | /* MPC556 */ | |
7629 | POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx), | |
7630 | #endif | |
7631 | #if defined(TODO_USER_ONLY) | |
7632 | /* MPC560 */ | |
7633 | POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx), | |
7634 | #endif | |
7635 | #if defined(TODO_USER_ONLY) | |
7636 | /* MPC561 */ | |
7637 | POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx), | |
7638 | #endif | |
7639 | #if defined(TODO_USER_ONLY) | |
7640 | /* MPC562 */ | |
7641 | POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx), | |
7642 | #endif | |
7643 | #if defined(TODO_USER_ONLY) | |
7644 | /* MPC563 */ | |
7645 | POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx), | |
7646 | #endif | |
7647 | #if defined(TODO_USER_ONLY) | |
7648 | /* MPC564 */ | |
7649 | POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx), | |
7650 | #endif | |
7651 | #if defined(TODO_USER_ONLY) | |
7652 | /* MPC565 */ | |
7653 | POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx), | |
7654 | #endif | |
7655 | #if defined(TODO_USER_ONLY) | |
7656 | /* MPC566 */ | |
7657 | POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx), | |
7658 | #endif | |
7659 | /* MPC8xx family (aka PowerQUICC) */ | |
7660 | #if defined(TODO_USER_ONLY) | |
7661 | /* Generic MPC8xx core */ | |
7662 | POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx), | |
7663 | #endif | |
7664 | #if defined(TODO_USER_ONLY) | |
7665 | /* Codename for MPC8xx core */ | |
7666 | POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx), | |
7667 | #endif | |
7668 | /* MPC8xx microcontrollers */ | |
7669 | #if defined(TODO_USER_ONLY) | |
7670 | /* MGT823 */ | |
7671 | POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx), | |
7672 | #endif | |
7673 | #if defined(TODO_USER_ONLY) | |
7674 | /* MPC821 */ | |
7675 | POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx), | |
7676 | #endif | |
7677 | #if defined(TODO_USER_ONLY) | |
7678 | /* MPC823 */ | |
7679 | POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx), | |
7680 | #endif | |
7681 | #if defined(TODO_USER_ONLY) | |
7682 | /* MPC850 */ | |
7683 | POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx), | |
7684 | #endif | |
7685 | #if defined(TODO_USER_ONLY) | |
7686 | /* MPC852T */ | |
7687 | POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx), | |
7688 | #endif | |
7689 | #if defined(TODO_USER_ONLY) | |
7690 | /* MPC855T */ | |
7691 | POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx), | |
7692 | #endif | |
7693 | #if defined(TODO_USER_ONLY) | |
7694 | /* MPC857 */ | |
7695 | POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx), | |
7696 | #endif | |
7697 | #if defined(TODO_USER_ONLY) | |
7698 | /* MPC859 */ | |
7699 | POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx), | |
7700 | #endif | |
7701 | #if defined(TODO_USER_ONLY) | |
7702 | /* MPC860 */ | |
7703 | POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx), | |
7704 | #endif | |
7705 | #if defined(TODO_USER_ONLY) | |
7706 | /* MPC862 */ | |
7707 | POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx), | |
7708 | #endif | |
7709 | #if defined(TODO_USER_ONLY) | |
7710 | /* MPC866 */ | |
7711 | POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx), | |
7712 | #endif | |
7713 | #if defined(TODO_USER_ONLY) | |
7714 | /* MPC870 */ | |
7715 | POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx), | |
7716 | #endif | |
7717 | #if defined(TODO_USER_ONLY) | |
7718 | /* MPC875 */ | |
7719 | POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx), | |
7720 | #endif | |
7721 | #if defined(TODO_USER_ONLY) | |
7722 | /* MPC880 */ | |
7723 | POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx), | |
7724 | #endif | |
7725 | #if defined(TODO_USER_ONLY) | |
7726 | /* MPC885 */ | |
7727 | POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx), | |
7728 | #endif | |
7729 | /* MPC82xx family (aka PowerQUICC-II) */ | |
7730 | /* Generic MPC52xx core */ | |
7731 | POWERPC_DEF_SVR("MPC52xx", | |
7732 | CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE), | |
7733 | /* Generic MPC82xx core */ | |
7734 | POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2), | |
7735 | /* Codename for MPC82xx */ | |
7736 | POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2), | |
7737 | /* PowerPC G2 core */ | |
7738 | POWERPC_DEF("G2", CPU_POWERPC_G2, G2), | |
7739 | /* PowerPC G2 H4 core */ | |
7740 | POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2), | |
7741 | /* PowerPC G2 GP core */ | |
7742 | POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2), | |
7743 | /* PowerPC G2 LS core */ | |
7744 | POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2), | |
7745 | /* PowerPC G2 HiP3 core */ | |
7746 | POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2), | |
7747 | /* PowerPC G2 HiP4 core */ | |
7748 | POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2), | |
7749 | /* PowerPC MPC603 core */ | |
7750 | POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E), | |
7751 | /* PowerPC G2le core (same as G2 plus little-endian mode support) */ | |
7752 | POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE), | |
7753 | /* PowerPC G2LE GP core */ | |
7754 | POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE), | |
7755 | /* PowerPC G2LE LS core */ | |
7756 | POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE), | |
7757 | /* PowerPC G2LE GP1 core */ | |
7758 | POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE), | |
7759 | /* PowerPC G2LE GP3 core */ | |
7760 | POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE), | |
7761 | /* PowerPC MPC603 microcontrollers */ | |
7762 | /* MPC8240 */ | |
7763 | POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E), | |
7764 | /* PowerPC G2 microcontrollers */ | |
082c6681 | 7765 | #if defined(TODO) |
80d11f44 JM |
7766 | /* MPC5121 */ |
7767 | POWERPC_DEF_SVR("MPC5121", | |
7768 | CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE), | |
7769 | #endif | |
7770 | /* MPC5200 */ | |
7771 | POWERPC_DEF_SVR("MPC5200", | |
7772 | CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE), | |
7773 | /* MPC5200 v1.0 */ | |
7774 | POWERPC_DEF_SVR("MPC5200_v10", | |
7775 | CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE), | |
7776 | /* MPC5200 v1.1 */ | |
7777 | POWERPC_DEF_SVR("MPC5200_v11", | |
7778 | CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE), | |
7779 | /* MPC5200 v1.2 */ | |
7780 | POWERPC_DEF_SVR("MPC5200_v12", | |
7781 | CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE), | |
7782 | /* MPC5200B */ | |
7783 | POWERPC_DEF_SVR("MPC5200B", | |
7784 | CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE), | |
7785 | /* MPC5200B v2.0 */ | |
7786 | POWERPC_DEF_SVR("MPC5200B_v20", | |
7787 | CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE), | |
7788 | /* MPC5200B v2.1 */ | |
7789 | POWERPC_DEF_SVR("MPC5200B_v21", | |
7790 | CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE), | |
7791 | /* MPC8241 */ | |
7792 | POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2), | |
7793 | /* MPC8245 */ | |
7794 | POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2), | |
7795 | /* MPC8247 */ | |
7796 | POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE), | |
7797 | /* MPC8248 */ | |
7798 | POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE), | |
7799 | /* MPC8250 */ | |
7800 | POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2), | |
7801 | /* MPC8250 HiP3 */ | |
7802 | POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2), | |
7803 | /* MPC8250 HiP4 */ | |
7804 | POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2), | |
7805 | /* MPC8255 */ | |
7806 | POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2), | |
7807 | /* MPC8255 HiP3 */ | |
7808 | POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2), | |
7809 | /* MPC8255 HiP4 */ | |
7810 | POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2), | |
7811 | /* MPC8260 */ | |
7812 | POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2), | |
7813 | /* MPC8260 HiP3 */ | |
7814 | POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2), | |
7815 | /* MPC8260 HiP4 */ | |
7816 | POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2), | |
7817 | /* MPC8264 */ | |
7818 | POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2), | |
7819 | /* MPC8264 HiP3 */ | |
7820 | POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2), | |
7821 | /* MPC8264 HiP4 */ | |
7822 | POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2), | |
7823 | /* MPC8265 */ | |
7824 | POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2), | |
7825 | /* MPC8265 HiP3 */ | |
7826 | POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2), | |
7827 | /* MPC8265 HiP4 */ | |
7828 | POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2), | |
7829 | /* MPC8266 */ | |
7830 | POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2), | |
7831 | /* MPC8266 HiP3 */ | |
7832 | POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2), | |
7833 | /* MPC8266 HiP4 */ | |
7834 | POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2), | |
7835 | /* MPC8270 */ | |
7836 | POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE), | |
7837 | /* MPC8271 */ | |
7838 | POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE), | |
7839 | /* MPC8272 */ | |
7840 | POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE), | |
7841 | /* MPC8275 */ | |
7842 | POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE), | |
7843 | /* MPC8280 */ | |
7844 | POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE), | |
a750fc0b | 7845 | /* e200 family */ |
a750fc0b | 7846 | /* Generic PowerPC e200 core */ |
80d11f44 JM |
7847 | POWERPC_DEF("e200", CPU_POWERPC_e200, e200), |
7848 | /* Generic MPC55xx core */ | |
7849 | #if defined (TODO) | |
7850 | POWERPC_DEF_SVR("MPC55xx", | |
7851 | CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200), | |
a750fc0b JM |
7852 | #endif |
7853 | #if defined (TODO) | |
80d11f44 JM |
7854 | /* PowerPC e200z0 core */ |
7855 | POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200), | |
a750fc0b JM |
7856 | #endif |
7857 | #if defined (TODO) | |
80d11f44 JM |
7858 | /* PowerPC e200z1 core */ |
7859 | POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200), | |
7860 | #endif | |
7861 | #if defined (TODO) | |
7862 | /* PowerPC e200z3 core */ | |
7863 | POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200), | |
7864 | #endif | |
7865 | /* PowerPC e200z5 core */ | |
7866 | POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200), | |
a750fc0b | 7867 | /* PowerPC e200z6 core */ |
80d11f44 JM |
7868 | POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200), |
7869 | /* PowerPC e200 microcontrollers */ | |
7870 | #if defined (TODO) | |
7871 | /* MPC5514E */ | |
7872 | POWERPC_DEF_SVR("MPC5514E", | |
7873 | CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200), | |
a750fc0b | 7874 | #endif |
a750fc0b | 7875 | #if defined (TODO) |
80d11f44 JM |
7876 | /* MPC5514E v0 */ |
7877 | POWERPC_DEF_SVR("MPC5514E_v0", | |
7878 | CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200), | |
a750fc0b JM |
7879 | #endif |
7880 | #if defined (TODO) | |
80d11f44 JM |
7881 | /* MPC5514E v1 */ |
7882 | POWERPC_DEF_SVR("MPC5514E_v1", | |
7883 | CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200), | |
a750fc0b JM |
7884 | #endif |
7885 | #if defined (TODO) | |
80d11f44 JM |
7886 | /* MPC5514G */ |
7887 | POWERPC_DEF_SVR("MPC5514G", | |
7888 | CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200), | |
a750fc0b JM |
7889 | #endif |
7890 | #if defined (TODO) | |
80d11f44 JM |
7891 | /* MPC5514G v0 */ |
7892 | POWERPC_DEF_SVR("MPC5514G_v0", | |
7893 | CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200), | |
a750fc0b | 7894 | #endif |
a750fc0b | 7895 | #if defined (TODO) |
80d11f44 JM |
7896 | /* MPC5514G v1 */ |
7897 | POWERPC_DEF_SVR("MPC5514G_v1", | |
7898 | CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200), | |
a750fc0b JM |
7899 | #endif |
7900 | #if defined (TODO) | |
80d11f44 JM |
7901 | /* MPC5515S */ |
7902 | POWERPC_DEF_SVR("MPC5515S", | |
7903 | CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200), | |
a750fc0b JM |
7904 | #endif |
7905 | #if defined (TODO) | |
80d11f44 JM |
7906 | /* MPC5516E */ |
7907 | POWERPC_DEF_SVR("MPC5516E", | |
7908 | CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200), | |
a750fc0b JM |
7909 | #endif |
7910 | #if defined (TODO) | |
80d11f44 JM |
7911 | /* MPC5516E v0 */ |
7912 | POWERPC_DEF_SVR("MPC5516E_v0", | |
7913 | CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200), | |
a750fc0b JM |
7914 | #endif |
7915 | #if defined (TODO) | |
80d11f44 JM |
7916 | /* MPC5516E v1 */ |
7917 | POWERPC_DEF_SVR("MPC5516E_v1", | |
7918 | CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200), | |
a750fc0b | 7919 | #endif |
a750fc0b | 7920 | #if defined (TODO) |
80d11f44 JM |
7921 | /* MPC5516G */ |
7922 | POWERPC_DEF_SVR("MPC5516G", | |
7923 | CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200), | |
a750fc0b | 7924 | #endif |
a750fc0b | 7925 | #if defined (TODO) |
80d11f44 JM |
7926 | /* MPC5516G v0 */ |
7927 | POWERPC_DEF_SVR("MPC5516G_v0", | |
7928 | CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200), | |
a750fc0b | 7929 | #endif |
a750fc0b | 7930 | #if defined (TODO) |
80d11f44 JM |
7931 | /* MPC5516G v1 */ |
7932 | POWERPC_DEF_SVR("MPC5516G_v1", | |
7933 | CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200), | |
a750fc0b | 7934 | #endif |
a750fc0b | 7935 | #if defined (TODO) |
80d11f44 JM |
7936 | /* MPC5516S */ |
7937 | POWERPC_DEF_SVR("MPC5516S", | |
7938 | CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200), | |
a750fc0b JM |
7939 | #endif |
7940 | #if defined (TODO) | |
80d11f44 JM |
7941 | /* MPC5533 */ |
7942 | POWERPC_DEF_SVR("MPC5533", | |
7943 | CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200), | |
a750fc0b JM |
7944 | #endif |
7945 | #if defined (TODO) | |
80d11f44 JM |
7946 | /* MPC5534 */ |
7947 | POWERPC_DEF_SVR("MPC5534", | |
7948 | CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200), | |
a750fc0b | 7949 | #endif |
80d11f44 JM |
7950 | #if defined (TODO) |
7951 | /* MPC5553 */ | |
7952 | POWERPC_DEF_SVR("MPC5553", | |
7953 | CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200), | |
7954 | #endif | |
7955 | #if defined (TODO) | |
7956 | /* MPC5554 */ | |
7957 | POWERPC_DEF_SVR("MPC5554", | |
7958 | CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200), | |
7959 | #endif | |
7960 | #if defined (TODO) | |
7961 | /* MPC5561 */ | |
7962 | POWERPC_DEF_SVR("MPC5561", | |
7963 | CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200), | |
7964 | #endif | |
7965 | #if defined (TODO) | |
7966 | /* MPC5565 */ | |
7967 | POWERPC_DEF_SVR("MPC5565", | |
7968 | CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200), | |
7969 | #endif | |
7970 | #if defined (TODO) | |
7971 | /* MPC5566 */ | |
7972 | POWERPC_DEF_SVR("MPC5566", | |
7973 | CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200), | |
7974 | #endif | |
7975 | #if defined (TODO) | |
7976 | /* MPC5567 */ | |
7977 | POWERPC_DEF_SVR("MPC5567", | |
7978 | CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200), | |
7979 | #endif | |
7980 | /* e300 family */ | |
7981 | /* Generic PowerPC e300 core */ | |
7982 | POWERPC_DEF("e300", CPU_POWERPC_e300, e300), | |
7983 | /* PowerPC e300c1 core */ | |
7984 | POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300), | |
7985 | /* PowerPC e300c2 core */ | |
7986 | POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300), | |
7987 | /* PowerPC e300c3 core */ | |
7988 | POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300), | |
7989 | /* PowerPC e300c4 core */ | |
7990 | POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300), | |
7991 | /* PowerPC e300 microcontrollers */ | |
7992 | #if defined (TODO) | |
7993 | /* MPC8313 */ | |
7994 | POWERPC_DEF_SVR("MPC8313", | |
7995 | CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300), | |
7996 | #endif | |
7997 | #if defined (TODO) | |
7998 | /* MPC8313E */ | |
7999 | POWERPC_DEF_SVR("MPC8313E", | |
8000 | CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300), | |
8001 | #endif | |
8002 | #if defined (TODO) | |
8003 | /* MPC8314 */ | |
8004 | POWERPC_DEF_SVR("MPC8314", | |
8005 | CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300), | |
8006 | #endif | |
8007 | #if defined (TODO) | |
8008 | /* MPC8314E */ | |
8009 | POWERPC_DEF_SVR("MPC8314E", | |
8010 | CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300), | |
8011 | #endif | |
8012 | #if defined (TODO) | |
8013 | /* MPC8315 */ | |
8014 | POWERPC_DEF_SVR("MPC8315", | |
8015 | CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300), | |
8016 | #endif | |
8017 | #if defined (TODO) | |
8018 | /* MPC8315E */ | |
8019 | POWERPC_DEF_SVR("MPC8315E", | |
8020 | CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300), | |
8021 | #endif | |
8022 | #if defined (TODO) | |
8023 | /* MPC8321 */ | |
8024 | POWERPC_DEF_SVR("MPC8321", | |
8025 | CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300), | |
8026 | #endif | |
8027 | #if defined (TODO) | |
8028 | /* MPC8321E */ | |
8029 | POWERPC_DEF_SVR("MPC8321E", | |
8030 | CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300), | |
8031 | #endif | |
8032 | #if defined (TODO) | |
8033 | /* MPC8323 */ | |
8034 | POWERPC_DEF_SVR("MPC8323", | |
8035 | CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300), | |
8036 | #endif | |
8037 | #if defined (TODO) | |
8038 | /* MPC8323E */ | |
8039 | POWERPC_DEF_SVR("MPC8323E", | |
8040 | CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300), | |
8041 | #endif | |
8042 | /* MPC8343A */ | |
8043 | POWERPC_DEF_SVR("MPC8343A", | |
8044 | CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300), | |
8045 | /* MPC8343EA */ | |
8046 | POWERPC_DEF_SVR("MPC8343EA", | |
8047 | CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300), | |
8048 | /* MPC8347A */ | |
8049 | POWERPC_DEF_SVR("MPC8347A", | |
8050 | CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300), | |
8051 | /* MPC8347AT */ | |
8052 | POWERPC_DEF_SVR("MPC8347AT", | |
8053 | CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300), | |
8054 | /* MPC8347AP */ | |
8055 | POWERPC_DEF_SVR("MPC8347AP", | |
8056 | CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300), | |
8057 | /* MPC8347EA */ | |
8058 | POWERPC_DEF_SVR("MPC8347EA", | |
8059 | CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300), | |
8060 | /* MPC8347EAT */ | |
8061 | POWERPC_DEF_SVR("MPC8347EAT", | |
8062 | CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300), | |
8063 | /* MPC8343EAP */ | |
8064 | POWERPC_DEF_SVR("MPC8347EAP", | |
8065 | CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300), | |
8066 | /* MPC8349 */ | |
8067 | POWERPC_DEF_SVR("MPC8349", | |
8068 | CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300), | |
8069 | /* MPC8349A */ | |
8070 | POWERPC_DEF_SVR("MPC8349A", | |
8071 | CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300), | |
8072 | /* MPC8349E */ | |
8073 | POWERPC_DEF_SVR("MPC8349E", | |
8074 | CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300), | |
8075 | /* MPC8349EA */ | |
8076 | POWERPC_DEF_SVR("MPC8349EA", | |
8077 | CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300), | |
8078 | #if defined (TODO) | |
8079 | /* MPC8358E */ | |
8080 | POWERPC_DEF_SVR("MPC8358E", | |
8081 | CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300), | |
8082 | #endif | |
8083 | #if defined (TODO) | |
8084 | /* MPC8360E */ | |
8085 | POWERPC_DEF_SVR("MPC8360E", | |
8086 | CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300), | |
8087 | #endif | |
8088 | /* MPC8377 */ | |
8089 | POWERPC_DEF_SVR("MPC8377", | |
8090 | CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300), | |
8091 | /* MPC8377E */ | |
8092 | POWERPC_DEF_SVR("MPC8377E", | |
8093 | CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300), | |
8094 | /* MPC8378 */ | |
8095 | POWERPC_DEF_SVR("MPC8378", | |
8096 | CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300), | |
8097 | /* MPC8378E */ | |
8098 | POWERPC_DEF_SVR("MPC8378E", | |
8099 | CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300), | |
8100 | /* MPC8379 */ | |
8101 | POWERPC_DEF_SVR("MPC8379", | |
8102 | CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300), | |
8103 | /* MPC8379E */ | |
8104 | POWERPC_DEF_SVR("MPC8379E", | |
8105 | CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300), | |
8106 | /* e500 family */ | |
8107 | /* PowerPC e500 core */ | |
bd5ea513 AJ |
8108 | POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2), |
8109 | /* PowerPC e500v1 core */ | |
8110 | POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1), | |
80d11f44 | 8111 | /* PowerPC e500 v1.0 core */ |
bd5ea513 | 8112 | POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1), |
80d11f44 | 8113 | /* PowerPC e500 v2.0 core */ |
bd5ea513 | 8114 | POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1), |
80d11f44 | 8115 | /* PowerPC e500v2 core */ |
bd5ea513 | 8116 | POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2), |
80d11f44 | 8117 | /* PowerPC e500v2 v1.0 core */ |
bd5ea513 | 8118 | POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2), |
80d11f44 | 8119 | /* PowerPC e500v2 v2.0 core */ |
bd5ea513 | 8120 | POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2), |
80d11f44 | 8121 | /* PowerPC e500v2 v2.1 core */ |
bd5ea513 | 8122 | POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2), |
80d11f44 | 8123 | /* PowerPC e500v2 v2.2 core */ |
bd5ea513 | 8124 | POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2), |
80d11f44 | 8125 | /* PowerPC e500v2 v3.0 core */ |
bd5ea513 | 8126 | POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2), |
80d11f44 JM |
8127 | /* PowerPC e500 microcontrollers */ |
8128 | /* MPC8533 */ | |
8129 | POWERPC_DEF_SVR("MPC8533", | |
bd5ea513 | 8130 | CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2), |
80d11f44 JM |
8131 | /* MPC8533 v1.0 */ |
8132 | POWERPC_DEF_SVR("MPC8533_v10", | |
bd5ea513 | 8133 | CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2), |
80d11f44 JM |
8134 | /* MPC8533 v1.1 */ |
8135 | POWERPC_DEF_SVR("MPC8533_v11", | |
bd5ea513 | 8136 | CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2), |
80d11f44 JM |
8137 | /* MPC8533E */ |
8138 | POWERPC_DEF_SVR("MPC8533E", | |
bd5ea513 | 8139 | CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2), |
80d11f44 JM |
8140 | /* MPC8533E v1.0 */ |
8141 | POWERPC_DEF_SVR("MPC8533E_v10", | |
bd5ea513 | 8142 | CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2), |
80d11f44 | 8143 | POWERPC_DEF_SVR("MPC8533E_v11", |
bd5ea513 | 8144 | CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2), |
80d11f44 JM |
8145 | /* MPC8540 */ |
8146 | POWERPC_DEF_SVR("MPC8540", | |
bd5ea513 | 8147 | CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1), |
80d11f44 JM |
8148 | /* MPC8540 v1.0 */ |
8149 | POWERPC_DEF_SVR("MPC8540_v10", | |
bd5ea513 | 8150 | CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1), |
80d11f44 JM |
8151 | /* MPC8540 v2.0 */ |
8152 | POWERPC_DEF_SVR("MPC8540_v20", | |
bd5ea513 | 8153 | CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1), |
80d11f44 JM |
8154 | /* MPC8540 v2.1 */ |
8155 | POWERPC_DEF_SVR("MPC8540_v21", | |
bd5ea513 | 8156 | CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1), |
80d11f44 JM |
8157 | /* MPC8541 */ |
8158 | POWERPC_DEF_SVR("MPC8541", | |
bd5ea513 | 8159 | CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1), |
80d11f44 JM |
8160 | /* MPC8541 v1.0 */ |
8161 | POWERPC_DEF_SVR("MPC8541_v10", | |
bd5ea513 | 8162 | CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1), |
80d11f44 JM |
8163 | /* MPC8541 v1.1 */ |
8164 | POWERPC_DEF_SVR("MPC8541_v11", | |
bd5ea513 | 8165 | CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1), |
80d11f44 JM |
8166 | /* MPC8541E */ |
8167 | POWERPC_DEF_SVR("MPC8541E", | |
bd5ea513 | 8168 | CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1), |
80d11f44 JM |
8169 | /* MPC8541E v1.0 */ |
8170 | POWERPC_DEF_SVR("MPC8541E_v10", | |
bd5ea513 | 8171 | CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1), |
80d11f44 JM |
8172 | /* MPC8541E v1.1 */ |
8173 | POWERPC_DEF_SVR("MPC8541E_v11", | |
bd5ea513 | 8174 | CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1), |
80d11f44 JM |
8175 | /* MPC8543 */ |
8176 | POWERPC_DEF_SVR("MPC8543", | |
bd5ea513 | 8177 | CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2), |
80d11f44 JM |
8178 | /* MPC8543 v1.0 */ |
8179 | POWERPC_DEF_SVR("MPC8543_v10", | |
bd5ea513 | 8180 | CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2), |
80d11f44 JM |
8181 | /* MPC8543 v1.1 */ |
8182 | POWERPC_DEF_SVR("MPC8543_v11", | |
bd5ea513 | 8183 | CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2), |
80d11f44 JM |
8184 | /* MPC8543 v2.0 */ |
8185 | POWERPC_DEF_SVR("MPC8543_v20", | |
bd5ea513 | 8186 | CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2), |
80d11f44 JM |
8187 | /* MPC8543 v2.1 */ |
8188 | POWERPC_DEF_SVR("MPC8543_v21", | |
bd5ea513 | 8189 | CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2), |
80d11f44 JM |
8190 | /* MPC8543E */ |
8191 | POWERPC_DEF_SVR("MPC8543E", | |
bd5ea513 | 8192 | CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2), |
80d11f44 JM |
8193 | /* MPC8543E v1.0 */ |
8194 | POWERPC_DEF_SVR("MPC8543E_v10", | |
bd5ea513 | 8195 | CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2), |
80d11f44 JM |
8196 | /* MPC8543E v1.1 */ |
8197 | POWERPC_DEF_SVR("MPC8543E_v11", | |
bd5ea513 | 8198 | CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2), |
80d11f44 JM |
8199 | /* MPC8543E v2.0 */ |
8200 | POWERPC_DEF_SVR("MPC8543E_v20", | |
bd5ea513 | 8201 | CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2), |
80d11f44 JM |
8202 | /* MPC8543E v2.1 */ |
8203 | POWERPC_DEF_SVR("MPC8543E_v21", | |
bd5ea513 | 8204 | CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2), |
80d11f44 JM |
8205 | /* MPC8544 */ |
8206 | POWERPC_DEF_SVR("MPC8544", | |
bd5ea513 | 8207 | CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2), |
80d11f44 JM |
8208 | /* MPC8544 v1.0 */ |
8209 | POWERPC_DEF_SVR("MPC8544_v10", | |
bd5ea513 | 8210 | CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2), |
80d11f44 JM |
8211 | /* MPC8544 v1.1 */ |
8212 | POWERPC_DEF_SVR("MPC8544_v11", | |
bd5ea513 | 8213 | CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2), |
80d11f44 JM |
8214 | /* MPC8544E */ |
8215 | POWERPC_DEF_SVR("MPC8544E", | |
bd5ea513 | 8216 | CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2), |
80d11f44 JM |
8217 | /* MPC8544E v1.0 */ |
8218 | POWERPC_DEF_SVR("MPC8544E_v10", | |
bd5ea513 | 8219 | CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2), |
80d11f44 JM |
8220 | /* MPC8544E v1.1 */ |
8221 | POWERPC_DEF_SVR("MPC8544E_v11", | |
bd5ea513 | 8222 | CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2), |
80d11f44 JM |
8223 | /* MPC8545 */ |
8224 | POWERPC_DEF_SVR("MPC8545", | |
bd5ea513 | 8225 | CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2), |
80d11f44 JM |
8226 | /* MPC8545 v2.0 */ |
8227 | POWERPC_DEF_SVR("MPC8545_v20", | |
bd5ea513 | 8228 | CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2), |
80d11f44 JM |
8229 | /* MPC8545 v2.1 */ |
8230 | POWERPC_DEF_SVR("MPC8545_v21", | |
bd5ea513 | 8231 | CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2), |
80d11f44 JM |
8232 | /* MPC8545E */ |
8233 | POWERPC_DEF_SVR("MPC8545E", | |
bd5ea513 | 8234 | CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2), |
80d11f44 JM |
8235 | /* MPC8545E v2.0 */ |
8236 | POWERPC_DEF_SVR("MPC8545E_v20", | |
bd5ea513 | 8237 | CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2), |
80d11f44 JM |
8238 | /* MPC8545E v2.1 */ |
8239 | POWERPC_DEF_SVR("MPC8545E_v21", | |
bd5ea513 | 8240 | CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2), |
80d11f44 JM |
8241 | /* MPC8547E */ |
8242 | POWERPC_DEF_SVR("MPC8547E", | |
bd5ea513 | 8243 | CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2), |
80d11f44 JM |
8244 | /* MPC8547E v2.0 */ |
8245 | POWERPC_DEF_SVR("MPC8547E_v20", | |
bd5ea513 | 8246 | CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2), |
80d11f44 JM |
8247 | /* MPC8547E v2.1 */ |
8248 | POWERPC_DEF_SVR("MPC8547E_v21", | |
bd5ea513 | 8249 | CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2), |
80d11f44 JM |
8250 | /* MPC8548 */ |
8251 | POWERPC_DEF_SVR("MPC8548", | |
bd5ea513 | 8252 | CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2), |
80d11f44 JM |
8253 | /* MPC8548 v1.0 */ |
8254 | POWERPC_DEF_SVR("MPC8548_v10", | |
bd5ea513 | 8255 | CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2), |
80d11f44 JM |
8256 | /* MPC8548 v1.1 */ |
8257 | POWERPC_DEF_SVR("MPC8548_v11", | |
bd5ea513 | 8258 | CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2), |
80d11f44 JM |
8259 | /* MPC8548 v2.0 */ |
8260 | POWERPC_DEF_SVR("MPC8548_v20", | |
bd5ea513 | 8261 | CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2), |
80d11f44 JM |
8262 | /* MPC8548 v2.1 */ |
8263 | POWERPC_DEF_SVR("MPC8548_v21", | |
bd5ea513 | 8264 | CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2), |
80d11f44 JM |
8265 | /* MPC8548E */ |
8266 | POWERPC_DEF_SVR("MPC8548E", | |
bd5ea513 | 8267 | CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2), |
80d11f44 JM |
8268 | /* MPC8548E v1.0 */ |
8269 | POWERPC_DEF_SVR("MPC8548E_v10", | |
bd5ea513 | 8270 | CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2), |
80d11f44 JM |
8271 | /* MPC8548E v1.1 */ |
8272 | POWERPC_DEF_SVR("MPC8548E_v11", | |
bd5ea513 | 8273 | CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2), |
80d11f44 JM |
8274 | /* MPC8548E v2.0 */ |
8275 | POWERPC_DEF_SVR("MPC8548E_v20", | |
bd5ea513 | 8276 | CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2), |
80d11f44 JM |
8277 | /* MPC8548E v2.1 */ |
8278 | POWERPC_DEF_SVR("MPC8548E_v21", | |
bd5ea513 | 8279 | CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2), |
80d11f44 JM |
8280 | /* MPC8555 */ |
8281 | POWERPC_DEF_SVR("MPC8555", | |
bd5ea513 | 8282 | CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2), |
80d11f44 JM |
8283 | /* MPC8555 v1.0 */ |
8284 | POWERPC_DEF_SVR("MPC8555_v10", | |
bd5ea513 | 8285 | CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2), |
80d11f44 JM |
8286 | /* MPC8555 v1.1 */ |
8287 | POWERPC_DEF_SVR("MPC8555_v11", | |
bd5ea513 | 8288 | CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2), |
80d11f44 JM |
8289 | /* MPC8555E */ |
8290 | POWERPC_DEF_SVR("MPC8555E", | |
bd5ea513 | 8291 | CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2), |
80d11f44 JM |
8292 | /* MPC8555E v1.0 */ |
8293 | POWERPC_DEF_SVR("MPC8555E_v10", | |
bd5ea513 | 8294 | CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2), |
80d11f44 JM |
8295 | /* MPC8555E v1.1 */ |
8296 | POWERPC_DEF_SVR("MPC8555E_v11", | |
bd5ea513 | 8297 | CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2), |
80d11f44 JM |
8298 | /* MPC8560 */ |
8299 | POWERPC_DEF_SVR("MPC8560", | |
bd5ea513 | 8300 | CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2), |
80d11f44 JM |
8301 | /* MPC8560 v1.0 */ |
8302 | POWERPC_DEF_SVR("MPC8560_v10", | |
bd5ea513 | 8303 | CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2), |
80d11f44 JM |
8304 | /* MPC8560 v2.0 */ |
8305 | POWERPC_DEF_SVR("MPC8560_v20", | |
bd5ea513 | 8306 | CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2), |
80d11f44 JM |
8307 | /* MPC8560 v2.1 */ |
8308 | POWERPC_DEF_SVR("MPC8560_v21", | |
bd5ea513 | 8309 | CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2), |
80d11f44 JM |
8310 | /* MPC8567 */ |
8311 | POWERPC_DEF_SVR("MPC8567", | |
bd5ea513 | 8312 | CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2), |
80d11f44 JM |
8313 | /* MPC8567E */ |
8314 | POWERPC_DEF_SVR("MPC8567E", | |
bd5ea513 | 8315 | CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2), |
80d11f44 JM |
8316 | /* MPC8568 */ |
8317 | POWERPC_DEF_SVR("MPC8568", | |
bd5ea513 | 8318 | CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2), |
80d11f44 JM |
8319 | /* MPC8568E */ |
8320 | POWERPC_DEF_SVR("MPC8568E", | |
bd5ea513 | 8321 | CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2), |
80d11f44 JM |
8322 | /* MPC8572 */ |
8323 | POWERPC_DEF_SVR("MPC8572", | |
bd5ea513 | 8324 | CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2), |
80d11f44 JM |
8325 | /* MPC8572E */ |
8326 | POWERPC_DEF_SVR("MPC8572E", | |
bd5ea513 | 8327 | CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2), |
80d11f44 JM |
8328 | /* e600 family */ |
8329 | /* PowerPC e600 core */ | |
8330 | POWERPC_DEF("e600", CPU_POWERPC_e600, 7400), | |
8331 | /* PowerPC e600 microcontrollers */ | |
8332 | #if defined (TODO) | |
8333 | /* MPC8610 */ | |
8334 | POWERPC_DEF_SVR("MPC8610", | |
8335 | CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400), | |
8336 | #endif | |
8337 | /* MPC8641 */ | |
8338 | POWERPC_DEF_SVR("MPC8641", | |
8339 | CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400), | |
8340 | /* MPC8641D */ | |
8341 | POWERPC_DEF_SVR("MPC8641D", | |
8342 | CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400), | |
a750fc0b JM |
8343 | /* 32 bits "classic" PowerPC */ |
8344 | /* PowerPC 6xx family */ | |
8345 | /* PowerPC 601 */ | |
bd928eba | 8346 | POWERPC_DEF("601", CPU_POWERPC_601, 601v), |
c3e36823 | 8347 | /* PowerPC 601v0 */ |
082c6681 | 8348 | POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601), |
c3e36823 | 8349 | /* PowerPC 601v1 */ |
082c6681 JM |
8350 | POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601), |
8351 | /* PowerPC 601v */ | |
bd928eba | 8352 | POWERPC_DEF("601v", CPU_POWERPC_601v, 601v), |
a750fc0b | 8353 | /* PowerPC 601v2 */ |
082c6681 | 8354 | POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v), |
a750fc0b | 8355 | /* PowerPC 602 */ |
80d11f44 | 8356 | POWERPC_DEF("602", CPU_POWERPC_602, 602), |
a750fc0b | 8357 | /* PowerPC 603 */ |
80d11f44 | 8358 | POWERPC_DEF("603", CPU_POWERPC_603, 603), |
a750fc0b | 8359 | /* Code name for PowerPC 603 */ |
80d11f44 | 8360 | POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603), |
082c6681 | 8361 | /* PowerPC 603e (aka PID6) */ |
80d11f44 | 8362 | POWERPC_DEF("603e", CPU_POWERPC_603E, 603E), |
a750fc0b | 8363 | /* Code name for PowerPC 603e */ |
80d11f44 | 8364 | POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E), |
a750fc0b | 8365 | /* PowerPC 603e v1.1 */ |
80d11f44 | 8366 | POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E), |
a750fc0b | 8367 | /* PowerPC 603e v1.2 */ |
80d11f44 | 8368 | POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E), |
a750fc0b | 8369 | /* PowerPC 603e v1.3 */ |
80d11f44 | 8370 | POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E), |
a750fc0b | 8371 | /* PowerPC 603e v1.4 */ |
80d11f44 | 8372 | POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E), |
a750fc0b | 8373 | /* PowerPC 603e v2.2 */ |
80d11f44 | 8374 | POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E), |
a750fc0b | 8375 | /* PowerPC 603e v3 */ |
80d11f44 | 8376 | POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E), |
a750fc0b | 8377 | /* PowerPC 603e v4 */ |
80d11f44 | 8378 | POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E), |
a750fc0b | 8379 | /* PowerPC 603e v4.1 */ |
80d11f44 | 8380 | POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E), |
082c6681 | 8381 | /* PowerPC 603e (aka PID7) */ |
80d11f44 | 8382 | POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E), |
a750fc0b | 8383 | /* PowerPC 603e7t */ |
80d11f44 | 8384 | POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E), |
a750fc0b | 8385 | /* PowerPC 603e7v */ |
80d11f44 | 8386 | POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E), |
a750fc0b | 8387 | /* Code name for PowerPC 603ev */ |
80d11f44 | 8388 | POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E), |
a750fc0b | 8389 | /* PowerPC 603e7v1 */ |
80d11f44 | 8390 | POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E), |
a750fc0b | 8391 | /* PowerPC 603e7v2 */ |
80d11f44 | 8392 | POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E), |
082c6681 JM |
8393 | /* PowerPC 603p (aka PID7v) */ |
8394 | POWERPC_DEF("603p", CPU_POWERPC_603P, 603E), | |
8395 | /* PowerPC 603r (aka PID7t) */ | |
80d11f44 | 8396 | POWERPC_DEF("603r", CPU_POWERPC_603R, 603E), |
a750fc0b | 8397 | /* Code name for PowerPC 603r */ |
80d11f44 | 8398 | POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E), |
a750fc0b | 8399 | /* PowerPC 604 */ |
80d11f44 | 8400 | POWERPC_DEF("604", CPU_POWERPC_604, 604), |
082c6681 JM |
8401 | /* PowerPC 604e (aka PID9) */ |
8402 | POWERPC_DEF("604e", CPU_POWERPC_604E, 604E), | |
8403 | /* Code name for PowerPC 604e */ | |
8404 | POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E), | |
a750fc0b | 8405 | /* PowerPC 604e v1.0 */ |
082c6681 | 8406 | POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E), |
a750fc0b | 8407 | /* PowerPC 604e v2.2 */ |
082c6681 | 8408 | POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E), |
a750fc0b | 8409 | /* PowerPC 604e v2.4 */ |
082c6681 JM |
8410 | POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E), |
8411 | /* PowerPC 604r (aka PIDA) */ | |
8412 | POWERPC_DEF("604r", CPU_POWERPC_604R, 604E), | |
8413 | /* Code name for PowerPC 604r */ | |
8414 | POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E), | |
a750fc0b JM |
8415 | #if defined(TODO) |
8416 | /* PowerPC 604ev */ | |
082c6681 | 8417 | POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E), |
a750fc0b JM |
8418 | #endif |
8419 | /* PowerPC 7xx family */ | |
8420 | /* Generic PowerPC 740 (G3) */ | |
bd928eba | 8421 | POWERPC_DEF("740", CPU_POWERPC_7x0, 740), |
082c6681 | 8422 | /* Code name for PowerPC 740 */ |
bd928eba | 8423 | POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740), |
a750fc0b | 8424 | /* Generic PowerPC 750 (G3) */ |
bd928eba | 8425 | POWERPC_DEF("750", CPU_POWERPC_7x0, 750), |
082c6681 | 8426 | /* Code name for PowerPC 750 */ |
bd928eba | 8427 | POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750), |
a750fc0b | 8428 | /* PowerPC 740/750 is also known as G3 */ |
bd928eba JM |
8429 | POWERPC_DEF("G3", CPU_POWERPC_7x0, 750), |
8430 | /* PowerPC 740 v1.0 (G3) */ | |
8431 | POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740), | |
8432 | /* PowerPC 750 v1.0 (G3) */ | |
8433 | POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750), | |
a750fc0b | 8434 | /* PowerPC 740 v2.0 (G3) */ |
bd928eba | 8435 | POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740), |
a750fc0b | 8436 | /* PowerPC 750 v2.0 (G3) */ |
bd928eba | 8437 | POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750), |
a750fc0b | 8438 | /* PowerPC 740 v2.1 (G3) */ |
bd928eba | 8439 | POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740), |
a750fc0b | 8440 | /* PowerPC 750 v2.1 (G3) */ |
bd928eba | 8441 | POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750), |
a750fc0b | 8442 | /* PowerPC 740 v2.2 (G3) */ |
bd928eba | 8443 | POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740), |
a750fc0b | 8444 | /* PowerPC 750 v2.2 (G3) */ |
bd928eba | 8445 | POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750), |
a750fc0b | 8446 | /* PowerPC 740 v3.0 (G3) */ |
bd928eba | 8447 | POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740), |
a750fc0b | 8448 | /* PowerPC 750 v3.0 (G3) */ |
bd928eba | 8449 | POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750), |
a750fc0b | 8450 | /* PowerPC 740 v3.1 (G3) */ |
bd928eba | 8451 | POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740), |
a750fc0b | 8452 | /* PowerPC 750 v3.1 (G3) */ |
bd928eba | 8453 | POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750), |
a750fc0b | 8454 | /* PowerPC 740E (G3) */ |
bd928eba JM |
8455 | POWERPC_DEF("740e", CPU_POWERPC_740E, 740), |
8456 | /* PowerPC 750E (G3) */ | |
8457 | POWERPC_DEF("750e", CPU_POWERPC_750E, 750), | |
a750fc0b | 8458 | /* PowerPC 740P (G3) */ |
bd928eba | 8459 | POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740), |
a750fc0b | 8460 | /* PowerPC 750P (G3) */ |
bd928eba | 8461 | POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750), |
a750fc0b | 8462 | /* Code name for PowerPC 740P/750P (G3) */ |
bd928eba | 8463 | POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750), |
a750fc0b | 8464 | /* PowerPC 750CL (G3 embedded) */ |
bd928eba JM |
8465 | POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl), |
8466 | /* PowerPC 750CL v1.0 */ | |
8467 | POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl), | |
8468 | /* PowerPC 750CL v2.0 */ | |
8469 | POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl), | |
a750fc0b | 8470 | /* PowerPC 750CX (G3 embedded) */ |
bd928eba JM |
8471 | POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx), |
8472 | /* PowerPC 750CX v1.0 (G3 embedded) */ | |
8473 | POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx), | |
8474 | /* PowerPC 750CX v2.1 (G3 embedded) */ | |
8475 | POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx), | |
a750fc0b | 8476 | /* PowerPC 750CX v2.1 (G3 embedded) */ |
bd928eba | 8477 | POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx), |
a750fc0b | 8478 | /* PowerPC 750CX v2.2 (G3 embedded) */ |
bd928eba | 8479 | POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx), |
a750fc0b | 8480 | /* PowerPC 750CXe (G3 embedded) */ |
bd928eba | 8481 | POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx), |
a750fc0b | 8482 | /* PowerPC 750CXe v2.1 (G3 embedded) */ |
bd928eba | 8483 | POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx), |
a750fc0b | 8484 | /* PowerPC 750CXe v2.2 (G3 embedded) */ |
bd928eba | 8485 | POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx), |
a750fc0b | 8486 | /* PowerPC 750CXe v2.3 (G3 embedded) */ |
bd928eba | 8487 | POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx), |
a750fc0b | 8488 | /* PowerPC 750CXe v2.4 (G3 embedded) */ |
bd928eba | 8489 | POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx), |
a750fc0b | 8490 | /* PowerPC 750CXe v2.4b (G3 embedded) */ |
bd928eba JM |
8491 | POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx), |
8492 | /* PowerPC 750CXe v3.0 (G3 embedded) */ | |
8493 | POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx), | |
a750fc0b | 8494 | /* PowerPC 750CXe v3.1 (G3 embedded) */ |
bd928eba | 8495 | POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx), |
a750fc0b | 8496 | /* PowerPC 750CXe v3.1b (G3 embedded) */ |
bd928eba | 8497 | POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx), |
a750fc0b | 8498 | /* PowerPC 750CXr (G3 embedded) */ |
bd928eba | 8499 | POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx), |
a750fc0b | 8500 | /* PowerPC 750FL (G3 embedded) */ |
80d11f44 | 8501 | POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx), |
a750fc0b | 8502 | /* PowerPC 750FX (G3 embedded) */ |
80d11f44 | 8503 | POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx), |
a750fc0b | 8504 | /* PowerPC 750FX v1.0 (G3 embedded) */ |
80d11f44 | 8505 | POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx), |
a750fc0b | 8506 | /* PowerPC 750FX v2.0 (G3 embedded) */ |
80d11f44 | 8507 | POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx), |
a750fc0b | 8508 | /* PowerPC 750FX v2.1 (G3 embedded) */ |
80d11f44 | 8509 | POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx), |
a750fc0b | 8510 | /* PowerPC 750FX v2.2 (G3 embedded) */ |
80d11f44 | 8511 | POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx), |
a750fc0b | 8512 | /* PowerPC 750FX v2.3 (G3 embedded) */ |
80d11f44 | 8513 | POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx), |
a750fc0b | 8514 | /* PowerPC 750GL (G3 embedded) */ |
bd928eba | 8515 | POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx), |
a750fc0b | 8516 | /* PowerPC 750GX (G3 embedded) */ |
bd928eba | 8517 | POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx), |
a750fc0b | 8518 | /* PowerPC 750GX v1.0 (G3 embedded) */ |
bd928eba | 8519 | POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx), |
a750fc0b | 8520 | /* PowerPC 750GX v1.1 (G3 embedded) */ |
bd928eba | 8521 | POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx), |
a750fc0b | 8522 | /* PowerPC 750GX v1.2 (G3 embedded) */ |
bd928eba | 8523 | POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx), |
a750fc0b | 8524 | /* PowerPC 750L (G3 embedded) */ |
bd928eba | 8525 | POWERPC_DEF("750l", CPU_POWERPC_750L, 750), |
a750fc0b | 8526 | /* Code name for PowerPC 750L (G3 embedded) */ |
bd928eba JM |
8527 | POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750), |
8528 | /* PowerPC 750L v2.0 (G3 embedded) */ | |
8529 | POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750), | |
8530 | /* PowerPC 750L v2.1 (G3 embedded) */ | |
8531 | POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750), | |
a750fc0b | 8532 | /* PowerPC 750L v2.2 (G3 embedded) */ |
bd928eba | 8533 | POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750), |
a750fc0b | 8534 | /* PowerPC 750L v3.0 (G3 embedded) */ |
bd928eba | 8535 | POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750), |
a750fc0b | 8536 | /* PowerPC 750L v3.2 (G3 embedded) */ |
bd928eba | 8537 | POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750), |
a750fc0b | 8538 | /* Generic PowerPC 745 */ |
bd928eba | 8539 | POWERPC_DEF("745", CPU_POWERPC_7x5, 745), |
a750fc0b | 8540 | /* Generic PowerPC 755 */ |
bd928eba | 8541 | POWERPC_DEF("755", CPU_POWERPC_7x5, 755), |
a750fc0b | 8542 | /* Code name for PowerPC 745/755 */ |
bd928eba | 8543 | POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755), |
a750fc0b | 8544 | /* PowerPC 745 v1.0 */ |
bd928eba | 8545 | POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745), |
a750fc0b | 8546 | /* PowerPC 755 v1.0 */ |
bd928eba | 8547 | POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755), |
a750fc0b | 8548 | /* PowerPC 745 v1.1 */ |
bd928eba | 8549 | POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745), |
a750fc0b | 8550 | /* PowerPC 755 v1.1 */ |
bd928eba | 8551 | POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755), |
a750fc0b | 8552 | /* PowerPC 745 v2.0 */ |
bd928eba | 8553 | POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745), |
a750fc0b | 8554 | /* PowerPC 755 v2.0 */ |
bd928eba | 8555 | POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755), |
a750fc0b | 8556 | /* PowerPC 745 v2.1 */ |
bd928eba | 8557 | POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745), |
a750fc0b | 8558 | /* PowerPC 755 v2.1 */ |
bd928eba | 8559 | POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755), |
a750fc0b | 8560 | /* PowerPC 745 v2.2 */ |
bd928eba | 8561 | POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745), |
a750fc0b | 8562 | /* PowerPC 755 v2.2 */ |
bd928eba | 8563 | POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755), |
a750fc0b | 8564 | /* PowerPC 745 v2.3 */ |
bd928eba | 8565 | POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745), |
a750fc0b | 8566 | /* PowerPC 755 v2.3 */ |
bd928eba | 8567 | POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755), |
a750fc0b | 8568 | /* PowerPC 745 v2.4 */ |
bd928eba | 8569 | POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745), |
a750fc0b | 8570 | /* PowerPC 755 v2.4 */ |
bd928eba | 8571 | POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755), |
a750fc0b | 8572 | /* PowerPC 745 v2.5 */ |
bd928eba | 8573 | POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745), |
a750fc0b | 8574 | /* PowerPC 755 v2.5 */ |
bd928eba | 8575 | POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755), |
a750fc0b | 8576 | /* PowerPC 745 v2.6 */ |
bd928eba | 8577 | POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745), |
a750fc0b | 8578 | /* PowerPC 755 v2.6 */ |
bd928eba | 8579 | POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755), |
a750fc0b | 8580 | /* PowerPC 745 v2.7 */ |
bd928eba | 8581 | POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745), |
a750fc0b | 8582 | /* PowerPC 755 v2.7 */ |
bd928eba | 8583 | POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755), |
a750fc0b | 8584 | /* PowerPC 745 v2.8 */ |
bd928eba | 8585 | POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745), |
a750fc0b | 8586 | /* PowerPC 755 v2.8 */ |
bd928eba | 8587 | POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755), |
a750fc0b JM |
8588 | #if defined (TODO) |
8589 | /* PowerPC 745P (G3) */ | |
bd928eba | 8590 | POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745), |
a750fc0b | 8591 | /* PowerPC 755P (G3) */ |
bd928eba | 8592 | POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755), |
a750fc0b JM |
8593 | #endif |
8594 | /* PowerPC 74xx family */ | |
8595 | /* PowerPC 7400 (G4) */ | |
80d11f44 | 8596 | POWERPC_DEF("7400", CPU_POWERPC_7400, 7400), |
a750fc0b | 8597 | /* Code name for PowerPC 7400 */ |
80d11f44 | 8598 | POWERPC_DEF("Max", CPU_POWERPC_7400, 7400), |
a750fc0b | 8599 | /* PowerPC 74xx is also well known as G4 */ |
80d11f44 | 8600 | POWERPC_DEF("G4", CPU_POWERPC_7400, 7400), |
a750fc0b | 8601 | /* PowerPC 7400 v1.0 (G4) */ |
80d11f44 | 8602 | POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400), |
a750fc0b | 8603 | /* PowerPC 7400 v1.1 (G4) */ |
80d11f44 | 8604 | POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400), |
a750fc0b | 8605 | /* PowerPC 7400 v2.0 (G4) */ |
80d11f44 | 8606 | POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400), |
4e777442 JM |
8607 | /* PowerPC 7400 v2.1 (G4) */ |
8608 | POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400), | |
a750fc0b | 8609 | /* PowerPC 7400 v2.2 (G4) */ |
80d11f44 | 8610 | POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400), |
a750fc0b | 8611 | /* PowerPC 7400 v2.6 (G4) */ |
80d11f44 | 8612 | POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400), |
a750fc0b | 8613 | /* PowerPC 7400 v2.7 (G4) */ |
80d11f44 | 8614 | POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400), |
a750fc0b | 8615 | /* PowerPC 7400 v2.8 (G4) */ |
80d11f44 | 8616 | POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400), |
a750fc0b | 8617 | /* PowerPC 7400 v2.9 (G4) */ |
80d11f44 | 8618 | POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400), |
a750fc0b | 8619 | /* PowerPC 7410 (G4) */ |
80d11f44 | 8620 | POWERPC_DEF("7410", CPU_POWERPC_7410, 7410), |
a750fc0b | 8621 | /* Code name for PowerPC 7410 */ |
80d11f44 | 8622 | POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410), |
a750fc0b | 8623 | /* PowerPC 7410 v1.0 (G4) */ |
80d11f44 | 8624 | POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410), |
a750fc0b | 8625 | /* PowerPC 7410 v1.1 (G4) */ |
80d11f44 | 8626 | POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410), |
a750fc0b | 8627 | /* PowerPC 7410 v1.2 (G4) */ |
80d11f44 | 8628 | POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410), |
a750fc0b | 8629 | /* PowerPC 7410 v1.3 (G4) */ |
80d11f44 | 8630 | POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410), |
a750fc0b | 8631 | /* PowerPC 7410 v1.4 (G4) */ |
80d11f44 | 8632 | POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410), |
a750fc0b | 8633 | /* PowerPC 7448 (G4) */ |
80d11f44 | 8634 | POWERPC_DEF("7448", CPU_POWERPC_7448, 7400), |
a750fc0b | 8635 | /* PowerPC 7448 v1.0 (G4) */ |
80d11f44 | 8636 | POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400), |
a750fc0b | 8637 | /* PowerPC 7448 v1.1 (G4) */ |
80d11f44 | 8638 | POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400), |
a750fc0b | 8639 | /* PowerPC 7448 v2.0 (G4) */ |
80d11f44 | 8640 | POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400), |
a750fc0b | 8641 | /* PowerPC 7448 v2.1 (G4) */ |
80d11f44 | 8642 | POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400), |
a750fc0b | 8643 | /* PowerPC 7450 (G4) */ |
80d11f44 | 8644 | POWERPC_DEF("7450", CPU_POWERPC_7450, 7450), |
a750fc0b | 8645 | /* Code name for PowerPC 7450 */ |
80d11f44 | 8646 | POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450), |
a750fc0b | 8647 | /* PowerPC 7450 v1.0 (G4) */ |
80d11f44 | 8648 | POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450), |
a750fc0b | 8649 | /* PowerPC 7450 v1.1 (G4) */ |
80d11f44 | 8650 | POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450), |
a750fc0b | 8651 | /* PowerPC 7450 v1.2 (G4) */ |
80d11f44 | 8652 | POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450), |
a750fc0b | 8653 | /* PowerPC 7450 v2.0 (G4) */ |
80d11f44 | 8654 | POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450), |
a750fc0b | 8655 | /* PowerPC 7450 v2.1 (G4) */ |
80d11f44 | 8656 | POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450), |
a750fc0b | 8657 | /* PowerPC 7441 (G4) */ |
80d11f44 | 8658 | POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440), |
a750fc0b | 8659 | /* PowerPC 7451 (G4) */ |
80d11f44 | 8660 | POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450), |
4e777442 JM |
8661 | /* PowerPC 7441 v2.1 (G4) */ |
8662 | POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440), | |
8663 | /* PowerPC 7441 v2.3 (G4) */ | |
8664 | POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440), | |
8665 | /* PowerPC 7451 v2.3 (G4) */ | |
8666 | POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450), | |
8667 | /* PowerPC 7441 v2.10 (G4) */ | |
8668 | POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440), | |
8669 | /* PowerPC 7451 v2.10 (G4) */ | |
8670 | POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450), | |
a750fc0b | 8671 | /* PowerPC 7445 (G4) */ |
80d11f44 | 8672 | POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445), |
a750fc0b | 8673 | /* PowerPC 7455 (G4) */ |
80d11f44 | 8674 | POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455), |
a750fc0b | 8675 | /* Code name for PowerPC 7445/7455 */ |
80d11f44 | 8676 | POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455), |
a750fc0b | 8677 | /* PowerPC 7445 v1.0 (G4) */ |
80d11f44 | 8678 | POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445), |
a750fc0b | 8679 | /* PowerPC 7455 v1.0 (G4) */ |
80d11f44 | 8680 | POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455), |
a750fc0b | 8681 | /* PowerPC 7445 v2.1 (G4) */ |
80d11f44 | 8682 | POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445), |
a750fc0b | 8683 | /* PowerPC 7455 v2.1 (G4) */ |
80d11f44 | 8684 | POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455), |
a750fc0b | 8685 | /* PowerPC 7445 v3.2 (G4) */ |
80d11f44 | 8686 | POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445), |
a750fc0b | 8687 | /* PowerPC 7455 v3.2 (G4) */ |
80d11f44 | 8688 | POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455), |
a750fc0b | 8689 | /* PowerPC 7445 v3.3 (G4) */ |
80d11f44 | 8690 | POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445), |
a750fc0b | 8691 | /* PowerPC 7455 v3.3 (G4) */ |
80d11f44 | 8692 | POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455), |
a750fc0b | 8693 | /* PowerPC 7445 v3.4 (G4) */ |
80d11f44 | 8694 | POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445), |
a750fc0b | 8695 | /* PowerPC 7455 v3.4 (G4) */ |
80d11f44 | 8696 | POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455), |
a750fc0b | 8697 | /* PowerPC 7447 (G4) */ |
80d11f44 | 8698 | POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445), |
a750fc0b | 8699 | /* PowerPC 7457 (G4) */ |
80d11f44 | 8700 | POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455), |
a750fc0b | 8701 | /* Code name for PowerPC 7447/7457 */ |
80d11f44 | 8702 | POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455), |
a750fc0b | 8703 | /* PowerPC 7447 v1.0 (G4) */ |
80d11f44 | 8704 | POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445), |
a750fc0b | 8705 | /* PowerPC 7457 v1.0 (G4) */ |
80d11f44 | 8706 | POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455), |
a750fc0b | 8707 | /* PowerPC 7447 v1.1 (G4) */ |
80d11f44 | 8708 | POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445), |
a750fc0b | 8709 | /* PowerPC 7457 v1.1 (G4) */ |
80d11f44 | 8710 | POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455), |
a750fc0b | 8711 | /* PowerPC 7457 v1.2 (G4) */ |
80d11f44 | 8712 | POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455), |
082c6681 JM |
8713 | /* PowerPC 7447A (G4) */ |
8714 | POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445), | |
8715 | /* PowerPC 7457A (G4) */ | |
8716 | POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455), | |
8717 | /* PowerPC 7447A v1.0 (G4) */ | |
8718 | POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445), | |
8719 | /* PowerPC 7457A v1.0 (G4) */ | |
8720 | POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455), | |
8721 | /* Code name for PowerPC 7447A/7457A */ | |
8722 | POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455), | |
8723 | /* PowerPC 7447A v1.1 (G4) */ | |
8724 | POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445), | |
8725 | /* PowerPC 7457A v1.1 (G4) */ | |
8726 | POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455), | |
8727 | /* PowerPC 7447A v1.2 (G4) */ | |
8728 | POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445), | |
8729 | /* PowerPC 7457A v1.2 (G4) */ | |
8730 | POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455), | |
a750fc0b JM |
8731 | /* 64 bits PowerPC */ |
8732 | #if defined (TARGET_PPC64) | |
a750fc0b | 8733 | /* PowerPC 620 */ |
80d11f44 | 8734 | POWERPC_DEF("620", CPU_POWERPC_620, 620), |
082c6681 JM |
8735 | /* Code name for PowerPC 620 */ |
8736 | POWERPC_DEF("Trident", CPU_POWERPC_620, 620), | |
3fc6c082 | 8737 | #if defined (TODO) |
a750fc0b | 8738 | /* PowerPC 630 (POWER3) */ |
80d11f44 JM |
8739 | POWERPC_DEF("630", CPU_POWERPC_630, 630), |
8740 | POWERPC_DEF("POWER3", CPU_POWERPC_630, 630), | |
082c6681 JM |
8741 | /* Code names for POWER3 */ |
8742 | POWERPC_DEF("Boxer", CPU_POWERPC_630, 630), | |
8743 | POWERPC_DEF("Dino", CPU_POWERPC_630, 630), | |
a750fc0b | 8744 | #endif |
3a607854 | 8745 | #if defined (TODO) |
a750fc0b | 8746 | /* PowerPC 631 (Power 3+) */ |
80d11f44 JM |
8747 | POWERPC_DEF("631", CPU_POWERPC_631, 631), |
8748 | POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631), | |
3a607854 JM |
8749 | #endif |
8750 | #if defined (TODO) | |
a750fc0b | 8751 | /* POWER4 */ |
80d11f44 | 8752 | POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4), |
a750fc0b | 8753 | #endif |
3a607854 | 8754 | #if defined (TODO) |
a750fc0b | 8755 | /* POWER4p */ |
80d11f44 | 8756 | POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P), |
a750fc0b | 8757 | #endif |
2662a059 | 8758 | #if defined (TODO) |
a750fc0b | 8759 | /* POWER5 */ |
80d11f44 | 8760 | POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5), |
a750fc0b | 8761 | /* POWER5GR */ |
80d11f44 | 8762 | POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5), |
2662a059 | 8763 | #endif |
3a607854 | 8764 | #if defined (TODO) |
a750fc0b | 8765 | /* POWER5+ */ |
80d11f44 | 8766 | POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P), |
a750fc0b | 8767 | /* POWER5GS */ |
80d11f44 | 8768 | POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P), |
a750fc0b | 8769 | #endif |
2662a059 | 8770 | #if defined (TODO) |
a750fc0b | 8771 | /* POWER6 */ |
80d11f44 | 8772 | POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6), |
a750fc0b | 8773 | /* POWER6 running in POWER5 mode */ |
80d11f44 | 8774 | POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5), |
a750fc0b | 8775 | /* POWER6A */ |
80d11f44 | 8776 | POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6), |
2662a059 | 8777 | #endif |
a750fc0b | 8778 | /* PowerPC 970 */ |
80d11f44 | 8779 | POWERPC_DEF("970", CPU_POWERPC_970, 970), |
a750fc0b | 8780 | /* PowerPC 970FX (G5) */ |
80d11f44 | 8781 | POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX), |
a750fc0b | 8782 | /* PowerPC 970FX v1.0 (G5) */ |
80d11f44 | 8783 | POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX), |
a750fc0b | 8784 | /* PowerPC 970FX v2.0 (G5) */ |
80d11f44 | 8785 | POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX), |
a750fc0b | 8786 | /* PowerPC 970FX v2.1 (G5) */ |
80d11f44 | 8787 | POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX), |
a750fc0b | 8788 | /* PowerPC 970FX v3.0 (G5) */ |
80d11f44 | 8789 | POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX), |
a750fc0b | 8790 | /* PowerPC 970FX v3.1 (G5) */ |
80d11f44 | 8791 | POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX), |
a750fc0b | 8792 | /* PowerPC 970GX (G5) */ |
80d11f44 | 8793 | POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX), |
a750fc0b | 8794 | /* PowerPC 970MP */ |
80d11f44 | 8795 | POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP), |
a750fc0b | 8796 | /* PowerPC 970MP v1.0 */ |
80d11f44 | 8797 | POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP), |
a750fc0b | 8798 | /* PowerPC 970MP v1.1 */ |
80d11f44 | 8799 | POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP), |
3a607854 | 8800 | #if defined (TODO) |
a750fc0b | 8801 | /* PowerPC Cell */ |
80d11f44 | 8802 | POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970), |
2662a059 JM |
8803 | #endif |
8804 | #if defined (TODO) | |
a750fc0b | 8805 | /* PowerPC Cell v1.0 */ |
80d11f44 | 8806 | POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970), |
2662a059 JM |
8807 | #endif |
8808 | #if defined (TODO) | |
a750fc0b | 8809 | /* PowerPC Cell v2.0 */ |
80d11f44 | 8810 | POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970), |
2662a059 JM |
8811 | #endif |
8812 | #if defined (TODO) | |
a750fc0b | 8813 | /* PowerPC Cell v3.0 */ |
80d11f44 | 8814 | POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970), |
3a607854 | 8815 | #endif |
3a607854 | 8816 | #if defined (TODO) |
a750fc0b | 8817 | /* PowerPC Cell v3.1 */ |
80d11f44 | 8818 | POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970), |
2662a059 JM |
8819 | #endif |
8820 | #if defined (TODO) | |
a750fc0b | 8821 | /* PowerPC Cell v3.2 */ |
80d11f44 | 8822 | POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970), |
2662a059 JM |
8823 | #endif |
8824 | #if defined (TODO) | |
a750fc0b JM |
8825 | /* RS64 (Apache/A35) */ |
8826 | /* This one seems to support the whole POWER2 instruction set | |
8827 | * and the PowerPC 64 one. | |
8828 | */ | |
8829 | /* What about A10 & A30 ? */ | |
80d11f44 JM |
8830 | POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64), |
8831 | POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64), | |
8832 | POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64), | |
3a607854 JM |
8833 | #endif |
8834 | #if defined (TODO) | |
a750fc0b | 8835 | /* RS64-II (NorthStar/A50) */ |
80d11f44 JM |
8836 | POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64), |
8837 | POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64), | |
8838 | POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64), | |
3a607854 JM |
8839 | #endif |
8840 | #if defined (TODO) | |
a750fc0b | 8841 | /* RS64-III (Pulsar) */ |
80d11f44 JM |
8842 | POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64), |
8843 | POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64), | |
2662a059 JM |
8844 | #endif |
8845 | #if defined (TODO) | |
a750fc0b | 8846 | /* RS64-IV (IceStar/IStar/SStar) */ |
80d11f44 JM |
8847 | POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64), |
8848 | POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64), | |
8849 | POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64), | |
8850 | POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64), | |
3a607854 | 8851 | #endif |
a750fc0b JM |
8852 | #endif /* defined (TARGET_PPC64) */ |
8853 | /* POWER */ | |
3fc6c082 | 8854 | #if defined (TODO) |
a750fc0b | 8855 | /* Original POWER */ |
80d11f44 JM |
8856 | POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER), |
8857 | POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER), | |
8858 | POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER), | |
8859 | POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER), | |
8860 | POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER), | |
76a66253 JM |
8861 | #endif |
8862 | #if defined (TODO) | |
a750fc0b | 8863 | /* POWER2 */ |
80d11f44 JM |
8864 | POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER), |
8865 | POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER), | |
8866 | POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER), | |
a750fc0b JM |
8867 | #endif |
8868 | /* PA semi cores */ | |
8869 | #if defined (TODO) | |
8870 | /* PA PA6T */ | |
80d11f44 | 8871 | POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T), |
a750fc0b JM |
8872 | #endif |
8873 | /* Generic PowerPCs */ | |
8874 | #if defined (TARGET_PPC64) | |
80d11f44 | 8875 | POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64), |
a750fc0b | 8876 | #endif |
80d11f44 JM |
8877 | POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32), |
8878 | POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT), | |
a750fc0b | 8879 | /* Fallback */ |
80d11f44 | 8880 | POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT), |
a750fc0b JM |
8881 | }; |
8882 | ||
8883 | /*****************************************************************************/ | |
8884 | /* Generic CPU instanciation routine */ | |
aaed909a | 8885 | static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def) |
a750fc0b JM |
8886 | { |
8887 | #if !defined(CONFIG_USER_ONLY) | |
e1833e1f JM |
8888 | int i; |
8889 | ||
a750fc0b | 8890 | env->irq_inputs = NULL; |
e1833e1f JM |
8891 | /* Set all exception vectors to an invalid address */ |
8892 | for (i = 0; i < POWERPC_EXCP_NB; i++) | |
8893 | env->excp_vectors[i] = (target_ulong)(-1ULL); | |
fc1c67bc | 8894 | env->hreset_excp_prefix = 0x00000000; |
e1833e1f JM |
8895 | env->ivor_mask = 0x00000000; |
8896 | env->ivpr_mask = 0x00000000; | |
a750fc0b JM |
8897 | /* Default MMU definitions */ |
8898 | env->nb_BATs = 0; | |
8899 | env->nb_tlb = 0; | |
8900 | env->nb_ways = 0; | |
f2e63a42 | 8901 | #endif |
a750fc0b JM |
8902 | /* Register SPR common to all PowerPC implementations */ |
8903 | gen_spr_generic(env); | |
8904 | spr_register(env, SPR_PVR, "PVR", | |
a139aa17 NF |
8905 | /* Linux permits userspace to read PVR */ |
8906 | #if defined(CONFIG_LINUX_USER) | |
8907 | &spr_read_generic, | |
8908 | #else | |
8909 | SPR_NOACCESS, | |
8910 | #endif | |
8911 | SPR_NOACCESS, | |
a750fc0b JM |
8912 | &spr_read_generic, SPR_NOACCESS, |
8913 | def->pvr); | |
80d11f44 JM |
8914 | /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ |
8915 | if (def->svr != POWERPC_SVR_NONE) { | |
8916 | if (def->svr & POWERPC_SVR_E500) { | |
8917 | spr_register(env, SPR_E500_SVR, "SVR", | |
8918 | SPR_NOACCESS, SPR_NOACCESS, | |
8919 | &spr_read_generic, SPR_NOACCESS, | |
8920 | def->svr & ~POWERPC_SVR_E500); | |
8921 | } else { | |
8922 | spr_register(env, SPR_SVR, "SVR", | |
8923 | SPR_NOACCESS, SPR_NOACCESS, | |
8924 | &spr_read_generic, SPR_NOACCESS, | |
8925 | def->svr); | |
8926 | } | |
8927 | } | |
a750fc0b JM |
8928 | /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ |
8929 | (*def->init_proc)(env); | |
fc1c67bc BS |
8930 | #if !defined(CONFIG_USER_ONLY) |
8931 | env->excp_prefix = env->hreset_excp_prefix; | |
8932 | #endif | |
25ba3a68 JM |
8933 | /* MSR bits & flags consistency checks */ |
8934 | if (env->msr_mask & (1 << 25)) { | |
8935 | switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { | |
8936 | case POWERPC_FLAG_SPE: | |
8937 | case POWERPC_FLAG_VRE: | |
8938 | break; | |
8939 | default: | |
8940 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8941 | "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); | |
8942 | exit(1); | |
8943 | } | |
8944 | } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { | |
8945 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8946 | "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); | |
8947 | exit(1); | |
8948 | } | |
8949 | if (env->msr_mask & (1 << 17)) { | |
8950 | switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { | |
8951 | case POWERPC_FLAG_TGPR: | |
8952 | case POWERPC_FLAG_CE: | |
8953 | break; | |
8954 | default: | |
8955 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8956 | "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); | |
8957 | exit(1); | |
8958 | } | |
8959 | } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { | |
8960 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8961 | "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); | |
8962 | exit(1); | |
8963 | } | |
8964 | if (env->msr_mask & (1 << 10)) { | |
8965 | switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | | |
8966 | POWERPC_FLAG_UBLE)) { | |
8967 | case POWERPC_FLAG_SE: | |
8968 | case POWERPC_FLAG_DWE: | |
8969 | case POWERPC_FLAG_UBLE: | |
8970 | break; | |
8971 | default: | |
8972 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8973 | "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " | |
8974 | "POWERPC_FLAG_UBLE\n"); | |
8975 | exit(1); | |
8976 | } | |
8977 | } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | | |
8978 | POWERPC_FLAG_UBLE)) { | |
8979 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8980 | "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " | |
8981 | "POWERPC_FLAG_UBLE\n"); | |
8982 | exit(1); | |
8983 | } | |
8984 | if (env->msr_mask & (1 << 9)) { | |
8985 | switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { | |
8986 | case POWERPC_FLAG_BE: | |
8987 | case POWERPC_FLAG_DE: | |
8988 | break; | |
8989 | default: | |
8990 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8991 | "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); | |
8992 | exit(1); | |
8993 | } | |
8994 | } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { | |
8995 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8996 | "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); | |
8997 | exit(1); | |
8998 | } | |
8999 | if (env->msr_mask & (1 << 2)) { | |
9000 | switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { | |
9001 | case POWERPC_FLAG_PX: | |
9002 | case POWERPC_FLAG_PMM: | |
9003 | break; | |
9004 | default: | |
9005 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
9006 | "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); | |
9007 | exit(1); | |
9008 | } | |
9009 | } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { | |
9010 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
9011 | "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); | |
9012 | exit(1); | |
9013 | } | |
4018bae9 JM |
9014 | if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { |
9015 | fprintf(stderr, "PowerPC flags inconsistency\n" | |
9016 | "Should define the time-base and decrementer clock source\n"); | |
9017 | exit(1); | |
9018 | } | |
a750fc0b | 9019 | /* Allocate TLBs buffer when needed */ |
f2e63a42 | 9020 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
9021 | if (env->nb_tlb != 0) { |
9022 | int nb_tlb = env->nb_tlb; | |
9023 | if (env->id_tlbs != 0) | |
9024 | nb_tlb *= 2; | |
9025 | env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t)); | |
9026 | /* Pre-compute some useful values */ | |
9027 | env->tlb_per_way = env->nb_tlb / env->nb_ways; | |
9028 | } | |
a750fc0b JM |
9029 | if (env->irq_inputs == NULL) { |
9030 | fprintf(stderr, "WARNING: no internal IRQ controller registered.\n" | |
9031 | " Attempt Qemu to crash very soon !\n"); | |
9032 | } | |
9033 | #endif | |
2f462816 JM |
9034 | if (env->check_pow == NULL) { |
9035 | fprintf(stderr, "WARNING: no power management check handler " | |
9036 | "registered.\n" | |
9037 | " Attempt Qemu to crash very soon !\n"); | |
9038 | } | |
a750fc0b JM |
9039 | } |
9040 | ||
9041 | #if defined(PPC_DUMP_CPU) | |
9042 | static void dump_ppc_sprs (CPUPPCState *env) | |
9043 | { | |
9044 | ppc_spr_t *spr; | |
9045 | #if !defined(CONFIG_USER_ONLY) | |
9046 | uint32_t sr, sw; | |
9047 | #endif | |
9048 | uint32_t ur, uw; | |
9049 | int i, j, n; | |
9050 | ||
9051 | printf("Special purpose registers:\n"); | |
9052 | for (i = 0; i < 32; i++) { | |
9053 | for (j = 0; j < 32; j++) { | |
9054 | n = (i << 5) | j; | |
9055 | spr = &env->spr_cb[n]; | |
9056 | uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; | |
9057 | ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; | |
9058 | #if !defined(CONFIG_USER_ONLY) | |
9059 | sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; | |
9060 | sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; | |
9061 | if (sw || sr || uw || ur) { | |
9062 | printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", | |
9063 | (i << 5) | j, (i << 5) | j, spr->name, | |
9064 | sw ? 'w' : '-', sr ? 'r' : '-', | |
9065 | uw ? 'w' : '-', ur ? 'r' : '-'); | |
9066 | } | |
9067 | #else | |
9068 | if (uw || ur) { | |
9069 | printf("SPR: %4d (%03x) %-8s u%c%c\n", | |
9070 | (i << 5) | j, (i << 5) | j, spr->name, | |
9071 | uw ? 'w' : '-', ur ? 'r' : '-'); | |
9072 | } | |
9073 | #endif | |
9074 | } | |
9075 | } | |
9076 | fflush(stdout); | |
9077 | fflush(stderr); | |
9078 | } | |
9079 | #endif | |
9080 | ||
9081 | /*****************************************************************************/ | |
9082 | #include <stdlib.h> | |
9083 | #include <string.h> | |
9084 | ||
a750fc0b JM |
9085 | /* Opcode types */ |
9086 | enum { | |
9087 | PPC_DIRECT = 0, /* Opcode routine */ | |
9088 | PPC_INDIRECT = 1, /* Indirect opcode table */ | |
9089 | }; | |
9090 | ||
9091 | static inline int is_indirect_opcode (void *handler) | |
9092 | { | |
9093 | return ((unsigned long)handler & 0x03) == PPC_INDIRECT; | |
9094 | } | |
9095 | ||
9096 | static inline opc_handler_t **ind_table(void *handler) | |
9097 | { | |
9098 | return (opc_handler_t **)((unsigned long)handler & ~3); | |
9099 | } | |
9100 | ||
9101 | /* Instruction table creation */ | |
9102 | /* Opcodes tables creation */ | |
9103 | static void fill_new_table (opc_handler_t **table, int len) | |
9104 | { | |
9105 | int i; | |
9106 | ||
9107 | for (i = 0; i < len; i++) | |
9108 | table[i] = &invalid_handler; | |
9109 | } | |
9110 | ||
9111 | static int create_new_table (opc_handler_t **table, unsigned char idx) | |
9112 | { | |
9113 | opc_handler_t **tmp; | |
9114 | ||
9115 | tmp = malloc(0x20 * sizeof(opc_handler_t)); | |
a750fc0b JM |
9116 | fill_new_table(tmp, 0x20); |
9117 | table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); | |
9118 | ||
9119 | return 0; | |
9120 | } | |
9121 | ||
9122 | static int insert_in_table (opc_handler_t **table, unsigned char idx, | |
9123 | opc_handler_t *handler) | |
9124 | { | |
9125 | if (table[idx] != &invalid_handler) | |
9126 | return -1; | |
9127 | table[idx] = handler; | |
9128 | ||
9129 | return 0; | |
9130 | } | |
9131 | ||
9132 | static int register_direct_insn (opc_handler_t **ppc_opcodes, | |
9133 | unsigned char idx, opc_handler_t *handler) | |
9134 | { | |
9135 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { | |
9136 | printf("*** ERROR: opcode %02x already assigned in main " | |
9137 | "opcode table\n", idx); | |
4c1b1bfe JM |
9138 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
9139 | printf(" Registered handler '%s' - new handler '%s'\n", | |
9140 | ppc_opcodes[idx]->oname, handler->oname); | |
9141 | #endif | |
a750fc0b JM |
9142 | return -1; |
9143 | } | |
9144 | ||
9145 | return 0; | |
9146 | } | |
9147 | ||
9148 | static int register_ind_in_table (opc_handler_t **table, | |
9149 | unsigned char idx1, unsigned char idx2, | |
9150 | opc_handler_t *handler) | |
9151 | { | |
9152 | if (table[idx1] == &invalid_handler) { | |
9153 | if (create_new_table(table, idx1) < 0) { | |
9154 | printf("*** ERROR: unable to create indirect table " | |
9155 | "idx=%02x\n", idx1); | |
9156 | return -1; | |
9157 | } | |
9158 | } else { | |
9159 | if (!is_indirect_opcode(table[idx1])) { | |
9160 | printf("*** ERROR: idx %02x already assigned to a direct " | |
9161 | "opcode\n", idx1); | |
4c1b1bfe JM |
9162 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
9163 | printf(" Registered handler '%s' - new handler '%s'\n", | |
9164 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
9165 | #endif | |
a750fc0b JM |
9166 | return -1; |
9167 | } | |
3a607854 | 9168 | } |
a750fc0b JM |
9169 | if (handler != NULL && |
9170 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { | |
9171 | printf("*** ERROR: opcode %02x already assigned in " | |
9172 | "opcode table %02x\n", idx2, idx1); | |
4c1b1bfe JM |
9173 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
9174 | printf(" Registered handler '%s' - new handler '%s'\n", | |
9175 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
9176 | #endif | |
a750fc0b | 9177 | return -1; |
3a607854 | 9178 | } |
a750fc0b JM |
9179 | |
9180 | return 0; | |
9181 | } | |
9182 | ||
9183 | static int register_ind_insn (opc_handler_t **ppc_opcodes, | |
9184 | unsigned char idx1, unsigned char idx2, | |
9185 | opc_handler_t *handler) | |
9186 | { | |
9187 | int ret; | |
9188 | ||
9189 | ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); | |
9190 | ||
9191 | return ret; | |
9192 | } | |
9193 | ||
9194 | static int register_dblind_insn (opc_handler_t **ppc_opcodes, | |
9195 | unsigned char idx1, unsigned char idx2, | |
9196 | unsigned char idx3, opc_handler_t *handler) | |
9197 | { | |
9198 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
9199 | printf("*** ERROR: unable to join indirect table idx " | |
9200 | "[%02x-%02x]\n", idx1, idx2); | |
9201 | return -1; | |
9202 | } | |
9203 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, | |
9204 | handler) < 0) { | |
9205 | printf("*** ERROR: unable to insert opcode " | |
9206 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
9207 | return -1; | |
9208 | } | |
9209 | ||
9210 | return 0; | |
9211 | } | |
9212 | ||
9213 | static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) | |
9214 | { | |
9215 | if (insn->opc2 != 0xFF) { | |
9216 | if (insn->opc3 != 0xFF) { | |
9217 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
9218 | insn->opc3, &insn->handler) < 0) | |
9219 | return -1; | |
9220 | } else { | |
9221 | if (register_ind_insn(ppc_opcodes, insn->opc1, | |
9222 | insn->opc2, &insn->handler) < 0) | |
9223 | return -1; | |
9224 | } | |
9225 | } else { | |
9226 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) | |
9227 | return -1; | |
9228 | } | |
9229 | ||
9230 | return 0; | |
9231 | } | |
9232 | ||
9233 | static int test_opcode_table (opc_handler_t **table, int len) | |
9234 | { | |
9235 | int i, count, tmp; | |
9236 | ||
9237 | for (i = 0, count = 0; i < len; i++) { | |
9238 | /* Consistency fixup */ | |
9239 | if (table[i] == NULL) | |
9240 | table[i] = &invalid_handler; | |
9241 | if (table[i] != &invalid_handler) { | |
9242 | if (is_indirect_opcode(table[i])) { | |
9243 | tmp = test_opcode_table(ind_table(table[i]), 0x20); | |
9244 | if (tmp == 0) { | |
9245 | free(table[i]); | |
9246 | table[i] = &invalid_handler; | |
9247 | } else { | |
9248 | count++; | |
9249 | } | |
9250 | } else { | |
9251 | count++; | |
9252 | } | |
9253 | } | |
9254 | } | |
9255 | ||
9256 | return count; | |
9257 | } | |
9258 | ||
9259 | static void fix_opcode_tables (opc_handler_t **ppc_opcodes) | |
9260 | { | |
9261 | if (test_opcode_table(ppc_opcodes, 0x40) == 0) | |
9262 | printf("*** WARNING: no opcode defined !\n"); | |
9263 | } | |
9264 | ||
9265 | /*****************************************************************************/ | |
aaed909a | 9266 | static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def) |
a750fc0b | 9267 | { |
5c55ff99 | 9268 | opcode_t *opc; |
a750fc0b JM |
9269 | |
9270 | fill_new_table(env->opcodes, 0x40); | |
5c55ff99 | 9271 | for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { |
a750fc0b JM |
9272 | if ((opc->handler.type & def->insns_flags) != 0) { |
9273 | if (register_insn(env->opcodes, opc) < 0) { | |
9274 | printf("*** ERROR initializing PowerPC instruction " | |
9275 | "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2, | |
9276 | opc->opc3); | |
9277 | return -1; | |
9278 | } | |
9279 | } | |
9280 | } | |
9281 | fix_opcode_tables(env->opcodes); | |
9282 | fflush(stdout); | |
9283 | fflush(stderr); | |
9284 | ||
9285 | return 0; | |
9286 | } | |
9287 | ||
9288 | #if defined(PPC_DUMP_CPU) | |
25ba3a68 | 9289 | static void dump_ppc_insns (CPUPPCState *env) |
a750fc0b JM |
9290 | { |
9291 | opc_handler_t **table, *handler; | |
b55266b5 | 9292 | const char *p, *q; |
a750fc0b JM |
9293 | uint8_t opc1, opc2, opc3; |
9294 | ||
9295 | printf("Instructions set:\n"); | |
9296 | /* opc1 is 6 bits long */ | |
9297 | for (opc1 = 0x00; opc1 < 0x40; opc1++) { | |
9298 | table = env->opcodes; | |
9299 | handler = table[opc1]; | |
9300 | if (is_indirect_opcode(handler)) { | |
9301 | /* opc2 is 5 bits long */ | |
9302 | for (opc2 = 0; opc2 < 0x20; opc2++) { | |
9303 | table = env->opcodes; | |
9304 | handler = env->opcodes[opc1]; | |
9305 | table = ind_table(handler); | |
9306 | handler = table[opc2]; | |
9307 | if (is_indirect_opcode(handler)) { | |
9308 | table = ind_table(handler); | |
9309 | /* opc3 is 5 bits long */ | |
9310 | for (opc3 = 0; opc3 < 0x20; opc3++) { | |
9311 | handler = table[opc3]; | |
9312 | if (handler->handler != &gen_invalid) { | |
4c1b1bfe JM |
9313 | /* Special hack to properly dump SPE insns */ |
9314 | p = strchr(handler->oname, '_'); | |
9315 | if (p == NULL) { | |
9316 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
9317 | "%s\n", | |
9318 | opc1, opc2, opc3, opc1, | |
9319 | (opc3 << 5) | opc2, | |
9320 | handler->oname); | |
9321 | } else { | |
9322 | q = "speundef"; | |
9323 | if ((p - handler->oname) != strlen(q) || | |
9324 | memcmp(handler->oname, q, strlen(q)) != 0) { | |
9325 | /* First instruction */ | |
9326 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
9327 | "%.*s\n", | |
9328 | opc1, opc2 << 1, opc3, opc1, | |
9329 | (opc3 << 6) | (opc2 << 1), | |
9330 | (int)(p - handler->oname), | |
9331 | handler->oname); | |
9332 | } | |
9333 | if (strcmp(p + 1, q) != 0) { | |
9334 | /* Second instruction */ | |
9335 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
9336 | "%s\n", | |
9337 | opc1, (opc2 << 1) | 1, opc3, opc1, | |
9338 | (opc3 << 6) | (opc2 << 1) | 1, | |
9339 | p + 1); | |
9340 | } | |
9341 | } | |
a750fc0b JM |
9342 | } |
9343 | } | |
9344 | } else { | |
9345 | if (handler->handler != &gen_invalid) { | |
9346 | printf("INSN: %02x %02x -- (%02d %04d) : %s\n", | |
9347 | opc1, opc2, opc1, opc2, handler->oname); | |
9348 | } | |
9349 | } | |
9350 | } | |
9351 | } else { | |
9352 | if (handler->handler != &gen_invalid) { | |
9353 | printf("INSN: %02x -- -- (%02d ----) : %s\n", | |
9354 | opc1, opc1, handler->oname); | |
9355 | } | |
9356 | } | |
9357 | } | |
9358 | } | |
3a607854 | 9359 | #endif |
a750fc0b | 9360 | |
24951522 AJ |
9361 | static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n) |
9362 | { | |
9363 | if (n < 32) { | |
9364 | stfq_p(mem_buf, env->fpr[n]); | |
9365 | return 8; | |
9366 | } | |
9367 | if (n == 32) { | |
9368 | /* FPSCR not implemented */ | |
9369 | memset(mem_buf, 0, 4); | |
9370 | return 4; | |
9371 | } | |
9372 | return 0; | |
9373 | } | |
9374 | ||
9375 | static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n) | |
9376 | { | |
9377 | if (n < 32) { | |
9378 | env->fpr[n] = ldfq_p(mem_buf); | |
9379 | return 8; | |
9380 | } | |
9381 | if (n == 32) { | |
9382 | /* FPSCR not implemented */ | |
9383 | return 4; | |
9384 | } | |
9385 | return 0; | |
9386 | } | |
9387 | ||
b4f8d821 AJ |
9388 | static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n) |
9389 | { | |
9390 | if (n < 32) { | |
9391 | #ifdef WORDS_BIGENDIAN | |
9392 | stq_p(mem_buf, env->avr[n].u64[0]); | |
9393 | stq_p(mem_buf+8, env->avr[n].u64[1]); | |
9394 | #else | |
9395 | stq_p(mem_buf, env->avr[n].u64[1]); | |
9396 | stq_p(mem_buf+8, env->avr[n].u64[0]); | |
9397 | #endif | |
9398 | return 16; | |
9399 | } | |
70976a79 | 9400 | if (n == 32) { |
b4f8d821 AJ |
9401 | stl_p(mem_buf, env->vscr); |
9402 | return 4; | |
9403 | } | |
70976a79 | 9404 | if (n == 33) { |
b4f8d821 AJ |
9405 | stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); |
9406 | return 4; | |
9407 | } | |
9408 | return 0; | |
9409 | } | |
9410 | ||
9411 | static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n) | |
9412 | { | |
9413 | if (n < 32) { | |
9414 | #ifdef WORDS_BIGENDIAN | |
9415 | env->avr[n].u64[0] = ldq_p(mem_buf); | |
9416 | env->avr[n].u64[1] = ldq_p(mem_buf+8); | |
9417 | #else | |
9418 | env->avr[n].u64[1] = ldq_p(mem_buf); | |
9419 | env->avr[n].u64[0] = ldq_p(mem_buf+8); | |
9420 | #endif | |
9421 | return 16; | |
9422 | } | |
70976a79 | 9423 | if (n == 32) { |
b4f8d821 AJ |
9424 | env->vscr = ldl_p(mem_buf); |
9425 | return 4; | |
9426 | } | |
70976a79 | 9427 | if (n == 33) { |
b4f8d821 AJ |
9428 | env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); |
9429 | return 4; | |
9430 | } | |
9431 | return 0; | |
9432 | } | |
9433 | ||
688890f7 AJ |
9434 | static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n) |
9435 | { | |
9436 | if (n < 32) { | |
9437 | #if defined(TARGET_PPC64) | |
9438 | stl_p(mem_buf, env->gpr[n] >> 32); | |
9439 | #else | |
9440 | stl_p(mem_buf, env->gprh[n]); | |
9441 | #endif | |
9442 | return 4; | |
9443 | } | |
70976a79 | 9444 | if (n == 32) { |
688890f7 AJ |
9445 | stq_p(mem_buf, env->spe_acc); |
9446 | return 8; | |
9447 | } | |
70976a79 | 9448 | if (n == 33) { |
d34defbc | 9449 | stl_p(mem_buf, env->spe_fscr); |
688890f7 AJ |
9450 | return 4; |
9451 | } | |
9452 | return 0; | |
9453 | } | |
9454 | ||
9455 | static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) | |
9456 | { | |
9457 | if (n < 32) { | |
9458 | #if defined(TARGET_PPC64) | |
9459 | target_ulong lo = (uint32_t)env->gpr[n]; | |
9460 | target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32; | |
9461 | env->gpr[n] = lo | hi; | |
9462 | #else | |
9463 | env->gprh[n] = ldl_p(mem_buf); | |
9464 | #endif | |
9465 | return 4; | |
9466 | } | |
70976a79 | 9467 | if (n == 32) { |
688890f7 AJ |
9468 | env->spe_acc = ldq_p(mem_buf); |
9469 | return 8; | |
9470 | } | |
70976a79 | 9471 | if (n == 33) { |
d34defbc | 9472 | env->spe_fscr = ldl_p(mem_buf); |
688890f7 AJ |
9473 | return 4; |
9474 | } | |
9475 | return 0; | |
9476 | } | |
9477 | ||
aaed909a | 9478 | int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) |
a750fc0b JM |
9479 | { |
9480 | env->msr_mask = def->msr_mask; | |
9481 | env->mmu_model = def->mmu_model; | |
9482 | env->excp_model = def->excp_model; | |
9483 | env->bus_model = def->bus_model; | |
c29b735c | 9484 | env->insns_flags = def->insns_flags; |
d26bfc9a | 9485 | env->flags = def->flags; |
237c0af0 | 9486 | env->bfd_mach = def->bfd_mach; |
2f462816 | 9487 | env->check_pow = def->check_pow; |
a750fc0b JM |
9488 | if (create_ppc_opcodes(env, def) < 0) |
9489 | return -1; | |
9490 | init_ppc_proc(env, def); | |
24951522 AJ |
9491 | |
9492 | if (def->insns_flags & PPC_FLOAT) { | |
9493 | gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg, | |
9494 | 33, "power-fpu.xml", 0); | |
9495 | } | |
b4f8d821 AJ |
9496 | if (def->insns_flags & PPC_ALTIVEC) { |
9497 | gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, | |
9498 | 34, "power-altivec.xml", 0); | |
9499 | } | |
40569b7e | 9500 | if (def->insns_flags & PPC_SPE) { |
688890f7 AJ |
9501 | gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg, |
9502 | 34, "power-spe.xml", 0); | |
9503 | } | |
9504 | ||
a750fc0b | 9505 | #if defined(PPC_DUMP_CPU) |
3a607854 | 9506 | { |
b55266b5 | 9507 | const char *mmu_model, *excp_model, *bus_model; |
a750fc0b JM |
9508 | switch (env->mmu_model) { |
9509 | case POWERPC_MMU_32B: | |
9510 | mmu_model = "PowerPC 32"; | |
9511 | break; | |
a750fc0b JM |
9512 | case POWERPC_MMU_SOFT_6xx: |
9513 | mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; | |
9514 | break; | |
9515 | case POWERPC_MMU_SOFT_74xx: | |
9516 | mmu_model = "PowerPC 74xx with software driven TLBs"; | |
9517 | break; | |
9518 | case POWERPC_MMU_SOFT_4xx: | |
9519 | mmu_model = "PowerPC 4xx with software driven TLBs"; | |
9520 | break; | |
9521 | case POWERPC_MMU_SOFT_4xx_Z: | |
9522 | mmu_model = "PowerPC 4xx with software driven TLBs " | |
9523 | "and zones protections"; | |
9524 | break; | |
b4095fed JM |
9525 | case POWERPC_MMU_REAL: |
9526 | mmu_model = "PowerPC real mode only"; | |
9527 | break; | |
9528 | case POWERPC_MMU_MPC8xx: | |
9529 | mmu_model = "PowerPC MPC8xx"; | |
a750fc0b JM |
9530 | break; |
9531 | case POWERPC_MMU_BOOKE: | |
9532 | mmu_model = "PowerPC BookE"; | |
9533 | break; | |
9534 | case POWERPC_MMU_BOOKE_FSL: | |
9535 | mmu_model = "PowerPC BookE FSL"; | |
9536 | break; | |
b4095fed JM |
9537 | case POWERPC_MMU_601: |
9538 | mmu_model = "PowerPC 601"; | |
9539 | break; | |
00af685f JM |
9540 | #if defined (TARGET_PPC64) |
9541 | case POWERPC_MMU_64B: | |
9542 | mmu_model = "PowerPC 64"; | |
9543 | break; | |
add78955 JM |
9544 | case POWERPC_MMU_620: |
9545 | mmu_model = "PowerPC 620"; | |
9546 | break; | |
00af685f | 9547 | #endif |
a750fc0b JM |
9548 | default: |
9549 | mmu_model = "Unknown or invalid"; | |
9550 | break; | |
9551 | } | |
9552 | switch (env->excp_model) { | |
9553 | case POWERPC_EXCP_STD: | |
9554 | excp_model = "PowerPC"; | |
9555 | break; | |
9556 | case POWERPC_EXCP_40x: | |
9557 | excp_model = "PowerPC 40x"; | |
9558 | break; | |
9559 | case POWERPC_EXCP_601: | |
9560 | excp_model = "PowerPC 601"; | |
9561 | break; | |
9562 | case POWERPC_EXCP_602: | |
9563 | excp_model = "PowerPC 602"; | |
9564 | break; | |
9565 | case POWERPC_EXCP_603: | |
9566 | excp_model = "PowerPC 603"; | |
9567 | break; | |
9568 | case POWERPC_EXCP_603E: | |
9569 | excp_model = "PowerPC 603e"; | |
9570 | break; | |
9571 | case POWERPC_EXCP_604: | |
9572 | excp_model = "PowerPC 604"; | |
9573 | break; | |
9574 | case POWERPC_EXCP_7x0: | |
9575 | excp_model = "PowerPC 740/750"; | |
9576 | break; | |
9577 | case POWERPC_EXCP_7x5: | |
9578 | excp_model = "PowerPC 745/755"; | |
9579 | break; | |
9580 | case POWERPC_EXCP_74xx: | |
9581 | excp_model = "PowerPC 74xx"; | |
9582 | break; | |
a750fc0b JM |
9583 | case POWERPC_EXCP_BOOKE: |
9584 | excp_model = "PowerPC BookE"; | |
9585 | break; | |
00af685f JM |
9586 | #if defined (TARGET_PPC64) |
9587 | case POWERPC_EXCP_970: | |
9588 | excp_model = "PowerPC 970"; | |
9589 | break; | |
9590 | #endif | |
a750fc0b JM |
9591 | default: |
9592 | excp_model = "Unknown or invalid"; | |
9593 | break; | |
9594 | } | |
9595 | switch (env->bus_model) { | |
9596 | case PPC_FLAGS_INPUT_6xx: | |
9597 | bus_model = "PowerPC 6xx"; | |
9598 | break; | |
9599 | case PPC_FLAGS_INPUT_BookE: | |
9600 | bus_model = "PowerPC BookE"; | |
9601 | break; | |
9602 | case PPC_FLAGS_INPUT_405: | |
9603 | bus_model = "PowerPC 405"; | |
9604 | break; | |
a750fc0b JM |
9605 | case PPC_FLAGS_INPUT_401: |
9606 | bus_model = "PowerPC 401/403"; | |
9607 | break; | |
b4095fed JM |
9608 | case PPC_FLAGS_INPUT_RCPU: |
9609 | bus_model = "RCPU / MPC8xx"; | |
9610 | break; | |
00af685f JM |
9611 | #if defined (TARGET_PPC64) |
9612 | case PPC_FLAGS_INPUT_970: | |
9613 | bus_model = "PowerPC 970"; | |
9614 | break; | |
9615 | #endif | |
a750fc0b JM |
9616 | default: |
9617 | bus_model = "Unknown or invalid"; | |
9618 | break; | |
9619 | } | |
9620 | printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" | |
9621 | " MMU model : %s\n", | |
9622 | def->name, def->pvr, def->msr_mask, mmu_model); | |
f2e63a42 | 9623 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
9624 | if (env->tlb != NULL) { |
9625 | printf(" %d %s TLB in %d ways\n", | |
9626 | env->nb_tlb, env->id_tlbs ? "splitted" : "merged", | |
9627 | env->nb_ways); | |
9628 | } | |
f2e63a42 | 9629 | #endif |
a750fc0b JM |
9630 | printf(" Exceptions model : %s\n" |
9631 | " Bus model : %s\n", | |
9632 | excp_model, bus_model); | |
25ba3a68 JM |
9633 | printf(" MSR features :\n"); |
9634 | if (env->flags & POWERPC_FLAG_SPE) | |
9635 | printf(" signal processing engine enable" | |
9636 | "\n"); | |
9637 | else if (env->flags & POWERPC_FLAG_VRE) | |
9638 | printf(" vector processor enable\n"); | |
9639 | if (env->flags & POWERPC_FLAG_TGPR) | |
9640 | printf(" temporary GPRs\n"); | |
9641 | else if (env->flags & POWERPC_FLAG_CE) | |
9642 | printf(" critical input enable\n"); | |
9643 | if (env->flags & POWERPC_FLAG_SE) | |
9644 | printf(" single-step trace mode\n"); | |
9645 | else if (env->flags & POWERPC_FLAG_DWE) | |
9646 | printf(" debug wait enable\n"); | |
9647 | else if (env->flags & POWERPC_FLAG_UBLE) | |
9648 | printf(" user BTB lock enable\n"); | |
9649 | if (env->flags & POWERPC_FLAG_BE) | |
9650 | printf(" branch-step trace mode\n"); | |
9651 | else if (env->flags & POWERPC_FLAG_DE) | |
9652 | printf(" debug interrupt enable\n"); | |
9653 | if (env->flags & POWERPC_FLAG_PX) | |
9654 | printf(" inclusive protection\n"); | |
9655 | else if (env->flags & POWERPC_FLAG_PMM) | |
9656 | printf(" performance monitor mark\n"); | |
9657 | if (env->flags == POWERPC_FLAG_NONE) | |
9658 | printf(" none\n"); | |
4018bae9 JM |
9659 | printf(" Time-base/decrementer clock source: %s\n", |
9660 | env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); | |
a750fc0b JM |
9661 | } |
9662 | dump_ppc_insns(env); | |
9663 | dump_ppc_sprs(env); | |
9664 | fflush(stdout); | |
3a607854 | 9665 | #endif |
a750fc0b JM |
9666 | |
9667 | return 0; | |
9668 | } | |
3fc6c082 | 9669 | |
ee4e83ed | 9670 | static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr) |
3fc6c082 | 9671 | { |
ee4e83ed JM |
9672 | const ppc_def_t *ret; |
9673 | uint32_t pvr_rev; | |
9674 | int i, best, match, best_match, max; | |
3fc6c082 | 9675 | |
ee4e83ed | 9676 | ret = NULL; |
b1503cda | 9677 | max = ARRAY_SIZE(ppc_defs); |
ee4e83ed JM |
9678 | best = -1; |
9679 | pvr_rev = pvr & 0xFFFF; | |
9680 | /* We want all specified bits to match */ | |
9681 | best_match = 32 - ctz32(pvr_rev); | |
068abdc8 | 9682 | for (i = 0; i < max; i++) { |
ee4e83ed JM |
9683 | /* We check that the 16 higher bits are the same to ensure the CPU |
9684 | * model will be the choosen one. | |
9685 | */ | |
9686 | if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) { | |
9687 | /* We want as much as possible of the low-level 16 bits | |
9688 | * to be the same but we allow inexact matches. | |
9689 | */ | |
9690 | match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF)); | |
9691 | /* We check '>=' instead of '>' because the PPC_defs table | |
9692 | * is ordered by increasing revision. | |
4c1b1bfe | 9693 | * Then, we will match the higher revision compatible |
ee4e83ed JM |
9694 | * with the requested PVR |
9695 | */ | |
9696 | if (match >= best_match) { | |
9697 | best = i; | |
9698 | best_match = match; | |
9699 | } | |
3fc6c082 FB |
9700 | } |
9701 | } | |
ee4e83ed JM |
9702 | if (best != -1) |
9703 | ret = &ppc_defs[best]; | |
9704 | ||
9705 | return ret; | |
3fc6c082 FB |
9706 | } |
9707 | ||
ee4e83ed | 9708 | #include <ctype.h> |
3fc6c082 | 9709 | |
b55266b5 | 9710 | const ppc_def_t *cpu_ppc_find_by_name (const char *name) |
ee4e83ed JM |
9711 | { |
9712 | const ppc_def_t *ret; | |
b55266b5 | 9713 | const char *p; |
ee4e83ed JM |
9714 | int i, max, len; |
9715 | ||
9716 | /* Check if the given name is a PVR */ | |
9717 | len = strlen(name); | |
9718 | if (len == 10 && name[0] == '0' && name[1] == 'x') { | |
9719 | p = name + 2; | |
9720 | goto check_pvr; | |
9721 | } else if (len == 8) { | |
9722 | p = name; | |
9723 | check_pvr: | |
9724 | for (i = 0; i < 8; i++) { | |
cd390083 | 9725 | if (!qemu_isxdigit(*p++)) |
ee4e83ed JM |
9726 | break; |
9727 | } | |
9728 | if (i == 8) | |
9729 | return ppc_find_by_pvr(strtoul(name, NULL, 16)); | |
9730 | } | |
9731 | ret = NULL; | |
b1503cda | 9732 | max = ARRAY_SIZE(ppc_defs); |
068abdc8 | 9733 | for (i = 0; i < max; i++) { |
ee4e83ed JM |
9734 | if (strcasecmp(name, ppc_defs[i].name) == 0) { |
9735 | ret = &ppc_defs[i]; | |
9736 | break; | |
3fc6c082 FB |
9737 | } |
9738 | } | |
ee4e83ed JM |
9739 | |
9740 | return ret; | |
3fc6c082 FB |
9741 | } |
9742 | ||
9743 | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
9744 | { | |
068abdc8 | 9745 | int i, max; |
3fc6c082 | 9746 | |
b1503cda | 9747 | max = ARRAY_SIZE(ppc_defs); |
068abdc8 | 9748 | for (i = 0; i < max; i++) { |
a750fc0b JM |
9749 | (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n", |
9750 | ppc_defs[i].name, ppc_defs[i].pvr); | |
3fc6c082 FB |
9751 | } |
9752 | } |