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Clean up slb_lookup() function
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 18 */
19
20/* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
237c0af0 25#include "dis-asm.h"
4e47ea67 26#include "gdbstub.h"
237c0af0 27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
80d11f44
JM		 30//#define PPC_DUMP_SPR_ACCESSES
31#if defined(CONFIG_USER_ONLY)
32#define TODO_USER_ONLY 1
33#endif
3fc6c082 34
c227f099 35struct ppc_def_t {
b55266b5 36 const char *name;
3fc6c082 37 uint32_t pvr;
80d11f44 38 uint32_t svr;
0487d6a8 39 uint64_t insns_flags;
3fc6c082 40 uint64_t msr_mask;
c227f099
AL		 41 powerpc_mmu_t mmu_model;
42 powerpc_excp_t excp_model;
43 powerpc_input_t bus_model;
d26bfc9a 44 uint32_t flags;
237c0af0 45 int bfd_mach;
a750fc0b 46 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 47 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 48};
49
e9df014c
JM		 50/* For user-mode emulation, we don't emulate any IRQ controller */
51#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 52#define PPC_IRQ_INIT_FN(name) \
53static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
54{ \
e9df014c
JM		 55}
56#else
a750fc0b 57#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 58void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
59#endif
a750fc0b 60
4e290a0b 61PPC_IRQ_INIT_FN(40x);
e9df014c 62PPC_IRQ_INIT_FN(6xx);
d0dfae6e 63PPC_IRQ_INIT_FN(970);
9fdc60bf 64PPC_IRQ_INIT_FN(e500);
e9df014c 65
3fc6c082
FB		 66/* Generic callbacks:
67 * do nothing but store/retrieve spr value
68 */
45d827d2 69static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 70{
45d827d2
AJ		 71 gen_load_spr(cpu_gpr[gprn], sprn);
72#ifdef PPC_DUMP_SPR_ACCESSES
73 {
74 TCGv t0 = tcg_const_i32(sprn);
75 gen_helper_load_dump_spr(t0);
76 tcg_temp_free_i32(t0);
77 }
78#endif
a496775f
JM		 79}
80
45d827d2 81static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 82{
45d827d2
AJ		 83 gen_store_spr(sprn, cpu_gpr[gprn]);
84#ifdef PPC_DUMP_SPR_ACCESSES
85 {
86 TCGv t0 = tcg_const_i32(sprn);
87 gen_helper_store_dump_spr(t0);
88 tcg_temp_free_i32(t0);
89 }
04f20795 90#endif
45d827d2 91}
a496775f
JM		 92
93#if !defined(CONFIG_USER_ONLY)
45d827d2 94static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 95{
45d827d2
AJ		 96 TCGv t0 = tcg_temp_new();
97 TCGv t1 = tcg_temp_new();
98 gen_load_spr(t0, sprn);
99 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
100 tcg_gen_and_tl(t0, t0, t1);
101 gen_store_spr(sprn, t0);
102 tcg_temp_free(t0);
103 tcg_temp_free(t1);
a496775f
JM		 104}
105#endif
106
76a66253 107/* SPR common to all PowerPC */
3fc6c082 108/* XER */
45d827d2 109static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 110{
45d827d2 111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 112}
113
45d827d2 114static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 115{
45d827d2 116 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 117}
118
119/* LR */
45d827d2 120static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 121{
45d827d2 122 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 123}
124
45d827d2 125static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 126{
45d827d2 127 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 128}
129
130/* CTR */
45d827d2 131static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 132{
45d827d2 133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 134}
135
45d827d2 136static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 137{
45d827d2 138 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 139}
140
141/* User read access to SPR */
142/* USPRx */
143/* UMMCRx */
144/* UPMCx */
145/* USIA */
146/* UDECR */
45d827d2 147static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 148{
45d827d2 149 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 150}
151
76a66253 152/* SPR common to all non-embedded PowerPC */
3fc6c082 153/* DECR */
76a66253 154#if !defined(CONFIG_USER_ONLY)
45d827d2 155static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 156{
630ecca0
TG		 157 if (use_icount) {
158 gen_io_start();
159 }
45d827d2 160 gen_helper_load_decr(cpu_gpr[gprn]);
630ecca0
TG		 161 if (use_icount) {
162 gen_io_end();
163 gen_stop_exception(opaque);
164 }
3fc6c082
FB		 165}
166
45d827d2 167static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 168{
630ecca0
TG		 169 if (use_icount) {
170 gen_io_start();
171 }
45d827d2 172 gen_helper_store_decr(cpu_gpr[gprn]);
630ecca0
TG		 173 if (use_icount) {
174 gen_io_end();
175 gen_stop_exception(opaque);
176 }
3fc6c082 177}
76a66253 178#endif
3fc6c082 179
76a66253 180/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 181/* Time base */
45d827d2 182static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 183{
630ecca0
TG		 184 if (use_icount) {
185 gen_io_start();
186 }
45d827d2 187 gen_helper_load_tbl(cpu_gpr[gprn]);
630ecca0
TG		 188 if (use_icount) {
189 gen_io_end();
190 gen_stop_exception(opaque);
191 }
3fc6c082
FB		 192}
193
45d827d2 194static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 195{
630ecca0
TG		 196 if (use_icount) {
197 gen_io_start();
198 }
45d827d2 199 gen_helper_load_tbu(cpu_gpr[gprn]);
630ecca0
TG		 200 if (use_icount) {
201 gen_io_end();
202 gen_stop_exception(opaque);
203 }
3fc6c082
FB		 204}
205
a062e36c 206__attribute__ (( unused ))
45d827d2 207static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 208{
45d827d2 209 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 210}
211
212__attribute__ (( unused ))
45d827d2 213static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 214{
45d827d2 215 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 216}
217
76a66253 218#if !defined(CONFIG_USER_ONLY)
45d827d2 219static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 220{
630ecca0
TG		 221 if (use_icount) {
222 gen_io_start();
223 }
45d827d2 224 gen_helper_store_tbl(cpu_gpr[gprn]);
630ecca0
TG		 225 if (use_icount) {
226 gen_io_end();
227 gen_stop_exception(opaque);
228 }
3fc6c082
FB		 229}
230
45d827d2 231static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 232{
630ecca0
TG		 233 if (use_icount) {
234 gen_io_start();
235 }
45d827d2 236 gen_helper_store_tbu(cpu_gpr[gprn]);
630ecca0
TG		 237 if (use_icount) {
238 gen_io_end();
239 gen_stop_exception(opaque);
240 }
3fc6c082 241}
a062e36c
JM		 242
243__attribute__ (( unused ))
45d827d2 244static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 245{
45d827d2 246 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 247}
248
249__attribute__ (( unused ))
45d827d2 250static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 251{
45d827d2 252 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 253}
3a7f009a
DG		 254
255#if defined(TARGET_PPC64)
256__attribute__ (( unused ))
257static void spr_read_purr (void *opaque, int gprn, int sprn)
258{
259 gen_helper_load_purr(cpu_gpr[gprn]);
260}
261#endif
76a66253 262#endif
3fc6c082 263
76a66253 264#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 265/* IBAT0U...IBAT0U */
266/* IBAT0L...IBAT7L */
45d827d2 267static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 268{
45d827d2 269 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 270}
271
45d827d2 272static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 273{
45d827d2 274 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 275}
276
45d827d2 277static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 278{
45d827d2
AJ		 279 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
280 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
281 tcg_temp_free_i32(t0);
3fc6c082
FB		 282}
283
45d827d2 284static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 285{
8daf1781 286 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
45d827d2
AJ		 287 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
288 tcg_temp_free_i32(t0);
3fc6c082
FB		 289}
290
45d827d2 291static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 292{
45d827d2
AJ		 293 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
294 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
295 tcg_temp_free_i32(t0);
3fc6c082
FB		 296}
297
45d827d2 298static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 299{
8daf1781 300 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
45d827d2
AJ		 301 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
302 tcg_temp_free_i32(t0);
3fc6c082
FB		 303}
304
305/* DBAT0U...DBAT7U */
306/* DBAT0L...DBAT7L */
45d827d2 307static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 308{
45d827d2 309 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 310}
311
45d827d2 312static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 313{
45d827d2 314 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 315}
316
45d827d2 317static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 318{
45d827d2
AJ		 319 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
320 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
321 tcg_temp_free_i32(t0);
3fc6c082
FB		 322}
323
45d827d2 324static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 325{
45d827d2
AJ		 326 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
327 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
328 tcg_temp_free_i32(t0);
3fc6c082
FB		 329}
330
45d827d2 331static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 332{
45d827d2
AJ		 333 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
334 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
335 tcg_temp_free_i32(t0);
3fc6c082
FB		 336}
337
45d827d2 338static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 339{
45d827d2
AJ		 340 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
341 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
342 tcg_temp_free_i32(t0);
3fc6c082
FB		 343}
344
345/* SDR1 */
45d827d2 346static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
3fc6c082 347{
45d827d2 348 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
3fc6c082
FB		 349}
350
45d827d2 351static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 352{
45d827d2 353 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 354}
355
76a66253
JM		 356/* 64 bits PowerPC specific SPRs */
357/* ASR */
578bb252 358#if defined(TARGET_PPC64)
2adab7d6
BS		 359static void spr_read_hior (void *opaque, int gprn, int sprn)
360{
361 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
362}
363
364static void spr_write_hior (void *opaque, int sprn, int gprn)
365{
366 TCGv t0 = tcg_temp_new();
367 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
368 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
369 tcg_temp_free(t0);
370}
371
45d827d2 372static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 373{
45d827d2 374 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 375}
376
45d827d2 377static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 378{
45d827d2 379 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 380}
381#endif
a750fc0b 382#endif
76a66253
JM		 383
384/* PowerPC 601 specific registers */
385/* RTC */
45d827d2 386static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 387{
45d827d2 388 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 389}
390
45d827d2 391static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 392{
45d827d2 393 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 394}
395
396#if !defined(CONFIG_USER_ONLY)
45d827d2 397static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 398{
45d827d2 399 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 400}
401
45d827d2 402static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 403{
45d827d2 404 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 405}
056401ea 406
45d827d2 407static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 408{
409 DisasContext *ctx = opaque;
410
45d827d2 411 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 412 /* Must stop the translation as endianness may have changed */
e06fcd75 413 gen_stop_exception(ctx);
056401ea 414}
76a66253
JM		 415#endif
416
417/* Unified bats */
418#if !defined(CONFIG_USER_ONLY)
45d827d2 419static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 420{
45d827d2 421 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 422}
423
45d827d2 424static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 425{
45d827d2
AJ		 426 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
427 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
428 tcg_temp_free_i32(t0);
76a66253
JM		 429}
430
45d827d2 431static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 432{
45d827d2
AJ		 433 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
434 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
435 tcg_temp_free_i32(t0);
76a66253
JM		 436}
437#endif
438
439/* PowerPC 40x specific registers */
440#if !defined(CONFIG_USER_ONLY)
45d827d2 441static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 442{
45d827d2 443 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 444}
445
45d827d2 446static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 447{
45d827d2 448 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 449}
450
45d827d2 451static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 452{
453 DisasContext *ctx = opaque;
454
45d827d2 455 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 456 /* We must stop translation as we may have rebooted */
e06fcd75 457 gen_stop_exception(ctx);
8ecc7913
JM		 458}
459
45d827d2 460static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 461{
45d827d2 462 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 463}
464
45d827d2 465static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 466{
45d827d2 467 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 468}
469
45d827d2 470static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 471{
45d827d2 472 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 473}
474#endif
475
476/* PowerPC 403 specific registers */
477/* PBL1 / PBU1 / PBL2 / PBU2 */
478#if !defined(CONFIG_USER_ONLY)
45d827d2 479static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 480{
45d827d2 481 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 482}
483
45d827d2 484static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 485{
45d827d2
AJ		 486 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
487 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
488 tcg_temp_free_i32(t0);
76a66253
JM		 489}
490
45d827d2 491static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 492{
45d827d2
AJ		 493 TCGv t0 = tcg_temp_new();
494 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
495 gen_store_spr(SPR_PIR, t0);
496 tcg_temp_free(t0);
3fc6c082 497}
76a66253 498#endif
3fc6c082 499
d34defbc
AJ		 500/* SPE specific registers */
501static void spr_read_spefscr (void *opaque, int gprn, int sprn)
502{
503 TCGv_i32 t0 = tcg_temp_new_i32();
515e2f7e 504 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 505 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
506 tcg_temp_free_i32(t0);
507}
508
509static void spr_write_spefscr (void *opaque, int sprn, int gprn)
510{
511 TCGv_i32 t0 = tcg_temp_new_i32();
512 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515e2f7e 513 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 514 tcg_temp_free_i32(t0);
515}
516
6f5d427d
JM		 517#if !defined(CONFIG_USER_ONLY)
518/* Callback used to write the exception vector base */
45d827d2 519static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 520{
45d827d2
AJ		 521 TCGv t0 = tcg_temp_new();
522 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
523 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
524 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
525 gen_store_spr(sprn, t0);
69bd5820 526 tcg_temp_free(t0);
6f5d427d
JM		 527}
528
45d827d2 529static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 530{
531 DisasContext *ctx = opaque;
532
533 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 534 TCGv t0 = tcg_temp_new();
535 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
536 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
537 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
538 gen_store_spr(sprn, t0);
539 tcg_temp_free(t0);
6f5d427d 540 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 541 TCGv t0 = tcg_temp_new();
542 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
543 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
544 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
545 gen_store_spr(sprn, t0);
546 tcg_temp_free(t0);
6f5d427d
JM		 547 } else {
548 printf("Trying to write an unknown exception vector %d %03x\n",
549 sprn, sprn);
e06fcd75 550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 551 }
552}
553#endif
554
cf8358c8
AJ		 555static inline void vscr_init (CPUPPCState *env, uint32_t val)
556{
557 env->vscr = val;
558 /* Altivec always uses round-to-nearest */
559 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
560 set_flush_to_zero(vscr_nj, &env->vec_status);
561}
562
76a66253
JM		 563#if defined(CONFIG_USER_ONLY)
564#define spr_register(env, num, name, uea_read, uea_write, \
565 oea_read, oea_write, initial_value) \
566do { \
567 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
568} while (0)
569static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 570 const char *name,
45d827d2
AJ		 571 void (*uea_read)(void *opaque, int gprn, int sprn),
572 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 573 target_ulong initial_value)
574#else
3fc6c082 575static inline void spr_register (CPUPPCState *env, int num,
b55266b5 576 const char *name,
45d827d2
AJ		 577 void (*uea_read)(void *opaque, int gprn, int sprn),
578 void (*uea_write)(void *opaque, int sprn, int gprn),
579 void (*oea_read)(void *opaque, int gprn, int sprn),
580 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 581 target_ulong initial_value)
76a66253 582#endif
3fc6c082 583{
c227f099 584 ppc_spr_t *spr;
3fc6c082
FB		 585
586 spr = &env->spr_cb[num];
587 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 588#if !defined(CONFIG_USER_ONLY)
589 spr->oea_read != NULL || spr->oea_write != NULL ||
590#endif
591 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 592 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
593 exit(1);
594 }
595#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 596 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
597 name, initial_value);
3fc6c082
FB		 598#endif
599 spr->name = name;
600 spr->uea_read = uea_read;
601 spr->uea_write = uea_write;
76a66253 602#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 603 spr->oea_read = oea_read;
604 spr->oea_write = oea_write;
76a66253 605#endif
3fc6c082
FB		 606 env->spr[num] = initial_value;
607}
608
609/* Generic PowerPC SPRs */
610static void gen_spr_generic (CPUPPCState *env)
611{
612 /* Integer processing */
613 spr_register(env, SPR_XER, "XER",
614 &spr_read_xer, &spr_write_xer,
615 &spr_read_xer, &spr_write_xer,
616 0x00000000);
617 /* Branch contol */
618 spr_register(env, SPR_LR, "LR",
619 &spr_read_lr, &spr_write_lr,
620 &spr_read_lr, &spr_write_lr,
621 0x00000000);
622 spr_register(env, SPR_CTR, "CTR",
623 &spr_read_ctr, &spr_write_ctr,
624 &spr_read_ctr, &spr_write_ctr,
625 0x00000000);
626 /* Interrupt processing */
627 spr_register(env, SPR_SRR0, "SRR0",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_generic, &spr_write_generic,
630 0x00000000);
631 spr_register(env, SPR_SRR1, "SRR1",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_generic, &spr_write_generic,
634 0x00000000);
635 /* Processor control */
636 spr_register(env, SPR_SPRG0, "SPRG0",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_generic, &spr_write_generic,
639 0x00000000);
640 spr_register(env, SPR_SPRG1, "SPRG1",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_generic, &spr_write_generic,
643 0x00000000);
644 spr_register(env, SPR_SPRG2, "SPRG2",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_generic, &spr_write_generic,
647 0x00000000);
648 spr_register(env, SPR_SPRG3, "SPRG3",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652}
653
654/* SPR common to all non-embedded PowerPC, including 601 */
655static void gen_spr_ne_601 (CPUPPCState *env)
656{
657 /* Exception processing */
658 spr_register(env, SPR_DSISR, "DSISR",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_generic, &spr_write_generic,
661 0x00000000);
662 spr_register(env, SPR_DAR, "DAR",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_generic,
665 0x00000000);
666 /* Timer */
667 spr_register(env, SPR_DECR, "DECR",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_decr, &spr_write_decr,
670 0x00000000);
671 /* Memory management */
672 spr_register(env, SPR_SDR1, "SDR1",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_sdr1, &spr_write_sdr1,
675 0x00000000);
676}
677
678/* BATs 0-3 */
679static void gen_low_BATs (CPUPPCState *env)
680{
f2e63a42 681#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 682 spr_register(env, SPR_IBAT0U, "IBAT0U",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_ibat, &spr_write_ibatu,
685 0x00000000);
686 spr_register(env, SPR_IBAT0L, "IBAT0L",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_ibat, &spr_write_ibatl,
689 0x00000000);
690 spr_register(env, SPR_IBAT1U, "IBAT1U",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_ibat, &spr_write_ibatu,
693 0x00000000);
694 spr_register(env, SPR_IBAT1L, "IBAT1L",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_ibat, &spr_write_ibatl,
697 0x00000000);
698 spr_register(env, SPR_IBAT2U, "IBAT2U",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_ibat, &spr_write_ibatu,
701 0x00000000);
702 spr_register(env, SPR_IBAT2L, "IBAT2L",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_ibat, &spr_write_ibatl,
705 0x00000000);
706 spr_register(env, SPR_IBAT3U, "IBAT3U",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_ibat, &spr_write_ibatu,
709 0x00000000);
710 spr_register(env, SPR_IBAT3L, "IBAT3L",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatl,
713 0x00000000);
714 spr_register(env, SPR_DBAT0U, "DBAT0U",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_dbat, &spr_write_dbatu,
717 0x00000000);
718 spr_register(env, SPR_DBAT0L, "DBAT0L",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_dbat, &spr_write_dbatl,
721 0x00000000);
722 spr_register(env, SPR_DBAT1U, "DBAT1U",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_dbat, &spr_write_dbatu,
725 0x00000000);
726 spr_register(env, SPR_DBAT1L, "DBAT1L",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_dbat, &spr_write_dbatl,
729 0x00000000);
730 spr_register(env, SPR_DBAT2U, "DBAT2U",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_dbat, &spr_write_dbatu,
733 0x00000000);
734 spr_register(env, SPR_DBAT2L, "DBAT2L",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_dbat, &spr_write_dbatl,
737 0x00000000);
738 spr_register(env, SPR_DBAT3U, "DBAT3U",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_dbat, &spr_write_dbatu,
741 0x00000000);
742 spr_register(env, SPR_DBAT3L, "DBAT3L",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatl,
745 0x00000000);
a750fc0b 746 env->nb_BATs += 4;
f2e63a42 747#endif
3fc6c082
FB		 748}
749
750/* BATs 4-7 */
751static void gen_high_BATs (CPUPPCState *env)
752{
f2e63a42 753#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 754 spr_register(env, SPR_IBAT4U, "IBAT4U",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_ibat_h, &spr_write_ibatu_h,
757 0x00000000);
758 spr_register(env, SPR_IBAT4L, "IBAT4L",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_ibat_h, &spr_write_ibatl_h,
761 0x00000000);
762 spr_register(env, SPR_IBAT5U, "IBAT5U",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_ibat_h, &spr_write_ibatu_h,
765 0x00000000);
766 spr_register(env, SPR_IBAT5L, "IBAT5L",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_ibat_h, &spr_write_ibatl_h,
769 0x00000000);
770 spr_register(env, SPR_IBAT6U, "IBAT6U",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_ibat_h, &spr_write_ibatu_h,
773 0x00000000);
774 spr_register(env, SPR_IBAT6L, "IBAT6L",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_ibat_h, &spr_write_ibatl_h,
777 0x00000000);
778 spr_register(env, SPR_IBAT7U, "IBAT7U",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_ibat_h, &spr_write_ibatu_h,
781 0x00000000);
782 spr_register(env, SPR_IBAT7L, "IBAT7L",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatl_h,
785 0x00000000);
786 spr_register(env, SPR_DBAT4U, "DBAT4U",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_dbat_h, &spr_write_dbatu_h,
789 0x00000000);
790 spr_register(env, SPR_DBAT4L, "DBAT4L",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_dbat_h, &spr_write_dbatl_h,
793 0x00000000);
794 spr_register(env, SPR_DBAT5U, "DBAT5U",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_dbat_h, &spr_write_dbatu_h,
797 0x00000000);
798 spr_register(env, SPR_DBAT5L, "DBAT5L",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_dbat_h, &spr_write_dbatl_h,
801 0x00000000);
802 spr_register(env, SPR_DBAT6U, "DBAT6U",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_dbat_h, &spr_write_dbatu_h,
805 0x00000000);
806 spr_register(env, SPR_DBAT6L, "DBAT6L",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_dbat_h, &spr_write_dbatl_h,
809 0x00000000);
810 spr_register(env, SPR_DBAT7U, "DBAT7U",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_dbat_h, &spr_write_dbatu_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT7L, "DBAT7L",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatl_h,
817 0x00000000);
a750fc0b 818 env->nb_BATs += 4;
f2e63a42 819#endif
3fc6c082
FB		 820}
821
822/* Generic PowerPC time base */
823static void gen_tbl (CPUPPCState *env)
824{
825 spr_register(env, SPR_VTBL, "TBL",
826 &spr_read_tbl, SPR_NOACCESS,
827 &spr_read_tbl, SPR_NOACCESS,
828 0x00000000);
829 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 830 &spr_read_tbl, SPR_NOACCESS,
831 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 832 0x00000000);
833 spr_register(env, SPR_VTBU, "TBU",
834 &spr_read_tbu, SPR_NOACCESS,
835 &spr_read_tbu, SPR_NOACCESS,
836 0x00000000);
837 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 838 &spr_read_tbu, SPR_NOACCESS,
839 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 840 0x00000000);
841}
842
76a66253
JM		 843/* Softare table search registers */
844static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
845{
f2e63a42 846#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 847 env->nb_tlb = nb_tlbs;
848 env->nb_ways = nb_ways;
849 env->id_tlbs = 1;
850 spr_register(env, SPR_DMISS, "DMISS",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_generic, SPR_NOACCESS,
853 0x00000000);
854 spr_register(env, SPR_DCMP, "DCMP",
855 SPR_NOACCESS, SPR_NOACCESS,
856 &spr_read_generic, SPR_NOACCESS,
857 0x00000000);
858 spr_register(env, SPR_HASH1, "HASH1",
859 SPR_NOACCESS, SPR_NOACCESS,
860 &spr_read_generic, SPR_NOACCESS,
861 0x00000000);
862 spr_register(env, SPR_HASH2, "HASH2",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, SPR_NOACCESS,
865 0x00000000);
866 spr_register(env, SPR_IMISS, "IMISS",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, SPR_NOACCESS,
869 0x00000000);
870 spr_register(env, SPR_ICMP, "ICMP",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_RPA, "RPA",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, &spr_write_generic,
877 0x00000000);
f2e63a42 878#endif
76a66253
JM		 879}
880
881/* SPR common to MPC755 and G2 */
882static void gen_spr_G2_755 (CPUPPCState *env)
883{
884 /* SGPRs */
885 spr_register(env, SPR_SPRG4, "SPRG4",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_generic,
888 0x00000000);
889 spr_register(env, SPR_SPRG5, "SPRG5",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, &spr_write_generic,
892 0x00000000);
893 spr_register(env, SPR_SPRG6, "SPRG6",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_generic,
896 0x00000000);
897 spr_register(env, SPR_SPRG7, "SPRG7",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, &spr_write_generic,
900 0x00000000);
76a66253
JM		 901}
902
3fc6c082
FB		 903/* SPR common to all 7xx PowerPC implementations */
904static void gen_spr_7xx (CPUPPCState *env)
905{
906 /* Breakpoints */
907 /* XXX : not implemented */
908 spr_register(env, SPR_DABR, "DABR",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 /* XXX : not implemented */
913 spr_register(env, SPR_IABR, "IABR",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 /* Cache management */
918 /* XXX : not implemented */
919 spr_register(env, SPR_ICTC, "ICTC",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* Performance monitors */
924 /* XXX : not implemented */
925 spr_register(env, SPR_MMCR0, "MMCR0",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_generic,
928 0x00000000);
929 /* XXX : not implemented */
930 spr_register(env, SPR_MMCR1, "MMCR1",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* XXX : not implemented */
935 spr_register(env, SPR_PMC1, "PMC1",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 /* XXX : not implemented */
940 spr_register(env, SPR_PMC2, "PMC2",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944 /* XXX : not implemented */
945 spr_register(env, SPR_PMC3, "PMC3",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_PMC4, "PMC4",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
a750fc0b 955 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, SPR_NOACCESS,
958 0x00000000);
578bb252 959 /* XXX : not implemented */
3fc6c082
FB		 960 spr_register(env, SPR_UMMCR0, "UMMCR0",
961 &spr_read_ureg, SPR_NOACCESS,
962 &spr_read_ureg, SPR_NOACCESS,
963 0x00000000);
578bb252 964 /* XXX : not implemented */
3fc6c082
FB		 965 spr_register(env, SPR_UMMCR1, "UMMCR1",
966 &spr_read_ureg, SPR_NOACCESS,
967 &spr_read_ureg, SPR_NOACCESS,
968 0x00000000);
578bb252 969 /* XXX : not implemented */
3fc6c082
FB		 970 spr_register(env, SPR_UPMC1, "UPMC1",
971 &spr_read_ureg, SPR_NOACCESS,
972 &spr_read_ureg, SPR_NOACCESS,
973 0x00000000);
578bb252 974 /* XXX : not implemented */
3fc6c082
FB		 975 spr_register(env, SPR_UPMC2, "UPMC2",
976 &spr_read_ureg, SPR_NOACCESS,
977 &spr_read_ureg, SPR_NOACCESS,
978 0x00000000);
578bb252 979 /* XXX : not implemented */
3fc6c082
FB		 980 spr_register(env, SPR_UPMC3, "UPMC3",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
578bb252 984 /* XXX : not implemented */
3fc6c082
FB		 985 spr_register(env, SPR_UPMC4, "UPMC4",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
578bb252 989 /* XXX : not implemented */
a750fc0b 990 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
a750fc0b 994 /* External access control */
3fc6c082 995 /* XXX : not implemented */
a750fc0b 996 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
a750fc0b
JM		 1000}
1001
1002static void gen_spr_thrm (CPUPPCState *env)
1003{
1004 /* Thermal management */
3fc6c082 1005 /* XXX : not implemented */
a750fc0b 1006 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* XXX : not implemented */
a750fc0b 1011 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
3fc6c082 1015 /* XXX : not implemented */
a750fc0b 1016 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020}
1021
1022/* SPR specific to PowerPC 604 implementation */
1023static void gen_spr_604 (CPUPPCState *env)
1024{
1025 /* Processor identification */
1026 spr_register(env, SPR_PIR, "PIR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_pir,
1029 0x00000000);
1030 /* Breakpoints */
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_IABR, "IABR",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, &spr_write_generic,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_DABR, "DABR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* Performance counters */
1042 /* XXX : not implemented */
1043 spr_register(env, SPR_MMCR0, "MMCR0",
1044 SPR_NOACCESS, SPR_NOACCESS,
1045 &spr_read_generic, &spr_write_generic,
1046 0x00000000);
1047 /* XXX : not implemented */
3fc6c082
FB		 1048 spr_register(env, SPR_PMC1, "PMC1",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* XXX : not implemented */
1053 spr_register(env, SPR_PMC2, "PMC2",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, &spr_write_generic,
1056 0x00000000);
1057 /* XXX : not implemented */
a750fc0b 1058 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, SPR_NOACCESS,
1061 0x00000000);
1062 /* XXX : not implemented */
1063 spr_register(env, SPR_SDA, "SDA",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, SPR_NOACCESS,
1066 0x00000000);
1067 /* External access control */
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_EAR, "EAR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073}
1074
76a66253
JM		 1075/* SPR specific to PowerPC 603 implementation */
1076static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1077{
76a66253
JM		 1078 /* External access control */
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1081 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
3fc6c082
FB		 1084}
1085
76a66253
JM		 1086/* SPR specific to PowerPC G2 implementation */
1087static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1088{
76a66253
JM		 1089 /* Memory base address */
1090 /* MBAR */
578bb252 1091 /* XXX : not implemented */
76a66253
JM		 1092 spr_register(env, SPR_MBAR, "MBAR",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
76a66253 1096 /* Exception processing */
363be49c 1097 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
363be49c 1101 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_generic, &spr_write_generic,
1104 0x00000000);
1105 /* Breakpoints */
1106 /* XXX : not implemented */
1107 spr_register(env, SPR_DABR, "DABR",
1108 SPR_NOACCESS, SPR_NOACCESS,
1109 &spr_read_generic, &spr_write_generic,
1110 0x00000000);
1111 /* XXX : not implemented */
1112 spr_register(env, SPR_DABR2, "DABR2",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* XXX : not implemented */
1117 spr_register(env, SPR_IABR, "IABR",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 /* XXX : not implemented */
1122 spr_register(env, SPR_IABR2, "IABR2",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_IBCR, "IBCR",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_DBCR, "DBCR",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136}
1137
1138/* SPR specific to PowerPC 602 implementation */
1139static void gen_spr_602 (CPUPPCState *env)
1140{
1141 /* ESA registers */
1142 /* XXX : not implemented */
1143 spr_register(env, SPR_SER, "SER",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_SEBR, "SEBR",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 /* XXX : not implemented */
a750fc0b 1153 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, &spr_write_generic,
1156 0x00000000);
1157 /* Floating point status */
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_SP, "SP",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_LT, "LT",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168 /* Watchdog timer */
1169 /* XXX : not implemented */
1170 spr_register(env, SPR_TCR, "TCR",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
1174 /* Interrupt base */
1175 spr_register(env, SPR_IBR, "IBR",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
a750fc0b
JM		 1179 /* XXX : not implemented */
1180 spr_register(env, SPR_IABR, "IABR",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
76a66253
JM		 1184}
1185
1186/* SPR specific to PowerPC 601 implementation */
1187static void gen_spr_601 (CPUPPCState *env)
1188{
1189 /* Multiplication/division register */
1190 /* MQ */
1191 spr_register(env, SPR_MQ, "MQ",
1192 &spr_read_generic, &spr_write_generic,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* RTC registers */
1196 spr_register(env, SPR_601_RTCU, "RTCU",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 SPR_NOACCESS, &spr_write_601_rtcu,
1199 0x00000000);
1200 spr_register(env, SPR_601_VRTCU, "RTCU",
1201 &spr_read_601_rtcu, SPR_NOACCESS,
1202 &spr_read_601_rtcu, SPR_NOACCESS,
1203 0x00000000);
1204 spr_register(env, SPR_601_RTCL, "RTCL",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 SPR_NOACCESS, &spr_write_601_rtcl,
1207 0x00000000);
1208 spr_register(env, SPR_601_VRTCL, "RTCL",
1209 &spr_read_601_rtcl, SPR_NOACCESS,
1210 &spr_read_601_rtcl, SPR_NOACCESS,
1211 0x00000000);
1212 /* Timer */
1213#if 0 /* ? */
1214 spr_register(env, SPR_601_UDECR, "UDECR",
1215 &spr_read_decr, SPR_NOACCESS,
1216 &spr_read_decr, SPR_NOACCESS,
1217 0x00000000);
1218#endif
1219 /* External access control */
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_EAR, "EAR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* Memory management */
f2e63a42 1226#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1227 spr_register(env, SPR_IBAT0U, "IBAT0U",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_601_ubat, &spr_write_601_ubatu,
1230 0x00000000);
1231 spr_register(env, SPR_IBAT0L, "IBAT0L",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_601_ubat, &spr_write_601_ubatl,
1234 0x00000000);
1235 spr_register(env, SPR_IBAT1U, "IBAT1U",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_601_ubat, &spr_write_601_ubatu,
1238 0x00000000);
1239 spr_register(env, SPR_IBAT1L, "IBAT1L",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_601_ubat, &spr_write_601_ubatl,
1242 0x00000000);
1243 spr_register(env, SPR_IBAT2U, "IBAT2U",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_601_ubat, &spr_write_601_ubatu,
1246 0x00000000);
1247 spr_register(env, SPR_IBAT2L, "IBAT2L",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_601_ubat, &spr_write_601_ubatl,
1250 0x00000000);
1251 spr_register(env, SPR_IBAT3U, "IBAT3U",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_601_ubat, &spr_write_601_ubatu,
1254 0x00000000);
1255 spr_register(env, SPR_IBAT3L, "IBAT3L",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_601_ubat, &spr_write_601_ubatl,
1258 0x00000000);
a750fc0b 1259 env->nb_BATs = 4;
f2e63a42 1260#endif
a750fc0b
JM		 1261}
1262
1263static void gen_spr_74xx (CPUPPCState *env)
1264{
1265 /* Processor identification */
1266 spr_register(env, SPR_PIR, "PIR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_pir,
1269 0x00000000);
1270 /* XXX : not implemented */
1271 spr_register(env, SPR_MMCR2, "MMCR2",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_generic, &spr_write_generic,
1274 0x00000000);
578bb252 1275 /* XXX : not implemented */
a750fc0b
JM		 1276 spr_register(env, SPR_UMMCR2, "UMMCR2",
1277 &spr_read_ureg, SPR_NOACCESS,
1278 &spr_read_ureg, SPR_NOACCESS,
1279 0x00000000);
1280 /* XXX: not implemented */
1281 spr_register(env, SPR_BAMR, "BAMR",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
578bb252 1285 /* XXX : not implemented */
a750fc0b
JM		 1286 spr_register(env, SPR_MSSCR0, "MSSCR0",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1289 0x00000000);
1290 /* Hardware implementation registers */
1291 /* XXX : not implemented */
1292 spr_register(env, SPR_HID0, "HID0",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 /* XXX : not implemented */
1297 spr_register(env, SPR_HID1, "HID1",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* Altivec */
1302 spr_register(env, SPR_VRSAVE, "VRSAVE",
1303 &spr_read_generic, &spr_write_generic,
1304 &spr_read_generic, &spr_write_generic,
1305 0x00000000);
bd928eba
JM		 1306 /* XXX : not implemented */
1307 spr_register(env, SPR_L2CR, "L2CR",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, &spr_write_generic,
1310 0x00000000);
cf8358c8
AJ		 1311 /* Not strictly an SPR */
1312 vscr_init(env, 0x00010000);
a750fc0b
JM		 1313}
1314
a750fc0b
JM		 1315static void gen_l3_ctrl (CPUPPCState *env)
1316{
1317 /* L3CR */
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_L3CR, "L3CR",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 /* L3ITCR0 */
578bb252 1324 /* XXX : not implemented */
a750fc0b
JM		 1325 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
a750fc0b 1329 /* L3PM */
578bb252 1330 /* XXX : not implemented */
a750fc0b
JM		 1331 spr_register(env, SPR_L3PM, "L3PM",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335}
a750fc0b 1336
578bb252 1337static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1338{
f2e63a42 1339#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1340 env->nb_tlb = nb_tlbs;
1341 env->nb_ways = nb_ways;
1342 env->id_tlbs = 1;
1343 /* XXX : not implemented */
a750fc0b
JM		 1344 spr_register(env, SPR_PTEHI, "PTEHI",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
578bb252 1348 /* XXX : not implemented */
a750fc0b
JM		 1349 spr_register(env, SPR_PTELO, "PTELO",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
578bb252 1353 /* XXX : not implemented */
a750fc0b
JM		 1354 spr_register(env, SPR_TLBMISS, "TLBMISS",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
f2e63a42 1358#endif
76a66253
JM		 1359}
1360
80d11f44 1361static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1362{
80d11f44
JM		 1363 spr_register(env, SPR_USPRG4, "USPRG4",
1364 &spr_read_ureg, SPR_NOACCESS,
1365 &spr_read_ureg, SPR_NOACCESS,
1366 0x00000000);
1367 spr_register(env, SPR_USPRG5, "USPRG5",
1368 &spr_read_ureg, SPR_NOACCESS,
1369 &spr_read_ureg, SPR_NOACCESS,
1370 0x00000000);
1371 spr_register(env, SPR_USPRG6, "USPRG6",
1372 &spr_read_ureg, SPR_NOACCESS,
1373 &spr_read_ureg, SPR_NOACCESS,
1374 0x00000000);
1375 spr_register(env, SPR_USPRG7, "USPRG7",
1376 &spr_read_ureg, SPR_NOACCESS,
1377 &spr_read_ureg, SPR_NOACCESS,
76a66253 1378 0x00000000);
80d11f44
JM		 1379}
1380
1381/* PowerPC BookE SPR */
1382static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1383{
b55266b5 1384 const char *ivor_names[64] = {
80d11f44
JM		 1385 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1386 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1387 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1388 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1389 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1390 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1391 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1392 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1393 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1394 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1395 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1396 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1397 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1398 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1399 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1400 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1401 };
1402#define SPR_BOOKE_IVORxx (-1)
1403 int ivor_sprn[64] = {
1404 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1405 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1406 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1407 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1408 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1409 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1410 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1411 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1412 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1413 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1414 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1415 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1416 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1417 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1418 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1419 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1420 };
1421 int i;
1422
76a66253 1423 /* Interrupt processing */
363be49c 1424 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
363be49c
JM		 1428 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_generic,
1431 0x00000000);
76a66253
JM		 1432 /* Debug */
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 /* XXX : not implemented */
76a66253
JM		 1444 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 /* XXX : not implemented */
1449 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 /* XXX : not implemented */
76a66253
JM		 1454 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 /* XXX : not implemented */
1459 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 /* XXX : not implemented */
1464 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* XXX : not implemented */
1469 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1470 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1471 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1472 0x00000000);
1473 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 spr_register(env, SPR_BOOKE_ESR, "ESR",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1480 0x00000000);
363be49c
JM		 1481 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1482 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1483 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1484 0x00000000);
1485 /* Exception vectors */
80d11f44
JM		 1486 for (i = 0; i < 64; i++) {
1487 if (ivor_mask & (1ULL << i)) {
1488 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1489 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1490 exit(1);
1491 }
1492 spr_register(env, ivor_sprn[i], ivor_names[i],
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, &spr_write_excp_vector,
1495 0x00000000);
1496 }
1497 }
76a66253
JM		 1498 spr_register(env, SPR_BOOKE_PID, "PID",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 spr_register(env, SPR_BOOKE_TCR, "TCR",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_booke_tcr,
1505 0x00000000);
1506 spr_register(env, SPR_BOOKE_TSR, "TSR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_booke_tsr,
1509 0x00000000);
1510 /* Timer */
1511 spr_register(env, SPR_DECR, "DECR",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_decr, &spr_write_decr,
1514 0x00000000);
1515 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 SPR_NOACCESS, &spr_write_generic,
1518 0x00000000);
1519 /* SPRGs */
1520 spr_register(env, SPR_USPRG0, "USPRG0",
1521 &spr_read_generic, &spr_write_generic,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524 spr_register(env, SPR_SPRG4, "SPRG4",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
76a66253
JM		 1528 spr_register(env, SPR_SPRG5, "SPRG5",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
76a66253
JM		 1532 spr_register(env, SPR_SPRG6, "SPRG6",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
76a66253
JM		 1536 spr_register(env, SPR_SPRG7, "SPRG7",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
76a66253
JM		 1540}
1541
363be49c 1542/* FSL storage control registers */
80d11f44 1543static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1544{
f2e63a42 1545#if !defined(CONFIG_USER_ONLY)
b55266b5 1546 const char *mas_names[8] = {
80d11f44
JM		 1547 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1548 };
1549 int mas_sprn[8] = {
1550 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1551 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1552 };
1553 int i;
1554
363be49c 1555 /* TLB assist registers */
578bb252 1556 /* XXX : not implemented */
80d11f44
JM		 1557 for (i = 0; i < 8; i++) {
1558 if (mas_mask & (1 << i)) {
1559 spr_register(env, mas_sprn[i], mas_names[i],
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 }
1564 }
363be49c 1565 if (env->nb_pids > 1) {
578bb252 1566 /* XXX : not implemented */
363be49c
JM		 1567 spr_register(env, SPR_BOOKE_PID1, "PID1",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 }
1572 if (env->nb_pids > 2) {
578bb252 1573 /* XXX : not implemented */
363be49c
JM		 1574 spr_register(env, SPR_BOOKE_PID2, "PID2",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 }
578bb252 1579 /* XXX : not implemented */
65f9ee8d 1580 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, SPR_NOACCESS,
1583 0x00000000); /* TOFIX */
578bb252 1584 /* XXX : not implemented */
65f9ee8d 1585 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000); /* TOFIX */
1589 switch (env->nb_ways) {
1590 case 4:
578bb252 1591 /* XXX : not implemented */
363be49c
JM		 1592 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, SPR_NOACCESS,
1595 0x00000000); /* TOFIX */
1596 /* Fallthru */
1597 case 3:
578bb252 1598 /* XXX : not implemented */
363be49c
JM		 1599 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, SPR_NOACCESS,
1602 0x00000000); /* TOFIX */
1603 /* Fallthru */
1604 case 2:
578bb252 1605 /* XXX : not implemented */
363be49c
JM		 1606 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, SPR_NOACCESS,
1609 0x00000000); /* TOFIX */
1610 /* Fallthru */
1611 case 1:
578bb252 1612 /* XXX : not implemented */
363be49c
JM		 1613 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, SPR_NOACCESS,
1616 0x00000000); /* TOFIX */
1617 /* Fallthru */
1618 case 0:
1619 default:
1620 break;
1621 }
f2e63a42 1622#endif
363be49c
JM		 1623}
1624
76a66253
JM		 1625/* SPR specific to PowerPC 440 implementation */
1626static void gen_spr_440 (CPUPPCState *env)
1627{
1628 /* Cache control */
1629 /* XXX : not implemented */
1630 spr_register(env, SPR_440_DNV0, "DNV0",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 /* XXX : not implemented */
1635 spr_register(env, SPR_440_DNV1, "DNV1",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_generic,
1638 0x00000000);
1639 /* XXX : not implemented */
1640 spr_register(env, SPR_440_DNV2, "DNV2",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, &spr_write_generic,
1643 0x00000000);
1644 /* XXX : not implemented */
1645 spr_register(env, SPR_440_DNV3, "DNV3",
1646 SPR_NOACCESS, SPR_NOACCESS,
1647 &spr_read_generic, &spr_write_generic,
1648 0x00000000);
1649 /* XXX : not implemented */
2662a059 1650 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, &spr_write_generic,
1653 0x00000000);
1654 /* XXX : not implemented */
2662a059 1655 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 /* XXX : not implemented */
2662a059 1660 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1661 SPR_NOACCESS, SPR_NOACCESS,
1662 &spr_read_generic, &spr_write_generic,
1663 0x00000000);
1664 /* XXX : not implemented */
2662a059 1665 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_generic,
1668 0x00000000);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_440_DVLIM, "DVLIM",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_440_INV0, "INV0",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, &spr_write_generic,
1678 0x00000000);
1679 /* XXX : not implemented */
1680 spr_register(env, SPR_440_INV1, "INV1",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 /* XXX : not implemented */
1685 spr_register(env, SPR_440_INV2, "INV2",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689 /* XXX : not implemented */
1690 spr_register(env, SPR_440_INV3, "INV3",
1691 SPR_NOACCESS, SPR_NOACCESS,
1692 &spr_read_generic, &spr_write_generic,
1693 0x00000000);
1694 /* XXX : not implemented */
2662a059 1695 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1698 0x00000000);
1699 /* XXX : not implemented */
2662a059 1700 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, &spr_write_generic,
1703 0x00000000);
1704 /* XXX : not implemented */
2662a059 1705 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_generic,
1708 0x00000000);
1709 /* XXX : not implemented */
2662a059 1710 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_440_IVLIM, "IVLIM",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719 /* Cache debug */
1720 /* XXX : not implemented */
2662a059 1721 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, SPR_NOACCESS,
1724 0x00000000);
1725 /* XXX : not implemented */
2662a059 1726 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, SPR_NOACCESS,
1729 0x00000000);
1730 /* XXX : not implemented */
2662a059 1731 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, SPR_NOACCESS,
1734 0x00000000);
1735 /* XXX : not implemented */
2662a059 1736 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, SPR_NOACCESS,
1739 0x00000000);
1740 /* XXX : not implemented */
2662a059 1741 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, SPR_NOACCESS,
1744 0x00000000);
1745 /* XXX : not implemented */
1746 spr_register(env, SPR_440_DBDR, "DBDR",
1747 SPR_NOACCESS, SPR_NOACCESS,
1748 &spr_read_generic, &spr_write_generic,
1749 0x00000000);
1750 /* Processor control */
1751 spr_register(env, SPR_4xx_CCR0, "CCR0",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 &spr_read_generic, &spr_write_generic,
1754 0x00000000);
1755 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, SPR_NOACCESS,
1758 0x00000000);
1759 /* Storage control */
1760 spr_register(env, SPR_440_MMUCR, "MMUCR",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764}
1765
1766/* SPR shared between PowerPC 40x implementations */
1767static void gen_spr_40x (CPUPPCState *env)
1768{
1769 /* Cache */
035feb88 1770 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1771 spr_register(env, SPR_40x_DCCR, "DCCR",
1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_generic,
1774 0x00000000);
035feb88 1775 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1776 spr_register(env, SPR_40x_ICCR, "ICCR",
1777 SPR_NOACCESS, SPR_NOACCESS,
1778 &spr_read_generic, &spr_write_generic,
1779 0x00000000);
578bb252 1780 /* not emulated, as Qemu do not emulate caches */
2662a059 1781 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, SPR_NOACCESS,
1784 0x00000000);
76a66253
JM		 1785 /* Exception */
1786 spr_register(env, SPR_40x_DEAR, "DEAR",
1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790 spr_register(env, SPR_40x_ESR, "ESR",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 spr_register(env, SPR_40x_EVPR, "EVPR",
1795 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1796 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1797 0x00000000);
1798 spr_register(env, SPR_40x_SRR2, "SRR2",
1799 &spr_read_generic, &spr_write_generic,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 spr_register(env, SPR_40x_SRR3, "SRR3",
1803 &spr_read_generic, &spr_write_generic,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* Timers */
1807 spr_register(env, SPR_40x_PIT, "PIT",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_40x_pit, &spr_write_40x_pit,
1810 0x00000000);
1811 spr_register(env, SPR_40x_TCR, "TCR",
1812 SPR_NOACCESS, SPR_NOACCESS,
1813 &spr_read_generic, &spr_write_booke_tcr,
1814 0x00000000);
1815 spr_register(env, SPR_40x_TSR, "TSR",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_booke_tsr,
1818 0x00000000);
2662a059
JM		 1819}
1820
1821/* SPR specific to PowerPC 405 implementation */
1822static void gen_spr_405 (CPUPPCState *env)
1823{
1824 /* MMU */
1825 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
2662a059 1829 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1832 0x00700000);
1833 /* Debug interface */
76a66253
JM		 1834 /* XXX : not implemented */
1835 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1836 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1837 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1838 0x00000000);
1839 /* XXX : not implemented */
2662a059
JM		 1840 spr_register(env, SPR_405_DBCR1, "DBCR1",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
1844 /* XXX : not implemented */
76a66253
JM		 1845 spr_register(env, SPR_40x_DBSR, "DBSR",
1846 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1847 &spr_read_generic, &spr_write_clear,
1848 /* Last reset was system reset */
76a66253
JM		 1849 0x00000300);
1850 /* XXX : not implemented */
2662a059 1851 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
2662a059 1855 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, &spr_write_generic,
1858 0x00000000);
2662a059
JM		 1859 /* XXX : not implemented */
1860 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_generic, &spr_write_generic,
2662a059 1863 0x00000000);
76a66253 1864 /* XXX : not implemented */
2662a059 1865 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, &spr_write_generic,
1868 0x00000000);
1869 /* XXX : not implemented */
2662a059 1870 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, &spr_write_generic,
1873 0x00000000);
2662a059 1874 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_generic,
1877 0x00000000);
1878 /* XXX : not implemented */
1879 spr_register(env, SPR_405_IAC3, "IAC3",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 /* XXX : not implemented */
1884 spr_register(env, SPR_405_IAC4, "IAC4",
1885 SPR_NOACCESS, SPR_NOACCESS,
1886 &spr_read_generic, &spr_write_generic,
1887 0x00000000);
1888 /* Storage control */
035feb88 1889 /* XXX: TODO: not implemented */
76a66253
JM		 1890 spr_register(env, SPR_405_SLER, "SLER",
1891 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1892 &spr_read_generic, &spr_write_40x_sler,
76a66253 1893 0x00000000);
2662a059
JM		 1894 spr_register(env, SPR_40x_ZPR, "ZPR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
76a66253
JM		 1898 /* XXX : not implemented */
1899 spr_register(env, SPR_405_SU0R, "SU0R",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
1903 /* SPRG */
1904 spr_register(env, SPR_USPRG0, "USPRG0",
1905 &spr_read_ureg, SPR_NOACCESS,
1906 &spr_read_ureg, SPR_NOACCESS,
1907 0x00000000);
1908 spr_register(env, SPR_SPRG4, "SPRG4",
1909 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1910 &spr_read_generic, &spr_write_generic,
76a66253 1911 0x00000000);
76a66253
JM		 1912 spr_register(env, SPR_SPRG5, "SPRG5",
1913 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1914 spr_read_generic, &spr_write_generic,
76a66253 1915 0x00000000);
76a66253
JM		 1916 spr_register(env, SPR_SPRG6, "SPRG6",
1917 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1918 spr_read_generic, &spr_write_generic,
76a66253 1919 0x00000000);
76a66253
JM		 1920 spr_register(env, SPR_SPRG7, "SPRG7",
1921 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1922 spr_read_generic, &spr_write_generic,
76a66253 1923 0x00000000);
80d11f44 1924 gen_spr_usprgh(env);
76a66253
JM		 1925}
1926
1927/* SPR shared between PowerPC 401 & 403 implementations */
1928static void gen_spr_401_403 (CPUPPCState *env)
1929{
1930 /* Time base */
1931 spr_register(env, SPR_403_VTBL, "TBL",
1932 &spr_read_tbl, SPR_NOACCESS,
1933 &spr_read_tbl, SPR_NOACCESS,
1934 0x00000000);
1935 spr_register(env, SPR_403_TBL, "TBL",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 SPR_NOACCESS, &spr_write_tbl,
1938 0x00000000);
1939 spr_register(env, SPR_403_VTBU, "TBU",
1940 &spr_read_tbu, SPR_NOACCESS,
1941 &spr_read_tbu, SPR_NOACCESS,
1942 0x00000000);
1943 spr_register(env, SPR_403_TBU, "TBU",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 SPR_NOACCESS, &spr_write_tbu,
1946 0x00000000);
1947 /* Debug */
578bb252 1948 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1949 spr_register(env, SPR_403_CDBCR, "CDBCR",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953}
1954
2662a059
JM		 1955/* SPR specific to PowerPC 401 implementation */
1956static void gen_spr_401 (CPUPPCState *env)
1957{
1958 /* Debug interface */
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_40x_DBCR0, "DBCR",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_40x_dbcr0,
1963 0x00000000);
1964 /* XXX : not implemented */
1965 spr_register(env, SPR_40x_DBSR, "DBSR",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_clear,
1968 /* Last reset was system reset */
1969 0x00000300);
1970 /* XXX : not implemented */
1971 spr_register(env, SPR_40x_DAC1, "DAC",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1974 0x00000000);
1975 /* XXX : not implemented */
1976 spr_register(env, SPR_40x_IAC1, "IAC",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_generic,
1979 0x00000000);
1980 /* Storage control */
035feb88 1981 /* XXX: TODO: not implemented */
2662a059
JM		 1982 spr_register(env, SPR_405_SLER, "SLER",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_40x_sler,
1985 0x00000000);
035feb88
JM		 1986 /* not emulated, as Qemu never does speculative access */
1987 spr_register(env, SPR_40x_SGR, "SGR",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0xFFFFFFFF);
1991 /* not emulated, as Qemu do not emulate caches */
1992 spr_register(env, SPR_40x_DCWR, "DCWR",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
2662a059
JM		 1996}
1997
a750fc0b
JM		 1998static void gen_spr_401x2 (CPUPPCState *env)
1999{
2000 gen_spr_401(env);
2001 spr_register(env, SPR_40x_PID, "PID",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 spr_register(env, SPR_40x_ZPR, "ZPR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009}
2010
76a66253
JM		 2011/* SPR specific to PowerPC 403 implementation */
2012static void gen_spr_403 (CPUPPCState *env)
2013{
2662a059
JM		 2014 /* Debug interface */
2015 /* XXX : not implemented */
2016 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_40x_dbcr0,
2019 0x00000000);
2020 /* XXX : not implemented */
2021 spr_register(env, SPR_40x_DBSR, "DBSR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_clear,
2024 /* Last reset was system reset */
2025 0x00000300);
2026 /* XXX : not implemented */
2027 spr_register(env, SPR_40x_DAC1, "DAC1",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
578bb252 2031 /* XXX : not implemented */
2662a059
JM		 2032 spr_register(env, SPR_40x_DAC2, "DAC2",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2035 0x00000000);
2036 /* XXX : not implemented */
2037 spr_register(env, SPR_40x_IAC1, "IAC1",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_generic,
2040 0x00000000);
578bb252 2041 /* XXX : not implemented */
2662a059
JM		 2042 spr_register(env, SPR_40x_IAC2, "IAC2",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
a750fc0b
JM		 2046}
2047
2048static void gen_spr_403_real (CPUPPCState *env)
2049{
76a66253
JM		 2050 spr_register(env, SPR_403_PBL1, "PBL1",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_403_pbr, &spr_write_403_pbr,
2053 0x00000000);
2054 spr_register(env, SPR_403_PBU1, "PBU1",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_403_pbr, &spr_write_403_pbr,
2057 0x00000000);
2058 spr_register(env, SPR_403_PBL2, "PBL2",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_403_pbr, &spr_write_403_pbr,
2061 0x00000000);
2062 spr_register(env, SPR_403_PBU2, "PBU2",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_403_pbr, &spr_write_403_pbr,
2065 0x00000000);
a750fc0b
JM		 2066}
2067
2068static void gen_spr_403_mmu (CPUPPCState *env)
2069{
2070 /* MMU */
2071 spr_register(env, SPR_40x_PID, "PID",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2662a059 2075 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_generic,
2078 0x00000000);
2079}
2080
2081/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2082static void gen_spr_compress (CPUPPCState *env)
2083{
578bb252 2084 /* XXX : not implemented */
76a66253
JM		 2085 spr_register(env, SPR_401_SKR, "SKR",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089}
a750fc0b
JM		 2090
2091#if defined (TARGET_PPC64)
a750fc0b
JM		 2092/* SPR specific to PowerPC 620 */
2093static void gen_spr_620 (CPUPPCState *env)
2094{
082c6681
JM		 2095 /* Processor identification */
2096 spr_register(env, SPR_PIR, "PIR",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_pir,
2099 0x00000000);
2100 spr_register(env, SPR_ASR, "ASR",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_asr, &spr_write_asr,
2103 0x00000000);
2104 /* Breakpoints */
2105 /* XXX : not implemented */
2106 spr_register(env, SPR_IABR, "IABR",
2107 SPR_NOACCESS, SPR_NOACCESS,
2108 &spr_read_generic, &spr_write_generic,
2109 0x00000000);
2110 /* XXX : not implemented */
2111 spr_register(env, SPR_DABR, "DABR",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 /* XXX : not implemented */
2116 spr_register(env, SPR_SIAR, "SIAR",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, SPR_NOACCESS,
2119 0x00000000);
2120 /* XXX : not implemented */
2121 spr_register(env, SPR_SDA, "SDA",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, SPR_NOACCESS,
2124 0x00000000);
2125 /* XXX : not implemented */
2126 spr_register(env, SPR_620_PMC1R, "PMC1",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, SPR_NOACCESS,
2129 0x00000000);
2130 spr_register(env, SPR_620_PMC1W, "PMC1",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 SPR_NOACCESS, &spr_write_generic,
2133 0x00000000);
2134 /* XXX : not implemented */
2135 spr_register(env, SPR_620_PMC2R, "PMC2",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, SPR_NOACCESS,
2138 0x00000000);
2139 spr_register(env, SPR_620_PMC2W, "PMC2",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 SPR_NOACCESS, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, SPR_NOACCESS,
2147 0x00000000);
2148 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 SPR_NOACCESS, &spr_write_generic,
2151 0x00000000);
2152 /* External access control */
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_EAR, "EAR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158#if 0 // XXX: check this
578bb252 2159 /* XXX : not implemented */
a750fc0b
JM		 2160 spr_register(env, SPR_620_PMR0, "PMR0",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
578bb252 2164 /* XXX : not implemented */
a750fc0b
JM		 2165 spr_register(env, SPR_620_PMR1, "PMR1",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
578bb252 2169 /* XXX : not implemented */
a750fc0b
JM		 2170 spr_register(env, SPR_620_PMR2, "PMR2",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
578bb252 2174 /* XXX : not implemented */
a750fc0b
JM		 2175 spr_register(env, SPR_620_PMR3, "PMR3",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
578bb252 2179 /* XXX : not implemented */
a750fc0b
JM		 2180 spr_register(env, SPR_620_PMR4, "PMR4",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
578bb252 2184 /* XXX : not implemented */
a750fc0b
JM		 2185 spr_register(env, SPR_620_PMR5, "PMR5",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
578bb252 2189 /* XXX : not implemented */
a750fc0b
JM		 2190 spr_register(env, SPR_620_PMR6, "PMR6",
2191 SPR_NOACCESS, SPR_NOACCESS,
2192 &spr_read_generic, &spr_write_generic,
2193 0x00000000);
578bb252 2194 /* XXX : not implemented */
a750fc0b
JM		 2195 spr_register(env, SPR_620_PMR7, "PMR7",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
578bb252 2199 /* XXX : not implemented */
a750fc0b
JM		 2200 spr_register(env, SPR_620_PMR8, "PMR8",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 0x00000000);
578bb252 2204 /* XXX : not implemented */
a750fc0b
JM		 2205 spr_register(env, SPR_620_PMR9, "PMR9",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_generic, &spr_write_generic,
2208 0x00000000);
578bb252 2209 /* XXX : not implemented */
a750fc0b
JM		 2210 spr_register(env, SPR_620_PMRA, "PMR10",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
578bb252 2214 /* XXX : not implemented */
a750fc0b
JM		 2215 spr_register(env, SPR_620_PMRB, "PMR11",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
578bb252 2219 /* XXX : not implemented */
a750fc0b
JM		 2220 spr_register(env, SPR_620_PMRC, "PMR12",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
578bb252 2224 /* XXX : not implemented */
a750fc0b
JM		 2225 spr_register(env, SPR_620_PMRD, "PMR13",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
578bb252 2229 /* XXX : not implemented */
a750fc0b
JM		 2230 spr_register(env, SPR_620_PMRE, "PMR14",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
578bb252 2234 /* XXX : not implemented */
a750fc0b
JM		 2235 spr_register(env, SPR_620_PMRF, "PMR15",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
082c6681 2239#endif
578bb252 2240 /* XXX : not implemented */
082c6681 2241 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
578bb252 2245 /* XXX : not implemented */
082c6681
JM		 2246 spr_register(env, SPR_620_L2CR, "L2CR",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255}
a750fc0b 2256#endif /* defined (TARGET_PPC64) */
76a66253 2257
80d11f44 2258static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2259{
80d11f44
JM		 2260 /* Exception processing */
2261 spr_register(env, SPR_DSISR, "DSISR",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 spr_register(env, SPR_DAR, "DAR",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* Timer */
2270 spr_register(env, SPR_DECR, "DECR",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_decr, &spr_write_decr,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_EIE, "EIE",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_EID, "EID",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_NRI, "NRI",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_CMPA, "CMPA",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_MPC_CMPB, "CMPB",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_MPC_CMPC, "CMPC",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_MPC_CMPD, "CMPD",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_MPC_ECR, "ECR",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_MPC_DER, "DER",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_MPC_CMPE, "CMPE",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* XXX : not implemented */
2335 spr_register(env, SPR_MPC_CMPF, "CMPF",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0x00000000);
2339 /* XXX : not implemented */
2340 spr_register(env, SPR_MPC_CMPG, "CMPG",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_MPC_CMPH, "CMPH",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* XXX : not implemented */
2360 spr_register(env, SPR_MPC_BAR, "BAR",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_generic, &spr_write_generic,
2363 0x00000000);
2364 /* XXX : not implemented */
2365 spr_register(env, SPR_MPC_DPDR, "DPDR",
2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369 /* XXX : not implemented */
2370 spr_register(env, SPR_MPC_IMMR, "IMMR",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374}
2375
2376static void gen_spr_5xx (CPUPPCState *env)
2377{
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433 /* XXX : not implemented */
2434 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2435 SPR_NOACCESS, SPR_NOACCESS,
2436 &spr_read_generic, &spr_write_generic,
2437 0x00000000);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 /* XXX : not implemented */
2459 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463 /* XXX : not implemented */
2464 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* XXX : not implemented */
2469 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 /* XXX : not implemented */
2474 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_generic, &spr_write_generic,
2477 0x00000000);
2478 /* XXX : not implemented */
2479 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 0x00000000);
2483}
2484
2485static void gen_spr_8xx (CPUPPCState *env)
2486{
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 /* XXX : not implemented */
2548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2549 SPR_NOACCESS, SPR_NOACCESS,
2550 &spr_read_generic, &spr_write_generic,
2551 0x00000000);
2552 /* XXX : not implemented */
2553 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2554 SPR_NOACCESS, SPR_NOACCESS,
2555 &spr_read_generic, &spr_write_generic,
2556 0x00000000);
2557 /* XXX : not implemented */
2558 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2559 SPR_NOACCESS, SPR_NOACCESS,
2560 &spr_read_generic, &spr_write_generic,
2561 0x00000000);
2562 /* XXX : not implemented */
2563 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2564 SPR_NOACCESS, SPR_NOACCESS,
2565 &spr_read_generic, &spr_write_generic,
2566 0x00000000);
2567 /* XXX : not implemented */
2568 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2569 SPR_NOACCESS, SPR_NOACCESS,
2570 &spr_read_generic, &spr_write_generic,
2571 0x00000000);
2572 /* XXX : not implemented */
2573 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2574 SPR_NOACCESS, SPR_NOACCESS,
2575 &spr_read_generic, &spr_write_generic,
2576 0x00000000);
2577 /* XXX : not implemented */
2578 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2579 SPR_NOACCESS, SPR_NOACCESS,
2580 &spr_read_generic, &spr_write_generic,
2581 0x00000000);
2582 /* XXX : not implemented */
2583 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2584 SPR_NOACCESS, SPR_NOACCESS,
2585 &spr_read_generic, &spr_write_generic,
2586 0x00000000);
2587 /* XXX : not implemented */
2588 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2589 SPR_NOACCESS, SPR_NOACCESS,
2590 &spr_read_generic, &spr_write_generic,
2591 0x00000000);
2592 /* XXX : not implemented */
2593 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2594 SPR_NOACCESS, SPR_NOACCESS,
2595 &spr_read_generic, &spr_write_generic,
2596 0x00000000);
2597 /* XXX : not implemented */
2598 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2599 SPR_NOACCESS, SPR_NOACCESS,
2600 &spr_read_generic, &spr_write_generic,
2601 0x00000000);
2602 /* XXX : not implemented */
2603 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2604 SPR_NOACCESS, SPR_NOACCESS,
2605 &spr_read_generic, &spr_write_generic,
2606 0x00000000);
2607 /* XXX : not implemented */
2608 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2609 SPR_NOACCESS, SPR_NOACCESS,
2610 &spr_read_generic, &spr_write_generic,
2611 0x00000000);
2612}
2613
2614// XXX: TODO
2615/*
2616 * AMR => SPR 29 (Power 2.04)
2617 * CTRL => SPR 136 (Power 2.04)
2618 * CTRL => SPR 152 (Power 2.04)
2619 * SCOMC => SPR 276 (64 bits ?)
2620 * SCOMD => SPR 277 (64 bits ?)
2621 * TBU40 => SPR 286 (Power 2.04 hypv)
2622 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2623 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2624 * HDSISR => SPR 306 (Power 2.04 hypv)
2625 * HDAR => SPR 307 (Power 2.04 hypv)
2626 * PURR => SPR 309 (Power 2.04 hypv)
2627 * HDEC => SPR 310 (Power 2.04 hypv)
2628 * HIOR => SPR 311 (hypv)
2629 * RMOR => SPR 312 (970)
2630 * HRMOR => SPR 313 (Power 2.04 hypv)
2631 * HSRR0 => SPR 314 (Power 2.04 hypv)
2632 * HSRR1 => SPR 315 (Power 2.04 hypv)
2633 * LPCR => SPR 316 (970)
2634 * LPIDR => SPR 317 (970)
80d11f44
JM		 2635 * EPR => SPR 702 (Power 2.04 emb)
2636 * perf => 768-783 (Power 2.04)
2637 * perf => 784-799 (Power 2.04)
2638 * PPR => SPR 896 (Power 2.04)
2639 * EPLC => SPR 947 (Power 2.04 emb)
2640 * EPSC => SPR 948 (Power 2.04 emb)
2641 * DABRX => 1015 (Power 2.04 hypv)
2642 * FPECR => SPR 1022 (?)
2643 * ... and more (thermal management, performance counters, ...)
2644 */
2645
2646/*****************************************************************************/
2647/* Exception vectors models */
2648static void init_excp_4xx_real (CPUPPCState *env)
2649{
2650#if !defined(CONFIG_USER_ONLY)
2651 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2652 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2653 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2654 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2655 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2656 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2657 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2658 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2659 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2660 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2661 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2662 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2663 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2664 /* Hardware reset vector */
2665 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2666#endif
2667}
2668
80d11f44
JM		 2669static void init_excp_4xx_softmmu (CPUPPCState *env)
2670{
2671#if !defined(CONFIG_USER_ONLY)
2672 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2673 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2674 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2675 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2676 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2677 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2678 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2680 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2681 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2682 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2683 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2684 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2685 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2686 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2687 env->ivor_mask = 0x0000FFF0UL;
2688 env->ivpr_mask = 0xFFFF0000UL;
2689 /* Hardware reset vector */
2690 env->hreset_vector = 0xFFFFFFFCUL;
2691#endif
2692}
2693
2694static void init_excp_MPC5xx (CPUPPCState *env)
2695{
2696#if !defined(CONFIG_USER_ONLY)
2697 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2698 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2699 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2700 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2701 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2702 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2703 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2704 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2705 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2706 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2707 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2708 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2709 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2710 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2711 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2712 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2713 env->ivor_mask = 0x0000FFF0UL;
2714 env->ivpr_mask = 0xFFFF0000UL;
2715 /* Hardware reset vector */
2716 env->hreset_vector = 0xFFFFFFFCUL;
2717#endif
2718}
2719
2720static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2721{
2722#if !defined(CONFIG_USER_ONLY)
2723 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2724 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2725 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2726 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2733 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2734 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2735 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2736 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2737 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2738 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2739 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2740 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2741 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2742 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2743 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2744 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2745 env->ivor_mask = 0x0000FFF0UL;
2746 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2747 /* Hardware reset vector */
80d11f44 2748 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2749#endif
2750}
2751
80d11f44 2752static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2753{
2754#if !defined(CONFIG_USER_ONLY)
2755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2756 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2757 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2758 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2759 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2760 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2761 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2762 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2763 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2764 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2765 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2766 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2767 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2768 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2769 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2770 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2771 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2772 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2773 /* Hardware reset vector */
2774 env->hreset_vector = 0xFFFFFFFCUL;
2775#endif
2776}
2777
2778static void init_excp_e200 (CPUPPCState *env)
2779{
2780#if !defined(CONFIG_USER_ONLY)
2781 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2782 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2783 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2784 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2785 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2786 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2787 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2788 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2789 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2790 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2791 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2792 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2793 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2794 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2795 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2796 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2797 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2798 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2799 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2800 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2801 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2802 env->ivor_mask = 0x0000FFF7UL;
2803 env->ivpr_mask = 0xFFFF0000UL;
2804 /* Hardware reset vector */
2805 env->hreset_vector = 0xFFFFFFFCUL;
2806#endif
2807}
2808
2809static void init_excp_BookE (CPUPPCState *env)
2810{
2811#if !defined(CONFIG_USER_ONLY)
2812 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2828 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2829 env->ivor_mask = 0x0000FFE0UL;
2830 env->ivpr_mask = 0xFFFF0000UL;
2831 /* Hardware reset vector */
2832 env->hreset_vector = 0xFFFFFFFCUL;
2833#endif
2834}
2835
2836static void init_excp_601 (CPUPPCState *env)
2837{
2838#if !defined(CONFIG_USER_ONLY)
2839 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2840 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2841 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2842 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2843 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2844 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2845 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2846 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2847 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2848 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2849 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2850 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2851 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2852 /* Hardware reset vector */
80d11f44 2853 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2854#endif
2855}
2856
80d11f44 2857static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2858{
2859#if !defined(CONFIG_USER_ONLY)
082c6681 2860 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2861 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2863 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2864 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2865 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2866 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2867 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2868 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2870 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2872 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2873 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2874 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2875 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2876 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2877 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2878 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2879 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2880 /* Hardware reset vector */
2881 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2882#endif
2883}
2884
80d11f44 2885static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2886{
2887#if !defined(CONFIG_USER_ONLY)
2888 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2889 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2890 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2891 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2892 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2893 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2894 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2895 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2896 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2897 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2898 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2899 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2900 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2901 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2902 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2903 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2904 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2905 /* Hardware reset vector */
2906 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2907#endif
2908}
2909
2910static void init_excp_604 (CPUPPCState *env)
2911{
2912#if !defined(CONFIG_USER_ONLY)
2913 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2914 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2915 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2916 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2917 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2918 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2919 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2920 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2921 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2922 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2923 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2924 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2925 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2926 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2927 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2928 /* Hardware reset vector */
2d3eb7bf 2929 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2930#endif
2931}
2932
578bb252 2933#if defined(TARGET_PPC64)
e1833e1f
JM		 2934static void init_excp_620 (CPUPPCState *env)
2935{
2936#if !defined(CONFIG_USER_ONLY)
2937 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2938 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2939 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2940 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2941 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2942 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2943 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2944 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2945 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2946 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2947 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2948 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2949 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2950 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2951 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2952 /* Hardware reset vector */
faadf50e 2953 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2954#endif
2955}
578bb252 2956#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2957
2958static void init_excp_7x0 (CPUPPCState *env)
2959{
2960#if !defined(CONFIG_USER_ONLY)
2961 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2962 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2963 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2964 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2965 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2967 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2968 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2969 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2970 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2971 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2972 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2973 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 2974 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 2975 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 2976 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2977 /* Hardware reset vector */
2978 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2979#endif
2980}
2981
bd928eba 2982static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 2983{
2984#if !defined(CONFIG_USER_ONLY)
2985 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2986 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2987 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2988 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2989 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2990 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2991 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2992 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2993 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2994 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2995 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2996 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2997 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2998 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2999 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3000 /* Hardware reset vector */
3001 env->hreset_vector = 0xFFFFFFFCUL;
3002#endif
3003}
3004
3005static void init_excp_750cx (CPUPPCState *env)
3006{
3007#if !defined(CONFIG_USER_ONLY)
3008 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3009 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3010 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3012 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3013 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3014 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3015 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3016 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3020 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3021 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3022 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3023 /* Hardware reset vector */
3024 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3025#endif
3026}
3027
7a3a6927
JM		 3028/* XXX: Check if this is correct */
3029static void init_excp_7x5 (CPUPPCState *env)
3030{
3031#if !defined(CONFIG_USER_ONLY)
3032 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3033 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3034 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3036 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3037 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3038 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3039 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3040 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3041 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3042 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3043 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3044 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3045 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3046 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3047 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3048 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3049 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3050 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3051 /* Hardware reset vector */
3052 env->hreset_vector = 0xFFFFFFFCUL;
3053#endif
3054}
3055
e1833e1f
JM		 3056static void init_excp_7400 (CPUPPCState *env)
3057{
3058#if !defined(CONFIG_USER_ONLY)
3059 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3060 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3061 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3062 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3063 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3064 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3065 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3066 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3067 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3068 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3069 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3070 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3071 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3072 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3073 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3074 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3075 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3076 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3077 /* Hardware reset vector */
3078 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3079#endif
3080}
3081
e1833e1f
JM		 3082static void init_excp_7450 (CPUPPCState *env)
3083{
3084#if !defined(CONFIG_USER_ONLY)
3085 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3086 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3087 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3088 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3089 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3090 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3091 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3092 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3093 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3094 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3095 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3096 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3097 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3098 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3099 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3100 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3104 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3107#endif
3108}
e1833e1f
JM		 3109
3110#if defined (TARGET_PPC64)
3111static void init_excp_970 (CPUPPCState *env)
3112{
3113#if !defined(CONFIG_USER_ONLY)
3114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3117 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3118 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3119 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3120 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3121 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3122 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3123 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3124 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3125 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3126 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3127 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3128 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3129 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3130 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3131 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3132 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3133 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3134 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3135 /* Hardware reset vector */
3136 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3137#endif
3138}
3139#endif
3140
2f462816
JM		 3141/*****************************************************************************/
3142/* Power management enable checks */
3143static int check_pow_none (CPUPPCState *env)
3144{
3145 return 0;
3146}
3147
3148static int check_pow_nocheck (CPUPPCState *env)
3149{
3150 return 1;
3151}
3152
3153static int check_pow_hid0 (CPUPPCState *env)
3154{
3155 if (env->spr[SPR_HID0] & 0x00E00000)
3156 return 1;
3157
3158 return 0;
3159}
3160
4e777442
JM		 3161static int check_pow_hid0_74xx (CPUPPCState *env)
3162{
3163 if (env->spr[SPR_HID0] & 0x00600000)
3164 return 1;
3165
3166 return 0;
3167}
3168
a750fc0b
JM		 3169/*****************************************************************************/
3170/* PowerPC implementations definitions */
76a66253 3171
a750fc0b 3172/* PowerPC 401 */
082c6681
JM		 3173#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3174 PPC_WRTEE | PPC_DCR | \
3175 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3176 PPC_CACHE_DCBZ | \
a750fc0b 3177 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3178 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3179#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3180#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3181#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3182#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3183#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3184#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3185 POWERPC_FLAG_BUS_CLK)
2f462816 3186#define check_pow_401 check_pow_nocheck
76a66253 3187
a750fc0b
JM		 3188static void init_proc_401 (CPUPPCState *env)
3189{
3190 gen_spr_40x(env);
3191 gen_spr_401_403(env);
3192 gen_spr_401(env);
e1833e1f 3193 init_excp_4xx_real(env);
d63001d1
JM		 3194 env->dcache_line_size = 32;
3195 env->icache_line_size = 32;
4e290a0b
JM		 3196 /* Allocate hardware IRQ controller */
3197 ppc40x_irq_init(env);
a750fc0b 3198}
76a66253 3199
a750fc0b 3200/* PowerPC 401x2 */
082c6681
JM		 3201#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3202 PPC_DCR | PPC_WRTEE | \
3203 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3204 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3205 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3206 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3207 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3208#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3209#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3210#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3211#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3212#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3213#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3214 POWERPC_FLAG_BUS_CLK)
2f462816 3215#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3216
3217static void init_proc_401x2 (CPUPPCState *env)
3218{
3219 gen_spr_40x(env);
3220 gen_spr_401_403(env);
3221 gen_spr_401x2(env);
3222 gen_spr_compress(env);
a750fc0b 3223 /* Memory management */
f2e63a42 3224#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3225 env->nb_tlb = 64;
3226 env->nb_ways = 1;
3227 env->id_tlbs = 0;
f2e63a42 3228#endif
e1833e1f 3229 init_excp_4xx_softmmu(env);
d63001d1
JM		 3230 env->dcache_line_size = 32;
3231 env->icache_line_size = 32;
4e290a0b
JM		 3232 /* Allocate hardware IRQ controller */
3233 ppc40x_irq_init(env);
76a66253
JM		 3234}
3235
a750fc0b 3236/* PowerPC 401x3 */
082c6681
JM		 3237#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3238 PPC_DCR | PPC_WRTEE | \
3239 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3240 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3241 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3242 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3243 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3244#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3245#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3246#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3247#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3248#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3249#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3250 POWERPC_FLAG_BUS_CLK)
2f462816 3251#define check_pow_401x3 check_pow_nocheck
a750fc0b 3252
578bb252 3253__attribute__ (( unused ))
e1833e1f 3254static void init_proc_401x3 (CPUPPCState *env)
76a66253 3255{
4e290a0b
JM		 3256 gen_spr_40x(env);
3257 gen_spr_401_403(env);
3258 gen_spr_401(env);
3259 gen_spr_401x2(env);
3260 gen_spr_compress(env);
e1833e1f 3261 init_excp_4xx_softmmu(env);
d63001d1
JM		 3262 env->dcache_line_size = 32;
3263 env->icache_line_size = 32;
4e290a0b
JM		 3264 /* Allocate hardware IRQ controller */
3265 ppc40x_irq_init(env);
3fc6c082 3266}
a750fc0b
JM		 3267
3268/* IOP480 */
082c6681
JM		 3269#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3270 PPC_DCR | PPC_WRTEE | \
3271 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3272 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3273 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3274 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3275 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3276#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3277#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3278#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3279#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3280#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3281#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3282 POWERPC_FLAG_BUS_CLK)
2f462816 3283#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3284
3285static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3286{
a750fc0b
JM		 3287 gen_spr_40x(env);
3288 gen_spr_401_403(env);
3289 gen_spr_401x2(env);
3290 gen_spr_compress(env);
a750fc0b 3291 /* Memory management */
f2e63a42 3292#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3293 env->nb_tlb = 64;
3294 env->nb_ways = 1;
3295 env->id_tlbs = 0;
f2e63a42 3296#endif
e1833e1f 3297 init_excp_4xx_softmmu(env);
d63001d1
JM		 3298 env->dcache_line_size = 32;
3299 env->icache_line_size = 32;
4e290a0b
JM		 3300 /* Allocate hardware IRQ controller */
3301 ppc40x_irq_init(env);
3fc6c082
FB		 3302}
3303
a750fc0b 3304/* PowerPC 403 */
082c6681
JM		 3305#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3306 PPC_DCR | PPC_WRTEE | \
3307 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3308 PPC_CACHE_DCBZ | \
a750fc0b 3309 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3310 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3311#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3312#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3313#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3314#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3315#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3316#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3317 POWERPC_FLAG_BUS_CLK)
2f462816 3318#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3319
3320static void init_proc_403 (CPUPPCState *env)
3fc6c082 3321{
a750fc0b
JM		 3322 gen_spr_40x(env);
3323 gen_spr_401_403(env);
3324 gen_spr_403(env);
3325 gen_spr_403_real(env);
e1833e1f 3326 init_excp_4xx_real(env);
d63001d1
JM		 3327 env->dcache_line_size = 32;
3328 env->icache_line_size = 32;
4e290a0b
JM		 3329 /* Allocate hardware IRQ controller */
3330 ppc40x_irq_init(env);
3fc6c082
FB		 3331}
3332
a750fc0b 3333/* PowerPC 403 GCX */
082c6681
JM		 3334#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3335 PPC_DCR | PPC_WRTEE | \
3336 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3337 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3338 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3339 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3340 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3341#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3342#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3343#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3344#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3345#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3346#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3347 POWERPC_FLAG_BUS_CLK)
2f462816 3348#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3349
3350static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3351{
a750fc0b
JM		 3352 gen_spr_40x(env);
3353 gen_spr_401_403(env);
3354 gen_spr_403(env);
3355 gen_spr_403_real(env);
3356 gen_spr_403_mmu(env);
3357 /* Bus access control */
035feb88 3358 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3359 spr_register(env, SPR_40x_SGR, "SGR",
3360 SPR_NOACCESS, SPR_NOACCESS,
3361 &spr_read_generic, &spr_write_generic,
3362 0xFFFFFFFF);
035feb88 3363 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3364 spr_register(env, SPR_40x_DCWR, "DCWR",
3365 SPR_NOACCESS, SPR_NOACCESS,
3366 &spr_read_generic, &spr_write_generic,
3367 0x00000000);
3368 /* Memory management */
f2e63a42 3369#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3370 env->nb_tlb = 64;
3371 env->nb_ways = 1;
3372 env->id_tlbs = 0;
f2e63a42 3373#endif
80d11f44
JM		 3374 init_excp_4xx_softmmu(env);
3375 env->dcache_line_size = 32;
3376 env->icache_line_size = 32;
3377 /* Allocate hardware IRQ controller */
3378 ppc40x_irq_init(env);
3379}
3380
3381/* PowerPC 405 */
082c6681
JM		 3382#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3383 PPC_DCR | PPC_WRTEE | \
3384 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3385 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3386 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3387 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3388 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
80d11f44
JM		 3389#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3390#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3391#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3392#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3393#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3394#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3395 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3396#define check_pow_405 check_pow_nocheck
3397
3398static void init_proc_405 (CPUPPCState *env)
3399{
3400 /* Time base */
3401 gen_tbl(env);
3402 gen_spr_40x(env);
3403 gen_spr_405(env);
3404 /* Bus access control */
3405 /* not emulated, as Qemu never does speculative access */
3406 spr_register(env, SPR_40x_SGR, "SGR",
3407 SPR_NOACCESS, SPR_NOACCESS,
3408 &spr_read_generic, &spr_write_generic,
3409 0xFFFFFFFF);
3410 /* not emulated, as Qemu do not emulate caches */
3411 spr_register(env, SPR_40x_DCWR, "DCWR",
3412 SPR_NOACCESS, SPR_NOACCESS,
3413 &spr_read_generic, &spr_write_generic,
3414 0x00000000);
3415 /* Memory management */
3416#if !defined(CONFIG_USER_ONLY)
3417 env->nb_tlb = 64;
3418 env->nb_ways = 1;
3419 env->id_tlbs = 0;
3420#endif
3421 init_excp_4xx_softmmu(env);
3422 env->dcache_line_size = 32;
3423 env->icache_line_size = 32;
3424 /* Allocate hardware IRQ controller */
3425 ppc40x_irq_init(env);
3426}
3427
3428/* PowerPC 440 EP */
082c6681
JM		 3429#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3430 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3431 PPC_CACHE | PPC_CACHE_ICBI | \
3432 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3433 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3434 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3435 PPC_440_SPEC)
80d11f44
JM		 3436#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3437#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3438#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3439#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3440#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3441#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3442 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3443#define check_pow_440EP check_pow_nocheck
3444
3445__attribute__ (( unused ))
3446static void init_proc_440EP (CPUPPCState *env)
3447{
3448 /* Time base */
3449 gen_tbl(env);
3450 gen_spr_BookE(env, 0x000000000000FFFFULL);
3451 gen_spr_440(env);
3452 gen_spr_usprgh(env);
3453 /* Processor identification */
3454 spr_register(env, SPR_BOOKE_PIR, "PIR",
3455 SPR_NOACCESS, SPR_NOACCESS,
3456 &spr_read_generic, &spr_write_pir,
3457 0x00000000);
3458 /* XXX : not implemented */
3459 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3460 SPR_NOACCESS, SPR_NOACCESS,
3461 &spr_read_generic, &spr_write_generic,
3462 0x00000000);
3463 /* XXX : not implemented */
3464 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3465 SPR_NOACCESS, SPR_NOACCESS,
3466 &spr_read_generic, &spr_write_generic,
3467 0x00000000);
3468 /* XXX : not implemented */
3469 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3470 SPR_NOACCESS, SPR_NOACCESS,
3471 &spr_read_generic, &spr_write_generic,
3472 0x00000000);
3473 /* XXX : not implemented */
3474 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3475 SPR_NOACCESS, SPR_NOACCESS,
3476 &spr_read_generic, &spr_write_generic,
3477 0x00000000);
3478 /* XXX : not implemented */
3479 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, &spr_write_generic,
3482 0x00000000);
3483 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3484 SPR_NOACCESS, SPR_NOACCESS,
3485 &spr_read_generic, &spr_write_generic,
3486 0x00000000);
3487 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, &spr_write_generic,
3490 0x00000000);
3491 /* XXX : not implemented */
3492 spr_register(env, SPR_440_CCR1, "CCR1",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0x00000000);
3496 /* Memory management */
3497#if !defined(CONFIG_USER_ONLY)
3498 env->nb_tlb = 64;
3499 env->nb_ways = 1;
3500 env->id_tlbs = 0;
3501#endif
3502 init_excp_BookE(env);
3503 env->dcache_line_size = 32;
3504 env->icache_line_size = 32;
3505 /* XXX: TODO: allocate internal IRQ controller */
3506}
3507
3508/* PowerPC 440 GP */
082c6681
JM		 3509#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3510 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3511 PPC_CACHE | PPC_CACHE_ICBI | \
3512 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3513 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
082c6681
JM		 3514 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3515 PPC_440_SPEC)
80d11f44
JM		 3516#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3517#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3518#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3519#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3520#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3521#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3522 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3523#define check_pow_440GP check_pow_nocheck
3524
3525__attribute__ (( unused ))
3526static void init_proc_440GP (CPUPPCState *env)
3527{
3528 /* Time base */
3529 gen_tbl(env);
3530 gen_spr_BookE(env, 0x000000000000FFFFULL);
3531 gen_spr_440(env);
3532 gen_spr_usprgh(env);
3533 /* Processor identification */
3534 spr_register(env, SPR_BOOKE_PIR, "PIR",
3535 SPR_NOACCESS, SPR_NOACCESS,
3536 &spr_read_generic, &spr_write_pir,
3537 0x00000000);
3538 /* XXX : not implemented */
3539 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3540 SPR_NOACCESS, SPR_NOACCESS,
3541 &spr_read_generic, &spr_write_generic,
3542 0x00000000);
3543 /* XXX : not implemented */
3544 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3545 SPR_NOACCESS, SPR_NOACCESS,
3546 &spr_read_generic, &spr_write_generic,
3547 0x00000000);
3548 /* XXX : not implemented */
3549 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, &spr_write_generic,
3552 0x00000000);
3553 /* XXX : not implemented */
3554 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_generic,
3557 0x00000000);
3558 /* Memory management */
3559#if !defined(CONFIG_USER_ONLY)
3560 env->nb_tlb = 64;
3561 env->nb_ways = 1;
3562 env->id_tlbs = 0;
3563#endif
3564 init_excp_BookE(env);
3565 env->dcache_line_size = 32;
3566 env->icache_line_size = 32;
3567 /* XXX: TODO: allocate internal IRQ controller */
3568}
3569
3570/* PowerPC 440x4 */
082c6681
JM		 3571#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3572 PPC_DCR | PPC_WRTEE | \
3573 PPC_CACHE | PPC_CACHE_ICBI | \
3574 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3575 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44
JM		 3576 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3577 PPC_440_SPEC)
3578#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3579#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3580#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3581#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3582#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3583#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3584 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3585#define check_pow_440x4 check_pow_nocheck
3586
3587__attribute__ (( unused ))
3588static void init_proc_440x4 (CPUPPCState *env)
3589{
3590 /* Time base */
3591 gen_tbl(env);
3592 gen_spr_BookE(env, 0x000000000000FFFFULL);
3593 gen_spr_440(env);
3594 gen_spr_usprgh(env);
3595 /* Processor identification */
3596 spr_register(env, SPR_BOOKE_PIR, "PIR",
3597 SPR_NOACCESS, SPR_NOACCESS,
3598 &spr_read_generic, &spr_write_pir,
3599 0x00000000);
3600 /* XXX : not implemented */
3601 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3602 SPR_NOACCESS, SPR_NOACCESS,
3603 &spr_read_generic, &spr_write_generic,
3604 0x00000000);
3605 /* XXX : not implemented */
3606 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3607 SPR_NOACCESS, SPR_NOACCESS,
3608 &spr_read_generic, &spr_write_generic,
3609 0x00000000);
3610 /* XXX : not implemented */
3611 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3612 SPR_NOACCESS, SPR_NOACCESS,
3613 &spr_read_generic, &spr_write_generic,
3614 0x00000000);
3615 /* XXX : not implemented */
3616 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3617 SPR_NOACCESS, SPR_NOACCESS,
3618 &spr_read_generic, &spr_write_generic,
3619 0x00000000);
3620 /* Memory management */
3621#if !defined(CONFIG_USER_ONLY)
3622 env->nb_tlb = 64;
3623 env->nb_ways = 1;
3624 env->id_tlbs = 0;
3625#endif
3626 init_excp_BookE(env);
d63001d1
JM		 3627 env->dcache_line_size = 32;
3628 env->icache_line_size = 32;
80d11f44 3629 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3630}
3631
80d11f44 3632/* PowerPC 440x5 */
082c6681
JM		 3633#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3634 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3635 PPC_CACHE | PPC_CACHE_ICBI | \
3636 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3637 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3638 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3639 PPC_440_SPEC)
80d11f44
JM		 3640#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3641#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3642#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3643#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3644#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3645#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3646 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3647#define check_pow_440x5 check_pow_nocheck
a750fc0b 3648
80d11f44 3649static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3650{
a750fc0b
JM		 3651 /* Time base */
3652 gen_tbl(env);
80d11f44
JM		 3653 gen_spr_BookE(env, 0x000000000000FFFFULL);
3654 gen_spr_440(env);
3655 gen_spr_usprgh(env);
3656 /* Processor identification */
3657 spr_register(env, SPR_BOOKE_PIR, "PIR",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_pir,
3660 0x00000000);
3661 /* XXX : not implemented */
3662 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3665 0x00000000);
3666 /* XXX : not implemented */
3667 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3668 SPR_NOACCESS, SPR_NOACCESS,
3669 &spr_read_generic, &spr_write_generic,
3670 0x00000000);
3671 /* XXX : not implemented */
3672 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3673 SPR_NOACCESS, SPR_NOACCESS,
3674 &spr_read_generic, &spr_write_generic,
3675 0x00000000);
3676 /* XXX : not implemented */
3677 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3678 SPR_NOACCESS, SPR_NOACCESS,
3679 &spr_read_generic, &spr_write_generic,
3680 0x00000000);
3681 /* XXX : not implemented */
3682 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3683 SPR_NOACCESS, SPR_NOACCESS,
3684 &spr_read_generic, &spr_write_generic,
3685 0x00000000);
3686 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3687 SPR_NOACCESS, SPR_NOACCESS,
3688 &spr_read_generic, &spr_write_generic,
3689 0x00000000);
3690 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3691 SPR_NOACCESS, SPR_NOACCESS,
3692 &spr_read_generic, &spr_write_generic,
3693 0x00000000);
3694 /* XXX : not implemented */
3695 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3696 SPR_NOACCESS, SPR_NOACCESS,
3697 &spr_read_generic, &spr_write_generic,
3698 0x00000000);
3699 /* Memory management */
f2e63a42 3700#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3701 env->nb_tlb = 64;
3702 env->nb_ways = 1;
3703 env->id_tlbs = 0;
f2e63a42 3704#endif
80d11f44 3705 init_excp_BookE(env);
d63001d1
JM		 3706 env->dcache_line_size = 32;
3707 env->icache_line_size = 32;
95070372 3708 ppc40x_irq_init(env);
3fc6c082
FB		 3709}
3710
80d11f44 3711/* PowerPC 460 (guessed) */
082c6681 3712#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3713 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
f4078236 3714 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
082c6681
JM		 3715 PPC_CACHE | PPC_CACHE_ICBI | \
3716 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3717 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3718 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3719 PPC_440_SPEC)
80d11f44
JM		 3720#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3721#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3722#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3723#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3724#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3725#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3726 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3727#define check_pow_460 check_pow_nocheck
a750fc0b 3728
80d11f44
JM		 3729__attribute__ (( unused ))
3730static void init_proc_460 (CPUPPCState *env)
3fc6c082 3731{
a750fc0b
JM		 3732 /* Time base */
3733 gen_tbl(env);
80d11f44 3734 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3735 gen_spr_440(env);
80d11f44
JM		 3736 gen_spr_usprgh(env);
3737 /* Processor identification */
3738 spr_register(env, SPR_BOOKE_PIR, "PIR",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_pir,
3741 0x00000000);
3742 /* XXX : not implemented */
3743 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3744 SPR_NOACCESS, SPR_NOACCESS,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
3747 /* XXX : not implemented */
3748 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3749 SPR_NOACCESS, SPR_NOACCESS,
3750 &spr_read_generic, &spr_write_generic,
3751 0x00000000);
3752 /* XXX : not implemented */
3753 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3754 SPR_NOACCESS, SPR_NOACCESS,
3755 &spr_read_generic, &spr_write_generic,
3756 0x00000000);
3757 /* XXX : not implemented */
3758 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3759 SPR_NOACCESS, SPR_NOACCESS,
3760 &spr_read_generic, &spr_write_generic,
3761 0x00000000);
578bb252 3762 /* XXX : not implemented */
a750fc0b
JM		 3763 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3764 SPR_NOACCESS, SPR_NOACCESS,
3765 &spr_read_generic, &spr_write_generic,
3766 0x00000000);
3767 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3768 SPR_NOACCESS, SPR_NOACCESS,
3769 &spr_read_generic, &spr_write_generic,
3770 0x00000000);
3771 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3772 SPR_NOACCESS, SPR_NOACCESS,
3773 &spr_read_generic, &spr_write_generic,
3774 0x00000000);
578bb252 3775 /* XXX : not implemented */
a750fc0b
JM		 3776 spr_register(env, SPR_440_CCR1, "CCR1",
3777 SPR_NOACCESS, SPR_NOACCESS,
3778 &spr_read_generic, &spr_write_generic,
3779 0x00000000);
80d11f44
JM		 3780 /* XXX : not implemented */
3781 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3782 &spr_read_generic, &spr_write_generic,
3783 &spr_read_generic, &spr_write_generic,
3784 0x00000000);
a750fc0b 3785 /* Memory management */
f2e63a42 3786#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3787 env->nb_tlb = 64;
3788 env->nb_ways = 1;
3789 env->id_tlbs = 0;
f2e63a42 3790#endif
e1833e1f 3791 init_excp_BookE(env);
d63001d1
JM		 3792 env->dcache_line_size = 32;
3793 env->icache_line_size = 32;
a750fc0b 3794 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3795}
3796
80d11f44 3797/* PowerPC 460F (guessed) */
082c6681
JM		 3798#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3799 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3800 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
f4078236 3801 PPC_FLOAT_STFIWX | PPC_MFTB | \
082c6681
JM		 3802 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3803 PPC_WRTEE | PPC_MFAPIDI | \
3804 PPC_CACHE | PPC_CACHE_ICBI | \
3805 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3806 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3807 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3808 PPC_440_SPEC)
80d11f44
JM		 3809#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3810#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3811#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3812#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3813#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3814#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3815 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3816#define check_pow_460F check_pow_nocheck
a750fc0b 3817
80d11f44
JM		 3818__attribute__ (( unused ))
3819static void init_proc_460F (CPUPPCState *env)
3fc6c082 3820{
a750fc0b
JM		 3821 /* Time base */
3822 gen_tbl(env);
80d11f44 3823 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3824 gen_spr_440(env);
80d11f44
JM		 3825 gen_spr_usprgh(env);
3826 /* Processor identification */
3827 spr_register(env, SPR_BOOKE_PIR, "PIR",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_pir,
3830 0x00000000);
3831 /* XXX : not implemented */
3832 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
3836 /* XXX : not implemented */
3837 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 /* XXX : not implemented */
3842 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3843 SPR_NOACCESS, SPR_NOACCESS,
3844 &spr_read_generic, &spr_write_generic,
3845 0x00000000);
3846 /* XXX : not implemented */
3847 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3848 SPR_NOACCESS, SPR_NOACCESS,
3849 &spr_read_generic, &spr_write_generic,
3850 0x00000000);
3851 /* XXX : not implemented */
3852 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3853 SPR_NOACCESS, SPR_NOACCESS,
3854 &spr_read_generic, &spr_write_generic,
3855 0x00000000);
3856 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3857 SPR_NOACCESS, SPR_NOACCESS,
3858 &spr_read_generic, &spr_write_generic,
3859 0x00000000);
3860 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3861 SPR_NOACCESS, SPR_NOACCESS,
3862 &spr_read_generic, &spr_write_generic,
3863 0x00000000);
3864 /* XXX : not implemented */
3865 spr_register(env, SPR_440_CCR1, "CCR1",
3866 SPR_NOACCESS, SPR_NOACCESS,
3867 &spr_read_generic, &spr_write_generic,
3868 0x00000000);
3869 /* XXX : not implemented */
3870 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3871 &spr_read_generic, &spr_write_generic,
3872 &spr_read_generic, &spr_write_generic,
3873 0x00000000);
a750fc0b 3874 /* Memory management */
f2e63a42 3875#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3876 env->nb_tlb = 64;
3877 env->nb_ways = 1;
3878 env->id_tlbs = 0;
f2e63a42 3879#endif
e1833e1f 3880 init_excp_BookE(env);
d63001d1
JM		 3881 env->dcache_line_size = 32;
3882 env->icache_line_size = 32;
a750fc0b 3883 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3884}
3885
80d11f44
JM		 3886/* Freescale 5xx cores (aka RCPU) */
3887#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3888 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3889 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3890 PPC_MFTB)
3891#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3892#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3893#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3894#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3895#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3896#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3897 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3898#define check_pow_MPC5xx check_pow_none
3899
3900__attribute__ (( unused ))
3901static void init_proc_MPC5xx (CPUPPCState *env)
3902{
3903 /* Time base */
3904 gen_tbl(env);
3905 gen_spr_5xx_8xx(env);
3906 gen_spr_5xx(env);
3907 init_excp_MPC5xx(env);
3908 env->dcache_line_size = 32;
3909 env->icache_line_size = 32;
3910 /* XXX: TODO: allocate internal IRQ controller */
3911}
3912
3913/* Freescale 8xx cores (aka PowerQUICC) */
3914#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3915 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3916 PPC_CACHE_ICBI | PPC_MFTB)
3917#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3918#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3919#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3920#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3921#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3922#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3923 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3924#define check_pow_MPC8xx check_pow_none
3925
3926__attribute__ (( unused ))
3927static void init_proc_MPC8xx (CPUPPCState *env)
3928{
3929 /* Time base */
3930 gen_tbl(env);
3931 gen_spr_5xx_8xx(env);
3932 gen_spr_8xx(env);
3933 init_excp_MPC8xx(env);
3934 env->dcache_line_size = 32;
3935 env->icache_line_size = 32;
3936 /* XXX: TODO: allocate internal IRQ controller */
3937}
3938
3939/* Freescale 82xx cores (aka PowerQUICC-II) */
3940/* PowerPC G2 */
082c6681
JM		 3941#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3942 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3943 PPC_FLOAT_STFIWX | \
3944 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3945 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3946 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3947 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3948#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3949#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3950//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3951#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3952#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3953#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3954 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3955#define check_pow_G2 check_pow_hid0
a750fc0b 3956
80d11f44 3957static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3958{
80d11f44
JM		 3959 gen_spr_ne_601(env);
3960 gen_spr_G2_755(env);
3961 gen_spr_G2(env);
a750fc0b
JM		 3962 /* Time base */
3963 gen_tbl(env);
bd928eba
JM		 3964 /* External access control */
3965 /* XXX : not implemented */
3966 spr_register(env, SPR_EAR, "EAR",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
80d11f44
JM		 3970 /* Hardware implementation register */
3971 /* XXX : not implemented */
3972 spr_register(env, SPR_HID0, "HID0",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_generic,
3975 0x00000000);
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_HID1, "HID1",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 /* XXX : not implemented */
3982 spr_register(env, SPR_HID2, "HID2",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985 0x00000000);
a750fc0b 3986 /* Memory management */
80d11f44
JM		 3987 gen_low_BATs(env);
3988 gen_high_BATs(env);
3989 gen_6xx_7xx_soft_tlb(env, 64, 2);
3990 init_excp_G2(env);
d63001d1
JM		 3991 env->dcache_line_size = 32;
3992 env->icache_line_size = 32;
80d11f44
JM		 3993 /* Allocate hardware IRQ controller */
3994 ppc6xx_irq_init(env);
3fc6c082 3995}
a750fc0b 3996
80d11f44 3997/* PowerPC G2LE */
082c6681
JM		 3998#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3999 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4000 PPC_FLOAT_STFIWX | \
4001 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4002 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4003 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4004 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4005#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4006#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4007#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4008#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4009#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4010#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4011 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4012#define check_pow_G2LE check_pow_hid0
a750fc0b 4013
80d11f44 4014static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4015{
80d11f44
JM		 4016 gen_spr_ne_601(env);
4017 gen_spr_G2_755(env);
4018 gen_spr_G2(env);
a750fc0b
JM		 4019 /* Time base */
4020 gen_tbl(env);
bd928eba
JM		 4021 /* External access control */
4022 /* XXX : not implemented */
4023 spr_register(env, SPR_EAR, "EAR",
4024 SPR_NOACCESS, SPR_NOACCESS,
4025 &spr_read_generic, &spr_write_generic,
4026 0x00000000);
80d11f44 4027 /* Hardware implementation register */
578bb252 4028 /* XXX : not implemented */
80d11f44 4029 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4030 SPR_NOACCESS, SPR_NOACCESS,
4031 &spr_read_generic, &spr_write_generic,
4032 0x00000000);
80d11f44
JM		 4033 /* XXX : not implemented */
4034 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4035 SPR_NOACCESS, SPR_NOACCESS,
4036 &spr_read_generic, &spr_write_generic,
4037 0x00000000);
578bb252 4038 /* XXX : not implemented */
80d11f44 4039 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4040 SPR_NOACCESS, SPR_NOACCESS,
4041 &spr_read_generic, &spr_write_generic,
4042 0x00000000);
4043 /* Memory management */
80d11f44
JM		 4044 gen_low_BATs(env);
4045 gen_high_BATs(env);
4046 gen_6xx_7xx_soft_tlb(env, 64, 2);
4047 init_excp_G2(env);
d63001d1
JM		 4048 env->dcache_line_size = 32;
4049 env->icache_line_size = 32;
80d11f44
JM		 4050 /* Allocate hardware IRQ controller */
4051 ppc6xx_irq_init(env);
3fc6c082
FB		 4052}
4053
80d11f44
JM		 4054/* e200 core */
4055/* XXX: unimplemented instructions:
4056 * dcblc
4057 * dcbtlst
4058 * dcbtstls
4059 * icblc
4060 * icbtls
4061 * tlbivax
4062 * all SPE multiply-accumulate instructions
4063 */
082c6681 4064#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4065 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4066 PPC_WRTEE | PPC_RFDI | \
4067 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4068 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4069 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4070 PPC_BOOKE)
80d11f44
JM		 4071#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4072#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
4073#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4074#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4075#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4076#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4077 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4078 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4079#define check_pow_e200 check_pow_hid0
4080
578bb252 4081__attribute__ (( unused ))
80d11f44 4082static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4083{
e1833e1f
JM		 4084 /* Time base */
4085 gen_tbl(env);
80d11f44 4086 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4087 /* XXX : not implemented */
80d11f44 4088 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4089 &spr_read_spefscr, &spr_write_spefscr,
4090 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4091 0x00000000);
80d11f44
JM		 4092 /* Memory management */
4093 gen_spr_BookE_FSL(env, 0x0000005D);
4094 /* XXX : not implemented */
4095 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_generic,
4098 0x00000000);
80d11f44
JM		 4099 /* XXX : not implemented */
4100 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4101 SPR_NOACCESS, SPR_NOACCESS,
4102 &spr_read_generic, &spr_write_generic,
4103 0x00000000);
578bb252 4104 /* XXX : not implemented */
80d11f44 4105 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4106 SPR_NOACCESS, SPR_NOACCESS,
4107 &spr_read_generic, &spr_write_generic,
4108 0x00000000);
578bb252 4109 /* XXX : not implemented */
80d11f44
JM		 4110 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4111 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4112 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4113 0x00000000);
4114 /* XXX : not implemented */
4115 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4116 SPR_NOACCESS, SPR_NOACCESS,
4117 &spr_read_generic, &spr_write_generic,
4118 0x00000000);
4119 /* XXX : not implemented */
4120 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4121 SPR_NOACCESS, SPR_NOACCESS,
4122 &spr_read_generic, &spr_write_generic,
4123 0x00000000);
4124 /* XXX : not implemented */
4125 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4126 SPR_NOACCESS, SPR_NOACCESS,
4127 &spr_read_generic, &spr_write_generic,
4128 0x00000000);
4129 /* XXX : not implemented */
4130 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4131 SPR_NOACCESS, SPR_NOACCESS,
4132 &spr_read_generic, &spr_write_generic,
4133 0x00000000);
4134 /* XXX : not implemented */
4135 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4136 SPR_NOACCESS, SPR_NOACCESS,
4137 &spr_read_generic, &spr_write_generic,
4138 0x00000000);
4139 /* XXX : not implemented */
4140 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4141 SPR_NOACCESS, SPR_NOACCESS,
4142 &spr_read_generic, &spr_write_generic,
4143 0x00000000);
4144 /* XXX : not implemented */
4145 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4146 SPR_NOACCESS, SPR_NOACCESS,
4147 &spr_read_generic, &spr_write_generic,
4148 0x00000000);
4149 /* XXX : not implemented */
4150 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4151 SPR_NOACCESS, SPR_NOACCESS,
4152 &spr_read_generic, &spr_write_generic,
4153 0x00000000);
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
4168 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4169 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4170 &spr_read_generic, &spr_write_generic,
4171 0x00000000);
f2e63a42 4172#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4173 env->nb_tlb = 64;
4174 env->nb_ways = 1;
4175 env->id_tlbs = 0;
f2e63a42 4176#endif
80d11f44 4177 init_excp_e200(env);
d63001d1
JM		 4178 env->dcache_line_size = 32;
4179 env->icache_line_size = 32;
e1833e1f 4180 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4181}
a750fc0b 4182
80d11f44 4183/* e300 core */
082c6681
JM		 4184#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4185 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4186 PPC_FLOAT_STFIWX | \
4187 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4188 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4189 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4190 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4191#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4192#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4193#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4194#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4195#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4196#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4197 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4198#define check_pow_e300 check_pow_hid0
a750fc0b 4199
578bb252 4200__attribute__ (( unused ))
80d11f44 4201static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4202{
80d11f44
JM		 4203 gen_spr_ne_601(env);
4204 gen_spr_603(env);
a750fc0b
JM		 4205 /* Time base */
4206 gen_tbl(env);
80d11f44
JM		 4207 /* hardware implementation registers */
4208 /* XXX : not implemented */
4209 spr_register(env, SPR_HID0, "HID0",
4210 SPR_NOACCESS, SPR_NOACCESS,
4211 &spr_read_generic, &spr_write_generic,
4212 0x00000000);
4213 /* XXX : not implemented */
4214 spr_register(env, SPR_HID1, "HID1",
4215 SPR_NOACCESS, SPR_NOACCESS,
4216 &spr_read_generic, &spr_write_generic,
4217 0x00000000);
8daf1781
TM		 4218 /* XXX : not implemented */
4219 spr_register(env, SPR_HID2, "HID2",
4220 SPR_NOACCESS, SPR_NOACCESS,
4221 &spr_read_generic, &spr_write_generic,
4222 0x00000000);
80d11f44
JM		 4223 /* Memory management */
4224 gen_low_BATs(env);
8daf1781 4225 gen_high_BATs(env);
80d11f44
JM		 4226 gen_6xx_7xx_soft_tlb(env, 64, 2);
4227 init_excp_603(env);
4228 env->dcache_line_size = 32;
4229 env->icache_line_size = 32;
4230 /* Allocate hardware IRQ controller */
4231 ppc6xx_irq_init(env);
4232}
4233
bd5ea513
AJ		 4234/* e500v1 core */
4235#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4236 PPC_SPE | PPC_SPE_SINGLE | \
4237 PPC_WRTEE | PPC_RFDI | \
4238 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4239 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4240 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4241 PPC_BOOKE)
4242#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4243#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
4244#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4245#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4246#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4247#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4248 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4249 POWERPC_FLAG_BUS_CLK)
4250#define check_pow_e500v1 check_pow_hid0
4251#define init_proc_e500v1 init_proc_e500
4252
4253/* e500v2 core */
4254#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4255 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4256 PPC_WRTEE | PPC_RFDI | \
4257 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4258 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4259 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4260 PPC_BOOKE)
4261#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4262#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
4263#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4264#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4265#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4266#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4267 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4268 POWERPC_FLAG_BUS_CLK)
4269#define check_pow_e500v2 check_pow_hid0
4270#define init_proc_e500v2 init_proc_e500
80d11f44 4271
80d11f44
JM		 4272static void init_proc_e500 (CPUPPCState *env)
4273{
4274 /* Time base */
4275 gen_tbl(env);
4276 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4277 /* Processor identification */
4278 spr_register(env, SPR_BOOKE_PIR, "PIR",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_pir,
4281 0x00000000);
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4284 &spr_read_spefscr, &spr_write_spefscr,
4285 &spr_read_spefscr, &spr_write_spefscr,
80d11f44
JM		 4286 0x00000000);
4287 /* Memory management */
4288#if !defined(CONFIG_USER_ONLY)
4289 env->nb_pids = 3;
4290#endif
4291 gen_spr_BookE_FSL(env, 0x0000005F);
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_HID0, "HID0",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 /* XXX : not implemented */
4298 spr_register(env, SPR_HID1, "HID1",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302 /* XXX : not implemented */
4303 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4304 SPR_NOACCESS, SPR_NOACCESS,
4305 &spr_read_generic, &spr_write_generic,
4306 0x00000000);
4307 /* XXX : not implemented */
4308 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4309 SPR_NOACCESS, SPR_NOACCESS,
4310 &spr_read_generic, &spr_write_generic,
4311 0x00000000);
4312 /* XXX : not implemented */
4313 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4314 SPR_NOACCESS, SPR_NOACCESS,
4315 &spr_read_generic, &spr_write_generic,
4316 0x00000000);
578bb252 4317 /* XXX : not implemented */
a750fc0b
JM		 4318 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4319 SPR_NOACCESS, SPR_NOACCESS,
4320 &spr_read_generic, &spr_write_generic,
4321 0x00000000);
80d11f44
JM		 4322 /* XXX : not implemented */
4323 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4324 SPR_NOACCESS, SPR_NOACCESS,
4325 &spr_read_generic, &spr_write_generic,
4326 0x00000000);
80d11f44
JM		 4327 /* XXX : not implemented */
4328 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4329 SPR_NOACCESS, SPR_NOACCESS,
4330 &spr_read_generic, &spr_write_generic,
4331 0x00000000);
578bb252 4332 /* XXX : not implemented */
80d11f44 4333 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4334 SPR_NOACCESS, SPR_NOACCESS,
4335 &spr_read_generic, &spr_write_generic,
4336 0x00000000);
578bb252 4337 /* XXX : not implemented */
80d11f44
JM		 4338 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4339 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4340 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4341 0x00000000);
4342 /* XXX : not implemented */
4343 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4344 SPR_NOACCESS, SPR_NOACCESS,
4345 &spr_read_generic, &spr_write_generic,
4346 0x00000000);
4347 /* XXX : not implemented */
4348 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4349 SPR_NOACCESS, SPR_NOACCESS,
4350 &spr_read_generic, &spr_write_generic,
4351 0x00000000);
4352 /* XXX : not implemented */
4353 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
4357 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4358 SPR_NOACCESS, SPR_NOACCESS,
4359 &spr_read_generic, &spr_write_generic,
4360 0x00000000);
4361 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4362 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4363 &spr_read_generic, &spr_write_generic,
4364 0x00000000);
f2e63a42 4365#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4366 env->nb_tlb = 64;
4367 env->nb_ways = 1;
4368 env->id_tlbs = 0;
f2e63a42 4369#endif
80d11f44 4370 init_excp_e200(env);
d63001d1
JM		 4371 env->dcache_line_size = 32;
4372 env->icache_line_size = 32;
9fdc60bf
AJ		 4373 /* Allocate hardware IRQ controller */
4374 ppce500_irq_init(env);
3fc6c082 4375}
a750fc0b 4376
a750fc0b 4377/* Non-embedded PowerPC */
a750fc0b
JM		 4378
4379/* POWER : same as 601, without mfmsr, mfsr */
4380#if defined(TODO)
4381#define POWERPC_INSNS_POWER (XXX_TODO)
4382/* POWER RSC (from RAD6000) */
4383#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4384#endif /* TODO */
4385
4386/* PowerPC 601 */
082c6681
JM		 4387#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4388 PPC_FLOAT | \
4389 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4390 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4391 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4392#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4393#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4394//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4395//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4396#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4397#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4398#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4399#define check_pow_601 check_pow_none
a750fc0b
JM		 4400
4401static void init_proc_601 (CPUPPCState *env)
3fc6c082 4402{
a750fc0b
JM		 4403 gen_spr_ne_601(env);
4404 gen_spr_601(env);
4405 /* Hardware implementation registers */
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_HID0, "HID0",
4408 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4409 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4410 0x80010080);
a750fc0b
JM		 4411 /* XXX : not implemented */
4412 spr_register(env, SPR_HID1, "HID1",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* XXX : not implemented */
4417 spr_register(env, SPR_601_HID2, "HID2",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421 /* XXX : not implemented */
4422 spr_register(env, SPR_601_HID5, "HID5",
4423 SPR_NOACCESS, SPR_NOACCESS,
4424 &spr_read_generic, &spr_write_generic,
4425 0x00000000);
a750fc0b 4426 /* Memory management */
e1833e1f 4427 init_excp_601(env);
082c6681
JM		 4428 /* XXX: beware that dcache line size is 64
4429 * but dcbz uses 32 bytes "sectors"
4430 * XXX: this breaks clcs instruction !
4431 */
4432 env->dcache_line_size = 32;
d63001d1 4433 env->icache_line_size = 64;
faadf50e
JM		 4434 /* Allocate hardware IRQ controller */
4435 ppc6xx_irq_init(env);
3fc6c082
FB		 4436}
4437
082c6681
JM		 4438/* PowerPC 601v */
4439#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4440 PPC_FLOAT | \
4441 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4442 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4443 PPC_SEGMENT | PPC_EXTERN)
4444#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4445#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4446#define POWERPC_MMU_601v (POWERPC_MMU_601)
4447#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4448#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4449#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4450#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4451#define check_pow_601v check_pow_none
4452
4453static void init_proc_601v (CPUPPCState *env)
4454{
4455 init_proc_601(env);
4456 /* XXX : not implemented */
4457 spr_register(env, SPR_601_HID15, "HID15",
4458 SPR_NOACCESS, SPR_NOACCESS,
4459 &spr_read_generic, &spr_write_generic,
4460 0x00000000);
4461}
4462
a750fc0b 4463/* PowerPC 602 */
082c6681
JM		 4464#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4465 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4466 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4467 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4468 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4469 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4470 PPC_SEGMENT | PPC_602_SPEC)
082c6681
JM		 4471#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4472/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4473#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4474//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4475#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4476#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4477#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4478 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4479#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4480
4481static void init_proc_602 (CPUPPCState *env)
3fc6c082 4482{
a750fc0b
JM		 4483 gen_spr_ne_601(env);
4484 gen_spr_602(env);
4485 /* Time base */
4486 gen_tbl(env);
4487 /* hardware implementation registers */
4488 /* XXX : not implemented */
4489 spr_register(env, SPR_HID0, "HID0",
4490 SPR_NOACCESS, SPR_NOACCESS,
4491 &spr_read_generic, &spr_write_generic,
4492 0x00000000);
4493 /* XXX : not implemented */
4494 spr_register(env, SPR_HID1, "HID1",
4495 SPR_NOACCESS, SPR_NOACCESS,
4496 &spr_read_generic, &spr_write_generic,
4497 0x00000000);
4498 /* Memory management */
4499 gen_low_BATs(env);
4500 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4501 init_excp_602(env);
d63001d1
JM		 4502 env->dcache_line_size = 32;
4503 env->icache_line_size = 32;
a750fc0b
JM		 4504 /* Allocate hardware IRQ controller */
4505 ppc6xx_irq_init(env);
4506}
3fc6c082 4507
a750fc0b 4508/* PowerPC 603 */
082c6681
JM		 4509#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4510 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4511 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4512 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4513 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4514 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4515 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4516#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4517#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4518//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4519#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4520#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4521#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4522 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4523#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4524
4525static void init_proc_603 (CPUPPCState *env)
4526{
4527 gen_spr_ne_601(env);
4528 gen_spr_603(env);
4529 /* Time base */
4530 gen_tbl(env);
4531 /* hardware implementation registers */
4532 /* XXX : not implemented */
4533 spr_register(env, SPR_HID0, "HID0",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 /* XXX : not implemented */
4538 spr_register(env, SPR_HID1, "HID1",
4539 SPR_NOACCESS, SPR_NOACCESS,
4540 &spr_read_generic, &spr_write_generic,
4541 0x00000000);
4542 /* Memory management */
4543 gen_low_BATs(env);
4544 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4545 init_excp_603(env);
d63001d1
JM		 4546 env->dcache_line_size = 32;
4547 env->icache_line_size = 32;
a750fc0b
JM		 4548 /* Allocate hardware IRQ controller */
4549 ppc6xx_irq_init(env);
3fc6c082
FB		 4550}
4551
a750fc0b 4552/* PowerPC 603e */
082c6681
JM		 4553#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4554 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4555 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4556 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4557 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4558 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4559 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4560#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4561#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4562//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4563#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4564#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4565#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4566 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4567#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4568
4569static void init_proc_603E (CPUPPCState *env)
4570{
4571 gen_spr_ne_601(env);
4572 gen_spr_603(env);
4573 /* Time base */
4574 gen_tbl(env);
4575 /* hardware implementation registers */
4576 /* XXX : not implemented */
4577 spr_register(env, SPR_HID0, "HID0",
4578 SPR_NOACCESS, SPR_NOACCESS,
4579 &spr_read_generic, &spr_write_generic,
4580 0x00000000);
4581 /* XXX : not implemented */
4582 spr_register(env, SPR_HID1, "HID1",
4583 SPR_NOACCESS, SPR_NOACCESS,
4584 &spr_read_generic, &spr_write_generic,
4585 0x00000000);
4586 /* XXX : not implemented */
4587 spr_register(env, SPR_IABR, "IABR",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 /* Memory management */
4592 gen_low_BATs(env);
4593 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4594 init_excp_603(env);
d63001d1
JM		 4595 env->dcache_line_size = 32;
4596 env->icache_line_size = 32;
a750fc0b
JM		 4597 /* Allocate hardware IRQ controller */
4598 ppc6xx_irq_init(env);
4599}
4600
a750fc0b 4601/* PowerPC 604 */
082c6681
JM		 4602#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4603 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4604 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4605 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4606 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4607 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4608 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4609#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4610#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4611//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4612#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4613#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4614#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4615 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4616#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4617
4618static void init_proc_604 (CPUPPCState *env)
4619{
4620 gen_spr_ne_601(env);
4621 gen_spr_604(env);
4622 /* Time base */
4623 gen_tbl(env);
4624 /* Hardware implementation registers */
4625 /* XXX : not implemented */
082c6681
JM		 4626 spr_register(env, SPR_HID0, "HID0",
4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
4629 0x00000000);
4630 /* Memory management */
4631 gen_low_BATs(env);
4632 init_excp_604(env);
4633 env->dcache_line_size = 32;
4634 env->icache_line_size = 32;
4635 /* Allocate hardware IRQ controller */
4636 ppc6xx_irq_init(env);
4637}
4638
4639/* PowerPC 604E */
4640#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4641 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4642 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4643 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4644 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4645 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4646 PPC_SEGMENT | PPC_EXTERN)
4647#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4648#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4649#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4650#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4651#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4652#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4653 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4654#define check_pow_604E check_pow_nocheck
4655
4656static void init_proc_604E (CPUPPCState *env)
4657{
4658 gen_spr_ne_601(env);
4659 gen_spr_604(env);
4660 /* XXX : not implemented */
4661 spr_register(env, SPR_MMCR1, "MMCR1",
4662 SPR_NOACCESS, SPR_NOACCESS,
4663 &spr_read_generic, &spr_write_generic,
4664 0x00000000);
4665 /* XXX : not implemented */
4666 spr_register(env, SPR_PMC3, "PMC3",
4667 SPR_NOACCESS, SPR_NOACCESS,
4668 &spr_read_generic, &spr_write_generic,
4669 0x00000000);
4670 /* XXX : not implemented */
4671 spr_register(env, SPR_PMC4, "PMC4",
4672 SPR_NOACCESS, SPR_NOACCESS,
4673 &spr_read_generic, &spr_write_generic,
4674 0x00000000);
4675 /* Time base */
4676 gen_tbl(env);
4677 /* Hardware implementation registers */
4678 /* XXX : not implemented */
a750fc0b
JM		 4679 spr_register(env, SPR_HID0, "HID0",
4680 SPR_NOACCESS, SPR_NOACCESS,
4681 &spr_read_generic, &spr_write_generic,
4682 0x00000000);
4683 /* XXX : not implemented */
4684 spr_register(env, SPR_HID1, "HID1",
4685 SPR_NOACCESS, SPR_NOACCESS,
4686 &spr_read_generic, &spr_write_generic,
4687 0x00000000);
4688 /* Memory management */
4689 gen_low_BATs(env);
e1833e1f 4690 init_excp_604(env);
d63001d1
JM		 4691 env->dcache_line_size = 32;
4692 env->icache_line_size = 32;
a750fc0b
JM		 4693 /* Allocate hardware IRQ controller */
4694 ppc6xx_irq_init(env);
4695}
4696
bd928eba
JM		 4697/* PowerPC 740 */
4698#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4699 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4700 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4701 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4702 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4703 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4704 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 4705#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4706#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4707#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4708#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4709#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4710#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4711 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4712#define check_pow_740 check_pow_hid0
a750fc0b 4713
bd928eba 4714static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4715{
4716 gen_spr_ne_601(env);
4717 gen_spr_7xx(env);
4718 /* Time base */
4719 gen_tbl(env);
4720 /* Thermal management */
4721 gen_spr_thrm(env);
4722 /* Hardware implementation registers */
4723 /* XXX : not implemented */
4724 spr_register(env, SPR_HID0, "HID0",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_generic,
4727 0x00000000);
4728 /* XXX : not implemented */
4729 spr_register(env, SPR_HID1, "HID1",
4730 SPR_NOACCESS, SPR_NOACCESS,
4731 &spr_read_generic, &spr_write_generic,
4732 0x00000000);
4733 /* Memory management */
4734 gen_low_BATs(env);
e1833e1f 4735 init_excp_7x0(env);
d63001d1
JM		 4736 env->dcache_line_size = 32;
4737 env->icache_line_size = 32;
a750fc0b
JM		 4738 /* Allocate hardware IRQ controller */
4739 ppc6xx_irq_init(env);
4740}
4741
bd928eba
JM		 4742/* PowerPC 750 */
4743#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4744 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4745 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4746 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4747 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4748 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4749 PPC_SEGMENT | PPC_EXTERN)
4750#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4751#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4752#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4753#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4754#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4755#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4756 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4757#define check_pow_750 check_pow_hid0
4758
4759static void init_proc_750 (CPUPPCState *env)
4760{
4761 gen_spr_ne_601(env);
4762 gen_spr_7xx(env);
4763 /* XXX : not implemented */
4764 spr_register(env, SPR_L2CR, "L2CR",
4765 SPR_NOACCESS, SPR_NOACCESS,
4766 &spr_read_generic, &spr_write_generic,
4767 0x00000000);
4768 /* Time base */
4769 gen_tbl(env);
4770 /* Thermal management */
4771 gen_spr_thrm(env);
4772 /* Hardware implementation registers */
4773 /* XXX : not implemented */
4774 spr_register(env, SPR_HID0, "HID0",
4775 SPR_NOACCESS, SPR_NOACCESS,
4776 &spr_read_generic, &spr_write_generic,
4777 0x00000000);
4778 /* XXX : not implemented */
4779 spr_register(env, SPR_HID1, "HID1",
4780 SPR_NOACCESS, SPR_NOACCESS,
4781 &spr_read_generic, &spr_write_generic,
4782 0x00000000);
4783 /* Memory management */
4784 gen_low_BATs(env);
4785 /* XXX: high BATs are also present but are known to be bugged on
4786 * die version 1.x
4787 */
4788 init_excp_7x0(env);
4789 env->dcache_line_size = 32;
4790 env->icache_line_size = 32;
4791 /* Allocate hardware IRQ controller */
4792 ppc6xx_irq_init(env);
4793}
4794
4795/* PowerPC 750 CL */
4796/* XXX: not implemented:
4797 * cache lock instructions:
4798 * dcbz_l
4799 * floating point paired instructions
4800 * psq_lux
4801 * psq_lx
4802 * psq_stux
4803 * psq_stx
4804 * ps_abs
4805 * ps_add
4806 * ps_cmpo0
4807 * ps_cmpo1
4808 * ps_cmpu0
4809 * ps_cmpu1
4810 * ps_div
4811 * ps_madd
4812 * ps_madds0
4813 * ps_madds1
4814 * ps_merge00
4815 * ps_merge01
4816 * ps_merge10
4817 * ps_merge11
4818 * ps_mr
4819 * ps_msub
4820 * ps_mul
4821 * ps_muls0
4822 * ps_muls1
4823 * ps_nabs
4824 * ps_neg
4825 * ps_nmadd
4826 * ps_nmsub
4827 * ps_res
4828 * ps_rsqrte
4829 * ps_sel
4830 * ps_sub
4831 * ps_sum0
4832 * ps_sum1
4833 */
4834#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4835 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4836 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4837 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4838 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4839 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4840 PPC_SEGMENT | PPC_EXTERN)
4841#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4842#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4843#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4844#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4845#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4846#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4847 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4848#define check_pow_750cl check_pow_hid0
4849
4850static void init_proc_750cl (CPUPPCState *env)
4851{
4852 gen_spr_ne_601(env);
4853 gen_spr_7xx(env);
4854 /* XXX : not implemented */
4855 spr_register(env, SPR_L2CR, "L2CR",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 /* Time base */
4860 gen_tbl(env);
4861 /* Thermal management */
4862 /* Those registers are fake on 750CL */
4863 spr_register(env, SPR_THRM1, "THRM1",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, &spr_write_generic,
4866 0x00000000);
4867 spr_register(env, SPR_THRM2, "THRM2",
4868 SPR_NOACCESS, SPR_NOACCESS,
4869 &spr_read_generic, &spr_write_generic,
4870 0x00000000);
4871 spr_register(env, SPR_THRM3, "THRM3",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 /* XXX: not implemented */
4876 spr_register(env, SPR_750_TDCL, "TDCL",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 spr_register(env, SPR_750_TDCH, "TDCH",
4881 SPR_NOACCESS, SPR_NOACCESS,
4882 &spr_read_generic, &spr_write_generic,
4883 0x00000000);
4884 /* DMA */
4885 /* XXX : not implemented */
4886 spr_register(env, SPR_750_WPAR, "WPAR",
4887 SPR_NOACCESS, SPR_NOACCESS,
4888 &spr_read_generic, &spr_write_generic,
4889 0x00000000);
4890 spr_register(env, SPR_750_DMAL, "DMAL",
4891 SPR_NOACCESS, SPR_NOACCESS,
4892 &spr_read_generic, &spr_write_generic,
4893 0x00000000);
4894 spr_register(env, SPR_750_DMAU, "DMAU",
4895 SPR_NOACCESS, SPR_NOACCESS,
4896 &spr_read_generic, &spr_write_generic,
4897 0x00000000);
4898 /* Hardware implementation registers */
4899 /* XXX : not implemented */
4900 spr_register(env, SPR_HID0, "HID0",
4901 SPR_NOACCESS, SPR_NOACCESS,
4902 &spr_read_generic, &spr_write_generic,
4903 0x00000000);
4904 /* XXX : not implemented */
4905 spr_register(env, SPR_HID1, "HID1",
4906 SPR_NOACCESS, SPR_NOACCESS,
4907 &spr_read_generic, &spr_write_generic,
4908 0x00000000);
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_750CL_HID2, "HID2",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_750CL_HID4, "HID4",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* Quantization registers */
4920 /* XXX : not implemented */
4921 spr_register(env, SPR_750_GQR0, "GQR0",
4922 SPR_NOACCESS, SPR_NOACCESS,
4923 &spr_read_generic, &spr_write_generic,
4924 0x00000000);
4925 /* XXX : not implemented */
4926 spr_register(env, SPR_750_GQR1, "GQR1",
4927 SPR_NOACCESS, SPR_NOACCESS,
4928 &spr_read_generic, &spr_write_generic,
4929 0x00000000);
4930 /* XXX : not implemented */
4931 spr_register(env, SPR_750_GQR2, "GQR2",
4932 SPR_NOACCESS, SPR_NOACCESS,
4933 &spr_read_generic, &spr_write_generic,
4934 0x00000000);
4935 /* XXX : not implemented */
4936 spr_register(env, SPR_750_GQR3, "GQR3",
4937 SPR_NOACCESS, SPR_NOACCESS,
4938 &spr_read_generic, &spr_write_generic,
4939 0x00000000);
4940 /* XXX : not implemented */
4941 spr_register(env, SPR_750_GQR4, "GQR4",
4942 SPR_NOACCESS, SPR_NOACCESS,
4943 &spr_read_generic, &spr_write_generic,
4944 0x00000000);
4945 /* XXX : not implemented */
4946 spr_register(env, SPR_750_GQR5, "GQR5",
4947 SPR_NOACCESS, SPR_NOACCESS,
4948 &spr_read_generic, &spr_write_generic,
4949 0x00000000);
4950 /* XXX : not implemented */
4951 spr_register(env, SPR_750_GQR6, "GQR6",
4952 SPR_NOACCESS, SPR_NOACCESS,
4953 &spr_read_generic, &spr_write_generic,
4954 0x00000000);
4955 /* XXX : not implemented */
4956 spr_register(env, SPR_750_GQR7, "GQR7",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_generic,
4959 0x00000000);
4960 /* Memory management */
4961 gen_low_BATs(env);
4962 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4963 gen_high_BATs(env);
4964 init_excp_750cl(env);
4965 env->dcache_line_size = 32;
4966 env->icache_line_size = 32;
4967 /* Allocate hardware IRQ controller */
4968 ppc6xx_irq_init(env);
4969}
4970
4e777442 4971/* PowerPC 750CX */
bd928eba
JM		 4972#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4973 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4974 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4975 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4976 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4977 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4978 PPC_SEGMENT | PPC_EXTERN)
4979#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4980#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4981#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4982#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4983#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4984#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4985 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4986#define check_pow_750cx check_pow_hid0
4987
4988static void init_proc_750cx (CPUPPCState *env)
4989{
4990 gen_spr_ne_601(env);
4991 gen_spr_7xx(env);
4992 /* XXX : not implemented */
4993 spr_register(env, SPR_L2CR, "L2CR",
4994 SPR_NOACCESS, SPR_NOACCESS,
4995 &spr_read_generic, &spr_write_generic,
4996 0x00000000);
4997 /* Time base */
4998 gen_tbl(env);
4999 /* Thermal management */
5000 gen_spr_thrm(env);
5001 /* This register is not implemented but is present for compatibility */
5002 spr_register(env, SPR_SDA, "SDA",
5003 SPR_NOACCESS, SPR_NOACCESS,
5004 &spr_read_generic, &spr_write_generic,
5005 0x00000000);
5006 /* Hardware implementation registers */
5007 /* XXX : not implemented */
5008 spr_register(env, SPR_HID0, "HID0",
5009 SPR_NOACCESS, SPR_NOACCESS,
5010 &spr_read_generic, &spr_write_generic,
5011 0x00000000);
5012 /* XXX : not implemented */
5013 spr_register(env, SPR_HID1, "HID1",
5014 SPR_NOACCESS, SPR_NOACCESS,
5015 &spr_read_generic, &spr_write_generic,
5016 0x00000000);
5017 /* Memory management */
5018 gen_low_BATs(env);
4e777442
JM		 5019 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5020 gen_high_BATs(env);
bd928eba
JM		 5021 init_excp_750cx(env);
5022 env->dcache_line_size = 32;
5023 env->icache_line_size = 32;
5024 /* Allocate hardware IRQ controller */
5025 ppc6xx_irq_init(env);
5026}
5027
5028/* PowerPC 750FX */
082c6681
JM		 5029#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5030 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 5031 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5032 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5033 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5034 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5035 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 5036#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 5037#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5038#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5039#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 5040#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 5041#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5042 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 5043#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 5044
5045static void init_proc_750fx (CPUPPCState *env)
5046{
5047 gen_spr_ne_601(env);
5048 gen_spr_7xx(env);
bd928eba
JM		 5049 /* XXX : not implemented */
5050 spr_register(env, SPR_L2CR, "L2CR",
5051 SPR_NOACCESS, SPR_NOACCESS,
5052 &spr_read_generic, &spr_write_generic,
5053 0x00000000);
a750fc0b
JM		 5054 /* Time base */
5055 gen_tbl(env);
5056 /* Thermal management */
5057 gen_spr_thrm(env);
bd928eba
JM		 5058 /* XXX : not implemented */
5059 spr_register(env, SPR_750_THRM4, "THRM4",
5060 SPR_NOACCESS, SPR_NOACCESS,
5061 &spr_read_generic, &spr_write_generic,
5062 0x00000000);
a750fc0b
JM		 5063 /* Hardware implementation registers */
5064 /* XXX : not implemented */
5065 spr_register(env, SPR_HID0, "HID0",
5066 SPR_NOACCESS, SPR_NOACCESS,
5067 &spr_read_generic, &spr_write_generic,
5068 0x00000000);
5069 /* XXX : not implemented */
5070 spr_register(env, SPR_HID1, "HID1",
5071 SPR_NOACCESS, SPR_NOACCESS,
5072 &spr_read_generic, &spr_write_generic,
5073 0x00000000);
5074 /* XXX : not implemented */
bd928eba 5075 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5076 SPR_NOACCESS, SPR_NOACCESS,
5077 &spr_read_generic, &spr_write_generic,
5078 0x00000000);
5079 /* Memory management */
5080 gen_low_BATs(env);
5081 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5082 gen_high_BATs(env);
bd928eba 5083 init_excp_7x0(env);
d63001d1
JM		 5084 env->dcache_line_size = 32;
5085 env->icache_line_size = 32;
a750fc0b
JM		 5086 /* Allocate hardware IRQ controller */
5087 ppc6xx_irq_init(env);
5088}
5089
bd928eba
JM		 5090/* PowerPC 750GX */
5091#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5092 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5093 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5094 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5095 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5096 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5097 PPC_SEGMENT | PPC_EXTERN)
5098#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5099#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5100#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5101#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5102#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5103#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5104 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5105#define check_pow_750gx check_pow_hid0
5106
5107static void init_proc_750gx (CPUPPCState *env)
5108{
5109 gen_spr_ne_601(env);
5110 gen_spr_7xx(env);
5111 /* XXX : not implemented (XXX: different from 750fx) */
5112 spr_register(env, SPR_L2CR, "L2CR",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
5115 0x00000000);
5116 /* Time base */
5117 gen_tbl(env);
5118 /* Thermal management */
5119 gen_spr_thrm(env);
5120 /* XXX : not implemented */
5121 spr_register(env, SPR_750_THRM4, "THRM4",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 0x00000000);
5125 /* Hardware implementation registers */
5126 /* XXX : not implemented (XXX: different from 750fx) */
5127 spr_register(env, SPR_HID0, "HID0",
5128 SPR_NOACCESS, SPR_NOACCESS,
5129 &spr_read_generic, &spr_write_generic,
5130 0x00000000);
5131 /* XXX : not implemented */
5132 spr_register(env, SPR_HID1, "HID1",
5133 SPR_NOACCESS, SPR_NOACCESS,
5134 &spr_read_generic, &spr_write_generic,
5135 0x00000000);
5136 /* XXX : not implemented (XXX: different from 750fx) */
5137 spr_register(env, SPR_750FX_HID2, "HID2",
5138 SPR_NOACCESS, SPR_NOACCESS,
5139 &spr_read_generic, &spr_write_generic,
5140 0x00000000);
5141 /* Memory management */
5142 gen_low_BATs(env);
5143 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5144 gen_high_BATs(env);
5145 init_excp_7x0(env);
5146 env->dcache_line_size = 32;
5147 env->icache_line_size = 32;
5148 /* Allocate hardware IRQ controller */
5149 ppc6xx_irq_init(env);
5150}
5151
5152/* PowerPC 745 */
5153#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5154 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5155 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5156 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5157 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5158 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5159 PPC_SEGMENT | PPC_EXTERN)
5160#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5161#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5162#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5163#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5164#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5165#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5166 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5167#define check_pow_745 check_pow_hid0
5168
5169static void init_proc_745 (CPUPPCState *env)
5170{
5171 gen_spr_ne_601(env);
5172 gen_spr_7xx(env);
5173 gen_spr_G2_755(env);
5174 /* Time base */
5175 gen_tbl(env);
5176 /* Thermal management */
5177 gen_spr_thrm(env);
5178 /* Hardware implementation registers */
5179 /* XXX : not implemented */
5180 spr_register(env, SPR_HID0, "HID0",
5181 SPR_NOACCESS, SPR_NOACCESS,
5182 &spr_read_generic, &spr_write_generic,
5183 0x00000000);
5184 /* XXX : not implemented */
5185 spr_register(env, SPR_HID1, "HID1",
5186 SPR_NOACCESS, SPR_NOACCESS,
5187 &spr_read_generic, &spr_write_generic,
5188 0x00000000);
5189 /* XXX : not implemented */
5190 spr_register(env, SPR_HID2, "HID2",
5191 SPR_NOACCESS, SPR_NOACCESS,
5192 &spr_read_generic, &spr_write_generic,
5193 0x00000000);
5194 /* Memory management */
5195 gen_low_BATs(env);
5196 gen_high_BATs(env);
5197 gen_6xx_7xx_soft_tlb(env, 64, 2);
5198 init_excp_7x5(env);
5199 env->dcache_line_size = 32;
5200 env->icache_line_size = 32;
5201 /* Allocate hardware IRQ controller */
5202 ppc6xx_irq_init(env);
5203}
5204
5205/* PowerPC 755 */
5206#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5207 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5208 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5209 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5210 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5211 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5212 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 5213#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5214#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5215#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5216#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5217#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5218#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5219 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5220#define check_pow_755 check_pow_hid0
a750fc0b 5221
bd928eba 5222static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5223{
5224 gen_spr_ne_601(env);
bd928eba 5225 gen_spr_7xx(env);
a750fc0b
JM		 5226 gen_spr_G2_755(env);
5227 /* Time base */
5228 gen_tbl(env);
5229 /* L2 cache control */
5230 /* XXX : not implemented */
bd928eba 5231 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5232 SPR_NOACCESS, SPR_NOACCESS,
5233 &spr_read_generic, &spr_write_generic,
5234 0x00000000);
5235 /* XXX : not implemented */
5236 spr_register(env, SPR_L2PMCR, "L2PMCR",
5237 SPR_NOACCESS, SPR_NOACCESS,
5238 &spr_read_generic, &spr_write_generic,
5239 0x00000000);
bd928eba
JM		 5240 /* Thermal management */
5241 gen_spr_thrm(env);
a750fc0b
JM		 5242 /* Hardware implementation registers */
5243 /* XXX : not implemented */
5244 spr_register(env, SPR_HID0, "HID0",
5245 SPR_NOACCESS, SPR_NOACCESS,
5246 &spr_read_generic, &spr_write_generic,
5247 0x00000000);
5248 /* XXX : not implemented */
5249 spr_register(env, SPR_HID1, "HID1",
5250 SPR_NOACCESS, SPR_NOACCESS,
5251 &spr_read_generic, &spr_write_generic,
5252 0x00000000);
5253 /* XXX : not implemented */
5254 spr_register(env, SPR_HID2, "HID2",
5255 SPR_NOACCESS, SPR_NOACCESS,
5256 &spr_read_generic, &spr_write_generic,
5257 0x00000000);
5258 /* Memory management */
5259 gen_low_BATs(env);
5260 gen_high_BATs(env);
5261 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5262 init_excp_7x5(env);
d63001d1
JM		 5263 env->dcache_line_size = 32;
5264 env->icache_line_size = 32;
a750fc0b
JM		 5265 /* Allocate hardware IRQ controller */
5266 ppc6xx_irq_init(env);
5267}
5268
5269/* PowerPC 7400 (aka G4) */
082c6681
JM		 5270#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5271 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5272 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5273 PPC_FLOAT_STFIWX | \
5274 PPC_CACHE | PPC_CACHE_ICBI | \
5275 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5276 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5277 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5278 PPC_MEM_TLBIA | \
5279 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5280 PPC_ALTIVEC)
5281#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5282#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5283#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5284#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5285#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5286#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5287 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5288 POWERPC_FLAG_BUS_CLK)
488243b0 5289#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 5290
5291static void init_proc_7400 (CPUPPCState *env)
5292{
5293 gen_spr_ne_601(env);
5294 gen_spr_7xx(env);
5295 /* Time base */
5296 gen_tbl(env);
5297 /* 74xx specific SPR */
5298 gen_spr_74xx(env);
4e777442
JM		 5299 /* XXX : not implemented */
5300 spr_register(env, SPR_UBAMR, "UBAMR",
5301 &spr_read_ureg, SPR_NOACCESS,
5302 &spr_read_ureg, SPR_NOACCESS,
5303 0x00000000);
5304 /* XXX: this seems not implemented on all revisions. */
5305 /* XXX : not implemented */
5306 spr_register(env, SPR_MSSCR1, "MSSCR1",
5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 0x00000000);
a750fc0b
JM		 5310 /* Thermal management */
5311 gen_spr_thrm(env);
5312 /* Memory management */
5313 gen_low_BATs(env);
e1833e1f 5314 init_excp_7400(env);
d63001d1
JM		 5315 env->dcache_line_size = 32;
5316 env->icache_line_size = 32;
a750fc0b
JM		 5317 /* Allocate hardware IRQ controller */
5318 ppc6xx_irq_init(env);
5319}
5320
5321/* PowerPC 7410 (aka G4) */
082c6681
JM		 5322#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5323 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5324 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5325 PPC_FLOAT_STFIWX | \
5326 PPC_CACHE | PPC_CACHE_ICBI | \
5327 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5328 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5329 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5330 PPC_MEM_TLBIA | \
5331 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5332 PPC_ALTIVEC)
5333#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5334#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5335#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5336#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5337#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5338#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5339 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5340 POWERPC_FLAG_BUS_CLK)
488243b0 5341#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 5342
5343static void init_proc_7410 (CPUPPCState *env)
5344{
5345 gen_spr_ne_601(env);
5346 gen_spr_7xx(env);
5347 /* Time base */
5348 gen_tbl(env);
5349 /* 74xx specific SPR */
5350 gen_spr_74xx(env);
4e777442
JM		 5351 /* XXX : not implemented */
5352 spr_register(env, SPR_UBAMR, "UBAMR",
5353 &spr_read_ureg, SPR_NOACCESS,
5354 &spr_read_ureg, SPR_NOACCESS,
5355 0x00000000);
a750fc0b
JM		 5356 /* Thermal management */
5357 gen_spr_thrm(env);
5358 /* L2PMCR */
5359 /* XXX : not implemented */
5360 spr_register(env, SPR_L2PMCR, "L2PMCR",
5361 SPR_NOACCESS, SPR_NOACCESS,
5362 &spr_read_generic, &spr_write_generic,
5363 0x00000000);
5364 /* LDSTDB */
5365 /* XXX : not implemented */
5366 spr_register(env, SPR_LDSTDB, "LDSTDB",
5367 SPR_NOACCESS, SPR_NOACCESS,
5368 &spr_read_generic, &spr_write_generic,
5369 0x00000000);
5370 /* Memory management */
5371 gen_low_BATs(env);
e1833e1f 5372 init_excp_7400(env);
d63001d1
JM		 5373 env->dcache_line_size = 32;
5374 env->icache_line_size = 32;
a750fc0b
JM		 5375 /* Allocate hardware IRQ controller */
5376 ppc6xx_irq_init(env);
5377}
5378
5379/* PowerPC 7440 (aka G4) */
082c6681
JM		 5380#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5382 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5383 PPC_FLOAT_STFIWX | \
5384 PPC_CACHE | PPC_CACHE_ICBI | \
5385 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5386 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5387 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5388 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5389 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5390 PPC_ALTIVEC)
5391#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5392#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5393#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5394#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5395#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5396#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5397 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5398 POWERPC_FLAG_BUS_CLK)
4e777442 5399#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5400
578bb252 5401__attribute__ (( unused ))
a750fc0b
JM		 5402static void init_proc_7440 (CPUPPCState *env)
5403{
5404 gen_spr_ne_601(env);
5405 gen_spr_7xx(env);
5406 /* Time base */
5407 gen_tbl(env);
5408 /* 74xx specific SPR */
5409 gen_spr_74xx(env);
4e777442
JM		 5410 /* XXX : not implemented */
5411 spr_register(env, SPR_UBAMR, "UBAMR",
5412 &spr_read_ureg, SPR_NOACCESS,
5413 &spr_read_ureg, SPR_NOACCESS,
5414 0x00000000);
a750fc0b
JM		 5415 /* LDSTCR */
5416 /* XXX : not implemented */
5417 spr_register(env, SPR_LDSTCR, "LDSTCR",
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 &spr_read_generic, &spr_write_generic,
5420 0x00000000);
5421 /* ICTRL */
5422 /* XXX : not implemented */
5423 spr_register(env, SPR_ICTRL, "ICTRL",
5424 SPR_NOACCESS, SPR_NOACCESS,
5425 &spr_read_generic, &spr_write_generic,
5426 0x00000000);
5427 /* MSSSR0 */
578bb252 5428 /* XXX : not implemented */
a750fc0b
JM		 5429 spr_register(env, SPR_MSSSR0, "MSSSR0",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, &spr_write_generic,
5432 0x00000000);
5433 /* PMC */
5434 /* XXX : not implemented */
5435 spr_register(env, SPR_PMC5, "PMC5",
5436 SPR_NOACCESS, SPR_NOACCESS,
5437 &spr_read_generic, &spr_write_generic,
5438 0x00000000);
578bb252 5439 /* XXX : not implemented */
a750fc0b
JM		 5440 spr_register(env, SPR_UPMC5, "UPMC5",
5441 &spr_read_ureg, SPR_NOACCESS,
5442 &spr_read_ureg, SPR_NOACCESS,
5443 0x00000000);
578bb252 5444 /* XXX : not implemented */
a750fc0b
JM		 5445 spr_register(env, SPR_PMC6, "PMC6",
5446 SPR_NOACCESS, SPR_NOACCESS,
5447 &spr_read_generic, &spr_write_generic,
5448 0x00000000);
578bb252 5449 /* XXX : not implemented */
a750fc0b
JM		 5450 spr_register(env, SPR_UPMC6, "UPMC6",
5451 &spr_read_ureg, SPR_NOACCESS,
5452 &spr_read_ureg, SPR_NOACCESS,
5453 0x00000000);
5454 /* Memory management */
5455 gen_low_BATs(env);
578bb252 5456 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5457 init_excp_7450(env);
d63001d1
JM		 5458 env->dcache_line_size = 32;
5459 env->icache_line_size = 32;
a750fc0b
JM		 5460 /* Allocate hardware IRQ controller */
5461 ppc6xx_irq_init(env);
5462}
a750fc0b
JM		 5463
5464/* PowerPC 7450 (aka G4) */
082c6681
JM		 5465#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5466 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5467 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5468 PPC_FLOAT_STFIWX | \
5469 PPC_CACHE | PPC_CACHE_ICBI | \
5470 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5471 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5472 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5473 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5474 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5475 PPC_ALTIVEC)
5476#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5477#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5478#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5479#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5480#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5481#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5482 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5483 POWERPC_FLAG_BUS_CLK)
4e777442 5484#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5485
578bb252 5486__attribute__ (( unused ))
a750fc0b
JM		 5487static void init_proc_7450 (CPUPPCState *env)
5488{
5489 gen_spr_ne_601(env);
5490 gen_spr_7xx(env);
5491 /* Time base */
5492 gen_tbl(env);
5493 /* 74xx specific SPR */
5494 gen_spr_74xx(env);
5495 /* Level 3 cache control */
5496 gen_l3_ctrl(env);
4e777442
JM		 5497 /* L3ITCR1 */
5498 /* XXX : not implemented */
5499 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5500 SPR_NOACCESS, SPR_NOACCESS,
5501 &spr_read_generic, &spr_write_generic,
5502 0x00000000);
5503 /* L3ITCR2 */
5504 /* XXX : not implemented */
5505 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5506 SPR_NOACCESS, SPR_NOACCESS,
5507 &spr_read_generic, &spr_write_generic,
5508 0x00000000);
5509 /* L3ITCR3 */
5510 /* XXX : not implemented */
5511 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5512 SPR_NOACCESS, SPR_NOACCESS,
5513 &spr_read_generic, &spr_write_generic,
5514 0x00000000);
5515 /* L3OHCR */
5516 /* XXX : not implemented */
5517 spr_register(env, SPR_L3OHCR, "L3OHCR",
5518 SPR_NOACCESS, SPR_NOACCESS,
5519 &spr_read_generic, &spr_write_generic,
5520 0x00000000);
5521 /* XXX : not implemented */
5522 spr_register(env, SPR_UBAMR, "UBAMR",
5523 &spr_read_ureg, SPR_NOACCESS,
5524 &spr_read_ureg, SPR_NOACCESS,
5525 0x00000000);
a750fc0b
JM		 5526 /* LDSTCR */
5527 /* XXX : not implemented */
5528 spr_register(env, SPR_LDSTCR, "LDSTCR",
5529 SPR_NOACCESS, SPR_NOACCESS,
5530 &spr_read_generic, &spr_write_generic,
5531 0x00000000);
5532 /* ICTRL */
5533 /* XXX : not implemented */
5534 spr_register(env, SPR_ICTRL, "ICTRL",
5535 SPR_NOACCESS, SPR_NOACCESS,
5536 &spr_read_generic, &spr_write_generic,
5537 0x00000000);
5538 /* MSSSR0 */
578bb252 5539 /* XXX : not implemented */
a750fc0b
JM		 5540 spr_register(env, SPR_MSSSR0, "MSSSR0",
5541 SPR_NOACCESS, SPR_NOACCESS,
5542 &spr_read_generic, &spr_write_generic,
5543 0x00000000);
5544 /* PMC */
5545 /* XXX : not implemented */
5546 spr_register(env, SPR_PMC5, "PMC5",
5547 SPR_NOACCESS, SPR_NOACCESS,
5548 &spr_read_generic, &spr_write_generic,
5549 0x00000000);
578bb252 5550 /* XXX : not implemented */
a750fc0b
JM		 5551 spr_register(env, SPR_UPMC5, "UPMC5",
5552 &spr_read_ureg, SPR_NOACCESS,
5553 &spr_read_ureg, SPR_NOACCESS,
5554 0x00000000);
578bb252 5555 /* XXX : not implemented */
a750fc0b
JM		 5556 spr_register(env, SPR_PMC6, "PMC6",
5557 SPR_NOACCESS, SPR_NOACCESS,
5558 &spr_read_generic, &spr_write_generic,
5559 0x00000000);
578bb252 5560 /* XXX : not implemented */
a750fc0b
JM		 5561 spr_register(env, SPR_UPMC6, "UPMC6",
5562 &spr_read_ureg, SPR_NOACCESS,
5563 &spr_read_ureg, SPR_NOACCESS,
5564 0x00000000);
5565 /* Memory management */
5566 gen_low_BATs(env);
578bb252 5567 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5568 init_excp_7450(env);
d63001d1
JM		 5569 env->dcache_line_size = 32;
5570 env->icache_line_size = 32;
a750fc0b
JM		 5571 /* Allocate hardware IRQ controller */
5572 ppc6xx_irq_init(env);
5573}
a750fc0b
JM		 5574
5575/* PowerPC 7445 (aka G4) */
082c6681
JM		 5576#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5577 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5578 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5579 PPC_FLOAT_STFIWX | \
5580 PPC_CACHE | PPC_CACHE_ICBI | \
5581 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5582 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5584 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5585 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5586 PPC_ALTIVEC)
5587#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5588#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5589#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5590#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5591#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5592#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5593 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5594 POWERPC_FLAG_BUS_CLK)
4e777442 5595#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5596
578bb252 5597__attribute__ (( unused ))
a750fc0b
JM		 5598static void init_proc_7445 (CPUPPCState *env)
5599{
5600 gen_spr_ne_601(env);
5601 gen_spr_7xx(env);
5602 /* Time base */
5603 gen_tbl(env);
5604 /* 74xx specific SPR */
5605 gen_spr_74xx(env);
5606 /* LDSTCR */
5607 /* XXX : not implemented */
5608 spr_register(env, SPR_LDSTCR, "LDSTCR",
5609 SPR_NOACCESS, SPR_NOACCESS,
5610 &spr_read_generic, &spr_write_generic,
5611 0x00000000);
5612 /* ICTRL */
5613 /* XXX : not implemented */
5614 spr_register(env, SPR_ICTRL, "ICTRL",
5615 SPR_NOACCESS, SPR_NOACCESS,
5616 &spr_read_generic, &spr_write_generic,
5617 0x00000000);
5618 /* MSSSR0 */
578bb252 5619 /* XXX : not implemented */
a750fc0b
JM		 5620 spr_register(env, SPR_MSSSR0, "MSSSR0",
5621 SPR_NOACCESS, SPR_NOACCESS,
5622 &spr_read_generic, &spr_write_generic,
5623 0x00000000);
5624 /* PMC */
5625 /* XXX : not implemented */
5626 spr_register(env, SPR_PMC5, "PMC5",
5627 SPR_NOACCESS, SPR_NOACCESS,
5628 &spr_read_generic, &spr_write_generic,
5629 0x00000000);
578bb252 5630 /* XXX : not implemented */
a750fc0b
JM		 5631 spr_register(env, SPR_UPMC5, "UPMC5",
5632 &spr_read_ureg, SPR_NOACCESS,
5633 &spr_read_ureg, SPR_NOACCESS,
5634 0x00000000);
578bb252 5635 /* XXX : not implemented */
a750fc0b
JM		 5636 spr_register(env, SPR_PMC6, "PMC6",
5637 SPR_NOACCESS, SPR_NOACCESS,
5638 &spr_read_generic, &spr_write_generic,
5639 0x00000000);
578bb252 5640 /* XXX : not implemented */
a750fc0b
JM		 5641 spr_register(env, SPR_UPMC6, "UPMC6",
5642 &spr_read_ureg, SPR_NOACCESS,
5643 &spr_read_ureg, SPR_NOACCESS,
5644 0x00000000);
5645 /* SPRGs */
5646 spr_register(env, SPR_SPRG4, "SPRG4",
5647 SPR_NOACCESS, SPR_NOACCESS,
5648 &spr_read_generic, &spr_write_generic,
5649 0x00000000);
5650 spr_register(env, SPR_USPRG4, "USPRG4",
5651 &spr_read_ureg, SPR_NOACCESS,
5652 &spr_read_ureg, SPR_NOACCESS,
5653 0x00000000);
5654 spr_register(env, SPR_SPRG5, "SPRG5",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_generic,
5657 0x00000000);
5658 spr_register(env, SPR_USPRG5, "USPRG5",
5659 &spr_read_ureg, SPR_NOACCESS,
5660 &spr_read_ureg, SPR_NOACCESS,
5661 0x00000000);
5662 spr_register(env, SPR_SPRG6, "SPRG6",
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_generic, &spr_write_generic,
5665 0x00000000);
5666 spr_register(env, SPR_USPRG6, "USPRG6",
5667 &spr_read_ureg, SPR_NOACCESS,
5668 &spr_read_ureg, SPR_NOACCESS,
5669 0x00000000);
5670 spr_register(env, SPR_SPRG7, "SPRG7",
5671 SPR_NOACCESS, SPR_NOACCESS,
5672 &spr_read_generic, &spr_write_generic,
5673 0x00000000);
5674 spr_register(env, SPR_USPRG7, "USPRG7",
5675 &spr_read_ureg, SPR_NOACCESS,
5676 &spr_read_ureg, SPR_NOACCESS,
5677 0x00000000);
5678 /* Memory management */
5679 gen_low_BATs(env);
5680 gen_high_BATs(env);
578bb252 5681 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5682 init_excp_7450(env);
d63001d1
JM		 5683 env->dcache_line_size = 32;
5684 env->icache_line_size = 32;
a750fc0b
JM		 5685 /* Allocate hardware IRQ controller */
5686 ppc6xx_irq_init(env);
5687}
a750fc0b
JM		 5688
5689/* PowerPC 7455 (aka G4) */
082c6681
JM		 5690#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5691 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5692 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5693 PPC_FLOAT_STFIWX | \
5694 PPC_CACHE | PPC_CACHE_ICBI | \
5695 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5696 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5697 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5698 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5699 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5700 PPC_ALTIVEC)
5701#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5702#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5703#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5704#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5705#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5706#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5707 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5708 POWERPC_FLAG_BUS_CLK)
4e777442 5709#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5710
578bb252 5711__attribute__ (( unused ))
a750fc0b
JM		 5712static void init_proc_7455 (CPUPPCState *env)
5713{
5714 gen_spr_ne_601(env);
5715 gen_spr_7xx(env);
5716 /* Time base */
5717 gen_tbl(env);
5718 /* 74xx specific SPR */
5719 gen_spr_74xx(env);
5720 /* Level 3 cache control */
5721 gen_l3_ctrl(env);
5722 /* LDSTCR */
5723 /* XXX : not implemented */
5724 spr_register(env, SPR_LDSTCR, "LDSTCR",
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 &spr_read_generic, &spr_write_generic,
5727 0x00000000);
5728 /* ICTRL */
5729 /* XXX : not implemented */
5730 spr_register(env, SPR_ICTRL, "ICTRL",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0x00000000);
5734 /* MSSSR0 */
578bb252 5735 /* XXX : not implemented */
a750fc0b
JM		 5736 spr_register(env, SPR_MSSSR0, "MSSSR0",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 0x00000000);
5740 /* PMC */
5741 /* XXX : not implemented */
5742 spr_register(env, SPR_PMC5, "PMC5",
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, &spr_write_generic,
5745 0x00000000);
578bb252 5746 /* XXX : not implemented */
a750fc0b
JM		 5747 spr_register(env, SPR_UPMC5, "UPMC5",
5748 &spr_read_ureg, SPR_NOACCESS,
5749 &spr_read_ureg, SPR_NOACCESS,
5750 0x00000000);
578bb252 5751 /* XXX : not implemented */
a750fc0b
JM		 5752 spr_register(env, SPR_PMC6, "PMC6",
5753 SPR_NOACCESS, SPR_NOACCESS,
5754 &spr_read_generic, &spr_write_generic,
5755 0x00000000);
578bb252 5756 /* XXX : not implemented */
a750fc0b
JM		 5757 spr_register(env, SPR_UPMC6, "UPMC6",
5758 &spr_read_ureg, SPR_NOACCESS,
5759 &spr_read_ureg, SPR_NOACCESS,
5760 0x00000000);
5761 /* SPRGs */
5762 spr_register(env, SPR_SPRG4, "SPRG4",
5763 SPR_NOACCESS, SPR_NOACCESS,
5764 &spr_read_generic, &spr_write_generic,
5765 0x00000000);
5766 spr_register(env, SPR_USPRG4, "USPRG4",
5767 &spr_read_ureg, SPR_NOACCESS,
5768 &spr_read_ureg, SPR_NOACCESS,
5769 0x00000000);
5770 spr_register(env, SPR_SPRG5, "SPRG5",
5771 SPR_NOACCESS, SPR_NOACCESS,
5772 &spr_read_generic, &spr_write_generic,
5773 0x00000000);
5774 spr_register(env, SPR_USPRG5, "USPRG5",
5775 &spr_read_ureg, SPR_NOACCESS,
5776 &spr_read_ureg, SPR_NOACCESS,
5777 0x00000000);
5778 spr_register(env, SPR_SPRG6, "SPRG6",
5779 SPR_NOACCESS, SPR_NOACCESS,
5780 &spr_read_generic, &spr_write_generic,
5781 0x00000000);
5782 spr_register(env, SPR_USPRG6, "USPRG6",
5783 &spr_read_ureg, SPR_NOACCESS,
5784 &spr_read_ureg, SPR_NOACCESS,
5785 0x00000000);
5786 spr_register(env, SPR_SPRG7, "SPRG7",
5787 SPR_NOACCESS, SPR_NOACCESS,
5788 &spr_read_generic, &spr_write_generic,
5789 0x00000000);
5790 spr_register(env, SPR_USPRG7, "USPRG7",
5791 &spr_read_ureg, SPR_NOACCESS,
5792 &spr_read_ureg, SPR_NOACCESS,
5793 0x00000000);
5794 /* Memory management */
5795 gen_low_BATs(env);
5796 gen_high_BATs(env);
578bb252 5797 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5798 init_excp_7450(env);
d63001d1
JM		 5799 env->dcache_line_size = 32;
5800 env->icache_line_size = 32;
a750fc0b
JM		 5801 /* Allocate hardware IRQ controller */
5802 ppc6xx_irq_init(env);
5803}
a750fc0b 5804
4e777442
JM		 5805/* PowerPC 7457 (aka G4) */
5806#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5807 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5808 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5809 PPC_FLOAT_STFIWX | \
5810 PPC_CACHE | PPC_CACHE_ICBI | \
5811 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5812 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5813 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5814 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5815 PPC_SEGMENT | PPC_EXTERN | \
5816 PPC_ALTIVEC)
5817#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5818#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5819#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5820#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5821#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5822#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5823 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5824 POWERPC_FLAG_BUS_CLK)
5825#define check_pow_7457 check_pow_hid0_74xx
5826
5827__attribute__ (( unused ))
5828static void init_proc_7457 (CPUPPCState *env)
5829{
5830 gen_spr_ne_601(env);
5831 gen_spr_7xx(env);
5832 /* Time base */
5833 gen_tbl(env);
5834 /* 74xx specific SPR */
5835 gen_spr_74xx(env);
5836 /* Level 3 cache control */
5837 gen_l3_ctrl(env);
5838 /* L3ITCR1 */
5839 /* XXX : not implemented */
5840 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5841 SPR_NOACCESS, SPR_NOACCESS,
5842 &spr_read_generic, &spr_write_generic,
5843 0x00000000);
5844 /* L3ITCR2 */
5845 /* XXX : not implemented */
5846 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
5850 /* L3ITCR3 */
5851 /* XXX : not implemented */
5852 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 /* L3OHCR */
5857 /* XXX : not implemented */
5858 spr_register(env, SPR_L3OHCR, "L3OHCR",
5859 SPR_NOACCESS, SPR_NOACCESS,
5860 &spr_read_generic, &spr_write_generic,
5861 0x00000000);
5862 /* LDSTCR */
5863 /* XXX : not implemented */
5864 spr_register(env, SPR_LDSTCR, "LDSTCR",
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 &spr_read_generic, &spr_write_generic,
5867 0x00000000);
5868 /* ICTRL */
5869 /* XXX : not implemented */
5870 spr_register(env, SPR_ICTRL, "ICTRL",
5871 SPR_NOACCESS, SPR_NOACCESS,
5872 &spr_read_generic, &spr_write_generic,
5873 0x00000000);
5874 /* MSSSR0 */
5875 /* XXX : not implemented */
5876 spr_register(env, SPR_MSSSR0, "MSSSR0",
5877 SPR_NOACCESS, SPR_NOACCESS,
5878 &spr_read_generic, &spr_write_generic,
5879 0x00000000);
5880 /* PMC */
5881 /* XXX : not implemented */
5882 spr_register(env, SPR_PMC5, "PMC5",
5883 SPR_NOACCESS, SPR_NOACCESS,
5884 &spr_read_generic, &spr_write_generic,
5885 0x00000000);
5886 /* XXX : not implemented */
5887 spr_register(env, SPR_UPMC5, "UPMC5",
5888 &spr_read_ureg, SPR_NOACCESS,
5889 &spr_read_ureg, SPR_NOACCESS,
5890 0x00000000);
5891 /* XXX : not implemented */
5892 spr_register(env, SPR_PMC6, "PMC6",
5893 SPR_NOACCESS, SPR_NOACCESS,
5894 &spr_read_generic, &spr_write_generic,
5895 0x00000000);
5896 /* XXX : not implemented */
5897 spr_register(env, SPR_UPMC6, "UPMC6",
5898 &spr_read_ureg, SPR_NOACCESS,
5899 &spr_read_ureg, SPR_NOACCESS,
5900 0x00000000);
5901 /* SPRGs */
5902 spr_register(env, SPR_SPRG4, "SPRG4",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
5906 spr_register(env, SPR_USPRG4, "USPRG4",
5907 &spr_read_ureg, SPR_NOACCESS,
5908 &spr_read_ureg, SPR_NOACCESS,
5909 0x00000000);
5910 spr_register(env, SPR_SPRG5, "SPRG5",
5911 SPR_NOACCESS, SPR_NOACCESS,
5912 &spr_read_generic, &spr_write_generic,
5913 0x00000000);
5914 spr_register(env, SPR_USPRG5, "USPRG5",
5915 &spr_read_ureg, SPR_NOACCESS,
5916 &spr_read_ureg, SPR_NOACCESS,
5917 0x00000000);
5918 spr_register(env, SPR_SPRG6, "SPRG6",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
5921 0x00000000);
5922 spr_register(env, SPR_USPRG6, "USPRG6",
5923 &spr_read_ureg, SPR_NOACCESS,
5924 &spr_read_ureg, SPR_NOACCESS,
5925 0x00000000);
5926 spr_register(env, SPR_SPRG7, "SPRG7",
5927 SPR_NOACCESS, SPR_NOACCESS,
5928 &spr_read_generic, &spr_write_generic,
5929 0x00000000);
5930 spr_register(env, SPR_USPRG7, "USPRG7",
5931 &spr_read_ureg, SPR_NOACCESS,
5932 &spr_read_ureg, SPR_NOACCESS,
5933 0x00000000);
5934 /* Memory management */
5935 gen_low_BATs(env);
5936 gen_high_BATs(env);
5937 gen_74xx_soft_tlb(env, 128, 2);
5938 init_excp_7450(env);
5939 env->dcache_line_size = 32;
5940 env->icache_line_size = 32;
5941 /* Allocate hardware IRQ controller */
5942 ppc6xx_irq_init(env);
5943}
5944
a750fc0b
JM		 5945#if defined (TARGET_PPC64)
5946/* PowerPC 970 */
082c6681
JM		 5947#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5948 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5949 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5950 PPC_FLOAT_STFIWX | \
5951 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5952 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5953 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5954 PPC_64B | PPC_ALTIVEC | \
12de9a39 5955 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5956#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 5957#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 5958//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5959#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 5960#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 5961#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5962 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5963 POWERPC_FLAG_BUS_CLK)
a750fc0b 5964
417bf010
JM		 5965#if defined(CONFIG_USER_ONLY)
5966#define POWERPC970_HID5_INIT 0x00000080
5967#else
5968#define POWERPC970_HID5_INIT 0x00000000
5969#endif
5970
2f462816
JM		 5971static int check_pow_970 (CPUPPCState *env)
5972{
5973 if (env->spr[SPR_HID0] & 0x00600000)
5974 return 1;
5975
5976 return 0;
5977}
5978
a750fc0b
JM		 5979static void init_proc_970 (CPUPPCState *env)
5980{
5981 gen_spr_ne_601(env);
5982 gen_spr_7xx(env);
5983 /* Time base */
5984 gen_tbl(env);
5985 /* Hardware implementation registers */
5986 /* XXX : not implemented */
5987 spr_register(env, SPR_HID0, "HID0",
5988 SPR_NOACCESS, SPR_NOACCESS,
06403421 5989 &spr_read_generic, &spr_write_clear,
d63001d1 5990 0x60000000);
a750fc0b
JM		 5991 /* XXX : not implemented */
5992 spr_register(env, SPR_HID1, "HID1",
5993 SPR_NOACCESS, SPR_NOACCESS,
5994 &spr_read_generic, &spr_write_generic,
5995 0x00000000);
5996 /* XXX : not implemented */
bd928eba 5997 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5998 SPR_NOACCESS, SPR_NOACCESS,
5999 &spr_read_generic, &spr_write_generic,
6000 0x00000000);
e57448f1
JM		 6001 /* XXX : not implemented */
6002 spr_register(env, SPR_970_HID5, "HID5",
6003 SPR_NOACCESS, SPR_NOACCESS,
6004 &spr_read_generic, &spr_write_generic,
417bf010 6005 POWERPC970_HID5_INIT);
bd928eba
JM		 6006 /* XXX : not implemented */
6007 spr_register(env, SPR_L2CR, "L2CR",
6008 SPR_NOACCESS, SPR_NOACCESS,
6009 &spr_read_generic, &spr_write_generic,
6010 0x00000000);
a750fc0b
JM		 6011 /* Memory management */
6012 /* XXX: not correct */
6013 gen_low_BATs(env);
12de9a39
JM		 6014 /* XXX : not implemented */
6015 spr_register(env, SPR_MMUCFG, "MMUCFG",
6016 SPR_NOACCESS, SPR_NOACCESS,
6017 &spr_read_generic, SPR_NOACCESS,
6018 0x00000000); /* TOFIX */
6019 /* XXX : not implemented */
6020 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, &spr_write_generic,
6023 0x00000000); /* TOFIX */
6024 spr_register(env, SPR_HIOR, "SPR_HIOR",
6025 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6026 &spr_read_hior, &spr_write_hior,
6027 0x00000000);
f2e63a42 6028#if !defined(CONFIG_USER_ONLY)
12de9a39 6029 env->slb_nr = 32;
f2e63a42 6030#endif
e1833e1f 6031 init_excp_970(env);
d63001d1
JM		 6032 env->dcache_line_size = 128;
6033 env->icache_line_size = 128;
a750fc0b
JM		 6034 /* Allocate hardware IRQ controller */
6035 ppc970_irq_init(env);
cf8358c8
AJ		 6036 /* Can't find information on what this should be on reset. This
6037 * value is the one used by 74xx processors. */
6038 vscr_init(env, 0x00010000);
a750fc0b 6039}
a750fc0b
JM		 6040
6041/* PowerPC 970FX (aka G5) */
082c6681
JM		 6042#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6043 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6044 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6045 PPC_FLOAT_STFIWX | \
6046 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6047 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6048 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6049 PPC_64B | PPC_ALTIVEC | \
12de9a39 6050 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6051#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6052#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6053#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6054#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6055#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6056#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6057 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6058 POWERPC_FLAG_BUS_CLK)
a750fc0b 6059
2f462816
JM		 6060static int check_pow_970FX (CPUPPCState *env)
6061{
6062 if (env->spr[SPR_HID0] & 0x00600000)
6063 return 1;
6064
6065 return 0;
6066}
6067
a750fc0b
JM		 6068static void init_proc_970FX (CPUPPCState *env)
6069{
6070 gen_spr_ne_601(env);
6071 gen_spr_7xx(env);
6072 /* Time base */
6073 gen_tbl(env);
6074 /* Hardware implementation registers */
6075 /* XXX : not implemented */
6076 spr_register(env, SPR_HID0, "HID0",
6077 SPR_NOACCESS, SPR_NOACCESS,
06403421 6078 &spr_read_generic, &spr_write_clear,
d63001d1 6079 0x60000000);
a750fc0b
JM		 6080 /* XXX : not implemented */
6081 spr_register(env, SPR_HID1, "HID1",
6082 SPR_NOACCESS, SPR_NOACCESS,
6083 &spr_read_generic, &spr_write_generic,
6084 0x00000000);
6085 /* XXX : not implemented */
bd928eba 6086 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6087 SPR_NOACCESS, SPR_NOACCESS,
6088 &spr_read_generic, &spr_write_generic,
6089 0x00000000);
d63001d1
JM		 6090 /* XXX : not implemented */
6091 spr_register(env, SPR_970_HID5, "HID5",
6092 SPR_NOACCESS, SPR_NOACCESS,
6093 &spr_read_generic, &spr_write_generic,
417bf010 6094 POWERPC970_HID5_INIT);
bd928eba
JM		 6095 /* XXX : not implemented */
6096 spr_register(env, SPR_L2CR, "L2CR",
6097 SPR_NOACCESS, SPR_NOACCESS,
6098 &spr_read_generic, &spr_write_generic,
6099 0x00000000);
a750fc0b
JM		 6100 /* Memory management */
6101 /* XXX: not correct */
6102 gen_low_BATs(env);
12de9a39
JM		 6103 /* XXX : not implemented */
6104 spr_register(env, SPR_MMUCFG, "MMUCFG",
6105 SPR_NOACCESS, SPR_NOACCESS,
6106 &spr_read_generic, SPR_NOACCESS,
6107 0x00000000); /* TOFIX */
6108 /* XXX : not implemented */
6109 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6110 SPR_NOACCESS, SPR_NOACCESS,
6111 &spr_read_generic, &spr_write_generic,
6112 0x00000000); /* TOFIX */
6113 spr_register(env, SPR_HIOR, "SPR_HIOR",
6114 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6115 &spr_read_hior, &spr_write_hior,
6116 0x00000000);
4e98d8cf
BS		 6117 spr_register(env, SPR_CTRL, "SPR_CTRL",
6118 SPR_NOACCESS, SPR_NOACCESS,
6119 &spr_read_generic, &spr_write_generic,
6120 0x00000000);
6121 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6122 SPR_NOACCESS, SPR_NOACCESS,
6123 &spr_read_generic, &spr_write_generic,
6124 0x00000000);
6125 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6126 &spr_read_generic, &spr_write_generic,
6127 &spr_read_generic, &spr_write_generic,
6128 0x00000000);
f2e63a42 6129#if !defined(CONFIG_USER_ONLY)
8eee0af9 6130 env->slb_nr = 64;
f2e63a42 6131#endif
e1833e1f 6132 init_excp_970(env);
d63001d1
JM		 6133 env->dcache_line_size = 128;
6134 env->icache_line_size = 128;
a750fc0b
JM		 6135 /* Allocate hardware IRQ controller */
6136 ppc970_irq_init(env);
cf8358c8
AJ		 6137 /* Can't find information on what this should be on reset. This
6138 * value is the one used by 74xx processors. */
6139 vscr_init(env, 0x00010000);
a750fc0b 6140}
a750fc0b
JM		 6141
6142/* PowerPC 970 GX */
082c6681
JM		 6143#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6144 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6145 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6146 PPC_FLOAT_STFIWX | \
6147 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6148 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6149 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6150 PPC_64B | PPC_ALTIVEC | \
12de9a39 6151 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6152#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6153#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6154#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6155#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6156#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6157#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6158 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6159 POWERPC_FLAG_BUS_CLK)
a750fc0b 6160
2f462816
JM		 6161static int check_pow_970GX (CPUPPCState *env)
6162{
6163 if (env->spr[SPR_HID0] & 0x00600000)
6164 return 1;
6165
6166 return 0;
6167}
6168
a750fc0b
JM		 6169static void init_proc_970GX (CPUPPCState *env)
6170{
6171 gen_spr_ne_601(env);
6172 gen_spr_7xx(env);
6173 /* Time base */
6174 gen_tbl(env);
6175 /* Hardware implementation registers */
6176 /* XXX : not implemented */
6177 spr_register(env, SPR_HID0, "HID0",
6178 SPR_NOACCESS, SPR_NOACCESS,
06403421 6179 &spr_read_generic, &spr_write_clear,
d63001d1 6180 0x60000000);
a750fc0b
JM		 6181 /* XXX : not implemented */
6182 spr_register(env, SPR_HID1, "HID1",
6183 SPR_NOACCESS, SPR_NOACCESS,
6184 &spr_read_generic, &spr_write_generic,
6185 0x00000000);
6186 /* XXX : not implemented */
bd928eba 6187 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6188 SPR_NOACCESS, SPR_NOACCESS,
6189 &spr_read_generic, &spr_write_generic,
6190 0x00000000);
d63001d1
JM		 6191 /* XXX : not implemented */
6192 spr_register(env, SPR_970_HID5, "HID5",
6193 SPR_NOACCESS, SPR_NOACCESS,
6194 &spr_read_generic, &spr_write_generic,
417bf010 6195 POWERPC970_HID5_INIT);
bd928eba
JM		 6196 /* XXX : not implemented */
6197 spr_register(env, SPR_L2CR, "L2CR",
6198 SPR_NOACCESS, SPR_NOACCESS,
6199 &spr_read_generic, &spr_write_generic,
6200 0x00000000);
a750fc0b
JM		 6201 /* Memory management */
6202 /* XXX: not correct */
6203 gen_low_BATs(env);
12de9a39
JM		 6204 /* XXX : not implemented */
6205 spr_register(env, SPR_MMUCFG, "MMUCFG",
6206 SPR_NOACCESS, SPR_NOACCESS,
6207 &spr_read_generic, SPR_NOACCESS,
6208 0x00000000); /* TOFIX */
6209 /* XXX : not implemented */
6210 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6211 SPR_NOACCESS, SPR_NOACCESS,
6212 &spr_read_generic, &spr_write_generic,
6213 0x00000000); /* TOFIX */
6214 spr_register(env, SPR_HIOR, "SPR_HIOR",
6215 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6216 &spr_read_hior, &spr_write_hior,
6217 0x00000000);
f2e63a42 6218#if !defined(CONFIG_USER_ONLY)
12de9a39 6219 env->slb_nr = 32;
f2e63a42 6220#endif
e1833e1f 6221 init_excp_970(env);
d63001d1
JM		 6222 env->dcache_line_size = 128;
6223 env->icache_line_size = 128;
a750fc0b
JM		 6224 /* Allocate hardware IRQ controller */
6225 ppc970_irq_init(env);
cf8358c8
AJ		 6226 /* Can't find information on what this should be on reset. This
6227 * value is the one used by 74xx processors. */
6228 vscr_init(env, 0x00010000);
a750fc0b 6229}
a750fc0b 6230
2f462816 6231/* PowerPC 970 MP */
082c6681
JM		 6232#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6233 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6234 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6235 PPC_FLOAT_STFIWX | \
6236 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6237 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6238 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6239 PPC_64B | PPC_ALTIVEC | \
6240 PPC_SEGMENT_64B | PPC_SLBI)
6241#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6242#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6243#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6244#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6245#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6246#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6247 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6248 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6249
6250static int check_pow_970MP (CPUPPCState *env)
6251{
6252 if (env->spr[SPR_HID0] & 0x01C00000)
6253 return 1;
6254
6255 return 0;
6256}
6257
6258static void init_proc_970MP (CPUPPCState *env)
6259{
6260 gen_spr_ne_601(env);
6261 gen_spr_7xx(env);
6262 /* Time base */
6263 gen_tbl(env);
6264 /* Hardware implementation registers */
6265 /* XXX : not implemented */
6266 spr_register(env, SPR_HID0, "HID0",
6267 SPR_NOACCESS, SPR_NOACCESS,
6268 &spr_read_generic, &spr_write_clear,
6269 0x60000000);
6270 /* XXX : not implemented */
6271 spr_register(env, SPR_HID1, "HID1",
6272 SPR_NOACCESS, SPR_NOACCESS,
6273 &spr_read_generic, &spr_write_generic,
6274 0x00000000);
6275 /* XXX : not implemented */
bd928eba 6276 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6277 SPR_NOACCESS, SPR_NOACCESS,
6278 &spr_read_generic, &spr_write_generic,
6279 0x00000000);
6280 /* XXX : not implemented */
6281 spr_register(env, SPR_970_HID5, "HID5",
6282 SPR_NOACCESS, SPR_NOACCESS,
6283 &spr_read_generic, &spr_write_generic,
6284 POWERPC970_HID5_INIT);
bd928eba
JM		 6285 /* XXX : not implemented */
6286 spr_register(env, SPR_L2CR, "L2CR",
6287 SPR_NOACCESS, SPR_NOACCESS,
6288 &spr_read_generic, &spr_write_generic,
6289 0x00000000);
2f462816
JM		 6290 /* Memory management */
6291 /* XXX: not correct */
6292 gen_low_BATs(env);
6293 /* XXX : not implemented */
6294 spr_register(env, SPR_MMUCFG, "MMUCFG",
6295 SPR_NOACCESS, SPR_NOACCESS,
6296 &spr_read_generic, SPR_NOACCESS,
6297 0x00000000); /* TOFIX */
6298 /* XXX : not implemented */
6299 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6300 SPR_NOACCESS, SPR_NOACCESS,
6301 &spr_read_generic, &spr_write_generic,
6302 0x00000000); /* TOFIX */
6303 spr_register(env, SPR_HIOR, "SPR_HIOR",
6304 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6305 &spr_read_hior, &spr_write_hior,
6306 0x00000000);
2f462816
JM		 6307#if !defined(CONFIG_USER_ONLY)
6308 env->slb_nr = 32;
6309#endif
6310 init_excp_970(env);
6311 env->dcache_line_size = 128;
6312 env->icache_line_size = 128;
6313 /* Allocate hardware IRQ controller */
6314 ppc970_irq_init(env);
cf8358c8
AJ		 6315 /* Can't find information on what this should be on reset. This
6316 * value is the one used by 74xx processors. */
6317 vscr_init(env, 0x00010000);
2f462816
JM		 6318}
6319
a750fc0b 6320/* PowerPC 620 */
082c6681
JM		 6321#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6322 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6323 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6324 PPC_FLOAT_STFIWX | \
6325 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6326 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6327 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6328 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6329 PPC_64B | PPC_SLBI)
add78955
JM		 6330#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6331//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6332#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6333#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6334#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6335#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6336 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6337#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6338
578bb252 6339__attribute__ (( unused ))
a750fc0b
JM		 6340static void init_proc_620 (CPUPPCState *env)
6341{
6342 gen_spr_ne_601(env);
6343 gen_spr_620(env);
6344 /* Time base */
6345 gen_tbl(env);
6346 /* Hardware implementation registers */
6347 /* XXX : not implemented */
6348 spr_register(env, SPR_HID0, "HID0",
6349 SPR_NOACCESS, SPR_NOACCESS,
6350 &spr_read_generic, &spr_write_generic,
6351 0x00000000);
6352 /* Memory management */
6353 gen_low_BATs(env);
e1833e1f 6354 init_excp_620(env);
d63001d1
JM		 6355 env->dcache_line_size = 64;
6356 env->icache_line_size = 64;
faadf50e
JM		 6357 /* Allocate hardware IRQ controller */
6358 ppc6xx_irq_init(env);
a750fc0b 6359}
a750fc0b
JM		 6360#endif /* defined (TARGET_PPC64) */
6361
6362/* Default 32 bits PowerPC target will be 604 */
6363#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6364#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6365#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6366#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6367#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6368#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6369#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6370#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6371#define check_pow_PPC32 check_pow_604
6372#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6373
6374/* Default 64 bits PowerPC target will be 970 FX */
6375#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6376#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6377#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6378#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6379#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6380#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6381#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6382#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6383#define check_pow_PPC64 check_pow_970FX
6384#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6385
6386/* Default PowerPC target will be PowerPC 32 */
6387#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 6388#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6389#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6390#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6391#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6392#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6393#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 6394#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 6395#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 6396#define check_pow_DEFAULT check_pow_PPC64
6397#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6398#else
d12f4c38
JM		 6399#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6400#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6401#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6402#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6403#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6404#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 6405#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 6406#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 6407#define check_pow_DEFAULT check_pow_PPC32
6408#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6409#endif
6410
6411/*****************************************************************************/
6412/* PVR definitions for most known PowerPC */
6413enum {
6414 /* PowerPC 401 family */
6415 /* Generic PowerPC 401 */
80d11f44 6416#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6417 /* PowerPC 401 cores */
80d11f44
JM		 6418 CPU_POWERPC_401A1 = 0x00210000,
6419 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6420#if 0
80d11f44 6421 CPU_POWERPC_401B3 = xxx,
a750fc0b 6422#endif
80d11f44
JM		 6423 CPU_POWERPC_401C2 = 0x00230000,
6424 CPU_POWERPC_401D2 = 0x00240000,
6425 CPU_POWERPC_401E2 = 0x00250000,
6426 CPU_POWERPC_401F2 = 0x00260000,
6427 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6428 /* PowerPC 401 microcontrolers */
6429#if 0
80d11f44 6430 CPU_POWERPC_401GF = xxx,
a750fc0b 6431#endif
80d11f44 6432#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6433 /* IBM Processor for Network Resources */
80d11f44 6434 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6435#if 0
80d11f44 6436 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6437#endif
6438 /* PowerPC 403 family */
6439 /* Generic PowerPC 403 */
80d11f44 6440#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6441 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6442 CPU_POWERPC_403GA = 0x00200011,
6443 CPU_POWERPC_403GB = 0x00200100,
6444 CPU_POWERPC_403GC = 0x00200200,
6445 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6446#if 0
80d11f44 6447 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6448#endif
6449 /* PowerPC 405 family */
6450 /* Generic PowerPC 405 */
80d11f44 6451#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6452 /* PowerPC 405 cores */
6453#if 0
80d11f44 6454 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6455#endif
6456#if 0
80d11f44 6457 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6458#endif
6459#if 0
80d11f44 6460 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6461#endif
6462#if 0
80d11f44 6463 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6464#endif
6465#if 0
80d11f44 6466 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6467#endif
6468#if 0
80d11f44 6469 CPU_POWERPC_405C4 = xxx,
a750fc0b 6470#endif
80d11f44 6471 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6472#if 0
80d11f44 6473 CPU_POWERPC_405D3 = xxx,
a750fc0b 6474#endif
80d11f44 6475 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6476#if 0
80d11f44 6477 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6478#endif
6479#if 0
80d11f44 6480 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6481#endif
6482#if 0
80d11f44 6483 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6484#endif
6485#if 0
80d11f44 6486 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6487#endif
6488#if 0
80d11f44 6489 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6490#endif
6491 /* PowerPC 405 microcontrolers */
6492 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6493#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6494 CPU_POWERPC_405CRa = 0x40110041,
6495 CPU_POWERPC_405CRb = 0x401100C5,
6496 CPU_POWERPC_405CRc = 0x40110145,
6497 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6498#if 0
80d11f44 6499 CPU_POWERPC_405EXr = xxx,
a750fc0b 6500#endif
80d11f44 6501 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6502#if 0
80d11f44
JM		 6503 CPU_POWERPC_405FX = xxx,
6504#endif
6505#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6506 CPU_POWERPC_405GPa = 0x40110000,
6507 CPU_POWERPC_405GPb = 0x40110040,
6508 CPU_POWERPC_405GPc = 0x40110082,
6509 CPU_POWERPC_405GPd = 0x401100C4,
6510#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6511 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6512#if 0
80d11f44 6513 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6514#endif
6515#if 0
80d11f44 6516 CPU_POWERPC_405L = xxx,
a750fc0b 6517#endif
80d11f44 6518 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6519#if 0
80d11f44 6520 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6521#endif
6522#if 0
80d11f44 6523 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6524#endif
6525#if 0
80d11f44 6526 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6527#endif
6528 /* IBM network processors */
80d11f44
JM		 6529 CPU_POWERPC_NPE405H = 0x414100C0,
6530 CPU_POWERPC_NPE405H2 = 0x41410140,
6531 CPU_POWERPC_NPE405L = 0x416100C0,
6532 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6533#if 0
80d11f44 6534 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6535#endif
6536#if 0
80d11f44 6537 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6538#endif
6539#if 0
80d11f44 6540 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6541#endif
6542 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6543#if 0
80d11f44 6544 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6545#endif
6546#if 0
80d11f44 6547 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6548#endif
6549#if 0
80d11f44 6550 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6551#endif
80d11f44 6552 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6553#if 0
80d11f44 6554 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6555#endif
6556#if 0
80d11f44 6557 CPU_POWERPC_STB045 = xxx,
a750fc0b 6558#endif
80d11f44
JM		 6559 CPU_POWERPC_STB04 = 0x41810000,
6560 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6561#if 0
80d11f44 6562 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6563#endif
6564 /* Xilinx cores */
80d11f44
JM		 6565 CPU_POWERPC_X2VP4 = 0x20010820,
6566#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6567 CPU_POWERPC_X2VP20 = 0x20010860,
6568#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6569#if 0
80d11f44 6570 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6571#endif
6572#if 0
80d11f44 6573 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6574#endif
6575#if 0
80d11f44 6576 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6577#endif
6578#if 0
80d11f44 6579 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6580#endif
6581 /* PowerPC 440 family */
6582 /* Generic PowerPC 440 */
80d11f44 6583#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6584 /* PowerPC 440 cores */
6585#if 0
80d11f44 6586 CPU_POWERPC_440A4 = xxx,
a750fc0b 6587#endif
95070372 6588 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 6589#if 0
80d11f44 6590 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6591#endif
6592#if 0
80d11f44 6593 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6594#endif
6595#if 0
80d11f44 6596 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6597#endif
6598#if 0
80d11f44 6599 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6600#endif
6601#if 0
80d11f44 6602 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6603#endif
6604#if 0
80d11f44 6605 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6606#endif
6607 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6608#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6609 CPU_POWERPC_440EPa = 0x42221850,
6610 CPU_POWERPC_440EPb = 0x422218D3,
6611#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6612 CPU_POWERPC_440GPb = 0x40120440,
6613 CPU_POWERPC_440GPc = 0x40120481,
6614#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6615#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6616 CPU_POWERPC_440GRX = 0x200008D0,
6617#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6618#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6619 CPU_POWERPC_440GXa = 0x51B21850,
6620 CPU_POWERPC_440GXb = 0x51B21851,
6621 CPU_POWERPC_440GXc = 0x51B21892,
6622 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6623#if 0
80d11f44 6624 CPU_POWERPC_440S = xxx,
a750fc0b 6625#endif
80d11f44
JM		 6626 CPU_POWERPC_440SP = 0x53221850,
6627 CPU_POWERPC_440SP2 = 0x53221891,
6628 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6629 /* PowerPC 460 family */
6630#if 0
6631 /* Generic PowerPC 464 */
80d11f44 6632#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6633#endif
6634 /* PowerPC 464 microcontrolers */
6635#if 0
80d11f44 6636 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6637#endif
6638#if 0
80d11f44 6639 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6640#endif
6641 /* Freescale embedded PowerPC cores */
c3e36823 6642 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6643 CPU_POWERPC_MPC5xx = 0x00020020,
6644#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6645#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6646#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6647#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6648#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6649#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6650#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6651#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6652#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6653#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6654#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6655#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6656#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6657 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6658 CPU_POWERPC_MPC8xx = 0x00500000,
6659#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6660#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6661#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6662#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6663#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6664#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6665#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6666#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6667#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6668#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6669#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6670#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6671#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6672#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6673#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6674 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6675 CPU_POWERPC_G2 = 0x00810011,
6676 CPU_POWERPC_G2H4 = 0x80811010,
6677 CPU_POWERPC_G2gp = 0x80821010,
6678 CPU_POWERPC_G2ls = 0x90810010,
6679 CPU_POWERPC_MPC603 = 0x00810100,
6680 CPU_POWERPC_G2_HIP3 = 0x00810101,
6681 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6682 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6683 CPU_POWERPC_G2LE = 0x80820010,
6684 CPU_POWERPC_G2LEgp = 0x80822010,
6685 CPU_POWERPC_G2LEls = 0xA0822010,
6686 CPU_POWERPC_G2LEgp1 = 0x80822011,
6687 CPU_POWERPC_G2LEgp3 = 0x80822013,
6688 /* MPC52xx microcontrollers */
c3e36823 6689 /* XXX: MPC 5121 ? */
80d11f44
JM		 6690#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6691#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6692#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6693#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6694#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6695#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6696#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6697#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6698 /* MPC82xx microcontrollers */
6699#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6700#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6701#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6702#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6703#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6704#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6705#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6706#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6707#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6708#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6709#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6710#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6711#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6712#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6713#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6714#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6715#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6716#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6717#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6718#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6719#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6720#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6721#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6722#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6723#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6724#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6725#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6726#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6727#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6728 /* e200 family */
80d11f44
JM		 6729 /* e200 cores */
6730#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6731#if 0
80d11f44 6732 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6733#endif
6734#if 0
80d11f44 6735 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6736#endif
6737#if 0 /* ? */
80d11f44
JM		 6738 CPU_POWERPC_e200z3 = 0x81120000,
6739#endif
6740 CPU_POWERPC_e200z5 = 0x81000000,
6741 CPU_POWERPC_e200z6 = 0x81120000,
6742 /* MPC55xx microcontrollers */
6743#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6744#if 0
6745#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6746#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6747#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6748#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6749#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6750#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6751#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6752#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6753#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6754#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6755#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6756#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6757#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6758#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6759#endif
6760#if 0
6761#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6762#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6763#endif
6764#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6765#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6766#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6767#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6768#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6769#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 6770 /* e300 family */
80d11f44
JM		 6771 /* e300 cores */
6772#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6773 CPU_POWERPC_e300c1 = 0x00830010,
6774 CPU_POWERPC_e300c2 = 0x00840010,
6775 CPU_POWERPC_e300c3 = 0x00850010,
6776 CPU_POWERPC_e300c4 = 0x00860010,
6777 /* MPC83xx microcontrollers */
74d77cae
TM		 6778#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
6779#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
6780#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
6781#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
6782#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
6783#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 6784 /* e500 family */
80d11f44
JM		 6785 /* e500 cores */
6786#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 6787#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 6788#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 6789 CPU_POWERPC_e500v1_v10 = 0x80200010,
6790 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 6791 CPU_POWERPC_e500v2_v10 = 0x80210010,
6792 CPU_POWERPC_e500v2_v11 = 0x80210011,
6793 CPU_POWERPC_e500v2_v20 = 0x80210020,
6794 CPU_POWERPC_e500v2_v21 = 0x80210021,
6795 CPU_POWERPC_e500v2_v22 = 0x80210022,
6796 CPU_POWERPC_e500v2_v30 = 0x80210030,
6797 /* MPC85xx microcontrollers */
6798#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6799#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6800#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6801#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6802#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6803#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6804#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 6805#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
6806#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
6807#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 6808#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 6809#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
6810#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 6811#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 6812#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
6813#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 6814#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6815#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6816#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6817#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6818#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6819#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6820#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6821#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6822#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6823#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6824#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6825#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6826#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6827#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6828#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6829#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6830#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6831#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6832#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6833#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6834#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6835#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6836#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6837#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6838#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6839#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6840#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6841#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6842#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6843#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6844#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6845#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6846#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6847#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6848#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6849#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6850#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6851#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6852#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6853#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6854#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6855#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6856#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6857#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6858#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6859#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6860#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6861#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6862#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6863#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6864#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6865#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6866#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6867#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 6868 /* e600 family */
80d11f44
JM		 6869 /* e600 cores */
6870 CPU_POWERPC_e600 = 0x80040010,
6871 /* MPC86xx microcontrollers */
6872#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6873#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6874#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 6875 /* PowerPC 6xx cores */
80d11f44
JM		 6876#define CPU_POWERPC_601 CPU_POWERPC_601_v2
6877 CPU_POWERPC_601_v0 = 0x00010001,
6878 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 6879#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 6880 CPU_POWERPC_601_v2 = 0x00010002,
6881 CPU_POWERPC_602 = 0x00050100,
6882 CPU_POWERPC_603 = 0x00030100,
6883#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6884 CPU_POWERPC_603E_v11 = 0x00060101,
6885 CPU_POWERPC_603E_v12 = 0x00060102,
6886 CPU_POWERPC_603E_v13 = 0x00060103,
6887 CPU_POWERPC_603E_v14 = 0x00060104,
6888 CPU_POWERPC_603E_v22 = 0x00060202,
6889 CPU_POWERPC_603E_v3 = 0x00060300,
6890 CPU_POWERPC_603E_v4 = 0x00060400,
6891 CPU_POWERPC_603E_v41 = 0x00060401,
6892 CPU_POWERPC_603E7t = 0x00071201,
6893 CPU_POWERPC_603E7v = 0x00070100,
6894 CPU_POWERPC_603E7v1 = 0x00070101,
6895 CPU_POWERPC_603E7v2 = 0x00070201,
6896 CPU_POWERPC_603E7 = 0x00070200,
6897 CPU_POWERPC_603P = 0x00070000,
6898#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 6899 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 6900 CPU_POWERPC_604 = 0x00040103,
6901#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 6902 /* XXX: missing 0x00091203 */
6903 /* XXX: missing 0x00092110 */
6904 /* XXX: missing 0x00092120 */
80d11f44
JM		 6905 CPU_POWERPC_604E_v10 = 0x00090100,
6906 CPU_POWERPC_604E_v22 = 0x00090202,
6907 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 6908 /* XXX: missing 0x000a0100 */
6909 /* XXX: missing 0x00093102 */
80d11f44 6910 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 6911#if 0
80d11f44 6912 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 6913#endif
6914 /* PowerPC 740/750 cores (aka G3) */
6915 /* XXX: missing 0x00084202 */
80d11f44 6916#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 6917 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 6918 CPU_POWERPC_7x0_v20 = 0x00080200,
6919 CPU_POWERPC_7x0_v21 = 0x00080201,
6920 CPU_POWERPC_7x0_v22 = 0x00080202,
6921 CPU_POWERPC_7x0_v30 = 0x00080300,
6922 CPU_POWERPC_7x0_v31 = 0x00080301,
6923 CPU_POWERPC_740E = 0x00080100,
bd928eba 6924 CPU_POWERPC_750E = 0x00080200,
80d11f44 6925 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 6926 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 6927#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6928 CPU_POWERPC_750CL_v10 = 0x00087200,
6929 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 6930#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 6931 CPU_POWERPC_750CX_v10 = 0x00082100,
6932 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 6933 CPU_POWERPC_750CX_v21 = 0x00082201,
6934 CPU_POWERPC_750CX_v22 = 0x00082202,
6935#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6936 CPU_POWERPC_750CXE_v21 = 0x00082211,
6937 CPU_POWERPC_750CXE_v22 = 0x00082212,
6938 CPU_POWERPC_750CXE_v23 = 0x00082213,
6939 CPU_POWERPC_750CXE_v24 = 0x00082214,
6940 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 6941 CPU_POWERPC_750CXE_v30 = 0x00082310,
6942 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 6943 CPU_POWERPC_750CXE_v31b = 0x00083311,
6944 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 6945 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 6946#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6947 CPU_POWERPC_750FX_v10 = 0x70000100,
6948 CPU_POWERPC_750FX_v20 = 0x70000200,
6949 CPU_POWERPC_750FX_v21 = 0x70000201,
6950 CPU_POWERPC_750FX_v22 = 0x70000202,
6951 CPU_POWERPC_750FX_v23 = 0x70000203,
6952 CPU_POWERPC_750GL = 0x70020102,
6953#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6954 CPU_POWERPC_750GX_v10 = 0x70020100,
6955 CPU_POWERPC_750GX_v11 = 0x70020101,
6956 CPU_POWERPC_750GX_v12 = 0x70020102,
6957#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 6958 CPU_POWERPC_750L_v20 = 0x00088200,
6959 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 6960 CPU_POWERPC_750L_v22 = 0x00088202,
6961 CPU_POWERPC_750L_v30 = 0x00088300,
6962 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 6963 /* PowerPC 745/755 cores */
80d11f44
JM		 6964#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6965 CPU_POWERPC_7x5_v10 = 0x00083100,
6966 CPU_POWERPC_7x5_v11 = 0x00083101,
6967 CPU_POWERPC_7x5_v20 = 0x00083200,
6968 CPU_POWERPC_7x5_v21 = 0x00083201,
6969 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6970 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6971 CPU_POWERPC_7x5_v24 = 0x00083204,
6972 CPU_POWERPC_7x5_v25 = 0x00083205,
6973 CPU_POWERPC_7x5_v26 = 0x00083206,
6974 CPU_POWERPC_7x5_v27 = 0x00083207,
6975 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 6976#if 0
80d11f44 6977 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 6978#endif
6979 /* PowerPC 74xx cores (aka G4) */
6980 /* XXX: missing 0x000C1101 */
80d11f44
JM		 6981#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6982 CPU_POWERPC_7400_v10 = 0x000C0100,
6983 CPU_POWERPC_7400_v11 = 0x000C0101,
6984 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 6985 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 6986 CPU_POWERPC_7400_v22 = 0x000C0202,
6987 CPU_POWERPC_7400_v26 = 0x000C0206,
6988 CPU_POWERPC_7400_v27 = 0x000C0207,
6989 CPU_POWERPC_7400_v28 = 0x000C0208,
6990 CPU_POWERPC_7400_v29 = 0x000C0209,
6991#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6992 CPU_POWERPC_7410_v10 = 0x800C1100,
6993 CPU_POWERPC_7410_v11 = 0x800C1101,
6994 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6995 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6996 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6997#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6998 CPU_POWERPC_7448_v10 = 0x80040100,
6999 CPU_POWERPC_7448_v11 = 0x80040101,
7000 CPU_POWERPC_7448_v20 = 0x80040200,
7001 CPU_POWERPC_7448_v21 = 0x80040201,
7002#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7003 CPU_POWERPC_7450_v10 = 0x80000100,
7004 CPU_POWERPC_7450_v11 = 0x80000101,
7005 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 7006 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 7007 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 7008#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7009 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7010 /* XXX: this entry might be a bug in some documentation */
7011 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 7012#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7013 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 7014 /* XXX: missing 0x80010200 */
80d11f44
JM		 7015 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7016 CPU_POWERPC_74x5_v32 = 0x80010302,
7017 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7018 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7019#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 7020 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 7021 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 7022 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 7023#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7024 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7025 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7026 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 7027 /* 64 bits PowerPC */
00af685f 7028#if defined(TARGET_PPC64)
80d11f44
JM		 7029 CPU_POWERPC_620 = 0x00140000,
7030 CPU_POWERPC_630 = 0x00400000,
7031 CPU_POWERPC_631 = 0x00410104,
7032 CPU_POWERPC_POWER4 = 0x00350000,
7033 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 7034 /* XXX: missing 0x003A0201 */
80d11f44
JM		 7035 CPU_POWERPC_POWER5 = 0x003A0203,
7036#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7037 CPU_POWERPC_POWER5P = 0x003B0000,
7038#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7039 CPU_POWERPC_POWER6 = 0x003E0000,
7040 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7041 CPU_POWERPC_POWER6A = 0x0F000002,
7042 CPU_POWERPC_970 = 0x00390202,
7043#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7044 CPU_POWERPC_970FX_v10 = 0x00391100,
7045 CPU_POWERPC_970FX_v20 = 0x003C0200,
7046 CPU_POWERPC_970FX_v21 = 0x003C0201,
7047 CPU_POWERPC_970FX_v30 = 0x003C0300,
7048 CPU_POWERPC_970FX_v31 = 0x003C0301,
7049 CPU_POWERPC_970GX = 0x00450000,
7050#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7051 CPU_POWERPC_970MP_v10 = 0x00440100,
7052 CPU_POWERPC_970MP_v11 = 0x00440101,
7053#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7054 CPU_POWERPC_CELL_v10 = 0x00700100,
7055 CPU_POWERPC_CELL_v20 = 0x00700400,
7056 CPU_POWERPC_CELL_v30 = 0x00700500,
7057 CPU_POWERPC_CELL_v31 = 0x00700501,
7058#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7059 CPU_POWERPC_RS64 = 0x00330000,
7060 CPU_POWERPC_RS64II = 0x00340000,
7061 CPU_POWERPC_RS64III = 0x00360000,
7062 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7063#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7064 /* Original POWER */
7065 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7066 * POWER2 (RIOS2) & RSC2 (P2SC) here
7067 */
7068#if 0
80d11f44 7069 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7070#endif
7071#if 0
80d11f44 7072 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7073#endif
7074 /* PA Semi core */
80d11f44 7075 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7076};
7077
7078/* System version register (used on MPC 8xxx) */
7079enum {
80d11f44
JM		 7080 POWERPC_SVR_NONE = 0x00000000,
7081#define POWERPC_SVR_52xx POWERPC_SVR_5200
7082#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7083 POWERPC_SVR_5200_v10 = 0x80110010,
7084 POWERPC_SVR_5200_v11 = 0x80110011,
7085 POWERPC_SVR_5200_v12 = 0x80110012,
7086#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7087 POWERPC_SVR_5200B_v20 = 0x80110020,
7088 POWERPC_SVR_5200B_v21 = 0x80110021,
7089#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7090#if 0
80d11f44 7091 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7092#endif
7093#if 0
80d11f44 7094 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7095#endif
7096#if 0
80d11f44 7097 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7098#endif
7099#if 0
80d11f44 7100 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7101#endif
7102#if 0
80d11f44 7103 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7104#endif
7105#if 0
80d11f44 7106 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7107#endif
7108#if 0
80d11f44 7109 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7110#endif
7111#if 0
80d11f44 7112 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7113#endif
7114#if 0
80d11f44 7115 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7116#endif
7117#if 0
80d11f44 7118 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7119#endif
7120#if 0
80d11f44 7121 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7122#endif
7123#if 0
80d11f44 7124 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7125#endif
7126#if 0
80d11f44 7127 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7128#endif
7129#if 0
80d11f44 7130 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7131#endif
7132#if 0
80d11f44 7133 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7134#endif
7135#if 0
80d11f44 7136 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7137#endif
7138#if 0
80d11f44 7139 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7140#endif
7141#if 0
80d11f44
JM		 7142 POWERPC_SVR_8323E = xxx,
7143#endif
492d7bf5 7144 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7145 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7146 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7147 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7148#define POWERPC_SVR_8347 POWERPC_SVR_8347T
7149 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7150 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7151#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7152 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7153 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7154#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7155 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7156 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7157#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7158 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7159 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7160 POWERPC_SVR_8349 = 0x80510010,
7161 POWERPC_SVR_8349A = 0x80510030,
7162 POWERPC_SVR_8349E = 0x80500010,
7163 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7164#if 0
80d11f44 7165 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7166#endif
7167#if 0
80d11f44
JM		 7168 POWERPC_SVR_8360E = xxx,
7169#endif
7170#define POWERPC_SVR_E500 0x40000000
7171 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7172 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7173 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7174 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7175 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7176 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7177#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7178 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7179 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7180#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7181 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7182 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7183#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7184 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7185 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7186 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7187#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7188 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7189 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7190#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7191 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7192 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7193#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7194 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7195 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7196 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7197 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7198#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7199 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7200 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7201 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7202 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7203#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7204 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7205 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7206#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7207 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7208 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7209#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7210 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7211 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7212#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7213 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7214 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7215#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7216 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7217 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7218#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7219 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7220 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7221 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7222 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7223#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7224 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7225 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7226 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7227 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7228#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7229 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7230 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7231#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7232 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7233 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7234#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7235 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7236 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7237 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7238 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7239 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7240 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7241 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7242 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7243 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7244#if 0
80d11f44 7245 POWERPC_SVR_8610 = xxx,
c3e36823 7246#endif
80d11f44
JM		 7247 POWERPC_SVR_8641 = 0x80900021,
7248 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7249};
7250
3fc6c082 7251/*****************************************************************************/
a750fc0b 7252/* PowerPC CPU definitions */
80d11f44 7253#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 7254 { \
7255 .name = _name, \
7256 .pvr = _pvr, \
80d11f44 7257 .svr = _svr, \
a750fc0b
JM		 7258 .insns_flags = glue(POWERPC_INSNS_,_type), \
7259 .msr_mask = glue(POWERPC_MSRM_,_type), \
7260 .mmu_model = glue(POWERPC_MMU_,_type), \
7261 .excp_model = glue(POWERPC_EXCP_,_type), \
7262 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 7263 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 7264 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 7265 .init_proc = &glue(init_proc_,_type), \
2f462816 7266 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7267 }
80d11f44
JM		 7268#define POWERPC_DEF(_name, _pvr, _type) \
7269POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7270
c227f099 7271static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7272 /* Embedded PowerPC */
7273 /* PowerPC 401 family */
2662a059 7274 /* Generic PowerPC 401 */
80d11f44 7275 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7276 /* PowerPC 401 cores */
2662a059 7277 /* PowerPC 401A1 */
80d11f44 7278 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7279 /* PowerPC 401B2 */
80d11f44 7280 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7281#if defined (TODO)
a750fc0b 7282 /* PowerPC 401B3 */
80d11f44 7283 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7284#endif
7285 /* PowerPC 401C2 */
80d11f44 7286 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7287 /* PowerPC 401D2 */
80d11f44 7288 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7289 /* PowerPC 401E2 */
80d11f44 7290 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7291 /* PowerPC 401F2 */
80d11f44 7292 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7293 /* PowerPC 401G2 */
7294 /* XXX: to be checked */
80d11f44 7295 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7296 /* PowerPC 401 microcontrolers */
2662a059 7297#if defined (TODO)
a750fc0b 7298 /* PowerPC 401GF */
80d11f44 7299 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7300#endif
a750fc0b 7301 /* IOP480 (401 microcontroler) */
80d11f44 7302 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7303 /* IBM Processor for Network Resources */
80d11f44 7304 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7305#if defined (TODO)
80d11f44 7306 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7307#endif
a750fc0b
JM		 7308 /* PowerPC 403 family */
7309 /* Generic PowerPC 403 */
80d11f44 7310 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7311 /* PowerPC 403 microcontrolers */
7312 /* PowerPC 403 GA */
80d11f44 7313 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7314 /* PowerPC 403 GB */
80d11f44 7315 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7316 /* PowerPC 403 GC */
80d11f44 7317 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7318 /* PowerPC 403 GCX */
80d11f44 7319 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7320#if defined (TODO)
a750fc0b 7321 /* PowerPC 403 GP */
80d11f44 7322 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7323#endif
a750fc0b
JM		 7324 /* PowerPC 405 family */
7325 /* Generic PowerPC 405 */
80d11f44 7326 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7327 /* PowerPC 405 cores */
2662a059 7328#if defined (TODO)
a750fc0b 7329 /* PowerPC 405 A3 */
80d11f44 7330 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7331#endif
3a607854 7332#if defined (TODO)
a750fc0b 7333 /* PowerPC 405 A4 */
80d11f44 7334 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7335#endif
3a607854 7336#if defined (TODO)
a750fc0b 7337 /* PowerPC 405 B3 */
80d11f44 7338 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7339#endif
7340#if defined (TODO)
a750fc0b 7341 /* PowerPC 405 B4 */
80d11f44 7342 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7343#endif
7344#if defined (TODO)
7345 /* PowerPC 405 C3 */
80d11f44 7346 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7347#endif
7348#if defined (TODO)
7349 /* PowerPC 405 C4 */
80d11f44 7350 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7351#endif
7352 /* PowerPC 405 D2 */
80d11f44 7353 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7354#if defined (TODO)
7355 /* PowerPC 405 D3 */
80d11f44 7356 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7357#endif
7358 /* PowerPC 405 D4 */
80d11f44 7359 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7360#if defined (TODO)
7361 /* PowerPC 405 D5 */
80d11f44 7362 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7363#endif
7364#if defined (TODO)
7365 /* PowerPC 405 E4 */
80d11f44 7366 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7367#endif
7368#if defined (TODO)
7369 /* PowerPC 405 F4 */
80d11f44 7370 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7371#endif
7372#if defined (TODO)
7373 /* PowerPC 405 F5 */
80d11f44 7374 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7375#endif
7376#if defined (TODO)
7377 /* PowerPC 405 F6 */
80d11f44 7378 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7379#endif
7380 /* PowerPC 405 microcontrolers */
7381 /* PowerPC 405 CR */
80d11f44 7382 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7383 /* PowerPC 405 CRa */
80d11f44 7384 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7385 /* PowerPC 405 CRb */
80d11f44 7386 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7387 /* PowerPC 405 CRc */
80d11f44 7388 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7389 /* PowerPC 405 EP */
80d11f44 7390 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7391#if defined(TODO)
7392 /* PowerPC 405 EXr */
80d11f44 7393 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7394#endif
7395 /* PowerPC 405 EZ */
80d11f44 7396 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7397#if defined(TODO)
7398 /* PowerPC 405 FX */
80d11f44 7399 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7400#endif
7401 /* PowerPC 405 GP */
80d11f44 7402 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7403 /* PowerPC 405 GPa */
80d11f44 7404 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7405 /* PowerPC 405 GPb */
80d11f44 7406 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7407 /* PowerPC 405 GPc */
80d11f44 7408 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7409 /* PowerPC 405 GPd */
80d11f44 7410 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7411 /* PowerPC 405 GPe */
80d11f44 7412 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7413 /* PowerPC 405 GPR */
80d11f44 7414 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7415#if defined(TODO)
7416 /* PowerPC 405 H */
80d11f44 7417 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7418#endif
7419#if defined(TODO)
7420 /* PowerPC 405 L */
80d11f44 7421 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7422#endif
7423 /* PowerPC 405 LP */
80d11f44 7424 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7425#if defined(TODO)
7426 /* PowerPC 405 PM */
80d11f44 7427 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7428#endif
7429#if defined(TODO)
7430 /* PowerPC 405 PS */
80d11f44 7431 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7432#endif
7433#if defined(TODO)
7434 /* PowerPC 405 S */
80d11f44 7435 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7436#endif
7437 /* Npe405 H */
80d11f44 7438 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7439 /* Npe405 H2 */
80d11f44 7440 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7441 /* Npe405 L */
80d11f44 7442 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7443 /* Npe4GS3 */
80d11f44 7444 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7445#if defined (TODO)
80d11f44 7446 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7447#endif
7448#if defined (TODO)
80d11f44 7449 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7450#endif
7451#if defined (TODO)
7452 /* PowerPC LC77700 (Sanyo) */
80d11f44 7453 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7454#endif
7455 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7456#if defined (TODO)
7457 /* STB010000 */
80d11f44 7458 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7459#endif
7460#if defined (TODO)
7461 /* STB01010 */
80d11f44 7462 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7463#endif
7464#if defined (TODO)
7465 /* STB0210 */
80d11f44 7466 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7467#endif
7468 /* STB03xx */
80d11f44 7469 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7470#if defined (TODO)
7471 /* STB043x */
80d11f44 7472 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7473#endif
7474#if defined (TODO)
7475 /* STB045x */
80d11f44 7476 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7477#endif
7478 /* STB04xx */
80d11f44 7479 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7480 /* STB25xx */
80d11f44 7481 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7482#if defined (TODO)
7483 /* STB130 */
80d11f44 7484 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7485#endif
7486 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7487 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7488 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7489 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7490 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7491#if defined (TODO)
7492 /* Zarlink ZL10310 */
80d11f44 7493 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7494#endif
7495#if defined (TODO)
7496 /* Zarlink ZL10311 */
80d11f44 7497 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7498#endif
7499#if defined (TODO)
7500 /* Zarlink ZL10320 */
80d11f44 7501 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7502#endif
7503#if defined (TODO)
7504 /* Zarlink ZL10321 */
80d11f44 7505 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7506#endif
7507 /* PowerPC 440 family */
80d11f44 7508#if defined(TODO_USER_ONLY)
a750fc0b 7509 /* Generic PowerPC 440 */
80d11f44
JM		 7510 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7511#endif
a750fc0b
JM		 7512 /* PowerPC 440 cores */
7513#if defined (TODO)
7514 /* PowerPC 440 A4 */
80d11f44 7515 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b 7516#endif
95070372
EI		 7517 /* PowerPC 440 Xilinx 5 */
7518 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
a750fc0b
JM		 7519#if defined (TODO)
7520 /* PowerPC 440 A5 */
80d11f44 7521 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7522#endif
7523#if defined (TODO)
7524 /* PowerPC 440 B4 */
80d11f44 7525 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7526#endif
7527#if defined (TODO)
7528 /* PowerPC 440 G4 */
80d11f44 7529 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7530#endif
7531#if defined (TODO)
7532 /* PowerPC 440 F5 */
80d11f44 7533 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7534#endif
7535#if defined (TODO)
7536 /* PowerPC 440 G5 */
80d11f44 7537 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7538#endif
7539#if defined (TODO)
7540 /* PowerPC 440H4 */
80d11f44 7541 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7542#endif
7543#if defined (TODO)
7544 /* PowerPC 440H6 */
80d11f44 7545 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7546#endif
7547 /* PowerPC 440 microcontrolers */
80d11f44 7548#if defined(TODO_USER_ONLY)
a750fc0b 7549 /* PowerPC 440 EP */
80d11f44
JM		 7550 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7551#endif
7552#if defined(TODO_USER_ONLY)
a750fc0b 7553 /* PowerPC 440 EPa */
80d11f44
JM		 7554 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7555#endif
7556#if defined(TODO_USER_ONLY)
a750fc0b 7557 /* PowerPC 440 EPb */
80d11f44
JM		 7558 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7559#endif
7560#if defined(TODO_USER_ONLY)
a750fc0b 7561 /* PowerPC 440 EPX */
80d11f44
JM		 7562 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7563#endif
7564#if defined(TODO_USER_ONLY)
a750fc0b 7565 /* PowerPC 440 GP */
80d11f44
JM		 7566 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7567#endif
7568#if defined(TODO_USER_ONLY)
a750fc0b 7569 /* PowerPC 440 GPb */
80d11f44
JM		 7570 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7571#endif
7572#if defined(TODO_USER_ONLY)
a750fc0b 7573 /* PowerPC 440 GPc */
80d11f44
JM		 7574 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7575#endif
7576#if defined(TODO_USER_ONLY)
a750fc0b 7577 /* PowerPC 440 GR */
80d11f44
JM		 7578 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7579#endif
7580#if defined(TODO_USER_ONLY)
a750fc0b 7581 /* PowerPC 440 GRa */
80d11f44
JM		 7582 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7583#endif
7584#if defined(TODO_USER_ONLY)
a750fc0b 7585 /* PowerPC 440 GRX */
80d11f44
JM		 7586 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7587#endif
7588#if defined(TODO_USER_ONLY)
a750fc0b 7589 /* PowerPC 440 GX */
80d11f44
JM		 7590 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7591#endif
7592#if defined(TODO_USER_ONLY)
a750fc0b 7593 /* PowerPC 440 GXa */
80d11f44
JM		 7594 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7595#endif
7596#if defined(TODO_USER_ONLY)
a750fc0b 7597 /* PowerPC 440 GXb */
80d11f44
JM		 7598 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7599#endif
7600#if defined(TODO_USER_ONLY)
a750fc0b 7601 /* PowerPC 440 GXc */
80d11f44
JM		 7602 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7603#endif
7604#if defined(TODO_USER_ONLY)
a750fc0b 7605 /* PowerPC 440 GXf */
80d11f44
JM		 7606 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7607#endif
a750fc0b
JM		 7608#if defined(TODO)
7609 /* PowerPC 440 S */
80d11f44 7610 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7611#endif
80d11f44 7612#if defined(TODO_USER_ONLY)
a750fc0b 7613 /* PowerPC 440 SP */
80d11f44
JM		 7614 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7615#endif
7616#if defined(TODO_USER_ONLY)
a750fc0b 7617 /* PowerPC 440 SP2 */
80d11f44
JM		 7618 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7619#endif
7620#if defined(TODO_USER_ONLY)
a750fc0b 7621 /* PowerPC 440 SPE */
80d11f44
JM		 7622 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7623#endif
a750fc0b
JM		 7624 /* PowerPC 460 family */
7625#if defined (TODO)
7626 /* Generic PowerPC 464 */
80d11f44 7627 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7628#endif
7629 /* PowerPC 464 microcontrolers */
7630#if defined (TODO)
7631 /* PowerPC 464H90 */
80d11f44 7632 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7633#endif
7634#if defined (TODO)
7635 /* PowerPC 464H90F */
80d11f44 7636 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7637#endif
7638 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7639 /* MPC5xx family (aka RCPU) */
7640#if defined(TODO_USER_ONLY)
7641 /* Generic MPC5xx core */
7642 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7643#endif
7644#if defined(TODO_USER_ONLY)
7645 /* Codename for MPC5xx core */
7646 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7647#endif
7648 /* MPC5xx microcontrollers */
7649#if defined(TODO_USER_ONLY)
7650 /* MGT560 */
7651 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7652#endif
7653#if defined(TODO_USER_ONLY)
7654 /* MPC509 */
7655 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7656#endif
7657#if defined(TODO_USER_ONLY)
7658 /* MPC533 */
7659 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7660#endif
7661#if defined(TODO_USER_ONLY)
7662 /* MPC534 */
7663 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7664#endif
7665#if defined(TODO_USER_ONLY)
7666 /* MPC555 */
7667 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7668#endif
7669#if defined(TODO_USER_ONLY)
7670 /* MPC556 */
7671 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7672#endif
7673#if defined(TODO_USER_ONLY)
7674 /* MPC560 */
7675 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7676#endif
7677#if defined(TODO_USER_ONLY)
7678 /* MPC561 */
7679 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7680#endif
7681#if defined(TODO_USER_ONLY)
7682 /* MPC562 */
7683 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7684#endif
7685#if defined(TODO_USER_ONLY)
7686 /* MPC563 */
7687 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7688#endif
7689#if defined(TODO_USER_ONLY)
7690 /* MPC564 */
7691 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7692#endif
7693#if defined(TODO_USER_ONLY)
7694 /* MPC565 */
7695 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7696#endif
7697#if defined(TODO_USER_ONLY)
7698 /* MPC566 */
7699 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7700#endif
7701 /* MPC8xx family (aka PowerQUICC) */
7702#if defined(TODO_USER_ONLY)
7703 /* Generic MPC8xx core */
7704 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7705#endif
7706#if defined(TODO_USER_ONLY)
7707 /* Codename for MPC8xx core */
7708 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7709#endif
7710 /* MPC8xx microcontrollers */
7711#if defined(TODO_USER_ONLY)
7712 /* MGT823 */
7713 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7714#endif
7715#if defined(TODO_USER_ONLY)
7716 /* MPC821 */
7717 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7718#endif
7719#if defined(TODO_USER_ONLY)
7720 /* MPC823 */
7721 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7722#endif
7723#if defined(TODO_USER_ONLY)
7724 /* MPC850 */
7725 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7726#endif
7727#if defined(TODO_USER_ONLY)
7728 /* MPC852T */
7729 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7730#endif
7731#if defined(TODO_USER_ONLY)
7732 /* MPC855T */
7733 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7734#endif
7735#if defined(TODO_USER_ONLY)
7736 /* MPC857 */
7737 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7738#endif
7739#if defined(TODO_USER_ONLY)
7740 /* MPC859 */
7741 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7742#endif
7743#if defined(TODO_USER_ONLY)
7744 /* MPC860 */
7745 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7746#endif
7747#if defined(TODO_USER_ONLY)
7748 /* MPC862 */
7749 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7750#endif
7751#if defined(TODO_USER_ONLY)
7752 /* MPC866 */
7753 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7754#endif
7755#if defined(TODO_USER_ONLY)
7756 /* MPC870 */
7757 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7758#endif
7759#if defined(TODO_USER_ONLY)
7760 /* MPC875 */
7761 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7762#endif
7763#if defined(TODO_USER_ONLY)
7764 /* MPC880 */
7765 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7766#endif
7767#if defined(TODO_USER_ONLY)
7768 /* MPC885 */
7769 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7770#endif
7771 /* MPC82xx family (aka PowerQUICC-II) */
7772 /* Generic MPC52xx core */
7773 POWERPC_DEF_SVR("MPC52xx",
7774 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7775 /* Generic MPC82xx core */
7776 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7777 /* Codename for MPC82xx */
7778 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7779 /* PowerPC G2 core */
7780 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7781 /* PowerPC G2 H4 core */
7782 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7783 /* PowerPC G2 GP core */
7784 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7785 /* PowerPC G2 LS core */
7786 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7787 /* PowerPC G2 HiP3 core */
7788 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7789 /* PowerPC G2 HiP4 core */
7790 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7791 /* PowerPC MPC603 core */
7792 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7793 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7794 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7795 /* PowerPC G2LE GP core */
7796 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7797 /* PowerPC G2LE LS core */
7798 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7799 /* PowerPC G2LE GP1 core */
7800 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7801 /* PowerPC G2LE GP3 core */
7802 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7803 /* PowerPC MPC603 microcontrollers */
7804 /* MPC8240 */
7805 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7806 /* PowerPC G2 microcontrollers */
082c6681 7807#if defined(TODO)
80d11f44
JM		 7808 /* MPC5121 */
7809 POWERPC_DEF_SVR("MPC5121",
7810 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7811#endif
7812 /* MPC5200 */
7813 POWERPC_DEF_SVR("MPC5200",
7814 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7815 /* MPC5200 v1.0 */
7816 POWERPC_DEF_SVR("MPC5200_v10",
7817 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7818 /* MPC5200 v1.1 */
7819 POWERPC_DEF_SVR("MPC5200_v11",
7820 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7821 /* MPC5200 v1.2 */
7822 POWERPC_DEF_SVR("MPC5200_v12",
7823 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7824 /* MPC5200B */
7825 POWERPC_DEF_SVR("MPC5200B",
7826 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7827 /* MPC5200B v2.0 */
7828 POWERPC_DEF_SVR("MPC5200B_v20",
7829 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7830 /* MPC5200B v2.1 */
7831 POWERPC_DEF_SVR("MPC5200B_v21",
7832 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7833 /* MPC8241 */
7834 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7835 /* MPC8245 */
7836 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7837 /* MPC8247 */
7838 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7839 /* MPC8248 */
7840 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7841 /* MPC8250 */
7842 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7843 /* MPC8250 HiP3 */
7844 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7845 /* MPC8250 HiP4 */
7846 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7847 /* MPC8255 */
7848 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7849 /* MPC8255 HiP3 */
7850 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7851 /* MPC8255 HiP4 */
7852 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7853 /* MPC8260 */
7854 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7855 /* MPC8260 HiP3 */
7856 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7857 /* MPC8260 HiP4 */
7858 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7859 /* MPC8264 */
7860 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7861 /* MPC8264 HiP3 */
7862 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7863 /* MPC8264 HiP4 */
7864 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7865 /* MPC8265 */
7866 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7867 /* MPC8265 HiP3 */
7868 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7869 /* MPC8265 HiP4 */
7870 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7871 /* MPC8266 */
7872 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7873 /* MPC8266 HiP3 */
7874 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7875 /* MPC8266 HiP4 */
7876 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7877 /* MPC8270 */
7878 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7879 /* MPC8271 */
7880 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7881 /* MPC8272 */
7882 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7883 /* MPC8275 */
7884 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7885 /* MPC8280 */
7886 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 7887 /* e200 family */
a750fc0b 7888 /* Generic PowerPC e200 core */
80d11f44
JM		 7889 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7890 /* Generic MPC55xx core */
7891#if defined (TODO)
7892 POWERPC_DEF_SVR("MPC55xx",
7893 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 7894#endif
7895#if defined (TODO)
80d11f44
JM		 7896 /* PowerPC e200z0 core */
7897 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 7898#endif
7899#if defined (TODO)
80d11f44
JM		 7900 /* PowerPC e200z1 core */
7901 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7902#endif
7903#if defined (TODO)
7904 /* PowerPC e200z3 core */
7905 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7906#endif
7907 /* PowerPC e200z5 core */
7908 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 7909 /* PowerPC e200z6 core */
80d11f44
JM		 7910 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7911 /* PowerPC e200 microcontrollers */
7912#if defined (TODO)
7913 /* MPC5514E */
7914 POWERPC_DEF_SVR("MPC5514E",
7915 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 7916#endif
a750fc0b 7917#if defined (TODO)
80d11f44
JM		 7918 /* MPC5514E v0 */
7919 POWERPC_DEF_SVR("MPC5514E_v0",
7920 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 7921#endif
7922#if defined (TODO)
80d11f44
JM		 7923 /* MPC5514E v1 */
7924 POWERPC_DEF_SVR("MPC5514E_v1",
7925 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 7926#endif
7927#if defined (TODO)
80d11f44
JM		 7928 /* MPC5514G */
7929 POWERPC_DEF_SVR("MPC5514G",
7930 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 7931#endif
7932#if defined (TODO)
80d11f44
JM		 7933 /* MPC5514G v0 */
7934 POWERPC_DEF_SVR("MPC5514G_v0",
7935 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 7936#endif
a750fc0b 7937#if defined (TODO)
80d11f44
JM		 7938 /* MPC5514G v1 */
7939 POWERPC_DEF_SVR("MPC5514G_v1",
7940 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 7941#endif
7942#if defined (TODO)
80d11f44
JM		 7943 /* MPC5515S */
7944 POWERPC_DEF_SVR("MPC5515S",
7945 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 7946#endif
7947#if defined (TODO)
80d11f44
JM		 7948 /* MPC5516E */
7949 POWERPC_DEF_SVR("MPC5516E",
7950 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 7951#endif
7952#if defined (TODO)
80d11f44
JM		 7953 /* MPC5516E v0 */
7954 POWERPC_DEF_SVR("MPC5516E_v0",
7955 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 7956#endif
7957#if defined (TODO)
80d11f44
JM		 7958 /* MPC5516E v1 */
7959 POWERPC_DEF_SVR("MPC5516E_v1",
7960 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 7961#endif
a750fc0b 7962#if defined (TODO)
80d11f44
JM		 7963 /* MPC5516G */
7964 POWERPC_DEF_SVR("MPC5516G",
7965 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 7966#endif
a750fc0b 7967#if defined (TODO)
80d11f44
JM		 7968 /* MPC5516G v0 */
7969 POWERPC_DEF_SVR("MPC5516G_v0",
7970 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 7971#endif
a750fc0b 7972#if defined (TODO)
80d11f44
JM		 7973 /* MPC5516G v1 */
7974 POWERPC_DEF_SVR("MPC5516G_v1",
7975 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 7976#endif
a750fc0b 7977#if defined (TODO)
80d11f44
JM		 7978 /* MPC5516S */
7979 POWERPC_DEF_SVR("MPC5516S",
7980 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 7981#endif
7982#if defined (TODO)
80d11f44
JM		 7983 /* MPC5533 */
7984 POWERPC_DEF_SVR("MPC5533",
7985 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 7986#endif
7987#if defined (TODO)
80d11f44
JM		 7988 /* MPC5534 */
7989 POWERPC_DEF_SVR("MPC5534",
7990 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 7991#endif
80d11f44
JM		 7992#if defined (TODO)
7993 /* MPC5553 */
7994 POWERPC_DEF_SVR("MPC5553",
7995 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7996#endif
7997#if defined (TODO)
7998 /* MPC5554 */
7999 POWERPC_DEF_SVR("MPC5554",
8000 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8001#endif
8002#if defined (TODO)
8003 /* MPC5561 */
8004 POWERPC_DEF_SVR("MPC5561",
8005 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8006#endif
8007#if defined (TODO)
8008 /* MPC5565 */
8009 POWERPC_DEF_SVR("MPC5565",
8010 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8011#endif
8012#if defined (TODO)
8013 /* MPC5566 */
8014 POWERPC_DEF_SVR("MPC5566",
8015 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8016#endif
8017#if defined (TODO)
8018 /* MPC5567 */
8019 POWERPC_DEF_SVR("MPC5567",
8020 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8021#endif
8022 /* e300 family */
8023 /* Generic PowerPC e300 core */
8024 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8025 /* PowerPC e300c1 core */
8026 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8027 /* PowerPC e300c2 core */
8028 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8029 /* PowerPC e300c3 core */
8030 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8031 /* PowerPC e300c4 core */
8032 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8033 /* PowerPC e300 microcontrollers */
8034#if defined (TODO)
8035 /* MPC8313 */
8036 POWERPC_DEF_SVR("MPC8313",
74d77cae 8037 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
80d11f44
JM		 8038#endif
8039#if defined (TODO)
8040 /* MPC8313E */
8041 POWERPC_DEF_SVR("MPC8313E",
74d77cae 8042 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
80d11f44
JM		 8043#endif
8044#if defined (TODO)
8045 /* MPC8314 */
8046 POWERPC_DEF_SVR("MPC8314",
74d77cae 8047 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
80d11f44
JM		 8048#endif
8049#if defined (TODO)
8050 /* MPC8314E */
8051 POWERPC_DEF_SVR("MPC8314E",
74d77cae 8052 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
80d11f44
JM		 8053#endif
8054#if defined (TODO)
8055 /* MPC8315 */
8056 POWERPC_DEF_SVR("MPC8315",
74d77cae 8057 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
80d11f44
JM		 8058#endif
8059#if defined (TODO)
8060 /* MPC8315E */
8061 POWERPC_DEF_SVR("MPC8315E",
74d77cae 8062 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
80d11f44
JM		 8063#endif
8064#if defined (TODO)
8065 /* MPC8321 */
8066 POWERPC_DEF_SVR("MPC8321",
74d77cae 8067 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
80d11f44
JM		 8068#endif
8069#if defined (TODO)
8070 /* MPC8321E */
8071 POWERPC_DEF_SVR("MPC8321E",
74d77cae 8072 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
80d11f44
JM		 8073#endif
8074#if defined (TODO)
8075 /* MPC8323 */
8076 POWERPC_DEF_SVR("MPC8323",
74d77cae 8077 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
80d11f44
JM		 8078#endif
8079#if defined (TODO)
8080 /* MPC8323E */
8081 POWERPC_DEF_SVR("MPC8323E",
74d77cae 8082 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
80d11f44 8083#endif
492d7bf5
TM		 8084 /* MPC8343 */
8085 POWERPC_DEF_SVR("MPC8343",
74d77cae 8086 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
80d11f44
JM		 8087 /* MPC8343A */
8088 POWERPC_DEF_SVR("MPC8343A",
74d77cae 8089 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
492d7bf5
TM		 8090 /* MPC8343E */
8091 POWERPC_DEF_SVR("MPC8343E",
74d77cae 8092 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
80d11f44
JM		 8093 /* MPC8343EA */
8094 POWERPC_DEF_SVR("MPC8343EA",
74d77cae 8095 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
492d7bf5
TM		 8096 /* MPC8347 */
8097 POWERPC_DEF_SVR("MPC8347",
74d77cae 8098 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
492d7bf5
TM		 8099 /* MPC8347T */
8100 POWERPC_DEF_SVR("MPC8347T",
74d77cae 8101 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
492d7bf5
TM		 8102 /* MPC8347P */
8103 POWERPC_DEF_SVR("MPC8347P",
74d77cae 8104 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
80d11f44
JM		 8105 /* MPC8347A */
8106 POWERPC_DEF_SVR("MPC8347A",
74d77cae 8107 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
80d11f44
JM		 8108 /* MPC8347AT */
8109 POWERPC_DEF_SVR("MPC8347AT",
74d77cae 8110 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
80d11f44
JM		 8111 /* MPC8347AP */
8112 POWERPC_DEF_SVR("MPC8347AP",
74d77cae 8113 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
492d7bf5
TM		 8114 /* MPC8347E */
8115 POWERPC_DEF_SVR("MPC8347E",
74d77cae 8116 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
492d7bf5
TM		 8117 /* MPC8347ET */
8118 POWERPC_DEF_SVR("MPC8347ET",
74d77cae 8119 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
492d7bf5
TM		 8120 /* MPC8343EP */
8121 POWERPC_DEF_SVR("MPC8347EP",
74d77cae 8122 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
80d11f44
JM		 8123 /* MPC8347EA */
8124 POWERPC_DEF_SVR("MPC8347EA",
74d77cae 8125 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
80d11f44
JM		 8126 /* MPC8347EAT */
8127 POWERPC_DEF_SVR("MPC8347EAT",
74d77cae 8128 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
80d11f44
JM		 8129 /* MPC8343EAP */
8130 POWERPC_DEF_SVR("MPC8347EAP",
74d77cae 8131 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
80d11f44
JM		 8132 /* MPC8349 */
8133 POWERPC_DEF_SVR("MPC8349",
74d77cae 8134 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
80d11f44
JM		 8135 /* MPC8349A */
8136 POWERPC_DEF_SVR("MPC8349A",
74d77cae 8137 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
80d11f44
JM		 8138 /* MPC8349E */
8139 POWERPC_DEF_SVR("MPC8349E",
74d77cae 8140 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
80d11f44
JM		 8141 /* MPC8349EA */
8142 POWERPC_DEF_SVR("MPC8349EA",
74d77cae 8143 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
80d11f44
JM		 8144#if defined (TODO)
8145 /* MPC8358E */
8146 POWERPC_DEF_SVR("MPC8358E",
74d77cae 8147 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
80d11f44
JM		 8148#endif
8149#if defined (TODO)
8150 /* MPC8360E */
8151 POWERPC_DEF_SVR("MPC8360E",
74d77cae 8152 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
80d11f44
JM		 8153#endif
8154 /* MPC8377 */
8155 POWERPC_DEF_SVR("MPC8377",
74d77cae 8156 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
80d11f44
JM		 8157 /* MPC8377E */
8158 POWERPC_DEF_SVR("MPC8377E",
74d77cae 8159 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
80d11f44
JM		 8160 /* MPC8378 */
8161 POWERPC_DEF_SVR("MPC8378",
74d77cae 8162 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
80d11f44
JM		 8163 /* MPC8378E */
8164 POWERPC_DEF_SVR("MPC8378E",
74d77cae 8165 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
80d11f44
JM		 8166 /* MPC8379 */
8167 POWERPC_DEF_SVR("MPC8379",
74d77cae 8168 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
80d11f44
JM		 8169 /* MPC8379E */
8170 POWERPC_DEF_SVR("MPC8379E",
74d77cae 8171 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
80d11f44
JM		 8172 /* e500 family */
8173 /* PowerPC e500 core */
bd5ea513
AJ		 8174 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8175 /* PowerPC e500v1 core */
8176 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8177 /* PowerPC e500 v1.0 core */
bd5ea513 8178 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8179 /* PowerPC e500 v2.0 core */
bd5ea513 8180 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8181 /* PowerPC e500v2 core */
bd5ea513 8182 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8183 /* PowerPC e500v2 v1.0 core */
bd5ea513 8184 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8185 /* PowerPC e500v2 v2.0 core */
bd5ea513 8186 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8187 /* PowerPC e500v2 v2.1 core */
bd5ea513 8188 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8189 /* PowerPC e500v2 v2.2 core */
bd5ea513 8190 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8191 /* PowerPC e500v2 v3.0 core */
bd5ea513 8192 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
80d11f44
JM		 8193 /* PowerPC e500 microcontrollers */
8194 /* MPC8533 */
8195 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8196 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8197 /* MPC8533 v1.0 */
8198 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8199 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8200 /* MPC8533 v1.1 */
8201 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8202 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8203 /* MPC8533E */
8204 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8205 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8206 /* MPC8533E v1.0 */
8207 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8208 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8209 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8210 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8211 /* MPC8540 */
8212 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8213 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8214 /* MPC8540 v1.0 */
8215 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8216 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8217 /* MPC8540 v2.0 */
8218 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8219 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8220 /* MPC8540 v2.1 */
8221 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8222 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8223 /* MPC8541 */
8224 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8225 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8226 /* MPC8541 v1.0 */
8227 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8228 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8229 /* MPC8541 v1.1 */
8230 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8231 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8232 /* MPC8541E */
8233 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8234 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8235 /* MPC8541E v1.0 */
8236 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8237 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8238 /* MPC8541E v1.1 */
8239 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8240 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8241 /* MPC8543 */
8242 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8243 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8244 /* MPC8543 v1.0 */
8245 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8246 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8247 /* MPC8543 v1.1 */
8248 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8249 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8250 /* MPC8543 v2.0 */
8251 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8252 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8253 /* MPC8543 v2.1 */
8254 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8255 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8256 /* MPC8543E */
8257 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8258 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8259 /* MPC8543E v1.0 */
8260 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8261 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8262 /* MPC8543E v1.1 */
8263 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8264 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8265 /* MPC8543E v2.0 */
8266 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8267 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8268 /* MPC8543E v2.1 */
8269 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8270 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8271 /* MPC8544 */
8272 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8273 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8274 /* MPC8544 v1.0 */
8275 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8276 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8277 /* MPC8544 v1.1 */
8278 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8279 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8280 /* MPC8544E */
8281 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8282 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8283 /* MPC8544E v1.0 */
8284 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8285 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8286 /* MPC8544E v1.1 */
8287 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8288 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8289 /* MPC8545 */
8290 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8291 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8292 /* MPC8545 v2.0 */
8293 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8294 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8295 /* MPC8545 v2.1 */
8296 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8297 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8298 /* MPC8545E */
8299 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8300 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8301 /* MPC8545E v2.0 */
8302 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8303 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8304 /* MPC8545E v2.1 */
8305 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8306 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8307 /* MPC8547E */
8308 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8309 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8310 /* MPC8547E v2.0 */
8311 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8312 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8313 /* MPC8547E v2.1 */
8314 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8315 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8316 /* MPC8548 */
8317 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8318 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8319 /* MPC8548 v1.0 */
8320 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8321 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8322 /* MPC8548 v1.1 */
8323 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8324 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8325 /* MPC8548 v2.0 */
8326 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8327 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8328 /* MPC8548 v2.1 */
8329 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8330 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8331 /* MPC8548E */
8332 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8333 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8334 /* MPC8548E v1.0 */
8335 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8336 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8337 /* MPC8548E v1.1 */
8338 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8339 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8340 /* MPC8548E v2.0 */
8341 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8342 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8343 /* MPC8548E v2.1 */
8344 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8345 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8346 /* MPC8555 */
8347 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8348 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8349 /* MPC8555 v1.0 */
8350 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8351 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8352 /* MPC8555 v1.1 */
8353 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8354 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8355 /* MPC8555E */
8356 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8357 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8358 /* MPC8555E v1.0 */
8359 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8360 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8361 /* MPC8555E v1.1 */
8362 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8363 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8364 /* MPC8560 */
8365 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8366 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8367 /* MPC8560 v1.0 */
8368 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8369 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8370 /* MPC8560 v2.0 */
8371 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8372 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8373 /* MPC8560 v2.1 */
8374 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8375 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8376 /* MPC8567 */
8377 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8378 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8379 /* MPC8567E */
8380 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8381 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8382 /* MPC8568 */
8383 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8384 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8385 /* MPC8568E */
8386 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8387 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8388 /* MPC8572 */
8389 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8390 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8391 /* MPC8572E */
8392 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8393 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8394 /* e600 family */
8395 /* PowerPC e600 core */
8396 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8397 /* PowerPC e600 microcontrollers */
8398#if defined (TODO)
8399 /* MPC8610 */
8400 POWERPC_DEF_SVR("MPC8610",
8401 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8402#endif
8403 /* MPC8641 */
8404 POWERPC_DEF_SVR("MPC8641",
8405 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8406 /* MPC8641D */
8407 POWERPC_DEF_SVR("MPC8641D",
8408 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8409 /* 32 bits "classic" PowerPC */
8410 /* PowerPC 6xx family */
8411 /* PowerPC 601 */
bd928eba 8412 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8413 /* PowerPC 601v0 */
082c6681 8414 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8415 /* PowerPC 601v1 */
082c6681
JM		 8416 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8417 /* PowerPC 601v */
bd928eba 8418 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8419 /* PowerPC 601v2 */
082c6681 8420 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8421 /* PowerPC 602 */
80d11f44 8422 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8423 /* PowerPC 603 */
80d11f44 8424 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8425 /* Code name for PowerPC 603 */
80d11f44 8426 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8427 /* PowerPC 603e (aka PID6) */
80d11f44 8428 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8429 /* Code name for PowerPC 603e */
80d11f44 8430 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8431 /* PowerPC 603e v1.1 */
80d11f44 8432 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8433 /* PowerPC 603e v1.2 */
80d11f44 8434 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8435 /* PowerPC 603e v1.3 */
80d11f44 8436 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8437 /* PowerPC 603e v1.4 */
80d11f44 8438 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8439 /* PowerPC 603e v2.2 */
80d11f44 8440 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8441 /* PowerPC 603e v3 */
80d11f44 8442 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8443 /* PowerPC 603e v4 */
80d11f44 8444 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8445 /* PowerPC 603e v4.1 */
80d11f44 8446 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8447 /* PowerPC 603e (aka PID7) */
80d11f44 8448 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8449 /* PowerPC 603e7t */
80d11f44 8450 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8451 /* PowerPC 603e7v */
80d11f44 8452 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8453 /* Code name for PowerPC 603ev */
80d11f44 8454 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8455 /* PowerPC 603e7v1 */
80d11f44 8456 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8457 /* PowerPC 603e7v2 */
80d11f44 8458 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8459 /* PowerPC 603p (aka PID7v) */
8460 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8461 /* PowerPC 603r (aka PID7t) */
80d11f44 8462 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8463 /* Code name for PowerPC 603r */
80d11f44 8464 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8465 /* PowerPC 604 */
80d11f44 8466 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8467 /* PowerPC 604e (aka PID9) */
8468 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8469 /* Code name for PowerPC 604e */
8470 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8471 /* PowerPC 604e v1.0 */
082c6681 8472 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8473 /* PowerPC 604e v2.2 */
082c6681 8474 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8475 /* PowerPC 604e v2.4 */
082c6681
JM		 8476 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8477 /* PowerPC 604r (aka PIDA) */
8478 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8479 /* Code name for PowerPC 604r */
8480 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8481#if defined(TODO)
8482 /* PowerPC 604ev */
082c6681 8483 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8484#endif
8485 /* PowerPC 7xx family */
8486 /* Generic PowerPC 740 (G3) */
bd928eba 8487 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8488 /* Code name for PowerPC 740 */
bd928eba 8489 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8490 /* Generic PowerPC 750 (G3) */
bd928eba 8491 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8492 /* Code name for PowerPC 750 */
bd928eba 8493 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8494 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8495 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8496 /* PowerPC 740 v1.0 (G3) */
8497 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8498 /* PowerPC 750 v1.0 (G3) */
8499 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8500 /* PowerPC 740 v2.0 (G3) */
bd928eba 8501 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8502 /* PowerPC 750 v2.0 (G3) */
bd928eba 8503 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8504 /* PowerPC 740 v2.1 (G3) */
bd928eba 8505 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8506 /* PowerPC 750 v2.1 (G3) */
bd928eba 8507 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8508 /* PowerPC 740 v2.2 (G3) */
bd928eba 8509 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8510 /* PowerPC 750 v2.2 (G3) */
bd928eba 8511 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8512 /* PowerPC 740 v3.0 (G3) */
bd928eba 8513 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8514 /* PowerPC 750 v3.0 (G3) */
bd928eba 8515 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8516 /* PowerPC 740 v3.1 (G3) */
bd928eba 8517 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8518 /* PowerPC 750 v3.1 (G3) */
bd928eba 8519 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8520 /* PowerPC 740E (G3) */
bd928eba
JM		 8521 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8522 /* PowerPC 750E (G3) */
8523 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8524 /* PowerPC 740P (G3) */
bd928eba 8525 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8526 /* PowerPC 750P (G3) */
bd928eba 8527 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8528 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8529 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8530 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8531 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8532 /* PowerPC 750CL v1.0 */
8533 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8534 /* PowerPC 750CL v2.0 */
8535 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8536 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8537 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8538 /* PowerPC 750CX v1.0 (G3 embedded) */
8539 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8540 /* PowerPC 750CX v2.1 (G3 embedded) */
8541 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8542 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8543 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8544 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8545 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8546 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8547 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8548 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8549 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8550 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8551 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8552 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8553 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8554 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8555 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8556 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8557 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8558 /* PowerPC 750CXe v3.0 (G3 embedded) */
8559 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8560 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8561 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8562 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8563 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8564 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8565 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8566 /* PowerPC 750FL (G3 embedded) */
80d11f44 8567 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8568 /* PowerPC 750FX (G3 embedded) */
80d11f44 8569 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8570 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8571 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8572 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8573 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8574 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8575 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8576 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8577 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8578 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8579 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8580 /* PowerPC 750GL (G3 embedded) */
bd928eba 8581 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8582 /* PowerPC 750GX (G3 embedded) */
bd928eba 8583 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8584 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8585 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8586 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8587 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8588 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8589 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8590 /* PowerPC 750L (G3 embedded) */
bd928eba 8591 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8592 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8593 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8594 /* PowerPC 750L v2.0 (G3 embedded) */
8595 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8596 /* PowerPC 750L v2.1 (G3 embedded) */
8597 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8598 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8599 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8600 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8601 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8602 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8603 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8604 /* Generic PowerPC 745 */
bd928eba 8605 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8606 /* Generic PowerPC 755 */
bd928eba 8607 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8608 /* Code name for PowerPC 745/755 */
bd928eba 8609 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8610 /* PowerPC 745 v1.0 */
bd928eba 8611 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8612 /* PowerPC 755 v1.0 */
bd928eba 8613 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8614 /* PowerPC 745 v1.1 */
bd928eba 8615 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8616 /* PowerPC 755 v1.1 */
bd928eba 8617 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8618 /* PowerPC 745 v2.0 */
bd928eba 8619 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8620 /* PowerPC 755 v2.0 */
bd928eba 8621 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8622 /* PowerPC 745 v2.1 */
bd928eba 8623 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8624 /* PowerPC 755 v2.1 */
bd928eba 8625 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8626 /* PowerPC 745 v2.2 */
bd928eba 8627 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8628 /* PowerPC 755 v2.2 */
bd928eba 8629 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8630 /* PowerPC 745 v2.3 */
bd928eba 8631 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8632 /* PowerPC 755 v2.3 */
bd928eba 8633 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8634 /* PowerPC 745 v2.4 */
bd928eba 8635 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8636 /* PowerPC 755 v2.4 */
bd928eba 8637 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8638 /* PowerPC 745 v2.5 */
bd928eba 8639 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8640 /* PowerPC 755 v2.5 */
bd928eba 8641 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8642 /* PowerPC 745 v2.6 */
bd928eba 8643 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8644 /* PowerPC 755 v2.6 */
bd928eba 8645 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8646 /* PowerPC 745 v2.7 */
bd928eba 8647 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8648 /* PowerPC 755 v2.7 */
bd928eba 8649 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8650 /* PowerPC 745 v2.8 */
bd928eba 8651 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8652 /* PowerPC 755 v2.8 */
bd928eba 8653 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8654#if defined (TODO)
8655 /* PowerPC 745P (G3) */
bd928eba 8656 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8657 /* PowerPC 755P (G3) */
bd928eba 8658 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8659#endif
8660 /* PowerPC 74xx family */
8661 /* PowerPC 7400 (G4) */
80d11f44 8662 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8663 /* Code name for PowerPC 7400 */
80d11f44 8664 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8665 /* PowerPC 74xx is also well known as G4 */
80d11f44 8666 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8667 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8668 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8669 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8670 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8671 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8672 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8673 /* PowerPC 7400 v2.1 (G4) */
8674 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8675 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8676 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8677 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8678 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8679 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8680 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8681 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8682 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8683 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8684 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8685 /* PowerPC 7410 (G4) */
80d11f44 8686 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8687 /* Code name for PowerPC 7410 */
80d11f44 8688 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8689 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8690 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8691 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8692 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8693 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8694 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8695 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8696 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8697 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8698 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8699 /* PowerPC 7448 (G4) */
80d11f44 8700 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8701 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8702 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8703 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8704 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8705 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8706 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8707 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8708 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8709 /* PowerPC 7450 (G4) */
80d11f44 8710 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8711 /* Code name for PowerPC 7450 */
80d11f44 8712 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8713 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8714 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8715 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8716 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8717 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8718 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8719 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8720 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8721 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8722 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8723 /* PowerPC 7441 (G4) */
80d11f44 8724 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8725 /* PowerPC 7451 (G4) */
80d11f44 8726 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8727 /* PowerPC 7441 v2.1 (G4) */
8728 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8729 /* PowerPC 7441 v2.3 (G4) */
8730 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8731 /* PowerPC 7451 v2.3 (G4) */
8732 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8733 /* PowerPC 7441 v2.10 (G4) */
8734 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8735 /* PowerPC 7451 v2.10 (G4) */
8736 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8737 /* PowerPC 7445 (G4) */
80d11f44 8738 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8739 /* PowerPC 7455 (G4) */
80d11f44 8740 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8741 /* Code name for PowerPC 7445/7455 */
80d11f44 8742 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8743 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8744 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8745 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8746 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8747 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8748 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8749 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8750 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8751 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8752 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8753 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8754 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8755 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8756 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8757 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8758 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8759 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8760 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8761 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8762 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8763 /* PowerPC 7447 (G4) */
80d11f44 8764 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8765 /* PowerPC 7457 (G4) */
80d11f44 8766 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 8767 /* Code name for PowerPC 7447/7457 */
80d11f44 8768 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 8769 /* PowerPC 7447 v1.0 (G4) */
80d11f44 8770 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 8771 /* PowerPC 7457 v1.0 (G4) */
80d11f44 8772 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 8773 /* PowerPC 7447 v1.1 (G4) */
80d11f44 8774 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 8775 /* PowerPC 7457 v1.1 (G4) */
80d11f44 8776 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 8777 /* PowerPC 7457 v1.2 (G4) */
80d11f44 8778 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 8779 /* PowerPC 7447A (G4) */
8780 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8781 /* PowerPC 7457A (G4) */
8782 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8783 /* PowerPC 7447A v1.0 (G4) */
8784 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8785 /* PowerPC 7457A v1.0 (G4) */
8786 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8787 /* Code name for PowerPC 7447A/7457A */
8788 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8789 /* PowerPC 7447A v1.1 (G4) */
8790 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8791 /* PowerPC 7457A v1.1 (G4) */
8792 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8793 /* PowerPC 7447A v1.2 (G4) */
8794 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8795 /* PowerPC 7457A v1.2 (G4) */
8796 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 8797 /* 64 bits PowerPC */
8798#if defined (TARGET_PPC64)
a750fc0b 8799 /* PowerPC 620 */
80d11f44 8800 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 8801 /* Code name for PowerPC 620 */
8802 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 8803#if defined (TODO)
a750fc0b 8804 /* PowerPC 630 (POWER3) */
80d11f44
JM		 8805 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8806 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 8807 /* Code names for POWER3 */
8808 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8809 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 8810#endif
3a607854 8811#if defined (TODO)
a750fc0b 8812 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 8813 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8814 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 8815#endif
8816#if defined (TODO)
a750fc0b 8817 /* POWER4 */
80d11f44 8818 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 8819#endif
3a607854 8820#if defined (TODO)
a750fc0b 8821 /* POWER4p */
80d11f44 8822 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 8823#endif
2662a059 8824#if defined (TODO)
a750fc0b 8825 /* POWER5 */
80d11f44 8826 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 8827 /* POWER5GR */
80d11f44 8828 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 8829#endif
3a607854 8830#if defined (TODO)
a750fc0b 8831 /* POWER5+ */
80d11f44 8832 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 8833 /* POWER5GS */
80d11f44 8834 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 8835#endif
2662a059 8836#if defined (TODO)
a750fc0b 8837 /* POWER6 */
80d11f44 8838 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 8839 /* POWER6 running in POWER5 mode */
80d11f44 8840 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 8841 /* POWER6A */
80d11f44 8842 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 8843#endif
a750fc0b 8844 /* PowerPC 970 */
80d11f44 8845 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 8846 /* PowerPC 970FX (G5) */
80d11f44 8847 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 8848 /* PowerPC 970FX v1.0 (G5) */
80d11f44 8849 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 8850 /* PowerPC 970FX v2.0 (G5) */
80d11f44 8851 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 8852 /* PowerPC 970FX v2.1 (G5) */
80d11f44 8853 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 8854 /* PowerPC 970FX v3.0 (G5) */
80d11f44 8855 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 8856 /* PowerPC 970FX v3.1 (G5) */
80d11f44 8857 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 8858 /* PowerPC 970GX (G5) */
80d11f44 8859 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 8860 /* PowerPC 970MP */
80d11f44 8861 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 8862 /* PowerPC 970MP v1.0 */
80d11f44 8863 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 8864 /* PowerPC 970MP v1.1 */
80d11f44 8865 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 8866#if defined (TODO)
a750fc0b 8867 /* PowerPC Cell */
80d11f44 8868 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 8869#endif
8870#if defined (TODO)
a750fc0b 8871 /* PowerPC Cell v1.0 */
80d11f44 8872 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 8873#endif
8874#if defined (TODO)
a750fc0b 8875 /* PowerPC Cell v2.0 */
80d11f44 8876 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 8877#endif
8878#if defined (TODO)
a750fc0b 8879 /* PowerPC Cell v3.0 */
80d11f44 8880 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 8881#endif
3a607854 8882#if defined (TODO)
a750fc0b 8883 /* PowerPC Cell v3.1 */
80d11f44 8884 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 8885#endif
8886#if defined (TODO)
a750fc0b 8887 /* PowerPC Cell v3.2 */
80d11f44 8888 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 8889#endif
8890#if defined (TODO)
a750fc0b
JM		 8891 /* RS64 (Apache/A35) */
8892 /* This one seems to support the whole POWER2 instruction set
8893 * and the PowerPC 64 one.
8894 */
8895 /* What about A10 & A30 ? */
80d11f44
JM		 8896 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8897 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8898 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 8899#endif
8900#if defined (TODO)
a750fc0b 8901 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 8902 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8903 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8904 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 8905#endif
8906#if defined (TODO)
a750fc0b 8907 /* RS64-III (Pulsar) */
80d11f44
JM		 8908 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8909 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 8910#endif
8911#if defined (TODO)
a750fc0b 8912 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 8913 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8914 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8915 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8916 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 8917#endif
a750fc0b
JM		 8918#endif /* defined (TARGET_PPC64) */
8919 /* POWER */
3fc6c082 8920#if defined (TODO)
a750fc0b 8921 /* Original POWER */
80d11f44
JM		 8922 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8923 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8924 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8925 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8926 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 8927#endif
8928#if defined (TODO)
a750fc0b 8929 /* POWER2 */
80d11f44
JM		 8930 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8931 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8932 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 8933#endif
8934 /* PA semi cores */
8935#if defined (TODO)
8936 /* PA PA6T */
80d11f44 8937 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 8938#endif
8939 /* Generic PowerPCs */
8940#if defined (TARGET_PPC64)
80d11f44 8941 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 8942#endif
80d11f44
JM		 8943 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8944 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 8945 /* Fallback */
80d11f44 8946 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 8947};
8948
8949/*****************************************************************************/
8950/* Generic CPU instanciation routine */
c227f099 8951static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8952{
8953#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 8954 int i;
8955
a750fc0b 8956 env->irq_inputs = NULL;
e1833e1f
JM		 8957 /* Set all exception vectors to an invalid address */
8958 for (i = 0; i < POWERPC_EXCP_NB; i++)
8959 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 8960 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 8961 env->ivor_mask = 0x00000000;
8962 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 8963 /* Default MMU definitions */
8964 env->nb_BATs = 0;
8965 env->nb_tlb = 0;
8966 env->nb_ways = 0;
f2e63a42 8967#endif
a750fc0b
JM		 8968 /* Register SPR common to all PowerPC implementations */
8969 gen_spr_generic(env);
8970 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 8971 /* Linux permits userspace to read PVR */
8972#if defined(CONFIG_LINUX_USER)
8973 &spr_read_generic,
8974#else
8975 SPR_NOACCESS,
8976#endif
8977 SPR_NOACCESS,
a750fc0b
JM		 8978 &spr_read_generic, SPR_NOACCESS,
8979 def->pvr);
80d11f44
JM		 8980 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8981 if (def->svr != POWERPC_SVR_NONE) {
8982 if (def->svr & POWERPC_SVR_E500) {
8983 spr_register(env, SPR_E500_SVR, "SVR",
8984 SPR_NOACCESS, SPR_NOACCESS,
8985 &spr_read_generic, SPR_NOACCESS,
8986 def->svr & ~POWERPC_SVR_E500);
8987 } else {
8988 spr_register(env, SPR_SVR, "SVR",
8989 SPR_NOACCESS, SPR_NOACCESS,
8990 &spr_read_generic, SPR_NOACCESS,
8991 def->svr);
8992 }
8993 }
a750fc0b
JM		 8994 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8995 (*def->init_proc)(env);
fc1c67bc
BS		 8996#if !defined(CONFIG_USER_ONLY)
8997 env->excp_prefix = env->hreset_excp_prefix;
8998#endif
25ba3a68
JM		 8999 /* MSR bits & flags consistency checks */
9000 if (env->msr_mask & (1 << 25)) {
9001 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9002 case POWERPC_FLAG_SPE:
9003 case POWERPC_FLAG_VRE:
9004 break;
9005 default:
9006 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9007 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9008 exit(1);
9009 }
9010 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9011 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9012 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9013 exit(1);
9014 }
9015 if (env->msr_mask & (1 << 17)) {
9016 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9017 case POWERPC_FLAG_TGPR:
9018 case POWERPC_FLAG_CE:
9019 break;
9020 default:
9021 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9022 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9023 exit(1);
9024 }
9025 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9026 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9027 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9028 exit(1);
9029 }
9030 if (env->msr_mask & (1 << 10)) {
9031 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9032 POWERPC_FLAG_UBLE)) {
9033 case POWERPC_FLAG_SE:
9034 case POWERPC_FLAG_DWE:
9035 case POWERPC_FLAG_UBLE:
9036 break;
9037 default:
9038 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9039 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9040 "POWERPC_FLAG_UBLE\n");
9041 exit(1);
9042 }
9043 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9044 POWERPC_FLAG_UBLE)) {
9045 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9046 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9047 "POWERPC_FLAG_UBLE\n");
9048 exit(1);
9049 }
9050 if (env->msr_mask & (1 << 9)) {
9051 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9052 case POWERPC_FLAG_BE:
9053 case POWERPC_FLAG_DE:
9054 break;
9055 default:
9056 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9057 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9058 exit(1);
9059 }
9060 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9061 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9062 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9063 exit(1);
9064 }
9065 if (env->msr_mask & (1 << 2)) {
9066 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9067 case POWERPC_FLAG_PX:
9068 case POWERPC_FLAG_PMM:
9069 break;
9070 default:
9071 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9072 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9073 exit(1);
9074 }
9075 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9076 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9077 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9078 exit(1);
9079 }
4018bae9
JM		 9080 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9081 fprintf(stderr, "PowerPC flags inconsistency\n"
9082 "Should define the time-base and decrementer clock source\n");
9083 exit(1);
9084 }
a750fc0b 9085 /* Allocate TLBs buffer when needed */
f2e63a42 9086#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9087 if (env->nb_tlb != 0) {
9088 int nb_tlb = env->nb_tlb;
9089 if (env->id_tlbs != 0)
9090 nb_tlb *= 2;
c227f099 9091 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
a750fc0b
JM		 9092 /* Pre-compute some useful values */
9093 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9094 }
a750fc0b
JM		 9095 if (env->irq_inputs == NULL) {
9096 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9097 " Attempt Qemu to crash very soon !\n");
9098 }
9099#endif
2f462816
JM		 9100 if (env->check_pow == NULL) {
9101 fprintf(stderr, "WARNING: no power management check handler "
9102 "registered.\n"
9103 " Attempt Qemu to crash very soon !\n");
9104 }
a750fc0b
JM		 9105}
9106
9107#if defined(PPC_DUMP_CPU)
9108static void dump_ppc_sprs (CPUPPCState *env)
9109{
9110 ppc_spr_t *spr;
9111#if !defined(CONFIG_USER_ONLY)
9112 uint32_t sr, sw;
9113#endif
9114 uint32_t ur, uw;
9115 int i, j, n;
9116
9117 printf("Special purpose registers:\n");
9118 for (i = 0; i < 32; i++) {
9119 for (j = 0; j < 32; j++) {
9120 n = (i << 5) | j;
9121 spr = &env->spr_cb[n];
9122 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9123 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9124#if !defined(CONFIG_USER_ONLY)
9125 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9126 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9127 if (sw || sr || uw || ur) {
9128 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9129 (i << 5) | j, (i << 5) | j, spr->name,
9130 sw ? 'w' : '-', sr ? 'r' : '-',
9131 uw ? 'w' : '-', ur ? 'r' : '-');
9132 }
9133#else
9134 if (uw || ur) {
9135 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9136 (i << 5) | j, (i << 5) | j, spr->name,
9137 uw ? 'w' : '-', ur ? 'r' : '-');
9138 }
9139#endif
9140 }
9141 }
9142 fflush(stdout);
9143 fflush(stderr);
9144}
9145#endif
9146
9147/*****************************************************************************/
9148#include <stdlib.h>
9149#include <string.h>
9150
a750fc0b
JM		 9151/* Opcode types */
9152enum {
9153 PPC_DIRECT = 0, /* Opcode routine */
9154 PPC_INDIRECT = 1, /* Indirect opcode table */
9155};
9156
9157static inline int is_indirect_opcode (void *handler)
9158{
9159 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9160}
9161
c227f099 9162static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9163{
c227f099 9164 return (opc_handler_t **)((unsigned long)handler & ~3);
a750fc0b
JM		 9165}
9166
9167/* Instruction table creation */
9168/* Opcodes tables creation */
c227f099 9169static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9170{
9171 int i;
9172
9173 for (i = 0; i < len; i++)
9174 table[i] = &invalid_handler;
9175}
9176
c227f099 9177static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9178{
c227f099 9179 opc_handler_t **tmp;
a750fc0b 9180
c227f099 9181 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9182 fill_new_table(tmp, 0x20);
c227f099 9183 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
a750fc0b
JM		 9184
9185 return 0;
9186}
9187
c227f099
AL		 9188static int insert_in_table (opc_handler_t **table, unsigned char idx,
9189 opc_handler_t *handler)
a750fc0b
JM		 9190{
9191 if (table[idx] != &invalid_handler)
9192 return -1;
9193 table[idx] = handler;
9194
9195 return 0;
9196}
9197
c227f099
AL		 9198static int register_direct_insn (opc_handler_t **ppc_opcodes,
9199 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9200{
9201 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9202 printf("*** ERROR: opcode %02x already assigned in main "
9203 "opcode table\n", idx);
4c1b1bfe
JM		 9204#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9205 printf(" Registered handler '%s' - new handler '%s'\n",
9206 ppc_opcodes[idx]->oname, handler->oname);
9207#endif
a750fc0b
JM		 9208 return -1;
9209 }
9210
9211 return 0;
9212}
9213
c227f099 9214static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9215 unsigned char idx1, unsigned char idx2,
c227f099 9216 opc_handler_t *handler)
a750fc0b
JM		 9217{
9218 if (table[idx1] == &invalid_handler) {
9219 if (create_new_table(table, idx1) < 0) {
9220 printf("*** ERROR: unable to create indirect table "
9221 "idx=%02x\n", idx1);
9222 return -1;
9223 }
9224 } else {
9225 if (!is_indirect_opcode(table[idx1])) {
9226 printf("*** ERROR: idx %02x already assigned to a direct "
9227 "opcode\n", idx1);
4c1b1bfe
JM		 9228#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9229 printf(" Registered handler '%s' - new handler '%s'\n",
9230 ind_table(table[idx1])[idx2]->oname, handler->oname);
9231#endif
a750fc0b
JM		 9232 return -1;
9233 }
3a607854 9234 }
a750fc0b
JM		 9235 if (handler != NULL &&
9236 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9237 printf("*** ERROR: opcode %02x already assigned in "
9238 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9239#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9240 printf(" Registered handler '%s' - new handler '%s'\n",
9241 ind_table(table[idx1])[idx2]->oname, handler->oname);
9242#endif
a750fc0b 9243 return -1;
3a607854 9244 }
a750fc0b
JM		 9245
9246 return 0;
9247}
9248
c227f099 9249static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9250 unsigned char idx1, unsigned char idx2,
c227f099 9251 opc_handler_t *handler)
a750fc0b
JM		 9252{
9253 int ret;
9254
9255 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9256
9257 return ret;
9258}
9259
c227f099 9260static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9261 unsigned char idx1, unsigned char idx2,
c227f099 9262 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9263{
9264 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9265 printf("*** ERROR: unable to join indirect table idx "
9266 "[%02x-%02x]\n", idx1, idx2);
9267 return -1;
9268 }
9269 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9270 handler) < 0) {
9271 printf("*** ERROR: unable to insert opcode "
9272 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9273 return -1;
9274 }
9275
9276 return 0;
9277}
9278
c227f099 9279static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9280{
9281 if (insn->opc2 != 0xFF) {
9282 if (insn->opc3 != 0xFF) {
9283 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9284 insn->opc3, &insn->handler) < 0)
9285 return -1;
9286 } else {
9287 if (register_ind_insn(ppc_opcodes, insn->opc1,
9288 insn->opc2, &insn->handler) < 0)
9289 return -1;
9290 }
9291 } else {
9292 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9293 return -1;
9294 }
9295
9296 return 0;
9297}
9298
c227f099 9299static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9300{
9301 int i, count, tmp;
9302
9303 for (i = 0, count = 0; i < len; i++) {
9304 /* Consistency fixup */
9305 if (table[i] == NULL)
9306 table[i] = &invalid_handler;
9307 if (table[i] != &invalid_handler) {
9308 if (is_indirect_opcode(table[i])) {
c227f099 9309 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9310 if (tmp == 0) {
9311 free(table[i]);
9312 table[i] = &invalid_handler;
9313 } else {
9314 count++;
9315 }
9316 } else {
9317 count++;
9318 }
9319 }
9320 }
9321
9322 return count;
9323}
9324
c227f099 9325static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9326{
c227f099 9327 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9328 printf("*** WARNING: no opcode defined !\n");
9329}
9330
9331/*****************************************************************************/
c227f099 9332static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b 9333{
c227f099 9334 opcode_t *opc;
a750fc0b
JM		 9335
9336 fill_new_table(env->opcodes, 0x40);
5c55ff99 9337 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
a750fc0b
JM		 9338 if ((opc->handler.type & def->insns_flags) != 0) {
9339 if (register_insn(env->opcodes, opc) < 0) {
9340 printf("*** ERROR initializing PowerPC instruction "
9341 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9342 opc->opc3);
9343 return -1;
9344 }
9345 }
9346 }
c227f099 9347 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9348 fflush(stdout);
9349 fflush(stderr);
9350
9351 return 0;
9352}
9353
9354#if defined(PPC_DUMP_CPU)
25ba3a68 9355static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9356{
c227f099 9357 opc_handler_t **table, *handler;
b55266b5 9358 const char *p, *q;
a750fc0b
JM		 9359 uint8_t opc1, opc2, opc3;
9360
9361 printf("Instructions set:\n");
9362 /* opc1 is 6 bits long */
9363 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9364 table = env->opcodes;
9365 handler = table[opc1];
9366 if (is_indirect_opcode(handler)) {
9367 /* opc2 is 5 bits long */
9368 for (opc2 = 0; opc2 < 0x20; opc2++) {
9369 table = env->opcodes;
9370 handler = env->opcodes[opc1];
9371 table = ind_table(handler);
9372 handler = table[opc2];
9373 if (is_indirect_opcode(handler)) {
9374 table = ind_table(handler);
9375 /* opc3 is 5 bits long */
9376 for (opc3 = 0; opc3 < 0x20; opc3++) {
9377 handler = table[opc3];
9378 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9379 /* Special hack to properly dump SPE insns */
9380 p = strchr(handler->oname, '_');
9381 if (p == NULL) {
9382 printf("INSN: %02x %02x %02x (%02d %04d) : "
9383 "%s\n",
9384 opc1, opc2, opc3, opc1,
9385 (opc3 << 5) | opc2,
9386 handler->oname);
9387 } else {
9388 q = "speundef";
9389 if ((p - handler->oname) != strlen(q) ||
9390 memcmp(handler->oname, q, strlen(q)) != 0) {
9391 /* First instruction */
9392 printf("INSN: %02x %02x %02x (%02d %04d) : "
9393 "%.*s\n",
9394 opc1, opc2 << 1, opc3, opc1,
9395 (opc3 << 6) | (opc2 << 1),
9396 (int)(p - handler->oname),
9397 handler->oname);
9398 }
9399 if (strcmp(p + 1, q) != 0) {
9400 /* Second instruction */
9401 printf("INSN: %02x %02x %02x (%02d %04d) : "
9402 "%s\n",
9403 opc1, (opc2 << 1) | 1, opc3, opc1,
9404 (opc3 << 6) | (opc2 << 1) | 1,
9405 p + 1);
9406 }
9407 }
a750fc0b
JM		 9408 }
9409 }
9410 } else {
9411 if (handler->handler != &gen_invalid) {
9412 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9413 opc1, opc2, opc1, opc2, handler->oname);
9414 }
9415 }
9416 }
9417 } else {
9418 if (handler->handler != &gen_invalid) {
9419 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9420 opc1, opc1, handler->oname);
9421 }
9422 }
9423 }
9424}
3a607854 9425#endif
a750fc0b 9426
24951522
AJ		 9427static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9428{
9429 if (n < 32) {
9430 stfq_p(mem_buf, env->fpr[n]);
9431 return 8;
9432 }
9433 if (n == 32) {
9434 /* FPSCR not implemented */
9435 memset(mem_buf, 0, 4);
9436 return 4;
9437 }
9438 return 0;
9439}
9440
9441static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9442{
9443 if (n < 32) {
9444 env->fpr[n] = ldfq_p(mem_buf);
9445 return 8;
9446 }
9447 if (n == 32) {
9448 /* FPSCR not implemented */
9449 return 4;
9450 }
9451 return 0;
9452}
9453
b4f8d821
AJ		 9454static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9455{
9456 if (n < 32) {
e2542fe2 9457#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9458 stq_p(mem_buf, env->avr[n].u64[0]);
9459 stq_p(mem_buf+8, env->avr[n].u64[1]);
9460#else
9461 stq_p(mem_buf, env->avr[n].u64[1]);
9462 stq_p(mem_buf+8, env->avr[n].u64[0]);
9463#endif
9464 return 16;
9465 }
70976a79 9466 if (n == 32) {
b4f8d821
AJ		 9467 stl_p(mem_buf, env->vscr);
9468 return 4;
9469 }
70976a79 9470 if (n == 33) {
b4f8d821
AJ		 9471 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9472 return 4;
9473 }
9474 return 0;
9475}
9476
9477static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9478{
9479 if (n < 32) {
e2542fe2 9480#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9481 env->avr[n].u64[0] = ldq_p(mem_buf);
9482 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9483#else
9484 env->avr[n].u64[1] = ldq_p(mem_buf);
9485 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9486#endif
9487 return 16;
9488 }
70976a79 9489 if (n == 32) {
b4f8d821
AJ		 9490 env->vscr = ldl_p(mem_buf);
9491 return 4;
9492 }
70976a79 9493 if (n == 33) {
b4f8d821
AJ		 9494 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9495 return 4;
9496 }
9497 return 0;
9498}
9499
688890f7
AJ		 9500static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9501{
9502 if (n < 32) {
9503#if defined(TARGET_PPC64)
9504 stl_p(mem_buf, env->gpr[n] >> 32);
9505#else
9506 stl_p(mem_buf, env->gprh[n]);
9507#endif
9508 return 4;
9509 }
70976a79 9510 if (n == 32) {
688890f7
AJ		 9511 stq_p(mem_buf, env->spe_acc);
9512 return 8;
9513 }
70976a79 9514 if (n == 33) {
d34defbc 9515 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9516 return 4;
9517 }
9518 return 0;
9519}
9520
9521static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9522{
9523 if (n < 32) {
9524#if defined(TARGET_PPC64)
9525 target_ulong lo = (uint32_t)env->gpr[n];
9526 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9527 env->gpr[n] = lo | hi;
9528#else
9529 env->gprh[n] = ldl_p(mem_buf);
9530#endif
9531 return 4;
9532 }
70976a79 9533 if (n == 32) {
688890f7
AJ		 9534 env->spe_acc = ldq_p(mem_buf);
9535 return 8;
9536 }
70976a79 9537 if (n == 33) {
d34defbc 9538 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9539 return 4;
9540 }
9541 return 0;
9542}
9543
c227f099 9544int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9545{
9546 env->msr_mask = def->msr_mask;
9547 env->mmu_model = def->mmu_model;
9548 env->excp_model = def->excp_model;
9549 env->bus_model = def->bus_model;
c29b735c 9550 env->insns_flags = def->insns_flags;
d26bfc9a 9551 env->flags = def->flags;
237c0af0 9552 env->bfd_mach = def->bfd_mach;
2f462816 9553 env->check_pow = def->check_pow;
a750fc0b
JM		 9554 if (create_ppc_opcodes(env, def) < 0)
9555 return -1;
9556 init_ppc_proc(env, def);
24951522
AJ		 9557
9558 if (def->insns_flags & PPC_FLOAT) {
9559 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9560 33, "power-fpu.xml", 0);
9561 }
b4f8d821
AJ		 9562 if (def->insns_flags & PPC_ALTIVEC) {
9563 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9564 34, "power-altivec.xml", 0);
9565 }
40569b7e 9566 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9567 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9568 34, "power-spe.xml", 0);
9569 }
9570
a750fc0b 9571#if defined(PPC_DUMP_CPU)
3a607854 9572 {
b55266b5 9573 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9574 switch (env->mmu_model) {
9575 case POWERPC_MMU_32B:
9576 mmu_model = "PowerPC 32";
9577 break;
a750fc0b
JM		 9578 case POWERPC_MMU_SOFT_6xx:
9579 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9580 break;
9581 case POWERPC_MMU_SOFT_74xx:
9582 mmu_model = "PowerPC 74xx with software driven TLBs";
9583 break;
9584 case POWERPC_MMU_SOFT_4xx:
9585 mmu_model = "PowerPC 4xx with software driven TLBs";
9586 break;
9587 case POWERPC_MMU_SOFT_4xx_Z:
9588 mmu_model = "PowerPC 4xx with software driven TLBs "
9589 "and zones protections";
9590 break;
b4095fed
JM		 9591 case POWERPC_MMU_REAL:
9592 mmu_model = "PowerPC real mode only";
9593 break;
9594 case POWERPC_MMU_MPC8xx:
9595 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9596 break;
9597 case POWERPC_MMU_BOOKE:
9598 mmu_model = "PowerPC BookE";
9599 break;
9600 case POWERPC_MMU_BOOKE_FSL:
9601 mmu_model = "PowerPC BookE FSL";
9602 break;
b4095fed
JM		 9603 case POWERPC_MMU_601:
9604 mmu_model = "PowerPC 601";
9605 break;
00af685f
JM		 9606#if defined (TARGET_PPC64)
9607 case POWERPC_MMU_64B:
9608 mmu_model = "PowerPC 64";
9609 break;
add78955
JM		 9610 case POWERPC_MMU_620:
9611 mmu_model = "PowerPC 620";
9612 break;
00af685f 9613#endif
a750fc0b
JM		 9614 default:
9615 mmu_model = "Unknown or invalid";
9616 break;
9617 }
9618 switch (env->excp_model) {
9619 case POWERPC_EXCP_STD:
9620 excp_model = "PowerPC";
9621 break;
9622 case POWERPC_EXCP_40x:
9623 excp_model = "PowerPC 40x";
9624 break;
9625 case POWERPC_EXCP_601:
9626 excp_model = "PowerPC 601";
9627 break;
9628 case POWERPC_EXCP_602:
9629 excp_model = "PowerPC 602";
9630 break;
9631 case POWERPC_EXCP_603:
9632 excp_model = "PowerPC 603";
9633 break;
9634 case POWERPC_EXCP_603E:
9635 excp_model = "PowerPC 603e";
9636 break;
9637 case POWERPC_EXCP_604:
9638 excp_model = "PowerPC 604";
9639 break;
9640 case POWERPC_EXCP_7x0:
9641 excp_model = "PowerPC 740/750";
9642 break;
9643 case POWERPC_EXCP_7x5:
9644 excp_model = "PowerPC 745/755";
9645 break;
9646 case POWERPC_EXCP_74xx:
9647 excp_model = "PowerPC 74xx";
9648 break;
a750fc0b
JM		 9649 case POWERPC_EXCP_BOOKE:
9650 excp_model = "PowerPC BookE";
9651 break;
00af685f
JM		 9652#if defined (TARGET_PPC64)
9653 case POWERPC_EXCP_970:
9654 excp_model = "PowerPC 970";
9655 break;
9656#endif
a750fc0b
JM		 9657 default:
9658 excp_model = "Unknown or invalid";
9659 break;
9660 }
9661 switch (env->bus_model) {
9662 case PPC_FLAGS_INPUT_6xx:
9663 bus_model = "PowerPC 6xx";
9664 break;
9665 case PPC_FLAGS_INPUT_BookE:
9666 bus_model = "PowerPC BookE";
9667 break;
9668 case PPC_FLAGS_INPUT_405:
9669 bus_model = "PowerPC 405";
9670 break;
a750fc0b
JM		 9671 case PPC_FLAGS_INPUT_401:
9672 bus_model = "PowerPC 401/403";
9673 break;
b4095fed
JM		 9674 case PPC_FLAGS_INPUT_RCPU:
9675 bus_model = "RCPU / MPC8xx";
9676 break;
00af685f
JM		 9677#if defined (TARGET_PPC64)
9678 case PPC_FLAGS_INPUT_970:
9679 bus_model = "PowerPC 970";
9680 break;
9681#endif
a750fc0b
JM		 9682 default:
9683 bus_model = "Unknown or invalid";
9684 break;
9685 }
9686 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9687 " MMU model : %s\n",
9688 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9689#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9690 if (env->tlb != NULL) {
9691 printf(" %d %s TLB in %d ways\n",
9692 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9693 env->nb_ways);
9694 }
f2e63a42 9695#endif
a750fc0b
JM		 9696 printf(" Exceptions model : %s\n"
9697 " Bus model : %s\n",
9698 excp_model, bus_model);
25ba3a68
JM		 9699 printf(" MSR features :\n");
9700 if (env->flags & POWERPC_FLAG_SPE)
9701 printf(" signal processing engine enable"
9702 "\n");
9703 else if (env->flags & POWERPC_FLAG_VRE)
9704 printf(" vector processor enable\n");
9705 if (env->flags & POWERPC_FLAG_TGPR)
9706 printf(" temporary GPRs\n");
9707 else if (env->flags & POWERPC_FLAG_CE)
9708 printf(" critical input enable\n");
9709 if (env->flags & POWERPC_FLAG_SE)
9710 printf(" single-step trace mode\n");
9711 else if (env->flags & POWERPC_FLAG_DWE)
9712 printf(" debug wait enable\n");
9713 else if (env->flags & POWERPC_FLAG_UBLE)
9714 printf(" user BTB lock enable\n");
9715 if (env->flags & POWERPC_FLAG_BE)
9716 printf(" branch-step trace mode\n");
9717 else if (env->flags & POWERPC_FLAG_DE)
9718 printf(" debug interrupt enable\n");
9719 if (env->flags & POWERPC_FLAG_PX)
9720 printf(" inclusive protection\n");
9721 else if (env->flags & POWERPC_FLAG_PMM)
9722 printf(" performance monitor mark\n");
9723 if (env->flags == POWERPC_FLAG_NONE)
9724 printf(" none\n");
4018bae9
JM		 9725 printf(" Time-base/decrementer clock source: %s\n",
9726 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9727 }
9728 dump_ppc_insns(env);
9729 dump_ppc_sprs(env);
9730 fflush(stdout);
3a607854 9731#endif
a750fc0b
JM		 9732
9733 return 0;
9734}
3fc6c082 9735
c227f099 9736static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9737{
c227f099 9738 const ppc_def_t *ret;
ee4e83ed
JM		 9739 uint32_t pvr_rev;
9740 int i, best, match, best_match, max;
3fc6c082 9741
ee4e83ed 9742 ret = NULL;
b1503cda 9743 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9744 best = -1;
9745 pvr_rev = pvr & 0xFFFF;
9746 /* We want all specified bits to match */
9747 best_match = 32 - ctz32(pvr_rev);
068abdc8 9748 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9749 /* We check that the 16 higher bits are the same to ensure the CPU
9750 * model will be the choosen one.
9751 */
9752 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9753 /* We want as much as possible of the low-level 16 bits
9754 * to be the same but we allow inexact matches.
9755 */
9756 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9757 /* We check '>=' instead of '>' because the PPC_defs table
9758 * is ordered by increasing revision.
4c1b1bfe 9759 * Then, we will match the higher revision compatible
ee4e83ed
JM		 9760 * with the requested PVR
9761 */
9762 if (match >= best_match) {
9763 best = i;
9764 best_match = match;
9765 }
3fc6c082
FB		 9766 }
9767 }
ee4e83ed
JM		 9768 if (best != -1)
9769 ret = &ppc_defs[best];
9770
9771 return ret;
3fc6c082
FB		 9772}
9773
ee4e83ed 9774#include <ctype.h>
3fc6c082 9775
c227f099 9776const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed 9777{
c227f099 9778 const ppc_def_t *ret;
b55266b5 9779 const char *p;
ee4e83ed
JM		 9780 int i, max, len;
9781
9782 /* Check if the given name is a PVR */
9783 len = strlen(name);
9784 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9785 p = name + 2;
9786 goto check_pvr;
9787 } else if (len == 8) {
9788 p = name;
9789 check_pvr:
9790 for (i = 0; i < 8; i++) {
cd390083 9791 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 9792 break;
9793 }
9794 if (i == 8)
9795 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9796 }
9797 ret = NULL;
b1503cda 9798 max = ARRAY_SIZE(ppc_defs);
068abdc8 9799 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9800 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9801 ret = &ppc_defs[i];
9802 break;
3fc6c082
FB		 9803 }
9804 }
ee4e83ed
JM		 9805
9806 return ret;
3fc6c082
FB		 9807}
9808
9a78eead 9809void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
3fc6c082 9810{
068abdc8 9811 int i, max;
3fc6c082 9812
b1503cda 9813 max = ARRAY_SIZE(ppc_defs);
068abdc8 9814 for (i = 0; i < max; i++) {
a750fc0b
JM		 9815 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9816 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 9817 }
9818}
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