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Commit | Line | Data |
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3fc6c082 FB |
1 | /* |
2 | * PowerPC CPU initialization for qemu. | |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
f7aa5583 | 5 | * Copyright 2011 Freescale Semiconductor, Inc. |
3fc6c082 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
3fc6c082 FB |
19 | */ |
20 | ||
0d75590d | 21 | #include "qemu/osdep.h" |
76cad711 | 22 | #include "disas/bfd.h" |
022c62cb | 23 | #include "exec/gdbstub.h" |
9c17d615 | 24 | #include <sysemu/kvm.h> |
a1e98583 | 25 | #include "kvm_ppc.h" |
9c17d615 | 26 | #include "sysemu/arch_init.h" |
fe828a4d | 27 | #include "sysemu/cpus.h" |
953af181 | 28 | #include "cpu-models.h" |
b632a148 DG |
29 | #include "mmu-hash32.h" |
30 | #include "mmu-hash64.h" | |
4a44d85e | 31 | #include "qemu/error-report.h" |
8dfa3a5e AK |
32 | #include "qapi/visitor.h" |
33 | #include "hw/qdev-properties.h" | |
aa5a9e24 | 34 | #include "hw/ppc/ppc.h" |
237c0af0 | 35 | |
3fc6c082 FB |
36 | //#define PPC_DUMP_CPU |
37 | //#define PPC_DEBUG_SPR | |
80d11f44 | 38 | //#define PPC_DUMP_SPR_ACCESSES |
b3cad3ab | 39 | /* #define USE_APPLE_GDB */ |
3fc6c082 | 40 | |
3fc6c082 FB |
41 | /* Generic callbacks: |
42 | * do nothing but store/retrieve spr value | |
43 | */ | |
91f477fd AG |
44 | static void spr_load_dump_spr(int sprn) |
45 | { | |
46 | #ifdef PPC_DUMP_SPR_ACCESSES | |
47 | TCGv_i32 t0 = tcg_const_i32(sprn); | |
edbe35e0 | 48 | gen_helper_load_dump_spr(cpu_env, t0); |
91f477fd AG |
49 | tcg_temp_free_i32(t0); |
50 | #endif | |
51 | } | |
52 | ||
69b058c8 | 53 | static void spr_read_generic (DisasContext *ctx, int gprn, int sprn) |
a496775f | 54 | { |
45d827d2 | 55 | gen_load_spr(cpu_gpr[gprn], sprn); |
91f477fd AG |
56 | spr_load_dump_spr(sprn); |
57 | } | |
58 | ||
59 | static void spr_store_dump_spr(int sprn) | |
60 | { | |
45d827d2 | 61 | #ifdef PPC_DUMP_SPR_ACCESSES |
91f477fd | 62 | TCGv_i32 t0 = tcg_const_i32(sprn); |
edbe35e0 | 63 | gen_helper_store_dump_spr(cpu_env, t0); |
91f477fd | 64 | tcg_temp_free_i32(t0); |
45d827d2 | 65 | #endif |
a496775f JM |
66 | } |
67 | ||
69b058c8 | 68 | static void spr_write_generic (DisasContext *ctx, int sprn, int gprn) |
a496775f | 69 | { |
45d827d2 | 70 | gen_store_spr(sprn, cpu_gpr[gprn]); |
91f477fd | 71 | spr_store_dump_spr(sprn); |
45d827d2 | 72 | } |
a496775f JM |
73 | |
74 | #if !defined(CONFIG_USER_ONLY) | |
69b058c8 | 75 | static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) |
ba38ab8d AG |
76 | { |
77 | #ifdef TARGET_PPC64 | |
78 | TCGv t0 = tcg_temp_new(); | |
79 | tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); | |
80 | gen_store_spr(sprn, t0); | |
81 | tcg_temp_free(t0); | |
82 | spr_store_dump_spr(sprn); | |
83 | #else | |
69b058c8 | 84 | spr_write_generic(ctx, sprn, gprn); |
ba38ab8d AG |
85 | #endif |
86 | } | |
87 | ||
69b058c8 | 88 | static void spr_write_clear (DisasContext *ctx, int sprn, int gprn) |
a496775f | 89 | { |
45d827d2 AJ |
90 | TCGv t0 = tcg_temp_new(); |
91 | TCGv t1 = tcg_temp_new(); | |
92 | gen_load_spr(t0, sprn); | |
93 | tcg_gen_neg_tl(t1, cpu_gpr[gprn]); | |
94 | tcg_gen_and_tl(t0, t0, t1); | |
95 | gen_store_spr(sprn, t0); | |
96 | tcg_temp_free(t0); | |
97 | tcg_temp_free(t1); | |
a496775f | 98 | } |
9633fcc6 | 99 | |
69b058c8 | 100 | static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) |
9633fcc6 AG |
101 | { |
102 | } | |
103 | ||
a496775f JM |
104 | #endif |
105 | ||
76a66253 | 106 | /* SPR common to all PowerPC */ |
3fc6c082 | 107 | /* XER */ |
69b058c8 | 108 | static void spr_read_xer (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 109 | { |
da91a00f | 110 | gen_read_xer(cpu_gpr[gprn]); |
3fc6c082 FB |
111 | } |
112 | ||
69b058c8 | 113 | static void spr_write_xer (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 114 | { |
da91a00f | 115 | gen_write_xer(cpu_gpr[gprn]); |
3fc6c082 FB |
116 | } |
117 | ||
118 | /* LR */ | |
69b058c8 | 119 | static void spr_read_lr (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 120 | { |
45d827d2 | 121 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); |
3fc6c082 FB |
122 | } |
123 | ||
69b058c8 | 124 | static void spr_write_lr (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 125 | { |
45d827d2 | 126 | tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); |
3fc6c082 FB |
127 | } |
128 | ||
697ab892 DG |
129 | /* CFAR */ |
130 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
69b058c8 | 131 | static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn) |
697ab892 DG |
132 | { |
133 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); | |
134 | } | |
135 | ||
69b058c8 | 136 | static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn) |
697ab892 DG |
137 | { |
138 | tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); | |
139 | } | |
140 | #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ | |
141 | ||
3fc6c082 | 142 | /* CTR */ |
69b058c8 | 143 | static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 144 | { |
45d827d2 | 145 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); |
3fc6c082 FB |
146 | } |
147 | ||
69b058c8 | 148 | static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 149 | { |
45d827d2 | 150 | tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); |
3fc6c082 FB |
151 | } |
152 | ||
153 | /* User read access to SPR */ | |
154 | /* USPRx */ | |
155 | /* UMMCRx */ | |
156 | /* UPMCx */ | |
157 | /* USIA */ | |
158 | /* UDECR */ | |
69b058c8 | 159 | static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 160 | { |
45d827d2 | 161 | gen_load_spr(cpu_gpr[gprn], sprn + 0x10); |
3fc6c082 FB |
162 | } |
163 | ||
fd51ff63 | 164 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
69b058c8 | 165 | static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) |
fd51ff63 AK |
166 | { |
167 | gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); | |
168 | } | |
169 | #endif | |
170 | ||
76a66253 | 171 | /* SPR common to all non-embedded PowerPC */ |
3fc6c082 | 172 | /* DECR */ |
76a66253 | 173 | #if !defined(CONFIG_USER_ONLY) |
69b058c8 | 174 | static void spr_read_decr (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 175 | { |
bd79255d | 176 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 TG |
177 | gen_io_start(); |
178 | } | |
d0f1562d | 179 | gen_helper_load_decr(cpu_gpr[gprn], cpu_env); |
bd79255d | 180 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 | 181 | gen_io_end(); |
69b058c8 | 182 | gen_stop_exception(ctx); |
630ecca0 | 183 | } |
3fc6c082 FB |
184 | } |
185 | ||
69b058c8 | 186 | static void spr_write_decr (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 187 | { |
bd79255d | 188 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 TG |
189 | gen_io_start(); |
190 | } | |
d0f1562d | 191 | gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); |
bd79255d | 192 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 | 193 | gen_io_end(); |
69b058c8 | 194 | gen_stop_exception(ctx); |
630ecca0 | 195 | } |
3fc6c082 | 196 | } |
76a66253 | 197 | #endif |
3fc6c082 | 198 | |
76a66253 | 199 | /* SPR common to all non-embedded PowerPC, except 601 */ |
3fc6c082 | 200 | /* Time base */ |
69b058c8 | 201 | static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 202 | { |
bd79255d | 203 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 TG |
204 | gen_io_start(); |
205 | } | |
d0f1562d | 206 | gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); |
bd79255d | 207 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 | 208 | gen_io_end(); |
69b058c8 | 209 | gen_stop_exception(ctx); |
630ecca0 | 210 | } |
3fc6c082 FB |
211 | } |
212 | ||
69b058c8 | 213 | static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 214 | { |
bd79255d | 215 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 TG |
216 | gen_io_start(); |
217 | } | |
d0f1562d | 218 | gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); |
bd79255d | 219 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 | 220 | gen_io_end(); |
69b058c8 | 221 | gen_stop_exception(ctx); |
630ecca0 | 222 | } |
3fc6c082 FB |
223 | } |
224 | ||
a062e36c | 225 | __attribute__ (( unused )) |
69b058c8 | 226 | static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn) |
a062e36c | 227 | { |
d0f1562d | 228 | gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); |
a062e36c JM |
229 | } |
230 | ||
231 | __attribute__ (( unused )) | |
69b058c8 | 232 | static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn) |
a062e36c | 233 | { |
d0f1562d | 234 | gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); |
a062e36c JM |
235 | } |
236 | ||
76a66253 | 237 | #if !defined(CONFIG_USER_ONLY) |
69b058c8 | 238 | static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 239 | { |
bd79255d | 240 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 TG |
241 | gen_io_start(); |
242 | } | |
d0f1562d | 243 | gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); |
bd79255d | 244 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 | 245 | gen_io_end(); |
69b058c8 | 246 | gen_stop_exception(ctx); |
630ecca0 | 247 | } |
3fc6c082 FB |
248 | } |
249 | ||
69b058c8 | 250 | static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 251 | { |
bd79255d | 252 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 TG |
253 | gen_io_start(); |
254 | } | |
d0f1562d | 255 | gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); |
bd79255d | 256 | if (ctx->tb->cflags & CF_USE_ICOUNT) { |
630ecca0 | 257 | gen_io_end(); |
69b058c8 | 258 | gen_stop_exception(ctx); |
630ecca0 | 259 | } |
3fc6c082 | 260 | } |
a062e36c JM |
261 | |
262 | __attribute__ (( unused )) | |
69b058c8 | 263 | static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn) |
a062e36c | 264 | { |
d0f1562d | 265 | gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); |
a062e36c JM |
266 | } |
267 | ||
268 | __attribute__ (( unused )) | |
69b058c8 | 269 | static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn) |
a062e36c | 270 | { |
d0f1562d | 271 | gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); |
a062e36c | 272 | } |
3a7f009a DG |
273 | |
274 | #if defined(TARGET_PPC64) | |
275 | __attribute__ (( unused )) | |
69b058c8 | 276 | static void spr_read_purr (DisasContext *ctx, int gprn, int sprn) |
3a7f009a | 277 | { |
d0f1562d | 278 | gen_helper_load_purr(cpu_gpr[gprn], cpu_env); |
3a7f009a DG |
279 | } |
280 | #endif | |
76a66253 | 281 | #endif |
3fc6c082 | 282 | |
76a66253 | 283 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
284 | /* IBAT0U...IBAT0U */ |
285 | /* IBAT0L...IBAT7L */ | |
69b058c8 | 286 | static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 287 | { |
1328c2bf | 288 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
3fc6c082 FB |
289 | } |
290 | ||
69b058c8 | 291 | static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 292 | { |
3ede8f69 | 293 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); |
3fc6c082 FB |
294 | } |
295 | ||
69b058c8 | 296 | static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 297 | { |
45d827d2 | 298 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
c6c7cf05 | 299 | gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 300 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
301 | } |
302 | ||
69b058c8 | 303 | static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 304 | { |
8daf1781 | 305 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); |
c6c7cf05 | 306 | gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 307 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
308 | } |
309 | ||
69b058c8 | 310 | static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 311 | { |
45d827d2 | 312 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); |
c6c7cf05 | 313 | gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 314 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
315 | } |
316 | ||
69b058c8 | 317 | static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 318 | { |
8daf1781 | 319 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); |
c6c7cf05 | 320 | gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 321 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
322 | } |
323 | ||
324 | /* DBAT0U...DBAT7U */ | |
325 | /* DBAT0L...DBAT7L */ | |
69b058c8 | 326 | static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 327 | { |
1328c2bf | 328 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); |
3fc6c082 FB |
329 | } |
330 | ||
69b058c8 | 331 | static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 332 | { |
1328c2bf | 333 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); |
3fc6c082 FB |
334 | } |
335 | ||
69b058c8 | 336 | static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 337 | { |
45d827d2 | 338 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); |
c6c7cf05 | 339 | gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 340 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
341 | } |
342 | ||
69b058c8 | 343 | static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 344 | { |
45d827d2 | 345 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
c6c7cf05 | 346 | gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 347 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
348 | } |
349 | ||
69b058c8 | 350 | static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 351 | { |
45d827d2 | 352 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); |
c6c7cf05 | 353 | gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 354 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
355 | } |
356 | ||
69b058c8 | 357 | static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 358 | { |
45d827d2 | 359 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
c6c7cf05 | 360 | gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 361 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
362 | } |
363 | ||
364 | /* SDR1 */ | |
69b058c8 | 365 | static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 366 | { |
d523dd00 | 367 | gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); |
3fc6c082 FB |
368 | } |
369 | ||
76a66253 | 370 | /* 64 bits PowerPC specific SPRs */ |
578bb252 | 371 | #if defined(TARGET_PPC64) |
69b058c8 | 372 | static void spr_read_hior (DisasContext *ctx, int gprn, int sprn) |
2adab7d6 | 373 | { |
1328c2bf | 374 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); |
2adab7d6 BS |
375 | } |
376 | ||
69b058c8 | 377 | static void spr_write_hior (DisasContext *ctx, int sprn, int gprn) |
2adab7d6 BS |
378 | { |
379 | TCGv t0 = tcg_temp_new(); | |
380 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); | |
1328c2bf | 381 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
2adab7d6 BS |
382 | tcg_temp_free(t0); |
383 | } | |
76a66253 | 384 | #endif |
a750fc0b | 385 | #endif |
76a66253 JM |
386 | |
387 | /* PowerPC 601 specific registers */ | |
388 | /* RTC */ | |
69b058c8 | 389 | static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn) |
76a66253 | 390 | { |
d0f1562d | 391 | gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); |
76a66253 JM |
392 | } |
393 | ||
69b058c8 | 394 | static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn) |
76a66253 | 395 | { |
d0f1562d | 396 | gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); |
76a66253 JM |
397 | } |
398 | ||
399 | #if !defined(CONFIG_USER_ONLY) | |
69b058c8 | 400 | static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 401 | { |
d0f1562d | 402 | gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
403 | } |
404 | ||
69b058c8 | 405 | static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 406 | { |
d0f1562d | 407 | gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); |
76a66253 | 408 | } |
056401ea | 409 | |
69b058c8 | 410 | static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn) |
056401ea | 411 | { |
d523dd00 | 412 | gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); |
056401ea | 413 | /* Must stop the translation as endianness may have changed */ |
e06fcd75 | 414 | gen_stop_exception(ctx); |
056401ea | 415 | } |
76a66253 JM |
416 | #endif |
417 | ||
418 | /* Unified bats */ | |
419 | #if !defined(CONFIG_USER_ONLY) | |
69b058c8 | 420 | static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn) |
76a66253 | 421 | { |
1328c2bf | 422 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
76a66253 JM |
423 | } |
424 | ||
69b058c8 | 425 | static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 426 | { |
45d827d2 | 427 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
c6c7cf05 | 428 | gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 429 | tcg_temp_free_i32(t0); |
76a66253 JM |
430 | } |
431 | ||
69b058c8 | 432 | static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 433 | { |
45d827d2 | 434 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
c6c7cf05 | 435 | gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 436 | tcg_temp_free_i32(t0); |
76a66253 JM |
437 | } |
438 | #endif | |
439 | ||
440 | /* PowerPC 40x specific registers */ | |
441 | #if !defined(CONFIG_USER_ONLY) | |
69b058c8 | 442 | static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn) |
76a66253 | 443 | { |
d0f1562d | 444 | gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); |
76a66253 JM |
445 | } |
446 | ||
69b058c8 | 447 | static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 448 | { |
d0f1562d | 449 | gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
450 | } |
451 | ||
69b058c8 | 452 | static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn) |
8ecc7913 | 453 | { |
d523dd00 | 454 | gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); |
8ecc7913 | 455 | /* We must stop translation as we may have rebooted */ |
e06fcd75 | 456 | gen_stop_exception(ctx); |
8ecc7913 JM |
457 | } |
458 | ||
69b058c8 | 459 | static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn) |
c294fc58 | 460 | { |
d523dd00 | 461 | gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); |
c294fc58 JM |
462 | } |
463 | ||
69b058c8 | 464 | static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 465 | { |
d0f1562d | 466 | gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
467 | } |
468 | ||
69b058c8 | 469 | static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 470 | { |
d0f1562d | 471 | gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
472 | } |
473 | #endif | |
474 | ||
475 | /* PowerPC 403 specific registers */ | |
476 | /* PBL1 / PBU1 / PBL2 / PBU2 */ | |
477 | #if !defined(CONFIG_USER_ONLY) | |
69b058c8 | 478 | static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn) |
76a66253 | 479 | { |
1328c2bf | 480 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); |
76a66253 JM |
481 | } |
482 | ||
69b058c8 | 483 | static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn) |
76a66253 | 484 | { |
45d827d2 | 485 | TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); |
d523dd00 | 486 | gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 487 | tcg_temp_free_i32(t0); |
76a66253 JM |
488 | } |
489 | ||
69b058c8 | 490 | static void spr_write_pir (DisasContext *ctx, int sprn, int gprn) |
3fc6c082 | 491 | { |
45d827d2 AJ |
492 | TCGv t0 = tcg_temp_new(); |
493 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); | |
494 | gen_store_spr(SPR_PIR, t0); | |
495 | tcg_temp_free(t0); | |
3fc6c082 | 496 | } |
76a66253 | 497 | #endif |
3fc6c082 | 498 | |
d34defbc | 499 | /* SPE specific registers */ |
69b058c8 | 500 | static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn) |
d34defbc AJ |
501 | { |
502 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1328c2bf | 503 | tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
d34defbc AJ |
504 | tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); |
505 | tcg_temp_free_i32(t0); | |
506 | } | |
507 | ||
69b058c8 | 508 | static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn) |
d34defbc AJ |
509 | { |
510 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
511 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); | |
1328c2bf | 512 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
d34defbc AJ |
513 | tcg_temp_free_i32(t0); |
514 | } | |
515 | ||
6f5d427d JM |
516 | #if !defined(CONFIG_USER_ONLY) |
517 | /* Callback used to write the exception vector base */ | |
69b058c8 | 518 | static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn) |
6f5d427d | 519 | { |
45d827d2 | 520 | TCGv t0 = tcg_temp_new(); |
1328c2bf | 521 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); |
45d827d2 | 522 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
1328c2bf | 523 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
45d827d2 | 524 | gen_store_spr(sprn, t0); |
69bd5820 | 525 | tcg_temp_free(t0); |
6f5d427d JM |
526 | } |
527 | ||
69b058c8 | 528 | static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn) |
6f5d427d | 529 | { |
e9205258 | 530 | int sprn_offs; |
6f5d427d JM |
531 | |
532 | if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { | |
e9205258 | 533 | sprn_offs = sprn - SPR_BOOKE_IVOR0; |
6f5d427d | 534 | } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { |
e9205258 AG |
535 | sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; |
536 | } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { | |
537 | sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; | |
6f5d427d JM |
538 | } else { |
539 | printf("Trying to write an unknown exception vector %d %03x\n", | |
540 | sprn, sprn); | |
e06fcd75 | 541 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
e9205258 | 542 | return; |
6f5d427d | 543 | } |
e9205258 AG |
544 | |
545 | TCGv t0 = tcg_temp_new(); | |
1328c2bf | 546 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); |
e9205258 | 547 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
1328c2bf | 548 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); |
e9205258 AG |
549 | gen_store_spr(sprn, t0); |
550 | tcg_temp_free(t0); | |
6f5d427d JM |
551 | } |
552 | #endif | |
553 | ||
cf8358c8 AJ |
554 | static inline void vscr_init (CPUPPCState *env, uint32_t val) |
555 | { | |
556 | env->vscr = val; | |
557 | /* Altivec always uses round-to-nearest */ | |
558 | set_float_rounding_mode(float_round_nearest_even, &env->vec_status); | |
559 | set_flush_to_zero(vscr_nj, &env->vec_status); | |
560 | } | |
561 | ||
d67d40ea DG |
562 | #ifdef CONFIG_USER_ONLY |
563 | #define spr_register_kvm(env, num, name, uea_read, uea_write, \ | |
564 | oea_read, oea_write, one_reg_id, initial_value) \ | |
565 | _spr_register(env, num, name, uea_read, uea_write, initial_value) | |
eb94268e BH |
566 | #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ |
567 | oea_read, oea_write, hea_read, hea_write, \ | |
568 | one_reg_id, initial_value) \ | |
569 | _spr_register(env, num, name, uea_read, uea_write, initial_value) | |
d67d40ea DG |
570 | #else |
571 | #if !defined(CONFIG_KVM) | |
572 | #define spr_register_kvm(env, num, name, uea_read, uea_write, \ | |
eb94268e BH |
573 | oea_read, oea_write, one_reg_id, initial_value) \ |
574 | _spr_register(env, num, name, uea_read, uea_write, \ | |
575 | oea_read, oea_write, oea_read, oea_write, initial_value) | |
576 | #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ | |
577 | oea_read, oea_write, hea_read, hea_write, \ | |
578 | one_reg_id, initial_value) \ | |
d67d40ea | 579 | _spr_register(env, num, name, uea_read, uea_write, \ |
eb94268e | 580 | oea_read, oea_write, hea_read, hea_write, initial_value) |
76a66253 | 581 | #else |
d67d40ea | 582 | #define spr_register_kvm(env, num, name, uea_read, uea_write, \ |
eb94268e BH |
583 | oea_read, oea_write, one_reg_id, initial_value) \ |
584 | _spr_register(env, num, name, uea_read, uea_write, \ | |
585 | oea_read, oea_write, oea_read, oea_write, \ | |
586 | one_reg_id, initial_value) | |
587 | #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ | |
588 | oea_read, oea_write, hea_read, hea_write, \ | |
589 | one_reg_id, initial_value) \ | |
d67d40ea | 590 | _spr_register(env, num, name, uea_read, uea_write, \ |
eb94268e BH |
591 | oea_read, oea_write, hea_read, hea_write, \ |
592 | one_reg_id, initial_value) | |
d67d40ea DG |
593 | #endif |
594 | #endif | |
595 | ||
596 | #define spr_register(env, num, name, uea_read, uea_write, \ | |
597 | oea_read, oea_write, initial_value) \ | |
598 | spr_register_kvm(env, num, name, uea_read, uea_write, \ | |
599 | oea_read, oea_write, 0, initial_value) | |
600 | ||
eb94268e BH |
601 | #define spr_register_hv(env, num, name, uea_read, uea_write, \ |
602 | oea_read, oea_write, hea_read, hea_write, \ | |
603 | initial_value) \ | |
604 | spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ | |
605 | oea_read, oea_write, hea_read, hea_write, \ | |
606 | 0, initial_value) | |
607 | ||
d67d40ea | 608 | static inline void _spr_register(CPUPPCState *env, int num, |
b55266b5 | 609 | const char *name, |
69b058c8 PB |
610 | void (*uea_read)(DisasContext *ctx, int gprn, int sprn), |
611 | void (*uea_write)(DisasContext *ctx, int sprn, int gprn), | |
d67d40ea DG |
612 | #if !defined(CONFIG_USER_ONLY) |
613 | ||
69b058c8 PB |
614 | void (*oea_read)(DisasContext *ctx, int gprn, int sprn), |
615 | void (*oea_write)(DisasContext *ctx, int sprn, int gprn), | |
eb94268e BH |
616 | void (*hea_read)(DisasContext *opaque, int gprn, int sprn), |
617 | void (*hea_write)(DisasContext *opaque, int sprn, int gprn), | |
76a66253 | 618 | #endif |
d67d40ea DG |
619 | #if defined(CONFIG_KVM) |
620 | uint64_t one_reg_id, | |
621 | #endif | |
622 | target_ulong initial_value) | |
3fc6c082 | 623 | { |
c227f099 | 624 | ppc_spr_t *spr; |
3fc6c082 FB |
625 | |
626 | spr = &env->spr_cb[num]; | |
627 | if (spr->name != NULL ||env-> spr[num] != 0x00000000 || | |
76a66253 JM |
628 | #if !defined(CONFIG_USER_ONLY) |
629 | spr->oea_read != NULL || spr->oea_write != NULL || | |
630 | #endif | |
631 | spr->uea_read != NULL || spr->uea_write != NULL) { | |
3fc6c082 FB |
632 | printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); |
633 | exit(1); | |
634 | } | |
635 | #if defined(PPC_DEBUG_SPR) | |
90e189ec BS |
636 | printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, |
637 | name, initial_value); | |
3fc6c082 FB |
638 | #endif |
639 | spr->name = name; | |
640 | spr->uea_read = uea_read; | |
641 | spr->uea_write = uea_write; | |
76a66253 | 642 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
643 | spr->oea_read = oea_read; |
644 | spr->oea_write = oea_write; | |
eb94268e BH |
645 | spr->hea_read = hea_read; |
646 | spr->hea_write = hea_write; | |
7a7c05d7 AK |
647 | #endif |
648 | #if defined(CONFIG_KVM) | |
649 | spr->one_reg_id = one_reg_id, | |
76a66253 | 650 | #endif |
d197fdbc | 651 | env->spr[num] = spr->default_value = initial_value; |
3fc6c082 FB |
652 | } |
653 | ||
654 | /* Generic PowerPC SPRs */ | |
655 | static void gen_spr_generic (CPUPPCState *env) | |
656 | { | |
657 | /* Integer processing */ | |
658 | spr_register(env, SPR_XER, "XER", | |
659 | &spr_read_xer, &spr_write_xer, | |
660 | &spr_read_xer, &spr_write_xer, | |
661 | 0x00000000); | |
662 | /* Branch contol */ | |
663 | spr_register(env, SPR_LR, "LR", | |
664 | &spr_read_lr, &spr_write_lr, | |
665 | &spr_read_lr, &spr_write_lr, | |
666 | 0x00000000); | |
667 | spr_register(env, SPR_CTR, "CTR", | |
668 | &spr_read_ctr, &spr_write_ctr, | |
669 | &spr_read_ctr, &spr_write_ctr, | |
670 | 0x00000000); | |
671 | /* Interrupt processing */ | |
672 | spr_register(env, SPR_SRR0, "SRR0", | |
673 | SPR_NOACCESS, SPR_NOACCESS, | |
674 | &spr_read_generic, &spr_write_generic, | |
675 | 0x00000000); | |
676 | spr_register(env, SPR_SRR1, "SRR1", | |
677 | SPR_NOACCESS, SPR_NOACCESS, | |
678 | &spr_read_generic, &spr_write_generic, | |
679 | 0x00000000); | |
680 | /* Processor control */ | |
681 | spr_register(env, SPR_SPRG0, "SPRG0", | |
682 | SPR_NOACCESS, SPR_NOACCESS, | |
683 | &spr_read_generic, &spr_write_generic, | |
684 | 0x00000000); | |
685 | spr_register(env, SPR_SPRG1, "SPRG1", | |
686 | SPR_NOACCESS, SPR_NOACCESS, | |
687 | &spr_read_generic, &spr_write_generic, | |
688 | 0x00000000); | |
689 | spr_register(env, SPR_SPRG2, "SPRG2", | |
690 | SPR_NOACCESS, SPR_NOACCESS, | |
691 | &spr_read_generic, &spr_write_generic, | |
692 | 0x00000000); | |
693 | spr_register(env, SPR_SPRG3, "SPRG3", | |
694 | SPR_NOACCESS, SPR_NOACCESS, | |
695 | &spr_read_generic, &spr_write_generic, | |
696 | 0x00000000); | |
697 | } | |
698 | ||
699 | /* SPR common to all non-embedded PowerPC, including 601 */ | |
700 | static void gen_spr_ne_601 (CPUPPCState *env) | |
701 | { | |
702 | /* Exception processing */ | |
d67d40ea DG |
703 | spr_register_kvm(env, SPR_DSISR, "DSISR", |
704 | SPR_NOACCESS, SPR_NOACCESS, | |
705 | &spr_read_generic, &spr_write_generic, | |
706 | KVM_REG_PPC_DSISR, 0x00000000); | |
707 | spr_register_kvm(env, SPR_DAR, "DAR", | |
708 | SPR_NOACCESS, SPR_NOACCESS, | |
709 | &spr_read_generic, &spr_write_generic, | |
710 | KVM_REG_PPC_DAR, 0x00000000); | |
3fc6c082 FB |
711 | /* Timer */ |
712 | spr_register(env, SPR_DECR, "DECR", | |
713 | SPR_NOACCESS, SPR_NOACCESS, | |
714 | &spr_read_decr, &spr_write_decr, | |
715 | 0x00000000); | |
716 | /* Memory management */ | |
717 | spr_register(env, SPR_SDR1, "SDR1", | |
718 | SPR_NOACCESS, SPR_NOACCESS, | |
bb593904 | 719 | &spr_read_generic, &spr_write_sdr1, |
3fc6c082 FB |
720 | 0x00000000); |
721 | } | |
722 | ||
723 | /* BATs 0-3 */ | |
724 | static void gen_low_BATs (CPUPPCState *env) | |
725 | { | |
f2e63a42 | 726 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
727 | spr_register(env, SPR_IBAT0U, "IBAT0U", |
728 | SPR_NOACCESS, SPR_NOACCESS, | |
729 | &spr_read_ibat, &spr_write_ibatu, | |
730 | 0x00000000); | |
731 | spr_register(env, SPR_IBAT0L, "IBAT0L", | |
732 | SPR_NOACCESS, SPR_NOACCESS, | |
733 | &spr_read_ibat, &spr_write_ibatl, | |
734 | 0x00000000); | |
735 | spr_register(env, SPR_IBAT1U, "IBAT1U", | |
736 | SPR_NOACCESS, SPR_NOACCESS, | |
737 | &spr_read_ibat, &spr_write_ibatu, | |
738 | 0x00000000); | |
739 | spr_register(env, SPR_IBAT1L, "IBAT1L", | |
740 | SPR_NOACCESS, SPR_NOACCESS, | |
741 | &spr_read_ibat, &spr_write_ibatl, | |
742 | 0x00000000); | |
743 | spr_register(env, SPR_IBAT2U, "IBAT2U", | |
744 | SPR_NOACCESS, SPR_NOACCESS, | |
745 | &spr_read_ibat, &spr_write_ibatu, | |
746 | 0x00000000); | |
747 | spr_register(env, SPR_IBAT2L, "IBAT2L", | |
748 | SPR_NOACCESS, SPR_NOACCESS, | |
749 | &spr_read_ibat, &spr_write_ibatl, | |
750 | 0x00000000); | |
751 | spr_register(env, SPR_IBAT3U, "IBAT3U", | |
752 | SPR_NOACCESS, SPR_NOACCESS, | |
753 | &spr_read_ibat, &spr_write_ibatu, | |
754 | 0x00000000); | |
755 | spr_register(env, SPR_IBAT3L, "IBAT3L", | |
756 | SPR_NOACCESS, SPR_NOACCESS, | |
757 | &spr_read_ibat, &spr_write_ibatl, | |
758 | 0x00000000); | |
759 | spr_register(env, SPR_DBAT0U, "DBAT0U", | |
760 | SPR_NOACCESS, SPR_NOACCESS, | |
761 | &spr_read_dbat, &spr_write_dbatu, | |
762 | 0x00000000); | |
763 | spr_register(env, SPR_DBAT0L, "DBAT0L", | |
764 | SPR_NOACCESS, SPR_NOACCESS, | |
765 | &spr_read_dbat, &spr_write_dbatl, | |
766 | 0x00000000); | |
767 | spr_register(env, SPR_DBAT1U, "DBAT1U", | |
768 | SPR_NOACCESS, SPR_NOACCESS, | |
769 | &spr_read_dbat, &spr_write_dbatu, | |
770 | 0x00000000); | |
771 | spr_register(env, SPR_DBAT1L, "DBAT1L", | |
772 | SPR_NOACCESS, SPR_NOACCESS, | |
773 | &spr_read_dbat, &spr_write_dbatl, | |
774 | 0x00000000); | |
775 | spr_register(env, SPR_DBAT2U, "DBAT2U", | |
776 | SPR_NOACCESS, SPR_NOACCESS, | |
777 | &spr_read_dbat, &spr_write_dbatu, | |
778 | 0x00000000); | |
779 | spr_register(env, SPR_DBAT2L, "DBAT2L", | |
780 | SPR_NOACCESS, SPR_NOACCESS, | |
781 | &spr_read_dbat, &spr_write_dbatl, | |
782 | 0x00000000); | |
783 | spr_register(env, SPR_DBAT3U, "DBAT3U", | |
784 | SPR_NOACCESS, SPR_NOACCESS, | |
785 | &spr_read_dbat, &spr_write_dbatu, | |
786 | 0x00000000); | |
787 | spr_register(env, SPR_DBAT3L, "DBAT3L", | |
788 | SPR_NOACCESS, SPR_NOACCESS, | |
789 | &spr_read_dbat, &spr_write_dbatl, | |
790 | 0x00000000); | |
a750fc0b | 791 | env->nb_BATs += 4; |
f2e63a42 | 792 | #endif |
3fc6c082 FB |
793 | } |
794 | ||
795 | /* BATs 4-7 */ | |
796 | static void gen_high_BATs (CPUPPCState *env) | |
797 | { | |
f2e63a42 | 798 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
799 | spr_register(env, SPR_IBAT4U, "IBAT4U", |
800 | SPR_NOACCESS, SPR_NOACCESS, | |
801 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
802 | 0x00000000); | |
803 | spr_register(env, SPR_IBAT4L, "IBAT4L", | |
804 | SPR_NOACCESS, SPR_NOACCESS, | |
805 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
806 | 0x00000000); | |
807 | spr_register(env, SPR_IBAT5U, "IBAT5U", | |
808 | SPR_NOACCESS, SPR_NOACCESS, | |
809 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
810 | 0x00000000); | |
811 | spr_register(env, SPR_IBAT5L, "IBAT5L", | |
812 | SPR_NOACCESS, SPR_NOACCESS, | |
813 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
814 | 0x00000000); | |
815 | spr_register(env, SPR_IBAT6U, "IBAT6U", | |
816 | SPR_NOACCESS, SPR_NOACCESS, | |
817 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
818 | 0x00000000); | |
819 | spr_register(env, SPR_IBAT6L, "IBAT6L", | |
820 | SPR_NOACCESS, SPR_NOACCESS, | |
821 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
822 | 0x00000000); | |
823 | spr_register(env, SPR_IBAT7U, "IBAT7U", | |
824 | SPR_NOACCESS, SPR_NOACCESS, | |
825 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
826 | 0x00000000); | |
827 | spr_register(env, SPR_IBAT7L, "IBAT7L", | |
828 | SPR_NOACCESS, SPR_NOACCESS, | |
829 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
830 | 0x00000000); | |
831 | spr_register(env, SPR_DBAT4U, "DBAT4U", | |
832 | SPR_NOACCESS, SPR_NOACCESS, | |
833 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
834 | 0x00000000); | |
835 | spr_register(env, SPR_DBAT4L, "DBAT4L", | |
836 | SPR_NOACCESS, SPR_NOACCESS, | |
837 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
838 | 0x00000000); | |
839 | spr_register(env, SPR_DBAT5U, "DBAT5U", | |
840 | SPR_NOACCESS, SPR_NOACCESS, | |
841 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
842 | 0x00000000); | |
843 | spr_register(env, SPR_DBAT5L, "DBAT5L", | |
844 | SPR_NOACCESS, SPR_NOACCESS, | |
845 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
846 | 0x00000000); | |
847 | spr_register(env, SPR_DBAT6U, "DBAT6U", | |
848 | SPR_NOACCESS, SPR_NOACCESS, | |
849 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
850 | 0x00000000); | |
851 | spr_register(env, SPR_DBAT6L, "DBAT6L", | |
852 | SPR_NOACCESS, SPR_NOACCESS, | |
853 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
854 | 0x00000000); | |
855 | spr_register(env, SPR_DBAT7U, "DBAT7U", | |
856 | SPR_NOACCESS, SPR_NOACCESS, | |
857 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
858 | 0x00000000); | |
859 | spr_register(env, SPR_DBAT7L, "DBAT7L", | |
860 | SPR_NOACCESS, SPR_NOACCESS, | |
861 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
862 | 0x00000000); | |
a750fc0b | 863 | env->nb_BATs += 4; |
f2e63a42 | 864 | #endif |
3fc6c082 FB |
865 | } |
866 | ||
867 | /* Generic PowerPC time base */ | |
868 | static void gen_tbl (CPUPPCState *env) | |
869 | { | |
870 | spr_register(env, SPR_VTBL, "TBL", | |
871 | &spr_read_tbl, SPR_NOACCESS, | |
872 | &spr_read_tbl, SPR_NOACCESS, | |
873 | 0x00000000); | |
874 | spr_register(env, SPR_TBL, "TBL", | |
de6a1dec DI |
875 | &spr_read_tbl, SPR_NOACCESS, |
876 | &spr_read_tbl, &spr_write_tbl, | |
3fc6c082 FB |
877 | 0x00000000); |
878 | spr_register(env, SPR_VTBU, "TBU", | |
879 | &spr_read_tbu, SPR_NOACCESS, | |
880 | &spr_read_tbu, SPR_NOACCESS, | |
881 | 0x00000000); | |
882 | spr_register(env, SPR_TBU, "TBU", | |
de6a1dec DI |
883 | &spr_read_tbu, SPR_NOACCESS, |
884 | &spr_read_tbu, &spr_write_tbu, | |
3fc6c082 FB |
885 | 0x00000000); |
886 | } | |
887 | ||
76a66253 JM |
888 | /* Softare table search registers */ |
889 | static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) | |
890 | { | |
f2e63a42 | 891 | #if !defined(CONFIG_USER_ONLY) |
76a66253 JM |
892 | env->nb_tlb = nb_tlbs; |
893 | env->nb_ways = nb_ways; | |
894 | env->id_tlbs = 1; | |
1c53accc | 895 | env->tlb_type = TLB_6XX; |
76a66253 JM |
896 | spr_register(env, SPR_DMISS, "DMISS", |
897 | SPR_NOACCESS, SPR_NOACCESS, | |
898 | &spr_read_generic, SPR_NOACCESS, | |
899 | 0x00000000); | |
900 | spr_register(env, SPR_DCMP, "DCMP", | |
901 | SPR_NOACCESS, SPR_NOACCESS, | |
902 | &spr_read_generic, SPR_NOACCESS, | |
903 | 0x00000000); | |
904 | spr_register(env, SPR_HASH1, "HASH1", | |
905 | SPR_NOACCESS, SPR_NOACCESS, | |
906 | &spr_read_generic, SPR_NOACCESS, | |
907 | 0x00000000); | |
908 | spr_register(env, SPR_HASH2, "HASH2", | |
909 | SPR_NOACCESS, SPR_NOACCESS, | |
910 | &spr_read_generic, SPR_NOACCESS, | |
911 | 0x00000000); | |
912 | spr_register(env, SPR_IMISS, "IMISS", | |
913 | SPR_NOACCESS, SPR_NOACCESS, | |
914 | &spr_read_generic, SPR_NOACCESS, | |
915 | 0x00000000); | |
916 | spr_register(env, SPR_ICMP, "ICMP", | |
917 | SPR_NOACCESS, SPR_NOACCESS, | |
918 | &spr_read_generic, SPR_NOACCESS, | |
919 | 0x00000000); | |
920 | spr_register(env, SPR_RPA, "RPA", | |
921 | SPR_NOACCESS, SPR_NOACCESS, | |
922 | &spr_read_generic, &spr_write_generic, | |
923 | 0x00000000); | |
f2e63a42 | 924 | #endif |
76a66253 JM |
925 | } |
926 | ||
927 | /* SPR common to MPC755 and G2 */ | |
928 | static void gen_spr_G2_755 (CPUPPCState *env) | |
929 | { | |
930 | /* SGPRs */ | |
931 | spr_register(env, SPR_SPRG4, "SPRG4", | |
932 | SPR_NOACCESS, SPR_NOACCESS, | |
933 | &spr_read_generic, &spr_write_generic, | |
934 | 0x00000000); | |
935 | spr_register(env, SPR_SPRG5, "SPRG5", | |
936 | SPR_NOACCESS, SPR_NOACCESS, | |
937 | &spr_read_generic, &spr_write_generic, | |
938 | 0x00000000); | |
939 | spr_register(env, SPR_SPRG6, "SPRG6", | |
940 | SPR_NOACCESS, SPR_NOACCESS, | |
941 | &spr_read_generic, &spr_write_generic, | |
942 | 0x00000000); | |
943 | spr_register(env, SPR_SPRG7, "SPRG7", | |
944 | SPR_NOACCESS, SPR_NOACCESS, | |
945 | &spr_read_generic, &spr_write_generic, | |
946 | 0x00000000); | |
76a66253 JM |
947 | } |
948 | ||
3fc6c082 FB |
949 | /* SPR common to all 7xx PowerPC implementations */ |
950 | static void gen_spr_7xx (CPUPPCState *env) | |
951 | { | |
952 | /* Breakpoints */ | |
953 | /* XXX : not implemented */ | |
d67d40ea DG |
954 | spr_register_kvm(env, SPR_DABR, "DABR", |
955 | SPR_NOACCESS, SPR_NOACCESS, | |
956 | &spr_read_generic, &spr_write_generic, | |
957 | KVM_REG_PPC_DABR, 0x00000000); | |
3fc6c082 FB |
958 | /* XXX : not implemented */ |
959 | spr_register(env, SPR_IABR, "IABR", | |
960 | SPR_NOACCESS, SPR_NOACCESS, | |
961 | &spr_read_generic, &spr_write_generic, | |
962 | 0x00000000); | |
963 | /* Cache management */ | |
964 | /* XXX : not implemented */ | |
965 | spr_register(env, SPR_ICTC, "ICTC", | |
966 | SPR_NOACCESS, SPR_NOACCESS, | |
967 | &spr_read_generic, &spr_write_generic, | |
968 | 0x00000000); | |
969 | /* Performance monitors */ | |
970 | /* XXX : not implemented */ | |
cb8b8bf8 | 971 | spr_register(env, SPR_7XX_MMCR0, "MMCR0", |
3fc6c082 FB |
972 | SPR_NOACCESS, SPR_NOACCESS, |
973 | &spr_read_generic, &spr_write_generic, | |
974 | 0x00000000); | |
975 | /* XXX : not implemented */ | |
cb8b8bf8 | 976 | spr_register(env, SPR_7XX_MMCR1, "MMCR1", |
3fc6c082 FB |
977 | SPR_NOACCESS, SPR_NOACCESS, |
978 | &spr_read_generic, &spr_write_generic, | |
979 | 0x00000000); | |
980 | /* XXX : not implemented */ | |
cb8b8bf8 | 981 | spr_register(env, SPR_7XX_PMC1, "PMC1", |
3fc6c082 FB |
982 | SPR_NOACCESS, SPR_NOACCESS, |
983 | &spr_read_generic, &spr_write_generic, | |
984 | 0x00000000); | |
985 | /* XXX : not implemented */ | |
cb8b8bf8 | 986 | spr_register(env, SPR_7XX_PMC2, "PMC2", |
3fc6c082 FB |
987 | SPR_NOACCESS, SPR_NOACCESS, |
988 | &spr_read_generic, &spr_write_generic, | |
989 | 0x00000000); | |
990 | /* XXX : not implemented */ | |
cb8b8bf8 | 991 | spr_register(env, SPR_7XX_PMC3, "PMC3", |
3fc6c082 FB |
992 | SPR_NOACCESS, SPR_NOACCESS, |
993 | &spr_read_generic, &spr_write_generic, | |
994 | 0x00000000); | |
995 | /* XXX : not implemented */ | |
cb8b8bf8 | 996 | spr_register(env, SPR_7XX_PMC4, "PMC4", |
3fc6c082 FB |
997 | SPR_NOACCESS, SPR_NOACCESS, |
998 | &spr_read_generic, &spr_write_generic, | |
999 | 0x00000000); | |
1000 | /* XXX : not implemented */ | |
cb8b8bf8 | 1001 | spr_register(env, SPR_7XX_SIAR, "SIAR", |
3fc6c082 FB |
1002 | SPR_NOACCESS, SPR_NOACCESS, |
1003 | &spr_read_generic, SPR_NOACCESS, | |
1004 | 0x00000000); | |
578bb252 | 1005 | /* XXX : not implemented */ |
cb8b8bf8 | 1006 | spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", |
3fc6c082 FB |
1007 | &spr_read_ureg, SPR_NOACCESS, |
1008 | &spr_read_ureg, SPR_NOACCESS, | |
1009 | 0x00000000); | |
578bb252 | 1010 | /* XXX : not implemented */ |
cb8b8bf8 | 1011 | spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", |
3fc6c082 FB |
1012 | &spr_read_ureg, SPR_NOACCESS, |
1013 | &spr_read_ureg, SPR_NOACCESS, | |
1014 | 0x00000000); | |
578bb252 | 1015 | /* XXX : not implemented */ |
cb8b8bf8 | 1016 | spr_register(env, SPR_7XX_UPMC1, "UPMC1", |
3fc6c082 FB |
1017 | &spr_read_ureg, SPR_NOACCESS, |
1018 | &spr_read_ureg, SPR_NOACCESS, | |
1019 | 0x00000000); | |
578bb252 | 1020 | /* XXX : not implemented */ |
cb8b8bf8 | 1021 | spr_register(env, SPR_7XX_UPMC2, "UPMC2", |
3fc6c082 FB |
1022 | &spr_read_ureg, SPR_NOACCESS, |
1023 | &spr_read_ureg, SPR_NOACCESS, | |
1024 | 0x00000000); | |
578bb252 | 1025 | /* XXX : not implemented */ |
cb8b8bf8 | 1026 | spr_register(env, SPR_7XX_UPMC3, "UPMC3", |
3fc6c082 FB |
1027 | &spr_read_ureg, SPR_NOACCESS, |
1028 | &spr_read_ureg, SPR_NOACCESS, | |
1029 | 0x00000000); | |
578bb252 | 1030 | /* XXX : not implemented */ |
cb8b8bf8 | 1031 | spr_register(env, SPR_7XX_UPMC4, "UPMC4", |
3fc6c082 FB |
1032 | &spr_read_ureg, SPR_NOACCESS, |
1033 | &spr_read_ureg, SPR_NOACCESS, | |
1034 | 0x00000000); | |
578bb252 | 1035 | /* XXX : not implemented */ |
cb8b8bf8 | 1036 | spr_register(env, SPR_7XX_USIAR, "USIAR", |
3fc6c082 FB |
1037 | &spr_read_ureg, SPR_NOACCESS, |
1038 | &spr_read_ureg, SPR_NOACCESS, | |
1039 | 0x00000000); | |
a750fc0b | 1040 | /* External access control */ |
3fc6c082 | 1041 | /* XXX : not implemented */ |
a750fc0b | 1042 | spr_register(env, SPR_EAR, "EAR", |
3fc6c082 FB |
1043 | SPR_NOACCESS, SPR_NOACCESS, |
1044 | &spr_read_generic, &spr_write_generic, | |
1045 | 0x00000000); | |
a750fc0b JM |
1046 | } |
1047 | ||
f80872e2 DG |
1048 | #ifdef TARGET_PPC64 |
1049 | #ifndef CONFIG_USER_ONLY | |
97eaf30e | 1050 | static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) |
f80872e2 | 1051 | { |
97eaf30e BH |
1052 | TCGv t0 = tcg_temp_new(); |
1053 | TCGv t1 = tcg_temp_new(); | |
1054 | TCGv t2 = tcg_temp_new(); | |
f80872e2 | 1055 | |
97eaf30e BH |
1056 | /* Note, the HV=1 PR=0 case is handled earlier by simply using |
1057 | * spr_write_generic for HV mode in the SPR table | |
1058 | */ | |
1059 | ||
1060 | /* Build insertion mask into t1 based on context */ | |
1061 | if (ctx->pr) { | |
1062 | gen_load_spr(t1, SPR_UAMOR); | |
1063 | } else { | |
1064 | gen_load_spr(t1, SPR_AMOR); | |
1065 | } | |
1066 | ||
1067 | /* Mask new bits into t2 */ | |
1068 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
1069 | ||
1070 | /* Load AMR and clear new bits in t0 */ | |
1071 | gen_load_spr(t0, SPR_AMR); | |
1072 | tcg_gen_andc_tl(t0, t0, t1); | |
1073 | ||
1074 | /* Or'in new bits and write it out */ | |
1075 | tcg_gen_or_tl(t0, t0, t2); | |
1076 | gen_store_spr(SPR_AMR, t0); | |
f80872e2 | 1077 | spr_store_dump_spr(SPR_AMR); |
97eaf30e BH |
1078 | |
1079 | tcg_temp_free(t0); | |
1080 | tcg_temp_free(t1); | |
1081 | tcg_temp_free(t2); | |
f80872e2 DG |
1082 | } |
1083 | ||
97eaf30e | 1084 | static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) |
f80872e2 DG |
1085 | { |
1086 | TCGv t0 = tcg_temp_new(); | |
97eaf30e BH |
1087 | TCGv t1 = tcg_temp_new(); |
1088 | TCGv t2 = tcg_temp_new(); | |
1089 | ||
1090 | /* Note, the HV=1 case is handled earlier by simply using | |
1091 | * spr_write_generic for HV mode in the SPR table | |
1092 | */ | |
f80872e2 | 1093 | |
97eaf30e BH |
1094 | /* Build insertion mask into t1 based on context */ |
1095 | gen_load_spr(t1, SPR_AMOR); | |
1096 | ||
1097 | /* Mask new bits into t2 */ | |
1098 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
1099 | ||
1100 | /* Load AMR and clear new bits in t0 */ | |
f80872e2 | 1101 | gen_load_spr(t0, SPR_UAMOR); |
97eaf30e BH |
1102 | tcg_gen_andc_tl(t0, t0, t1); |
1103 | ||
1104 | /* Or'in new bits and write it out */ | |
1105 | tcg_gen_or_tl(t0, t0, t2); | |
1106 | gen_store_spr(SPR_UAMOR, t0); | |
1107 | spr_store_dump_spr(SPR_UAMOR); | |
1108 | ||
1109 | tcg_temp_free(t0); | |
1110 | tcg_temp_free(t1); | |
1111 | tcg_temp_free(t2); | |
f80872e2 | 1112 | } |
a6eabb9e BH |
1113 | |
1114 | static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) | |
1115 | { | |
1116 | TCGv t0 = tcg_temp_new(); | |
1117 | TCGv t1 = tcg_temp_new(); | |
1118 | TCGv t2 = tcg_temp_new(); | |
1119 | ||
1120 | /* Note, the HV=1 case is handled earlier by simply using | |
1121 | * spr_write_generic for HV mode in the SPR table | |
1122 | */ | |
1123 | ||
1124 | /* Build insertion mask into t1 based on context */ | |
1125 | gen_load_spr(t1, SPR_AMOR); | |
1126 | ||
1127 | /* Mask new bits into t2 */ | |
1128 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
1129 | ||
1130 | /* Load AMR and clear new bits in t0 */ | |
1131 | gen_load_spr(t0, SPR_IAMR); | |
1132 | tcg_gen_andc_tl(t0, t0, t1); | |
1133 | ||
1134 | /* Or'in new bits and write it out */ | |
1135 | tcg_gen_or_tl(t0, t0, t2); | |
1136 | gen_store_spr(SPR_IAMR, t0); | |
1137 | spr_store_dump_spr(SPR_IAMR); | |
1138 | ||
1139 | tcg_temp_free(t0); | |
1140 | tcg_temp_free(t1); | |
1141 | tcg_temp_free(t2); | |
1142 | } | |
f80872e2 DG |
1143 | #endif /* CONFIG_USER_ONLY */ |
1144 | ||
a6eabb9e | 1145 | static void gen_spr_amr(CPUPPCState *env, bool has_iamr) |
f80872e2 DG |
1146 | { |
1147 | #ifndef CONFIG_USER_ONLY | |
1148 | /* Virtual Page Class Key protection */ | |
1149 | /* The AMR is accessible either via SPR 13 or SPR 29. 13 is | |
1150 | * userspace accessible, 29 is privileged. So we only need to set | |
1151 | * the kvm ONE_REG id on one of them, we use 29 */ | |
1152 | spr_register(env, SPR_UAMR, "UAMR", | |
97eaf30e BH |
1153 | &spr_read_generic, &spr_write_amr, |
1154 | &spr_read_generic, &spr_write_amr, | |
f80872e2 | 1155 | 0); |
97eaf30e | 1156 | spr_register_kvm_hv(env, SPR_AMR, "AMR", |
f80872e2 | 1157 | SPR_NOACCESS, SPR_NOACCESS, |
97eaf30e | 1158 | &spr_read_generic, &spr_write_amr, |
f80872e2 | 1159 | &spr_read_generic, &spr_write_generic, |
0dc083fe | 1160 | KVM_REG_PPC_AMR, 0); |
97eaf30e | 1161 | spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", |
f80872e2 | 1162 | SPR_NOACCESS, SPR_NOACCESS, |
97eaf30e | 1163 | &spr_read_generic, &spr_write_uamor, |
f80872e2 DG |
1164 | &spr_read_generic, &spr_write_generic, |
1165 | KVM_REG_PPC_UAMOR, 0); | |
f401dd32 BH |
1166 | spr_register_hv(env, SPR_AMOR, "AMOR", |
1167 | SPR_NOACCESS, SPR_NOACCESS, | |
1168 | SPR_NOACCESS, SPR_NOACCESS, | |
1169 | &spr_read_generic, &spr_write_generic, | |
1170 | 0); | |
a6eabb9e BH |
1171 | if (has_iamr) { |
1172 | spr_register_kvm_hv(env, SPR_IAMR, "IAMR", | |
1173 | SPR_NOACCESS, SPR_NOACCESS, | |
1174 | &spr_read_generic, &spr_write_iamr, | |
1175 | &spr_read_generic, &spr_write_generic, | |
1176 | KVM_REG_PPC_IAMR, 0); | |
1177 | } | |
f80872e2 DG |
1178 | #endif /* !CONFIG_USER_ONLY */ |
1179 | } | |
1180 | #endif /* TARGET_PPC64 */ | |
1181 | ||
f0278900 BH |
1182 | #ifndef CONFIG_USER_ONLY |
1183 | static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) | |
1184 | { | |
1185 | gen_helper_fixup_thrm(cpu_env); | |
1186 | gen_load_spr(cpu_gpr[gprn], sprn); | |
1187 | spr_load_dump_spr(sprn); | |
1188 | } | |
1189 | #endif /* !CONFIG_USER_ONLY */ | |
1190 | ||
a750fc0b JM |
1191 | static void gen_spr_thrm (CPUPPCState *env) |
1192 | { | |
1193 | /* Thermal management */ | |
3fc6c082 | 1194 | /* XXX : not implemented */ |
a750fc0b | 1195 | spr_register(env, SPR_THRM1, "THRM1", |
3fc6c082 | 1196 | SPR_NOACCESS, SPR_NOACCESS, |
f0278900 | 1197 | &spr_read_thrm, &spr_write_generic, |
3fc6c082 FB |
1198 | 0x00000000); |
1199 | /* XXX : not implemented */ | |
a750fc0b | 1200 | spr_register(env, SPR_THRM2, "THRM2", |
3fc6c082 | 1201 | SPR_NOACCESS, SPR_NOACCESS, |
f0278900 | 1202 | &spr_read_thrm, &spr_write_generic, |
3fc6c082 | 1203 | 0x00000000); |
3fc6c082 | 1204 | /* XXX : not implemented */ |
a750fc0b | 1205 | spr_register(env, SPR_THRM3, "THRM3", |
3fc6c082 | 1206 | SPR_NOACCESS, SPR_NOACCESS, |
f0278900 | 1207 | &spr_read_thrm, &spr_write_generic, |
3fc6c082 FB |
1208 | 0x00000000); |
1209 | } | |
1210 | ||
1211 | /* SPR specific to PowerPC 604 implementation */ | |
1212 | static void gen_spr_604 (CPUPPCState *env) | |
1213 | { | |
1214 | /* Processor identification */ | |
1215 | spr_register(env, SPR_PIR, "PIR", | |
1216 | SPR_NOACCESS, SPR_NOACCESS, | |
1217 | &spr_read_generic, &spr_write_pir, | |
1218 | 0x00000000); | |
1219 | /* Breakpoints */ | |
1220 | /* XXX : not implemented */ | |
1221 | spr_register(env, SPR_IABR, "IABR", | |
1222 | SPR_NOACCESS, SPR_NOACCESS, | |
1223 | &spr_read_generic, &spr_write_generic, | |
1224 | 0x00000000); | |
1225 | /* XXX : not implemented */ | |
d67d40ea DG |
1226 | spr_register_kvm(env, SPR_DABR, "DABR", |
1227 | SPR_NOACCESS, SPR_NOACCESS, | |
1228 | &spr_read_generic, &spr_write_generic, | |
1229 | KVM_REG_PPC_DABR, 0x00000000); | |
3fc6c082 FB |
1230 | /* Performance counters */ |
1231 | /* XXX : not implemented */ | |
cb8b8bf8 | 1232 | spr_register(env, SPR_7XX_MMCR0, "MMCR0", |
3fc6c082 FB |
1233 | SPR_NOACCESS, SPR_NOACCESS, |
1234 | &spr_read_generic, &spr_write_generic, | |
1235 | 0x00000000); | |
1236 | /* XXX : not implemented */ | |
cb8b8bf8 | 1237 | spr_register(env, SPR_7XX_PMC1, "PMC1", |
3fc6c082 FB |
1238 | SPR_NOACCESS, SPR_NOACCESS, |
1239 | &spr_read_generic, &spr_write_generic, | |
1240 | 0x00000000); | |
1241 | /* XXX : not implemented */ | |
cb8b8bf8 | 1242 | spr_register(env, SPR_7XX_PMC2, "PMC2", |
3fc6c082 FB |
1243 | SPR_NOACCESS, SPR_NOACCESS, |
1244 | &spr_read_generic, &spr_write_generic, | |
1245 | 0x00000000); | |
1246 | /* XXX : not implemented */ | |
cb8b8bf8 | 1247 | spr_register(env, SPR_7XX_SIAR, "SIAR", |
3fc6c082 FB |
1248 | SPR_NOACCESS, SPR_NOACCESS, |
1249 | &spr_read_generic, SPR_NOACCESS, | |
1250 | 0x00000000); | |
1251 | /* XXX : not implemented */ | |
1252 | spr_register(env, SPR_SDA, "SDA", | |
1253 | SPR_NOACCESS, SPR_NOACCESS, | |
1254 | &spr_read_generic, SPR_NOACCESS, | |
1255 | 0x00000000); | |
1256 | /* External access control */ | |
1257 | /* XXX : not implemented */ | |
1258 | spr_register(env, SPR_EAR, "EAR", | |
1259 | SPR_NOACCESS, SPR_NOACCESS, | |
1260 | &spr_read_generic, &spr_write_generic, | |
1261 | 0x00000000); | |
1262 | } | |
1263 | ||
76a66253 JM |
1264 | /* SPR specific to PowerPC 603 implementation */ |
1265 | static void gen_spr_603 (CPUPPCState *env) | |
3fc6c082 | 1266 | { |
76a66253 JM |
1267 | /* External access control */ |
1268 | /* XXX : not implemented */ | |
1269 | spr_register(env, SPR_EAR, "EAR", | |
3fc6c082 | 1270 | SPR_NOACCESS, SPR_NOACCESS, |
76a66253 JM |
1271 | &spr_read_generic, &spr_write_generic, |
1272 | 0x00000000); | |
2bc17322 FC |
1273 | /* Breakpoints */ |
1274 | /* XXX : not implemented */ | |
1275 | spr_register(env, SPR_IABR, "IABR", | |
1276 | SPR_NOACCESS, SPR_NOACCESS, | |
1277 | &spr_read_generic, &spr_write_generic, | |
1278 | 0x00000000); | |
1279 | ||
3fc6c082 FB |
1280 | } |
1281 | ||
76a66253 JM |
1282 | /* SPR specific to PowerPC G2 implementation */ |
1283 | static void gen_spr_G2 (CPUPPCState *env) | |
3fc6c082 | 1284 | { |
76a66253 JM |
1285 | /* Memory base address */ |
1286 | /* MBAR */ | |
578bb252 | 1287 | /* XXX : not implemented */ |
76a66253 JM |
1288 | spr_register(env, SPR_MBAR, "MBAR", |
1289 | SPR_NOACCESS, SPR_NOACCESS, | |
1290 | &spr_read_generic, &spr_write_generic, | |
1291 | 0x00000000); | |
76a66253 | 1292 | /* Exception processing */ |
363be49c | 1293 | spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
76a66253 JM |
1294 | SPR_NOACCESS, SPR_NOACCESS, |
1295 | &spr_read_generic, &spr_write_generic, | |
1296 | 0x00000000); | |
363be49c | 1297 | spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
76a66253 JM |
1298 | SPR_NOACCESS, SPR_NOACCESS, |
1299 | &spr_read_generic, &spr_write_generic, | |
1300 | 0x00000000); | |
1301 | /* Breakpoints */ | |
1302 | /* XXX : not implemented */ | |
1303 | spr_register(env, SPR_DABR, "DABR", | |
1304 | SPR_NOACCESS, SPR_NOACCESS, | |
1305 | &spr_read_generic, &spr_write_generic, | |
1306 | 0x00000000); | |
1307 | /* XXX : not implemented */ | |
1308 | spr_register(env, SPR_DABR2, "DABR2", | |
1309 | SPR_NOACCESS, SPR_NOACCESS, | |
1310 | &spr_read_generic, &spr_write_generic, | |
1311 | 0x00000000); | |
1312 | /* XXX : not implemented */ | |
1313 | spr_register(env, SPR_IABR, "IABR", | |
1314 | SPR_NOACCESS, SPR_NOACCESS, | |
1315 | &spr_read_generic, &spr_write_generic, | |
1316 | 0x00000000); | |
1317 | /* XXX : not implemented */ | |
1318 | spr_register(env, SPR_IABR2, "IABR2", | |
1319 | SPR_NOACCESS, SPR_NOACCESS, | |
1320 | &spr_read_generic, &spr_write_generic, | |
1321 | 0x00000000); | |
1322 | /* XXX : not implemented */ | |
1323 | spr_register(env, SPR_IBCR, "IBCR", | |
1324 | SPR_NOACCESS, SPR_NOACCESS, | |
1325 | &spr_read_generic, &spr_write_generic, | |
1326 | 0x00000000); | |
1327 | /* XXX : not implemented */ | |
1328 | spr_register(env, SPR_DBCR, "DBCR", | |
1329 | SPR_NOACCESS, SPR_NOACCESS, | |
1330 | &spr_read_generic, &spr_write_generic, | |
1331 | 0x00000000); | |
1332 | } | |
1333 | ||
1334 | /* SPR specific to PowerPC 602 implementation */ | |
1335 | static void gen_spr_602 (CPUPPCState *env) | |
1336 | { | |
1337 | /* ESA registers */ | |
1338 | /* XXX : not implemented */ | |
1339 | spr_register(env, SPR_SER, "SER", | |
1340 | SPR_NOACCESS, SPR_NOACCESS, | |
1341 | &spr_read_generic, &spr_write_generic, | |
1342 | 0x00000000); | |
1343 | /* XXX : not implemented */ | |
1344 | spr_register(env, SPR_SEBR, "SEBR", | |
1345 | SPR_NOACCESS, SPR_NOACCESS, | |
1346 | &spr_read_generic, &spr_write_generic, | |
1347 | 0x00000000); | |
1348 | /* XXX : not implemented */ | |
a750fc0b | 1349 | spr_register(env, SPR_ESASRR, "ESASRR", |
76a66253 JM |
1350 | SPR_NOACCESS, SPR_NOACCESS, |
1351 | &spr_read_generic, &spr_write_generic, | |
1352 | 0x00000000); | |
1353 | /* Floating point status */ | |
1354 | /* XXX : not implemented */ | |
1355 | spr_register(env, SPR_SP, "SP", | |
1356 | SPR_NOACCESS, SPR_NOACCESS, | |
1357 | &spr_read_generic, &spr_write_generic, | |
1358 | 0x00000000); | |
1359 | /* XXX : not implemented */ | |
1360 | spr_register(env, SPR_LT, "LT", | |
1361 | SPR_NOACCESS, SPR_NOACCESS, | |
1362 | &spr_read_generic, &spr_write_generic, | |
1363 | 0x00000000); | |
1364 | /* Watchdog timer */ | |
1365 | /* XXX : not implemented */ | |
1366 | spr_register(env, SPR_TCR, "TCR", | |
1367 | SPR_NOACCESS, SPR_NOACCESS, | |
1368 | &spr_read_generic, &spr_write_generic, | |
1369 | 0x00000000); | |
1370 | /* Interrupt base */ | |
1371 | spr_register(env, SPR_IBR, "IBR", | |
1372 | SPR_NOACCESS, SPR_NOACCESS, | |
1373 | &spr_read_generic, &spr_write_generic, | |
1374 | 0x00000000); | |
a750fc0b JM |
1375 | /* XXX : not implemented */ |
1376 | spr_register(env, SPR_IABR, "IABR", | |
1377 | SPR_NOACCESS, SPR_NOACCESS, | |
1378 | &spr_read_generic, &spr_write_generic, | |
1379 | 0x00000000); | |
76a66253 JM |
1380 | } |
1381 | ||
1382 | /* SPR specific to PowerPC 601 implementation */ | |
1383 | static void gen_spr_601 (CPUPPCState *env) | |
1384 | { | |
1385 | /* Multiplication/division register */ | |
1386 | /* MQ */ | |
1387 | spr_register(env, SPR_MQ, "MQ", | |
1388 | &spr_read_generic, &spr_write_generic, | |
1389 | &spr_read_generic, &spr_write_generic, | |
1390 | 0x00000000); | |
1391 | /* RTC registers */ | |
1392 | spr_register(env, SPR_601_RTCU, "RTCU", | |
1393 | SPR_NOACCESS, SPR_NOACCESS, | |
1394 | SPR_NOACCESS, &spr_write_601_rtcu, | |
1395 | 0x00000000); | |
1396 | spr_register(env, SPR_601_VRTCU, "RTCU", | |
1397 | &spr_read_601_rtcu, SPR_NOACCESS, | |
1398 | &spr_read_601_rtcu, SPR_NOACCESS, | |
1399 | 0x00000000); | |
1400 | spr_register(env, SPR_601_RTCL, "RTCL", | |
1401 | SPR_NOACCESS, SPR_NOACCESS, | |
1402 | SPR_NOACCESS, &spr_write_601_rtcl, | |
1403 | 0x00000000); | |
1404 | spr_register(env, SPR_601_VRTCL, "RTCL", | |
1405 | &spr_read_601_rtcl, SPR_NOACCESS, | |
1406 | &spr_read_601_rtcl, SPR_NOACCESS, | |
1407 | 0x00000000); | |
1408 | /* Timer */ | |
1409 | #if 0 /* ? */ | |
1410 | spr_register(env, SPR_601_UDECR, "UDECR", | |
1411 | &spr_read_decr, SPR_NOACCESS, | |
1412 | &spr_read_decr, SPR_NOACCESS, | |
1413 | 0x00000000); | |
1414 | #endif | |
1415 | /* External access control */ | |
1416 | /* XXX : not implemented */ | |
1417 | spr_register(env, SPR_EAR, "EAR", | |
1418 | SPR_NOACCESS, SPR_NOACCESS, | |
1419 | &spr_read_generic, &spr_write_generic, | |
1420 | 0x00000000); | |
1421 | /* Memory management */ | |
f2e63a42 | 1422 | #if !defined(CONFIG_USER_ONLY) |
76a66253 JM |
1423 | spr_register(env, SPR_IBAT0U, "IBAT0U", |
1424 | SPR_NOACCESS, SPR_NOACCESS, | |
1425 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1426 | 0x00000000); | |
1427 | spr_register(env, SPR_IBAT0L, "IBAT0L", | |
1428 | SPR_NOACCESS, SPR_NOACCESS, | |
1429 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1430 | 0x00000000); | |
1431 | spr_register(env, SPR_IBAT1U, "IBAT1U", | |
1432 | SPR_NOACCESS, SPR_NOACCESS, | |
1433 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1434 | 0x00000000); | |
1435 | spr_register(env, SPR_IBAT1L, "IBAT1L", | |
1436 | SPR_NOACCESS, SPR_NOACCESS, | |
1437 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1438 | 0x00000000); | |
1439 | spr_register(env, SPR_IBAT2U, "IBAT2U", | |
1440 | SPR_NOACCESS, SPR_NOACCESS, | |
1441 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1442 | 0x00000000); | |
1443 | spr_register(env, SPR_IBAT2L, "IBAT2L", | |
1444 | SPR_NOACCESS, SPR_NOACCESS, | |
1445 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1446 | 0x00000000); | |
1447 | spr_register(env, SPR_IBAT3U, "IBAT3U", | |
1448 | SPR_NOACCESS, SPR_NOACCESS, | |
1449 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1450 | 0x00000000); | |
1451 | spr_register(env, SPR_IBAT3L, "IBAT3L", | |
1452 | SPR_NOACCESS, SPR_NOACCESS, | |
1453 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1454 | 0x00000000); | |
a750fc0b | 1455 | env->nb_BATs = 4; |
f2e63a42 | 1456 | #endif |
a750fc0b JM |
1457 | } |
1458 | ||
1459 | static void gen_spr_74xx (CPUPPCState *env) | |
1460 | { | |
1461 | /* Processor identification */ | |
1462 | spr_register(env, SPR_PIR, "PIR", | |
1463 | SPR_NOACCESS, SPR_NOACCESS, | |
1464 | &spr_read_generic, &spr_write_pir, | |
1465 | 0x00000000); | |
1466 | /* XXX : not implemented */ | |
cb8b8bf8 | 1467 | spr_register(env, SPR_74XX_MMCR2, "MMCR2", |
a750fc0b JM |
1468 | SPR_NOACCESS, SPR_NOACCESS, |
1469 | &spr_read_generic, &spr_write_generic, | |
1470 | 0x00000000); | |
578bb252 | 1471 | /* XXX : not implemented */ |
cb8b8bf8 | 1472 | spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", |
a750fc0b JM |
1473 | &spr_read_ureg, SPR_NOACCESS, |
1474 | &spr_read_ureg, SPR_NOACCESS, | |
1475 | 0x00000000); | |
1476 | /* XXX: not implemented */ | |
1477 | spr_register(env, SPR_BAMR, "BAMR", | |
1478 | SPR_NOACCESS, SPR_NOACCESS, | |
1479 | &spr_read_generic, &spr_write_generic, | |
1480 | 0x00000000); | |
578bb252 | 1481 | /* XXX : not implemented */ |
a750fc0b JM |
1482 | spr_register(env, SPR_MSSCR0, "MSSCR0", |
1483 | SPR_NOACCESS, SPR_NOACCESS, | |
1484 | &spr_read_generic, &spr_write_generic, | |
1485 | 0x00000000); | |
1486 | /* Hardware implementation registers */ | |
1487 | /* XXX : not implemented */ | |
1488 | spr_register(env, SPR_HID0, "HID0", | |
1489 | SPR_NOACCESS, SPR_NOACCESS, | |
1490 | &spr_read_generic, &spr_write_generic, | |
1491 | 0x00000000); | |
1492 | /* XXX : not implemented */ | |
1493 | spr_register(env, SPR_HID1, "HID1", | |
1494 | SPR_NOACCESS, SPR_NOACCESS, | |
1495 | &spr_read_generic, &spr_write_generic, | |
1496 | 0x00000000); | |
1497 | /* Altivec */ | |
1498 | spr_register(env, SPR_VRSAVE, "VRSAVE", | |
1499 | &spr_read_generic, &spr_write_generic, | |
1500 | &spr_read_generic, &spr_write_generic, | |
1501 | 0x00000000); | |
bd928eba JM |
1502 | /* XXX : not implemented */ |
1503 | spr_register(env, SPR_L2CR, "L2CR", | |
1504 | SPR_NOACCESS, SPR_NOACCESS, | |
9633fcc6 | 1505 | &spr_read_generic, spr_access_nop, |
bd928eba | 1506 | 0x00000000); |
cf8358c8 AJ |
1507 | /* Not strictly an SPR */ |
1508 | vscr_init(env, 0x00010000); | |
a750fc0b JM |
1509 | } |
1510 | ||
a750fc0b JM |
1511 | static void gen_l3_ctrl (CPUPPCState *env) |
1512 | { | |
1513 | /* L3CR */ | |
1514 | /* XXX : not implemented */ | |
1515 | spr_register(env, SPR_L3CR, "L3CR", | |
1516 | SPR_NOACCESS, SPR_NOACCESS, | |
1517 | &spr_read_generic, &spr_write_generic, | |
1518 | 0x00000000); | |
1519 | /* L3ITCR0 */ | |
578bb252 | 1520 | /* XXX : not implemented */ |
a750fc0b JM |
1521 | spr_register(env, SPR_L3ITCR0, "L3ITCR0", |
1522 | SPR_NOACCESS, SPR_NOACCESS, | |
1523 | &spr_read_generic, &spr_write_generic, | |
1524 | 0x00000000); | |
a750fc0b | 1525 | /* L3PM */ |
578bb252 | 1526 | /* XXX : not implemented */ |
a750fc0b JM |
1527 | spr_register(env, SPR_L3PM, "L3PM", |
1528 | SPR_NOACCESS, SPR_NOACCESS, | |
1529 | &spr_read_generic, &spr_write_generic, | |
1530 | 0x00000000); | |
1531 | } | |
a750fc0b | 1532 | |
578bb252 | 1533 | static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
a750fc0b | 1534 | { |
f2e63a42 | 1535 | #if !defined(CONFIG_USER_ONLY) |
578bb252 JM |
1536 | env->nb_tlb = nb_tlbs; |
1537 | env->nb_ways = nb_ways; | |
1538 | env->id_tlbs = 1; | |
1c53accc | 1539 | env->tlb_type = TLB_6XX; |
578bb252 | 1540 | /* XXX : not implemented */ |
a750fc0b JM |
1541 | spr_register(env, SPR_PTEHI, "PTEHI", |
1542 | SPR_NOACCESS, SPR_NOACCESS, | |
1543 | &spr_read_generic, &spr_write_generic, | |
1544 | 0x00000000); | |
578bb252 | 1545 | /* XXX : not implemented */ |
a750fc0b JM |
1546 | spr_register(env, SPR_PTELO, "PTELO", |
1547 | SPR_NOACCESS, SPR_NOACCESS, | |
1548 | &spr_read_generic, &spr_write_generic, | |
1549 | 0x00000000); | |
578bb252 | 1550 | /* XXX : not implemented */ |
a750fc0b JM |
1551 | spr_register(env, SPR_TLBMISS, "TLBMISS", |
1552 | SPR_NOACCESS, SPR_NOACCESS, | |
1553 | &spr_read_generic, &spr_write_generic, | |
1554 | 0x00000000); | |
f2e63a42 | 1555 | #endif |
76a66253 JM |
1556 | } |
1557 | ||
01662f3e | 1558 | #if !defined(CONFIG_USER_ONLY) |
69b058c8 | 1559 | static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn) |
01662f3e AG |
1560 | { |
1561 | TCGv t0 = tcg_temp_new(); | |
1562 | ||
ea71258d AG |
1563 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); |
1564 | gen_store_spr(sprn, t0); | |
1565 | tcg_temp_free(t0); | |
1566 | } | |
1567 | ||
69b058c8 | 1568 | static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) |
ea71258d AG |
1569 | { |
1570 | TCGv t0 = tcg_temp_new(); | |
1571 | ||
1572 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); | |
01662f3e AG |
1573 | gen_store_spr(sprn, t0); |
1574 | tcg_temp_free(t0); | |
1575 | } | |
1576 | ||
69b058c8 | 1577 | static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn) |
01662f3e | 1578 | { |
a721d390 | 1579 | gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); |
01662f3e AG |
1580 | } |
1581 | ||
69b058c8 | 1582 | static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn) |
01662f3e | 1583 | { |
1ff7854e | 1584 | TCGv_i32 t0 = tcg_const_i32(sprn); |
c6c7cf05 | 1585 | gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); |
1ff7854e | 1586 | tcg_temp_free_i32(t0); |
01662f3e AG |
1587 | } |
1588 | #endif | |
1589 | ||
80d11f44 | 1590 | static void gen_spr_usprgh (CPUPPCState *env) |
76a66253 | 1591 | { |
80d11f44 JM |
1592 | spr_register(env, SPR_USPRG4, "USPRG4", |
1593 | &spr_read_ureg, SPR_NOACCESS, | |
1594 | &spr_read_ureg, SPR_NOACCESS, | |
1595 | 0x00000000); | |
1596 | spr_register(env, SPR_USPRG5, "USPRG5", | |
1597 | &spr_read_ureg, SPR_NOACCESS, | |
1598 | &spr_read_ureg, SPR_NOACCESS, | |
1599 | 0x00000000); | |
1600 | spr_register(env, SPR_USPRG6, "USPRG6", | |
1601 | &spr_read_ureg, SPR_NOACCESS, | |
1602 | &spr_read_ureg, SPR_NOACCESS, | |
1603 | 0x00000000); | |
1604 | spr_register(env, SPR_USPRG7, "USPRG7", | |
1605 | &spr_read_ureg, SPR_NOACCESS, | |
1606 | &spr_read_ureg, SPR_NOACCESS, | |
76a66253 | 1607 | 0x00000000); |
80d11f44 JM |
1608 | } |
1609 | ||
1610 | /* PowerPC BookE SPR */ | |
1611 | static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) | |
1612 | { | |
b55266b5 | 1613 | const char *ivor_names[64] = { |
80d11f44 JM |
1614 | "IVOR0", "IVOR1", "IVOR2", "IVOR3", |
1615 | "IVOR4", "IVOR5", "IVOR6", "IVOR7", | |
1616 | "IVOR8", "IVOR9", "IVOR10", "IVOR11", | |
1617 | "IVOR12", "IVOR13", "IVOR14", "IVOR15", | |
1618 | "IVOR16", "IVOR17", "IVOR18", "IVOR19", | |
1619 | "IVOR20", "IVOR21", "IVOR22", "IVOR23", | |
1620 | "IVOR24", "IVOR25", "IVOR26", "IVOR27", | |
1621 | "IVOR28", "IVOR29", "IVOR30", "IVOR31", | |
1622 | "IVOR32", "IVOR33", "IVOR34", "IVOR35", | |
1623 | "IVOR36", "IVOR37", "IVOR38", "IVOR39", | |
1624 | "IVOR40", "IVOR41", "IVOR42", "IVOR43", | |
1625 | "IVOR44", "IVOR45", "IVOR46", "IVOR47", | |
1626 | "IVOR48", "IVOR49", "IVOR50", "IVOR51", | |
1627 | "IVOR52", "IVOR53", "IVOR54", "IVOR55", | |
1628 | "IVOR56", "IVOR57", "IVOR58", "IVOR59", | |
1629 | "IVOR60", "IVOR61", "IVOR62", "IVOR63", | |
1630 | }; | |
1631 | #define SPR_BOOKE_IVORxx (-1) | |
1632 | int ivor_sprn[64] = { | |
1633 | SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, | |
1634 | SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, | |
1635 | SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, | |
1636 | SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, | |
1637 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1638 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1639 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1640 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1641 | SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, | |
e9205258 AG |
1642 | SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, |
1643 | SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, | |
80d11f44 JM |
1644 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1645 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1646 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1647 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1648 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1649 | }; | |
1650 | int i; | |
1651 | ||
76a66253 | 1652 | /* Interrupt processing */ |
363be49c | 1653 | spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
76a66253 JM |
1654 | SPR_NOACCESS, SPR_NOACCESS, |
1655 | &spr_read_generic, &spr_write_generic, | |
1656 | 0x00000000); | |
363be49c JM |
1657 | spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
1658 | SPR_NOACCESS, SPR_NOACCESS, | |
1659 | &spr_read_generic, &spr_write_generic, | |
1660 | 0x00000000); | |
76a66253 JM |
1661 | /* Debug */ |
1662 | /* XXX : not implemented */ | |
1663 | spr_register(env, SPR_BOOKE_IAC1, "IAC1", | |
1664 | SPR_NOACCESS, SPR_NOACCESS, | |
1665 | &spr_read_generic, &spr_write_generic, | |
1666 | 0x00000000); | |
1667 | /* XXX : not implemented */ | |
1668 | spr_register(env, SPR_BOOKE_IAC2, "IAC2", | |
1669 | SPR_NOACCESS, SPR_NOACCESS, | |
1670 | &spr_read_generic, &spr_write_generic, | |
1671 | 0x00000000); | |
1672 | /* XXX : not implemented */ | |
76a66253 JM |
1673 | spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
1674 | SPR_NOACCESS, SPR_NOACCESS, | |
1675 | &spr_read_generic, &spr_write_generic, | |
1676 | 0x00000000); | |
1677 | /* XXX : not implemented */ | |
1678 | spr_register(env, SPR_BOOKE_DAC2, "DAC2", | |
1679 | SPR_NOACCESS, SPR_NOACCESS, | |
1680 | &spr_read_generic, &spr_write_generic, | |
1681 | 0x00000000); | |
1682 | /* XXX : not implemented */ | |
76a66253 JM |
1683 | spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
1684 | SPR_NOACCESS, SPR_NOACCESS, | |
e598a9c5 | 1685 | &spr_read_generic, &spr_write_40x_dbcr0, |
76a66253 JM |
1686 | 0x00000000); |
1687 | /* XXX : not implemented */ | |
1688 | spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", | |
1689 | SPR_NOACCESS, SPR_NOACCESS, | |
1690 | &spr_read_generic, &spr_write_generic, | |
1691 | 0x00000000); | |
1692 | /* XXX : not implemented */ | |
1693 | spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", | |
1694 | SPR_NOACCESS, SPR_NOACCESS, | |
1695 | &spr_read_generic, &spr_write_generic, | |
1696 | 0x00000000); | |
1697 | /* XXX : not implemented */ | |
1698 | spr_register(env, SPR_BOOKE_DBSR, "DBSR", | |
1699 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 | 1700 | &spr_read_generic, &spr_write_clear, |
76a66253 JM |
1701 | 0x00000000); |
1702 | spr_register(env, SPR_BOOKE_DEAR, "DEAR", | |
1703 | SPR_NOACCESS, SPR_NOACCESS, | |
1704 | &spr_read_generic, &spr_write_generic, | |
1705 | 0x00000000); | |
1706 | spr_register(env, SPR_BOOKE_ESR, "ESR", | |
1707 | SPR_NOACCESS, SPR_NOACCESS, | |
1708 | &spr_read_generic, &spr_write_generic, | |
1709 | 0x00000000); | |
363be49c JM |
1710 | spr_register(env, SPR_BOOKE_IVPR, "IVPR", |
1711 | SPR_NOACCESS, SPR_NOACCESS, | |
6f5d427d | 1712 | &spr_read_generic, &spr_write_excp_prefix, |
363be49c JM |
1713 | 0x00000000); |
1714 | /* Exception vectors */ | |
80d11f44 JM |
1715 | for (i = 0; i < 64; i++) { |
1716 | if (ivor_mask & (1ULL << i)) { | |
1717 | if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { | |
1718 | fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); | |
1719 | exit(1); | |
1720 | } | |
1721 | spr_register(env, ivor_sprn[i], ivor_names[i], | |
1722 | SPR_NOACCESS, SPR_NOACCESS, | |
1723 | &spr_read_generic, &spr_write_excp_vector, | |
1724 | 0x00000000); | |
1725 | } | |
1726 | } | |
76a66253 JM |
1727 | spr_register(env, SPR_BOOKE_PID, "PID", |
1728 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 1729 | &spr_read_generic, &spr_write_booke_pid, |
76a66253 JM |
1730 | 0x00000000); |
1731 | spr_register(env, SPR_BOOKE_TCR, "TCR", | |
1732 | SPR_NOACCESS, SPR_NOACCESS, | |
1733 | &spr_read_generic, &spr_write_booke_tcr, | |
1734 | 0x00000000); | |
1735 | spr_register(env, SPR_BOOKE_TSR, "TSR", | |
1736 | SPR_NOACCESS, SPR_NOACCESS, | |
1737 | &spr_read_generic, &spr_write_booke_tsr, | |
1738 | 0x00000000); | |
1739 | /* Timer */ | |
1740 | spr_register(env, SPR_DECR, "DECR", | |
1741 | SPR_NOACCESS, SPR_NOACCESS, | |
1742 | &spr_read_decr, &spr_write_decr, | |
1743 | 0x00000000); | |
1744 | spr_register(env, SPR_BOOKE_DECAR, "DECAR", | |
1745 | SPR_NOACCESS, SPR_NOACCESS, | |
1746 | SPR_NOACCESS, &spr_write_generic, | |
1747 | 0x00000000); | |
1748 | /* SPRGs */ | |
1749 | spr_register(env, SPR_USPRG0, "USPRG0", | |
1750 | &spr_read_generic, &spr_write_generic, | |
1751 | &spr_read_generic, &spr_write_generic, | |
1752 | 0x00000000); | |
1753 | spr_register(env, SPR_SPRG4, "SPRG4", | |
1754 | SPR_NOACCESS, SPR_NOACCESS, | |
1755 | &spr_read_generic, &spr_write_generic, | |
1756 | 0x00000000); | |
76a66253 JM |
1757 | spr_register(env, SPR_SPRG5, "SPRG5", |
1758 | SPR_NOACCESS, SPR_NOACCESS, | |
1759 | &spr_read_generic, &spr_write_generic, | |
1760 | 0x00000000); | |
76a66253 JM |
1761 | spr_register(env, SPR_SPRG6, "SPRG6", |
1762 | SPR_NOACCESS, SPR_NOACCESS, | |
1763 | &spr_read_generic, &spr_write_generic, | |
1764 | 0x00000000); | |
76a66253 JM |
1765 | spr_register(env, SPR_SPRG7, "SPRG7", |
1766 | SPR_NOACCESS, SPR_NOACCESS, | |
1767 | &spr_read_generic, &spr_write_generic, | |
1768 | 0x00000000); | |
76a66253 JM |
1769 | } |
1770 | ||
01662f3e AG |
1771 | static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, |
1772 | uint32_t maxsize, uint32_t flags, | |
1773 | uint32_t nentries) | |
1774 | { | |
1775 | return (assoc << TLBnCFG_ASSOC_SHIFT) | | |
1776 | (minsize << TLBnCFG_MINSIZE_SHIFT) | | |
1777 | (maxsize << TLBnCFG_MAXSIZE_SHIFT) | | |
1778 | flags | nentries; | |
1779 | } | |
1780 | ||
1781 | /* BookE 2.06 storage control registers */ | |
1782 | static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, | |
1783 | uint32_t *tlbncfg) | |
363be49c | 1784 | { |
f2e63a42 | 1785 | #if !defined(CONFIG_USER_ONLY) |
b55266b5 | 1786 | const char *mas_names[8] = { |
80d11f44 JM |
1787 | "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
1788 | }; | |
1789 | int mas_sprn[8] = { | |
1790 | SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, | |
1791 | SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, | |
1792 | }; | |
1793 | int i; | |
1794 | ||
363be49c | 1795 | /* TLB assist registers */ |
578bb252 | 1796 | /* XXX : not implemented */ |
80d11f44 | 1797 | for (i = 0; i < 8; i++) { |
69b058c8 | 1798 | void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32; |
ba38ab8d AG |
1799 | if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { |
1800 | uea_write = &spr_write_generic; | |
1801 | } | |
80d11f44 JM |
1802 | if (mas_mask & (1 << i)) { |
1803 | spr_register(env, mas_sprn[i], mas_names[i], | |
1804 | SPR_NOACCESS, SPR_NOACCESS, | |
ba38ab8d | 1805 | &spr_read_generic, uea_write, |
80d11f44 JM |
1806 | 0x00000000); |
1807 | } | |
1808 | } | |
363be49c | 1809 | if (env->nb_pids > 1) { |
578bb252 | 1810 | /* XXX : not implemented */ |
363be49c JM |
1811 | spr_register(env, SPR_BOOKE_PID1, "PID1", |
1812 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 1813 | &spr_read_generic, &spr_write_booke_pid, |
363be49c JM |
1814 | 0x00000000); |
1815 | } | |
1816 | if (env->nb_pids > 2) { | |
578bb252 | 1817 | /* XXX : not implemented */ |
363be49c JM |
1818 | spr_register(env, SPR_BOOKE_PID2, "PID2", |
1819 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 1820 | &spr_read_generic, &spr_write_booke_pid, |
363be49c JM |
1821 | 0x00000000); |
1822 | } | |
578bb252 | 1823 | /* XXX : not implemented */ |
65f9ee8d | 1824 | spr_register(env, SPR_MMUCFG, "MMUCFG", |
363be49c JM |
1825 | SPR_NOACCESS, SPR_NOACCESS, |
1826 | &spr_read_generic, SPR_NOACCESS, | |
1827 | 0x00000000); /* TOFIX */ | |
363be49c JM |
1828 | switch (env->nb_ways) { |
1829 | case 4: | |
1830 | spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", | |
1831 | SPR_NOACCESS, SPR_NOACCESS, | |
1832 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1833 | tlbncfg[3]); |
363be49c JM |
1834 | /* Fallthru */ |
1835 | case 3: | |
1836 | spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", | |
1837 | SPR_NOACCESS, SPR_NOACCESS, | |
1838 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1839 | tlbncfg[2]); |
363be49c JM |
1840 | /* Fallthru */ |
1841 | case 2: | |
1842 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", | |
1843 | SPR_NOACCESS, SPR_NOACCESS, | |
1844 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1845 | tlbncfg[1]); |
363be49c JM |
1846 | /* Fallthru */ |
1847 | case 1: | |
1848 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", | |
1849 | SPR_NOACCESS, SPR_NOACCESS, | |
1850 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1851 | tlbncfg[0]); |
363be49c JM |
1852 | /* Fallthru */ |
1853 | case 0: | |
1854 | default: | |
1855 | break; | |
1856 | } | |
f2e63a42 | 1857 | #endif |
01662f3e AG |
1858 | |
1859 | gen_spr_usprgh(env); | |
363be49c JM |
1860 | } |
1861 | ||
76a66253 JM |
1862 | /* SPR specific to PowerPC 440 implementation */ |
1863 | static void gen_spr_440 (CPUPPCState *env) | |
1864 | { | |
1865 | /* Cache control */ | |
1866 | /* XXX : not implemented */ | |
1867 | spr_register(env, SPR_440_DNV0, "DNV0", | |
1868 | SPR_NOACCESS, SPR_NOACCESS, | |
1869 | &spr_read_generic, &spr_write_generic, | |
1870 | 0x00000000); | |
1871 | /* XXX : not implemented */ | |
1872 | spr_register(env, SPR_440_DNV1, "DNV1", | |
1873 | SPR_NOACCESS, SPR_NOACCESS, | |
1874 | &spr_read_generic, &spr_write_generic, | |
1875 | 0x00000000); | |
1876 | /* XXX : not implemented */ | |
1877 | spr_register(env, SPR_440_DNV2, "DNV2", | |
1878 | SPR_NOACCESS, SPR_NOACCESS, | |
1879 | &spr_read_generic, &spr_write_generic, | |
1880 | 0x00000000); | |
1881 | /* XXX : not implemented */ | |
1882 | spr_register(env, SPR_440_DNV3, "DNV3", | |
1883 | SPR_NOACCESS, SPR_NOACCESS, | |
1884 | &spr_read_generic, &spr_write_generic, | |
1885 | 0x00000000); | |
1886 | /* XXX : not implemented */ | |
2662a059 | 1887 | spr_register(env, SPR_440_DTV0, "DTV0", |
76a66253 JM |
1888 | SPR_NOACCESS, SPR_NOACCESS, |
1889 | &spr_read_generic, &spr_write_generic, | |
1890 | 0x00000000); | |
1891 | /* XXX : not implemented */ | |
2662a059 | 1892 | spr_register(env, SPR_440_DTV1, "DTV1", |
76a66253 JM |
1893 | SPR_NOACCESS, SPR_NOACCESS, |
1894 | &spr_read_generic, &spr_write_generic, | |
1895 | 0x00000000); | |
1896 | /* XXX : not implemented */ | |
2662a059 | 1897 | spr_register(env, SPR_440_DTV2, "DTV2", |
76a66253 JM |
1898 | SPR_NOACCESS, SPR_NOACCESS, |
1899 | &spr_read_generic, &spr_write_generic, | |
1900 | 0x00000000); | |
1901 | /* XXX : not implemented */ | |
2662a059 | 1902 | spr_register(env, SPR_440_DTV3, "DTV3", |
76a66253 JM |
1903 | SPR_NOACCESS, SPR_NOACCESS, |
1904 | &spr_read_generic, &spr_write_generic, | |
1905 | 0x00000000); | |
1906 | /* XXX : not implemented */ | |
1907 | spr_register(env, SPR_440_DVLIM, "DVLIM", | |
1908 | SPR_NOACCESS, SPR_NOACCESS, | |
1909 | &spr_read_generic, &spr_write_generic, | |
1910 | 0x00000000); | |
1911 | /* XXX : not implemented */ | |
1912 | spr_register(env, SPR_440_INV0, "INV0", | |
1913 | SPR_NOACCESS, SPR_NOACCESS, | |
1914 | &spr_read_generic, &spr_write_generic, | |
1915 | 0x00000000); | |
1916 | /* XXX : not implemented */ | |
1917 | spr_register(env, SPR_440_INV1, "INV1", | |
1918 | SPR_NOACCESS, SPR_NOACCESS, | |
1919 | &spr_read_generic, &spr_write_generic, | |
1920 | 0x00000000); | |
1921 | /* XXX : not implemented */ | |
1922 | spr_register(env, SPR_440_INV2, "INV2", | |
1923 | SPR_NOACCESS, SPR_NOACCESS, | |
1924 | &spr_read_generic, &spr_write_generic, | |
1925 | 0x00000000); | |
1926 | /* XXX : not implemented */ | |
1927 | spr_register(env, SPR_440_INV3, "INV3", | |
1928 | SPR_NOACCESS, SPR_NOACCESS, | |
1929 | &spr_read_generic, &spr_write_generic, | |
1930 | 0x00000000); | |
1931 | /* XXX : not implemented */ | |
2662a059 | 1932 | spr_register(env, SPR_440_ITV0, "ITV0", |
76a66253 JM |
1933 | SPR_NOACCESS, SPR_NOACCESS, |
1934 | &spr_read_generic, &spr_write_generic, | |
1935 | 0x00000000); | |
1936 | /* XXX : not implemented */ | |
2662a059 | 1937 | spr_register(env, SPR_440_ITV1, "ITV1", |
76a66253 JM |
1938 | SPR_NOACCESS, SPR_NOACCESS, |
1939 | &spr_read_generic, &spr_write_generic, | |
1940 | 0x00000000); | |
1941 | /* XXX : not implemented */ | |
2662a059 | 1942 | spr_register(env, SPR_440_ITV2, "ITV2", |
76a66253 JM |
1943 | SPR_NOACCESS, SPR_NOACCESS, |
1944 | &spr_read_generic, &spr_write_generic, | |
1945 | 0x00000000); | |
1946 | /* XXX : not implemented */ | |
2662a059 | 1947 | spr_register(env, SPR_440_ITV3, "ITV3", |
76a66253 JM |
1948 | SPR_NOACCESS, SPR_NOACCESS, |
1949 | &spr_read_generic, &spr_write_generic, | |
1950 | 0x00000000); | |
1951 | /* XXX : not implemented */ | |
1952 | spr_register(env, SPR_440_IVLIM, "IVLIM", | |
1953 | SPR_NOACCESS, SPR_NOACCESS, | |
1954 | &spr_read_generic, &spr_write_generic, | |
1955 | 0x00000000); | |
1956 | /* Cache debug */ | |
1957 | /* XXX : not implemented */ | |
2662a059 | 1958 | spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", |
76a66253 JM |
1959 | SPR_NOACCESS, SPR_NOACCESS, |
1960 | &spr_read_generic, SPR_NOACCESS, | |
1961 | 0x00000000); | |
1962 | /* XXX : not implemented */ | |
2662a059 | 1963 | spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", |
76a66253 JM |
1964 | SPR_NOACCESS, SPR_NOACCESS, |
1965 | &spr_read_generic, SPR_NOACCESS, | |
1966 | 0x00000000); | |
1967 | /* XXX : not implemented */ | |
2662a059 | 1968 | spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
76a66253 JM |
1969 | SPR_NOACCESS, SPR_NOACCESS, |
1970 | &spr_read_generic, SPR_NOACCESS, | |
1971 | 0x00000000); | |
1972 | /* XXX : not implemented */ | |
2662a059 | 1973 | spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", |
76a66253 JM |
1974 | SPR_NOACCESS, SPR_NOACCESS, |
1975 | &spr_read_generic, SPR_NOACCESS, | |
1976 | 0x00000000); | |
1977 | /* XXX : not implemented */ | |
2662a059 | 1978 | spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", |
76a66253 JM |
1979 | SPR_NOACCESS, SPR_NOACCESS, |
1980 | &spr_read_generic, SPR_NOACCESS, | |
1981 | 0x00000000); | |
1982 | /* XXX : not implemented */ | |
1983 | spr_register(env, SPR_440_DBDR, "DBDR", | |
1984 | SPR_NOACCESS, SPR_NOACCESS, | |
1985 | &spr_read_generic, &spr_write_generic, | |
1986 | 0x00000000); | |
1987 | /* Processor control */ | |
1988 | spr_register(env, SPR_4xx_CCR0, "CCR0", | |
1989 | SPR_NOACCESS, SPR_NOACCESS, | |
1990 | &spr_read_generic, &spr_write_generic, | |
1991 | 0x00000000); | |
1992 | spr_register(env, SPR_440_RSTCFG, "RSTCFG", | |
1993 | SPR_NOACCESS, SPR_NOACCESS, | |
1994 | &spr_read_generic, SPR_NOACCESS, | |
1995 | 0x00000000); | |
1996 | /* Storage control */ | |
1997 | spr_register(env, SPR_440_MMUCR, "MMUCR", | |
1998 | SPR_NOACCESS, SPR_NOACCESS, | |
1999 | &spr_read_generic, &spr_write_generic, | |
2000 | 0x00000000); | |
2001 | } | |
2002 | ||
2003 | /* SPR shared between PowerPC 40x implementations */ | |
2004 | static void gen_spr_40x (CPUPPCState *env) | |
2005 | { | |
2006 | /* Cache */ | |
5cbdb3a3 | 2007 | /* not emulated, as QEMU do not emulate caches */ |
76a66253 JM |
2008 | spr_register(env, SPR_40x_DCCR, "DCCR", |
2009 | SPR_NOACCESS, SPR_NOACCESS, | |
2010 | &spr_read_generic, &spr_write_generic, | |
2011 | 0x00000000); | |
5cbdb3a3 | 2012 | /* not emulated, as QEMU do not emulate caches */ |
76a66253 JM |
2013 | spr_register(env, SPR_40x_ICCR, "ICCR", |
2014 | SPR_NOACCESS, SPR_NOACCESS, | |
2015 | &spr_read_generic, &spr_write_generic, | |
2016 | 0x00000000); | |
5cbdb3a3 | 2017 | /* not emulated, as QEMU do not emulate caches */ |
2662a059 | 2018 | spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
76a66253 JM |
2019 | SPR_NOACCESS, SPR_NOACCESS, |
2020 | &spr_read_generic, SPR_NOACCESS, | |
2021 | 0x00000000); | |
76a66253 JM |
2022 | /* Exception */ |
2023 | spr_register(env, SPR_40x_DEAR, "DEAR", | |
2024 | SPR_NOACCESS, SPR_NOACCESS, | |
2025 | &spr_read_generic, &spr_write_generic, | |
2026 | 0x00000000); | |
2027 | spr_register(env, SPR_40x_ESR, "ESR", | |
2028 | SPR_NOACCESS, SPR_NOACCESS, | |
2029 | &spr_read_generic, &spr_write_generic, | |
2030 | 0x00000000); | |
2031 | spr_register(env, SPR_40x_EVPR, "EVPR", | |
2032 | SPR_NOACCESS, SPR_NOACCESS, | |
6f5d427d | 2033 | &spr_read_generic, &spr_write_excp_prefix, |
76a66253 JM |
2034 | 0x00000000); |
2035 | spr_register(env, SPR_40x_SRR2, "SRR2", | |
2036 | &spr_read_generic, &spr_write_generic, | |
2037 | &spr_read_generic, &spr_write_generic, | |
2038 | 0x00000000); | |
2039 | spr_register(env, SPR_40x_SRR3, "SRR3", | |
2040 | &spr_read_generic, &spr_write_generic, | |
2041 | &spr_read_generic, &spr_write_generic, | |
2042 | 0x00000000); | |
2043 | /* Timers */ | |
2044 | spr_register(env, SPR_40x_PIT, "PIT", | |
2045 | SPR_NOACCESS, SPR_NOACCESS, | |
2046 | &spr_read_40x_pit, &spr_write_40x_pit, | |
2047 | 0x00000000); | |
2048 | spr_register(env, SPR_40x_TCR, "TCR", | |
2049 | SPR_NOACCESS, SPR_NOACCESS, | |
2050 | &spr_read_generic, &spr_write_booke_tcr, | |
2051 | 0x00000000); | |
2052 | spr_register(env, SPR_40x_TSR, "TSR", | |
2053 | SPR_NOACCESS, SPR_NOACCESS, | |
2054 | &spr_read_generic, &spr_write_booke_tsr, | |
2055 | 0x00000000); | |
2662a059 JM |
2056 | } |
2057 | ||
2058 | /* SPR specific to PowerPC 405 implementation */ | |
2059 | static void gen_spr_405 (CPUPPCState *env) | |
2060 | { | |
2061 | /* MMU */ | |
2062 | spr_register(env, SPR_40x_PID, "PID", | |
76a66253 JM |
2063 | SPR_NOACCESS, SPR_NOACCESS, |
2064 | &spr_read_generic, &spr_write_generic, | |
2065 | 0x00000000); | |
2662a059 | 2066 | spr_register(env, SPR_4xx_CCR0, "CCR0", |
76a66253 JM |
2067 | SPR_NOACCESS, SPR_NOACCESS, |
2068 | &spr_read_generic, &spr_write_generic, | |
2662a059 JM |
2069 | 0x00700000); |
2070 | /* Debug interface */ | |
76a66253 JM |
2071 | /* XXX : not implemented */ |
2072 | spr_register(env, SPR_40x_DBCR0, "DBCR0", | |
2073 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 | 2074 | &spr_read_generic, &spr_write_40x_dbcr0, |
76a66253 JM |
2075 | 0x00000000); |
2076 | /* XXX : not implemented */ | |
2662a059 JM |
2077 | spr_register(env, SPR_405_DBCR1, "DBCR1", |
2078 | SPR_NOACCESS, SPR_NOACCESS, | |
2079 | &spr_read_generic, &spr_write_generic, | |
2080 | 0x00000000); | |
2081 | /* XXX : not implemented */ | |
76a66253 JM |
2082 | spr_register(env, SPR_40x_DBSR, "DBSR", |
2083 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 JM |
2084 | &spr_read_generic, &spr_write_clear, |
2085 | /* Last reset was system reset */ | |
76a66253 JM |
2086 | 0x00000300); |
2087 | /* XXX : not implemented */ | |
2662a059 | 2088 | spr_register(env, SPR_40x_DAC1, "DAC1", |
76a66253 JM |
2089 | SPR_NOACCESS, SPR_NOACCESS, |
2090 | &spr_read_generic, &spr_write_generic, | |
2091 | 0x00000000); | |
2662a059 | 2092 | spr_register(env, SPR_40x_DAC2, "DAC2", |
76a66253 JM |
2093 | SPR_NOACCESS, SPR_NOACCESS, |
2094 | &spr_read_generic, &spr_write_generic, | |
2095 | 0x00000000); | |
2662a059 JM |
2096 | /* XXX : not implemented */ |
2097 | spr_register(env, SPR_405_DVC1, "DVC1", | |
76a66253 JM |
2098 | SPR_NOACCESS, SPR_NOACCESS, |
2099 | &spr_read_generic, &spr_write_generic, | |
2662a059 | 2100 | 0x00000000); |
76a66253 | 2101 | /* XXX : not implemented */ |
2662a059 | 2102 | spr_register(env, SPR_405_DVC2, "DVC2", |
76a66253 JM |
2103 | SPR_NOACCESS, SPR_NOACCESS, |
2104 | &spr_read_generic, &spr_write_generic, | |
2105 | 0x00000000); | |
2106 | /* XXX : not implemented */ | |
2662a059 | 2107 | spr_register(env, SPR_40x_IAC1, "IAC1", |
76a66253 JM |
2108 | SPR_NOACCESS, SPR_NOACCESS, |
2109 | &spr_read_generic, &spr_write_generic, | |
2110 | 0x00000000); | |
2662a059 | 2111 | spr_register(env, SPR_40x_IAC2, "IAC2", |
76a66253 JM |
2112 | SPR_NOACCESS, SPR_NOACCESS, |
2113 | &spr_read_generic, &spr_write_generic, | |
2114 | 0x00000000); | |
2115 | /* XXX : not implemented */ | |
2116 | spr_register(env, SPR_405_IAC3, "IAC3", | |
2117 | SPR_NOACCESS, SPR_NOACCESS, | |
2118 | &spr_read_generic, &spr_write_generic, | |
2119 | 0x00000000); | |
2120 | /* XXX : not implemented */ | |
2121 | spr_register(env, SPR_405_IAC4, "IAC4", | |
2122 | SPR_NOACCESS, SPR_NOACCESS, | |
2123 | &spr_read_generic, &spr_write_generic, | |
2124 | 0x00000000); | |
2125 | /* Storage control */ | |
035feb88 | 2126 | /* XXX: TODO: not implemented */ |
76a66253 JM |
2127 | spr_register(env, SPR_405_SLER, "SLER", |
2128 | SPR_NOACCESS, SPR_NOACCESS, | |
c294fc58 | 2129 | &spr_read_generic, &spr_write_40x_sler, |
76a66253 | 2130 | 0x00000000); |
2662a059 JM |
2131 | spr_register(env, SPR_40x_ZPR, "ZPR", |
2132 | SPR_NOACCESS, SPR_NOACCESS, | |
2133 | &spr_read_generic, &spr_write_generic, | |
2134 | 0x00000000); | |
76a66253 JM |
2135 | /* XXX : not implemented */ |
2136 | spr_register(env, SPR_405_SU0R, "SU0R", | |
2137 | SPR_NOACCESS, SPR_NOACCESS, | |
2138 | &spr_read_generic, &spr_write_generic, | |
2139 | 0x00000000); | |
2140 | /* SPRG */ | |
2141 | spr_register(env, SPR_USPRG0, "USPRG0", | |
2142 | &spr_read_ureg, SPR_NOACCESS, | |
2143 | &spr_read_ureg, SPR_NOACCESS, | |
2144 | 0x00000000); | |
2145 | spr_register(env, SPR_SPRG4, "SPRG4", | |
2146 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2147 | &spr_read_generic, &spr_write_generic, |
76a66253 | 2148 | 0x00000000); |
76a66253 JM |
2149 | spr_register(env, SPR_SPRG5, "SPRG5", |
2150 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2151 | spr_read_generic, &spr_write_generic, |
76a66253 | 2152 | 0x00000000); |
76a66253 JM |
2153 | spr_register(env, SPR_SPRG6, "SPRG6", |
2154 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2155 | spr_read_generic, &spr_write_generic, |
76a66253 | 2156 | 0x00000000); |
76a66253 JM |
2157 | spr_register(env, SPR_SPRG7, "SPRG7", |
2158 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2159 | spr_read_generic, &spr_write_generic, |
76a66253 | 2160 | 0x00000000); |
80d11f44 | 2161 | gen_spr_usprgh(env); |
76a66253 JM |
2162 | } |
2163 | ||
2164 | /* SPR shared between PowerPC 401 & 403 implementations */ | |
2165 | static void gen_spr_401_403 (CPUPPCState *env) | |
2166 | { | |
2167 | /* Time base */ | |
2168 | spr_register(env, SPR_403_VTBL, "TBL", | |
2169 | &spr_read_tbl, SPR_NOACCESS, | |
2170 | &spr_read_tbl, SPR_NOACCESS, | |
2171 | 0x00000000); | |
2172 | spr_register(env, SPR_403_TBL, "TBL", | |
2173 | SPR_NOACCESS, SPR_NOACCESS, | |
2174 | SPR_NOACCESS, &spr_write_tbl, | |
2175 | 0x00000000); | |
2176 | spr_register(env, SPR_403_VTBU, "TBU", | |
2177 | &spr_read_tbu, SPR_NOACCESS, | |
2178 | &spr_read_tbu, SPR_NOACCESS, | |
2179 | 0x00000000); | |
2180 | spr_register(env, SPR_403_TBU, "TBU", | |
2181 | SPR_NOACCESS, SPR_NOACCESS, | |
2182 | SPR_NOACCESS, &spr_write_tbu, | |
2183 | 0x00000000); | |
2184 | /* Debug */ | |
5cbdb3a3 | 2185 | /* not emulated, as QEMU do not emulate caches */ |
76a66253 JM |
2186 | spr_register(env, SPR_403_CDBCR, "CDBCR", |
2187 | SPR_NOACCESS, SPR_NOACCESS, | |
2188 | &spr_read_generic, &spr_write_generic, | |
2189 | 0x00000000); | |
2190 | } | |
2191 | ||
2662a059 JM |
2192 | /* SPR specific to PowerPC 401 implementation */ |
2193 | static void gen_spr_401 (CPUPPCState *env) | |
2194 | { | |
2195 | /* Debug interface */ | |
2196 | /* XXX : not implemented */ | |
2197 | spr_register(env, SPR_40x_DBCR0, "DBCR", | |
2198 | SPR_NOACCESS, SPR_NOACCESS, | |
2199 | &spr_read_generic, &spr_write_40x_dbcr0, | |
2200 | 0x00000000); | |
2201 | /* XXX : not implemented */ | |
2202 | spr_register(env, SPR_40x_DBSR, "DBSR", | |
2203 | SPR_NOACCESS, SPR_NOACCESS, | |
2204 | &spr_read_generic, &spr_write_clear, | |
2205 | /* Last reset was system reset */ | |
2206 | 0x00000300); | |
2207 | /* XXX : not implemented */ | |
2208 | spr_register(env, SPR_40x_DAC1, "DAC", | |
2209 | SPR_NOACCESS, SPR_NOACCESS, | |
2210 | &spr_read_generic, &spr_write_generic, | |
2211 | 0x00000000); | |
2212 | /* XXX : not implemented */ | |
2213 | spr_register(env, SPR_40x_IAC1, "IAC", | |
2214 | SPR_NOACCESS, SPR_NOACCESS, | |
2215 | &spr_read_generic, &spr_write_generic, | |
2216 | 0x00000000); | |
2217 | /* Storage control */ | |
035feb88 | 2218 | /* XXX: TODO: not implemented */ |
2662a059 JM |
2219 | spr_register(env, SPR_405_SLER, "SLER", |
2220 | SPR_NOACCESS, SPR_NOACCESS, | |
2221 | &spr_read_generic, &spr_write_40x_sler, | |
2222 | 0x00000000); | |
5cbdb3a3 | 2223 | /* not emulated, as QEMU never does speculative access */ |
035feb88 JM |
2224 | spr_register(env, SPR_40x_SGR, "SGR", |
2225 | SPR_NOACCESS, SPR_NOACCESS, | |
2226 | &spr_read_generic, &spr_write_generic, | |
2227 | 0xFFFFFFFF); | |
5cbdb3a3 | 2228 | /* not emulated, as QEMU do not emulate caches */ |
035feb88 JM |
2229 | spr_register(env, SPR_40x_DCWR, "DCWR", |
2230 | SPR_NOACCESS, SPR_NOACCESS, | |
2231 | &spr_read_generic, &spr_write_generic, | |
2232 | 0x00000000); | |
2662a059 JM |
2233 | } |
2234 | ||
a750fc0b JM |
2235 | static void gen_spr_401x2 (CPUPPCState *env) |
2236 | { | |
2237 | gen_spr_401(env); | |
2238 | spr_register(env, SPR_40x_PID, "PID", | |
2239 | SPR_NOACCESS, SPR_NOACCESS, | |
2240 | &spr_read_generic, &spr_write_generic, | |
2241 | 0x00000000); | |
2242 | spr_register(env, SPR_40x_ZPR, "ZPR", | |
2243 | SPR_NOACCESS, SPR_NOACCESS, | |
2244 | &spr_read_generic, &spr_write_generic, | |
2245 | 0x00000000); | |
2246 | } | |
2247 | ||
76a66253 JM |
2248 | /* SPR specific to PowerPC 403 implementation */ |
2249 | static void gen_spr_403 (CPUPPCState *env) | |
2250 | { | |
2662a059 JM |
2251 | /* Debug interface */ |
2252 | /* XXX : not implemented */ | |
2253 | spr_register(env, SPR_40x_DBCR0, "DBCR0", | |
2254 | SPR_NOACCESS, SPR_NOACCESS, | |
2255 | &spr_read_generic, &spr_write_40x_dbcr0, | |
2256 | 0x00000000); | |
2257 | /* XXX : not implemented */ | |
2258 | spr_register(env, SPR_40x_DBSR, "DBSR", | |
2259 | SPR_NOACCESS, SPR_NOACCESS, | |
2260 | &spr_read_generic, &spr_write_clear, | |
2261 | /* Last reset was system reset */ | |
2262 | 0x00000300); | |
2263 | /* XXX : not implemented */ | |
2264 | spr_register(env, SPR_40x_DAC1, "DAC1", | |
2265 | SPR_NOACCESS, SPR_NOACCESS, | |
2266 | &spr_read_generic, &spr_write_generic, | |
2267 | 0x00000000); | |
578bb252 | 2268 | /* XXX : not implemented */ |
2662a059 JM |
2269 | spr_register(env, SPR_40x_DAC2, "DAC2", |
2270 | SPR_NOACCESS, SPR_NOACCESS, | |
2271 | &spr_read_generic, &spr_write_generic, | |
2272 | 0x00000000); | |
2273 | /* XXX : not implemented */ | |
2274 | spr_register(env, SPR_40x_IAC1, "IAC1", | |
2275 | SPR_NOACCESS, SPR_NOACCESS, | |
2276 | &spr_read_generic, &spr_write_generic, | |
2277 | 0x00000000); | |
578bb252 | 2278 | /* XXX : not implemented */ |
2662a059 JM |
2279 | spr_register(env, SPR_40x_IAC2, "IAC2", |
2280 | SPR_NOACCESS, SPR_NOACCESS, | |
2281 | &spr_read_generic, &spr_write_generic, | |
2282 | 0x00000000); | |
a750fc0b JM |
2283 | } |
2284 | ||
2285 | static void gen_spr_403_real (CPUPPCState *env) | |
2286 | { | |
76a66253 JM |
2287 | spr_register(env, SPR_403_PBL1, "PBL1", |
2288 | SPR_NOACCESS, SPR_NOACCESS, | |
2289 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2290 | 0x00000000); | |
2291 | spr_register(env, SPR_403_PBU1, "PBU1", | |
2292 | SPR_NOACCESS, SPR_NOACCESS, | |
2293 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2294 | 0x00000000); | |
2295 | spr_register(env, SPR_403_PBL2, "PBL2", | |
2296 | SPR_NOACCESS, SPR_NOACCESS, | |
2297 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2298 | 0x00000000); | |
2299 | spr_register(env, SPR_403_PBU2, "PBU2", | |
2300 | SPR_NOACCESS, SPR_NOACCESS, | |
2301 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2302 | 0x00000000); | |
a750fc0b JM |
2303 | } |
2304 | ||
2305 | static void gen_spr_403_mmu (CPUPPCState *env) | |
2306 | { | |
2307 | /* MMU */ | |
2308 | spr_register(env, SPR_40x_PID, "PID", | |
2309 | SPR_NOACCESS, SPR_NOACCESS, | |
2310 | &spr_read_generic, &spr_write_generic, | |
2311 | 0x00000000); | |
2662a059 | 2312 | spr_register(env, SPR_40x_ZPR, "ZPR", |
76a66253 JM |
2313 | SPR_NOACCESS, SPR_NOACCESS, |
2314 | &spr_read_generic, &spr_write_generic, | |
2315 | 0x00000000); | |
2316 | } | |
2317 | ||
2318 | /* SPR specific to PowerPC compression coprocessor extension */ | |
76a66253 JM |
2319 | static void gen_spr_compress (CPUPPCState *env) |
2320 | { | |
578bb252 | 2321 | /* XXX : not implemented */ |
76a66253 JM |
2322 | spr_register(env, SPR_401_SKR, "SKR", |
2323 | SPR_NOACCESS, SPR_NOACCESS, | |
2324 | &spr_read_generic, &spr_write_generic, | |
2325 | 0x00000000); | |
2326 | } | |
a750fc0b | 2327 | |
80d11f44 | 2328 | static void gen_spr_5xx_8xx (CPUPPCState *env) |
e1833e1f | 2329 | { |
80d11f44 | 2330 | /* Exception processing */ |
d67d40ea DG |
2331 | spr_register_kvm(env, SPR_DSISR, "DSISR", |
2332 | SPR_NOACCESS, SPR_NOACCESS, | |
2333 | &spr_read_generic, &spr_write_generic, | |
2334 | KVM_REG_PPC_DSISR, 0x00000000); | |
2335 | spr_register_kvm(env, SPR_DAR, "DAR", | |
2336 | SPR_NOACCESS, SPR_NOACCESS, | |
2337 | &spr_read_generic, &spr_write_generic, | |
2338 | KVM_REG_PPC_DAR, 0x00000000); | |
80d11f44 JM |
2339 | /* Timer */ |
2340 | spr_register(env, SPR_DECR, "DECR", | |
2341 | SPR_NOACCESS, SPR_NOACCESS, | |
2342 | &spr_read_decr, &spr_write_decr, | |
2343 | 0x00000000); | |
2344 | /* XXX : not implemented */ | |
2345 | spr_register(env, SPR_MPC_EIE, "EIE", | |
2346 | SPR_NOACCESS, SPR_NOACCESS, | |
2347 | &spr_read_generic, &spr_write_generic, | |
2348 | 0x00000000); | |
2349 | /* XXX : not implemented */ | |
2350 | spr_register(env, SPR_MPC_EID, "EID", | |
2351 | SPR_NOACCESS, SPR_NOACCESS, | |
2352 | &spr_read_generic, &spr_write_generic, | |
2353 | 0x00000000); | |
2354 | /* XXX : not implemented */ | |
2355 | spr_register(env, SPR_MPC_NRI, "NRI", | |
2356 | SPR_NOACCESS, SPR_NOACCESS, | |
2357 | &spr_read_generic, &spr_write_generic, | |
2358 | 0x00000000); | |
2359 | /* XXX : not implemented */ | |
2360 | spr_register(env, SPR_MPC_CMPA, "CMPA", | |
2361 | SPR_NOACCESS, SPR_NOACCESS, | |
2362 | &spr_read_generic, &spr_write_generic, | |
2363 | 0x00000000); | |
2364 | /* XXX : not implemented */ | |
2365 | spr_register(env, SPR_MPC_CMPB, "CMPB", | |
2366 | SPR_NOACCESS, SPR_NOACCESS, | |
2367 | &spr_read_generic, &spr_write_generic, | |
2368 | 0x00000000); | |
2369 | /* XXX : not implemented */ | |
2370 | spr_register(env, SPR_MPC_CMPC, "CMPC", | |
2371 | SPR_NOACCESS, SPR_NOACCESS, | |
2372 | &spr_read_generic, &spr_write_generic, | |
2373 | 0x00000000); | |
2374 | /* XXX : not implemented */ | |
2375 | spr_register(env, SPR_MPC_CMPD, "CMPD", | |
2376 | SPR_NOACCESS, SPR_NOACCESS, | |
2377 | &spr_read_generic, &spr_write_generic, | |
2378 | 0x00000000); | |
2379 | /* XXX : not implemented */ | |
2380 | spr_register(env, SPR_MPC_ECR, "ECR", | |
2381 | SPR_NOACCESS, SPR_NOACCESS, | |
2382 | &spr_read_generic, &spr_write_generic, | |
2383 | 0x00000000); | |
2384 | /* XXX : not implemented */ | |
2385 | spr_register(env, SPR_MPC_DER, "DER", | |
2386 | SPR_NOACCESS, SPR_NOACCESS, | |
2387 | &spr_read_generic, &spr_write_generic, | |
2388 | 0x00000000); | |
2389 | /* XXX : not implemented */ | |
2390 | spr_register(env, SPR_MPC_COUNTA, "COUNTA", | |
2391 | SPR_NOACCESS, SPR_NOACCESS, | |
2392 | &spr_read_generic, &spr_write_generic, | |
2393 | 0x00000000); | |
2394 | /* XXX : not implemented */ | |
2395 | spr_register(env, SPR_MPC_COUNTB, "COUNTB", | |
2396 | SPR_NOACCESS, SPR_NOACCESS, | |
2397 | &spr_read_generic, &spr_write_generic, | |
2398 | 0x00000000); | |
2399 | /* XXX : not implemented */ | |
2400 | spr_register(env, SPR_MPC_CMPE, "CMPE", | |
2401 | SPR_NOACCESS, SPR_NOACCESS, | |
2402 | &spr_read_generic, &spr_write_generic, | |
2403 | 0x00000000); | |
2404 | /* XXX : not implemented */ | |
2405 | spr_register(env, SPR_MPC_CMPF, "CMPF", | |
2406 | SPR_NOACCESS, SPR_NOACCESS, | |
2407 | &spr_read_generic, &spr_write_generic, | |
2408 | 0x00000000); | |
2409 | /* XXX : not implemented */ | |
2410 | spr_register(env, SPR_MPC_CMPG, "CMPG", | |
2411 | SPR_NOACCESS, SPR_NOACCESS, | |
2412 | &spr_read_generic, &spr_write_generic, | |
2413 | 0x00000000); | |
2414 | /* XXX : not implemented */ | |
2415 | spr_register(env, SPR_MPC_CMPH, "CMPH", | |
2416 | SPR_NOACCESS, SPR_NOACCESS, | |
2417 | &spr_read_generic, &spr_write_generic, | |
2418 | 0x00000000); | |
2419 | /* XXX : not implemented */ | |
2420 | spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", | |
2421 | SPR_NOACCESS, SPR_NOACCESS, | |
2422 | &spr_read_generic, &spr_write_generic, | |
2423 | 0x00000000); | |
2424 | /* XXX : not implemented */ | |
2425 | spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", | |
2426 | SPR_NOACCESS, SPR_NOACCESS, | |
2427 | &spr_read_generic, &spr_write_generic, | |
2428 | 0x00000000); | |
2429 | /* XXX : not implemented */ | |
2430 | spr_register(env, SPR_MPC_BAR, "BAR", | |
2431 | SPR_NOACCESS, SPR_NOACCESS, | |
2432 | &spr_read_generic, &spr_write_generic, | |
2433 | 0x00000000); | |
2434 | /* XXX : not implemented */ | |
2435 | spr_register(env, SPR_MPC_DPDR, "DPDR", | |
2436 | SPR_NOACCESS, SPR_NOACCESS, | |
2437 | &spr_read_generic, &spr_write_generic, | |
2438 | 0x00000000); | |
2439 | /* XXX : not implemented */ | |
2440 | spr_register(env, SPR_MPC_IMMR, "IMMR", | |
2441 | SPR_NOACCESS, SPR_NOACCESS, | |
2442 | &spr_read_generic, &spr_write_generic, | |
2443 | 0x00000000); | |
2444 | } | |
2445 | ||
2446 | static void gen_spr_5xx (CPUPPCState *env) | |
2447 | { | |
2448 | /* XXX : not implemented */ | |
2449 | spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", | |
2450 | SPR_NOACCESS, SPR_NOACCESS, | |
2451 | &spr_read_generic, &spr_write_generic, | |
2452 | 0x00000000); | |
2453 | /* XXX : not implemented */ | |
2454 | spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", | |
2455 | SPR_NOACCESS, SPR_NOACCESS, | |
2456 | &spr_read_generic, &spr_write_generic, | |
2457 | 0x00000000); | |
2458 | /* XXX : not implemented */ | |
2459 | spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", | |
2460 | SPR_NOACCESS, SPR_NOACCESS, | |
2461 | &spr_read_generic, &spr_write_generic, | |
2462 | 0x00000000); | |
2463 | /* XXX : not implemented */ | |
2464 | spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", | |
2465 | SPR_NOACCESS, SPR_NOACCESS, | |
2466 | &spr_read_generic, &spr_write_generic, | |
2467 | 0x00000000); | |
2468 | /* XXX : not implemented */ | |
2469 | spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", | |
2470 | SPR_NOACCESS, SPR_NOACCESS, | |
2471 | &spr_read_generic, &spr_write_generic, | |
2472 | 0x00000000); | |
2473 | /* XXX : not implemented */ | |
2474 | spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", | |
2475 | SPR_NOACCESS, SPR_NOACCESS, | |
2476 | &spr_read_generic, &spr_write_generic, | |
2477 | 0x00000000); | |
2478 | /* XXX : not implemented */ | |
2479 | spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", | |
2480 | SPR_NOACCESS, SPR_NOACCESS, | |
2481 | &spr_read_generic, &spr_write_generic, | |
2482 | 0x00000000); | |
2483 | /* XXX : not implemented */ | |
2484 | spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", | |
2485 | SPR_NOACCESS, SPR_NOACCESS, | |
2486 | &spr_read_generic, &spr_write_generic, | |
2487 | 0x00000000); | |
2488 | /* XXX : not implemented */ | |
2489 | spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", | |
2490 | SPR_NOACCESS, SPR_NOACCESS, | |
2491 | &spr_read_generic, &spr_write_generic, | |
2492 | 0x00000000); | |
2493 | /* XXX : not implemented */ | |
2494 | spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", | |
2495 | SPR_NOACCESS, SPR_NOACCESS, | |
2496 | &spr_read_generic, &spr_write_generic, | |
2497 | 0x00000000); | |
2498 | /* XXX : not implemented */ | |
2499 | spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", | |
2500 | SPR_NOACCESS, SPR_NOACCESS, | |
2501 | &spr_read_generic, &spr_write_generic, | |
2502 | 0x00000000); | |
2503 | /* XXX : not implemented */ | |
2504 | spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", | |
2505 | SPR_NOACCESS, SPR_NOACCESS, | |
2506 | &spr_read_generic, &spr_write_generic, | |
2507 | 0x00000000); | |
2508 | /* XXX : not implemented */ | |
2509 | spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", | |
2510 | SPR_NOACCESS, SPR_NOACCESS, | |
2511 | &spr_read_generic, &spr_write_generic, | |
2512 | 0x00000000); | |
2513 | /* XXX : not implemented */ | |
2514 | spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", | |
2515 | SPR_NOACCESS, SPR_NOACCESS, | |
2516 | &spr_read_generic, &spr_write_generic, | |
2517 | 0x00000000); | |
2518 | /* XXX : not implemented */ | |
2519 | spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", | |
2520 | SPR_NOACCESS, SPR_NOACCESS, | |
2521 | &spr_read_generic, &spr_write_generic, | |
2522 | 0x00000000); | |
2523 | /* XXX : not implemented */ | |
2524 | spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", | |
2525 | SPR_NOACCESS, SPR_NOACCESS, | |
2526 | &spr_read_generic, &spr_write_generic, | |
2527 | 0x00000000); | |
2528 | /* XXX : not implemented */ | |
2529 | spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", | |
2530 | SPR_NOACCESS, SPR_NOACCESS, | |
2531 | &spr_read_generic, &spr_write_generic, | |
2532 | 0x00000000); | |
2533 | /* XXX : not implemented */ | |
2534 | spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", | |
2535 | SPR_NOACCESS, SPR_NOACCESS, | |
2536 | &spr_read_generic, &spr_write_generic, | |
2537 | 0x00000000); | |
2538 | /* XXX : not implemented */ | |
2539 | spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", | |
2540 | SPR_NOACCESS, SPR_NOACCESS, | |
2541 | &spr_read_generic, &spr_write_generic, | |
2542 | 0x00000000); | |
2543 | /* XXX : not implemented */ | |
2544 | spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", | |
2545 | SPR_NOACCESS, SPR_NOACCESS, | |
2546 | &spr_read_generic, &spr_write_generic, | |
2547 | 0x00000000); | |
2548 | /* XXX : not implemented */ | |
2549 | spr_register(env, SPR_RCPU_FPECR, "FPECR", | |
2550 | SPR_NOACCESS, SPR_NOACCESS, | |
2551 | &spr_read_generic, &spr_write_generic, | |
2552 | 0x00000000); | |
2553 | } | |
2554 | ||
2555 | static void gen_spr_8xx (CPUPPCState *env) | |
2556 | { | |
2557 | /* XXX : not implemented */ | |
2558 | spr_register(env, SPR_MPC_IC_CST, "IC_CST", | |
2559 | SPR_NOACCESS, SPR_NOACCESS, | |
2560 | &spr_read_generic, &spr_write_generic, | |
2561 | 0x00000000); | |
2562 | /* XXX : not implemented */ | |
2563 | spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", | |
2564 | SPR_NOACCESS, SPR_NOACCESS, | |
2565 | &spr_read_generic, &spr_write_generic, | |
2566 | 0x00000000); | |
2567 | /* XXX : not implemented */ | |
2568 | spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", | |
2569 | SPR_NOACCESS, SPR_NOACCESS, | |
2570 | &spr_read_generic, &spr_write_generic, | |
2571 | 0x00000000); | |
2572 | /* XXX : not implemented */ | |
2573 | spr_register(env, SPR_MPC_DC_CST, "DC_CST", | |
2574 | SPR_NOACCESS, SPR_NOACCESS, | |
2575 | &spr_read_generic, &spr_write_generic, | |
2576 | 0x00000000); | |
2577 | /* XXX : not implemented */ | |
2578 | spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", | |
2579 | SPR_NOACCESS, SPR_NOACCESS, | |
2580 | &spr_read_generic, &spr_write_generic, | |
2581 | 0x00000000); | |
2582 | /* XXX : not implemented */ | |
2583 | spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", | |
2584 | SPR_NOACCESS, SPR_NOACCESS, | |
2585 | &spr_read_generic, &spr_write_generic, | |
2586 | 0x00000000); | |
2587 | /* XXX : not implemented */ | |
2588 | spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", | |
2589 | SPR_NOACCESS, SPR_NOACCESS, | |
2590 | &spr_read_generic, &spr_write_generic, | |
2591 | 0x00000000); | |
2592 | /* XXX : not implemented */ | |
2593 | spr_register(env, SPR_MPC_MI_AP, "MI_AP", | |
2594 | SPR_NOACCESS, SPR_NOACCESS, | |
2595 | &spr_read_generic, &spr_write_generic, | |
2596 | 0x00000000); | |
2597 | /* XXX : not implemented */ | |
2598 | spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", | |
2599 | SPR_NOACCESS, SPR_NOACCESS, | |
2600 | &spr_read_generic, &spr_write_generic, | |
2601 | 0x00000000); | |
2602 | /* XXX : not implemented */ | |
2603 | spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", | |
2604 | SPR_NOACCESS, SPR_NOACCESS, | |
2605 | &spr_read_generic, &spr_write_generic, | |
2606 | 0x00000000); | |
2607 | /* XXX : not implemented */ | |
2608 | spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", | |
2609 | SPR_NOACCESS, SPR_NOACCESS, | |
2610 | &spr_read_generic, &spr_write_generic, | |
2611 | 0x00000000); | |
2612 | /* XXX : not implemented */ | |
2613 | spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", | |
2614 | SPR_NOACCESS, SPR_NOACCESS, | |
2615 | &spr_read_generic, &spr_write_generic, | |
2616 | 0x00000000); | |
2617 | /* XXX : not implemented */ | |
2618 | spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", | |
2619 | SPR_NOACCESS, SPR_NOACCESS, | |
2620 | &spr_read_generic, &spr_write_generic, | |
2621 | 0x00000000); | |
2622 | /* XXX : not implemented */ | |
2623 | spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", | |
2624 | SPR_NOACCESS, SPR_NOACCESS, | |
2625 | &spr_read_generic, &spr_write_generic, | |
2626 | 0x00000000); | |
2627 | /* XXX : not implemented */ | |
2628 | spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", | |
2629 | SPR_NOACCESS, SPR_NOACCESS, | |
2630 | &spr_read_generic, &spr_write_generic, | |
2631 | 0x00000000); | |
2632 | /* XXX : not implemented */ | |
2633 | spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", | |
2634 | SPR_NOACCESS, SPR_NOACCESS, | |
2635 | &spr_read_generic, &spr_write_generic, | |
2636 | 0x00000000); | |
2637 | /* XXX : not implemented */ | |
2638 | spr_register(env, SPR_MPC_MD_AP, "MD_AP", | |
2639 | SPR_NOACCESS, SPR_NOACCESS, | |
2640 | &spr_read_generic, &spr_write_generic, | |
2641 | 0x00000000); | |
2642 | /* XXX : not implemented */ | |
2643 | spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", | |
2644 | SPR_NOACCESS, SPR_NOACCESS, | |
2645 | &spr_read_generic, &spr_write_generic, | |
2646 | 0x00000000); | |
2647 | /* XXX : not implemented */ | |
2648 | spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", | |
2649 | SPR_NOACCESS, SPR_NOACCESS, | |
2650 | &spr_read_generic, &spr_write_generic, | |
2651 | 0x00000000); | |
2652 | /* XXX : not implemented */ | |
2653 | spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", | |
2654 | SPR_NOACCESS, SPR_NOACCESS, | |
2655 | &spr_read_generic, &spr_write_generic, | |
2656 | 0x00000000); | |
2657 | /* XXX : not implemented */ | |
2658 | spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", | |
2659 | SPR_NOACCESS, SPR_NOACCESS, | |
2660 | &spr_read_generic, &spr_write_generic, | |
2661 | 0x00000000); | |
2662 | /* XXX : not implemented */ | |
2663 | spr_register(env, SPR_MPC_MD_TW, "MD_TW", | |
2664 | SPR_NOACCESS, SPR_NOACCESS, | |
2665 | &spr_read_generic, &spr_write_generic, | |
2666 | 0x00000000); | |
2667 | /* XXX : not implemented */ | |
2668 | spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", | |
2669 | SPR_NOACCESS, SPR_NOACCESS, | |
2670 | &spr_read_generic, &spr_write_generic, | |
2671 | 0x00000000); | |
2672 | /* XXX : not implemented */ | |
2673 | spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", | |
2674 | SPR_NOACCESS, SPR_NOACCESS, | |
2675 | &spr_read_generic, &spr_write_generic, | |
2676 | 0x00000000); | |
2677 | /* XXX : not implemented */ | |
2678 | spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", | |
2679 | SPR_NOACCESS, SPR_NOACCESS, | |
2680 | &spr_read_generic, &spr_write_generic, | |
2681 | 0x00000000); | |
2682 | } | |
2683 | ||
2684 | // XXX: TODO | |
2685 | /* | |
2686 | * AMR => SPR 29 (Power 2.04) | |
2687 | * CTRL => SPR 136 (Power 2.04) | |
2688 | * CTRL => SPR 152 (Power 2.04) | |
2689 | * SCOMC => SPR 276 (64 bits ?) | |
2690 | * SCOMD => SPR 277 (64 bits ?) | |
2691 | * TBU40 => SPR 286 (Power 2.04 hypv) | |
2692 | * HSPRG0 => SPR 304 (Power 2.04 hypv) | |
2693 | * HSPRG1 => SPR 305 (Power 2.04 hypv) | |
2694 | * HDSISR => SPR 306 (Power 2.04 hypv) | |
2695 | * HDAR => SPR 307 (Power 2.04 hypv) | |
2696 | * PURR => SPR 309 (Power 2.04 hypv) | |
2697 | * HDEC => SPR 310 (Power 2.04 hypv) | |
2698 | * HIOR => SPR 311 (hypv) | |
2699 | * RMOR => SPR 312 (970) | |
2700 | * HRMOR => SPR 313 (Power 2.04 hypv) | |
2701 | * HSRR0 => SPR 314 (Power 2.04 hypv) | |
2702 | * HSRR1 => SPR 315 (Power 2.04 hypv) | |
80d11f44 | 2703 | * LPIDR => SPR 317 (970) |
80d11f44 JM |
2704 | * EPR => SPR 702 (Power 2.04 emb) |
2705 | * perf => 768-783 (Power 2.04) | |
2706 | * perf => 784-799 (Power 2.04) | |
2707 | * PPR => SPR 896 (Power 2.04) | |
2708 | * EPLC => SPR 947 (Power 2.04 emb) | |
2709 | * EPSC => SPR 948 (Power 2.04 emb) | |
2710 | * DABRX => 1015 (Power 2.04 hypv) | |
2711 | * FPECR => SPR 1022 (?) | |
2712 | * ... and more (thermal management, performance counters, ...) | |
2713 | */ | |
2714 | ||
2715 | /*****************************************************************************/ | |
2716 | /* Exception vectors models */ | |
2717 | static void init_excp_4xx_real (CPUPPCState *env) | |
2718 | { | |
2719 | #if !defined(CONFIG_USER_ONLY) | |
2720 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; | |
2721 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2722 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2723 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2724 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2725 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2726 | env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; | |
2727 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; | |
2728 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; | |
2729 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; | |
80d11f44 | 2730 | env->ivor_mask = 0x0000FFF0UL; |
faadf50e | 2731 | env->ivpr_mask = 0xFFFF0000UL; |
1c27f8fb JM |
2732 | /* Hardware reset vector */ |
2733 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2734 | #endif |
2735 | } | |
2736 | ||
80d11f44 JM |
2737 | static void init_excp_4xx_softmmu (CPUPPCState *env) |
2738 | { | |
2739 | #if !defined(CONFIG_USER_ONLY) | |
2740 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; | |
2741 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2742 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2743 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2744 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2745 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2746 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2747 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2748 | env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; | |
2749 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; | |
2750 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; | |
2751 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; | |
2752 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; | |
2753 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; | |
80d11f44 JM |
2754 | env->ivor_mask = 0x0000FFF0UL; |
2755 | env->ivpr_mask = 0xFFFF0000UL; | |
2756 | /* Hardware reset vector */ | |
2757 | env->hreset_vector = 0xFFFFFFFCUL; | |
2758 | #endif | |
2759 | } | |
2760 | ||
2761 | static void init_excp_MPC5xx (CPUPPCState *env) | |
2762 | { | |
2763 | #if !defined(CONFIG_USER_ONLY) | |
2764 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2765 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2766 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2767 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2768 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2769 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; | |
2770 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2771 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2772 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2773 | env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; | |
2774 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; | |
2775 | env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; | |
2776 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; | |
2777 | env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; | |
2778 | env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; | |
80d11f44 JM |
2779 | env->ivor_mask = 0x0000FFF0UL; |
2780 | env->ivpr_mask = 0xFFFF0000UL; | |
2781 | /* Hardware reset vector */ | |
09d9828a | 2782 | env->hreset_vector = 0x00000100UL; |
80d11f44 JM |
2783 | #endif |
2784 | } | |
2785 | ||
2786 | static void init_excp_MPC8xx (CPUPPCState *env) | |
e1833e1f JM |
2787 | { |
2788 | #if !defined(CONFIG_USER_ONLY) | |
2789 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2790 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2791 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2792 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2793 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2794 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2795 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
80d11f44 | 2796 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
e1833e1f | 2797 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
e1833e1f | 2798 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
80d11f44 JM |
2799 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
2800 | env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; | |
2801 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; | |
2802 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; | |
2803 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; | |
2804 | env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; | |
2805 | env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; | |
2806 | env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; | |
2807 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; | |
2808 | env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; | |
2809 | env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; | |
80d11f44 JM |
2810 | env->ivor_mask = 0x0000FFF0UL; |
2811 | env->ivpr_mask = 0xFFFF0000UL; | |
1c27f8fb | 2812 | /* Hardware reset vector */ |
09d9828a | 2813 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2814 | #endif |
2815 | } | |
2816 | ||
80d11f44 | 2817 | static void init_excp_G2 (CPUPPCState *env) |
e1833e1f JM |
2818 | { |
2819 | #if !defined(CONFIG_USER_ONLY) | |
2820 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2821 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2822 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2823 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2824 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2825 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2826 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2827 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2828 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
80d11f44 | 2829 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; |
e1833e1f JM |
2830 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
2831 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
e1833e1f JM |
2832 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
2833 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2834 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2835 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2836 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
80d11f44 | 2837 | /* Hardware reset vector */ |
09d9828a | 2838 | env->hreset_vector = 0x00000100UL; |
80d11f44 JM |
2839 | #endif |
2840 | } | |
2841 | ||
e9cd84b9 | 2842 | static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) |
80d11f44 JM |
2843 | { |
2844 | #if !defined(CONFIG_USER_ONLY) | |
2845 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; | |
2846 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; | |
2847 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; | |
2848 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; | |
2849 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; | |
2850 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; | |
2851 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; | |
2852 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; | |
2853 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; | |
2854 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; | |
2855 | env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; | |
2856 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; | |
2857 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; | |
2858 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; | |
2859 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; | |
2860 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; | |
2861 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; | |
2862 | env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; | |
2863 | env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; | |
2864 | env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; | |
80d11f44 | 2865 | env->ivor_mask = 0x0000FFF7UL; |
e9cd84b9 | 2866 | env->ivpr_mask = ivpr_mask; |
80d11f44 JM |
2867 | /* Hardware reset vector */ |
2868 | env->hreset_vector = 0xFFFFFFFCUL; | |
2869 | #endif | |
2870 | } | |
2871 | ||
2872 | static void init_excp_BookE (CPUPPCState *env) | |
2873 | { | |
2874 | #if !defined(CONFIG_USER_ONLY) | |
2875 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; | |
2876 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; | |
2877 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; | |
2878 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; | |
2879 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; | |
2880 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; | |
2881 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; | |
2882 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; | |
2883 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; | |
2884 | env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; | |
2885 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; | |
2886 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; | |
2887 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; | |
2888 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; | |
2889 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; | |
2890 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; | |
8412d112 | 2891 | env->ivor_mask = 0x0000FFF0UL; |
80d11f44 JM |
2892 | env->ivpr_mask = 0xFFFF0000UL; |
2893 | /* Hardware reset vector */ | |
2894 | env->hreset_vector = 0xFFFFFFFCUL; | |
2895 | #endif | |
2896 | } | |
2897 | ||
2898 | static void init_excp_601 (CPUPPCState *env) | |
2899 | { | |
2900 | #if !defined(CONFIG_USER_ONLY) | |
2901 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2902 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2903 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2904 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2905 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2906 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2907 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2908 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2909 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2910 | env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; | |
2911 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2912 | env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; | |
1c27f8fb | 2913 | /* Hardware reset vector */ |
80d11f44 | 2914 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2915 | #endif |
2916 | } | |
2917 | ||
80d11f44 | 2918 | static void init_excp_602 (CPUPPCState *env) |
e1833e1f JM |
2919 | { |
2920 | #if !defined(CONFIG_USER_ONLY) | |
082c6681 | 2921 | /* XXX: exception prefix has a special behavior on 602 */ |
e1833e1f JM |
2922 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
2923 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2924 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2925 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2926 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2927 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2928 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2929 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2930 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2931 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2932 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2933 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
2934 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2935 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2936 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2937 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
80d11f44 JM |
2938 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; |
2939 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; | |
1c27f8fb | 2940 | /* Hardware reset vector */ |
09d9828a | 2941 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2942 | #endif |
2943 | } | |
2944 | ||
80d11f44 | 2945 | static void init_excp_603 (CPUPPCState *env) |
e1833e1f JM |
2946 | { |
2947 | #if !defined(CONFIG_USER_ONLY) | |
2948 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2949 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2950 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2951 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2952 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2953 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2954 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2955 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2956 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
e1833e1f JM |
2957 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
2958 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2959 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
2960 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2961 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2962 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2963 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
1c27f8fb | 2964 | /* Hardware reset vector */ |
09d9828a | 2965 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2966 | #endif |
2967 | } | |
2968 | ||
2969 | static void init_excp_604 (CPUPPCState *env) | |
2970 | { | |
2971 | #if !defined(CONFIG_USER_ONLY) | |
2972 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2973 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2974 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2975 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2976 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2977 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2978 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2979 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2980 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2981 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2982 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2983 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2984 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2985 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
1c27f8fb | 2986 | /* Hardware reset vector */ |
2d3eb7bf | 2987 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2988 | #endif |
2989 | } | |
2990 | ||
e1833e1f JM |
2991 | static void init_excp_7x0 (CPUPPCState *env) |
2992 | { | |
2993 | #if !defined(CONFIG_USER_ONLY) | |
2994 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2995 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2996 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2997 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2998 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2999 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3000 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3001 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3002 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3003 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3004 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3005 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3006 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
bd928eba | 3007 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
e1833e1f | 3008 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
1c27f8fb | 3009 | /* Hardware reset vector */ |
09d9828a | 3010 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
3011 | #endif |
3012 | } | |
3013 | ||
bd928eba | 3014 | static void init_excp_750cl (CPUPPCState *env) |
e1833e1f JM |
3015 | { |
3016 | #if !defined(CONFIG_USER_ONLY) | |
3017 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3018 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3019 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3020 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3021 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3022 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3023 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3024 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3025 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3026 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3027 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3028 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3029 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3030 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
bd928eba | 3031 | /* Hardware reset vector */ |
09d9828a | 3032 | env->hreset_vector = 0x00000100UL; |
bd928eba JM |
3033 | #endif |
3034 | } | |
3035 | ||
3036 | static void init_excp_750cx (CPUPPCState *env) | |
3037 | { | |
3038 | #if !defined(CONFIG_USER_ONLY) | |
3039 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3040 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3041 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3042 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3043 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3044 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3045 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3046 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3047 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3048 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3049 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3050 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3051 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
e1833e1f | 3052 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
1c27f8fb | 3053 | /* Hardware reset vector */ |
09d9828a | 3054 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
3055 | #endif |
3056 | } | |
3057 | ||
7a3a6927 JM |
3058 | /* XXX: Check if this is correct */ |
3059 | static void init_excp_7x5 (CPUPPCState *env) | |
3060 | { | |
3061 | #if !defined(CONFIG_USER_ONLY) | |
3062 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3063 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3064 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3065 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3066 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3067 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3068 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3069 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3070 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3071 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3072 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
bd928eba | 3073 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
7a3a6927 JM |
3074 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
3075 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
3076 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
7a3a6927 JM |
3077 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
3078 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
bd928eba | 3079 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
7a3a6927 | 3080 | /* Hardware reset vector */ |
09d9828a | 3081 | env->hreset_vector = 0x00000100UL; |
7a3a6927 JM |
3082 | #endif |
3083 | } | |
3084 | ||
e1833e1f JM |
3085 | static void init_excp_7400 (CPUPPCState *env) |
3086 | { | |
3087 | #if !defined(CONFIG_USER_ONLY) | |
3088 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3089 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3090 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3091 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3092 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3093 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3094 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3095 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3096 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3097 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3098 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3099 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3100 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3101 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3102 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
3103 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; | |
3104 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; | |
1c27f8fb | 3105 | /* Hardware reset vector */ |
09d9828a | 3106 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
3107 | #endif |
3108 | } | |
3109 | ||
e1833e1f JM |
3110 | static void init_excp_7450 (CPUPPCState *env) |
3111 | { | |
3112 | #if !defined(CONFIG_USER_ONLY) | |
3113 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3114 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3115 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3116 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3117 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3118 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3119 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3120 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3121 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3122 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3123 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3124 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3125 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3126 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
3127 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
3128 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
3129 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3130 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
3131 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; | |
1c27f8fb | 3132 | /* Hardware reset vector */ |
09d9828a | 3133 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
3134 | #endif |
3135 | } | |
e1833e1f JM |
3136 | |
3137 | #if defined (TARGET_PPC64) | |
3138 | static void init_excp_970 (CPUPPCState *env) | |
3139 | { | |
3140 | #if !defined(CONFIG_USER_ONLY) | |
3141 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3142 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3143 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3144 | env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; | |
3145 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3146 | env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; | |
3147 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3148 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3149 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3150 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3151 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
e1833e1f | 3152 | env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; |
e1833e1f JM |
3153 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
3154 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3155 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3156 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3157 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3158 | env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; | |
3159 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; | |
3160 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; | |
1c27f8fb JM |
3161 | /* Hardware reset vector */ |
3162 | env->hreset_vector = 0x0000000000000100ULL; | |
e1833e1f JM |
3163 | #endif |
3164 | } | |
9d52e907 DG |
3165 | |
3166 | static void init_excp_POWER7 (CPUPPCState *env) | |
3167 | { | |
3168 | #if !defined(CONFIG_USER_ONLY) | |
3169 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3170 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3171 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3172 | env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; | |
3173 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3174 | env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; | |
3175 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3176 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3177 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3178 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3179 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3180 | env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; | |
3181 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3182 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
f03a1af5 BH |
3183 | env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; |
3184 | env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; | |
3185 | env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; | |
3186 | env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; | |
9d52e907 DG |
3187 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
3188 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
1f29871c | 3189 | env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; |
9d52e907 DG |
3190 | /* Hardware reset vector */ |
3191 | env->hreset_vector = 0x0000000000000100ULL; | |
3192 | #endif | |
3193 | } | |
f03a1af5 BH |
3194 | |
3195 | static void init_excp_POWER8(CPUPPCState *env) | |
3196 | { | |
3197 | init_excp_POWER7(env); | |
3198 | ||
3199 | #if !defined(CONFIG_USER_ONLY) | |
3200 | env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; | |
3201 | env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; | |
3202 | env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; | |
3203 | env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; | |
3204 | #endif | |
3205 | } | |
3206 | ||
e1833e1f JM |
3207 | #endif |
3208 | ||
2f462816 JM |
3209 | /*****************************************************************************/ |
3210 | /* Power management enable checks */ | |
3211 | static int check_pow_none (CPUPPCState *env) | |
3212 | { | |
3213 | return 0; | |
3214 | } | |
3215 | ||
3216 | static int check_pow_nocheck (CPUPPCState *env) | |
3217 | { | |
3218 | return 1; | |
3219 | } | |
3220 | ||
3221 | static int check_pow_hid0 (CPUPPCState *env) | |
3222 | { | |
3223 | if (env->spr[SPR_HID0] & 0x00E00000) | |
3224 | return 1; | |
3225 | ||
3226 | return 0; | |
3227 | } | |
3228 | ||
4e777442 JM |
3229 | static int check_pow_hid0_74xx (CPUPPCState *env) |
3230 | { | |
3231 | if (env->spr[SPR_HID0] & 0x00600000) | |
3232 | return 1; | |
3233 | ||
3234 | return 0; | |
3235 | } | |
3236 | ||
382d2db6 GK |
3237 | static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) |
3238 | { | |
3239 | return true; | |
3240 | } | |
3241 | ||
3242 | #ifdef TARGET_PPC64 | |
3243 | static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) | |
3244 | { | |
3245 | return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); | |
3246 | } | |
3247 | #endif | |
3248 | ||
a750fc0b JM |
3249 | /*****************************************************************************/ |
3250 | /* PowerPC implementations definitions */ | |
76a66253 | 3251 | |
7856e3a4 AF |
3252 | #define POWERPC_FAMILY(_name) \ |
3253 | static void \ | |
3254 | glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ | |
3255 | \ | |
3256 | static const TypeInfo \ | |
3257 | glue(glue(ppc_, _name), _cpu_family_type_info) = { \ | |
3258 | .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ | |
3259 | .parent = TYPE_POWERPC_CPU, \ | |
3260 | .abstract = true, \ | |
3261 | .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ | |
3262 | }; \ | |
3263 | \ | |
3264 | static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ | |
3265 | { \ | |
3266 | type_register_static( \ | |
3267 | &glue(glue(ppc_, _name), _cpu_family_type_info)); \ | |
3268 | } \ | |
3269 | \ | |
3270 | type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ | |
3271 | \ | |
3272 | static void glue(glue(ppc_, _name), _cpu_family_class_init) | |
3273 | ||
a750fc0b JM |
3274 | static void init_proc_401 (CPUPPCState *env) |
3275 | { | |
3276 | gen_spr_40x(env); | |
3277 | gen_spr_401_403(env); | |
3278 | gen_spr_401(env); | |
e1833e1f | 3279 | init_excp_4xx_real(env); |
d63001d1 JM |
3280 | env->dcache_line_size = 32; |
3281 | env->icache_line_size = 32; | |
4e290a0b | 3282 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 3283 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3284 | |
3285 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3286 | SET_WDT_PERIOD(16, 20, 24, 28); | |
a750fc0b | 3287 | } |
76a66253 | 3288 | |
7856e3a4 AF |
3289 | POWERPC_FAMILY(401)(ObjectClass *oc, void *data) |
3290 | { | |
ca5dff0a | 3291 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3292 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3293 | ||
ca5dff0a | 3294 | dc->desc = "PowerPC 401"; |
7856e3a4 AF |
3295 | pcc->init_proc = init_proc_401; |
3296 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3297 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3298 | PPC_WRTEE | PPC_DCR | | |
3299 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3300 | PPC_CACHE_DCBZ | | |
3301 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3302 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
9df5a466 TM |
3303 | pcc->msr_mask = (1ull << MSR_KEY) | |
3304 | (1ull << MSR_POW) | | |
3305 | (1ull << MSR_CE) | | |
3306 | (1ull << MSR_ILE) | | |
3307 | (1ull << MSR_EE) | | |
3308 | (1ull << MSR_PR) | | |
3309 | (1ull << MSR_ME) | | |
3310 | (1ull << MSR_DE) | | |
3311 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
3312 | pcc->mmu_model = POWERPC_MMU_REAL; |
3313 | pcc->excp_model = POWERPC_EXCP_40x; | |
3314 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3315 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3316 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3317 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3318 | } |
3319 | ||
a750fc0b JM |
3320 | static void init_proc_401x2 (CPUPPCState *env) |
3321 | { | |
3322 | gen_spr_40x(env); | |
3323 | gen_spr_401_403(env); | |
3324 | gen_spr_401x2(env); | |
3325 | gen_spr_compress(env); | |
a750fc0b | 3326 | /* Memory management */ |
f2e63a42 | 3327 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3328 | env->nb_tlb = 64; |
3329 | env->nb_ways = 1; | |
3330 | env->id_tlbs = 0; | |
1c53accc | 3331 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3332 | #endif |
e1833e1f | 3333 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3334 | env->dcache_line_size = 32; |
3335 | env->icache_line_size = 32; | |
4e290a0b | 3336 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 3337 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3338 | |
3339 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3340 | SET_WDT_PERIOD(16, 20, 24, 28); | |
76a66253 JM |
3341 | } |
3342 | ||
7856e3a4 AF |
3343 | POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) |
3344 | { | |
ca5dff0a | 3345 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3346 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3347 | ||
ca5dff0a | 3348 | dc->desc = "PowerPC 401x2"; |
7856e3a4 AF |
3349 | pcc->init_proc = init_proc_401x2; |
3350 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3351 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
3352 | PPC_DCR | PPC_WRTEE | | |
3353 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3354 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3355 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3356 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3357 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
9df5a466 TM |
3358 | pcc->msr_mask = (1ull << 20) | |
3359 | (1ull << MSR_KEY) | | |
3360 | (1ull << MSR_POW) | | |
3361 | (1ull << MSR_CE) | | |
3362 | (1ull << MSR_ILE) | | |
3363 | (1ull << MSR_EE) | | |
3364 | (1ull << MSR_PR) | | |
3365 | (1ull << MSR_ME) | | |
3366 | (1ull << MSR_DE) | | |
3367 | (1ull << MSR_IR) | | |
3368 | (1ull << MSR_DR) | | |
3369 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
3370 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; |
3371 | pcc->excp_model = POWERPC_EXCP_40x; | |
3372 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3373 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3374 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3375 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3376 | } |
3377 | ||
e1833e1f | 3378 | static void init_proc_401x3 (CPUPPCState *env) |
76a66253 | 3379 | { |
4e290a0b JM |
3380 | gen_spr_40x(env); |
3381 | gen_spr_401_403(env); | |
3382 | gen_spr_401(env); | |
3383 | gen_spr_401x2(env); | |
3384 | gen_spr_compress(env); | |
e1833e1f | 3385 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3386 | env->dcache_line_size = 32; |
3387 | env->icache_line_size = 32; | |
4e290a0b | 3388 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 3389 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3390 | |
3391 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3392 | SET_WDT_PERIOD(16, 20, 24, 28); | |
3fc6c082 | 3393 | } |
a750fc0b | 3394 | |
7856e3a4 AF |
3395 | POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) |
3396 | { | |
ca5dff0a | 3397 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3398 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3399 | ||
ca5dff0a | 3400 | dc->desc = "PowerPC 401x3"; |
7856e3a4 AF |
3401 | pcc->init_proc = init_proc_401x3; |
3402 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3403 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
3404 | PPC_DCR | PPC_WRTEE | | |
3405 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3406 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3407 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3408 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3409 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
9df5a466 TM |
3410 | pcc->msr_mask = (1ull << 20) | |
3411 | (1ull << MSR_KEY) | | |
3412 | (1ull << MSR_POW) | | |
3413 | (1ull << MSR_CE) | | |
3414 | (1ull << MSR_ILE) | | |
3415 | (1ull << MSR_EE) | | |
3416 | (1ull << MSR_PR) | | |
3417 | (1ull << MSR_ME) | | |
3418 | (1ull << MSR_DWE) | | |
3419 | (1ull << MSR_DE) | | |
3420 | (1ull << MSR_IR) | | |
3421 | (1ull << MSR_DR) | | |
3422 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
3423 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; |
3424 | pcc->excp_model = POWERPC_EXCP_40x; | |
3425 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3426 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3427 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3428 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3429 | } |
3430 | ||
a750fc0b | 3431 | static void init_proc_IOP480 (CPUPPCState *env) |
3fc6c082 | 3432 | { |
a750fc0b JM |
3433 | gen_spr_40x(env); |
3434 | gen_spr_401_403(env); | |
3435 | gen_spr_401x2(env); | |
3436 | gen_spr_compress(env); | |
a750fc0b | 3437 | /* Memory management */ |
f2e63a42 | 3438 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3439 | env->nb_tlb = 64; |
3440 | env->nb_ways = 1; | |
3441 | env->id_tlbs = 0; | |
1c53accc | 3442 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3443 | #endif |
e1833e1f | 3444 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3445 | env->dcache_line_size = 32; |
3446 | env->icache_line_size = 32; | |
4e290a0b | 3447 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 3448 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3449 | |
3450 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3451 | SET_WDT_PERIOD(16, 20, 24, 28); | |
3fc6c082 FB |
3452 | } |
3453 | ||
7856e3a4 AF |
3454 | POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) |
3455 | { | |
ca5dff0a | 3456 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3457 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3458 | ||
ca5dff0a | 3459 | dc->desc = "IOP480"; |
7856e3a4 AF |
3460 | pcc->init_proc = init_proc_IOP480; |
3461 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3462 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3463 | PPC_DCR | PPC_WRTEE | | |
3464 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3465 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3466 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3467 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3468 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
9df5a466 TM |
3469 | pcc->msr_mask = (1ull << 20) | |
3470 | (1ull << MSR_KEY) | | |
3471 | (1ull << MSR_POW) | | |
3472 | (1ull << MSR_CE) | | |
3473 | (1ull << MSR_ILE) | | |
3474 | (1ull << MSR_EE) | | |
3475 | (1ull << MSR_PR) | | |
3476 | (1ull << MSR_ME) | | |
3477 | (1ull << MSR_DE) | | |
3478 | (1ull << MSR_IR) | | |
3479 | (1ull << MSR_DR) | | |
3480 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
3481 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; |
3482 | pcc->excp_model = POWERPC_EXCP_40x; | |
3483 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3484 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3485 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3486 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3487 | } |
3488 | ||
a750fc0b | 3489 | static void init_proc_403 (CPUPPCState *env) |
3fc6c082 | 3490 | { |
a750fc0b JM |
3491 | gen_spr_40x(env); |
3492 | gen_spr_401_403(env); | |
3493 | gen_spr_403(env); | |
3494 | gen_spr_403_real(env); | |
e1833e1f | 3495 | init_excp_4xx_real(env); |
d63001d1 JM |
3496 | env->dcache_line_size = 32; |
3497 | env->icache_line_size = 32; | |
4e290a0b | 3498 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 3499 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3500 | |
3501 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3502 | SET_WDT_PERIOD(16, 20, 24, 28); | |
3fc6c082 FB |
3503 | } |
3504 | ||
7856e3a4 AF |
3505 | POWERPC_FAMILY(403)(ObjectClass *oc, void *data) |
3506 | { | |
ca5dff0a | 3507 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3508 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3509 | ||
ca5dff0a | 3510 | dc->desc = "PowerPC 403"; |
7856e3a4 AF |
3511 | pcc->init_proc = init_proc_403; |
3512 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3513 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3514 | PPC_DCR | PPC_WRTEE | | |
3515 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3516 | PPC_CACHE_DCBZ | | |
3517 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3518 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
9df5a466 TM |
3519 | pcc->msr_mask = (1ull << MSR_POW) | |
3520 | (1ull << MSR_CE) | | |
3521 | (1ull << MSR_ILE) | | |
3522 | (1ull << MSR_EE) | | |
3523 | (1ull << MSR_PR) | | |
3524 | (1ull << MSR_ME) | | |
3525 | (1ull << MSR_PE) | | |
3526 | (1ull << MSR_PX) | | |
3527 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
3528 | pcc->mmu_model = POWERPC_MMU_REAL; |
3529 | pcc->excp_model = POWERPC_EXCP_40x; | |
3530 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3531 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3532 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | | |
3533 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3534 | } |
3535 | ||
a750fc0b | 3536 | static void init_proc_403GCX (CPUPPCState *env) |
3fc6c082 | 3537 | { |
a750fc0b JM |
3538 | gen_spr_40x(env); |
3539 | gen_spr_401_403(env); | |
3540 | gen_spr_403(env); | |
3541 | gen_spr_403_real(env); | |
3542 | gen_spr_403_mmu(env); | |
3543 | /* Bus access control */ | |
5cbdb3a3 | 3544 | /* not emulated, as QEMU never does speculative access */ |
a750fc0b JM |
3545 | spr_register(env, SPR_40x_SGR, "SGR", |
3546 | SPR_NOACCESS, SPR_NOACCESS, | |
3547 | &spr_read_generic, &spr_write_generic, | |
3548 | 0xFFFFFFFF); | |
5cbdb3a3 | 3549 | /* not emulated, as QEMU do not emulate caches */ |
a750fc0b JM |
3550 | spr_register(env, SPR_40x_DCWR, "DCWR", |
3551 | SPR_NOACCESS, SPR_NOACCESS, | |
3552 | &spr_read_generic, &spr_write_generic, | |
3553 | 0x00000000); | |
3554 | /* Memory management */ | |
f2e63a42 | 3555 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3556 | env->nb_tlb = 64; |
3557 | env->nb_ways = 1; | |
3558 | env->id_tlbs = 0; | |
1c53accc | 3559 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3560 | #endif |
80d11f44 JM |
3561 | init_excp_4xx_softmmu(env); |
3562 | env->dcache_line_size = 32; | |
3563 | env->icache_line_size = 32; | |
3564 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 3565 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3566 | |
3567 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3568 | SET_WDT_PERIOD(16, 20, 24, 28); | |
80d11f44 JM |
3569 | } |
3570 | ||
7856e3a4 AF |
3571 | POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) |
3572 | { | |
ca5dff0a | 3573 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3574 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3575 | ||
ca5dff0a | 3576 | dc->desc = "PowerPC 403 GCX"; |
7856e3a4 AF |
3577 | pcc->init_proc = init_proc_403GCX; |
3578 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3579 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3580 | PPC_DCR | PPC_WRTEE | | |
3581 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3582 | PPC_CACHE_DCBZ | | |
3583 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3584 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3585 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
9df5a466 TM |
3586 | pcc->msr_mask = (1ull << MSR_POW) | |
3587 | (1ull << MSR_CE) | | |
3588 | (1ull << MSR_ILE) | | |
3589 | (1ull << MSR_EE) | | |
3590 | (1ull << MSR_PR) | | |
3591 | (1ull << MSR_ME) | | |
3592 | (1ull << MSR_PE) | | |
3593 | (1ull << MSR_PX) | | |
3594 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
3595 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; |
3596 | pcc->excp_model = POWERPC_EXCP_40x; | |
3597 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3598 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3599 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | | |
3600 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3601 | } |
3602 | ||
80d11f44 JM |
3603 | static void init_proc_405 (CPUPPCState *env) |
3604 | { | |
3605 | /* Time base */ | |
3606 | gen_tbl(env); | |
3607 | gen_spr_40x(env); | |
3608 | gen_spr_405(env); | |
3609 | /* Bus access control */ | |
5cbdb3a3 | 3610 | /* not emulated, as QEMU never does speculative access */ |
80d11f44 JM |
3611 | spr_register(env, SPR_40x_SGR, "SGR", |
3612 | SPR_NOACCESS, SPR_NOACCESS, | |
3613 | &spr_read_generic, &spr_write_generic, | |
3614 | 0xFFFFFFFF); | |
5cbdb3a3 | 3615 | /* not emulated, as QEMU do not emulate caches */ |
80d11f44 JM |
3616 | spr_register(env, SPR_40x_DCWR, "DCWR", |
3617 | SPR_NOACCESS, SPR_NOACCESS, | |
3618 | &spr_read_generic, &spr_write_generic, | |
3619 | 0x00000000); | |
3620 | /* Memory management */ | |
3621 | #if !defined(CONFIG_USER_ONLY) | |
3622 | env->nb_tlb = 64; | |
3623 | env->nb_ways = 1; | |
3624 | env->id_tlbs = 0; | |
1c53accc | 3625 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3626 | #endif |
3627 | init_excp_4xx_softmmu(env); | |
3628 | env->dcache_line_size = 32; | |
3629 | env->icache_line_size = 32; | |
3630 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 3631 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3632 | |
3633 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3634 | SET_WDT_PERIOD(16, 20, 24, 28); | |
80d11f44 JM |
3635 | } |
3636 | ||
7856e3a4 AF |
3637 | POWERPC_FAMILY(405)(ObjectClass *oc, void *data) |
3638 | { | |
ca5dff0a | 3639 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3640 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3641 | ||
ca5dff0a | 3642 | dc->desc = "PowerPC 405"; |
7856e3a4 AF |
3643 | pcc->init_proc = init_proc_405; |
3644 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3645 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
3646 | PPC_DCR | PPC_WRTEE | | |
3647 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3648 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3649 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3650 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3651 | PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; | |
9df5a466 TM |
3652 | pcc->msr_mask = (1ull << MSR_POW) | |
3653 | (1ull << MSR_CE) | | |
3654 | (1ull << MSR_EE) | | |
3655 | (1ull << MSR_PR) | | |
3656 | (1ull << MSR_FP) | | |
3657 | (1ull << MSR_DWE) | | |
3658 | (1ull << MSR_DE) | | |
3659 | (1ull << MSR_IR) | | |
3660 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
3661 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx; |
3662 | pcc->excp_model = POWERPC_EXCP_40x; | |
3663 | pcc->bus_model = PPC_FLAGS_INPUT_405; | |
3664 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3665 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3666 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3667 | } |
3668 | ||
80d11f44 JM |
3669 | static void init_proc_440EP (CPUPPCState *env) |
3670 | { | |
3671 | /* Time base */ | |
3672 | gen_tbl(env); | |
3673 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3674 | gen_spr_440(env); | |
3675 | gen_spr_usprgh(env); | |
3676 | /* Processor identification */ | |
3677 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3678 | SPR_NOACCESS, SPR_NOACCESS, | |
3679 | &spr_read_generic, &spr_write_pir, | |
3680 | 0x00000000); | |
3681 | /* XXX : not implemented */ | |
3682 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3683 | SPR_NOACCESS, SPR_NOACCESS, | |
3684 | &spr_read_generic, &spr_write_generic, | |
3685 | 0x00000000); | |
3686 | /* XXX : not implemented */ | |
3687 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3688 | SPR_NOACCESS, SPR_NOACCESS, | |
3689 | &spr_read_generic, &spr_write_generic, | |
3690 | 0x00000000); | |
3691 | /* XXX : not implemented */ | |
3692 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3693 | SPR_NOACCESS, SPR_NOACCESS, | |
3694 | &spr_read_generic, &spr_write_generic, | |
3695 | 0x00000000); | |
3696 | /* XXX : not implemented */ | |
3697 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3698 | SPR_NOACCESS, SPR_NOACCESS, | |
3699 | &spr_read_generic, &spr_write_generic, | |
3700 | 0x00000000); | |
3701 | /* XXX : not implemented */ | |
3702 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3703 | SPR_NOACCESS, SPR_NOACCESS, | |
3704 | &spr_read_generic, &spr_write_generic, | |
3705 | 0x00000000); | |
3706 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3707 | SPR_NOACCESS, SPR_NOACCESS, | |
3708 | &spr_read_generic, &spr_write_generic, | |
3709 | 0x00000000); | |
3710 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3711 | SPR_NOACCESS, SPR_NOACCESS, | |
3712 | &spr_read_generic, &spr_write_generic, | |
3713 | 0x00000000); | |
3714 | /* XXX : not implemented */ | |
3715 | spr_register(env, SPR_440_CCR1, "CCR1", | |
3716 | SPR_NOACCESS, SPR_NOACCESS, | |
3717 | &spr_read_generic, &spr_write_generic, | |
3718 | 0x00000000); | |
3719 | /* Memory management */ | |
3720 | #if !defined(CONFIG_USER_ONLY) | |
3721 | env->nb_tlb = 64; | |
3722 | env->nb_ways = 1; | |
3723 | env->id_tlbs = 0; | |
1c53accc | 3724 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3725 | #endif |
3726 | init_excp_BookE(env); | |
3727 | env->dcache_line_size = 32; | |
3728 | env->icache_line_size = 32; | |
aa5a9e24 | 3729 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
3730 | |
3731 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3732 | SET_WDT_PERIOD(20, 24, 28, 32); | |
80d11f44 JM |
3733 | } |
3734 | ||
7856e3a4 AF |
3735 | POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) |
3736 | { | |
ca5dff0a | 3737 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3738 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3739 | ||
ca5dff0a | 3740 | dc->desc = "PowerPC 440 EP"; |
7856e3a4 AF |
3741 | pcc->init_proc = init_proc_440EP; |
3742 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3743 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3744 | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | | |
3745 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
3746 | PPC_FLOAT_STFIWX | | |
3747 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | | |
3748 | PPC_CACHE | PPC_CACHE_ICBI | | |
3749 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3750 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
3751 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3752 | PPC_440_SPEC; | |
9df5a466 TM |
3753 | pcc->msr_mask = (1ull << MSR_POW) | |
3754 | (1ull << MSR_CE) | | |
3755 | (1ull << MSR_EE) | | |
3756 | (1ull << MSR_PR) | | |
3757 | (1ull << MSR_FP) | | |
3758 | (1ull << MSR_ME) | | |
3759 | (1ull << MSR_FE0) | | |
3760 | (1ull << MSR_DWE) | | |
3761 | (1ull << MSR_DE) | | |
3762 | (1ull << MSR_FE1) | | |
3763 | (1ull << MSR_IR) | | |
3764 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
3765 | pcc->mmu_model = POWERPC_MMU_BOOKE; |
3766 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3767 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3768 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3769 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3770 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3771 | } |
3772 | ||
80d11f44 JM |
3773 | static void init_proc_440GP (CPUPPCState *env) |
3774 | { | |
3775 | /* Time base */ | |
3776 | gen_tbl(env); | |
3777 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3778 | gen_spr_440(env); | |
3779 | gen_spr_usprgh(env); | |
3780 | /* Processor identification */ | |
3781 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3782 | SPR_NOACCESS, SPR_NOACCESS, | |
3783 | &spr_read_generic, &spr_write_pir, | |
3784 | 0x00000000); | |
3785 | /* XXX : not implemented */ | |
3786 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3787 | SPR_NOACCESS, SPR_NOACCESS, | |
3788 | &spr_read_generic, &spr_write_generic, | |
3789 | 0x00000000); | |
3790 | /* XXX : not implemented */ | |
3791 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3792 | SPR_NOACCESS, SPR_NOACCESS, | |
3793 | &spr_read_generic, &spr_write_generic, | |
3794 | 0x00000000); | |
3795 | /* XXX : not implemented */ | |
3796 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3797 | SPR_NOACCESS, SPR_NOACCESS, | |
3798 | &spr_read_generic, &spr_write_generic, | |
3799 | 0x00000000); | |
3800 | /* XXX : not implemented */ | |
3801 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3802 | SPR_NOACCESS, SPR_NOACCESS, | |
3803 | &spr_read_generic, &spr_write_generic, | |
3804 | 0x00000000); | |
3805 | /* Memory management */ | |
3806 | #if !defined(CONFIG_USER_ONLY) | |
3807 | env->nb_tlb = 64; | |
3808 | env->nb_ways = 1; | |
3809 | env->id_tlbs = 0; | |
1c53accc | 3810 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3811 | #endif |
3812 | init_excp_BookE(env); | |
3813 | env->dcache_line_size = 32; | |
3814 | env->icache_line_size = 32; | |
3815 | /* XXX: TODO: allocate internal IRQ controller */ | |
ddd1055b FC |
3816 | |
3817 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3818 | SET_WDT_PERIOD(20, 24, 28, 32); | |
80d11f44 JM |
3819 | } |
3820 | ||
7856e3a4 AF |
3821 | POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) |
3822 | { | |
ca5dff0a | 3823 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3824 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3825 | ||
ca5dff0a | 3826 | dc->desc = "PowerPC 440 GP"; |
7856e3a4 AF |
3827 | pcc->init_proc = init_proc_440GP; |
3828 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3829 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3830 | PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | | |
3831 | PPC_CACHE | PPC_CACHE_ICBI | | |
3832 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3833 | PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | | |
3834 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3835 | PPC_440_SPEC; | |
9df5a466 TM |
3836 | pcc->msr_mask = (1ull << MSR_POW) | |
3837 | (1ull << MSR_CE) | | |
3838 | (1ull << MSR_EE) | | |
3839 | (1ull << MSR_PR) | | |
3840 | (1ull << MSR_FP) | | |
3841 | (1ull << MSR_ME) | | |
3842 | (1ull << MSR_FE0) | | |
3843 | (1ull << MSR_DWE) | | |
3844 | (1ull << MSR_DE) | | |
3845 | (1ull << MSR_FE1) | | |
3846 | (1ull << MSR_IR) | | |
3847 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
3848 | pcc->mmu_model = POWERPC_MMU_BOOKE; |
3849 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3850 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3851 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3852 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3853 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3854 | } |
3855 | ||
80d11f44 JM |
3856 | static void init_proc_440x4 (CPUPPCState *env) |
3857 | { | |
3858 | /* Time base */ | |
3859 | gen_tbl(env); | |
3860 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3861 | gen_spr_440(env); | |
3862 | gen_spr_usprgh(env); | |
3863 | /* Processor identification */ | |
3864 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3865 | SPR_NOACCESS, SPR_NOACCESS, | |
3866 | &spr_read_generic, &spr_write_pir, | |
3867 | 0x00000000); | |
3868 | /* XXX : not implemented */ | |
3869 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3870 | SPR_NOACCESS, SPR_NOACCESS, | |
3871 | &spr_read_generic, &spr_write_generic, | |
3872 | 0x00000000); | |
3873 | /* XXX : not implemented */ | |
3874 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3875 | SPR_NOACCESS, SPR_NOACCESS, | |
3876 | &spr_read_generic, &spr_write_generic, | |
3877 | 0x00000000); | |
3878 | /* XXX : not implemented */ | |
3879 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3880 | SPR_NOACCESS, SPR_NOACCESS, | |
3881 | &spr_read_generic, &spr_write_generic, | |
3882 | 0x00000000); | |
3883 | /* XXX : not implemented */ | |
3884 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3885 | SPR_NOACCESS, SPR_NOACCESS, | |
3886 | &spr_read_generic, &spr_write_generic, | |
3887 | 0x00000000); | |
3888 | /* Memory management */ | |
3889 | #if !defined(CONFIG_USER_ONLY) | |
3890 | env->nb_tlb = 64; | |
3891 | env->nb_ways = 1; | |
3892 | env->id_tlbs = 0; | |
1c53accc | 3893 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3894 | #endif |
3895 | init_excp_BookE(env); | |
d63001d1 JM |
3896 | env->dcache_line_size = 32; |
3897 | env->icache_line_size = 32; | |
80d11f44 | 3898 | /* XXX: TODO: allocate internal IRQ controller */ |
ddd1055b FC |
3899 | |
3900 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3901 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
3902 | } |
3903 | ||
7856e3a4 AF |
3904 | POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) |
3905 | { | |
ca5dff0a | 3906 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3907 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3908 | ||
ca5dff0a | 3909 | dc->desc = "PowerPC 440x4"; |
7856e3a4 AF |
3910 | pcc->init_proc = init_proc_440x4; |
3911 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3912 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3913 | PPC_DCR | PPC_WRTEE | | |
3914 | PPC_CACHE | PPC_CACHE_ICBI | | |
3915 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3916 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
3917 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3918 | PPC_440_SPEC; | |
9df5a466 TM |
3919 | pcc->msr_mask = (1ull << MSR_POW) | |
3920 | (1ull << MSR_CE) | | |
3921 | (1ull << MSR_EE) | | |
3922 | (1ull << MSR_PR) | | |
3923 | (1ull << MSR_FP) | | |
3924 | (1ull << MSR_ME) | | |
3925 | (1ull << MSR_FE0) | | |
3926 | (1ull << MSR_DWE) | | |
3927 | (1ull << MSR_DE) | | |
3928 | (1ull << MSR_FE1) | | |
3929 | (1ull << MSR_IR) | | |
3930 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
3931 | pcc->mmu_model = POWERPC_MMU_BOOKE; |
3932 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3933 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3934 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3935 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3936 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3937 | } |
3938 | ||
80d11f44 | 3939 | static void init_proc_440x5 (CPUPPCState *env) |
3fc6c082 | 3940 | { |
a750fc0b JM |
3941 | /* Time base */ |
3942 | gen_tbl(env); | |
80d11f44 JM |
3943 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
3944 | gen_spr_440(env); | |
3945 | gen_spr_usprgh(env); | |
3946 | /* Processor identification */ | |
3947 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3948 | SPR_NOACCESS, SPR_NOACCESS, | |
3949 | &spr_read_generic, &spr_write_pir, | |
3950 | 0x00000000); | |
3951 | /* XXX : not implemented */ | |
3952 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
a750fc0b JM |
3953 | SPR_NOACCESS, SPR_NOACCESS, |
3954 | &spr_read_generic, &spr_write_generic, | |
80d11f44 JM |
3955 | 0x00000000); |
3956 | /* XXX : not implemented */ | |
3957 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3958 | SPR_NOACCESS, SPR_NOACCESS, | |
3959 | &spr_read_generic, &spr_write_generic, | |
3960 | 0x00000000); | |
3961 | /* XXX : not implemented */ | |
3962 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3963 | SPR_NOACCESS, SPR_NOACCESS, | |
3964 | &spr_read_generic, &spr_write_generic, | |
3965 | 0x00000000); | |
3966 | /* XXX : not implemented */ | |
3967 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3968 | SPR_NOACCESS, SPR_NOACCESS, | |
3969 | &spr_read_generic, &spr_write_generic, | |
3970 | 0x00000000); | |
3971 | /* XXX : not implemented */ | |
3972 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3973 | SPR_NOACCESS, SPR_NOACCESS, | |
3974 | &spr_read_generic, &spr_write_generic, | |
3975 | 0x00000000); | |
3976 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3977 | SPR_NOACCESS, SPR_NOACCESS, | |
3978 | &spr_read_generic, &spr_write_generic, | |
3979 | 0x00000000); | |
3980 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3981 | SPR_NOACCESS, SPR_NOACCESS, | |
3982 | &spr_read_generic, &spr_write_generic, | |
3983 | 0x00000000); | |
3984 | /* XXX : not implemented */ | |
3985 | spr_register(env, SPR_440_CCR1, "CCR1", | |
a750fc0b JM |
3986 | SPR_NOACCESS, SPR_NOACCESS, |
3987 | &spr_read_generic, &spr_write_generic, | |
3988 | 0x00000000); | |
3989 | /* Memory management */ | |
f2e63a42 | 3990 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3991 | env->nb_tlb = 64; |
3992 | env->nb_ways = 1; | |
3993 | env->id_tlbs = 0; | |
1c53accc | 3994 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3995 | #endif |
80d11f44 | 3996 | init_excp_BookE(env); |
d63001d1 JM |
3997 | env->dcache_line_size = 32; |
3998 | env->icache_line_size = 32; | |
aa5a9e24 | 3999 | ppc40x_irq_init(ppc_env_get_cpu(env)); |
ddd1055b FC |
4000 | |
4001 | SET_FIT_PERIOD(12, 16, 20, 24); | |
4002 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
4003 | } |
4004 | ||
7856e3a4 AF |
4005 | POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) |
4006 | { | |
ca5dff0a | 4007 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4008 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4009 | ||
ca5dff0a | 4010 | dc->desc = "PowerPC 440x5"; |
7856e3a4 AF |
4011 | pcc->init_proc = init_proc_440x5; |
4012 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
4013 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
4014 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | | |
4015 | PPC_CACHE | PPC_CACHE_ICBI | | |
4016 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4017 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
4018 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
4019 | PPC_440_SPEC; | |
9df5a466 TM |
4020 | pcc->msr_mask = (1ull << MSR_POW) | |
4021 | (1ull << MSR_CE) | | |
4022 | (1ull << MSR_EE) | | |
4023 | (1ull << MSR_PR) | | |
4024 | (1ull << MSR_FP) | | |
4025 | (1ull << MSR_ME) | | |
4026 | (1ull << MSR_FE0) | | |
4027 | (1ull << MSR_DWE) | | |
4028 | (1ull << MSR_DE) | | |
4029 | (1ull << MSR_FE1) | | |
4030 | (1ull << MSR_IR) | | |
4031 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
4032 | pcc->mmu_model = POWERPC_MMU_BOOKE; |
4033 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4034 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4035 | pcc->bfd_mach = bfd_mach_ppc_403; | |
4036 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
4037 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4038 | } |
4039 | ||
b8c867ed PM |
4040 | POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) |
4041 | { | |
4042 | DeviceClass *dc = DEVICE_CLASS(oc); | |
4043 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
4044 | ||
4045 | dc->desc = "PowerPC 440x5 with double precision FPU"; | |
4046 | pcc->init_proc = init_proc_440x5; | |
4047 | pcc->check_pow = check_pow_nocheck; | |
4048 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | | |
4049 | PPC_FLOAT | PPC_FLOAT_FSQRT | | |
4050 | PPC_FLOAT_STFIWX | | |
4051 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | | |
4052 | PPC_CACHE | PPC_CACHE_ICBI | | |
4053 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4054 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
4055 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
4056 | PPC_440_SPEC; | |
4057 | pcc->insns_flags2 = PPC2_FP_CVT_S64; | |
4058 | pcc->msr_mask = (1ull << MSR_POW) | | |
4059 | (1ull << MSR_CE) | | |
4060 | (1ull << MSR_EE) | | |
4061 | (1ull << MSR_PR) | | |
4062 | (1ull << MSR_FP) | | |
4063 | (1ull << MSR_ME) | | |
4064 | (1ull << MSR_FE0) | | |
4065 | (1ull << MSR_DWE) | | |
4066 | (1ull << MSR_DE) | | |
4067 | (1ull << MSR_FE1) | | |
4068 | (1ull << MSR_IR) | | |
4069 | (1ull << MSR_DR); | |
4070 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
4071 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4072 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4073 | pcc->bfd_mach = bfd_mach_ppc_403; | |
4074 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
4075 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
4076 | } | |
4077 | ||
80d11f44 | 4078 | static void init_proc_460 (CPUPPCState *env) |
3fc6c082 | 4079 | { |
a750fc0b JM |
4080 | /* Time base */ |
4081 | gen_tbl(env); | |
80d11f44 | 4082 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
a750fc0b | 4083 | gen_spr_440(env); |
80d11f44 JM |
4084 | gen_spr_usprgh(env); |
4085 | /* Processor identification */ | |
4086 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
4087 | SPR_NOACCESS, SPR_NOACCESS, | |
4088 | &spr_read_generic, &spr_write_pir, | |
4089 | 0x00000000); | |
4090 | /* XXX : not implemented */ | |
4091 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
4092 | SPR_NOACCESS, SPR_NOACCESS, | |
4093 | &spr_read_generic, &spr_write_generic, | |
4094 | 0x00000000); | |
4095 | /* XXX : not implemented */ | |
4096 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
4097 | SPR_NOACCESS, SPR_NOACCESS, | |
4098 | &spr_read_generic, &spr_write_generic, | |
4099 | 0x00000000); | |
4100 | /* XXX : not implemented */ | |
4101 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
4102 | SPR_NOACCESS, SPR_NOACCESS, | |
4103 | &spr_read_generic, &spr_write_generic, | |
4104 | 0x00000000); | |
4105 | /* XXX : not implemented */ | |
4106 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
4107 | SPR_NOACCESS, SPR_NOACCESS, | |
4108 | &spr_read_generic, &spr_write_generic, | |
4109 | 0x00000000); | |
578bb252 | 4110 | /* XXX : not implemented */ |
a750fc0b JM |
4111 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
4112 | SPR_NOACCESS, SPR_NOACCESS, | |
4113 | &spr_read_generic, &spr_write_generic, | |
4114 | 0x00000000); | |
4115 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
4116 | SPR_NOACCESS, SPR_NOACCESS, | |
4117 | &spr_read_generic, &spr_write_generic, | |
4118 | 0x00000000); | |
4119 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
4120 | SPR_NOACCESS, SPR_NOACCESS, | |
4121 | &spr_read_generic, &spr_write_generic, | |
4122 | 0x00000000); | |
578bb252 | 4123 | /* XXX : not implemented */ |
a750fc0b JM |
4124 | spr_register(env, SPR_440_CCR1, "CCR1", |
4125 | SPR_NOACCESS, SPR_NOACCESS, | |
4126 | &spr_read_generic, &spr_write_generic, | |
4127 | 0x00000000); | |
80d11f44 JM |
4128 | /* XXX : not implemented */ |
4129 | spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", | |
4130 | &spr_read_generic, &spr_write_generic, | |
4131 | &spr_read_generic, &spr_write_generic, | |
4132 | 0x00000000); | |
a750fc0b | 4133 | /* Memory management */ |
f2e63a42 | 4134 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
4135 | env->nb_tlb = 64; |
4136 | env->nb_ways = 1; | |
4137 | env->id_tlbs = 0; | |
1c53accc | 4138 | env->tlb_type = TLB_EMB; |
f2e63a42 | 4139 | #endif |
e1833e1f | 4140 | init_excp_BookE(env); |
d63001d1 JM |
4141 | env->dcache_line_size = 32; |
4142 | env->icache_line_size = 32; | |
a750fc0b | 4143 | /* XXX: TODO: allocate internal IRQ controller */ |
ddd1055b FC |
4144 | |
4145 | SET_FIT_PERIOD(12, 16, 20, 24); | |
4146 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
4147 | } |
4148 | ||
7856e3a4 AF |
4149 | POWERPC_FAMILY(460)(ObjectClass *oc, void *data) |
4150 | { | |
ca5dff0a | 4151 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4152 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4153 | ||
ca5dff0a | 4154 | dc->desc = "PowerPC 460 (guessed)"; |
7856e3a4 AF |
4155 | pcc->init_proc = init_proc_460; |
4156 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
4157 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
4158 | PPC_DCR | PPC_DCRX | PPC_DCRUX | | |
4159 | PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | | |
4160 | PPC_CACHE | PPC_CACHE_ICBI | | |
4161 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4162 | PPC_MEM_TLBSYNC | PPC_TLBIVA | | |
4163 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
4164 | PPC_440_SPEC; | |
9df5a466 TM |
4165 | pcc->msr_mask = (1ull << MSR_POW) | |
4166 | (1ull << MSR_CE) | | |
4167 | (1ull << MSR_EE) | | |
4168 | (1ull << MSR_PR) | | |
4169 | (1ull << MSR_FP) | | |
4170 | (1ull << MSR_ME) | | |
4171 | (1ull << MSR_FE0) | | |
4172 | (1ull << MSR_DWE) | | |
4173 | (1ull << MSR_DE) | | |
4174 | (1ull << MSR_FE1) | | |
4175 | (1ull << MSR_IR) | | |
4176 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
4177 | pcc->mmu_model = POWERPC_MMU_BOOKE; |
4178 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4179 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4180 | pcc->bfd_mach = bfd_mach_ppc_403; | |
4181 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
4182 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4183 | } |
4184 | ||
80d11f44 | 4185 | static void init_proc_460F (CPUPPCState *env) |
3fc6c082 | 4186 | { |
a750fc0b JM |
4187 | /* Time base */ |
4188 | gen_tbl(env); | |
80d11f44 | 4189 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
a750fc0b | 4190 | gen_spr_440(env); |
80d11f44 JM |
4191 | gen_spr_usprgh(env); |
4192 | /* Processor identification */ | |
4193 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
4194 | SPR_NOACCESS, SPR_NOACCESS, | |
4195 | &spr_read_generic, &spr_write_pir, | |
4196 | 0x00000000); | |
4197 | /* XXX : not implemented */ | |
4198 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
4199 | SPR_NOACCESS, SPR_NOACCESS, | |
4200 | &spr_read_generic, &spr_write_generic, | |
4201 | 0x00000000); | |
4202 | /* XXX : not implemented */ | |
4203 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
4204 | SPR_NOACCESS, SPR_NOACCESS, | |
4205 | &spr_read_generic, &spr_write_generic, | |
4206 | 0x00000000); | |
4207 | /* XXX : not implemented */ | |
4208 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
4209 | SPR_NOACCESS, SPR_NOACCESS, | |
4210 | &spr_read_generic, &spr_write_generic, | |
4211 | 0x00000000); | |
4212 | /* XXX : not implemented */ | |
4213 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
4214 | SPR_NOACCESS, SPR_NOACCESS, | |
4215 | &spr_read_generic, &spr_write_generic, | |
4216 | 0x00000000); | |
4217 | /* XXX : not implemented */ | |
4218 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
4219 | SPR_NOACCESS, SPR_NOACCESS, | |
4220 | &spr_read_generic, &spr_write_generic, | |
4221 | 0x00000000); | |
4222 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
4223 | SPR_NOACCESS, SPR_NOACCESS, | |
4224 | &spr_read_generic, &spr_write_generic, | |
4225 | 0x00000000); | |
4226 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
4227 | SPR_NOACCESS, SPR_NOACCESS, | |
4228 | &spr_read_generic, &spr_write_generic, | |
4229 | 0x00000000); | |
4230 | /* XXX : not implemented */ | |
4231 | spr_register(env, SPR_440_CCR1, "CCR1", | |
4232 | SPR_NOACCESS, SPR_NOACCESS, | |
4233 | &spr_read_generic, &spr_write_generic, | |
4234 | 0x00000000); | |
4235 | /* XXX : not implemented */ | |
4236 | spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", | |
4237 | &spr_read_generic, &spr_write_generic, | |
4238 | &spr_read_generic, &spr_write_generic, | |
4239 | 0x00000000); | |
a750fc0b | 4240 | /* Memory management */ |
f2e63a42 | 4241 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
4242 | env->nb_tlb = 64; |
4243 | env->nb_ways = 1; | |
4244 | env->id_tlbs = 0; | |
1c53accc | 4245 | env->tlb_type = TLB_EMB; |
f2e63a42 | 4246 | #endif |
e1833e1f | 4247 | init_excp_BookE(env); |
d63001d1 JM |
4248 | env->dcache_line_size = 32; |
4249 | env->icache_line_size = 32; | |
a750fc0b | 4250 | /* XXX: TODO: allocate internal IRQ controller */ |
ddd1055b FC |
4251 | |
4252 | SET_FIT_PERIOD(12, 16, 20, 24); | |
4253 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
4254 | } |
4255 | ||
7856e3a4 AF |
4256 | POWERPC_FAMILY(460F)(ObjectClass *oc, void *data) |
4257 | { | |
ca5dff0a | 4258 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4259 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4260 | ||
ca5dff0a | 4261 | dc->desc = "PowerPC 460F (guessed)"; |
7856e3a4 AF |
4262 | pcc->init_proc = init_proc_460F; |
4263 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
4264 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
4265 | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | | |
4266 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
4267 | PPC_FLOAT_STFIWX | PPC_MFTB | | |
4268 | PPC_DCR | PPC_DCRX | PPC_DCRUX | | |
4269 | PPC_WRTEE | PPC_MFAPIDI | | |
4270 | PPC_CACHE | PPC_CACHE_ICBI | | |
4271 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4272 | PPC_MEM_TLBSYNC | PPC_TLBIVA | | |
4273 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
4274 | PPC_440_SPEC; | |
9df5a466 TM |
4275 | pcc->msr_mask = (1ull << MSR_POW) | |
4276 | (1ull << MSR_CE) | | |
4277 | (1ull << MSR_EE) | | |
4278 | (1ull << MSR_PR) | | |
4279 | (1ull << MSR_FP) | | |
4280 | (1ull << MSR_ME) | | |
4281 | (1ull << MSR_FE0) | | |
4282 | (1ull << MSR_DWE) | | |
4283 | (1ull << MSR_DE) | | |
4284 | (1ull << MSR_FE1) | | |
4285 | (1ull << MSR_IR) | | |
4286 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
4287 | pcc->mmu_model = POWERPC_MMU_BOOKE; |
4288 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4289 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4290 | pcc->bfd_mach = bfd_mach_ppc_403; | |
4291 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
4292 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4293 | } |
4294 | ||
80d11f44 JM |
4295 | static void init_proc_MPC5xx (CPUPPCState *env) |
4296 | { | |
4297 | /* Time base */ | |
4298 | gen_tbl(env); | |
4299 | gen_spr_5xx_8xx(env); | |
4300 | gen_spr_5xx(env); | |
4301 | init_excp_MPC5xx(env); | |
4302 | env->dcache_line_size = 32; | |
4303 | env->icache_line_size = 32; | |
4304 | /* XXX: TODO: allocate internal IRQ controller */ | |
4305 | } | |
4306 | ||
7856e3a4 AF |
4307 | POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) |
4308 | { | |
ca5dff0a | 4309 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4310 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4311 | ||
ca5dff0a | 4312 | dc->desc = "Freescale 5xx cores (aka RCPU)"; |
7856e3a4 AF |
4313 | pcc->init_proc = init_proc_MPC5xx; |
4314 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4315 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
4316 | PPC_MEM_EIEIO | PPC_MEM_SYNC | | |
4317 | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | | |
4318 | PPC_MFTB; | |
9df5a466 TM |
4319 | pcc->msr_mask = (1ull << MSR_ILE) | |
4320 | (1ull << MSR_EE) | | |
4321 | (1ull << MSR_PR) | | |
4322 | (1ull << MSR_FP) | | |
4323 | (1ull << MSR_ME) | | |
4324 | (1ull << MSR_FE0) | | |
4325 | (1ull << MSR_SE) | | |
4326 | (1ull << MSR_DE) | | |
4327 | (1ull << MSR_FE1) | | |
4328 | (1ull << MSR_EP) | | |
4329 | (1ull << MSR_RI) | | |
4330 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
4331 | pcc->mmu_model = POWERPC_MMU_REAL; |
4332 | pcc->excp_model = POWERPC_EXCP_603; | |
4333 | pcc->bus_model = PPC_FLAGS_INPUT_RCPU; | |
4334 | pcc->bfd_mach = bfd_mach_ppc_505; | |
4335 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
4336 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4337 | } |
4338 | ||
80d11f44 JM |
4339 | static void init_proc_MPC8xx (CPUPPCState *env) |
4340 | { | |
4341 | /* Time base */ | |
4342 | gen_tbl(env); | |
4343 | gen_spr_5xx_8xx(env); | |
4344 | gen_spr_8xx(env); | |
4345 | init_excp_MPC8xx(env); | |
4346 | env->dcache_line_size = 32; | |
4347 | env->icache_line_size = 32; | |
4348 | /* XXX: TODO: allocate internal IRQ controller */ | |
4349 | } | |
4350 | ||
7856e3a4 AF |
4351 | POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) |
4352 | { | |
ca5dff0a | 4353 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4354 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4355 | ||
ca5dff0a | 4356 | dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; |
7856e3a4 AF |
4357 | pcc->init_proc = init_proc_MPC8xx; |
4358 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4359 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
4360 | PPC_MEM_EIEIO | PPC_MEM_SYNC | | |
4361 | PPC_CACHE_ICBI | PPC_MFTB; | |
9df5a466 TM |
4362 | pcc->msr_mask = (1ull << MSR_ILE) | |
4363 | (1ull << MSR_EE) | | |
4364 | (1ull << MSR_PR) | | |
4365 | (1ull << MSR_FP) | | |
4366 | (1ull << MSR_ME) | | |
4367 | (1ull << MSR_SE) | | |
4368 | (1ull << MSR_DE) | | |
4369 | (1ull << MSR_EP) | | |
4370 | (1ull << MSR_IR) | | |
4371 | (1ull << MSR_DR) | | |
4372 | (1ull << MSR_RI) | | |
4373 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
4374 | pcc->mmu_model = POWERPC_MMU_MPC8xx; |
4375 | pcc->excp_model = POWERPC_EXCP_603; | |
4376 | pcc->bus_model = PPC_FLAGS_INPUT_RCPU; | |
4377 | pcc->bfd_mach = bfd_mach_ppc_860; | |
4378 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
4379 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4380 | } |
4381 | ||
80d11f44 | 4382 | /* Freescale 82xx cores (aka PowerQUICC-II) */ |
ca5dff0a | 4383 | |
80d11f44 | 4384 | static void init_proc_G2 (CPUPPCState *env) |
3fc6c082 | 4385 | { |
80d11f44 JM |
4386 | gen_spr_ne_601(env); |
4387 | gen_spr_G2_755(env); | |
4388 | gen_spr_G2(env); | |
a750fc0b JM |
4389 | /* Time base */ |
4390 | gen_tbl(env); | |
bd928eba JM |
4391 | /* External access control */ |
4392 | /* XXX : not implemented */ | |
4393 | spr_register(env, SPR_EAR, "EAR", | |
4394 | SPR_NOACCESS, SPR_NOACCESS, | |
4395 | &spr_read_generic, &spr_write_generic, | |
4396 | 0x00000000); | |
80d11f44 JM |
4397 | /* Hardware implementation register */ |
4398 | /* XXX : not implemented */ | |
4399 | spr_register(env, SPR_HID0, "HID0", | |
4400 | SPR_NOACCESS, SPR_NOACCESS, | |
4401 | &spr_read_generic, &spr_write_generic, | |
4402 | 0x00000000); | |
4403 | /* XXX : not implemented */ | |
4404 | spr_register(env, SPR_HID1, "HID1", | |
4405 | SPR_NOACCESS, SPR_NOACCESS, | |
4406 | &spr_read_generic, &spr_write_generic, | |
4407 | 0x00000000); | |
4408 | /* XXX : not implemented */ | |
4409 | spr_register(env, SPR_HID2, "HID2", | |
4410 | SPR_NOACCESS, SPR_NOACCESS, | |
4411 | &spr_read_generic, &spr_write_generic, | |
4412 | 0x00000000); | |
a750fc0b | 4413 | /* Memory management */ |
80d11f44 JM |
4414 | gen_low_BATs(env); |
4415 | gen_high_BATs(env); | |
4416 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
4417 | init_excp_G2(env); | |
d63001d1 JM |
4418 | env->dcache_line_size = 32; |
4419 | env->icache_line_size = 32; | |
80d11f44 | 4420 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 4421 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
3fc6c082 | 4422 | } |
a750fc0b | 4423 | |
7856e3a4 AF |
4424 | POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) |
4425 | { | |
ca5dff0a | 4426 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4427 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4428 | ||
ca5dff0a | 4429 | dc->desc = "PowerPC G2"; |
7856e3a4 AF |
4430 | pcc->init_proc = init_proc_G2; |
4431 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4432 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4433 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4434 | PPC_FLOAT_STFIWX | | |
4435 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4436 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4437 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4438 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
4439 | pcc->msr_mask = (1ull << MSR_POW) | |
4440 | (1ull << MSR_TGPR) | | |
4441 | (1ull << MSR_EE) | | |
4442 | (1ull << MSR_PR) | | |
4443 | (1ull << MSR_FP) | | |
4444 | (1ull << MSR_ME) | | |
4445 | (1ull << MSR_FE0) | | |
4446 | (1ull << MSR_SE) | | |
4447 | (1ull << MSR_DE) | | |
4448 | (1ull << MSR_FE1) | | |
4449 | (1ull << MSR_AL) | | |
4450 | (1ull << MSR_EP) | | |
4451 | (1ull << MSR_IR) | | |
4452 | (1ull << MSR_DR) | | |
4453 | (1ull << MSR_RI); | |
ba9fd9f1 AF |
4454 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
4455 | pcc->excp_model = POWERPC_EXCP_G2; | |
4456 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4457 | pcc->bfd_mach = bfd_mach_ppc_ec603e; | |
4458 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4459 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4460 | } |
4461 | ||
80d11f44 | 4462 | static void init_proc_G2LE (CPUPPCState *env) |
3fc6c082 | 4463 | { |
80d11f44 JM |
4464 | gen_spr_ne_601(env); |
4465 | gen_spr_G2_755(env); | |
4466 | gen_spr_G2(env); | |
a750fc0b JM |
4467 | /* Time base */ |
4468 | gen_tbl(env); | |
bd928eba JM |
4469 | /* External access control */ |
4470 | /* XXX : not implemented */ | |
4471 | spr_register(env, SPR_EAR, "EAR", | |
4472 | SPR_NOACCESS, SPR_NOACCESS, | |
4473 | &spr_read_generic, &spr_write_generic, | |
4474 | 0x00000000); | |
80d11f44 | 4475 | /* Hardware implementation register */ |
578bb252 | 4476 | /* XXX : not implemented */ |
80d11f44 | 4477 | spr_register(env, SPR_HID0, "HID0", |
a750fc0b JM |
4478 | SPR_NOACCESS, SPR_NOACCESS, |
4479 | &spr_read_generic, &spr_write_generic, | |
4480 | 0x00000000); | |
80d11f44 JM |
4481 | /* XXX : not implemented */ |
4482 | spr_register(env, SPR_HID1, "HID1", | |
a750fc0b JM |
4483 | SPR_NOACCESS, SPR_NOACCESS, |
4484 | &spr_read_generic, &spr_write_generic, | |
4485 | 0x00000000); | |
578bb252 | 4486 | /* XXX : not implemented */ |
80d11f44 | 4487 | spr_register(env, SPR_HID2, "HID2", |
a750fc0b JM |
4488 | SPR_NOACCESS, SPR_NOACCESS, |
4489 | &spr_read_generic, &spr_write_generic, | |
4490 | 0x00000000); | |
2bc17322 | 4491 | |
a750fc0b | 4492 | /* Memory management */ |
80d11f44 JM |
4493 | gen_low_BATs(env); |
4494 | gen_high_BATs(env); | |
4495 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
4496 | init_excp_G2(env); | |
d63001d1 JM |
4497 | env->dcache_line_size = 32; |
4498 | env->icache_line_size = 32; | |
80d11f44 | 4499 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 4500 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
3fc6c082 FB |
4501 | } |
4502 | ||
7856e3a4 AF |
4503 | POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) |
4504 | { | |
ca5dff0a | 4505 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4506 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4507 | ||
ca5dff0a | 4508 | dc->desc = "PowerPC G2LE"; |
7856e3a4 AF |
4509 | pcc->init_proc = init_proc_G2LE; |
4510 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4511 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4512 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4513 | PPC_FLOAT_STFIWX | | |
4514 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4515 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4516 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4517 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
4518 | pcc->msr_mask = (1ull << MSR_POW) | |
4519 | (1ull << MSR_TGPR) | | |
4520 | (1ull << MSR_ILE) | | |
4521 | (1ull << MSR_EE) | | |
4522 | (1ull << MSR_PR) | | |
4523 | (1ull << MSR_FP) | | |
4524 | (1ull << MSR_ME) | | |
4525 | (1ull << MSR_FE0) | | |
4526 | (1ull << MSR_SE) | | |
4527 | (1ull << MSR_DE) | | |
4528 | (1ull << MSR_FE1) | | |
4529 | (1ull << MSR_AL) | | |
4530 | (1ull << MSR_EP) | | |
4531 | (1ull << MSR_IR) | | |
4532 | (1ull << MSR_DR) | | |
4533 | (1ull << MSR_RI) | | |
4534 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
4535 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
4536 | pcc->excp_model = POWERPC_EXCP_G2; | |
4537 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4538 | pcc->bfd_mach = bfd_mach_ppc_ec603e; | |
4539 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4540 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4541 | } |
4542 | ||
80d11f44 | 4543 | static void init_proc_e200 (CPUPPCState *env) |
3fc6c082 | 4544 | { |
e1833e1f JM |
4545 | /* Time base */ |
4546 | gen_tbl(env); | |
80d11f44 | 4547 | gen_spr_BookE(env, 0x000000070000FFFFULL); |
578bb252 | 4548 | /* XXX : not implemented */ |
80d11f44 | 4549 | spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", |
d34defbc AJ |
4550 | &spr_read_spefscr, &spr_write_spefscr, |
4551 | &spr_read_spefscr, &spr_write_spefscr, | |
e1833e1f | 4552 | 0x00000000); |
80d11f44 | 4553 | /* Memory management */ |
01662f3e | 4554 | gen_spr_BookE206(env, 0x0000005D, NULL); |
80d11f44 JM |
4555 | /* XXX : not implemented */ |
4556 | spr_register(env, SPR_HID0, "HID0", | |
e1833e1f JM |
4557 | SPR_NOACCESS, SPR_NOACCESS, |
4558 | &spr_read_generic, &spr_write_generic, | |
4559 | 0x00000000); | |
80d11f44 JM |
4560 | /* XXX : not implemented */ |
4561 | spr_register(env, SPR_HID1, "HID1", | |
e1833e1f JM |
4562 | SPR_NOACCESS, SPR_NOACCESS, |
4563 | &spr_read_generic, &spr_write_generic, | |
4564 | 0x00000000); | |
578bb252 | 4565 | /* XXX : not implemented */ |
80d11f44 | 4566 | spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", |
e1833e1f JM |
4567 | SPR_NOACCESS, SPR_NOACCESS, |
4568 | &spr_read_generic, &spr_write_generic, | |
4569 | 0x00000000); | |
578bb252 | 4570 | /* XXX : not implemented */ |
80d11f44 JM |
4571 | spr_register(env, SPR_Exxx_BUCSR, "BUCSR", |
4572 | SPR_NOACCESS, SPR_NOACCESS, | |
e1833e1f | 4573 | &spr_read_generic, &spr_write_generic, |
80d11f44 JM |
4574 | 0x00000000); |
4575 | /* XXX : not implemented */ | |
4576 | spr_register(env, SPR_Exxx_CTXCR, "CTXCR", | |
4577 | SPR_NOACCESS, SPR_NOACCESS, | |
4578 | &spr_read_generic, &spr_write_generic, | |
4579 | 0x00000000); | |
4580 | /* XXX : not implemented */ | |
4581 | spr_register(env, SPR_Exxx_DBCNT, "DBCNT", | |
4582 | SPR_NOACCESS, SPR_NOACCESS, | |
4583 | &spr_read_generic, &spr_write_generic, | |
4584 | 0x00000000); | |
4585 | /* XXX : not implemented */ | |
4586 | spr_register(env, SPR_Exxx_DBCR3, "DBCR3", | |
4587 | SPR_NOACCESS, SPR_NOACCESS, | |
4588 | &spr_read_generic, &spr_write_generic, | |
4589 | 0x00000000); | |
4590 | /* XXX : not implemented */ | |
4591 | spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", | |
deb05c4c AG |
4592 | &spr_read_generic, SPR_NOACCESS, |
4593 | &spr_read_generic, SPR_NOACCESS, | |
80d11f44 JM |
4594 | 0x00000000); |
4595 | /* XXX : not implemented */ | |
4596 | spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", | |
4597 | SPR_NOACCESS, SPR_NOACCESS, | |
4598 | &spr_read_generic, &spr_write_generic, | |
4599 | 0x00000000); | |
4600 | /* XXX : not implemented */ | |
4601 | spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", | |
4602 | SPR_NOACCESS, SPR_NOACCESS, | |
4603 | &spr_read_generic, &spr_write_generic, | |
4604 | 0x00000000); | |
4605 | /* XXX : not implemented */ | |
4606 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", | |
4607 | SPR_NOACCESS, SPR_NOACCESS, | |
4608 | &spr_read_generic, &spr_write_generic, | |
4609 | 0x00000000); | |
4610 | /* XXX : not implemented */ | |
4611 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", | |
4612 | SPR_NOACCESS, SPR_NOACCESS, | |
4613 | &spr_read_generic, &spr_write_generic, | |
4614 | 0x00000000); | |
4615 | /* XXX : not implemented */ | |
4616 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
4617 | SPR_NOACCESS, SPR_NOACCESS, | |
4618 | &spr_read_generic, &spr_write_generic, | |
4619 | 0x00000000); | |
4620 | /* XXX : not implemented */ | |
4621 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
4622 | SPR_NOACCESS, SPR_NOACCESS, | |
4623 | &spr_read_generic, &spr_write_generic, | |
4624 | 0x00000000); | |
01662f3e AG |
4625 | /* XXX : not implemented */ |
4626 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
4627 | SPR_NOACCESS, SPR_NOACCESS, | |
4628 | &spr_read_generic, &spr_write_generic, | |
4629 | 0x00000000); /* TOFIX */ | |
80d11f44 JM |
4630 | spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", |
4631 | SPR_NOACCESS, SPR_NOACCESS, | |
4632 | &spr_read_generic, &spr_write_generic, | |
4633 | 0x00000000); | |
4634 | spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", | |
4635 | SPR_NOACCESS, SPR_NOACCESS, | |
e1833e1f JM |
4636 | &spr_read_generic, &spr_write_generic, |
4637 | 0x00000000); | |
f2e63a42 | 4638 | #if !defined(CONFIG_USER_ONLY) |
e1833e1f JM |
4639 | env->nb_tlb = 64; |
4640 | env->nb_ways = 1; | |
4641 | env->id_tlbs = 0; | |
1c53accc | 4642 | env->tlb_type = TLB_EMB; |
f2e63a42 | 4643 | #endif |
e9cd84b9 | 4644 | init_excp_e200(env, 0xFFFF0000UL); |
d63001d1 JM |
4645 | env->dcache_line_size = 32; |
4646 | env->icache_line_size = 32; | |
e1833e1f | 4647 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 | 4648 | } |
a750fc0b | 4649 | |
7856e3a4 AF |
4650 | POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) |
4651 | { | |
ca5dff0a | 4652 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4653 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4654 | ||
ca5dff0a | 4655 | dc->desc = "e200 core"; |
7856e3a4 AF |
4656 | pcc->init_proc = init_proc_e200; |
4657 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4658 | /* XXX: unimplemented instructions: |
4659 | * dcblc | |
4660 | * dcbtlst | |
4661 | * dcbtstls | |
4662 | * icblc | |
4663 | * icbtls | |
4664 | * tlbivax | |
4665 | * all SPE multiply-accumulate instructions | |
4666 | */ | |
4667 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | | |
4668 | PPC_SPE | PPC_SPE_SINGLE | | |
4669 | PPC_WRTEE | PPC_RFDI | | |
4670 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
4671 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4672 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | | |
4673 | PPC_BOOKE; | |
9df5a466 TM |
4674 | pcc->msr_mask = (1ull << MSR_UCLE) | |
4675 | (1ull << MSR_SPE) | | |
4676 | (1ull << MSR_POW) | | |
4677 | (1ull << MSR_CE) | | |
4678 | (1ull << MSR_EE) | | |
4679 | (1ull << MSR_PR) | | |
4680 | (1ull << MSR_FP) | | |
4681 | (1ull << MSR_ME) | | |
4682 | (1ull << MSR_FE0) | | |
4683 | (1ull << MSR_DWE) | | |
4684 | (1ull << MSR_DE) | | |
4685 | (1ull << MSR_FE1) | | |
4686 | (1ull << MSR_IR) | | |
4687 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
4688 | pcc->mmu_model = POWERPC_MMU_BOOKE206; |
4689 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4690 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4691 | pcc->bfd_mach = bfd_mach_ppc_860; | |
4692 | pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | | |
4693 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | | |
4694 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4695 | } |
4696 | ||
80d11f44 | 4697 | static void init_proc_e300 (CPUPPCState *env) |
3fc6c082 | 4698 | { |
80d11f44 JM |
4699 | gen_spr_ne_601(env); |
4700 | gen_spr_603(env); | |
a750fc0b JM |
4701 | /* Time base */ |
4702 | gen_tbl(env); | |
80d11f44 JM |
4703 | /* hardware implementation registers */ |
4704 | /* XXX : not implemented */ | |
4705 | spr_register(env, SPR_HID0, "HID0", | |
4706 | SPR_NOACCESS, SPR_NOACCESS, | |
4707 | &spr_read_generic, &spr_write_generic, | |
4708 | 0x00000000); | |
4709 | /* XXX : not implemented */ | |
4710 | spr_register(env, SPR_HID1, "HID1", | |
4711 | SPR_NOACCESS, SPR_NOACCESS, | |
4712 | &spr_read_generic, &spr_write_generic, | |
4713 | 0x00000000); | |
8daf1781 TM |
4714 | /* XXX : not implemented */ |
4715 | spr_register(env, SPR_HID2, "HID2", | |
4716 | SPR_NOACCESS, SPR_NOACCESS, | |
4717 | &spr_read_generic, &spr_write_generic, | |
4718 | 0x00000000); | |
3ade1a05 FC |
4719 | /* Breakpoints */ |
4720 | /* XXX : not implemented */ | |
4721 | spr_register(env, SPR_DABR, "DABR", | |
4722 | SPR_NOACCESS, SPR_NOACCESS, | |
4723 | &spr_read_generic, &spr_write_generic, | |
4724 | 0x00000000); | |
4725 | /* XXX : not implemented */ | |
4726 | spr_register(env, SPR_DABR2, "DABR2", | |
4727 | SPR_NOACCESS, SPR_NOACCESS, | |
4728 | &spr_read_generic, &spr_write_generic, | |
4729 | 0x00000000); | |
4730 | /* XXX : not implemented */ | |
4731 | spr_register(env, SPR_IABR2, "IABR2", | |
4732 | SPR_NOACCESS, SPR_NOACCESS, | |
4733 | &spr_read_generic, &spr_write_generic, | |
4734 | 0x00000000); | |
4735 | /* XXX : not implemented */ | |
4736 | spr_register(env, SPR_IBCR, "IBCR", | |
4737 | SPR_NOACCESS, SPR_NOACCESS, | |
4738 | &spr_read_generic, &spr_write_generic, | |
4739 | 0x00000000); | |
4740 | /* XXX : not implemented */ | |
4741 | spr_register(env, SPR_DBCR, "DBCR", | |
4742 | SPR_NOACCESS, SPR_NOACCESS, | |
4743 | &spr_read_generic, &spr_write_generic, | |
4744 | 0x00000000); | |
80d11f44 JM |
4745 | /* Memory management */ |
4746 | gen_low_BATs(env); | |
8daf1781 | 4747 | gen_high_BATs(env); |
80d11f44 JM |
4748 | gen_6xx_7xx_soft_tlb(env, 64, 2); |
4749 | init_excp_603(env); | |
4750 | env->dcache_line_size = 32; | |
4751 | env->icache_line_size = 32; | |
4752 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 4753 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
80d11f44 JM |
4754 | } |
4755 | ||
7856e3a4 AF |
4756 | POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) |
4757 | { | |
ca5dff0a | 4758 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4759 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4760 | ||
ca5dff0a | 4761 | dc->desc = "e300 core"; |
7856e3a4 AF |
4762 | pcc->init_proc = init_proc_e300; |
4763 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4764 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4765 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4766 | PPC_FLOAT_STFIWX | | |
4767 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4768 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4769 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4770 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
4771 | pcc->msr_mask = (1ull << MSR_POW) | |
4772 | (1ull << MSR_TGPR) | | |
4773 | (1ull << MSR_ILE) | | |
4774 | (1ull << MSR_EE) | | |
4775 | (1ull << MSR_PR) | | |
4776 | (1ull << MSR_FP) | | |
4777 | (1ull << MSR_ME) | | |
4778 | (1ull << MSR_FE0) | | |
4779 | (1ull << MSR_SE) | | |
4780 | (1ull << MSR_DE) | | |
4781 | (1ull << MSR_FE1) | | |
4782 | (1ull << MSR_AL) | | |
4783 | (1ull << MSR_EP) | | |
4784 | (1ull << MSR_IR) | | |
4785 | (1ull << MSR_DR) | | |
4786 | (1ull << MSR_RI) | | |
4787 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
4788 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
4789 | pcc->excp_model = POWERPC_EXCP_603; | |
4790 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4791 | pcc->bfd_mach = bfd_mach_ppc_603; | |
4792 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4793 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4794 | } |
4795 | ||
b81ccf8a | 4796 | #if !defined(CONFIG_USER_ONLY) |
69b058c8 | 4797 | static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) |
b81ccf8a AG |
4798 | { |
4799 | TCGv val = tcg_temp_new(); | |
4800 | tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); | |
4801 | gen_store_spr(SPR_BOOKE_MAS3, val); | |
cfee0218 | 4802 | tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); |
b81ccf8a AG |
4803 | gen_store_spr(SPR_BOOKE_MAS7, val); |
4804 | tcg_temp_free(val); | |
4805 | } | |
4806 | ||
69b058c8 | 4807 | static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) |
b81ccf8a AG |
4808 | { |
4809 | TCGv mas7 = tcg_temp_new(); | |
4810 | TCGv mas3 = tcg_temp_new(); | |
4811 | gen_load_spr(mas7, SPR_BOOKE_MAS7); | |
4812 | tcg_gen_shli_tl(mas7, mas7, 32); | |
4813 | gen_load_spr(mas3, SPR_BOOKE_MAS3); | |
4814 | tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); | |
4815 | tcg_temp_free(mas3); | |
4816 | tcg_temp_free(mas7); | |
4817 | } | |
4818 | ||
b81ccf8a AG |
4819 | #endif |
4820 | ||
f7aa5583 VS |
4821 | enum fsl_e500_version { |
4822 | fsl_e500v1, | |
4823 | fsl_e500v2, | |
4824 | fsl_e500mc, | |
b81ccf8a | 4825 | fsl_e5500, |
f7aa5583 VS |
4826 | }; |
4827 | ||
01662f3e | 4828 | static void init_proc_e500 (CPUPPCState *env, int version) |
80d11f44 | 4829 | { |
a47dddd7 | 4830 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
01662f3e | 4831 | uint32_t tlbncfg[2]; |
b81ccf8a | 4832 | uint64_t ivor_mask; |
e9cd84b9 | 4833 | uint64_t ivpr_mask = 0xFFFF0000ULL; |
a496e8ee AG |
4834 | uint32_t l1cfg0 = 0x3800 /* 8 ways */ |
4835 | | 0x0020; /* 32 kb */ | |
d2ea2bf7 AG |
4836 | uint32_t l1cfg1 = 0x3800 /* 8 ways */ |
4837 | | 0x0020; /* 32 kb */ | |
01662f3e AG |
4838 | #if !defined(CONFIG_USER_ONLY) |
4839 | int i; | |
4840 | #endif | |
4841 | ||
80d11f44 JM |
4842 | /* Time base */ |
4843 | gen_tbl(env); | |
01662f3e AG |
4844 | /* |
4845 | * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't | |
4846 | * complain when accessing them. | |
4847 | * gen_spr_BookE(env, 0x0000000F0000FD7FULL); | |
4848 | */ | |
b81ccf8a AG |
4849 | switch (version) { |
4850 | case fsl_e500v1: | |
4851 | case fsl_e500v2: | |
4852 | default: | |
4853 | ivor_mask = 0x0000000F0000FFFFULL; | |
4854 | break; | |
4855 | case fsl_e500mc: | |
4856 | case fsl_e5500: | |
4857 | ivor_mask = 0x000003FE0000FFFFULL; | |
4858 | break; | |
2c9732db AG |
4859 | } |
4860 | gen_spr_BookE(env, ivor_mask); | |
80d11f44 JM |
4861 | /* Processor identification */ |
4862 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
4863 | SPR_NOACCESS, SPR_NOACCESS, | |
4864 | &spr_read_generic, &spr_write_pir, | |
4865 | 0x00000000); | |
4866 | /* XXX : not implemented */ | |
4867 | spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", | |
d34defbc AJ |
4868 | &spr_read_spefscr, &spr_write_spefscr, |
4869 | &spr_read_spefscr, &spr_write_spefscr, | |
80d11f44 | 4870 | 0x00000000); |
892c587f | 4871 | #if !defined(CONFIG_USER_ONLY) |
80d11f44 | 4872 | /* Memory management */ |
80d11f44 | 4873 | env->nb_pids = 3; |
01662f3e AG |
4874 | env->nb_ways = 2; |
4875 | env->id_tlbs = 0; | |
4876 | switch (version) { | |
f7aa5583 | 4877 | case fsl_e500v1: |
01662f3e AG |
4878 | tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); |
4879 | tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); | |
4880 | break; | |
f7aa5583 | 4881 | case fsl_e500v2: |
01662f3e AG |
4882 | tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); |
4883 | tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); | |
f7aa5583 VS |
4884 | break; |
4885 | case fsl_e500mc: | |
b81ccf8a | 4886 | case fsl_e5500: |
f7aa5583 VS |
4887 | tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); |
4888 | tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); | |
892c587f AG |
4889 | break; |
4890 | default: | |
a47dddd7 | 4891 | cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); |
892c587f AG |
4892 | } |
4893 | #endif | |
4894 | /* Cache sizes */ | |
4895 | switch (version) { | |
4896 | case fsl_e500v1: | |
4897 | case fsl_e500v2: | |
4898 | env->dcache_line_size = 32; | |
4899 | env->icache_line_size = 32; | |
4900 | break; | |
4901 | case fsl_e500mc: | |
b81ccf8a | 4902 | case fsl_e5500: |
f7aa5583 VS |
4903 | env->dcache_line_size = 64; |
4904 | env->icache_line_size = 64; | |
a496e8ee | 4905 | l1cfg0 |= 0x1000000; /* 64 byte cache block size */ |
d2ea2bf7 | 4906 | l1cfg1 |= 0x1000000; /* 64 byte cache block size */ |
01662f3e AG |
4907 | break; |
4908 | default: | |
a47dddd7 | 4909 | cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); |
01662f3e | 4910 | } |
01662f3e | 4911 | gen_spr_BookE206(env, 0x000000DF, tlbncfg); |
80d11f44 JM |
4912 | /* XXX : not implemented */ |
4913 | spr_register(env, SPR_HID0, "HID0", | |
4914 | SPR_NOACCESS, SPR_NOACCESS, | |
4915 | &spr_read_generic, &spr_write_generic, | |
4916 | 0x00000000); | |
4917 | /* XXX : not implemented */ | |
4918 | spr_register(env, SPR_HID1, "HID1", | |
4919 | SPR_NOACCESS, SPR_NOACCESS, | |
4920 | &spr_read_generic, &spr_write_generic, | |
4921 | 0x00000000); | |
4922 | /* XXX : not implemented */ | |
4923 | spr_register(env, SPR_Exxx_BBEAR, "BBEAR", | |
4924 | SPR_NOACCESS, SPR_NOACCESS, | |
4925 | &spr_read_generic, &spr_write_generic, | |
4926 | 0x00000000); | |
4927 | /* XXX : not implemented */ | |
4928 | spr_register(env, SPR_Exxx_BBTAR, "BBTAR", | |
4929 | SPR_NOACCESS, SPR_NOACCESS, | |
4930 | &spr_read_generic, &spr_write_generic, | |
4931 | 0x00000000); | |
4932 | /* XXX : not implemented */ | |
4933 | spr_register(env, SPR_Exxx_MCAR, "MCAR", | |
4934 | SPR_NOACCESS, SPR_NOACCESS, | |
4935 | &spr_read_generic, &spr_write_generic, | |
4936 | 0x00000000); | |
578bb252 | 4937 | /* XXX : not implemented */ |
a750fc0b JM |
4938 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
4939 | SPR_NOACCESS, SPR_NOACCESS, | |
4940 | &spr_read_generic, &spr_write_generic, | |
4941 | 0x00000000); | |
80d11f44 JM |
4942 | /* XXX : not implemented */ |
4943 | spr_register(env, SPR_Exxx_NPIDR, "NPIDR", | |
a750fc0b JM |
4944 | SPR_NOACCESS, SPR_NOACCESS, |
4945 | &spr_read_generic, &spr_write_generic, | |
4946 | 0x00000000); | |
80d11f44 JM |
4947 | /* XXX : not implemented */ |
4948 | spr_register(env, SPR_Exxx_BUCSR, "BUCSR", | |
a750fc0b JM |
4949 | SPR_NOACCESS, SPR_NOACCESS, |
4950 | &spr_read_generic, &spr_write_generic, | |
4951 | 0x00000000); | |
578bb252 | 4952 | /* XXX : not implemented */ |
80d11f44 | 4953 | spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", |
deb05c4c AG |
4954 | &spr_read_generic, SPR_NOACCESS, |
4955 | &spr_read_generic, SPR_NOACCESS, | |
a496e8ee | 4956 | l1cfg0); |
d2ea2bf7 AG |
4957 | spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", |
4958 | &spr_read_generic, SPR_NOACCESS, | |
4959 | &spr_read_generic, SPR_NOACCESS, | |
4960 | l1cfg1); | |
80d11f44 JM |
4961 | spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", |
4962 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 4963 | &spr_read_generic, &spr_write_e500_l1csr0, |
80d11f44 | 4964 | 0x00000000); |
80d11f44 JM |
4965 | spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", |
4966 | SPR_NOACCESS, SPR_NOACCESS, | |
ea71258d | 4967 | &spr_read_generic, &spr_write_e500_l1csr1, |
80d11f44 | 4968 | 0x00000000); |
80d11f44 JM |
4969 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", |
4970 | SPR_NOACCESS, SPR_NOACCESS, | |
4971 | &spr_read_generic, &spr_write_generic, | |
4972 | 0x00000000); | |
4973 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
4974 | SPR_NOACCESS, SPR_NOACCESS, | |
a750fc0b JM |
4975 | &spr_read_generic, &spr_write_generic, |
4976 | 0x00000000); | |
01662f3e AG |
4977 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", |
4978 | SPR_NOACCESS, SPR_NOACCESS, | |
4979 | &spr_read_generic, &spr_write_booke206_mmucsr0, | |
4980 | 0x00000000); | |
b81ccf8a AG |
4981 | spr_register(env, SPR_BOOKE_EPR, "EPR", |
4982 | SPR_NOACCESS, SPR_NOACCESS, | |
68c2dd70 | 4983 | &spr_read_generic, SPR_NOACCESS, |
b81ccf8a AG |
4984 | 0x00000000); |
4985 | /* XXX better abstract into Emb.xxx features */ | |
4986 | if (version == fsl_e5500) { | |
4987 | spr_register(env, SPR_BOOKE_EPCR, "EPCR", | |
4988 | SPR_NOACCESS, SPR_NOACCESS, | |
4989 | &spr_read_generic, &spr_write_generic, | |
4990 | 0x00000000); | |
4991 | spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", | |
4992 | SPR_NOACCESS, SPR_NOACCESS, | |
4993 | &spr_read_mas73, &spr_write_mas73, | |
4994 | 0x00000000); | |
4995 | ivpr_mask = (target_ulong)~0xFFFFULL; | |
4996 | } | |
01662f3e | 4997 | |
f2e63a42 | 4998 | #if !defined(CONFIG_USER_ONLY) |
01662f3e | 4999 | env->nb_tlb = 0; |
1c53accc | 5000 | env->tlb_type = TLB_MAS; |
01662f3e AG |
5001 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
5002 | env->nb_tlb += booke206_tlb_size(env, i); | |
5003 | } | |
f2e63a42 | 5004 | #endif |
01662f3e | 5005 | |
e9cd84b9 | 5006 | init_excp_e200(env, ivpr_mask); |
9fdc60bf | 5007 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5008 | ppce500_irq_init(ppc_env_get_cpu(env)); |
3fc6c082 | 5009 | } |
a750fc0b | 5010 | |
01662f3e AG |
5011 | static void init_proc_e500v1(CPUPPCState *env) |
5012 | { | |
f7aa5583 | 5013 | init_proc_e500(env, fsl_e500v1); |
01662f3e AG |
5014 | } |
5015 | ||
7856e3a4 AF |
5016 | POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) |
5017 | { | |
ca5dff0a | 5018 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5019 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5020 | ||
ca5dff0a | 5021 | dc->desc = "e500v1 core"; |
7856e3a4 AF |
5022 | pcc->init_proc = init_proc_e500v1; |
5023 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5024 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
5025 | PPC_SPE | PPC_SPE_SINGLE | | |
5026 | PPC_WRTEE | PPC_RFDI | | |
5027 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
5028 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
5029 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; | |
5030 | pcc->insns_flags2 = PPC2_BOOKE206; | |
9df5a466 TM |
5031 | pcc->msr_mask = (1ull << MSR_UCLE) | |
5032 | (1ull << MSR_SPE) | | |
5033 | (1ull << MSR_POW) | | |
5034 | (1ull << MSR_CE) | | |
5035 | (1ull << MSR_EE) | | |
5036 | (1ull << MSR_PR) | | |
5037 | (1ull << MSR_FP) | | |
5038 | (1ull << MSR_ME) | | |
5039 | (1ull << MSR_FE0) | | |
5040 | (1ull << MSR_DWE) | | |
5041 | (1ull << MSR_DE) | | |
5042 | (1ull << MSR_FE1) | | |
5043 | (1ull << MSR_IR) | | |
5044 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
5045 | pcc->mmu_model = POWERPC_MMU_BOOKE206; |
5046 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
5047 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
5048 | pcc->bfd_mach = bfd_mach_ppc_860; | |
5049 | pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | | |
5050 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | | |
5051 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5052 | } |
5053 | ||
01662f3e AG |
5054 | static void init_proc_e500v2(CPUPPCState *env) |
5055 | { | |
f7aa5583 VS |
5056 | init_proc_e500(env, fsl_e500v2); |
5057 | } | |
5058 | ||
7856e3a4 AF |
5059 | POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) |
5060 | { | |
ca5dff0a | 5061 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5062 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5063 | ||
ca5dff0a | 5064 | dc->desc = "e500v2 core"; |
7856e3a4 AF |
5065 | pcc->init_proc = init_proc_e500v2; |
5066 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5067 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
5068 | PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | | |
5069 | PPC_WRTEE | PPC_RFDI | | |
5070 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
5071 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
5072 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; | |
5073 | pcc->insns_flags2 = PPC2_BOOKE206; | |
9df5a466 TM |
5074 | pcc->msr_mask = (1ull << MSR_UCLE) | |
5075 | (1ull << MSR_SPE) | | |
5076 | (1ull << MSR_POW) | | |
5077 | (1ull << MSR_CE) | | |
5078 | (1ull << MSR_EE) | | |
5079 | (1ull << MSR_PR) | | |
5080 | (1ull << MSR_FP) | | |
5081 | (1ull << MSR_ME) | | |
5082 | (1ull << MSR_FE0) | | |
5083 | (1ull << MSR_DWE) | | |
5084 | (1ull << MSR_DE) | | |
5085 | (1ull << MSR_FE1) | | |
5086 | (1ull << MSR_IR) | | |
5087 | (1ull << MSR_DR); | |
ba9fd9f1 AF |
5088 | pcc->mmu_model = POWERPC_MMU_BOOKE206; |
5089 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
5090 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
5091 | pcc->bfd_mach = bfd_mach_ppc_860; | |
5092 | pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | | |
5093 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | | |
5094 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5095 | } |
5096 | ||
f7aa5583 VS |
5097 | static void init_proc_e500mc(CPUPPCState *env) |
5098 | { | |
5099 | init_proc_e500(env, fsl_e500mc); | |
01662f3e AG |
5100 | } |
5101 | ||
7856e3a4 AF |
5102 | POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) |
5103 | { | |
ca5dff0a | 5104 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5105 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5106 | ||
ca5dff0a | 5107 | dc->desc = "e500mc core"; |
7856e3a4 AF |
5108 | pcc->init_proc = init_proc_e500mc; |
5109 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
5110 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
5111 | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | | |
5112 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
5113 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
5114 | PPC_FLOAT | PPC_FLOAT_FRES | | |
5115 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | | |
5116 | PPC_FLOAT_STFIWX | PPC_WAIT | | |
5117 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; | |
5118 | pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; | |
9df5a466 TM |
5119 | pcc->msr_mask = (1ull << MSR_GS) | |
5120 | (1ull << MSR_UCLE) | | |
5121 | (1ull << MSR_CE) | | |
5122 | (1ull << MSR_EE) | | |
5123 | (1ull << MSR_PR) | | |
5124 | (1ull << MSR_FP) | | |
5125 | (1ull << MSR_ME) | | |
5126 | (1ull << MSR_FE0) | | |
5127 | (1ull << MSR_DE) | | |
5128 | (1ull << MSR_FE1) | | |
5129 | (1ull << MSR_IR) | | |
5130 | (1ull << MSR_DR) | | |
5131 | (1ull << MSR_PX) | | |
5132 | (1ull << MSR_RI); | |
ba9fd9f1 AF |
5133 | pcc->mmu_model = POWERPC_MMU_BOOKE206; |
5134 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
5135 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
5136 | /* FIXME: figure out the correct flag for e500mc */ | |
5137 | pcc->bfd_mach = bfd_mach_ppc_e500; | |
5138 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
5139 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5140 | } |
5141 | ||
b81ccf8a AG |
5142 | #ifdef TARGET_PPC64 |
5143 | static void init_proc_e5500(CPUPPCState *env) | |
5144 | { | |
5145 | init_proc_e500(env, fsl_e5500); | |
5146 | } | |
7856e3a4 AF |
5147 | |
5148 | POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) | |
5149 | { | |
ca5dff0a | 5150 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5151 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5152 | ||
ca5dff0a | 5153 | dc->desc = "e5500 core"; |
7856e3a4 AF |
5154 | pcc->init_proc = init_proc_e5500; |
5155 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
5156 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
5157 | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | | |
5158 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
5159 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
5160 | PPC_FLOAT | PPC_FLOAT_FRES | | |
5161 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | | |
5162 | PPC_FLOAT_STFIWX | PPC_WAIT | | |
5163 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | | |
5164 | PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; | |
4171853c PM |
5165 | pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \ |
5166 | PPC2_FP_CVT_S64; | |
9df5a466 TM |
5167 | pcc->msr_mask = (1ull << MSR_CM) | |
5168 | (1ull << MSR_GS) | | |
5169 | (1ull << MSR_UCLE) | | |
5170 | (1ull << MSR_CE) | | |
5171 | (1ull << MSR_EE) | | |
5172 | (1ull << MSR_PR) | | |
5173 | (1ull << MSR_FP) | | |
5174 | (1ull << MSR_ME) | | |
5175 | (1ull << MSR_FE0) | | |
5176 | (1ull << MSR_DE) | | |
5177 | (1ull << MSR_FE1) | | |
5178 | (1ull << MSR_IR) | | |
5179 | (1ull << MSR_DR) | | |
5180 | (1ull << MSR_PX) | | |
5181 | (1ull << MSR_RI); | |
ba9fd9f1 AF |
5182 | pcc->mmu_model = POWERPC_MMU_BOOKE206; |
5183 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
5184 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
5185 | /* FIXME: figure out the correct flag for e5500 */ | |
5186 | pcc->bfd_mach = bfd_mach_ppc_e500; | |
5187 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
5188 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 | 5189 | } |
b81ccf8a AG |
5190 | #endif |
5191 | ||
a750fc0b | 5192 | /* Non-embedded PowerPC */ |
a750fc0b JM |
5193 | |
5194 | /* POWER : same as 601, without mfmsr, mfsr */ | |
53116ebf AF |
5195 | POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data) |
5196 | { | |
ca5dff0a | 5197 | DeviceClass *dc = DEVICE_CLASS(oc); |
53116ebf AF |
5198 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5199 | ||
ca5dff0a | 5200 | dc->desc = "POWER"; |
953af181 | 5201 | /* pcc->insns_flags = XXX_TODO; */ |
ba9fd9f1 | 5202 | /* POWER RSC (from RAD6000) */ |
9df5a466 TM |
5203 | pcc->msr_mask = (1ull << MSR_EE) | |
5204 | (1ull << MSR_PR) | | |
5205 | (1ull << MSR_FP) | | |
5206 | (1ull << MSR_ME) | | |
5207 | (1ull << MSR_FE0) | | |
5208 | (1ull << MSR_SE) | | |
5209 | (1ull << MSR_DE) | | |
5210 | (1ull << MSR_AL) | | |
5211 | (1ull << MSR_EP) | | |
5212 | (1ull << MSR_IR) | | |
5213 | (1ull << MSR_DR); | |
53116ebf | 5214 | } |
a750fc0b | 5215 | |
082c6681 | 5216 | #define POWERPC_MSRR_601 (0x0000000000001040ULL) |
a750fc0b JM |
5217 | |
5218 | static void init_proc_601 (CPUPPCState *env) | |
3fc6c082 | 5219 | { |
a750fc0b JM |
5220 | gen_spr_ne_601(env); |
5221 | gen_spr_601(env); | |
5222 | /* Hardware implementation registers */ | |
5223 | /* XXX : not implemented */ | |
5224 | spr_register(env, SPR_HID0, "HID0", | |
5225 | SPR_NOACCESS, SPR_NOACCESS, | |
056401ea | 5226 | &spr_read_generic, &spr_write_hid0_601, |
faadf50e | 5227 | 0x80010080); |
a750fc0b JM |
5228 | /* XXX : not implemented */ |
5229 | spr_register(env, SPR_HID1, "HID1", | |
5230 | SPR_NOACCESS, SPR_NOACCESS, | |
5231 | &spr_read_generic, &spr_write_generic, | |
5232 | 0x00000000); | |
5233 | /* XXX : not implemented */ | |
5234 | spr_register(env, SPR_601_HID2, "HID2", | |
5235 | SPR_NOACCESS, SPR_NOACCESS, | |
5236 | &spr_read_generic, &spr_write_generic, | |
5237 | 0x00000000); | |
5238 | /* XXX : not implemented */ | |
5239 | spr_register(env, SPR_601_HID5, "HID5", | |
5240 | SPR_NOACCESS, SPR_NOACCESS, | |
5241 | &spr_read_generic, &spr_write_generic, | |
5242 | 0x00000000); | |
a750fc0b | 5243 | /* Memory management */ |
e1833e1f | 5244 | init_excp_601(env); |
082c6681 JM |
5245 | /* XXX: beware that dcache line size is 64 |
5246 | * but dcbz uses 32 bytes "sectors" | |
5247 | * XXX: this breaks clcs instruction ! | |
5248 | */ | |
5249 | env->dcache_line_size = 32; | |
d63001d1 | 5250 | env->icache_line_size = 64; |
faadf50e | 5251 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5252 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
3fc6c082 FB |
5253 | } |
5254 | ||
7856e3a4 AF |
5255 | POWERPC_FAMILY(601)(ObjectClass *oc, void *data) |
5256 | { | |
ca5dff0a | 5257 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5258 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5259 | ||
ca5dff0a | 5260 | dc->desc = "PowerPC 601"; |
7856e3a4 AF |
5261 | pcc->init_proc = init_proc_601; |
5262 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
5263 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | |
5264 | PPC_FLOAT | | |
5265 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5266 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | | |
5267 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5268 | pcc->msr_mask = (1ull << MSR_EE) | |
5269 | (1ull << MSR_PR) | | |
5270 | (1ull << MSR_FP) | | |
5271 | (1ull << MSR_ME) | | |
5272 | (1ull << MSR_FE0) | | |
5273 | (1ull << MSR_SE) | | |
5274 | (1ull << MSR_FE1) | | |
5275 | (1ull << MSR_EP) | | |
5276 | (1ull << MSR_IR) | | |
5277 | (1ull << MSR_DR); | |
ba9fd9f1 | 5278 | pcc->mmu_model = POWERPC_MMU_601; |
b632a148 DG |
5279 | #if defined(CONFIG_SOFTMMU) |
5280 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5281 | #endif | |
ba9fd9f1 AF |
5282 | pcc->excp_model = POWERPC_EXCP_601; |
5283 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5284 | pcc->bfd_mach = bfd_mach_ppc_601; | |
5285 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; | |
7856e3a4 AF |
5286 | } |
5287 | ||
082c6681 | 5288 | #define POWERPC_MSRR_601v (0x0000000000001040ULL) |
082c6681 JM |
5289 | |
5290 | static void init_proc_601v (CPUPPCState *env) | |
5291 | { | |
5292 | init_proc_601(env); | |
5293 | /* XXX : not implemented */ | |
5294 | spr_register(env, SPR_601_HID15, "HID15", | |
5295 | SPR_NOACCESS, SPR_NOACCESS, | |
5296 | &spr_read_generic, &spr_write_generic, | |
5297 | 0x00000000); | |
5298 | } | |
5299 | ||
7856e3a4 AF |
5300 | POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) |
5301 | { | |
ca5dff0a | 5302 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5303 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5304 | ||
ca5dff0a | 5305 | dc->desc = "PowerPC 601v"; |
7856e3a4 AF |
5306 | pcc->init_proc = init_proc_601v; |
5307 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
5308 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | |
5309 | PPC_FLOAT | | |
5310 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5311 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | | |
5312 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5313 | pcc->msr_mask = (1ull << MSR_EE) | |
5314 | (1ull << MSR_PR) | | |
5315 | (1ull << MSR_FP) | | |
5316 | (1ull << MSR_ME) | | |
5317 | (1ull << MSR_FE0) | | |
5318 | (1ull << MSR_SE) | | |
5319 | (1ull << MSR_FE1) | | |
5320 | (1ull << MSR_EP) | | |
5321 | (1ull << MSR_IR) | | |
5322 | (1ull << MSR_DR); | |
ba9fd9f1 | 5323 | pcc->mmu_model = POWERPC_MMU_601; |
b632a148 DG |
5324 | #if defined(CONFIG_SOFTMMU) |
5325 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5326 | #endif | |
ba9fd9f1 AF |
5327 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; |
5328 | pcc->bfd_mach = bfd_mach_ppc_601; | |
5329 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; | |
7856e3a4 AF |
5330 | } |
5331 | ||
a750fc0b | 5332 | static void init_proc_602 (CPUPPCState *env) |
3fc6c082 | 5333 | { |
a750fc0b JM |
5334 | gen_spr_ne_601(env); |
5335 | gen_spr_602(env); | |
5336 | /* Time base */ | |
5337 | gen_tbl(env); | |
5338 | /* hardware implementation registers */ | |
5339 | /* XXX : not implemented */ | |
5340 | spr_register(env, SPR_HID0, "HID0", | |
5341 | SPR_NOACCESS, SPR_NOACCESS, | |
5342 | &spr_read_generic, &spr_write_generic, | |
5343 | 0x00000000); | |
5344 | /* XXX : not implemented */ | |
5345 | spr_register(env, SPR_HID1, "HID1", | |
5346 | SPR_NOACCESS, SPR_NOACCESS, | |
5347 | &spr_read_generic, &spr_write_generic, | |
5348 | 0x00000000); | |
5349 | /* Memory management */ | |
5350 | gen_low_BATs(env); | |
5351 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 5352 | init_excp_602(env); |
d63001d1 JM |
5353 | env->dcache_line_size = 32; |
5354 | env->icache_line_size = 32; | |
a750fc0b | 5355 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5356 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b | 5357 | } |
3fc6c082 | 5358 | |
7856e3a4 AF |
5359 | POWERPC_FAMILY(602)(ObjectClass *oc, void *data) |
5360 | { | |
ca5dff0a | 5361 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5362 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5363 | ||
ca5dff0a | 5364 | dc->desc = "PowerPC 602"; |
7856e3a4 AF |
5365 | pcc->init_proc = init_proc_602; |
5366 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5367 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5368 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5369 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5370 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5371 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5372 | PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | | |
5373 | PPC_SEGMENT | PPC_602_SPEC; | |
9df5a466 TM |
5374 | pcc->msr_mask = (1ull << MSR_VSX) | |
5375 | (1ull << MSR_SA) | | |
5376 | (1ull << MSR_POW) | | |
5377 | (1ull << MSR_TGPR) | | |
5378 | (1ull << MSR_ILE) | | |
5379 | (1ull << MSR_EE) | | |
5380 | (1ull << MSR_PR) | | |
5381 | (1ull << MSR_FP) | | |
5382 | (1ull << MSR_ME) | | |
5383 | (1ull << MSR_FE0) | | |
5384 | (1ull << MSR_SE) | | |
5385 | (1ull << MSR_DE) | | |
5386 | (1ull << MSR_FE1) | | |
5387 | (1ull << MSR_EP) | | |
5388 | (1ull << MSR_IR) | | |
5389 | (1ull << MSR_DR) | | |
5390 | (1ull << MSR_RI) | | |
5391 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
5392 | /* XXX: 602 MMU is quite specific. Should add a special case */ |
5393 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
5394 | pcc->excp_model = POWERPC_EXCP_602; | |
5395 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5396 | pcc->bfd_mach = bfd_mach_ppc_602; | |
5397 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
5398 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5399 | } |
5400 | ||
a750fc0b JM |
5401 | static void init_proc_603 (CPUPPCState *env) |
5402 | { | |
5403 | gen_spr_ne_601(env); | |
5404 | gen_spr_603(env); | |
5405 | /* Time base */ | |
5406 | gen_tbl(env); | |
5407 | /* hardware implementation registers */ | |
5408 | /* XXX : not implemented */ | |
5409 | spr_register(env, SPR_HID0, "HID0", | |
5410 | SPR_NOACCESS, SPR_NOACCESS, | |
5411 | &spr_read_generic, &spr_write_generic, | |
5412 | 0x00000000); | |
5413 | /* XXX : not implemented */ | |
5414 | spr_register(env, SPR_HID1, "HID1", | |
5415 | SPR_NOACCESS, SPR_NOACCESS, | |
5416 | &spr_read_generic, &spr_write_generic, | |
5417 | 0x00000000); | |
5418 | /* Memory management */ | |
5419 | gen_low_BATs(env); | |
5420 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 5421 | init_excp_603(env); |
d63001d1 JM |
5422 | env->dcache_line_size = 32; |
5423 | env->icache_line_size = 32; | |
a750fc0b | 5424 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5425 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
3fc6c082 FB |
5426 | } |
5427 | ||
7856e3a4 AF |
5428 | POWERPC_FAMILY(603)(ObjectClass *oc, void *data) |
5429 | { | |
ca5dff0a | 5430 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5431 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5432 | ||
ca5dff0a | 5433 | dc->desc = "PowerPC 603"; |
7856e3a4 AF |
5434 | pcc->init_proc = init_proc_603; |
5435 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5436 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5437 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5438 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5439 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5440 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5441 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
5442 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5443 | pcc->msr_mask = (1ull << MSR_POW) | |
5444 | (1ull << MSR_TGPR) | | |
5445 | (1ull << MSR_ILE) | | |
5446 | (1ull << MSR_EE) | | |
5447 | (1ull << MSR_PR) | | |
5448 | (1ull << MSR_FP) | | |
5449 | (1ull << MSR_ME) | | |
5450 | (1ull << MSR_FE0) | | |
5451 | (1ull << MSR_SE) | | |
5452 | (1ull << MSR_DE) | | |
5453 | (1ull << MSR_FE1) | | |
5454 | (1ull << MSR_EP) | | |
5455 | (1ull << MSR_IR) | | |
5456 | (1ull << MSR_DR) | | |
5457 | (1ull << MSR_RI) | | |
5458 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
5459 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
5460 | pcc->excp_model = POWERPC_EXCP_603; | |
5461 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5462 | pcc->bfd_mach = bfd_mach_ppc_603; | |
5463 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
5464 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5465 | } |
5466 | ||
a750fc0b JM |
5467 | static void init_proc_603E (CPUPPCState *env) |
5468 | { | |
5469 | gen_spr_ne_601(env); | |
5470 | gen_spr_603(env); | |
5471 | /* Time base */ | |
5472 | gen_tbl(env); | |
5473 | /* hardware implementation registers */ | |
5474 | /* XXX : not implemented */ | |
5475 | spr_register(env, SPR_HID0, "HID0", | |
5476 | SPR_NOACCESS, SPR_NOACCESS, | |
5477 | &spr_read_generic, &spr_write_generic, | |
5478 | 0x00000000); | |
5479 | /* XXX : not implemented */ | |
5480 | spr_register(env, SPR_HID1, "HID1", | |
5481 | SPR_NOACCESS, SPR_NOACCESS, | |
5482 | &spr_read_generic, &spr_write_generic, | |
5483 | 0x00000000); | |
a750fc0b JM |
5484 | /* Memory management */ |
5485 | gen_low_BATs(env); | |
5486 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 5487 | init_excp_603(env); |
d63001d1 JM |
5488 | env->dcache_line_size = 32; |
5489 | env->icache_line_size = 32; | |
a750fc0b | 5490 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5491 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
5492 | } |
5493 | ||
7856e3a4 AF |
5494 | POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) |
5495 | { | |
ca5dff0a | 5496 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5497 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5498 | ||
ca5dff0a | 5499 | dc->desc = "PowerPC 603e"; |
7856e3a4 AF |
5500 | pcc->init_proc = init_proc_603E; |
5501 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5502 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5503 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5504 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5505 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5506 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5507 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
5508 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5509 | pcc->msr_mask = (1ull << MSR_POW) | |
5510 | (1ull << MSR_TGPR) | | |
5511 | (1ull << MSR_ILE) | | |
5512 | (1ull << MSR_EE) | | |
5513 | (1ull << MSR_PR) | | |
5514 | (1ull << MSR_FP) | | |
5515 | (1ull << MSR_ME) | | |
5516 | (1ull << MSR_FE0) | | |
5517 | (1ull << MSR_SE) | | |
5518 | (1ull << MSR_DE) | | |
5519 | (1ull << MSR_FE1) | | |
5520 | (1ull << MSR_EP) | | |
5521 | (1ull << MSR_IR) | | |
5522 | (1ull << MSR_DR) | | |
5523 | (1ull << MSR_RI) | | |
5524 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
5525 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
5526 | pcc->excp_model = POWERPC_EXCP_603E; | |
5527 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5528 | pcc->bfd_mach = bfd_mach_ppc_ec603e; | |
5529 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
5530 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5531 | } |
5532 | ||
a750fc0b JM |
5533 | static void init_proc_604 (CPUPPCState *env) |
5534 | { | |
5535 | gen_spr_ne_601(env); | |
5536 | gen_spr_604(env); | |
5537 | /* Time base */ | |
5538 | gen_tbl(env); | |
5539 | /* Hardware implementation registers */ | |
5540 | /* XXX : not implemented */ | |
082c6681 JM |
5541 | spr_register(env, SPR_HID0, "HID0", |
5542 | SPR_NOACCESS, SPR_NOACCESS, | |
5543 | &spr_read_generic, &spr_write_generic, | |
5544 | 0x00000000); | |
5545 | /* Memory management */ | |
5546 | gen_low_BATs(env); | |
5547 | init_excp_604(env); | |
5548 | env->dcache_line_size = 32; | |
5549 | env->icache_line_size = 32; | |
5550 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 5551 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
082c6681 JM |
5552 | } |
5553 | ||
7856e3a4 AF |
5554 | POWERPC_FAMILY(604)(ObjectClass *oc, void *data) |
5555 | { | |
ca5dff0a | 5556 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5557 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5558 | ||
ca5dff0a | 5559 | dc->desc = "PowerPC 604"; |
7856e3a4 AF |
5560 | pcc->init_proc = init_proc_604; |
5561 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
5562 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5563 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5564 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5565 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5566 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5567 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5568 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5569 | pcc->msr_mask = (1ull << MSR_POW) | |
5570 | (1ull << MSR_ILE) | | |
5571 | (1ull << MSR_EE) | | |
5572 | (1ull << MSR_PR) | | |
5573 | (1ull << MSR_FP) | | |
5574 | (1ull << MSR_ME) | | |
5575 | (1ull << MSR_FE0) | | |
5576 | (1ull << MSR_SE) | | |
5577 | (1ull << MSR_DE) | | |
5578 | (1ull << MSR_FE1) | | |
5579 | (1ull << MSR_EP) | | |
5580 | (1ull << MSR_IR) | | |
5581 | (1ull << MSR_DR) | | |
5582 | (1ull << MSR_PMM) | | |
5583 | (1ull << MSR_RI) | | |
5584 | (1ull << MSR_LE); | |
ba9fd9f1 | 5585 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
5586 | #if defined(CONFIG_SOFTMMU) |
5587 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5588 | #endif | |
ba9fd9f1 AF |
5589 | pcc->excp_model = POWERPC_EXCP_604; |
5590 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5591 | pcc->bfd_mach = bfd_mach_ppc_604; | |
5592 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5593 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5594 | } |
5595 | ||
082c6681 JM |
5596 | static void init_proc_604E (CPUPPCState *env) |
5597 | { | |
5598 | gen_spr_ne_601(env); | |
5599 | gen_spr_604(env); | |
5600 | /* XXX : not implemented */ | |
cb8b8bf8 | 5601 | spr_register(env, SPR_7XX_MMCR1, "MMCR1", |
082c6681 JM |
5602 | SPR_NOACCESS, SPR_NOACCESS, |
5603 | &spr_read_generic, &spr_write_generic, | |
5604 | 0x00000000); | |
5605 | /* XXX : not implemented */ | |
cb8b8bf8 | 5606 | spr_register(env, SPR_7XX_PMC3, "PMC3", |
082c6681 JM |
5607 | SPR_NOACCESS, SPR_NOACCESS, |
5608 | &spr_read_generic, &spr_write_generic, | |
5609 | 0x00000000); | |
5610 | /* XXX : not implemented */ | |
cb8b8bf8 | 5611 | spr_register(env, SPR_7XX_PMC4, "PMC4", |
082c6681 JM |
5612 | SPR_NOACCESS, SPR_NOACCESS, |
5613 | &spr_read_generic, &spr_write_generic, | |
5614 | 0x00000000); | |
5615 | /* Time base */ | |
5616 | gen_tbl(env); | |
5617 | /* Hardware implementation registers */ | |
5618 | /* XXX : not implemented */ | |
a750fc0b JM |
5619 | spr_register(env, SPR_HID0, "HID0", |
5620 | SPR_NOACCESS, SPR_NOACCESS, | |
5621 | &spr_read_generic, &spr_write_generic, | |
5622 | 0x00000000); | |
5623 | /* XXX : not implemented */ | |
5624 | spr_register(env, SPR_HID1, "HID1", | |
5625 | SPR_NOACCESS, SPR_NOACCESS, | |
5626 | &spr_read_generic, &spr_write_generic, | |
5627 | 0x00000000); | |
5628 | /* Memory management */ | |
5629 | gen_low_BATs(env); | |
e1833e1f | 5630 | init_excp_604(env); |
d63001d1 JM |
5631 | env->dcache_line_size = 32; |
5632 | env->icache_line_size = 32; | |
a750fc0b | 5633 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5634 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
5635 | } |
5636 | ||
7856e3a4 AF |
5637 | POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) |
5638 | { | |
ca5dff0a | 5639 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5640 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5641 | ||
ca5dff0a | 5642 | dc->desc = "PowerPC 604E"; |
7856e3a4 AF |
5643 | pcc->init_proc = init_proc_604E; |
5644 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
5645 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5646 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5647 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5648 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5649 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5650 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5651 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5652 | pcc->msr_mask = (1ull << MSR_POW) | |
5653 | (1ull << MSR_ILE) | | |
5654 | (1ull << MSR_EE) | | |
5655 | (1ull << MSR_PR) | | |
5656 | (1ull << MSR_FP) | | |
5657 | (1ull << MSR_ME) | | |
5658 | (1ull << MSR_FE0) | | |
5659 | (1ull << MSR_SE) | | |
5660 | (1ull << MSR_DE) | | |
5661 | (1ull << MSR_FE1) | | |
5662 | (1ull << MSR_EP) | | |
5663 | (1ull << MSR_IR) | | |
5664 | (1ull << MSR_DR) | | |
5665 | (1ull << MSR_PMM) | | |
5666 | (1ull << MSR_RI) | | |
5667 | (1ull << MSR_LE); | |
ba9fd9f1 | 5668 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
5669 | #if defined(CONFIG_SOFTMMU) |
5670 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5671 | #endif | |
ba9fd9f1 AF |
5672 | pcc->excp_model = POWERPC_EXCP_604; |
5673 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5674 | pcc->bfd_mach = bfd_mach_ppc_604; | |
5675 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5676 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5677 | } |
5678 | ||
bd928eba | 5679 | static void init_proc_740 (CPUPPCState *env) |
a750fc0b JM |
5680 | { |
5681 | gen_spr_ne_601(env); | |
5682 | gen_spr_7xx(env); | |
5683 | /* Time base */ | |
5684 | gen_tbl(env); | |
5685 | /* Thermal management */ | |
5686 | gen_spr_thrm(env); | |
5687 | /* Hardware implementation registers */ | |
5688 | /* XXX : not implemented */ | |
5689 | spr_register(env, SPR_HID0, "HID0", | |
5690 | SPR_NOACCESS, SPR_NOACCESS, | |
5691 | &spr_read_generic, &spr_write_generic, | |
5692 | 0x00000000); | |
5693 | /* XXX : not implemented */ | |
5694 | spr_register(env, SPR_HID1, "HID1", | |
5695 | SPR_NOACCESS, SPR_NOACCESS, | |
5696 | &spr_read_generic, &spr_write_generic, | |
5697 | 0x00000000); | |
5698 | /* Memory management */ | |
5699 | gen_low_BATs(env); | |
e1833e1f | 5700 | init_excp_7x0(env); |
d63001d1 JM |
5701 | env->dcache_line_size = 32; |
5702 | env->icache_line_size = 32; | |
a750fc0b | 5703 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 5704 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
5705 | } |
5706 | ||
7856e3a4 AF |
5707 | POWERPC_FAMILY(740)(ObjectClass *oc, void *data) |
5708 | { | |
ca5dff0a | 5709 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5710 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5711 | ||
ca5dff0a | 5712 | dc->desc = "PowerPC 740"; |
7856e3a4 AF |
5713 | pcc->init_proc = init_proc_740; |
5714 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5715 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5716 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5717 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5718 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5719 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5720 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5721 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5722 | pcc->msr_mask = (1ull << MSR_POW) | |
5723 | (1ull << MSR_ILE) | | |
5724 | (1ull << MSR_EE) | | |
5725 | (1ull << MSR_PR) | | |
5726 | (1ull << MSR_FP) | | |
5727 | (1ull << MSR_ME) | | |
5728 | (1ull << MSR_FE0) | | |
5729 | (1ull << MSR_SE) | | |
5730 | (1ull << MSR_DE) | | |
5731 | (1ull << MSR_FE1) | | |
5732 | (1ull << MSR_EP) | | |
5733 | (1ull << MSR_IR) | | |
5734 | (1ull << MSR_DR) | | |
5735 | (1ull << MSR_PMM) | | |
5736 | (1ull << MSR_RI) | | |
5737 | (1ull << MSR_LE); | |
ba9fd9f1 | 5738 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
5739 | #if defined(CONFIG_SOFTMMU) |
5740 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5741 | #endif | |
ba9fd9f1 AF |
5742 | pcc->excp_model = POWERPC_EXCP_7x0; |
5743 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5744 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5745 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5746 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5747 | } |
5748 | ||
bd928eba JM |
5749 | static void init_proc_750 (CPUPPCState *env) |
5750 | { | |
5751 | gen_spr_ne_601(env); | |
5752 | gen_spr_7xx(env); | |
5753 | /* XXX : not implemented */ | |
5754 | spr_register(env, SPR_L2CR, "L2CR", | |
5755 | SPR_NOACCESS, SPR_NOACCESS, | |
9633fcc6 | 5756 | &spr_read_generic, spr_access_nop, |
bd928eba JM |
5757 | 0x00000000); |
5758 | /* Time base */ | |
5759 | gen_tbl(env); | |
5760 | /* Thermal management */ | |
5761 | gen_spr_thrm(env); | |
5762 | /* Hardware implementation registers */ | |
5763 | /* XXX : not implemented */ | |
5764 | spr_register(env, SPR_HID0, "HID0", | |
5765 | SPR_NOACCESS, SPR_NOACCESS, | |
5766 | &spr_read_generic, &spr_write_generic, | |
5767 | 0x00000000); | |
5768 | /* XXX : not implemented */ | |
5769 | spr_register(env, SPR_HID1, "HID1", | |
5770 | SPR_NOACCESS, SPR_NOACCESS, | |
5771 | &spr_read_generic, &spr_write_generic, | |
5772 | 0x00000000); | |
5773 | /* Memory management */ | |
5774 | gen_low_BATs(env); | |
5775 | /* XXX: high BATs are also present but are known to be bugged on | |
5776 | * die version 1.x | |
5777 | */ | |
5778 | init_excp_7x0(env); | |
5779 | env->dcache_line_size = 32; | |
5780 | env->icache_line_size = 32; | |
5781 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 5782 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
bd928eba JM |
5783 | } |
5784 | ||
7856e3a4 AF |
5785 | POWERPC_FAMILY(750)(ObjectClass *oc, void *data) |
5786 | { | |
ca5dff0a | 5787 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5788 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5789 | ||
ca5dff0a | 5790 | dc->desc = "PowerPC 750"; |
7856e3a4 AF |
5791 | pcc->init_proc = init_proc_750; |
5792 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5793 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5794 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5795 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5796 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5797 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5798 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5799 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
5800 | pcc->msr_mask = (1ull << MSR_POW) | |
5801 | (1ull << MSR_ILE) | | |
5802 | (1ull << MSR_EE) | | |
5803 | (1ull << MSR_PR) | | |
5804 | (1ull << MSR_FP) | | |
5805 | (1ull << MSR_ME) | | |
5806 | (1ull << MSR_FE0) | | |
5807 | (1ull << MSR_SE) | | |
5808 | (1ull << MSR_DE) | | |
5809 | (1ull << MSR_FE1) | | |
5810 | (1ull << MSR_EP) | | |
5811 | (1ull << MSR_IR) | | |
5812 | (1ull << MSR_DR) | | |
5813 | (1ull << MSR_PMM) | | |
5814 | (1ull << MSR_RI) | | |
5815 | (1ull << MSR_LE); | |
ba9fd9f1 | 5816 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
5817 | #if defined(CONFIG_SOFTMMU) |
5818 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5819 | #endif | |
ba9fd9f1 AF |
5820 | pcc->excp_model = POWERPC_EXCP_7x0; |
5821 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5822 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5823 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5824 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5825 | } |
5826 | ||
bd928eba JM |
5827 | static void init_proc_750cl (CPUPPCState *env) |
5828 | { | |
5829 | gen_spr_ne_601(env); | |
5830 | gen_spr_7xx(env); | |
5831 | /* XXX : not implemented */ | |
5832 | spr_register(env, SPR_L2CR, "L2CR", | |
5833 | SPR_NOACCESS, SPR_NOACCESS, | |
9633fcc6 | 5834 | &spr_read_generic, spr_access_nop, |
bd928eba JM |
5835 | 0x00000000); |
5836 | /* Time base */ | |
5837 | gen_tbl(env); | |
5838 | /* Thermal management */ | |
5839 | /* Those registers are fake on 750CL */ | |
5840 | spr_register(env, SPR_THRM1, "THRM1", | |
5841 | SPR_NOACCESS, SPR_NOACCESS, | |
5842 | &spr_read_generic, &spr_write_generic, | |
5843 | 0x00000000); | |
5844 | spr_register(env, SPR_THRM2, "THRM2", | |
5845 | SPR_NOACCESS, SPR_NOACCESS, | |
5846 | &spr_read_generic, &spr_write_generic, | |
5847 | 0x00000000); | |
5848 | spr_register(env, SPR_THRM3, "THRM3", | |
5849 | SPR_NOACCESS, SPR_NOACCESS, | |
5850 | &spr_read_generic, &spr_write_generic, | |
5851 | 0x00000000); | |
5852 | /* XXX: not implemented */ | |
5853 | spr_register(env, SPR_750_TDCL, "TDCL", | |
5854 | SPR_NOACCESS, SPR_NOACCESS, | |
5855 | &spr_read_generic, &spr_write_generic, | |
5856 | 0x00000000); | |
5857 | spr_register(env, SPR_750_TDCH, "TDCH", | |
5858 | SPR_NOACCESS, SPR_NOACCESS, | |
5859 | &spr_read_generic, &spr_write_generic, | |
5860 | 0x00000000); | |
5861 | /* DMA */ | |
5862 | /* XXX : not implemented */ | |
5863 | spr_register(env, SPR_750_WPAR, "WPAR", | |
5864 | SPR_NOACCESS, SPR_NOACCESS, | |
5865 | &spr_read_generic, &spr_write_generic, | |
5866 | 0x00000000); | |
5867 | spr_register(env, SPR_750_DMAL, "DMAL", | |
5868 | SPR_NOACCESS, SPR_NOACCESS, | |
5869 | &spr_read_generic, &spr_write_generic, | |
5870 | 0x00000000); | |
5871 | spr_register(env, SPR_750_DMAU, "DMAU", | |
5872 | SPR_NOACCESS, SPR_NOACCESS, | |
5873 | &spr_read_generic, &spr_write_generic, | |
5874 | 0x00000000); | |
5875 | /* Hardware implementation registers */ | |
5876 | /* XXX : not implemented */ | |
5877 | spr_register(env, SPR_HID0, "HID0", | |
5878 | SPR_NOACCESS, SPR_NOACCESS, | |
5879 | &spr_read_generic, &spr_write_generic, | |
5880 | 0x00000000); | |
5881 | /* XXX : not implemented */ | |
5882 | spr_register(env, SPR_HID1, "HID1", | |
5883 | SPR_NOACCESS, SPR_NOACCESS, | |
5884 | &spr_read_generic, &spr_write_generic, | |
5885 | 0x00000000); | |
5886 | /* XXX : not implemented */ | |
5887 | spr_register(env, SPR_750CL_HID2, "HID2", | |
5888 | SPR_NOACCESS, SPR_NOACCESS, | |
5889 | &spr_read_generic, &spr_write_generic, | |
5890 | 0x00000000); | |
5891 | /* XXX : not implemented */ | |
5892 | spr_register(env, SPR_750CL_HID4, "HID4", | |
5893 | SPR_NOACCESS, SPR_NOACCESS, | |
5894 | &spr_read_generic, &spr_write_generic, | |
5895 | 0x00000000); | |
5896 | /* Quantization registers */ | |
5897 | /* XXX : not implemented */ | |
5898 | spr_register(env, SPR_750_GQR0, "GQR0", | |
5899 | SPR_NOACCESS, SPR_NOACCESS, | |
5900 | &spr_read_generic, &spr_write_generic, | |
5901 | 0x00000000); | |
5902 | /* XXX : not implemented */ | |
5903 | spr_register(env, SPR_750_GQR1, "GQR1", | |
5904 | SPR_NOACCESS, SPR_NOACCESS, | |
5905 | &spr_read_generic, &spr_write_generic, | |
5906 | 0x00000000); | |
5907 | /* XXX : not implemented */ | |
5908 | spr_register(env, SPR_750_GQR2, "GQR2", | |
5909 | SPR_NOACCESS, SPR_NOACCESS, | |
5910 | &spr_read_generic, &spr_write_generic, | |
5911 | 0x00000000); | |
5912 | /* XXX : not implemented */ | |
5913 | spr_register(env, SPR_750_GQR3, "GQR3", | |
5914 | SPR_NOACCESS, SPR_NOACCESS, | |
5915 | &spr_read_generic, &spr_write_generic, | |
5916 | 0x00000000); | |
5917 | /* XXX : not implemented */ | |
5918 | spr_register(env, SPR_750_GQR4, "GQR4", | |
5919 | SPR_NOACCESS, SPR_NOACCESS, | |
5920 | &spr_read_generic, &spr_write_generic, | |
5921 | 0x00000000); | |
5922 | /* XXX : not implemented */ | |
5923 | spr_register(env, SPR_750_GQR5, "GQR5", | |
5924 | SPR_NOACCESS, SPR_NOACCESS, | |
5925 | &spr_read_generic, &spr_write_generic, | |
5926 | 0x00000000); | |
5927 | /* XXX : not implemented */ | |
5928 | spr_register(env, SPR_750_GQR6, "GQR6", | |
5929 | SPR_NOACCESS, SPR_NOACCESS, | |
5930 | &spr_read_generic, &spr_write_generic, | |
5931 | 0x00000000); | |
5932 | /* XXX : not implemented */ | |
5933 | spr_register(env, SPR_750_GQR7, "GQR7", | |
5934 | SPR_NOACCESS, SPR_NOACCESS, | |
5935 | &spr_read_generic, &spr_write_generic, | |
5936 | 0x00000000); | |
5937 | /* Memory management */ | |
5938 | gen_low_BATs(env); | |
5939 | /* PowerPC 750cl has 8 DBATs and 8 IBATs */ | |
5940 | gen_high_BATs(env); | |
5941 | init_excp_750cl(env); | |
5942 | env->dcache_line_size = 32; | |
5943 | env->icache_line_size = 32; | |
5944 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 5945 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
bd928eba JM |
5946 | } |
5947 | ||
7856e3a4 AF |
5948 | POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) |
5949 | { | |
ca5dff0a | 5950 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5951 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5952 | ||
ca5dff0a | 5953 | dc->desc = "PowerPC 750 CL"; |
7856e3a4 AF |
5954 | pcc->init_proc = init_proc_750cl; |
5955 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5956 | /* XXX: not implemented: |
5957 | * cache lock instructions: | |
5958 | * dcbz_l | |
5959 | * floating point paired instructions | |
5960 | * psq_lux | |
5961 | * psq_lx | |
5962 | * psq_stux | |
5963 | * psq_stx | |
5964 | * ps_abs | |
5965 | * ps_add | |
5966 | * ps_cmpo0 | |
5967 | * ps_cmpo1 | |
5968 | * ps_cmpu0 | |
5969 | * ps_cmpu1 | |
5970 | * ps_div | |
5971 | * ps_madd | |
5972 | * ps_madds0 | |
5973 | * ps_madds1 | |
5974 | * ps_merge00 | |
5975 | * ps_merge01 | |
5976 | * ps_merge10 | |
5977 | * ps_merge11 | |
5978 | * ps_mr | |
5979 | * ps_msub | |
5980 | * ps_mul | |
5981 | * ps_muls0 | |
5982 | * ps_muls1 | |
5983 | * ps_nabs | |
5984 | * ps_neg | |
5985 | * ps_nmadd | |
5986 | * ps_nmsub | |
5987 | * ps_res | |
5988 | * ps_rsqrte | |
5989 | * ps_sel | |
5990 | * ps_sub | |
5991 | * ps_sum0 | |
5992 | * ps_sum1 | |
5993 | */ | |
5994 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | | |
5995 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5996 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5997 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5998 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5999 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6000 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
6001 | pcc->msr_mask = (1ull << MSR_POW) | |
6002 | (1ull << MSR_ILE) | | |
6003 | (1ull << MSR_EE) | | |
6004 | (1ull << MSR_PR) | | |
6005 | (1ull << MSR_FP) | | |
6006 | (1ull << MSR_ME) | | |
6007 | (1ull << MSR_FE0) | | |
6008 | (1ull << MSR_SE) | | |
6009 | (1ull << MSR_DE) | | |
6010 | (1ull << MSR_FE1) | | |
6011 | (1ull << MSR_EP) | | |
6012 | (1ull << MSR_IR) | | |
6013 | (1ull << MSR_DR) | | |
6014 | (1ull << MSR_PMM) | | |
6015 | (1ull << MSR_RI) | | |
6016 | (1ull << MSR_LE); | |
ba9fd9f1 | 6017 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
6018 | #if defined(CONFIG_SOFTMMU) |
6019 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6020 | #endif | |
ba9fd9f1 AF |
6021 | pcc->excp_model = POWERPC_EXCP_7x0; |
6022 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6023 | pcc->bfd_mach = bfd_mach_ppc_750; | |
6024 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
6025 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6026 | } |
6027 | ||
bd928eba JM |
6028 | static void init_proc_750cx (CPUPPCState *env) |
6029 | { | |
6030 | gen_spr_ne_601(env); | |
6031 | gen_spr_7xx(env); | |
6032 | /* XXX : not implemented */ | |
6033 | spr_register(env, SPR_L2CR, "L2CR", | |
6034 | SPR_NOACCESS, SPR_NOACCESS, | |
9633fcc6 | 6035 | &spr_read_generic, spr_access_nop, |
bd928eba JM |
6036 | 0x00000000); |
6037 | /* Time base */ | |
6038 | gen_tbl(env); | |
6039 | /* Thermal management */ | |
6040 | gen_spr_thrm(env); | |
6041 | /* This register is not implemented but is present for compatibility */ | |
6042 | spr_register(env, SPR_SDA, "SDA", | |
6043 | SPR_NOACCESS, SPR_NOACCESS, | |
6044 | &spr_read_generic, &spr_write_generic, | |
6045 | 0x00000000); | |
6046 | /* Hardware implementation registers */ | |
6047 | /* XXX : not implemented */ | |
6048 | spr_register(env, SPR_HID0, "HID0", | |
6049 | SPR_NOACCESS, SPR_NOACCESS, | |
6050 | &spr_read_generic, &spr_write_generic, | |
6051 | 0x00000000); | |
6052 | /* XXX : not implemented */ | |
6053 | spr_register(env, SPR_HID1, "HID1", | |
6054 | SPR_NOACCESS, SPR_NOACCESS, | |
6055 | &spr_read_generic, &spr_write_generic, | |
6056 | 0x00000000); | |
6057 | /* Memory management */ | |
6058 | gen_low_BATs(env); | |
4e777442 JM |
6059 | /* PowerPC 750cx has 8 DBATs and 8 IBATs */ |
6060 | gen_high_BATs(env); | |
bd928eba JM |
6061 | init_excp_750cx(env); |
6062 | env->dcache_line_size = 32; | |
6063 | env->icache_line_size = 32; | |
6064 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 6065 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
bd928eba JM |
6066 | } |
6067 | ||
7856e3a4 AF |
6068 | POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) |
6069 | { | |
ca5dff0a | 6070 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6071 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6072 | ||
ca5dff0a | 6073 | dc->desc = "PowerPC 750CX"; |
7856e3a4 AF |
6074 | pcc->init_proc = init_proc_750cx; |
6075 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6076 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6077 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6078 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
6079 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6080 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6081 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6082 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
6083 | pcc->msr_mask = (1ull << MSR_POW) | |
6084 | (1ull << MSR_ILE) | | |
6085 | (1ull << MSR_EE) | | |
6086 | (1ull << MSR_PR) | | |
6087 | (1ull << MSR_FP) | | |
6088 | (1ull << MSR_ME) | | |
6089 | (1ull << MSR_FE0) | | |
6090 | (1ull << MSR_SE) | | |
6091 | (1ull << MSR_DE) | | |
6092 | (1ull << MSR_FE1) | | |
6093 | (1ull << MSR_EP) | | |
6094 | (1ull << MSR_IR) | | |
6095 | (1ull << MSR_DR) | | |
6096 | (1ull << MSR_PMM) | | |
6097 | (1ull << MSR_RI) | | |
6098 | (1ull << MSR_LE); | |
ba9fd9f1 | 6099 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
6100 | #if defined(CONFIG_SOFTMMU) |
6101 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6102 | #endif | |
ba9fd9f1 AF |
6103 | pcc->excp_model = POWERPC_EXCP_7x0; |
6104 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6105 | pcc->bfd_mach = bfd_mach_ppc_750; | |
6106 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
6107 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6108 | } |
6109 | ||
a750fc0b JM |
6110 | static void init_proc_750fx (CPUPPCState *env) |
6111 | { | |
6112 | gen_spr_ne_601(env); | |
6113 | gen_spr_7xx(env); | |
bd928eba JM |
6114 | /* XXX : not implemented */ |
6115 | spr_register(env, SPR_L2CR, "L2CR", | |
6116 | SPR_NOACCESS, SPR_NOACCESS, | |
9633fcc6 | 6117 | &spr_read_generic, spr_access_nop, |
bd928eba | 6118 | 0x00000000); |
a750fc0b JM |
6119 | /* Time base */ |
6120 | gen_tbl(env); | |
6121 | /* Thermal management */ | |
6122 | gen_spr_thrm(env); | |
bd928eba JM |
6123 | /* XXX : not implemented */ |
6124 | spr_register(env, SPR_750_THRM4, "THRM4", | |
6125 | SPR_NOACCESS, SPR_NOACCESS, | |
6126 | &spr_read_generic, &spr_write_generic, | |
6127 | 0x00000000); | |
a750fc0b JM |
6128 | /* Hardware implementation registers */ |
6129 | /* XXX : not implemented */ | |
6130 | spr_register(env, SPR_HID0, "HID0", | |
6131 | SPR_NOACCESS, SPR_NOACCESS, | |
6132 | &spr_read_generic, &spr_write_generic, | |
6133 | 0x00000000); | |
6134 | /* XXX : not implemented */ | |
6135 | spr_register(env, SPR_HID1, "HID1", | |
6136 | SPR_NOACCESS, SPR_NOACCESS, | |
6137 | &spr_read_generic, &spr_write_generic, | |
6138 | 0x00000000); | |
6139 | /* XXX : not implemented */ | |
bd928eba | 6140 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
6141 | SPR_NOACCESS, SPR_NOACCESS, |
6142 | &spr_read_generic, &spr_write_generic, | |
6143 | 0x00000000); | |
6144 | /* Memory management */ | |
6145 | gen_low_BATs(env); | |
6146 | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ | |
6147 | gen_high_BATs(env); | |
bd928eba | 6148 | init_excp_7x0(env); |
d63001d1 JM |
6149 | env->dcache_line_size = 32; |
6150 | env->icache_line_size = 32; | |
a750fc0b | 6151 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6152 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
6153 | } |
6154 | ||
7856e3a4 AF |
6155 | POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) |
6156 | { | |
ca5dff0a | 6157 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6158 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6159 | ||
ca5dff0a | 6160 | dc->desc = "PowerPC 750FX"; |
7856e3a4 AF |
6161 | pcc->init_proc = init_proc_750fx; |
6162 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6163 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6164 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6165 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
6166 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6167 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6168 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6169 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
6170 | pcc->msr_mask = (1ull << MSR_POW) | |
6171 | (1ull << MSR_ILE) | | |
6172 | (1ull << MSR_EE) | | |
6173 | (1ull << MSR_PR) | | |
6174 | (1ull << MSR_FP) | | |
6175 | (1ull << MSR_ME) | | |
6176 | (1ull << MSR_FE0) | | |
6177 | (1ull << MSR_SE) | | |
6178 | (1ull << MSR_DE) | | |
6179 | (1ull << MSR_FE1) | | |
6180 | (1ull << MSR_EP) | | |
6181 | (1ull << MSR_IR) | | |
6182 | (1ull << MSR_DR) | | |
6183 | (1ull << MSR_PMM) | | |
6184 | (1ull << MSR_RI) | | |
6185 | (1ull << MSR_LE); | |
ba9fd9f1 | 6186 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
6187 | #if defined(CONFIG_SOFTMMU) |
6188 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6189 | #endif | |
ba9fd9f1 AF |
6190 | pcc->excp_model = POWERPC_EXCP_7x0; |
6191 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6192 | pcc->bfd_mach = bfd_mach_ppc_750; | |
6193 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
6194 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6195 | } |
6196 | ||
bd928eba JM |
6197 | static void init_proc_750gx (CPUPPCState *env) |
6198 | { | |
6199 | gen_spr_ne_601(env); | |
6200 | gen_spr_7xx(env); | |
6201 | /* XXX : not implemented (XXX: different from 750fx) */ | |
6202 | spr_register(env, SPR_L2CR, "L2CR", | |
6203 | SPR_NOACCESS, SPR_NOACCESS, | |
9633fcc6 | 6204 | &spr_read_generic, spr_access_nop, |
bd928eba JM |
6205 | 0x00000000); |
6206 | /* Time base */ | |
6207 | gen_tbl(env); | |
6208 | /* Thermal management */ | |
6209 | gen_spr_thrm(env); | |
6210 | /* XXX : not implemented */ | |
6211 | spr_register(env, SPR_750_THRM4, "THRM4", | |
6212 | SPR_NOACCESS, SPR_NOACCESS, | |
6213 | &spr_read_generic, &spr_write_generic, | |
6214 | 0x00000000); | |
6215 | /* Hardware implementation registers */ | |
6216 | /* XXX : not implemented (XXX: different from 750fx) */ | |
6217 | spr_register(env, SPR_HID0, "HID0", | |
6218 | SPR_NOACCESS, SPR_NOACCESS, | |
6219 | &spr_read_generic, &spr_write_generic, | |
6220 | 0x00000000); | |
6221 | /* XXX : not implemented */ | |
6222 | spr_register(env, SPR_HID1, "HID1", | |
6223 | SPR_NOACCESS, SPR_NOACCESS, | |
6224 | &spr_read_generic, &spr_write_generic, | |
6225 | 0x00000000); | |
6226 | /* XXX : not implemented (XXX: different from 750fx) */ | |
6227 | spr_register(env, SPR_750FX_HID2, "HID2", | |
6228 | SPR_NOACCESS, SPR_NOACCESS, | |
6229 | &spr_read_generic, &spr_write_generic, | |
6230 | 0x00000000); | |
6231 | /* Memory management */ | |
6232 | gen_low_BATs(env); | |
6233 | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ | |
6234 | gen_high_BATs(env); | |
6235 | init_excp_7x0(env); | |
6236 | env->dcache_line_size = 32; | |
6237 | env->icache_line_size = 32; | |
6238 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 6239 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
bd928eba JM |
6240 | } |
6241 | ||
7856e3a4 AF |
6242 | POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) |
6243 | { | |
ca5dff0a | 6244 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6245 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6246 | ||
ca5dff0a | 6247 | dc->desc = "PowerPC 750GX"; |
7856e3a4 AF |
6248 | pcc->init_proc = init_proc_750gx; |
6249 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6250 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6251 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6252 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
6253 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6254 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6255 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6256 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
6257 | pcc->msr_mask = (1ull << MSR_POW) | |
6258 | (1ull << MSR_ILE) | | |
6259 | (1ull << MSR_EE) | | |
6260 | (1ull << MSR_PR) | | |
6261 | (1ull << MSR_FP) | | |
6262 | (1ull << MSR_ME) | | |
6263 | (1ull << MSR_FE0) | | |
6264 | (1ull << MSR_SE) | | |
6265 | (1ull << MSR_DE) | | |
6266 | (1ull << MSR_FE1) | | |
6267 | (1ull << MSR_EP) | | |
6268 | (1ull << MSR_IR) | | |
6269 | (1ull << MSR_DR) | | |
6270 | (1ull << MSR_PMM) | | |
6271 | (1ull << MSR_RI) | | |
6272 | (1ull << MSR_LE); | |
ba9fd9f1 | 6273 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
6274 | #if defined(CONFIG_SOFTMMU) |
6275 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6276 | #endif | |
ba9fd9f1 AF |
6277 | pcc->excp_model = POWERPC_EXCP_7x0; |
6278 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6279 | pcc->bfd_mach = bfd_mach_ppc_750; | |
6280 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
6281 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6282 | } |
6283 | ||
bd928eba JM |
6284 | static void init_proc_745 (CPUPPCState *env) |
6285 | { | |
6286 | gen_spr_ne_601(env); | |
6287 | gen_spr_7xx(env); | |
6288 | gen_spr_G2_755(env); | |
6289 | /* Time base */ | |
6290 | gen_tbl(env); | |
6291 | /* Thermal management */ | |
6292 | gen_spr_thrm(env); | |
6293 | /* Hardware implementation registers */ | |
6294 | /* XXX : not implemented */ | |
6295 | spr_register(env, SPR_HID0, "HID0", | |
6296 | SPR_NOACCESS, SPR_NOACCESS, | |
6297 | &spr_read_generic, &spr_write_generic, | |
6298 | 0x00000000); | |
6299 | /* XXX : not implemented */ | |
6300 | spr_register(env, SPR_HID1, "HID1", | |
6301 | SPR_NOACCESS, SPR_NOACCESS, | |
6302 | &spr_read_generic, &spr_write_generic, | |
6303 | 0x00000000); | |
6304 | /* XXX : not implemented */ | |
6305 | spr_register(env, SPR_HID2, "HID2", | |
6306 | SPR_NOACCESS, SPR_NOACCESS, | |
6307 | &spr_read_generic, &spr_write_generic, | |
6308 | 0x00000000); | |
6309 | /* Memory management */ | |
6310 | gen_low_BATs(env); | |
6311 | gen_high_BATs(env); | |
6312 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
6313 | init_excp_7x5(env); | |
6314 | env->dcache_line_size = 32; | |
6315 | env->icache_line_size = 32; | |
6316 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 6317 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
bd928eba JM |
6318 | } |
6319 | ||
7856e3a4 AF |
6320 | POWERPC_FAMILY(745)(ObjectClass *oc, void *data) |
6321 | { | |
ca5dff0a | 6322 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6323 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6324 | ||
ca5dff0a | 6325 | dc->desc = "PowerPC 745"; |
7856e3a4 AF |
6326 | pcc->init_proc = init_proc_745; |
6327 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6328 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6329 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6330 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
6331 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6332 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6333 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
6334 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
6335 | pcc->msr_mask = (1ull << MSR_POW) | |
6336 | (1ull << MSR_ILE) | | |
6337 | (1ull << MSR_EE) | | |
6338 | (1ull << MSR_PR) | | |
6339 | (1ull << MSR_FP) | | |
6340 | (1ull << MSR_ME) | | |
6341 | (1ull << MSR_FE0) | | |
6342 | (1ull << MSR_SE) | | |
6343 | (1ull << MSR_DE) | | |
6344 | (1ull << MSR_FE1) | | |
6345 | (1ull << MSR_EP) | | |
6346 | (1ull << MSR_IR) | | |
6347 | (1ull << MSR_DR) | | |
6348 | (1ull << MSR_PMM) | | |
6349 | (1ull << MSR_RI) | | |
6350 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
6351 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
6352 | pcc->excp_model = POWERPC_EXCP_7x5; | |
6353 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6354 | pcc->bfd_mach = bfd_mach_ppc_750; | |
6355 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
6356 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6357 | } |
6358 | ||
bd928eba | 6359 | static void init_proc_755 (CPUPPCState *env) |
a750fc0b JM |
6360 | { |
6361 | gen_spr_ne_601(env); | |
bd928eba | 6362 | gen_spr_7xx(env); |
a750fc0b JM |
6363 | gen_spr_G2_755(env); |
6364 | /* Time base */ | |
6365 | gen_tbl(env); | |
6366 | /* L2 cache control */ | |
6367 | /* XXX : not implemented */ | |
bd928eba | 6368 | spr_register(env, SPR_L2CR, "L2CR", |
a750fc0b | 6369 | SPR_NOACCESS, SPR_NOACCESS, |
9633fcc6 | 6370 | &spr_read_generic, spr_access_nop, |
a750fc0b JM |
6371 | 0x00000000); |
6372 | /* XXX : not implemented */ | |
6373 | spr_register(env, SPR_L2PMCR, "L2PMCR", | |
6374 | SPR_NOACCESS, SPR_NOACCESS, | |
6375 | &spr_read_generic, &spr_write_generic, | |
6376 | 0x00000000); | |
bd928eba JM |
6377 | /* Thermal management */ |
6378 | gen_spr_thrm(env); | |
a750fc0b JM |
6379 | /* Hardware implementation registers */ |
6380 | /* XXX : not implemented */ | |
6381 | spr_register(env, SPR_HID0, "HID0", | |
6382 | SPR_NOACCESS, SPR_NOACCESS, | |
6383 | &spr_read_generic, &spr_write_generic, | |
6384 | 0x00000000); | |
6385 | /* XXX : not implemented */ | |
6386 | spr_register(env, SPR_HID1, "HID1", | |
6387 | SPR_NOACCESS, SPR_NOACCESS, | |
6388 | &spr_read_generic, &spr_write_generic, | |
6389 | 0x00000000); | |
6390 | /* XXX : not implemented */ | |
6391 | spr_register(env, SPR_HID2, "HID2", | |
6392 | SPR_NOACCESS, SPR_NOACCESS, | |
6393 | &spr_read_generic, &spr_write_generic, | |
6394 | 0x00000000); | |
6395 | /* Memory management */ | |
6396 | gen_low_BATs(env); | |
6397 | gen_high_BATs(env); | |
6398 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
7a3a6927 | 6399 | init_excp_7x5(env); |
d63001d1 JM |
6400 | env->dcache_line_size = 32; |
6401 | env->icache_line_size = 32; | |
a750fc0b | 6402 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6403 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
6404 | } |
6405 | ||
7856e3a4 AF |
6406 | POWERPC_FAMILY(755)(ObjectClass *oc, void *data) |
6407 | { | |
ca5dff0a | 6408 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6409 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6410 | ||
ca5dff0a | 6411 | dc->desc = "PowerPC 755"; |
7856e3a4 AF |
6412 | pcc->init_proc = init_proc_755; |
6413 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6414 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6415 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6416 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
6417 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6418 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6419 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
6420 | PPC_SEGMENT | PPC_EXTERN; | |
9df5a466 TM |
6421 | pcc->msr_mask = (1ull << MSR_POW) | |
6422 | (1ull << MSR_ILE) | | |
6423 | (1ull << MSR_EE) | | |
6424 | (1ull << MSR_PR) | | |
6425 | (1ull << MSR_FP) | | |
6426 | (1ull << MSR_ME) | | |
6427 | (1ull << MSR_FE0) | | |
6428 | (1ull << MSR_SE) | | |
6429 | (1ull << MSR_DE) | | |
6430 | (1ull << MSR_FE1) | | |
6431 | (1ull << MSR_EP) | | |
6432 | (1ull << MSR_IR) | | |
6433 | (1ull << MSR_DR) | | |
6434 | (1ull << MSR_PMM) | | |
6435 | (1ull << MSR_RI) | | |
6436 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
6437 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; |
6438 | pcc->excp_model = POWERPC_EXCP_7x5; | |
6439 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6440 | pcc->bfd_mach = bfd_mach_ppc_750; | |
6441 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
6442 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6443 | } |
6444 | ||
a750fc0b JM |
6445 | static void init_proc_7400 (CPUPPCState *env) |
6446 | { | |
6447 | gen_spr_ne_601(env); | |
6448 | gen_spr_7xx(env); | |
6449 | /* Time base */ | |
6450 | gen_tbl(env); | |
6451 | /* 74xx specific SPR */ | |
6452 | gen_spr_74xx(env); | |
4e777442 JM |
6453 | /* XXX : not implemented */ |
6454 | spr_register(env, SPR_UBAMR, "UBAMR", | |
6455 | &spr_read_ureg, SPR_NOACCESS, | |
6456 | &spr_read_ureg, SPR_NOACCESS, | |
6457 | 0x00000000); | |
6458 | /* XXX: this seems not implemented on all revisions. */ | |
6459 | /* XXX : not implemented */ | |
6460 | spr_register(env, SPR_MSSCR1, "MSSCR1", | |
6461 | SPR_NOACCESS, SPR_NOACCESS, | |
6462 | &spr_read_generic, &spr_write_generic, | |
6463 | 0x00000000); | |
a750fc0b JM |
6464 | /* Thermal management */ |
6465 | gen_spr_thrm(env); | |
6466 | /* Memory management */ | |
6467 | gen_low_BATs(env); | |
e1833e1f | 6468 | init_excp_7400(env); |
d63001d1 JM |
6469 | env->dcache_line_size = 32; |
6470 | env->icache_line_size = 32; | |
a750fc0b | 6471 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6472 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
6473 | } |
6474 | ||
7856e3a4 AF |
6475 | POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) |
6476 | { | |
ca5dff0a | 6477 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6478 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6479 | ||
ca5dff0a | 6480 | dc->desc = "PowerPC 7400 (aka G4)"; |
7856e3a4 AF |
6481 | pcc->init_proc = init_proc_7400; |
6482 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6483 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6484 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6485 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6486 | PPC_FLOAT_STFIWX | | |
6487 | PPC_CACHE | PPC_CACHE_ICBI | | |
6488 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6489 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6490 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6491 | PPC_MEM_TLBIA | | |
6492 | PPC_SEGMENT | PPC_EXTERN | | |
6493 | PPC_ALTIVEC; | |
9df5a466 TM |
6494 | pcc->msr_mask = (1ull << MSR_VR) | |
6495 | (1ull << MSR_POW) | | |
6496 | (1ull << MSR_ILE) | | |
6497 | (1ull << MSR_EE) | | |
6498 | (1ull << MSR_PR) | | |
6499 | (1ull << MSR_FP) | | |
6500 | (1ull << MSR_ME) | | |
6501 | (1ull << MSR_FE0) | | |
6502 | (1ull << MSR_SE) | | |
6503 | (1ull << MSR_DE) | | |
6504 | (1ull << MSR_FE1) | | |
6505 | (1ull << MSR_EP) | | |
6506 | (1ull << MSR_IR) | | |
6507 | (1ull << MSR_DR) | | |
6508 | (1ull << MSR_PMM) | | |
6509 | (1ull << MSR_RI) | | |
6510 | (1ull << MSR_LE); | |
ba9fd9f1 | 6511 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
6512 | #if defined(CONFIG_SOFTMMU) |
6513 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6514 | #endif | |
ba9fd9f1 AF |
6515 | pcc->excp_model = POWERPC_EXCP_74xx; |
6516 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6517 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6518 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6519 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6520 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6521 | } |
6522 | ||
a750fc0b JM |
6523 | static void init_proc_7410 (CPUPPCState *env) |
6524 | { | |
6525 | gen_spr_ne_601(env); | |
6526 | gen_spr_7xx(env); | |
6527 | /* Time base */ | |
6528 | gen_tbl(env); | |
6529 | /* 74xx specific SPR */ | |
6530 | gen_spr_74xx(env); | |
4e777442 JM |
6531 | /* XXX : not implemented */ |
6532 | spr_register(env, SPR_UBAMR, "UBAMR", | |
6533 | &spr_read_ureg, SPR_NOACCESS, | |
6534 | &spr_read_ureg, SPR_NOACCESS, | |
6535 | 0x00000000); | |
a750fc0b JM |
6536 | /* Thermal management */ |
6537 | gen_spr_thrm(env); | |
6538 | /* L2PMCR */ | |
6539 | /* XXX : not implemented */ | |
6540 | spr_register(env, SPR_L2PMCR, "L2PMCR", | |
6541 | SPR_NOACCESS, SPR_NOACCESS, | |
6542 | &spr_read_generic, &spr_write_generic, | |
6543 | 0x00000000); | |
6544 | /* LDSTDB */ | |
6545 | /* XXX : not implemented */ | |
6546 | spr_register(env, SPR_LDSTDB, "LDSTDB", | |
6547 | SPR_NOACCESS, SPR_NOACCESS, | |
6548 | &spr_read_generic, &spr_write_generic, | |
6549 | 0x00000000); | |
6550 | /* Memory management */ | |
6551 | gen_low_BATs(env); | |
e1833e1f | 6552 | init_excp_7400(env); |
d63001d1 JM |
6553 | env->dcache_line_size = 32; |
6554 | env->icache_line_size = 32; | |
a750fc0b | 6555 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6556 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b JM |
6557 | } |
6558 | ||
7856e3a4 AF |
6559 | POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) |
6560 | { | |
ca5dff0a | 6561 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6562 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6563 | ||
ca5dff0a | 6564 | dc->desc = "PowerPC 7410 (aka G4)"; |
7856e3a4 AF |
6565 | pcc->init_proc = init_proc_7410; |
6566 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
6567 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6568 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6569 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6570 | PPC_FLOAT_STFIWX | | |
6571 | PPC_CACHE | PPC_CACHE_ICBI | | |
6572 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6573 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6574 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6575 | PPC_MEM_TLBIA | | |
6576 | PPC_SEGMENT | PPC_EXTERN | | |
6577 | PPC_ALTIVEC; | |
9df5a466 TM |
6578 | pcc->msr_mask = (1ull << MSR_VR) | |
6579 | (1ull << MSR_POW) | | |
6580 | (1ull << MSR_ILE) | | |
6581 | (1ull << MSR_EE) | | |
6582 | (1ull << MSR_PR) | | |
6583 | (1ull << MSR_FP) | | |
6584 | (1ull << MSR_ME) | | |
6585 | (1ull << MSR_FE0) | | |
6586 | (1ull << MSR_SE) | | |
6587 | (1ull << MSR_DE) | | |
6588 | (1ull << MSR_FE1) | | |
6589 | (1ull << MSR_EP) | | |
6590 | (1ull << MSR_IR) | | |
6591 | (1ull << MSR_DR) | | |
6592 | (1ull << MSR_PMM) | | |
6593 | (1ull << MSR_RI) | | |
6594 | (1ull << MSR_LE); | |
ba9fd9f1 | 6595 | pcc->mmu_model = POWERPC_MMU_32B; |
b632a148 DG |
6596 | #if defined(CONFIG_SOFTMMU) |
6597 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6598 | #endif | |
ba9fd9f1 AF |
6599 | pcc->excp_model = POWERPC_EXCP_74xx; |
6600 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6601 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6602 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6603 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6604 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6605 | } |
6606 | ||
a750fc0b JM |
6607 | static void init_proc_7440 (CPUPPCState *env) |
6608 | { | |
6609 | gen_spr_ne_601(env); | |
6610 | gen_spr_7xx(env); | |
6611 | /* Time base */ | |
6612 | gen_tbl(env); | |
6613 | /* 74xx specific SPR */ | |
6614 | gen_spr_74xx(env); | |
4e777442 JM |
6615 | /* XXX : not implemented */ |
6616 | spr_register(env, SPR_UBAMR, "UBAMR", | |
6617 | &spr_read_ureg, SPR_NOACCESS, | |
6618 | &spr_read_ureg, SPR_NOACCESS, | |
6619 | 0x00000000); | |
a750fc0b JM |
6620 | /* LDSTCR */ |
6621 | /* XXX : not implemented */ | |
6622 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6623 | SPR_NOACCESS, SPR_NOACCESS, | |
6624 | &spr_read_generic, &spr_write_generic, | |
6625 | 0x00000000); | |
6626 | /* ICTRL */ | |
6627 | /* XXX : not implemented */ | |
6628 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6629 | SPR_NOACCESS, SPR_NOACCESS, | |
6630 | &spr_read_generic, &spr_write_generic, | |
6631 | 0x00000000); | |
6632 | /* MSSSR0 */ | |
578bb252 | 6633 | /* XXX : not implemented */ |
a750fc0b JM |
6634 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
6635 | SPR_NOACCESS, SPR_NOACCESS, | |
6636 | &spr_read_generic, &spr_write_generic, | |
6637 | 0x00000000); | |
6638 | /* PMC */ | |
6639 | /* XXX : not implemented */ | |
cb8b8bf8 | 6640 | spr_register(env, SPR_7XX_PMC5, "PMC5", |
a750fc0b JM |
6641 | SPR_NOACCESS, SPR_NOACCESS, |
6642 | &spr_read_generic, &spr_write_generic, | |
6643 | 0x00000000); | |
578bb252 | 6644 | /* XXX : not implemented */ |
cb8b8bf8 | 6645 | spr_register(env, SPR_7XX_UPMC5, "UPMC5", |
a750fc0b JM |
6646 | &spr_read_ureg, SPR_NOACCESS, |
6647 | &spr_read_ureg, SPR_NOACCESS, | |
6648 | 0x00000000); | |
578bb252 | 6649 | /* XXX : not implemented */ |
cb8b8bf8 | 6650 | spr_register(env, SPR_7XX_PMC6, "PMC6", |
a750fc0b JM |
6651 | SPR_NOACCESS, SPR_NOACCESS, |
6652 | &spr_read_generic, &spr_write_generic, | |
6653 | 0x00000000); | |
578bb252 | 6654 | /* XXX : not implemented */ |
cb8b8bf8 | 6655 | spr_register(env, SPR_7XX_UPMC6, "UPMC6", |
a750fc0b JM |
6656 | &spr_read_ureg, SPR_NOACCESS, |
6657 | &spr_read_ureg, SPR_NOACCESS, | |
6658 | 0x00000000); | |
6659 | /* Memory management */ | |
6660 | gen_low_BATs(env); | |
578bb252 | 6661 | gen_74xx_soft_tlb(env, 128, 2); |
1c27f8fb | 6662 | init_excp_7450(env); |
d63001d1 JM |
6663 | env->dcache_line_size = 32; |
6664 | env->icache_line_size = 32; | |
a750fc0b | 6665 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6666 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b | 6667 | } |
a750fc0b | 6668 | |
7856e3a4 AF |
6669 | POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) |
6670 | { | |
ca5dff0a | 6671 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6672 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6673 | ||
ca5dff0a | 6674 | dc->desc = "PowerPC 7440 (aka G4)"; |
7856e3a4 AF |
6675 | pcc->init_proc = init_proc_7440; |
6676 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6677 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6678 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6679 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6680 | PPC_FLOAT_STFIWX | | |
6681 | PPC_CACHE | PPC_CACHE_ICBI | | |
6682 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6683 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6684 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6685 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6686 | PPC_SEGMENT | PPC_EXTERN | | |
6687 | PPC_ALTIVEC; | |
9df5a466 TM |
6688 | pcc->msr_mask = (1ull << MSR_VR) | |
6689 | (1ull << MSR_POW) | | |
6690 | (1ull << MSR_ILE) | | |
6691 | (1ull << MSR_EE) | | |
6692 | (1ull << MSR_PR) | | |
6693 | (1ull << MSR_FP) | | |
6694 | (1ull << MSR_ME) | | |
6695 | (1ull << MSR_FE0) | | |
6696 | (1ull << MSR_SE) | | |
6697 | (1ull << MSR_DE) | | |
6698 | (1ull << MSR_FE1) | | |
6699 | (1ull << MSR_EP) | | |
6700 | (1ull << MSR_IR) | | |
6701 | (1ull << MSR_DR) | | |
6702 | (1ull << MSR_PMM) | | |
6703 | (1ull << MSR_RI) | | |
6704 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
6705 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; |
6706 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6707 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6708 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6709 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6710 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6711 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6712 | } |
6713 | ||
a750fc0b JM |
6714 | static void init_proc_7450 (CPUPPCState *env) |
6715 | { | |
6716 | gen_spr_ne_601(env); | |
6717 | gen_spr_7xx(env); | |
6718 | /* Time base */ | |
6719 | gen_tbl(env); | |
6720 | /* 74xx specific SPR */ | |
6721 | gen_spr_74xx(env); | |
6722 | /* Level 3 cache control */ | |
6723 | gen_l3_ctrl(env); | |
4e777442 JM |
6724 | /* L3ITCR1 */ |
6725 | /* XXX : not implemented */ | |
6726 | spr_register(env, SPR_L3ITCR1, "L3ITCR1", | |
6727 | SPR_NOACCESS, SPR_NOACCESS, | |
6728 | &spr_read_generic, &spr_write_generic, | |
6729 | 0x00000000); | |
6730 | /* L3ITCR2 */ | |
6731 | /* XXX : not implemented */ | |
6732 | spr_register(env, SPR_L3ITCR2, "L3ITCR2", | |
6733 | SPR_NOACCESS, SPR_NOACCESS, | |
6734 | &spr_read_generic, &spr_write_generic, | |
6735 | 0x00000000); | |
6736 | /* L3ITCR3 */ | |
6737 | /* XXX : not implemented */ | |
6738 | spr_register(env, SPR_L3ITCR3, "L3ITCR3", | |
6739 | SPR_NOACCESS, SPR_NOACCESS, | |
6740 | &spr_read_generic, &spr_write_generic, | |
6741 | 0x00000000); | |
6742 | /* L3OHCR */ | |
6743 | /* XXX : not implemented */ | |
6744 | spr_register(env, SPR_L3OHCR, "L3OHCR", | |
6745 | SPR_NOACCESS, SPR_NOACCESS, | |
6746 | &spr_read_generic, &spr_write_generic, | |
6747 | 0x00000000); | |
6748 | /* XXX : not implemented */ | |
6749 | spr_register(env, SPR_UBAMR, "UBAMR", | |
6750 | &spr_read_ureg, SPR_NOACCESS, | |
6751 | &spr_read_ureg, SPR_NOACCESS, | |
6752 | 0x00000000); | |
a750fc0b JM |
6753 | /* LDSTCR */ |
6754 | /* XXX : not implemented */ | |
6755 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6756 | SPR_NOACCESS, SPR_NOACCESS, | |
6757 | &spr_read_generic, &spr_write_generic, | |
6758 | 0x00000000); | |
6759 | /* ICTRL */ | |
6760 | /* XXX : not implemented */ | |
6761 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6762 | SPR_NOACCESS, SPR_NOACCESS, | |
6763 | &spr_read_generic, &spr_write_generic, | |
6764 | 0x00000000); | |
6765 | /* MSSSR0 */ | |
578bb252 | 6766 | /* XXX : not implemented */ |
a750fc0b JM |
6767 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
6768 | SPR_NOACCESS, SPR_NOACCESS, | |
6769 | &spr_read_generic, &spr_write_generic, | |
6770 | 0x00000000); | |
6771 | /* PMC */ | |
6772 | /* XXX : not implemented */ | |
cb8b8bf8 | 6773 | spr_register(env, SPR_7XX_PMC5, "PMC5", |
a750fc0b JM |
6774 | SPR_NOACCESS, SPR_NOACCESS, |
6775 | &spr_read_generic, &spr_write_generic, | |
6776 | 0x00000000); | |
578bb252 | 6777 | /* XXX : not implemented */ |
cb8b8bf8 | 6778 | spr_register(env, SPR_7XX_UPMC5, "UPMC5", |
a750fc0b JM |
6779 | &spr_read_ureg, SPR_NOACCESS, |
6780 | &spr_read_ureg, SPR_NOACCESS, | |
6781 | 0x00000000); | |
578bb252 | 6782 | /* XXX : not implemented */ |
cb8b8bf8 | 6783 | spr_register(env, SPR_7XX_PMC6, "PMC6", |
a750fc0b JM |
6784 | SPR_NOACCESS, SPR_NOACCESS, |
6785 | &spr_read_generic, &spr_write_generic, | |
6786 | 0x00000000); | |
578bb252 | 6787 | /* XXX : not implemented */ |
cb8b8bf8 | 6788 | spr_register(env, SPR_7XX_UPMC6, "UPMC6", |
a750fc0b JM |
6789 | &spr_read_ureg, SPR_NOACCESS, |
6790 | &spr_read_ureg, SPR_NOACCESS, | |
6791 | 0x00000000); | |
6792 | /* Memory management */ | |
6793 | gen_low_BATs(env); | |
578bb252 | 6794 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 6795 | init_excp_7450(env); |
d63001d1 JM |
6796 | env->dcache_line_size = 32; |
6797 | env->icache_line_size = 32; | |
a750fc0b | 6798 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6799 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b | 6800 | } |
a750fc0b | 6801 | |
7856e3a4 AF |
6802 | POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) |
6803 | { | |
ca5dff0a | 6804 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6805 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6806 | ||
ca5dff0a | 6807 | dc->desc = "PowerPC 7450 (aka G4)"; |
7856e3a4 AF |
6808 | pcc->init_proc = init_proc_7450; |
6809 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6810 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6811 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6812 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6813 | PPC_FLOAT_STFIWX | | |
6814 | PPC_CACHE | PPC_CACHE_ICBI | | |
6815 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6816 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6817 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6818 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6819 | PPC_SEGMENT | PPC_EXTERN | | |
6820 | PPC_ALTIVEC; | |
9df5a466 TM |
6821 | pcc->msr_mask = (1ull << MSR_VR) | |
6822 | (1ull << MSR_POW) | | |
6823 | (1ull << MSR_ILE) | | |
6824 | (1ull << MSR_EE) | | |
6825 | (1ull << MSR_PR) | | |
6826 | (1ull << MSR_FP) | | |
6827 | (1ull << MSR_ME) | | |
6828 | (1ull << MSR_FE0) | | |
6829 | (1ull << MSR_SE) | | |
6830 | (1ull << MSR_DE) | | |
6831 | (1ull << MSR_FE1) | | |
6832 | (1ull << MSR_EP) | | |
6833 | (1ull << MSR_IR) | | |
6834 | (1ull << MSR_DR) | | |
6835 | (1ull << MSR_PMM) | | |
6836 | (1ull << MSR_RI) | | |
6837 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
6838 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; |
6839 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6840 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6841 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6842 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6843 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6844 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6845 | } |
6846 | ||
a750fc0b JM |
6847 | static void init_proc_7445 (CPUPPCState *env) |
6848 | { | |
6849 | gen_spr_ne_601(env); | |
6850 | gen_spr_7xx(env); | |
6851 | /* Time base */ | |
6852 | gen_tbl(env); | |
6853 | /* 74xx specific SPR */ | |
6854 | gen_spr_74xx(env); | |
6855 | /* LDSTCR */ | |
6856 | /* XXX : not implemented */ | |
6857 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6858 | SPR_NOACCESS, SPR_NOACCESS, | |
6859 | &spr_read_generic, &spr_write_generic, | |
6860 | 0x00000000); | |
6861 | /* ICTRL */ | |
6862 | /* XXX : not implemented */ | |
6863 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6864 | SPR_NOACCESS, SPR_NOACCESS, | |
6865 | &spr_read_generic, &spr_write_generic, | |
6866 | 0x00000000); | |
6867 | /* MSSSR0 */ | |
578bb252 | 6868 | /* XXX : not implemented */ |
a750fc0b JM |
6869 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
6870 | SPR_NOACCESS, SPR_NOACCESS, | |
6871 | &spr_read_generic, &spr_write_generic, | |
6872 | 0x00000000); | |
6873 | /* PMC */ | |
6874 | /* XXX : not implemented */ | |
cb8b8bf8 | 6875 | spr_register(env, SPR_7XX_PMC5, "PMC5", |
a750fc0b JM |
6876 | SPR_NOACCESS, SPR_NOACCESS, |
6877 | &spr_read_generic, &spr_write_generic, | |
6878 | 0x00000000); | |
578bb252 | 6879 | /* XXX : not implemented */ |
cb8b8bf8 | 6880 | spr_register(env, SPR_7XX_UPMC5, "UPMC5", |
a750fc0b JM |
6881 | &spr_read_ureg, SPR_NOACCESS, |
6882 | &spr_read_ureg, SPR_NOACCESS, | |
6883 | 0x00000000); | |
578bb252 | 6884 | /* XXX : not implemented */ |
cb8b8bf8 | 6885 | spr_register(env, SPR_7XX_PMC6, "PMC6", |
a750fc0b JM |
6886 | SPR_NOACCESS, SPR_NOACCESS, |
6887 | &spr_read_generic, &spr_write_generic, | |
6888 | 0x00000000); | |
578bb252 | 6889 | /* XXX : not implemented */ |
cb8b8bf8 | 6890 | spr_register(env, SPR_7XX_UPMC6, "UPMC6", |
a750fc0b JM |
6891 | &spr_read_ureg, SPR_NOACCESS, |
6892 | &spr_read_ureg, SPR_NOACCESS, | |
6893 | 0x00000000); | |
6894 | /* SPRGs */ | |
6895 | spr_register(env, SPR_SPRG4, "SPRG4", | |
6896 | SPR_NOACCESS, SPR_NOACCESS, | |
6897 | &spr_read_generic, &spr_write_generic, | |
6898 | 0x00000000); | |
6899 | spr_register(env, SPR_USPRG4, "USPRG4", | |
6900 | &spr_read_ureg, SPR_NOACCESS, | |
6901 | &spr_read_ureg, SPR_NOACCESS, | |
6902 | 0x00000000); | |
6903 | spr_register(env, SPR_SPRG5, "SPRG5", | |
6904 | SPR_NOACCESS, SPR_NOACCESS, | |
6905 | &spr_read_generic, &spr_write_generic, | |
6906 | 0x00000000); | |
6907 | spr_register(env, SPR_USPRG5, "USPRG5", | |
6908 | &spr_read_ureg, SPR_NOACCESS, | |
6909 | &spr_read_ureg, SPR_NOACCESS, | |
6910 | 0x00000000); | |
6911 | spr_register(env, SPR_SPRG6, "SPRG6", | |
6912 | SPR_NOACCESS, SPR_NOACCESS, | |
6913 | &spr_read_generic, &spr_write_generic, | |
6914 | 0x00000000); | |
6915 | spr_register(env, SPR_USPRG6, "USPRG6", | |
6916 | &spr_read_ureg, SPR_NOACCESS, | |
6917 | &spr_read_ureg, SPR_NOACCESS, | |
6918 | 0x00000000); | |
6919 | spr_register(env, SPR_SPRG7, "SPRG7", | |
6920 | SPR_NOACCESS, SPR_NOACCESS, | |
6921 | &spr_read_generic, &spr_write_generic, | |
6922 | 0x00000000); | |
6923 | spr_register(env, SPR_USPRG7, "USPRG7", | |
6924 | &spr_read_ureg, SPR_NOACCESS, | |
6925 | &spr_read_ureg, SPR_NOACCESS, | |
6926 | 0x00000000); | |
6927 | /* Memory management */ | |
6928 | gen_low_BATs(env); | |
6929 | gen_high_BATs(env); | |
578bb252 | 6930 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 6931 | init_excp_7450(env); |
d63001d1 JM |
6932 | env->dcache_line_size = 32; |
6933 | env->icache_line_size = 32; | |
a750fc0b | 6934 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 6935 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b | 6936 | } |
a750fc0b | 6937 | |
7856e3a4 AF |
6938 | POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) |
6939 | { | |
ca5dff0a | 6940 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6941 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6942 | ||
ca5dff0a | 6943 | dc->desc = "PowerPC 7445 (aka G4)"; |
7856e3a4 AF |
6944 | pcc->init_proc = init_proc_7445; |
6945 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6946 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6947 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6948 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6949 | PPC_FLOAT_STFIWX | | |
6950 | PPC_CACHE | PPC_CACHE_ICBI | | |
6951 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6952 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6953 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6954 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6955 | PPC_SEGMENT | PPC_EXTERN | | |
6956 | PPC_ALTIVEC; | |
9df5a466 TM |
6957 | pcc->msr_mask = (1ull << MSR_VR) | |
6958 | (1ull << MSR_POW) | | |
6959 | (1ull << MSR_ILE) | | |
6960 | (1ull << MSR_EE) | | |
6961 | (1ull << MSR_PR) | | |
6962 | (1ull << MSR_FP) | | |
6963 | (1ull << MSR_ME) | | |
6964 | (1ull << MSR_FE0) | | |
6965 | (1ull << MSR_SE) | | |
6966 | (1ull << MSR_DE) | | |
6967 | (1ull << MSR_FE1) | | |
6968 | (1ull << MSR_EP) | | |
6969 | (1ull << MSR_IR) | | |
6970 | (1ull << MSR_DR) | | |
6971 | (1ull << MSR_PMM) | | |
6972 | (1ull << MSR_RI) | | |
6973 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
6974 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; |
6975 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6976 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6977 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6978 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6979 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6980 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6981 | } |
6982 | ||
a750fc0b JM |
6983 | static void init_proc_7455 (CPUPPCState *env) |
6984 | { | |
6985 | gen_spr_ne_601(env); | |
6986 | gen_spr_7xx(env); | |
6987 | /* Time base */ | |
6988 | gen_tbl(env); | |
6989 | /* 74xx specific SPR */ | |
6990 | gen_spr_74xx(env); | |
6991 | /* Level 3 cache control */ | |
6992 | gen_l3_ctrl(env); | |
6993 | /* LDSTCR */ | |
6994 | /* XXX : not implemented */ | |
6995 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6996 | SPR_NOACCESS, SPR_NOACCESS, | |
6997 | &spr_read_generic, &spr_write_generic, | |
6998 | 0x00000000); | |
6999 | /* ICTRL */ | |
7000 | /* XXX : not implemented */ | |
7001 | spr_register(env, SPR_ICTRL, "ICTRL", | |
7002 | SPR_NOACCESS, SPR_NOACCESS, | |
7003 | &spr_read_generic, &spr_write_generic, | |
7004 | 0x00000000); | |
7005 | /* MSSSR0 */ | |
578bb252 | 7006 | /* XXX : not implemented */ |
a750fc0b JM |
7007 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
7008 | SPR_NOACCESS, SPR_NOACCESS, | |
7009 | &spr_read_generic, &spr_write_generic, | |
7010 | 0x00000000); | |
7011 | /* PMC */ | |
7012 | /* XXX : not implemented */ | |
cb8b8bf8 | 7013 | spr_register(env, SPR_7XX_PMC5, "PMC5", |
a750fc0b JM |
7014 | SPR_NOACCESS, SPR_NOACCESS, |
7015 | &spr_read_generic, &spr_write_generic, | |
7016 | 0x00000000); | |
578bb252 | 7017 | /* XXX : not implemented */ |
cb8b8bf8 | 7018 | spr_register(env, SPR_7XX_UPMC5, "UPMC5", |
a750fc0b JM |
7019 | &spr_read_ureg, SPR_NOACCESS, |
7020 | &spr_read_ureg, SPR_NOACCESS, | |
7021 | 0x00000000); | |
578bb252 | 7022 | /* XXX : not implemented */ |
cb8b8bf8 | 7023 | spr_register(env, SPR_7XX_PMC6, "PMC6", |
a750fc0b JM |
7024 | SPR_NOACCESS, SPR_NOACCESS, |
7025 | &spr_read_generic, &spr_write_generic, | |
7026 | 0x00000000); | |
578bb252 | 7027 | /* XXX : not implemented */ |
cb8b8bf8 | 7028 | spr_register(env, SPR_7XX_UPMC6, "UPMC6", |
a750fc0b JM |
7029 | &spr_read_ureg, SPR_NOACCESS, |
7030 | &spr_read_ureg, SPR_NOACCESS, | |
7031 | 0x00000000); | |
7032 | /* SPRGs */ | |
7033 | spr_register(env, SPR_SPRG4, "SPRG4", | |
7034 | SPR_NOACCESS, SPR_NOACCESS, | |
7035 | &spr_read_generic, &spr_write_generic, | |
7036 | 0x00000000); | |
7037 | spr_register(env, SPR_USPRG4, "USPRG4", | |
7038 | &spr_read_ureg, SPR_NOACCESS, | |
7039 | &spr_read_ureg, SPR_NOACCESS, | |
7040 | 0x00000000); | |
7041 | spr_register(env, SPR_SPRG5, "SPRG5", | |
7042 | SPR_NOACCESS, SPR_NOACCESS, | |
7043 | &spr_read_generic, &spr_write_generic, | |
7044 | 0x00000000); | |
7045 | spr_register(env, SPR_USPRG5, "USPRG5", | |
7046 | &spr_read_ureg, SPR_NOACCESS, | |
7047 | &spr_read_ureg, SPR_NOACCESS, | |
7048 | 0x00000000); | |
7049 | spr_register(env, SPR_SPRG6, "SPRG6", | |
7050 | SPR_NOACCESS, SPR_NOACCESS, | |
7051 | &spr_read_generic, &spr_write_generic, | |
7052 | 0x00000000); | |
7053 | spr_register(env, SPR_USPRG6, "USPRG6", | |
7054 | &spr_read_ureg, SPR_NOACCESS, | |
7055 | &spr_read_ureg, SPR_NOACCESS, | |
7056 | 0x00000000); | |
7057 | spr_register(env, SPR_SPRG7, "SPRG7", | |
7058 | SPR_NOACCESS, SPR_NOACCESS, | |
7059 | &spr_read_generic, &spr_write_generic, | |
7060 | 0x00000000); | |
7061 | spr_register(env, SPR_USPRG7, "USPRG7", | |
7062 | &spr_read_ureg, SPR_NOACCESS, | |
7063 | &spr_read_ureg, SPR_NOACCESS, | |
7064 | 0x00000000); | |
7065 | /* Memory management */ | |
7066 | gen_low_BATs(env); | |
7067 | gen_high_BATs(env); | |
578bb252 | 7068 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 7069 | init_excp_7450(env); |
d63001d1 JM |
7070 | env->dcache_line_size = 32; |
7071 | env->icache_line_size = 32; | |
a750fc0b | 7072 | /* Allocate hardware IRQ controller */ |
aa5a9e24 | 7073 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
a750fc0b | 7074 | } |
a750fc0b | 7075 | |
7856e3a4 AF |
7076 | POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) |
7077 | { | |
ca5dff0a | 7078 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
7079 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
7080 | ||
ca5dff0a | 7081 | dc->desc = "PowerPC 7455 (aka G4)"; |
7856e3a4 AF |
7082 | pcc->init_proc = init_proc_7455; |
7083 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
7084 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
7085 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
7086 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7087 | PPC_FLOAT_STFIWX | | |
7088 | PPC_CACHE | PPC_CACHE_ICBI | | |
7089 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
7090 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7091 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7092 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
7093 | PPC_SEGMENT | PPC_EXTERN | | |
7094 | PPC_ALTIVEC; | |
9df5a466 TM |
7095 | pcc->msr_mask = (1ull << MSR_VR) | |
7096 | (1ull << MSR_POW) | | |
7097 | (1ull << MSR_ILE) | | |
7098 | (1ull << MSR_EE) | | |
7099 | (1ull << MSR_PR) | | |
7100 | (1ull << MSR_FP) | | |
7101 | (1ull << MSR_ME) | | |
7102 | (1ull << MSR_FE0) | | |
7103 | (1ull << MSR_SE) | | |
7104 | (1ull << MSR_DE) | | |
7105 | (1ull << MSR_FE1) | | |
7106 | (1ull << MSR_EP) | | |
7107 | (1ull << MSR_IR) | | |
7108 | (1ull << MSR_DR) | | |
7109 | (1ull << MSR_PMM) | | |
7110 | (1ull << MSR_RI) | | |
7111 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
7112 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; |
7113 | pcc->excp_model = POWERPC_EXCP_74xx; | |
7114 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
7115 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
7116 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7117 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7118 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
7119 | } |
7120 | ||
4e777442 JM |
7121 | static void init_proc_7457 (CPUPPCState *env) |
7122 | { | |
7123 | gen_spr_ne_601(env); | |
7124 | gen_spr_7xx(env); | |
7125 | /* Time base */ | |
7126 | gen_tbl(env); | |
7127 | /* 74xx specific SPR */ | |
7128 | gen_spr_74xx(env); | |
7129 | /* Level 3 cache control */ | |
7130 | gen_l3_ctrl(env); | |
7131 | /* L3ITCR1 */ | |
7132 | /* XXX : not implemented */ | |
7133 | spr_register(env, SPR_L3ITCR1, "L3ITCR1", | |
7134 | SPR_NOACCESS, SPR_NOACCESS, | |
7135 | &spr_read_generic, &spr_write_generic, | |
7136 | 0x00000000); | |
7137 | /* L3ITCR2 */ | |
7138 | /* XXX : not implemented */ | |
7139 | spr_register(env, SPR_L3ITCR2, "L3ITCR2", | |
7140 | SPR_NOACCESS, SPR_NOACCESS, | |
7141 | &spr_read_generic, &spr_write_generic, | |
7142 | 0x00000000); | |
7143 | /* L3ITCR3 */ | |
7144 | /* XXX : not implemented */ | |
7145 | spr_register(env, SPR_L3ITCR3, "L3ITCR3", | |
7146 | SPR_NOACCESS, SPR_NOACCESS, | |
7147 | &spr_read_generic, &spr_write_generic, | |
7148 | 0x00000000); | |
7149 | /* L3OHCR */ | |
7150 | /* XXX : not implemented */ | |
7151 | spr_register(env, SPR_L3OHCR, "L3OHCR", | |
7152 | SPR_NOACCESS, SPR_NOACCESS, | |
7153 | &spr_read_generic, &spr_write_generic, | |
7154 | 0x00000000); | |
7155 | /* LDSTCR */ | |
7156 | /* XXX : not implemented */ | |
7157 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
7158 | SPR_NOACCESS, SPR_NOACCESS, | |
7159 | &spr_read_generic, &spr_write_generic, | |
7160 | 0x00000000); | |
7161 | /* ICTRL */ | |
7162 | /* XXX : not implemented */ | |
7163 | spr_register(env, SPR_ICTRL, "ICTRL", | |
7164 | SPR_NOACCESS, SPR_NOACCESS, | |
7165 | &spr_read_generic, &spr_write_generic, | |
7166 | 0x00000000); | |
7167 | /* MSSSR0 */ | |
7168 | /* XXX : not implemented */ | |
7169 | spr_register(env, SPR_MSSSR0, "MSSSR0", | |
7170 | SPR_NOACCESS, SPR_NOACCESS, | |
7171 | &spr_read_generic, &spr_write_generic, | |
7172 | 0x00000000); | |
7173 | /* PMC */ | |
7174 | /* XXX : not implemented */ | |
cb8b8bf8 | 7175 | spr_register(env, SPR_7XX_PMC5, "PMC5", |
4e777442 JM |
7176 | SPR_NOACCESS, SPR_NOACCESS, |
7177 | &spr_read_generic, &spr_write_generic, | |
7178 | 0x00000000); | |
7179 | /* XXX : not implemented */ | |
cb8b8bf8 | 7180 | spr_register(env, SPR_7XX_UPMC5, "UPMC5", |
4e777442 JM |
7181 | &spr_read_ureg, SPR_NOACCESS, |
7182 | &spr_read_ureg, SPR_NOACCESS, | |
7183 | 0x00000000); | |
7184 | /* XXX : not implemented */ | |
cb8b8bf8 | 7185 | spr_register(env, SPR_7XX_PMC6, "PMC6", |
4e777442 JM |
7186 | SPR_NOACCESS, SPR_NOACCESS, |
7187 | &spr_read_generic, &spr_write_generic, | |
7188 | 0x00000000); | |
7189 | /* XXX : not implemented */ | |
cb8b8bf8 | 7190 | spr_register(env, SPR_7XX_UPMC6, "UPMC6", |
4e777442 JM |
7191 | &spr_read_ureg, SPR_NOACCESS, |
7192 | &spr_read_ureg, SPR_NOACCESS, | |
7193 | 0x00000000); | |
7194 | /* SPRGs */ | |
7195 | spr_register(env, SPR_SPRG4, "SPRG4", | |
7196 | SPR_NOACCESS, SPR_NOACCESS, | |
7197 | &spr_read_generic, &spr_write_generic, | |
7198 | 0x00000000); | |
7199 | spr_register(env, SPR_USPRG4, "USPRG4", | |
7200 | &spr_read_ureg, SPR_NOACCESS, | |
7201 | &spr_read_ureg, SPR_NOACCESS, | |
7202 | 0x00000000); | |
7203 | spr_register(env, SPR_SPRG5, "SPRG5", | |
7204 | SPR_NOACCESS, SPR_NOACCESS, | |
7205 | &spr_read_generic, &spr_write_generic, | |
7206 | 0x00000000); | |
7207 | spr_register(env, SPR_USPRG5, "USPRG5", | |
7208 | &spr_read_ureg, SPR_NOACCESS, | |
7209 | &spr_read_ureg, SPR_NOACCESS, | |
7210 | 0x00000000); | |
7211 | spr_register(env, SPR_SPRG6, "SPRG6", | |
7212 | SPR_NOACCESS, SPR_NOACCESS, | |
7213 | &spr_read_generic, &spr_write_generic, | |
7214 | 0x00000000); | |
7215 | spr_register(env, SPR_USPRG6, "USPRG6", | |
7216 | &spr_read_ureg, SPR_NOACCESS, | |
7217 | &spr_read_ureg, SPR_NOACCESS, | |
7218 | 0x00000000); | |
7219 | spr_register(env, SPR_SPRG7, "SPRG7", | |
7220 | SPR_NOACCESS, SPR_NOACCESS, | |
7221 | &spr_read_generic, &spr_write_generic, | |
7222 | 0x00000000); | |
7223 | spr_register(env, SPR_USPRG7, "USPRG7", | |
7224 | &spr_read_ureg, SPR_NOACCESS, | |
7225 | &spr_read_ureg, SPR_NOACCESS, | |
7226 | 0x00000000); | |
7227 | /* Memory management */ | |
7228 | gen_low_BATs(env); | |
7229 | gen_high_BATs(env); | |
7230 | gen_74xx_soft_tlb(env, 128, 2); | |
7231 | init_excp_7450(env); | |
7232 | env->dcache_line_size = 32; | |
7233 | env->icache_line_size = 32; | |
7234 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 7235 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
4e777442 JM |
7236 | } |
7237 | ||
7856e3a4 AF |
7238 | POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) |
7239 | { | |
ca5dff0a | 7240 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
7241 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
7242 | ||
ca5dff0a | 7243 | dc->desc = "PowerPC 7457 (aka G4)"; |
7856e3a4 AF |
7244 | pcc->init_proc = init_proc_7457; |
7245 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
7246 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
7247 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
7248 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7249 | PPC_FLOAT_STFIWX | | |
7250 | PPC_CACHE | PPC_CACHE_ICBI | | |
7251 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
7252 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7253 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7254 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
7255 | PPC_SEGMENT | PPC_EXTERN | | |
7256 | PPC_ALTIVEC; | |
9df5a466 TM |
7257 | pcc->msr_mask = (1ull << MSR_VR) | |
7258 | (1ull << MSR_POW) | | |
7259 | (1ull << MSR_ILE) | | |
7260 | (1ull << MSR_EE) | | |
7261 | (1ull << MSR_PR) | | |
7262 | (1ull << MSR_FP) | | |
7263 | (1ull << MSR_ME) | | |
7264 | (1ull << MSR_FE0) | | |
7265 | (1ull << MSR_SE) | | |
7266 | (1ull << MSR_DE) | | |
7267 | (1ull << MSR_FE1) | | |
7268 | (1ull << MSR_EP) | | |
7269 | (1ull << MSR_IR) | | |
7270 | (1ull << MSR_DR) | | |
7271 | (1ull << MSR_PMM) | | |
7272 | (1ull << MSR_RI) | | |
7273 | (1ull << MSR_LE); | |
ba9fd9f1 AF |
7274 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; |
7275 | pcc->excp_model = POWERPC_EXCP_74xx; | |
7276 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
7277 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
7278 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7279 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7280 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
7281 | } |
7282 | ||
7162bdea JG |
7283 | static void init_proc_e600 (CPUPPCState *env) |
7284 | { | |
7285 | gen_spr_ne_601(env); | |
7286 | gen_spr_7xx(env); | |
7287 | /* Time base */ | |
7288 | gen_tbl(env); | |
7289 | /* 74xx specific SPR */ | |
7290 | gen_spr_74xx(env); | |
7291 | /* XXX : not implemented */ | |
7292 | spr_register(env, SPR_UBAMR, "UBAMR", | |
7293 | &spr_read_ureg, SPR_NOACCESS, | |
7294 | &spr_read_ureg, SPR_NOACCESS, | |
7295 | 0x00000000); | |
7296 | /* XXX : not implemented */ | |
7297 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
7298 | SPR_NOACCESS, SPR_NOACCESS, | |
7299 | &spr_read_generic, &spr_write_generic, | |
7300 | 0x00000000); | |
7301 | /* XXX : not implemented */ | |
7302 | spr_register(env, SPR_ICTRL, "ICTRL", | |
7303 | SPR_NOACCESS, SPR_NOACCESS, | |
7304 | &spr_read_generic, &spr_write_generic, | |
7305 | 0x00000000); | |
7306 | /* XXX : not implemented */ | |
7307 | spr_register(env, SPR_MSSSR0, "MSSSR0", | |
7308 | SPR_NOACCESS, SPR_NOACCESS, | |
7309 | &spr_read_generic, &spr_write_generic, | |
7310 | 0x00000000); | |
7311 | /* XXX : not implemented */ | |
cb8b8bf8 | 7312 | spr_register(env, SPR_7XX_PMC5, "PMC5", |
7162bdea JG |
7313 | SPR_NOACCESS, SPR_NOACCESS, |
7314 | &spr_read_generic, &spr_write_generic, | |
7315 | 0x00000000); | |
7316 | /* XXX : not implemented */ | |
cb8b8bf8 | 7317 | spr_register(env, SPR_7XX_UPMC5, "UPMC5", |
7162bdea JG |
7318 | &spr_read_ureg, SPR_NOACCESS, |
7319 | &spr_read_ureg, SPR_NOACCESS, | |
7320 | 0x00000000); | |
7321 | /* XXX : not implemented */ | |
cb8b8bf8 | 7322 | spr_register(env, SPR_7XX_PMC6, "PMC6", |
7162bdea JG |
7323 | SPR_NOACCESS, SPR_NOACCESS, |
7324 | &spr_read_generic, &spr_write_generic, | |
7325 | 0x00000000); | |
7326 | /* XXX : not implemented */ | |
cb8b8bf8 | 7327 | spr_register(env, SPR_7XX_UPMC6, "UPMC6", |
7162bdea JG |
7328 | &spr_read_ureg, SPR_NOACCESS, |
7329 | &spr_read_ureg, SPR_NOACCESS, | |
7330 | 0x00000000); | |
7331 | /* SPRGs */ | |
7332 | spr_register(env, SPR_SPRG4, "SPRG4", | |
7333 | SPR_NOACCESS, SPR_NOACCESS, | |
7334 | &spr_read_generic, &spr_write_generic, | |
7335 | 0x00000000); | |
7336 | spr_register(env, SPR_USPRG4, "USPRG4", | |
7337 | &spr_read_ureg, SPR_NOACCESS, | |
7338 | &spr_read_ureg, SPR_NOACCESS, | |
7339 | 0x00000000); | |
7340 | spr_register(env, SPR_SPRG5, "SPRG5", | |
7341 | SPR_NOACCESS, SPR_NOACCESS, | |
7342 | &spr_read_generic, &spr_write_generic, | |
7343 | 0x00000000); | |
7344 | spr_register(env, SPR_USPRG5, "USPRG5", | |
7345 | &spr_read_ureg, SPR_NOACCESS, | |
7346 | &spr_read_ureg, SPR_NOACCESS, | |
7347 | 0x00000000); | |
7348 | spr_register(env, SPR_SPRG6, "SPRG6", | |
7349 | SPR_NOACCESS, SPR_NOACCESS, | |
7350 | &spr_read_generic, &spr_write_generic, | |
7351 | 0x00000000); | |
7352 | spr_register(env, SPR_USPRG6, "USPRG6", | |
7353 | &spr_read_ureg, SPR_NOACCESS, | |
7354 | &spr_read_ureg, SPR_NOACCESS, | |
7355 | 0x00000000); | |
7356 | spr_register(env, SPR_SPRG7, "SPRG7", | |
7357 | SPR_NOACCESS, SPR_NOACCESS, | |
7358 | &spr_read_generic, &spr_write_generic, | |
7359 | 0x00000000); | |
7360 | spr_register(env, SPR_USPRG7, "USPRG7", | |
7361 | &spr_read_ureg, SPR_NOACCESS, | |
7362 | &spr_read_ureg, SPR_NOACCESS, | |
7363 | 0x00000000); | |
7364 | /* Memory management */ | |
7365 | gen_low_BATs(env); | |
7366 | gen_high_BATs(env); | |
7367 | gen_74xx_soft_tlb(env, 128, 2); | |
7368 | init_excp_7450(env); | |
7369 | env->dcache_line_size = 32; | |
7370 | env->icache_line_size = 32; | |
7371 | /* Allocate hardware IRQ controller */ | |
aa5a9e24 | 7372 | ppc6xx_irq_init(ppc_env_get_cpu(env)); |
7162bdea JG |
7373 | } |
7374 | ||
7375 | POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) | |
7376 | { | |
7377 | DeviceClass *dc = DEVICE_CLASS(oc); | |
7378 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
7379 | ||
7380 | dc->desc = "PowerPC e600"; | |
7381 | pcc->init_proc = init_proc_e600; | |
7382 | pcc->check_pow = check_pow_hid0_74xx; | |
7383 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | | |
7384 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
7385 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7386 | PPC_FLOAT_STFIWX | | |
7387 | PPC_CACHE | PPC_CACHE_ICBI | | |
7388 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
7389 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7390 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7391 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
7392 | PPC_SEGMENT | PPC_EXTERN | | |
7393 | PPC_ALTIVEC; | |
7394 | pcc->insns_flags2 = PPC_NONE; | |
9df5a466 TM |
7395 | pcc->msr_mask = (1ull << MSR_VR) | |
7396 | (1ull << MSR_POW) | | |
7397 | (1ull << MSR_ILE) | | |
7398 | (1ull << MSR_EE) | | |
7399 | (1ull << MSR_PR) | | |
7400 | (1ull << MSR_FP) | | |
7401 | (1ull << MSR_ME) | | |
7402 | (1ull << MSR_FE0) | | |
7403 | (1ull << MSR_SE) | | |
7404 | (1ull << MSR_DE) | | |
7405 | (1ull << MSR_FE1) | | |
7406 | (1ull << MSR_EP) | | |
7407 | (1ull << MSR_IR) | | |
7408 | (1ull << MSR_DR) | | |
7409 | (1ull << MSR_PMM) | | |
7410 | (1ull << MSR_RI) | | |
7411 | (1ull << MSR_LE); | |
7162bdea JG |
7412 | pcc->mmu_model = POWERPC_MMU_32B; |
7413 | #if defined(CONFIG_SOFTMMU) | |
7414 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
7415 | #endif | |
7416 | pcc->excp_model = POWERPC_EXCP_74xx; | |
7417 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
7418 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
7419 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7420 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7421 | POWERPC_FLAG_BUS_CLK; | |
7422 | } | |
7423 | ||
a750fc0b | 7424 | #if defined (TARGET_PPC64) |
417bf010 JM |
7425 | #if defined(CONFIG_USER_ONLY) |
7426 | #define POWERPC970_HID5_INIT 0x00000080 | |
7427 | #else | |
7428 | #define POWERPC970_HID5_INIT 0x00000000 | |
7429 | #endif | |
7430 | ||
7488d481 AK |
7431 | enum BOOK3S_CPU_TYPE { |
7432 | BOOK3S_CPU_970, | |
7433 | BOOK3S_CPU_POWER5PLUS, | |
a2428814 AK |
7434 | BOOK3S_CPU_POWER6, |
7435 | BOOK3S_CPU_POWER7, | |
7436 | BOOK3S_CPU_POWER8 | |
7488d481 AK |
7437 | }; |
7438 | ||
69b058c8 PB |
7439 | static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, |
7440 | int bit, int sprn, int cause) | |
45ed0be1 AK |
7441 | { |
7442 | TCGv_i32 t1 = tcg_const_i32(bit); | |
7443 | TCGv_i32 t2 = tcg_const_i32(sprn); | |
7444 | TCGv_i32 t3 = tcg_const_i32(cause); | |
7445 | ||
69b058c8 | 7446 | gen_update_current_nip(ctx); |
45ed0be1 AK |
7447 | gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); |
7448 | ||
7449 | tcg_temp_free_i32(t3); | |
7450 | tcg_temp_free_i32(t2); | |
7451 | tcg_temp_free_i32(t1); | |
7452 | } | |
7453 | ||
69b058c8 PB |
7454 | static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, |
7455 | int bit, int sprn, int cause) | |
cdcdda27 AK |
7456 | { |
7457 | TCGv_i32 t1 = tcg_const_i32(bit); | |
7458 | TCGv_i32 t2 = tcg_const_i32(sprn); | |
7459 | TCGv_i32 t3 = tcg_const_i32(cause); | |
7460 | ||
69b058c8 | 7461 | gen_update_current_nip(ctx); |
cdcdda27 AK |
7462 | gen_helper_msr_facility_check(cpu_env, t1, t2, t3); |
7463 | ||
7464 | tcg_temp_free_i32(t3); | |
7465 | tcg_temp_free_i32(t2); | |
7466 | tcg_temp_free_i32(t1); | |
7467 | } | |
7468 | ||
69b058c8 | 7469 | static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) |
cdcdda27 AK |
7470 | { |
7471 | TCGv spr_up = tcg_temp_new(); | |
7472 | TCGv spr = tcg_temp_new(); | |
7473 | ||
7474 | gen_load_spr(spr, sprn - 1); | |
7475 | tcg_gen_shri_tl(spr_up, spr, 32); | |
7476 | tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); | |
7477 | ||
7478 | tcg_temp_free(spr); | |
7479 | tcg_temp_free(spr_up); | |
7480 | } | |
7481 | ||
69b058c8 | 7482 | static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) |
cdcdda27 AK |
7483 | { |
7484 | TCGv spr = tcg_temp_new(); | |
7485 | ||
7486 | gen_load_spr(spr, sprn - 1); | |
7487 | tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); | |
7488 | gen_store_spr(sprn - 1, spr); | |
7489 | ||
7490 | tcg_temp_free(spr); | |
7491 | } | |
7492 | ||
2f462816 JM |
7493 | static int check_pow_970 (CPUPPCState *env) |
7494 | { | |
bbc01ca7 | 7495 | if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { |
2f462816 | 7496 | return 1; |
bbc01ca7 | 7497 | } |
2f462816 JM |
7498 | |
7499 | return 0; | |
7500 | } | |
7501 | ||
42382f62 | 7502 | static void gen_spr_970_hid(CPUPPCState *env) |
a750fc0b | 7503 | { |
a750fc0b JM |
7504 | /* Hardware implementation registers */ |
7505 | /* XXX : not implemented */ | |
7506 | spr_register(env, SPR_HID0, "HID0", | |
7507 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 7508 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 7509 | 0x60000000); |
a750fc0b JM |
7510 | spr_register(env, SPR_HID1, "HID1", |
7511 | SPR_NOACCESS, SPR_NOACCESS, | |
7512 | &spr_read_generic, &spr_write_generic, | |
7513 | 0x00000000); | |
e57448f1 JM |
7514 | spr_register(env, SPR_970_HID5, "HID5", |
7515 | SPR_NOACCESS, SPR_NOACCESS, | |
7516 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 7517 | POWERPC970_HID5_INIT); |
42382f62 AK |
7518 | } |
7519 | ||
7520 | static void gen_spr_970_hior(CPUPPCState *env) | |
7521 | { | |
12de9a39 JM |
7522 | spr_register(env, SPR_HIOR, "SPR_HIOR", |
7523 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
7524 | &spr_read_hior, &spr_write_hior, |
7525 | 0x00000000); | |
42382f62 | 7526 | } |
7856e3a4 | 7527 | |
ba881002 AK |
7528 | static void gen_spr_970_lpar(CPUPPCState *env) |
7529 | { | |
7530 | /* Logical partitionning */ | |
7531 | /* PPC970: HID4 is effectively the LPCR */ | |
7532 | spr_register(env, SPR_970_HID4, "HID4", | |
7533 | SPR_NOACCESS, SPR_NOACCESS, | |
7534 | &spr_read_generic, &spr_write_generic, | |
7535 | 0x00000000); | |
7536 | } | |
7537 | ||
42382f62 AK |
7538 | static void gen_spr_book3s_common(CPUPPCState *env) |
7539 | { | |
4e98d8cf BS |
7540 | spr_register(env, SPR_CTRL, "SPR_CTRL", |
7541 | SPR_NOACCESS, SPR_NOACCESS, | |
4e381819 | 7542 | SPR_NOACCESS, &spr_write_generic, |
4e98d8cf BS |
7543 | 0x00000000); |
7544 | spr_register(env, SPR_UCTRL, "SPR_UCTRL", | |
eb16dd9c AK |
7545 | &spr_read_ureg, SPR_NOACCESS, |
7546 | &spr_read_ureg, SPR_NOACCESS, | |
4e98d8cf | 7547 | 0x00000000); |
42382f62 AK |
7548 | } |
7549 | ||
7550 | static void gen_spr_book3s_altivec(CPUPPCState *env) | |
7551 | { | |
7552 | if (!(env->insns_flags & PPC_ALTIVEC)) { | |
7553 | return; | |
7554 | } | |
7555 | ||
7303f83d AK |
7556 | spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", |
7557 | &spr_read_generic, &spr_write_generic, | |
7558 | &spr_read_generic, &spr_write_generic, | |
7559 | KVM_REG_PPC_VRSAVE, 0x00000000); | |
42382f62 AK |
7560 | |
7561 | /* Can't find information on what this should be on reset. This | |
7562 | * value is the one used by 74xx processors. */ | |
7563 | vscr_init(env, 0x00010000); | |
7564 | } | |
7565 | ||
fd51ff63 AK |
7566 | static void gen_spr_book3s_dbg(CPUPPCState *env) |
7567 | { | |
cd9adfdd AK |
7568 | /* |
7569 | * TODO: different specs define different scopes for these, | |
7570 | * will have to address this: | |
7571 | * 970: super/write and super/read | |
7572 | * powerisa 2.03..2.04: hypv/write and super/read. | |
7573 | * powerisa 2.05 and newer: hypv/write and hypv/read. | |
7574 | */ | |
fd51ff63 AK |
7575 | spr_register_kvm(env, SPR_DABR, "DABR", |
7576 | SPR_NOACCESS, SPR_NOACCESS, | |
7577 | &spr_read_generic, &spr_write_generic, | |
7578 | KVM_REG_PPC_DABR, 0x00000000); | |
cd9adfdd AK |
7579 | spr_register_kvm(env, SPR_DABRX, "DABRX", |
7580 | SPR_NOACCESS, SPR_NOACCESS, | |
7581 | &spr_read_generic, &spr_write_generic, | |
7582 | KVM_REG_PPC_DABRX, 0x00000000); | |
fd51ff63 AK |
7583 | } |
7584 | ||
f401dd32 BH |
7585 | static void gen_spr_book3s_207_dbg(CPUPPCState *env) |
7586 | { | |
7587 | spr_register_kvm_hv(env, SPR_DAWR, "DAWR", | |
7588 | SPR_NOACCESS, SPR_NOACCESS, | |
7589 | SPR_NOACCESS, SPR_NOACCESS, | |
7590 | &spr_read_generic, &spr_write_generic, | |
7591 | KVM_REG_PPC_DAWR, 0x00000000); | |
7592 | spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", | |
7593 | SPR_NOACCESS, SPR_NOACCESS, | |
7594 | SPR_NOACCESS, SPR_NOACCESS, | |
7595 | &spr_read_generic, &spr_write_generic, | |
7596 | KVM_REG_PPC_DAWRX, 0x00000000); | |
eb5ceb4d BH |
7597 | spr_register_kvm_hv(env, SPR_CIABR, "CIABR", |
7598 | SPR_NOACCESS, SPR_NOACCESS, | |
7599 | SPR_NOACCESS, SPR_NOACCESS, | |
7600 | &spr_read_generic, &spr_write_generic, | |
7601 | KVM_REG_PPC_CIABR, 0x00000000); | |
f401dd32 BH |
7602 | } |
7603 | ||
fd51ff63 AK |
7604 | static void gen_spr_970_dbg(CPUPPCState *env) |
7605 | { | |
7606 | /* Breakpoints */ | |
7607 | spr_register(env, SPR_IABR, "IABR", | |
7608 | SPR_NOACCESS, SPR_NOACCESS, | |
7609 | &spr_read_generic, &spr_write_generic, | |
7610 | 0x00000000); | |
7611 | } | |
7612 | ||
7613 | static void gen_spr_book3s_pmu_sup(CPUPPCState *env) | |
7614 | { | |
83cc6f8c AK |
7615 | spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", |
7616 | SPR_NOACCESS, SPR_NOACCESS, | |
7617 | &spr_read_generic, &spr_write_generic, | |
7618 | KVM_REG_PPC_MMCR0, 0x00000000); | |
7619 | spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", | |
7620 | SPR_NOACCESS, SPR_NOACCESS, | |
7621 | &spr_read_generic, &spr_write_generic, | |
7622 | KVM_REG_PPC_MMCR1, 0x00000000); | |
7623 | spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", | |
7624 | SPR_NOACCESS, SPR_NOACCESS, | |
7625 | &spr_read_generic, &spr_write_generic, | |
7626 | KVM_REG_PPC_MMCRA, 0x00000000); | |
7627 | spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", | |
7628 | SPR_NOACCESS, SPR_NOACCESS, | |
7629 | &spr_read_generic, &spr_write_generic, | |
7630 | KVM_REG_PPC_PMC1, 0x00000000); | |
7631 | spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", | |
7632 | SPR_NOACCESS, SPR_NOACCESS, | |
7633 | &spr_read_generic, &spr_write_generic, | |
7634 | KVM_REG_PPC_PMC2, 0x00000000); | |
7635 | spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", | |
7636 | SPR_NOACCESS, SPR_NOACCESS, | |
7637 | &spr_read_generic, &spr_write_generic, | |
7638 | KVM_REG_PPC_PMC3, 0x00000000); | |
7639 | spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", | |
7640 | SPR_NOACCESS, SPR_NOACCESS, | |
7641 | &spr_read_generic, &spr_write_generic, | |
7642 | KVM_REG_PPC_PMC4, 0x00000000); | |
7643 | spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", | |
7644 | SPR_NOACCESS, SPR_NOACCESS, | |
7645 | &spr_read_generic, &spr_write_generic, | |
7646 | KVM_REG_PPC_PMC5, 0x00000000); | |
7647 | spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", | |
7648 | SPR_NOACCESS, SPR_NOACCESS, | |
7649 | &spr_read_generic, &spr_write_generic, | |
7650 | KVM_REG_PPC_PMC6, 0x00000000); | |
7651 | spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", | |
7652 | SPR_NOACCESS, SPR_NOACCESS, | |
7653 | &spr_read_generic, &spr_write_generic, | |
7654 | KVM_REG_PPC_SIAR, 0x00000000); | |
7655 | spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", | |
7656 | SPR_NOACCESS, SPR_NOACCESS, | |
7657 | &spr_read_generic, &spr_write_generic, | |
7658 | KVM_REG_PPC_SDAR, 0x00000000); | |
fd51ff63 AK |
7659 | } |
7660 | ||
7661 | static void gen_spr_book3s_pmu_user(CPUPPCState *env) | |
7662 | { | |
7663 | spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", | |
7664 | &spr_read_ureg, SPR_NOACCESS, | |
7665 | &spr_read_ureg, &spr_write_ureg, | |
7666 | 0x00000000); | |
7667 | spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", | |
7668 | &spr_read_ureg, SPR_NOACCESS, | |
7669 | &spr_read_ureg, &spr_write_ureg, | |
7670 | 0x00000000); | |
077850b0 AK |
7671 | spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", |
7672 | &spr_read_ureg, SPR_NOACCESS, | |
7673 | &spr_read_ureg, &spr_write_ureg, | |
7674 | 0x00000000); | |
fd51ff63 AK |
7675 | spr_register(env, SPR_POWER_UPMC1, "UPMC1", |
7676 | &spr_read_ureg, SPR_NOACCESS, | |
7677 | &spr_read_ureg, &spr_write_ureg, | |
7678 | 0x00000000); | |
7679 | spr_register(env, SPR_POWER_UPMC2, "UPMC2", | |
7680 | &spr_read_ureg, SPR_NOACCESS, | |
7681 | &spr_read_ureg, &spr_write_ureg, | |
7682 | 0x00000000); | |
7683 | spr_register(env, SPR_POWER_UPMC3, "UPMC3", | |
7684 | &spr_read_ureg, SPR_NOACCESS, | |
7685 | &spr_read_ureg, &spr_write_ureg, | |
7686 | 0x00000000); | |
7687 | spr_register(env, SPR_POWER_UPMC4, "UPMC4", | |
7688 | &spr_read_ureg, SPR_NOACCESS, | |
7689 | &spr_read_ureg, &spr_write_ureg, | |
7690 | 0x00000000); | |
077850b0 AK |
7691 | spr_register(env, SPR_POWER_UPMC5, "UPMC5", |
7692 | &spr_read_ureg, SPR_NOACCESS, | |
7693 | &spr_read_ureg, &spr_write_ureg, | |
7694 | 0x00000000); | |
7695 | spr_register(env, SPR_POWER_UPMC6, "UPMC6", | |
7696 | &spr_read_ureg, SPR_NOACCESS, | |
7697 | &spr_read_ureg, &spr_write_ureg, | |
7698 | 0x00000000); | |
fd51ff63 AK |
7699 | spr_register(env, SPR_POWER_USIAR, "USIAR", |
7700 | &spr_read_ureg, SPR_NOACCESS, | |
7701 | &spr_read_ureg, &spr_write_ureg, | |
7702 | 0x00000000); | |
077850b0 AK |
7703 | spr_register(env, SPR_POWER_USDAR, "USDAR", |
7704 | &spr_read_ureg, SPR_NOACCESS, | |
7705 | &spr_read_ureg, &spr_write_ureg, | |
7706 | 0x00000000); | |
fd51ff63 AK |
7707 | } |
7708 | ||
c36c97f8 AK |
7709 | static void gen_spr_970_pmu_sup(CPUPPCState *env) |
7710 | { | |
83cc6f8c AK |
7711 | spr_register_kvm(env, SPR_970_PMC7, "PMC7", |
7712 | SPR_NOACCESS, SPR_NOACCESS, | |
7713 | &spr_read_generic, &spr_write_generic, | |
7714 | KVM_REG_PPC_PMC7, 0x00000000); | |
7715 | spr_register_kvm(env, SPR_970_PMC8, "PMC8", | |
7716 | SPR_NOACCESS, SPR_NOACCESS, | |
7717 | &spr_read_generic, &spr_write_generic, | |
7718 | KVM_REG_PPC_PMC8, 0x00000000); | |
c36c97f8 AK |
7719 | } |
7720 | ||
7721 | static void gen_spr_970_pmu_user(CPUPPCState *env) | |
7722 | { | |
7723 | spr_register(env, SPR_970_UPMC7, "UPMC7", | |
7724 | &spr_read_ureg, SPR_NOACCESS, | |
7725 | &spr_read_ureg, &spr_write_ureg, | |
7726 | 0x00000000); | |
7727 | spr_register(env, SPR_970_UPMC8, "UPMC8", | |
7728 | &spr_read_ureg, SPR_NOACCESS, | |
7729 | &spr_read_ureg, &spr_write_ureg, | |
7730 | 0x00000000); | |
7731 | } | |
7732 | ||
70c53407 AK |
7733 | static void gen_spr_power8_pmu_sup(CPUPPCState *env) |
7734 | { | |
7735 | spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", | |
7736 | SPR_NOACCESS, SPR_NOACCESS, | |
7737 | &spr_read_generic, &spr_write_generic, | |
7738 | KVM_REG_PPC_MMCR2, 0x00000000); | |
7739 | spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", | |
7740 | SPR_NOACCESS, SPR_NOACCESS, | |
7741 | &spr_read_generic, &spr_write_generic, | |
7742 | KVM_REG_PPC_MMCRS, 0x00000000); | |
14646457 BH |
7743 | spr_register_kvm(env, SPR_POWER_SIER, "SIER", |
7744 | SPR_NOACCESS, SPR_NOACCESS, | |
7745 | &spr_read_generic, &spr_write_generic, | |
7746 | KVM_REG_PPC_SIER, 0x00000000); | |
7747 | spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", | |
7748 | SPR_NOACCESS, SPR_NOACCESS, | |
7749 | &spr_read_generic, &spr_write_generic, | |
7750 | KVM_REG_PPC_SPMC1, 0x00000000); | |
7751 | spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", | |
7752 | SPR_NOACCESS, SPR_NOACCESS, | |
7753 | &spr_read_generic, &spr_write_generic, | |
7754 | KVM_REG_PPC_SPMC2, 0x00000000); | |
7755 | spr_register_kvm(env, SPR_TACR, "TACR", | |
7756 | SPR_NOACCESS, SPR_NOACCESS, | |
7757 | &spr_read_generic, &spr_write_generic, | |
7758 | KVM_REG_PPC_TACR, 0x00000000); | |
7759 | spr_register_kvm(env, SPR_TCSCR, "TCSCR", | |
7760 | SPR_NOACCESS, SPR_NOACCESS, | |
7761 | &spr_read_generic, &spr_write_generic, | |
7762 | KVM_REG_PPC_TCSCR, 0x00000000); | |
7763 | spr_register_kvm(env, SPR_CSIGR, "CSIGR", | |
7764 | SPR_NOACCESS, SPR_NOACCESS, | |
7765 | &spr_read_generic, &spr_write_generic, | |
7766 | KVM_REG_PPC_CSIGR, 0x00000000); | |
70c53407 AK |
7767 | } |
7768 | ||
7769 | static void gen_spr_power8_pmu_user(CPUPPCState *env) | |
7770 | { | |
7771 | spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", | |
7772 | &spr_read_ureg, SPR_NOACCESS, | |
7773 | &spr_read_ureg, &spr_write_ureg, | |
7774 | 0x00000000); | |
14646457 BH |
7775 | spr_register(env, SPR_POWER_USIER, "USIER", |
7776 | &spr_read_generic, SPR_NOACCESS, | |
7777 | &spr_read_generic, &spr_write_generic, | |
7778 | 0x00000000); | |
70c53407 AK |
7779 | } |
7780 | ||
fd51ff63 AK |
7781 | static void gen_spr_power5p_ear(CPUPPCState *env) |
7782 | { | |
7783 | /* External access control */ | |
7784 | spr_register(env, SPR_EAR, "EAR", | |
7785 | SPR_NOACCESS, SPR_NOACCESS, | |
7786 | &spr_read_generic, &spr_write_generic, | |
7787 | 0x00000000); | |
7788 | } | |
7789 | ||
7488d481 AK |
7790 | static void gen_spr_power5p_lpar(CPUPPCState *env) |
7791 | { | |
7792 | /* Logical partitionning */ | |
7793 | spr_register_kvm(env, SPR_LPCR, "LPCR", | |
7794 | SPR_NOACCESS, SPR_NOACCESS, | |
7795 | &spr_read_generic, &spr_write_generic, | |
7796 | KVM_REG_PPC_LPCR, 0x00000000); | |
7797 | } | |
7798 | ||
e61716aa AK |
7799 | static void gen_spr_book3s_ids(CPUPPCState *env) |
7800 | { | |
7801 | /* Processor identification */ | |
7802 | spr_register(env, SPR_PIR, "PIR", | |
7803 | SPR_NOACCESS, SPR_NOACCESS, | |
7804 | &spr_read_generic, &spr_write_pir, | |
7805 | 0x00000000); | |
7806 | } | |
7807 | ||
d1a721ab AK |
7808 | static void gen_spr_power8_ids(CPUPPCState *env) |
7809 | { | |
7810 | /* Thread identification */ | |
7811 | spr_register(env, SPR_TIR, "TIR", | |
7812 | SPR_NOACCESS, SPR_NOACCESS, | |
7813 | &spr_read_generic, SPR_NOACCESS, | |
7814 | 0x00000000); | |
7815 | } | |
7816 | ||
e61716aa AK |
7817 | static void gen_spr_book3s_purr(CPUPPCState *env) |
7818 | { | |
7819 | #if !defined(CONFIG_USER_ONLY) | |
7820 | /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ | |
7821 | spr_register_kvm(env, SPR_PURR, "PURR", | |
7822 | &spr_read_purr, SPR_NOACCESS, | |
7823 | &spr_read_purr, SPR_NOACCESS, | |
7824 | KVM_REG_PPC_PURR, 0x00000000); | |
7825 | spr_register_kvm(env, SPR_SPURR, "SPURR", | |
7826 | &spr_read_purr, SPR_NOACCESS, | |
7827 | &spr_read_purr, SPR_NOACCESS, | |
7828 | KVM_REG_PPC_SPURR, 0x00000000); | |
7829 | #endif | |
7830 | } | |
7831 | ||
5db7d4fa AK |
7832 | static void gen_spr_power6_dbg(CPUPPCState *env) |
7833 | { | |
7834 | #if !defined(CONFIG_USER_ONLY) | |
7835 | spr_register(env, SPR_CFAR, "SPR_CFAR", | |
7836 | SPR_NOACCESS, SPR_NOACCESS, | |
7837 | &spr_read_cfar, &spr_write_cfar, | |
7838 | 0x00000000); | |
7839 | #endif | |
7840 | } | |
7841 | ||
7842 | static void gen_spr_power5p_common(CPUPPCState *env) | |
7843 | { | |
7303f83d AK |
7844 | spr_register_kvm(env, SPR_PPR, "PPR", |
7845 | &spr_read_generic, &spr_write_generic, | |
7846 | &spr_read_generic, &spr_write_generic, | |
7847 | KVM_REG_PPC_PPR, 0x00000000); | |
5db7d4fa AK |
7848 | } |
7849 | ||
7850 | static void gen_spr_power6_common(CPUPPCState *env) | |
7851 | { | |
7852 | #if !defined(CONFIG_USER_ONLY) | |
7853 | spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", | |
7854 | SPR_NOACCESS, SPR_NOACCESS, | |
7855 | &spr_read_generic, &spr_write_generic, | |
7856 | KVM_REG_PPC_DSCR, 0x00000000); | |
7857 | #endif | |
7858 | /* | |
7859 | * Register PCR to report POWERPC_EXCP_PRIV_REG instead of | |
7860 | * POWERPC_EXCP_INVAL_SPR. | |
7861 | */ | |
7862 | spr_register(env, SPR_PCR, "PCR", | |
7863 | SPR_NOACCESS, SPR_NOACCESS, | |
7864 | SPR_NOACCESS, SPR_NOACCESS, | |
7865 | 0x00000000); | |
7866 | } | |
7867 | ||
69b058c8 | 7868 | static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) |
45ed0be1 | 7869 | { |
69b058c8 PB |
7870 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); |
7871 | spr_read_generic(ctx, gprn, sprn); | |
45ed0be1 AK |
7872 | } |
7873 | ||
69b058c8 | 7874 | static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) |
45ed0be1 | 7875 | { |
69b058c8 PB |
7876 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); |
7877 | spr_write_generic(ctx, sprn, gprn); | |
45ed0be1 AK |
7878 | } |
7879 | ||
768167ab AK |
7880 | static void gen_spr_power8_tce_address_control(CPUPPCState *env) |
7881 | { | |
1e440cbc TH |
7882 | spr_register_kvm(env, SPR_TAR, "TAR", |
7883 | &spr_read_tar, &spr_write_tar, | |
7884 | &spr_read_generic, &spr_write_generic, | |
7885 | KVM_REG_PPC_TAR, 0x00000000); | |
768167ab AK |
7886 | } |
7887 | ||
69b058c8 | 7888 | static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) |
cdcdda27 | 7889 | { |
69b058c8 PB |
7890 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); |
7891 | spr_read_generic(ctx, gprn, sprn); | |
cdcdda27 AK |
7892 | } |
7893 | ||
69b058c8 | 7894 | static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) |
cdcdda27 | 7895 | { |
69b058c8 PB |
7896 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); |
7897 | spr_write_generic(ctx, sprn, gprn); | |
cdcdda27 AK |
7898 | } |
7899 | ||
69b058c8 | 7900 | static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) |
cdcdda27 | 7901 | { |
69b058c8 PB |
7902 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); |
7903 | spr_read_prev_upper32(ctx, gprn, sprn); | |
cdcdda27 AK |
7904 | } |
7905 | ||
69b058c8 | 7906 | static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) |
cdcdda27 | 7907 | { |
69b058c8 PB |
7908 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); |
7909 | spr_write_prev_upper32(ctx, sprn, gprn); | |
cdcdda27 AK |
7910 | } |
7911 | ||
7912 | static void gen_spr_power8_tm(CPUPPCState *env) | |
7913 | { | |
7914 | spr_register_kvm(env, SPR_TFHAR, "TFHAR", | |
7915 | &spr_read_tm, &spr_write_tm, | |
7916 | &spr_read_tm, &spr_write_tm, | |
7917 | KVM_REG_PPC_TFHAR, 0x00000000); | |
7918 | spr_register_kvm(env, SPR_TFIAR, "TFIAR", | |
7919 | &spr_read_tm, &spr_write_tm, | |
7920 | &spr_read_tm, &spr_write_tm, | |
7921 | KVM_REG_PPC_TFIAR, 0x00000000); | |
7922 | spr_register_kvm(env, SPR_TEXASR, "TEXASR", | |
7923 | &spr_read_tm, &spr_write_tm, | |
7924 | &spr_read_tm, &spr_write_tm, | |
7925 | KVM_REG_PPC_TEXASR, 0x00000000); | |
7926 | spr_register(env, SPR_TEXASRU, "TEXASRU", | |
7927 | &spr_read_tm_upper32, &spr_write_tm_upper32, | |
7928 | &spr_read_tm_upper32, &spr_write_tm_upper32, | |
7929 | 0x00000000); | |
7930 | } | |
7931 | ||
69b058c8 | 7932 | static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) |
4ee4a03b | 7933 | { |
69b058c8 PB |
7934 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); |
7935 | spr_read_generic(ctx, gprn, sprn); | |
4ee4a03b AK |
7936 | } |
7937 | ||
69b058c8 | 7938 | static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) |
4ee4a03b | 7939 | { |
69b058c8 PB |
7940 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); |
7941 | spr_write_generic(ctx, sprn, gprn); | |
4ee4a03b AK |
7942 | } |
7943 | ||
69b058c8 | 7944 | static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) |
4ee4a03b | 7945 | { |
69b058c8 PB |
7946 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); |
7947 | spr_read_prev_upper32(ctx, gprn, sprn); | |
4ee4a03b AK |
7948 | } |
7949 | ||
69b058c8 | 7950 | static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) |
4ee4a03b | 7951 | { |
69b058c8 PB |
7952 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); |
7953 | spr_write_prev_upper32(ctx, sprn, gprn); | |
4ee4a03b AK |
7954 | } |
7955 | ||
7956 | static void gen_spr_power8_ebb(CPUPPCState *env) | |
7957 | { | |
7958 | spr_register(env, SPR_BESCRS, "BESCRS", | |
7959 | &spr_read_ebb, &spr_write_ebb, | |
7960 | &spr_read_generic, &spr_write_generic, | |
7961 | 0x00000000); | |
7962 | spr_register(env, SPR_BESCRSU, "BESCRSU", | |
7963 | &spr_read_ebb_upper32, &spr_write_ebb_upper32, | |
7964 | &spr_read_prev_upper32, &spr_write_prev_upper32, | |
7965 | 0x00000000); | |
7966 | spr_register(env, SPR_BESCRR, "BESCRR", | |
7967 | &spr_read_ebb, &spr_write_ebb, | |
7968 | &spr_read_generic, &spr_write_generic, | |
7969 | 0x00000000); | |
7970 | spr_register(env, SPR_BESCRRU, "BESCRRU", | |
7971 | &spr_read_ebb_upper32, &spr_write_ebb_upper32, | |
7972 | &spr_read_prev_upper32, &spr_write_prev_upper32, | |
7973 | 0x00000000); | |
7974 | spr_register_kvm(env, SPR_EBBHR, "EBBHR", | |
7975 | &spr_read_ebb, &spr_write_ebb, | |
7976 | &spr_read_generic, &spr_write_generic, | |
7977 | KVM_REG_PPC_EBBHR, 0x00000000); | |
7978 | spr_register_kvm(env, SPR_EBBRR, "EBBRR", | |
7979 | &spr_read_ebb, &spr_write_ebb, | |
7980 | &spr_read_generic, &spr_write_generic, | |
7981 | KVM_REG_PPC_EBBRR, 0x00000000); | |
7982 | spr_register_kvm(env, SPR_BESCR, "BESCR", | |
7983 | &spr_read_ebb, &spr_write_ebb, | |
7984 | &spr_read_generic, &spr_write_generic, | |
7985 | KVM_REG_PPC_BESCR, 0x00000000); | |
7986 | } | |
7987 | ||
3ba55e39 CB |
7988 | /* Virtual Time Base */ |
7989 | static void gen_spr_vtb(CPUPPCState *env) | |
7990 | { | |
7991 | spr_register(env, SPR_VTB, "VTB", | |
7992 | SPR_NOACCESS, SPR_NOACCESS, | |
7993 | &spr_read_tbl, SPR_NOACCESS, | |
7994 | 0x00000000); | |
7995 | } | |
7996 | ||
7019cb3d AK |
7997 | static void gen_spr_power8_fscr(CPUPPCState *env) |
7998 | { | |
45ed0be1 AK |
7999 | #if defined(CONFIG_USER_ONLY) |
8000 | target_ulong initval = 1ULL << FSCR_TAR; | |
8001 | #else | |
8002 | target_ulong initval = 0; | |
8003 | #endif | |
7019cb3d AK |
8004 | spr_register_kvm(env, SPR_FSCR, "FSCR", |
8005 | SPR_NOACCESS, SPR_NOACCESS, | |
8006 | &spr_read_generic, &spr_write_generic, | |
45ed0be1 | 8007 | KVM_REG_PPC_FSCR, initval); |
7019cb3d AK |
8008 | } |
8009 | ||
d6f1445f TH |
8010 | static void gen_spr_power8_pspb(CPUPPCState *env) |
8011 | { | |
8012 | spr_register_kvm(env, SPR_PSPB, "PSPB", | |
8013 | SPR_NOACCESS, SPR_NOACCESS, | |
8014 | &spr_read_generic, &spr_write_generic32, | |
8015 | KVM_REG_PPC_PSPB, 0); | |
8016 | } | |
8017 | ||
21a558be BH |
8018 | static void gen_spr_power8_ic(CPUPPCState *env) |
8019 | { | |
8020 | #if !defined(CONFIG_USER_ONLY) | |
8021 | spr_register_hv(env, SPR_IC, "IC", | |
8022 | SPR_NOACCESS, SPR_NOACCESS, | |
8023 | &spr_read_generic, SPR_NOACCESS, | |
8024 | &spr_read_generic, &spr_write_generic, | |
8025 | 0); | |
9d0e5c8c CLG |
8026 | #endif |
8027 | } | |
8028 | ||
8029 | static void gen_spr_power8_book4(CPUPPCState *env) | |
8030 | { | |
8031 | /* Add a number of P8 book4 registers */ | |
8032 | #if !defined(CONFIG_USER_ONLY) | |
9c1cf38d BH |
8033 | spr_register_kvm(env, SPR_ACOP, "ACOP", |
8034 | SPR_NOACCESS, SPR_NOACCESS, | |
8035 | &spr_read_generic, &spr_write_generic, | |
8036 | KVM_REG_PPC_ACOP, 0); | |
8037 | spr_register_kvm(env, SPR_BOOKS_PID, "PID", | |
8038 | SPR_NOACCESS, SPR_NOACCESS, | |
8039 | &spr_read_generic, &spr_write_generic, | |
8040 | KVM_REG_PPC_PID, 0); | |
8041 | spr_register_kvm(env, SPR_WORT, "WORT", | |
8042 | SPR_NOACCESS, SPR_NOACCESS, | |
8043 | &spr_read_generic, &spr_write_generic, | |
8044 | KVM_REG_PPC_WORT, 0); | |
21a558be BH |
8045 | #endif |
8046 | } | |
8047 | ||
8eb0f563 BH |
8048 | static void gen_spr_power7_book4(CPUPPCState *env) |
8049 | { | |
8050 | /* Add a number of P7 book4 registers */ | |
8051 | #if !defined(CONFIG_USER_ONLY) | |
8052 | spr_register_kvm(env, SPR_ACOP, "ACOP", | |
8053 | SPR_NOACCESS, SPR_NOACCESS, | |
8054 | &spr_read_generic, &spr_write_generic, | |
8055 | KVM_REG_PPC_ACOP, 0); | |
8056 | spr_register_kvm(env, SPR_BOOKS_PID, "PID", | |
8057 | SPR_NOACCESS, SPR_NOACCESS, | |
8058 | &spr_read_generic, &spr_write_generic, | |
8059 | KVM_REG_PPC_PID, 0); | |
8060 | #endif | |
8061 | } | |
8062 | ||
7488d481 | 8063 | static void init_proc_book3s_64(CPUPPCState *env, int version) |
42382f62 AK |
8064 | { |
8065 | gen_spr_ne_601(env); | |
42382f62 AK |
8066 | gen_tbl(env); |
8067 | gen_spr_book3s_altivec(env); | |
fd51ff63 AK |
8068 | gen_spr_book3s_pmu_sup(env); |
8069 | gen_spr_book3s_pmu_user(env); | |
42382f62 | 8070 | gen_spr_book3s_common(env); |
fd51ff63 | 8071 | |
a2428814 AK |
8072 | switch (version) { |
8073 | case BOOK3S_CPU_970: | |
8074 | case BOOK3S_CPU_POWER5PLUS: | |
8075 | gen_spr_970_hid(env); | |
8076 | gen_spr_970_hior(env); | |
8077 | gen_low_BATs(env); | |
8078 | gen_spr_970_pmu_sup(env); | |
8079 | gen_spr_970_pmu_user(env); | |
8080 | break; | |
8081 | case BOOK3S_CPU_POWER7: | |
8082 | case BOOK3S_CPU_POWER8: | |
8083 | gen_spr_book3s_ids(env); | |
a6eabb9e | 8084 | gen_spr_amr(env, version >= BOOK3S_CPU_POWER8); |
a2428814 | 8085 | gen_spr_book3s_purr(env); |
90da0d5a | 8086 | env->ci_large_pages = true; |
a2428814 AK |
8087 | break; |
8088 | default: | |
8089 | g_assert_not_reached(); | |
8090 | } | |
7488d481 | 8091 | if (version >= BOOK3S_CPU_POWER5PLUS) { |
a2428814 | 8092 | gen_spr_power5p_common(env); |
7488d481 AK |
8093 | gen_spr_power5p_lpar(env); |
8094 | gen_spr_power5p_ear(env); | |
8095 | } else { | |
8096 | gen_spr_970_lpar(env); | |
8097 | } | |
a2428814 AK |
8098 | if (version == BOOK3S_CPU_970) { |
8099 | gen_spr_970_dbg(env); | |
8100 | } | |
8101 | if (version >= BOOK3S_CPU_POWER6) { | |
8102 | gen_spr_power6_common(env); | |
8103 | gen_spr_power6_dbg(env); | |
8104 | } | |
8eb0f563 BH |
8105 | if (version == BOOK3S_CPU_POWER7) { |
8106 | gen_spr_power7_book4(env); | |
8107 | } | |
a2428814 AK |
8108 | if (version >= BOOK3S_CPU_POWER8) { |
8109 | gen_spr_power8_tce_address_control(env); | |
d1a721ab | 8110 | gen_spr_power8_ids(env); |
4ee4a03b | 8111 | gen_spr_power8_ebb(env); |
7019cb3d | 8112 | gen_spr_power8_fscr(env); |
70c53407 AK |
8113 | gen_spr_power8_pmu_sup(env); |
8114 | gen_spr_power8_pmu_user(env); | |
cdcdda27 | 8115 | gen_spr_power8_tm(env); |
d6f1445f | 8116 | gen_spr_power8_pspb(env); |
3ba55e39 | 8117 | gen_spr_vtb(env); |
21a558be | 8118 | gen_spr_power8_ic(env); |
9d0e5c8c | 8119 | gen_spr_power8_book4(env); |
a2428814 | 8120 | } |
cd9adfdd AK |
8121 | if (version < BOOK3S_CPU_POWER8) { |
8122 | gen_spr_book3s_dbg(env); | |
f401dd32 BH |
8123 | } else { |
8124 | gen_spr_book3s_207_dbg(env); | |
cd9adfdd | 8125 | } |
f2e63a42 | 8126 | #if !defined(CONFIG_USER_ONLY) |
a2428814 AK |
8127 | switch (version) { |
8128 | case BOOK3S_CPU_970: | |
8129 | case BOOK3S_CPU_POWER5PLUS: | |
8130 | env->slb_nr = 64; | |
8131 | break; | |
8132 | case BOOK3S_CPU_POWER7: | |
8133 | case BOOK3S_CPU_POWER8: | |
8134 | default: | |
8135 | env->slb_nr = 32; | |
8136 | break; | |
8137 | } | |
f2e63a42 | 8138 | #endif |
a2428814 AK |
8139 | /* Allocate hardware IRQ controller */ |
8140 | switch (version) { | |
8141 | case BOOK3S_CPU_970: | |
8142 | case BOOK3S_CPU_POWER5PLUS: | |
8143 | init_excp_970(env); | |
aa5a9e24 | 8144 | ppc970_irq_init(ppc_env_get_cpu(env)); |
a2428814 AK |
8145 | break; |
8146 | case BOOK3S_CPU_POWER7: | |
a2428814 | 8147 | init_excp_POWER7(env); |
aa5a9e24 | 8148 | ppcPOWER7_irq_init(ppc_env_get_cpu(env)); |
a2428814 | 8149 | break; |
f03a1af5 BH |
8150 | case BOOK3S_CPU_POWER8: |
8151 | init_excp_POWER8(env); | |
8152 | ppcPOWER7_irq_init(ppc_env_get_cpu(env)); | |
8153 | break; | |
a2428814 AK |
8154 | default: |
8155 | g_assert_not_reached(); | |
8156 | } | |
8157 | ||
d63001d1 JM |
8158 | env->dcache_line_size = 128; |
8159 | env->icache_line_size = 128; | |
a750fc0b | 8160 | } |
a750fc0b | 8161 | |
7488d481 AK |
8162 | static void init_proc_970(CPUPPCState *env) |
8163 | { | |
8164 | init_proc_book3s_64(env, BOOK3S_CPU_970); | |
8165 | } | |
8166 | ||
bbc01ca7 | 8167 | POWERPC_FAMILY(970)(ObjectClass *oc, void *data) |
7856e3a4 | 8168 | { |
ca5dff0a | 8169 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
8170 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
8171 | ||
bbc01ca7 AK |
8172 | dc->desc = "PowerPC 970"; |
8173 | pcc->init_proc = init_proc_970; | |
8174 | pcc->check_pow = check_pow_970; | |
53116ebf AF |
8175 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
8176 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
8177 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
8178 | PPC_FLOAT_STFIWX | | |
8179 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
8180 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
8181 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
8182 | PPC_64B | PPC_ALTIVEC | | |
8183 | PPC_SEGMENT_64B | PPC_SLBI; | |
4171853c | 8184 | pcc->insns_flags2 = PPC2_FP_CVT_S64; |
9df5a466 TM |
8185 | pcc->msr_mask = (1ull << MSR_SF) | |
8186 | (1ull << MSR_VR) | | |
8187 | (1ull << MSR_POW) | | |
8188 | (1ull << MSR_EE) | | |
8189 | (1ull << MSR_PR) | | |
8190 | (1ull << MSR_FP) | | |
8191 | (1ull << MSR_ME) | | |
8192 | (1ull << MSR_FE0) | | |
8193 | (1ull << MSR_SE) | | |
8194 | (1ull << MSR_DE) | | |
8195 | (1ull << MSR_FE1) | | |
8196 | (1ull << MSR_IR) | | |
8197 | (1ull << MSR_DR) | | |
8198 | (1ull << MSR_PMM) | | |
8199 | (1ull << MSR_RI); | |
ba9fd9f1 | 8200 | pcc->mmu_model = POWERPC_MMU_64B; |
b632a148 DG |
8201 | #if defined(CONFIG_SOFTMMU) |
8202 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
8203 | #endif | |
ba9fd9f1 AF |
8204 | pcc->excp_model = POWERPC_EXCP_970; |
8205 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
8206 | pcc->bfd_mach = bfd_mach_ppc64; | |
8207 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
8208 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
8209 | POWERPC_FLAG_BUS_CLK; | |
06f6e124 AG |
8210 | pcc->l1_dcache_size = 0x8000; |
8211 | pcc->l1_icache_size = 0x10000; | |
7856e3a4 AF |
8212 | } |
8213 | ||
35ebcb2b AF |
8214 | static void init_proc_power5plus(CPUPPCState *env) |
8215 | { | |
7488d481 | 8216 | init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS); |
35ebcb2b AF |
8217 | } |
8218 | ||
8219 | POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) | |
8220 | { | |
8221 | DeviceClass *dc = DEVICE_CLASS(oc); | |
8222 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
8223 | ||
793826cd | 8224 | dc->fw_name = "PowerPC,POWER5"; |
35ebcb2b AF |
8225 | dc->desc = "POWER5+"; |
8226 | pcc->init_proc = init_proc_power5plus; | |
90618f4f | 8227 | pcc->check_pow = check_pow_970; |
35ebcb2b AF |
8228 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
8229 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
8230 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
8231 | PPC_FLOAT_STFIWX | | |
8232 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
8233 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
8234 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
8235 | PPC_64B | | |
8236 | PPC_SEGMENT_64B | PPC_SLBI; | |
4171853c | 8237 | pcc->insns_flags2 = PPC2_FP_CVT_S64; |
9df5a466 TM |
8238 | pcc->msr_mask = (1ull << MSR_SF) | |
8239 | (1ull << MSR_VR) | | |
8240 | (1ull << MSR_POW) | | |
8241 | (1ull << MSR_EE) | | |
8242 | (1ull << MSR_PR) | | |
8243 | (1ull << MSR_FP) | | |
8244 | (1ull << MSR_ME) | | |
8245 | (1ull << MSR_FE0) | | |
8246 | (1ull << MSR_SE) | | |
8247 | (1ull << MSR_DE) | | |
8248 | (1ull << MSR_FE1) | | |
8249 | (1ull << MSR_IR) | | |
8250 | (1ull << MSR_DR) | | |
8251 | (1ull << MSR_PMM) | | |
8252 | (1ull << MSR_RI); | |
aa4bb587 | 8253 | pcc->mmu_model = POWERPC_MMU_2_03; |
35ebcb2b AF |
8254 | #if defined(CONFIG_SOFTMMU) |
8255 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
8256 | #endif | |
8257 | pcc->excp_model = POWERPC_EXCP_970; | |
8258 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
8259 | pcc->bfd_mach = bfd_mach_ppc64; | |
8260 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
8261 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
8262 | POWERPC_FLAG_BUS_CLK; | |
06f6e124 AG |
8263 | pcc->l1_dcache_size = 0x8000; |
8264 | pcc->l1_icache_size = 0x10000; | |
35ebcb2b AF |
8265 | } |
8266 | ||
d7bce999 EB |
8267 | static void powerpc_get_compat(Object *obj, Visitor *v, const char *name, |
8268 | void *opaque, Error **errp) | |
8dfa3a5e AK |
8269 | { |
8270 | char *value = (char *)""; | |
8271 | Property *prop = opaque; | |
8272 | uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop); | |
8273 | ||
8274 | switch (*max_compat) { | |
8275 | case CPU_POWERPC_LOGICAL_2_05: | |
8276 | value = (char *)"power6"; | |
8277 | break; | |
8278 | case CPU_POWERPC_LOGICAL_2_06: | |
8279 | value = (char *)"power7"; | |
8280 | break; | |
8281 | case CPU_POWERPC_LOGICAL_2_07: | |
8282 | value = (char *)"power8"; | |
8283 | break; | |
8284 | case 0: | |
8285 | break; | |
8286 | default: | |
8287 | error_setg(errp, "Internal error: compat is set to %x", | |
8288 | max_compat ? *max_compat : -1); | |
8289 | break; | |
8290 | } | |
8291 | ||
51e72bc1 | 8292 | visit_type_str(v, name, &value, errp); |
8dfa3a5e AK |
8293 | } |
8294 | ||
d7bce999 EB |
8295 | static void powerpc_set_compat(Object *obj, Visitor *v, const char *name, |
8296 | void *opaque, Error **errp) | |
8dfa3a5e AK |
8297 | { |
8298 | Error *error = NULL; | |
8299 | char *value = NULL; | |
8300 | Property *prop = opaque; | |
8301 | uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop); | |
8302 | ||
51e72bc1 | 8303 | visit_type_str(v, name, &value, &error); |
8dfa3a5e AK |
8304 | if (error) { |
8305 | error_propagate(errp, error); | |
8306 | return; | |
8307 | } | |
8308 | ||
8309 | if (strcmp(value, "power6") == 0) { | |
8310 | *max_compat = CPU_POWERPC_LOGICAL_2_05; | |
8311 | } else if (strcmp(value, "power7") == 0) { | |
8312 | *max_compat = CPU_POWERPC_LOGICAL_2_06; | |
8313 | } else if (strcmp(value, "power8") == 0) { | |
8314 | *max_compat = CPU_POWERPC_LOGICAL_2_07; | |
8315 | } else { | |
8316 | error_setg(errp, "Invalid compatibility mode \"%s\"", value); | |
8317 | } | |
8318 | ||
8319 | g_free(value); | |
8320 | } | |
8321 | ||
8322 | static PropertyInfo powerpc_compat_propinfo = { | |
8323 | .name = "str", | |
51b2e8c3 | 8324 | .description = "compatibility mode, power6/power7/power8", |
8dfa3a5e AK |
8325 | .get = powerpc_get_compat, |
8326 | .set = powerpc_set_compat, | |
8327 | }; | |
8328 | ||
8329 | #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \ | |
8330 | DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t) | |
8331 | ||
8332 | static Property powerpc_servercpu_properties[] = { | |
8333 | DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat), | |
8334 | DEFINE_PROP_END_OF_LIST(), | |
8335 | }; | |
8336 | ||
a8891fbf DG |
8337 | #ifdef CONFIG_SOFTMMU |
8338 | static const struct ppc_segment_page_sizes POWER7_POWER8_sps = { | |
8339 | .sps = { | |
8340 | { | |
8341 | .page_shift = 12, /* 4K */ | |
8342 | .slb_enc = 0, | |
8343 | .enc = { { .page_shift = 12, .pte_enc = 0 }, | |
8344 | { .page_shift = 16, .pte_enc = 0x7 }, | |
8345 | { .page_shift = 24, .pte_enc = 0x38 }, }, | |
8346 | }, | |
8347 | { | |
8348 | .page_shift = 16, /* 64K */ | |
8349 | .slb_enc = SLB_VSID_64K, | |
8350 | .enc = { { .page_shift = 16, .pte_enc = 0x1 }, | |
8351 | { .page_shift = 24, .pte_enc = 0x8 }, }, | |
8352 | }, | |
8353 | { | |
8354 | .page_shift = 24, /* 16M */ | |
8355 | .slb_enc = SLB_VSID_16M, | |
8356 | .enc = { { .page_shift = 24, .pte_enc = 0 }, }, | |
8357 | }, | |
8358 | { | |
8359 | .page_shift = 34, /* 16G */ | |
8360 | .slb_enc = SLB_VSID_16G, | |
8361 | .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, | |
8362 | }, | |
8363 | } | |
8364 | }; | |
8365 | #endif /* CONFIG_SOFTMMU */ | |
8366 | ||
9d52e907 DG |
8367 | static void init_proc_POWER7 (CPUPPCState *env) |
8368 | { | |
a2428814 | 8369 | init_proc_book3s_64(env, BOOK3S_CPU_POWER7); |
9d52e907 | 8370 | } |
9d52e907 | 8371 | |
03ae4133 AK |
8372 | static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) |
8373 | { | |
8374 | if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { | |
8375 | return true; | |
8376 | } | |
8377 | if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { | |
8378 | return true; | |
8379 | } | |
8380 | return false; | |
8381 | } | |
8382 | ||
7778a575 BH |
8383 | static bool cpu_has_work_POWER7(CPUState *cs) |
8384 | { | |
8385 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
8386 | CPUPPCState *env = &cpu->env; | |
8387 | ||
8388 | if (cs->halted) { | |
8389 | if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { | |
8390 | return false; | |
8391 | } | |
8392 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && | |
8393 | (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { | |
8394 | return true; | |
8395 | } | |
8396 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && | |
8397 | (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { | |
8398 | return true; | |
8399 | } | |
8400 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && | |
8401 | (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { | |
8402 | return true; | |
8403 | } | |
8404 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && | |
8405 | (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { | |
8406 | return true; | |
8407 | } | |
8408 | if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { | |
8409 | return true; | |
8410 | } | |
8411 | return false; | |
8412 | } else { | |
8413 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | |
8414 | } | |
8415 | } | |
8416 | ||
7856e3a4 AF |
8417 | POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) |
8418 | { | |
ca5dff0a | 8419 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 | 8420 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
7778a575 | 8421 | CPUClass *cc = CPU_CLASS(oc); |
7856e3a4 | 8422 | |
793826cd | 8423 | dc->fw_name = "PowerPC,POWER7"; |
ca5dff0a | 8424 | dc->desc = "POWER7"; |
8dfa3a5e | 8425 | dc->props = powerpc_servercpu_properties; |
03ae4133 | 8426 | pcc->pvr_match = ppc_pvr_match_power7; |
8cd2ce7a TH |
8427 | pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; |
8428 | pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | |
7856e3a4 AF |
8429 | pcc->init_proc = init_proc_POWER7; |
8430 | pcc->check_pow = check_pow_nocheck; | |
7778a575 | 8431 | cc->has_work = cpu_has_work_POWER7; |
e71ec2e9 | 8432 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | |
53116ebf AF |
8433 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | |
8434 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
ce8ca30b | 8435 | PPC_FLOAT_FRSQRTES | |
53116ebf | 8436 | PPC_FLOAT_STFIWX | |
c7386080 | 8437 | PPC_FLOAT_EXT | |
53116ebf AF |
8438 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | |
8439 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
8440 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
dfdd3e43 | 8441 | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | |
53116ebf | 8442 | PPC_SEGMENT_64B | PPC_SLBI | |
b7815375 BH |
8443 | PPC_POPCNTB | PPC_POPCNTWD | |
8444 | PPC_CILDST; | |
86ba37ed | 8445 | pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | |
1fa6c533 | 8446 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | |
29a0e4e9 | 8447 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | |
7778a575 BH |
8448 | PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | |
8449 | PPC2_PM_ISA206; | |
9df5a466 TM |
8450 | pcc->msr_mask = (1ull << MSR_SF) | |
8451 | (1ull << MSR_VR) | | |
8452 | (1ull << MSR_VSX) | | |
8453 | (1ull << MSR_EE) | | |
8454 | (1ull << MSR_PR) | | |
8455 | (1ull << MSR_FP) | | |
8456 | (1ull << MSR_ME) | | |
8457 | (1ull << MSR_FE0) | | |
8458 | (1ull << MSR_SE) | | |
8459 | (1ull << MSR_DE) | | |
8460 | (1ull << MSR_FE1) | | |
8461 | (1ull << MSR_IR) | | |
8462 | (1ull << MSR_DR) | | |
8463 | (1ull << MSR_PMM) | | |
8464 | (1ull << MSR_RI) | | |
8465 | (1ull << MSR_LE); | |
ba9fd9f1 | 8466 | pcc->mmu_model = POWERPC_MMU_2_06; |
b632a148 DG |
8467 | #if defined(CONFIG_SOFTMMU) |
8468 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
a8891fbf | 8469 | pcc->sps = &POWER7_POWER8_sps; |
b650d6a2 AK |
8470 | #endif |
8471 | pcc->excp_model = POWERPC_EXCP_POWER7; | |
8472 | pcc->bus_model = PPC_FLAGS_INPUT_POWER7; | |
8473 | pcc->bfd_mach = bfd_mach_ppc64; | |
8474 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
8475 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
8476 | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | | |
8477 | POWERPC_FLAG_VSX; | |
8478 | pcc->l1_dcache_size = 0x8000; | |
8479 | pcc->l1_icache_size = 0x8000; | |
382d2db6 | 8480 | pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; |
b650d6a2 AK |
8481 | } |
8482 | ||
60511041 TM |
8483 | static void init_proc_POWER8(CPUPPCState *env) |
8484 | { | |
a2428814 | 8485 | init_proc_book3s_64(env, BOOK3S_CPU_POWER8); |
60511041 TM |
8486 | } |
8487 | ||
03ae4133 AK |
8488 | static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) |
8489 | { | |
a88dced8 AK |
8490 | if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { |
8491 | return true; | |
8492 | } | |
03ae4133 AK |
8493 | if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { |
8494 | return true; | |
8495 | } | |
8496 | if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { | |
8497 | return true; | |
8498 | } | |
8499 | return false; | |
8500 | } | |
8501 | ||
7778a575 BH |
8502 | static bool cpu_has_work_POWER8(CPUState *cs) |
8503 | { | |
8504 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
8505 | CPUPPCState *env = &cpu->env; | |
8506 | ||
8507 | if (cs->halted) { | |
8508 | if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { | |
8509 | return false; | |
8510 | } | |
8511 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && | |
8512 | (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { | |
8513 | return true; | |
8514 | } | |
8515 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && | |
8516 | (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { | |
8517 | return true; | |
8518 | } | |
8519 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && | |
8520 | (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { | |
8521 | return true; | |
8522 | } | |
8523 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && | |
8524 | (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { | |
8525 | return true; | |
8526 | } | |
8527 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && | |
8528 | (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { | |
8529 | return true; | |
8530 | } | |
8531 | if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && | |
8532 | (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { | |
8533 | return true; | |
8534 | } | |
8535 | if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { | |
8536 | return true; | |
8537 | } | |
8538 | return false; | |
8539 | } else { | |
8540 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | |
8541 | } | |
8542 | } | |
8543 | ||
b60c6007 | 8544 | POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) |
8d43ea1c PS |
8545 | { |
8546 | DeviceClass *dc = DEVICE_CLASS(oc); | |
8547 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
7778a575 | 8548 | CPUClass *cc = CPU_CLASS(oc); |
8d43ea1c | 8549 | |
793826cd | 8550 | dc->fw_name = "PowerPC,POWER8"; |
b60c6007 | 8551 | dc->desc = "POWER8"; |
8dfa3a5e | 8552 | dc->props = powerpc_servercpu_properties; |
03ae4133 | 8553 | pcc->pvr_match = ppc_pvr_match_power8; |
8cd2ce7a TH |
8554 | pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; |
8555 | pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | |
60511041 | 8556 | pcc->init_proc = init_proc_POWER8; |
8d43ea1c | 8557 | pcc->check_pow = check_pow_nocheck; |
7778a575 | 8558 | cc->has_work = cpu_has_work_POWER8; |
536492eb | 8559 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | |
8d43ea1c PS |
8560 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | |
8561 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
ce8ca30b | 8562 | PPC_FLOAT_FRSQRTES | |
8d43ea1c | 8563 | PPC_FLOAT_STFIWX | |
c7386080 | 8564 | PPC_FLOAT_EXT | |
8d43ea1c PS |
8565 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | |
8566 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
8567 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
4e080611 | 8568 | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | |
8d43ea1c | 8569 | PPC_SEGMENT_64B | PPC_SLBI | |
b7815375 BH |
8570 | PPC_POPCNTB | PPC_POPCNTWD | |
8571 | PPC_CILDST; | |
86ba37ed | 8572 | pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | |
1fa6c533 | 8573 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | |
29a0e4e9 | 8574 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | |
38a85337 | 8575 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | |
df99d30d | 8576 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | |
3e28c5e3 | 8577 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | |
7778a575 | 8578 | PPC2_TM | PPC2_PM_ISA206; |
9df5a466 | 8579 | pcc->msr_mask = (1ull << MSR_SF) | |
932ccbdd | 8580 | (1ull << MSR_SHV) | |
cdcdda27 | 8581 | (1ull << MSR_TM) | |
9df5a466 TM |
8582 | (1ull << MSR_VR) | |
8583 | (1ull << MSR_VSX) | | |
8584 | (1ull << MSR_EE) | | |
8585 | (1ull << MSR_PR) | | |
8586 | (1ull << MSR_FP) | | |
8587 | (1ull << MSR_ME) | | |
8588 | (1ull << MSR_FE0) | | |
8589 | (1ull << MSR_SE) | | |
8590 | (1ull << MSR_DE) | | |
8591 | (1ull << MSR_FE1) | | |
8592 | (1ull << MSR_IR) | | |
8593 | (1ull << MSR_DR) | | |
8594 | (1ull << MSR_PMM) | | |
8595 | (1ull << MSR_RI) | | |
8596 | (1ull << MSR_LE); | |
aa4bb587 | 8597 | pcc->mmu_model = POWERPC_MMU_2_07; |
8d43ea1c PS |
8598 | #if defined(CONFIG_SOFTMMU) |
8599 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
a8891fbf | 8600 | pcc->sps = &POWER7_POWER8_sps; |
8d43ea1c | 8601 | #endif |
5c94b2a5 | 8602 | pcc->excp_model = POWERPC_EXCP_POWER8; |
8d43ea1c PS |
8603 | pcc->bus_model = PPC_FLAGS_INPUT_POWER7; |
8604 | pcc->bfd_mach = bfd_mach_ppc64; | |
8605 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
8606 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
74f23997 | 8607 | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | |
3e28c5e3 | 8608 | POWERPC_FLAG_VSX | POWERPC_FLAG_TM; |
8d43ea1c PS |
8609 | pcc->l1_dcache_size = 0x8000; |
8610 | pcc->l1_icache_size = 0x8000; | |
382d2db6 | 8611 | pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; |
8d43ea1c | 8612 | } |
a750fc0b | 8613 | |
26a7f129 BH |
8614 | #if !defined(CONFIG_USER_ONLY) |
8615 | ||
8616 | void cpu_ppc_set_papr(PowerPCCPU *cpu) | |
8617 | { | |
8618 | CPUPPCState *env = &cpu->env; | |
61687db2 | 8619 | ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR]; |
6a9c4ef4 | 8620 | ppc_spr_t *amor = &env->spr_cb[SPR_AMOR]; |
26a7f129 BH |
8621 | |
8622 | /* PAPR always has exception vectors in RAM not ROM. To ensure this, | |
8623 | * MSR[IP] should never be set. | |
8624 | * | |
8625 | * We also disallow setting of MSR_HV | |
8626 | */ | |
8627 | env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB); | |
8628 | ||
61687db2 BH |
8629 | /* Set emulated LPCR to not send interrupts to hypervisor. Note that |
8630 | * under KVM, the actual HW LPCR will be set differently by KVM itself, | |
8631 | * the settings below ensure proper operations with TCG in absence of | |
8632 | * a real hypervisor | |
8633 | */ | |
8634 | lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV); | |
8635 | lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1; | |
8636 | ||
7778a575 BH |
8637 | /* P7 and P8 has slightly different PECE bits, mostly because P8 adds |
8638 | * bit 47 and 48 which are reserved on P7. Here we set them all, which | |
8639 | * will work as expected for both implementations | |
8640 | */ | |
8641 | lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | | |
8642 | LPCR_P8_PECE3 | LPCR_P8_PECE4; | |
8643 | ||
61687db2 BH |
8644 | /* We should be followed by a CPU reset but update the active value |
8645 | * just in case... | |
8646 | */ | |
8647 | env->spr[SPR_LPCR] = lpcr->default_value; | |
8648 | ||
6a9c4ef4 BH |
8649 | /* Set a full AMOR so guest can use the AMR as it sees fit */ |
8650 | env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull; | |
8651 | ||
26a7f129 BH |
8652 | /* Tell KVM that we're in PAPR mode */ |
8653 | if (kvm_enabled()) { | |
8654 | kvmppc_set_papr(cpu); | |
8655 | } | |
8656 | } | |
8657 | ||
8658 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
8659 | ||
8660 | #endif /* defined (TARGET_PPC64) */ | |
fd5ed418 | 8661 | |
a750fc0b | 8662 | /*****************************************************************************/ |
60b14d95 | 8663 | /* Generic CPU instantiation routine */ |
cfe34f44 | 8664 | static void init_ppc_proc(PowerPCCPU *cpu) |
a750fc0b | 8665 | { |
cfe34f44 AF |
8666 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
8667 | CPUPPCState *env = &cpu->env; | |
a750fc0b | 8668 | #if !defined(CONFIG_USER_ONLY) |
e1833e1f JM |
8669 | int i; |
8670 | ||
a750fc0b | 8671 | env->irq_inputs = NULL; |
e1833e1f JM |
8672 | /* Set all exception vectors to an invalid address */ |
8673 | for (i = 0; i < POWERPC_EXCP_NB; i++) | |
8674 | env->excp_vectors[i] = (target_ulong)(-1ULL); | |
e1833e1f JM |
8675 | env->ivor_mask = 0x00000000; |
8676 | env->ivpr_mask = 0x00000000; | |
a750fc0b JM |
8677 | /* Default MMU definitions */ |
8678 | env->nb_BATs = 0; | |
8679 | env->nb_tlb = 0; | |
8680 | env->nb_ways = 0; | |
1c53accc | 8681 | env->tlb_type = TLB_NONE; |
f2e63a42 | 8682 | #endif |
a750fc0b JM |
8683 | /* Register SPR common to all PowerPC implementations */ |
8684 | gen_spr_generic(env); | |
8685 | spr_register(env, SPR_PVR, "PVR", | |
a139aa17 NF |
8686 | /* Linux permits userspace to read PVR */ |
8687 | #if defined(CONFIG_LINUX_USER) | |
8688 | &spr_read_generic, | |
8689 | #else | |
8690 | SPR_NOACCESS, | |
8691 | #endif | |
8692 | SPR_NOACCESS, | |
a750fc0b | 8693 | &spr_read_generic, SPR_NOACCESS, |
cfe34f44 | 8694 | pcc->pvr); |
80d11f44 | 8695 | /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ |
cfe34f44 AF |
8696 | if (pcc->svr != POWERPC_SVR_NONE) { |
8697 | if (pcc->svr & POWERPC_SVR_E500) { | |
80d11f44 JM |
8698 | spr_register(env, SPR_E500_SVR, "SVR", |
8699 | SPR_NOACCESS, SPR_NOACCESS, | |
8700 | &spr_read_generic, SPR_NOACCESS, | |
cfe34f44 | 8701 | pcc->svr & ~POWERPC_SVR_E500); |
80d11f44 JM |
8702 | } else { |
8703 | spr_register(env, SPR_SVR, "SVR", | |
8704 | SPR_NOACCESS, SPR_NOACCESS, | |
8705 | &spr_read_generic, SPR_NOACCESS, | |
cfe34f44 | 8706 | pcc->svr); |
80d11f44 JM |
8707 | } |
8708 | } | |
a750fc0b | 8709 | /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ |
cfe34f44 | 8710 | (*pcc->init_proc)(env); |
2cf3eb6d | 8711 | |
25ba3a68 JM |
8712 | /* MSR bits & flags consistency checks */ |
8713 | if (env->msr_mask & (1 << 25)) { | |
8714 | switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { | |
8715 | case POWERPC_FLAG_SPE: | |
8716 | case POWERPC_FLAG_VRE: | |
8717 | break; | |
8718 | default: | |
8719 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8720 | "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); | |
8721 | exit(1); | |
8722 | } | |
8723 | } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { | |
8724 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8725 | "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); | |
8726 | exit(1); | |
8727 | } | |
8728 | if (env->msr_mask & (1 << 17)) { | |
8729 | switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { | |
8730 | case POWERPC_FLAG_TGPR: | |
8731 | case POWERPC_FLAG_CE: | |
8732 | break; | |
8733 | default: | |
8734 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8735 | "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); | |
8736 | exit(1); | |
8737 | } | |
8738 | } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { | |
8739 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8740 | "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); | |
8741 | exit(1); | |
8742 | } | |
8743 | if (env->msr_mask & (1 << 10)) { | |
8744 | switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | | |
8745 | POWERPC_FLAG_UBLE)) { | |
8746 | case POWERPC_FLAG_SE: | |
8747 | case POWERPC_FLAG_DWE: | |
8748 | case POWERPC_FLAG_UBLE: | |
8749 | break; | |
8750 | default: | |
8751 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8752 | "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " | |
8753 | "POWERPC_FLAG_UBLE\n"); | |
8754 | exit(1); | |
8755 | } | |
8756 | } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | | |
8757 | POWERPC_FLAG_UBLE)) { | |
8758 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8759 | "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " | |
8760 | "POWERPC_FLAG_UBLE\n"); | |
8761 | exit(1); | |
8762 | } | |
8763 | if (env->msr_mask & (1 << 9)) { | |
8764 | switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { | |
8765 | case POWERPC_FLAG_BE: | |
8766 | case POWERPC_FLAG_DE: | |
8767 | break; | |
8768 | default: | |
8769 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8770 | "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); | |
8771 | exit(1); | |
8772 | } | |
8773 | } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { | |
8774 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8775 | "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); | |
8776 | exit(1); | |
8777 | } | |
8778 | if (env->msr_mask & (1 << 2)) { | |
8779 | switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { | |
8780 | case POWERPC_FLAG_PX: | |
8781 | case POWERPC_FLAG_PMM: | |
8782 | break; | |
8783 | default: | |
8784 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8785 | "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); | |
8786 | exit(1); | |
8787 | } | |
8788 | } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { | |
8789 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
8790 | "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); | |
8791 | exit(1); | |
8792 | } | |
4018bae9 JM |
8793 | if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { |
8794 | fprintf(stderr, "PowerPC flags inconsistency\n" | |
8795 | "Should define the time-base and decrementer clock source\n"); | |
8796 | exit(1); | |
8797 | } | |
a750fc0b | 8798 | /* Allocate TLBs buffer when needed */ |
f2e63a42 | 8799 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
8800 | if (env->nb_tlb != 0) { |
8801 | int nb_tlb = env->nb_tlb; | |
8802 | if (env->id_tlbs != 0) | |
8803 | nb_tlb *= 2; | |
1c53accc AG |
8804 | switch (env->tlb_type) { |
8805 | case TLB_6XX: | |
7267c094 | 8806 | env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t)); |
1c53accc AG |
8807 | break; |
8808 | case TLB_EMB: | |
7267c094 | 8809 | env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t)); |
1c53accc AG |
8810 | break; |
8811 | case TLB_MAS: | |
7267c094 | 8812 | env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t)); |
1c53accc AG |
8813 | break; |
8814 | } | |
a750fc0b JM |
8815 | /* Pre-compute some useful values */ |
8816 | env->tlb_per_way = env->nb_tlb / env->nb_ways; | |
8817 | } | |
a750fc0b JM |
8818 | if (env->irq_inputs == NULL) { |
8819 | fprintf(stderr, "WARNING: no internal IRQ controller registered.\n" | |
5cbdb3a3 | 8820 | " Attempt QEMU to crash very soon !\n"); |
a750fc0b JM |
8821 | } |
8822 | #endif | |
2f462816 JM |
8823 | if (env->check_pow == NULL) { |
8824 | fprintf(stderr, "WARNING: no power management check handler " | |
8825 | "registered.\n" | |
5cbdb3a3 | 8826 | " Attempt QEMU to crash very soon !\n"); |
2f462816 | 8827 | } |
a750fc0b JM |
8828 | } |
8829 | ||
8830 | #if defined(PPC_DUMP_CPU) | |
8831 | static void dump_ppc_sprs (CPUPPCState *env) | |
8832 | { | |
8833 | ppc_spr_t *spr; | |
8834 | #if !defined(CONFIG_USER_ONLY) | |
8835 | uint32_t sr, sw; | |
8836 | #endif | |
8837 | uint32_t ur, uw; | |
8838 | int i, j, n; | |
8839 | ||
8840 | printf("Special purpose registers:\n"); | |
8841 | for (i = 0; i < 32; i++) { | |
8842 | for (j = 0; j < 32; j++) { | |
8843 | n = (i << 5) | j; | |
8844 | spr = &env->spr_cb[n]; | |
8845 | uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; | |
8846 | ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; | |
8847 | #if !defined(CONFIG_USER_ONLY) | |
8848 | sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; | |
8849 | sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; | |
8850 | if (sw || sr || uw || ur) { | |
8851 | printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", | |
8852 | (i << 5) | j, (i << 5) | j, spr->name, | |
8853 | sw ? 'w' : '-', sr ? 'r' : '-', | |
8854 | uw ? 'w' : '-', ur ? 'r' : '-'); | |
8855 | } | |
8856 | #else | |
8857 | if (uw || ur) { | |
8858 | printf("SPR: %4d (%03x) %-8s u%c%c\n", | |
8859 | (i << 5) | j, (i << 5) | j, spr->name, | |
8860 | uw ? 'w' : '-', ur ? 'r' : '-'); | |
8861 | } | |
8862 | #endif | |
8863 | } | |
8864 | } | |
8865 | fflush(stdout); | |
8866 | fflush(stderr); | |
8867 | } | |
8868 | #endif | |
8869 | ||
8870 | /*****************************************************************************/ | |
a750fc0b | 8871 | |
a750fc0b JM |
8872 | /* Opcode types */ |
8873 | enum { | |
8874 | PPC_DIRECT = 0, /* Opcode routine */ | |
8875 | PPC_INDIRECT = 1, /* Indirect opcode table */ | |
8876 | }; | |
8877 | ||
54ff58bb BR |
8878 | #define PPC_OPCODE_MASK 0x3 |
8879 | ||
a750fc0b JM |
8880 | static inline int is_indirect_opcode (void *handler) |
8881 | { | |
54ff58bb | 8882 | return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; |
a750fc0b JM |
8883 | } |
8884 | ||
c227f099 | 8885 | static inline opc_handler_t **ind_table(void *handler) |
a750fc0b | 8886 | { |
54ff58bb | 8887 | return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); |
a750fc0b JM |
8888 | } |
8889 | ||
8890 | /* Instruction table creation */ | |
8891 | /* Opcodes tables creation */ | |
c227f099 | 8892 | static void fill_new_table (opc_handler_t **table, int len) |
a750fc0b JM |
8893 | { |
8894 | int i; | |
8895 | ||
8896 | for (i = 0; i < len; i++) | |
8897 | table[i] = &invalid_handler; | |
8898 | } | |
8899 | ||
c227f099 | 8900 | static int create_new_table (opc_handler_t **table, unsigned char idx) |
a750fc0b | 8901 | { |
c227f099 | 8902 | opc_handler_t **tmp; |
a750fc0b | 8903 | |
54ff58bb BR |
8904 | tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); |
8905 | fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); | |
5724753e | 8906 | table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); |
a750fc0b JM |
8907 | |
8908 | return 0; | |
8909 | } | |
8910 | ||
c227f099 AL |
8911 | static int insert_in_table (opc_handler_t **table, unsigned char idx, |
8912 | opc_handler_t *handler) | |
a750fc0b JM |
8913 | { |
8914 | if (table[idx] != &invalid_handler) | |
8915 | return -1; | |
8916 | table[idx] = handler; | |
8917 | ||
8918 | return 0; | |
8919 | } | |
8920 | ||
c227f099 AL |
8921 | static int register_direct_insn (opc_handler_t **ppc_opcodes, |
8922 | unsigned char idx, opc_handler_t *handler) | |
a750fc0b JM |
8923 | { |
8924 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { | |
8925 | printf("*** ERROR: opcode %02x already assigned in main " | |
8926 | "opcode table\n", idx); | |
4c1b1bfe JM |
8927 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
8928 | printf(" Registered handler '%s' - new handler '%s'\n", | |
8929 | ppc_opcodes[idx]->oname, handler->oname); | |
8930 | #endif | |
a750fc0b JM |
8931 | return -1; |
8932 | } | |
8933 | ||
8934 | return 0; | |
8935 | } | |
8936 | ||
c227f099 | 8937 | static int register_ind_in_table (opc_handler_t **table, |
a750fc0b | 8938 | unsigned char idx1, unsigned char idx2, |
c227f099 | 8939 | opc_handler_t *handler) |
a750fc0b JM |
8940 | { |
8941 | if (table[idx1] == &invalid_handler) { | |
8942 | if (create_new_table(table, idx1) < 0) { | |
8943 | printf("*** ERROR: unable to create indirect table " | |
8944 | "idx=%02x\n", idx1); | |
8945 | return -1; | |
8946 | } | |
8947 | } else { | |
8948 | if (!is_indirect_opcode(table[idx1])) { | |
8949 | printf("*** ERROR: idx %02x already assigned to a direct " | |
8950 | "opcode\n", idx1); | |
4c1b1bfe JM |
8951 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
8952 | printf(" Registered handler '%s' - new handler '%s'\n", | |
8953 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
8954 | #endif | |
a750fc0b JM |
8955 | return -1; |
8956 | } | |
3a607854 | 8957 | } |
a750fc0b JM |
8958 | if (handler != NULL && |
8959 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { | |
8960 | printf("*** ERROR: opcode %02x already assigned in " | |
8961 | "opcode table %02x\n", idx2, idx1); | |
4c1b1bfe JM |
8962 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
8963 | printf(" Registered handler '%s' - new handler '%s'\n", | |
8964 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
8965 | #endif | |
a750fc0b | 8966 | return -1; |
3a607854 | 8967 | } |
a750fc0b JM |
8968 | |
8969 | return 0; | |
8970 | } | |
8971 | ||
c227f099 | 8972 | static int register_ind_insn (opc_handler_t **ppc_opcodes, |
a750fc0b | 8973 | unsigned char idx1, unsigned char idx2, |
c227f099 | 8974 | opc_handler_t *handler) |
a750fc0b | 8975 | { |
74c373e4 | 8976 | return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
a750fc0b JM |
8977 | } |
8978 | ||
c227f099 | 8979 | static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
a750fc0b | 8980 | unsigned char idx1, unsigned char idx2, |
c227f099 | 8981 | unsigned char idx3, opc_handler_t *handler) |
a750fc0b JM |
8982 | { |
8983 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
8984 | printf("*** ERROR: unable to join indirect table idx " | |
8985 | "[%02x-%02x]\n", idx1, idx2); | |
8986 | return -1; | |
8987 | } | |
8988 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, | |
8989 | handler) < 0) { | |
8990 | printf("*** ERROR: unable to insert opcode " | |
8991 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
8992 | return -1; | |
8993 | } | |
8994 | ||
8995 | return 0; | |
8996 | } | |
8997 | ||
c227f099 | 8998 | static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
a750fc0b JM |
8999 | { |
9000 | if (insn->opc2 != 0xFF) { | |
9001 | if (insn->opc3 != 0xFF) { | |
9002 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
9003 | insn->opc3, &insn->handler) < 0) | |
9004 | return -1; | |
9005 | } else { | |
9006 | if (register_ind_insn(ppc_opcodes, insn->opc1, | |
9007 | insn->opc2, &insn->handler) < 0) | |
9008 | return -1; | |
9009 | } | |
9010 | } else { | |
9011 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) | |
9012 | return -1; | |
9013 | } | |
9014 | ||
9015 | return 0; | |
9016 | } | |
9017 | ||
c227f099 | 9018 | static int test_opcode_table (opc_handler_t **table, int len) |
a750fc0b JM |
9019 | { |
9020 | int i, count, tmp; | |
9021 | ||
9022 | for (i = 0, count = 0; i < len; i++) { | |
9023 | /* Consistency fixup */ | |
9024 | if (table[i] == NULL) | |
9025 | table[i] = &invalid_handler; | |
9026 | if (table[i] != &invalid_handler) { | |
9027 | if (is_indirect_opcode(table[i])) { | |
54ff58bb BR |
9028 | tmp = test_opcode_table(ind_table(table[i]), |
9029 | PPC_CPU_INDIRECT_OPCODES_LEN); | |
a750fc0b JM |
9030 | if (tmp == 0) { |
9031 | free(table[i]); | |
9032 | table[i] = &invalid_handler; | |
9033 | } else { | |
9034 | count++; | |
9035 | } | |
9036 | } else { | |
9037 | count++; | |
9038 | } | |
9039 | } | |
9040 | } | |
9041 | ||
9042 | return count; | |
9043 | } | |
9044 | ||
c227f099 | 9045 | static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
a750fc0b | 9046 | { |
54ff58bb | 9047 | if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) |
a750fc0b JM |
9048 | printf("*** WARNING: no opcode defined !\n"); |
9049 | } | |
9050 | ||
9051 | /*****************************************************************************/ | |
2985b86b | 9052 | static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) |
a750fc0b | 9053 | { |
2985b86b AF |
9054 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
9055 | CPUPPCState *env = &cpu->env; | |
c227f099 | 9056 | opcode_t *opc; |
a750fc0b | 9057 | |
54ff58bb | 9058 | fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN); |
5c55ff99 | 9059 | for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { |
cfe34f44 AF |
9060 | if (((opc->handler.type & pcc->insns_flags) != 0) || |
9061 | ((opc->handler.type2 & pcc->insns_flags2) != 0)) { | |
a750fc0b | 9062 | if (register_insn(env->opcodes, opc) < 0) { |
2985b86b | 9063 | error_setg(errp, "ERROR initializing PowerPC instruction " |
312fd5f2 | 9064 | "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, |
2985b86b AF |
9065 | opc->opc3); |
9066 | return; | |
a750fc0b JM |
9067 | } |
9068 | } | |
9069 | } | |
c227f099 | 9070 | fix_opcode_tables(env->opcodes); |
a750fc0b JM |
9071 | fflush(stdout); |
9072 | fflush(stderr); | |
a750fc0b JM |
9073 | } |
9074 | ||
9075 | #if defined(PPC_DUMP_CPU) | |
25ba3a68 | 9076 | static void dump_ppc_insns (CPUPPCState *env) |
a750fc0b | 9077 | { |
c227f099 | 9078 | opc_handler_t **table, *handler; |
b55266b5 | 9079 | const char *p, *q; |
a750fc0b JM |
9080 | uint8_t opc1, opc2, opc3; |
9081 | ||
9082 | printf("Instructions set:\n"); | |
9083 | /* opc1 is 6 bits long */ | |
54ff58bb | 9084 | for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { |
a750fc0b JM |
9085 | table = env->opcodes; |
9086 | handler = table[opc1]; | |
9087 | if (is_indirect_opcode(handler)) { | |
9088 | /* opc2 is 5 bits long */ | |
54ff58bb | 9089 | for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { |
a750fc0b JM |
9090 | table = env->opcodes; |
9091 | handler = env->opcodes[opc1]; | |
9092 | table = ind_table(handler); | |
9093 | handler = table[opc2]; | |
9094 | if (is_indirect_opcode(handler)) { | |
9095 | table = ind_table(handler); | |
9096 | /* opc3 is 5 bits long */ | |
54ff58bb BR |
9097 | for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; |
9098 | opc3++) { | |
a750fc0b JM |
9099 | handler = table[opc3]; |
9100 | if (handler->handler != &gen_invalid) { | |
4c1b1bfe JM |
9101 | /* Special hack to properly dump SPE insns */ |
9102 | p = strchr(handler->oname, '_'); | |
9103 | if (p == NULL) { | |
9104 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
9105 | "%s\n", | |
9106 | opc1, opc2, opc3, opc1, | |
9107 | (opc3 << 5) | opc2, | |
9108 | handler->oname); | |
9109 | } else { | |
9110 | q = "speundef"; | |
9111 | if ((p - handler->oname) != strlen(q) || | |
9112 | memcmp(handler->oname, q, strlen(q)) != 0) { | |
9113 | /* First instruction */ | |
9114 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
9115 | "%.*s\n", | |
9116 | opc1, opc2 << 1, opc3, opc1, | |
9117 | (opc3 << 6) | (opc2 << 1), | |
9118 | (int)(p - handler->oname), | |
9119 | handler->oname); | |
9120 | } | |
9121 | if (strcmp(p + 1, q) != 0) { | |
9122 | /* Second instruction */ | |
9123 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
9124 | "%s\n", | |
9125 | opc1, (opc2 << 1) | 1, opc3, opc1, | |
9126 | (opc3 << 6) | (opc2 << 1) | 1, | |
9127 | p + 1); | |
9128 | } | |
9129 | } | |
a750fc0b JM |
9130 | } |
9131 | } | |
9132 | } else { | |
9133 | if (handler->handler != &gen_invalid) { | |
9134 | printf("INSN: %02x %02x -- (%02d %04d) : %s\n", | |
9135 | opc1, opc2, opc1, opc2, handler->oname); | |
9136 | } | |
9137 | } | |
9138 | } | |
9139 | } else { | |
9140 | if (handler->handler != &gen_invalid) { | |
9141 | printf("INSN: %02x -- -- (%02d ----) : %s\n", | |
9142 | opc1, opc1, handler->oname); | |
9143 | } | |
9144 | } | |
9145 | } | |
9146 | } | |
3a607854 | 9147 | #endif |
a750fc0b | 9148 | |
87601e2d GK |
9149 | static bool avr_need_swap(CPUPPCState *env) |
9150 | { | |
9151 | #ifdef HOST_WORDS_BIGENDIAN | |
ea499e71 | 9152 | return msr_le; |
87601e2d | 9153 | #else |
ea499e71 | 9154 | return !msr_le; |
87601e2d GK |
9155 | #endif |
9156 | } | |
9157 | ||
1328c2bf | 9158 | static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
24951522 AJ |
9159 | { |
9160 | if (n < 32) { | |
9161 | stfq_p(mem_buf, env->fpr[n]); | |
385abeb3 | 9162 | ppc_maybe_bswap_register(env, mem_buf, 8); |
24951522 AJ |
9163 | return 8; |
9164 | } | |
9165 | if (n == 32) { | |
5a576fb3 | 9166 | stl_p(mem_buf, env->fpscr); |
385abeb3 | 9167 | ppc_maybe_bswap_register(env, mem_buf, 4); |
24951522 AJ |
9168 | return 4; |
9169 | } | |
9170 | return 0; | |
9171 | } | |
9172 | ||
1328c2bf | 9173 | static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
24951522 AJ |
9174 | { |
9175 | if (n < 32) { | |
385abeb3 | 9176 | ppc_maybe_bswap_register(env, mem_buf, 8); |
24951522 AJ |
9177 | env->fpr[n] = ldfq_p(mem_buf); |
9178 | return 8; | |
9179 | } | |
9180 | if (n == 32) { | |
385abeb3 | 9181 | ppc_maybe_bswap_register(env, mem_buf, 4); |
d6478bc7 | 9182 | helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff); |
24951522 AJ |
9183 | return 4; |
9184 | } | |
9185 | return 0; | |
9186 | } | |
9187 | ||
1328c2bf | 9188 | static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
b4f8d821 AJ |
9189 | { |
9190 | if (n < 32) { | |
87601e2d GK |
9191 | if (!avr_need_swap(env)) { |
9192 | stq_p(mem_buf, env->avr[n].u64[0]); | |
9193 | stq_p(mem_buf+8, env->avr[n].u64[1]); | |
9194 | } else { | |
9195 | stq_p(mem_buf, env->avr[n].u64[1]); | |
9196 | stq_p(mem_buf+8, env->avr[n].u64[0]); | |
9197 | } | |
ea499e71 GK |
9198 | ppc_maybe_bswap_register(env, mem_buf, 8); |
9199 | ppc_maybe_bswap_register(env, mem_buf + 8, 8); | |
b4f8d821 AJ |
9200 | return 16; |
9201 | } | |
70976a79 | 9202 | if (n == 32) { |
b4f8d821 | 9203 | stl_p(mem_buf, env->vscr); |
ea499e71 | 9204 | ppc_maybe_bswap_register(env, mem_buf, 4); |
b4f8d821 AJ |
9205 | return 4; |
9206 | } | |
70976a79 | 9207 | if (n == 33) { |
b4f8d821 | 9208 | stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); |
ea499e71 | 9209 | ppc_maybe_bswap_register(env, mem_buf, 4); |
b4f8d821 AJ |
9210 | return 4; |
9211 | } | |
9212 | return 0; | |
9213 | } | |
9214 | ||
1328c2bf | 9215 | static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
b4f8d821 AJ |
9216 | { |
9217 | if (n < 32) { | |
ea499e71 GK |
9218 | ppc_maybe_bswap_register(env, mem_buf, 8); |
9219 | ppc_maybe_bswap_register(env, mem_buf + 8, 8); | |
87601e2d GK |
9220 | if (!avr_need_swap(env)) { |
9221 | env->avr[n].u64[0] = ldq_p(mem_buf); | |
9222 | env->avr[n].u64[1] = ldq_p(mem_buf+8); | |
9223 | } else { | |
9224 | env->avr[n].u64[1] = ldq_p(mem_buf); | |
9225 | env->avr[n].u64[0] = ldq_p(mem_buf+8); | |
9226 | } | |
b4f8d821 AJ |
9227 | return 16; |
9228 | } | |
70976a79 | 9229 | if (n == 32) { |
ea499e71 | 9230 | ppc_maybe_bswap_register(env, mem_buf, 4); |
b4f8d821 AJ |
9231 | env->vscr = ldl_p(mem_buf); |
9232 | return 4; | |
9233 | } | |
70976a79 | 9234 | if (n == 33) { |
ea499e71 | 9235 | ppc_maybe_bswap_register(env, mem_buf, 4); |
b4f8d821 AJ |
9236 | env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); |
9237 | return 4; | |
9238 | } | |
9239 | return 0; | |
9240 | } | |
9241 | ||
1328c2bf | 9242 | static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
688890f7 AJ |
9243 | { |
9244 | if (n < 32) { | |
9245 | #if defined(TARGET_PPC64) | |
9246 | stl_p(mem_buf, env->gpr[n] >> 32); | |
95f5b540 | 9247 | ppc_maybe_bswap_register(env, mem_buf, 4); |
688890f7 AJ |
9248 | #else |
9249 | stl_p(mem_buf, env->gprh[n]); | |
9250 | #endif | |
9251 | return 4; | |
9252 | } | |
70976a79 | 9253 | if (n == 32) { |
688890f7 | 9254 | stq_p(mem_buf, env->spe_acc); |
95f5b540 | 9255 | ppc_maybe_bswap_register(env, mem_buf, 8); |
688890f7 AJ |
9256 | return 8; |
9257 | } | |
70976a79 | 9258 | if (n == 33) { |
d34defbc | 9259 | stl_p(mem_buf, env->spe_fscr); |
95f5b540 | 9260 | ppc_maybe_bswap_register(env, mem_buf, 4); |
688890f7 AJ |
9261 | return 4; |
9262 | } | |
9263 | return 0; | |
9264 | } | |
9265 | ||
1328c2bf | 9266 | static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
688890f7 AJ |
9267 | { |
9268 | if (n < 32) { | |
9269 | #if defined(TARGET_PPC64) | |
9270 | target_ulong lo = (uint32_t)env->gpr[n]; | |
95f5b540 GK |
9271 | target_ulong hi; |
9272 | ||
9273 | ppc_maybe_bswap_register(env, mem_buf, 4); | |
9274 | ||
9275 | hi = (target_ulong)ldl_p(mem_buf) << 32; | |
688890f7 AJ |
9276 | env->gpr[n] = lo | hi; |
9277 | #else | |
9278 | env->gprh[n] = ldl_p(mem_buf); | |
9279 | #endif | |
9280 | return 4; | |
9281 | } | |
70976a79 | 9282 | if (n == 32) { |
95f5b540 | 9283 | ppc_maybe_bswap_register(env, mem_buf, 8); |
688890f7 AJ |
9284 | env->spe_acc = ldq_p(mem_buf); |
9285 | return 8; | |
9286 | } | |
70976a79 | 9287 | if (n == 33) { |
95f5b540 | 9288 | ppc_maybe_bswap_register(env, mem_buf, 4); |
d34defbc | 9289 | env->spe_fscr = ldl_p(mem_buf); |
688890f7 AJ |
9290 | return 4; |
9291 | } | |
9292 | return 0; | |
9293 | } | |
9294 | ||
1438eff3 AB |
9295 | static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
9296 | { | |
9297 | if (n < 32) { | |
9298 | stq_p(mem_buf, env->vsr[n]); | |
9299 | ppc_maybe_bswap_register(env, mem_buf, 8); | |
9300 | return 8; | |
9301 | } | |
9302 | return 0; | |
9303 | } | |
9304 | ||
9305 | static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) | |
9306 | { | |
9307 | if (n < 32) { | |
9308 | ppc_maybe_bswap_register(env, mem_buf, 8); | |
9309 | env->vsr[n] = ldq_p(mem_buf); | |
9310 | return 8; | |
9311 | } | |
9312 | return 0; | |
9313 | } | |
9314 | ||
55e5c285 | 9315 | static int ppc_fixup_cpu(PowerPCCPU *cpu) |
12b1143b | 9316 | { |
55e5c285 AF |
9317 | CPUPPCState *env = &cpu->env; |
9318 | ||
12b1143b DG |
9319 | /* TCG doesn't (yet) emulate some groups of instructions that |
9320 | * are implemented on some otherwise supported CPUs (e.g. VSX | |
9321 | * and decimal floating point instructions on POWER7). We | |
9322 | * remove unsupported instruction groups from the cpu state's | |
9323 | * instruction masks and hope the guest can cope. For at | |
9324 | * least the pseries machine, the unavailability of these | |
9325 | * instructions can be advertised to the guest via the device | |
9326 | * tree. */ | |
9327 | if ((env->insns_flags & ~PPC_TCG_INSNS) | |
9328 | || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { | |
9329 | fprintf(stderr, "Warning: Disabling some instructions which are not " | |
9330 | "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n", | |
9331 | env->insns_flags & ~PPC_TCG_INSNS, | |
9332 | env->insns_flags2 & ~PPC_TCG_INSNS2); | |
9333 | } | |
9334 | env->insns_flags &= PPC_TCG_INSNS; | |
9335 | env->insns_flags2 &= PPC_TCG_INSNS2; | |
9336 | return 0; | |
9337 | } | |
9338 | ||
292363e1 AF |
9339 | static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc) |
9340 | { | |
9341 | #ifdef TARGET_PPCEMB | |
9342 | return pcc->mmu_model == POWERPC_MMU_BOOKE || | |
9343 | pcc->mmu_model == POWERPC_MMU_SOFT_4xx || | |
9344 | pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z; | |
9345 | #else | |
9346 | return true; | |
9347 | #endif | |
9348 | } | |
9349 | ||
4776ce60 | 9350 | static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) |
a750fc0b | 9351 | { |
22169d41 | 9352 | CPUState *cs = CPU(dev); |
4776ce60 | 9353 | PowerPCCPU *cpu = POWERPC_CPU(dev); |
2985b86b | 9354 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
2985b86b | 9355 | Error *local_err = NULL; |
fe828a4d MQ |
9356 | #if !defined(CONFIG_USER_ONLY) |
9357 | int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1; | |
9358 | #endif | |
9359 | ||
9360 | #if !defined(CONFIG_USER_ONLY) | |
9361 | if (smp_threads > max_smt) { | |
5e95acc8 AF |
9362 | error_setg(errp, "Cannot support more than %d threads on PPC with %s", |
9363 | max_smt, kvm_enabled() ? "KVM" : "TCG"); | |
9364 | return; | |
fe828a4d | 9365 | } |
5ec83c73 BR |
9366 | if (!is_power_of_2(smp_threads)) { |
9367 | error_setg(errp, "Cannot support %d threads on PPC with %s, " | |
9368 | "threads count must be a power of 2.", | |
9369 | smp_threads, kvm_enabled() ? "KVM" : "TCG"); | |
9370 | return; | |
9371 | } | |
6dd0f834 BR |
9372 | #endif |
9373 | ||
4bad9e39 | 9374 | cpu_exec_init(cs, &local_err); |
6dd0f834 BR |
9375 | if (local_err != NULL) { |
9376 | error_propagate(errp, local_err); | |
9377 | return; | |
9378 | } | |
0ce470cd | 9379 | |
6dd0f834 | 9380 | #if !defined(CONFIG_USER_ONLY) |
0ce470cd AK |
9381 | cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt |
9382 | + (cs->cpu_index % smp_threads); | |
41264b38 GK |
9383 | |
9384 | if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->cpu_dt_id)) { | |
9385 | error_setg(errp, "Can't create CPU with id %d in KVM", cpu->cpu_dt_id); | |
9386 | error_append_hint(errp, "Adjust the number of cpus to %d " | |
9387 | "or try to raise the number of threads per core\n", | |
9388 | cpu->cpu_dt_id * smp_threads / max_smt); | |
9389 | return; | |
9390 | } | |
fe828a4d | 9391 | #endif |
4656e1f0 | 9392 | |
0ce470cd | 9393 | if (tcg_enabled()) { |
55e5c285 | 9394 | if (ppc_fixup_cpu(cpu) != 0) { |
2985b86b AF |
9395 | error_setg(errp, "Unable to emulate selected CPU with TCG"); |
9396 | return; | |
12b1143b DG |
9397 | } |
9398 | } | |
9399 | ||
4d7fb187 | 9400 | #if defined(TARGET_PPCEMB) |
292363e1 AF |
9401 | if (!ppc_cpu_is_valid(pcc)) { |
9402 | error_setg(errp, "CPU does not possess a BookE or 4xx MMU. " | |
4d7fb187 AF |
9403 | "Please use qemu-system-ppc or qemu-system-ppc64 instead " |
9404 | "or choose another CPU model."); | |
9405 | return; | |
9406 | } | |
9407 | #endif | |
9408 | ||
2985b86b AF |
9409 | create_ppc_opcodes(cpu, &local_err); |
9410 | if (local_err != NULL) { | |
9411 | error_propagate(errp, local_err); | |
9412 | return; | |
9413 | } | |
cfe34f44 | 9414 | init_ppc_proc(cpu); |
24951522 | 9415 | |
cfe34f44 | 9416 | if (pcc->insns_flags & PPC_FLOAT) { |
22169d41 | 9417 | gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, |
24951522 AJ |
9418 | 33, "power-fpu.xml", 0); |
9419 | } | |
cfe34f44 | 9420 | if (pcc->insns_flags & PPC_ALTIVEC) { |
22169d41 | 9421 | gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, |
b4f8d821 AJ |
9422 | 34, "power-altivec.xml", 0); |
9423 | } | |
cfe34f44 | 9424 | if (pcc->insns_flags & PPC_SPE) { |
22169d41 | 9425 | gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, |
688890f7 AJ |
9426 | 34, "power-spe.xml", 0); |
9427 | } | |
1438eff3 AB |
9428 | if (pcc->insns_flags2 & PPC2_VSX) { |
9429 | gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, | |
9430 | 32, "power-vsx.xml", 0); | |
9431 | } | |
688890f7 | 9432 | |
14a10fc3 AF |
9433 | qemu_init_vcpu(cs); |
9434 | ||
4776ce60 AF |
9435 | pcc->parent_realize(dev, errp); |
9436 | ||
a750fc0b | 9437 | #if defined(PPC_DUMP_CPU) |
3a607854 | 9438 | { |
22169d41 | 9439 | CPUPPCState *env = &cpu->env; |
b55266b5 | 9440 | const char *mmu_model, *excp_model, *bus_model; |
a750fc0b JM |
9441 | switch (env->mmu_model) { |
9442 | case POWERPC_MMU_32B: | |
9443 | mmu_model = "PowerPC 32"; | |
9444 | break; | |
a750fc0b JM |
9445 | case POWERPC_MMU_SOFT_6xx: |
9446 | mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; | |
9447 | break; | |
9448 | case POWERPC_MMU_SOFT_74xx: | |
9449 | mmu_model = "PowerPC 74xx with software driven TLBs"; | |
9450 | break; | |
9451 | case POWERPC_MMU_SOFT_4xx: | |
9452 | mmu_model = "PowerPC 4xx with software driven TLBs"; | |
9453 | break; | |
9454 | case POWERPC_MMU_SOFT_4xx_Z: | |
9455 | mmu_model = "PowerPC 4xx with software driven TLBs " | |
9456 | "and zones protections"; | |
9457 | break; | |
b4095fed JM |
9458 | case POWERPC_MMU_REAL: |
9459 | mmu_model = "PowerPC real mode only"; | |
9460 | break; | |
9461 | case POWERPC_MMU_MPC8xx: | |
9462 | mmu_model = "PowerPC MPC8xx"; | |
a750fc0b JM |
9463 | break; |
9464 | case POWERPC_MMU_BOOKE: | |
9465 | mmu_model = "PowerPC BookE"; | |
9466 | break; | |
01662f3e AG |
9467 | case POWERPC_MMU_BOOKE206: |
9468 | mmu_model = "PowerPC BookE 2.06"; | |
a750fc0b | 9469 | break; |
b4095fed JM |
9470 | case POWERPC_MMU_601: |
9471 | mmu_model = "PowerPC 601"; | |
9472 | break; | |
00af685f JM |
9473 | #if defined (TARGET_PPC64) |
9474 | case POWERPC_MMU_64B: | |
9475 | mmu_model = "PowerPC 64"; | |
9476 | break; | |
00af685f | 9477 | #endif |
a750fc0b JM |
9478 | default: |
9479 | mmu_model = "Unknown or invalid"; | |
9480 | break; | |
9481 | } | |
9482 | switch (env->excp_model) { | |
9483 | case POWERPC_EXCP_STD: | |
9484 | excp_model = "PowerPC"; | |
9485 | break; | |
9486 | case POWERPC_EXCP_40x: | |
9487 | excp_model = "PowerPC 40x"; | |
9488 | break; | |
9489 | case POWERPC_EXCP_601: | |
9490 | excp_model = "PowerPC 601"; | |
9491 | break; | |
9492 | case POWERPC_EXCP_602: | |
9493 | excp_model = "PowerPC 602"; | |
9494 | break; | |
9495 | case POWERPC_EXCP_603: | |
9496 | excp_model = "PowerPC 603"; | |
9497 | break; | |
9498 | case POWERPC_EXCP_603E: | |
9499 | excp_model = "PowerPC 603e"; | |
9500 | break; | |
9501 | case POWERPC_EXCP_604: | |
9502 | excp_model = "PowerPC 604"; | |
9503 | break; | |
9504 | case POWERPC_EXCP_7x0: | |
9505 | excp_model = "PowerPC 740/750"; | |
9506 | break; | |
9507 | case POWERPC_EXCP_7x5: | |
9508 | excp_model = "PowerPC 745/755"; | |
9509 | break; | |
9510 | case POWERPC_EXCP_74xx: | |
9511 | excp_model = "PowerPC 74xx"; | |
9512 | break; | |
a750fc0b JM |
9513 | case POWERPC_EXCP_BOOKE: |
9514 | excp_model = "PowerPC BookE"; | |
9515 | break; | |
00af685f JM |
9516 | #if defined (TARGET_PPC64) |
9517 | case POWERPC_EXCP_970: | |
9518 | excp_model = "PowerPC 970"; | |
9519 | break; | |
9520 | #endif | |
a750fc0b JM |
9521 | default: |
9522 | excp_model = "Unknown or invalid"; | |
9523 | break; | |
9524 | } | |
9525 | switch (env->bus_model) { | |
9526 | case PPC_FLAGS_INPUT_6xx: | |
9527 | bus_model = "PowerPC 6xx"; | |
9528 | break; | |
9529 | case PPC_FLAGS_INPUT_BookE: | |
9530 | bus_model = "PowerPC BookE"; | |
9531 | break; | |
9532 | case PPC_FLAGS_INPUT_405: | |
9533 | bus_model = "PowerPC 405"; | |
9534 | break; | |
a750fc0b JM |
9535 | case PPC_FLAGS_INPUT_401: |
9536 | bus_model = "PowerPC 401/403"; | |
9537 | break; | |
b4095fed JM |
9538 | case PPC_FLAGS_INPUT_RCPU: |
9539 | bus_model = "RCPU / MPC8xx"; | |
9540 | break; | |
00af685f JM |
9541 | #if defined (TARGET_PPC64) |
9542 | case PPC_FLAGS_INPUT_970: | |
9543 | bus_model = "PowerPC 970"; | |
9544 | break; | |
9545 | #endif | |
a750fc0b JM |
9546 | default: |
9547 | bus_model = "Unknown or invalid"; | |
9548 | break; | |
9549 | } | |
9550 | printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" | |
9551 | " MMU model : %s\n", | |
a5100e75 AK |
9552 | object_class_get_name(OBJECT_CLASS(pcc)), |
9553 | pcc->pvr, pcc->msr_mask, mmu_model); | |
f2e63a42 | 9554 | #if !defined(CONFIG_USER_ONLY) |
a5100e75 | 9555 | if (env->tlb.tlb6) { |
a750fc0b JM |
9556 | printf(" %d %s TLB in %d ways\n", |
9557 | env->nb_tlb, env->id_tlbs ? "splitted" : "merged", | |
9558 | env->nb_ways); | |
9559 | } | |
f2e63a42 | 9560 | #endif |
a750fc0b JM |
9561 | printf(" Exceptions model : %s\n" |
9562 | " Bus model : %s\n", | |
9563 | excp_model, bus_model); | |
25ba3a68 JM |
9564 | printf(" MSR features :\n"); |
9565 | if (env->flags & POWERPC_FLAG_SPE) | |
9566 | printf(" signal processing engine enable" | |
9567 | "\n"); | |
9568 | else if (env->flags & POWERPC_FLAG_VRE) | |
9569 | printf(" vector processor enable\n"); | |
9570 | if (env->flags & POWERPC_FLAG_TGPR) | |
9571 | printf(" temporary GPRs\n"); | |
9572 | else if (env->flags & POWERPC_FLAG_CE) | |
9573 | printf(" critical input enable\n"); | |
9574 | if (env->flags & POWERPC_FLAG_SE) | |
9575 | printf(" single-step trace mode\n"); | |
9576 | else if (env->flags & POWERPC_FLAG_DWE) | |
9577 | printf(" debug wait enable\n"); | |
9578 | else if (env->flags & POWERPC_FLAG_UBLE) | |
9579 | printf(" user BTB lock enable\n"); | |
9580 | if (env->flags & POWERPC_FLAG_BE) | |
9581 | printf(" branch-step trace mode\n"); | |
9582 | else if (env->flags & POWERPC_FLAG_DE) | |
9583 | printf(" debug interrupt enable\n"); | |
9584 | if (env->flags & POWERPC_FLAG_PX) | |
9585 | printf(" inclusive protection\n"); | |
9586 | else if (env->flags & POWERPC_FLAG_PMM) | |
9587 | printf(" performance monitor mark\n"); | |
9588 | if (env->flags == POWERPC_FLAG_NONE) | |
9589 | printf(" none\n"); | |
4018bae9 JM |
9590 | printf(" Time-base/decrementer clock source: %s\n", |
9591 | env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); | |
22169d41 AF |
9592 | dump_ppc_insns(env); |
9593 | dump_ppc_sprs(env); | |
9594 | fflush(stdout); | |
a750fc0b | 9595 | } |
3a607854 | 9596 | #endif |
a750fc0b | 9597 | } |
3fc6c082 | 9598 | |
b048960f AF |
9599 | static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) |
9600 | { | |
9601 | PowerPCCPU *cpu = POWERPC_CPU(dev); | |
9602 | CPUPPCState *env = &cpu->env; | |
81f194dd BR |
9603 | opc_handler_t **table; |
9604 | int i, j; | |
b048960f | 9605 | |
6dd0f834 BR |
9606 | cpu_exec_exit(CPU(dev)); |
9607 | ||
b048960f | 9608 | for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { |
81f194dd BR |
9609 | if (env->opcodes[i] == &invalid_handler) { |
9610 | continue; | |
9611 | } | |
9612 | if (is_indirect_opcode(env->opcodes[i])) { | |
9613 | table = ind_table(env->opcodes[i]); | |
9614 | for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { | |
9615 | if (table[j] != &invalid_handler && | |
9616 | is_indirect_opcode(table[j])) { | |
9617 | g_free((opc_handler_t *)((uintptr_t)table[j] & | |
9618 | ~PPC_INDIRECT)); | |
9619 | } | |
9620 | } | |
9621 | g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] & | |
9622 | ~PPC_INDIRECT)); | |
b048960f AF |
9623 | } |
9624 | } | |
9625 | } | |
9626 | ||
2a48d993 AK |
9627 | int ppc_get_compat_smt_threads(PowerPCCPU *cpu) |
9628 | { | |
063cac53 | 9629 | int ret = MIN(smp_threads, kvmppc_smt_threads()); |
2a48d993 AK |
9630 | |
9631 | switch (cpu->cpu_version) { | |
9632 | case CPU_POWERPC_LOGICAL_2_05: | |
063cac53 | 9633 | ret = MIN(ret, 2); |
2a48d993 AK |
9634 | break; |
9635 | case CPU_POWERPC_LOGICAL_2_06: | |
063cac53 | 9636 | ret = MIN(ret, 4); |
2a48d993 AK |
9637 | break; |
9638 | case CPU_POWERPC_LOGICAL_2_07: | |
063cac53 | 9639 | ret = MIN(ret, 8); |
2a48d993 AK |
9640 | break; |
9641 | } | |
9642 | ||
063cac53 | 9643 | return ret; |
2a48d993 AK |
9644 | } |
9645 | ||
eac4fba9 | 9646 | #ifdef TARGET_PPC64 |
f9ab1e87 | 9647 | void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp) |
6d9412ea AK |
9648 | { |
9649 | int ret = 0; | |
9650 | CPUPPCState *env = &cpu->env; | |
eac4fba9 | 9651 | PowerPCCPUClass *host_pcc; |
6d9412ea AK |
9652 | |
9653 | cpu->cpu_version = cpu_version; | |
9654 | ||
9655 | switch (cpu_version) { | |
9656 | case CPU_POWERPC_LOGICAL_2_05: | |
eac4fba9 TH |
9657 | env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 | |
9658 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | |
6d9412ea AK |
9659 | break; |
9660 | case CPU_POWERPC_LOGICAL_2_06: | |
6d9412ea | 9661 | case CPU_POWERPC_LOGICAL_2_06_PLUS: |
eac4fba9 | 9662 | env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06; |
6d9412ea | 9663 | break; |
b30ff227 TH |
9664 | case CPU_POWERPC_LOGICAL_2_07: |
9665 | env->spr[SPR_PCR] = PCR_COMPAT_2_07; | |
9666 | break; | |
6d9412ea AK |
9667 | default: |
9668 | env->spr[SPR_PCR] = 0; | |
9669 | break; | |
9670 | } | |
9671 | ||
eac4fba9 TH |
9672 | host_pcc = kvm_ppc_get_host_cpu_class(); |
9673 | if (host_pcc) { | |
9674 | env->spr[SPR_PCR] &= host_pcc->pcr_mask; | |
9675 | } | |
9676 | ||
f9ab1e87 DG |
9677 | if (kvm_enabled()) { |
9678 | ret = kvmppc_set_compat(cpu, cpu->cpu_version); | |
9679 | if (ret < 0) { | |
9680 | error_setg_errno(errp, -ret, | |
9681 | "Unable to set CPU compatibility mode in KVM"); | |
9682 | } | |
6db5bb0f | 9683 | } |
6d9412ea | 9684 | } |
eac4fba9 | 9685 | #endif |
6d9412ea | 9686 | |
2985b86b | 9687 | static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) |
f0ad8c34 | 9688 | { |
2985b86b AF |
9689 | ObjectClass *oc = (ObjectClass *)a; |
9690 | uint32_t pvr = *(uint32_t *)b; | |
9691 | PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; | |
9692 | ||
9693 | /* -cpu host does a PVR lookup during construction */ | |
9694 | if (unlikely(strcmp(object_class_get_name(oc), | |
9695 | TYPE_HOST_POWERPC_CPU) == 0)) { | |
9696 | return -1; | |
f0ad8c34 | 9697 | } |
f0ad8c34 | 9698 | |
292363e1 | 9699 | if (!ppc_cpu_is_valid(pcc)) { |
4d7fb187 AF |
9700 | return -1; |
9701 | } | |
4d7fb187 | 9702 | |
cfe34f44 | 9703 | return pcc->pvr == pvr ? 0 : -1; |
f0ad8c34 AG |
9704 | } |
9705 | ||
2985b86b | 9706 | PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) |
3fc6c082 | 9707 | { |
2985b86b AF |
9708 | GSList *list, *item; |
9709 | PowerPCCPUClass *pcc = NULL; | |
be40edcd | 9710 | |
2985b86b AF |
9711 | list = object_class_get_list(TYPE_POWERPC_CPU, false); |
9712 | item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); | |
9713 | if (item != NULL) { | |
9714 | pcc = POWERPC_CPU_CLASS(item->data); | |
3fc6c082 | 9715 | } |
2985b86b AF |
9716 | g_slist_free(list); |
9717 | ||
9718 | return pcc; | |
9719 | } | |
9720 | ||
3bc9ccc0 AK |
9721 | static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) |
9722 | { | |
9723 | ObjectClass *oc = (ObjectClass *)a; | |
9724 | uint32_t pvr = *(uint32_t *)b; | |
9725 | PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; | |
3bc9ccc0 AK |
9726 | |
9727 | /* -cpu host does a PVR lookup during construction */ | |
9728 | if (unlikely(strcmp(object_class_get_name(oc), | |
9729 | TYPE_HOST_POWERPC_CPU) == 0)) { | |
9730 | return -1; | |
9731 | } | |
9732 | ||
292363e1 | 9733 | if (!ppc_cpu_is_valid(pcc)) { |
3bc9ccc0 AK |
9734 | return -1; |
9735 | } | |
292363e1 | 9736 | |
03ae4133 AK |
9737 | if (pcc->pvr_match(pcc, pvr)) { |
9738 | return 0; | |
9739 | } | |
3bc9ccc0 | 9740 | |
03ae4133 | 9741 | return -1; |
3bc9ccc0 AK |
9742 | } |
9743 | ||
9744 | PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) | |
9745 | { | |
9746 | GSList *list, *item; | |
9747 | PowerPCCPUClass *pcc = NULL; | |
9748 | ||
9749 | list = object_class_get_list(TYPE_POWERPC_CPU, true); | |
9750 | item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); | |
9751 | if (item != NULL) { | |
9752 | pcc = POWERPC_CPU_CLASS(item->data); | |
9753 | } | |
9754 | g_slist_free(list); | |
9755 | ||
9756 | return pcc; | |
9757 | } | |
9758 | ||
2985b86b AF |
9759 | static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b) |
9760 | { | |
9761 | ObjectClass *oc = (ObjectClass *)a; | |
9762 | const char *name = b; | |
4d7fb187 | 9763 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
ee4e83ed | 9764 | |
2985b86b | 9765 | if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 && |
292363e1 | 9766 | ppc_cpu_is_valid(pcc) && |
2985b86b AF |
9767 | strcmp(object_class_get_name(oc) + strlen(name), |
9768 | "-" TYPE_POWERPC_CPU) == 0) { | |
9769 | return 0; | |
9770 | } | |
9771 | return -1; | |
3fc6c082 FB |
9772 | } |
9773 | ||
3fc6c082 | 9774 | |
9761ad75 AG |
9775 | static ObjectClass *ppc_cpu_class_by_name(const char *name); |
9776 | ||
9777 | static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias) | |
9778 | { | |
9779 | ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias; | |
9780 | ||
9781 | /* Cache target class lookups in the alias table */ | |
9782 | if (!alias->oc) { | |
9783 | alias->oc = ppc_cpu_class_by_name(alias->model); | |
9784 | if (!alias->oc) { | |
9785 | /* Fast check for non-existing aliases */ | |
9786 | alias->oc = invalid_class; | |
9787 | } | |
9788 | } | |
9789 | ||
9790 | if (alias->oc == invalid_class) { | |
9791 | return NULL; | |
9792 | } else { | |
9793 | return alias->oc; | |
9794 | } | |
9795 | } | |
9796 | ||
2985b86b | 9797 | static ObjectClass *ppc_cpu_class_by_name(const char *name) |
ee4e83ed | 9798 | { |
2985b86b AF |
9799 | GSList *list, *item; |
9800 | ObjectClass *ret = NULL; | |
b55266b5 | 9801 | const char *p; |
2985b86b | 9802 | int i, len; |
ee4e83ed JM |
9803 | |
9804 | /* Check if the given name is a PVR */ | |
9805 | len = strlen(name); | |
9806 | if (len == 10 && name[0] == '0' && name[1] == 'x') { | |
9807 | p = name + 2; | |
9808 | goto check_pvr; | |
9809 | } else if (len == 8) { | |
9810 | p = name; | |
9811 | check_pvr: | |
9812 | for (i = 0; i < 8; i++) { | |
cd390083 | 9813 | if (!qemu_isxdigit(*p++)) |
ee4e83ed JM |
9814 | break; |
9815 | } | |
2985b86b | 9816 | if (i == 8) { |
74c373e4 | 9817 | return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16))); |
f0ad8c34 | 9818 | } |
2985b86b | 9819 | } |
f0ad8c34 | 9820 | |
2985b86b AF |
9821 | list = object_class_get_list(TYPE_POWERPC_CPU, false); |
9822 | item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name); | |
9823 | if (item != NULL) { | |
9824 | ret = OBJECT_CLASS(item->data); | |
3fc6c082 | 9825 | } |
2985b86b | 9826 | g_slist_free(list); |
ee4e83ed | 9827 | |
fdf8a960 AK |
9828 | if (ret) { |
9829 | return ret; | |
9830 | } | |
9831 | ||
9832 | for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { | |
9833 | if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) { | |
9834 | return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]); | |
9835 | } | |
9836 | } | |
9837 | ||
9838 | return NULL; | |
3fc6c082 FB |
9839 | } |
9840 | ||
2985b86b | 9841 | PowerPCCPU *cpu_ppc_init(const char *cpu_model) |
3fc6c082 | 9842 | { |
9262685b | 9843 | return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); |
2985b86b AF |
9844 | } |
9845 | ||
9846 | /* Sort by PVR, ordering special case "host" last. */ | |
9847 | static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
9848 | { | |
9849 | ObjectClass *oc_a = (ObjectClass *)a; | |
9850 | ObjectClass *oc_b = (ObjectClass *)b; | |
9851 | PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); | |
9852 | PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); | |
9853 | const char *name_a = object_class_get_name(oc_a); | |
9854 | const char *name_b = object_class_get_name(oc_b); | |
9855 | ||
9856 | if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { | |
9857 | return 1; | |
9858 | } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { | |
9859 | return -1; | |
9860 | } else { | |
9861 | /* Avoid an integer overflow during subtraction */ | |
cfe34f44 | 9862 | if (pcc_a->pvr < pcc_b->pvr) { |
2985b86b | 9863 | return -1; |
cfe34f44 | 9864 | } else if (pcc_a->pvr > pcc_b->pvr) { |
2985b86b AF |
9865 | return 1; |
9866 | } else { | |
9867 | return 0; | |
9868 | } | |
9869 | } | |
9870 | } | |
9871 | ||
9872 | static void ppc_cpu_list_entry(gpointer data, gpointer user_data) | |
9873 | { | |
9874 | ObjectClass *oc = data; | |
9875 | CPUListState *s = user_data; | |
9876 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
de400129 AF |
9877 | const char *typename = object_class_get_name(oc); |
9878 | char *name; | |
55d3d1a4 | 9879 | int i; |
2985b86b | 9880 | |
292363e1 | 9881 | if (!ppc_cpu_is_valid(pcc)) { |
4d7fb187 AF |
9882 | return; |
9883 | } | |
5ba4576b AF |
9884 | if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { |
9885 | return; | |
9886 | } | |
4d7fb187 | 9887 | |
de400129 AF |
9888 | name = g_strndup(typename, |
9889 | strlen(typename) - strlen("-" TYPE_POWERPC_CPU)); | |
2985b86b | 9890 | (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n", |
cfe34f44 | 9891 | name, pcc->pvr); |
e9a96075 | 9892 | for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { |
9761ad75 AG |
9893 | PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; |
9894 | ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias); | |
55d3d1a4 AF |
9895 | |
9896 | if (alias_oc != oc) { | |
9897 | continue; | |
9898 | } | |
9899 | (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n", | |
9900 | alias->alias, name); | |
9901 | } | |
de400129 | 9902 | g_free(name); |
2985b86b AF |
9903 | } |
9904 | ||
9905 | void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
9906 | { | |
9907 | CPUListState s = { | |
9908 | .file = f, | |
9909 | .cpu_fprintf = cpu_fprintf, | |
9910 | }; | |
9911 | GSList *list; | |
9912 | ||
9913 | list = object_class_get_list(TYPE_POWERPC_CPU, false); | |
9914 | list = g_slist_sort(list, ppc_cpu_list_compare); | |
9915 | g_slist_foreach(list, ppc_cpu_list_entry, &s); | |
9916 | g_slist_free(list); | |
fd5ed418 | 9917 | |
5ba4576b AF |
9918 | #ifdef CONFIG_KVM |
9919 | cpu_fprintf(f, "\n"); | |
9920 | cpu_fprintf(f, "PowerPC %-16s\n", "host"); | |
9921 | #endif | |
2985b86b AF |
9922 | } |
9923 | ||
9924 | static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) | |
9925 | { | |
9926 | ObjectClass *oc = data; | |
9927 | CpuDefinitionInfoList **first = user_data; | |
de400129 | 9928 | const char *typename; |
2985b86b AF |
9929 | CpuDefinitionInfoList *entry; |
9930 | CpuDefinitionInfo *info; | |
4d7fb187 AF |
9931 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
9932 | ||
292363e1 | 9933 | if (!ppc_cpu_is_valid(pcc)) { |
4d7fb187 AF |
9934 | return; |
9935 | } | |
2985b86b | 9936 | |
de400129 | 9937 | typename = object_class_get_name(oc); |
2985b86b | 9938 | info = g_malloc0(sizeof(*info)); |
de400129 AF |
9939 | info->name = g_strndup(typename, |
9940 | strlen(typename) - strlen("-" TYPE_POWERPC_CPU)); | |
2985b86b AF |
9941 | |
9942 | entry = g_malloc0(sizeof(*entry)); | |
9943 | entry->value = info; | |
9944 | entry->next = *first; | |
9945 | *first = entry; | |
3fc6c082 | 9946 | } |
1d0cb67d | 9947 | |
76b64a7a | 9948 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) |
70b7660a AL |
9949 | { |
9950 | CpuDefinitionInfoList *cpu_list = NULL; | |
2985b86b | 9951 | GSList *list; |
35e21d3f | 9952 | int i; |
70b7660a | 9953 | |
2985b86b AF |
9954 | list = object_class_get_list(TYPE_POWERPC_CPU, false); |
9955 | g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); | |
9956 | g_slist_free(list); | |
70b7660a | 9957 | |
e9a96075 | 9958 | for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { |
9761ad75 | 9959 | PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; |
35e21d3f AF |
9960 | ObjectClass *oc; |
9961 | CpuDefinitionInfoList *entry; | |
9962 | CpuDefinitionInfo *info; | |
9963 | ||
9761ad75 | 9964 | oc = ppc_cpu_class_by_alias(alias); |
35e21d3f AF |
9965 | if (oc == NULL) { |
9966 | continue; | |
9967 | } | |
9968 | ||
9969 | info = g_malloc0(sizeof(*info)); | |
9970 | info->name = g_strdup(alias->alias); | |
9971 | ||
9972 | entry = g_malloc0(sizeof(*entry)); | |
9973 | entry->value = info; | |
9974 | entry->next = cpu_list; | |
9975 | cpu_list = entry; | |
9976 | } | |
9977 | ||
2985b86b AF |
9978 | return cpu_list; |
9979 | } | |
70b7660a | 9980 | |
f45748f1 AF |
9981 | static void ppc_cpu_set_pc(CPUState *cs, vaddr value) |
9982 | { | |
9983 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
9984 | ||
9985 | cpu->env.nip = value; | |
9986 | } | |
9987 | ||
8c2e1b00 AF |
9988 | static bool ppc_cpu_has_work(CPUState *cs) |
9989 | { | |
9990 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
9991 | CPUPPCState *env = &cpu->env; | |
9992 | ||
9993 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | |
9994 | } | |
9995 | ||
774f0abe RH |
9996 | static void ppc_cpu_exec_enter(CPUState *cs) |
9997 | { | |
9998 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
9999 | CPUPPCState *env = &cpu->env; | |
10000 | ||
10001 | env->reserve_addr = -1; | |
10002 | } | |
10003 | ||
1d0cb67d AF |
10004 | /* CPUClass::reset() */ |
10005 | static void ppc_cpu_reset(CPUState *s) | |
10006 | { | |
10007 | PowerPCCPU *cpu = POWERPC_CPU(s); | |
10008 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
10009 | CPUPPCState *env = &cpu->env; | |
a1389542 | 10010 | target_ulong msr; |
d197fdbc | 10011 | int i; |
a1389542 | 10012 | |
1d0cb67d AF |
10013 | pcc->parent_reset(s); |
10014 | ||
a1389542 | 10015 | msr = (target_ulong)0; |
932ccbdd | 10016 | msr |= (target_ulong)MSR_HVB; |
a1389542 AF |
10017 | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
10018 | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ | |
10019 | msr |= (target_ulong)1 << MSR_EP; | |
10020 | #if defined(DO_SINGLE_STEP) && 0 | |
10021 | /* Single step trace mode */ | |
10022 | msr |= (target_ulong)1 << MSR_SE; | |
10023 | msr |= (target_ulong)1 << MSR_BE; | |
10024 | #endif | |
10025 | #if defined(CONFIG_USER_ONLY) | |
10026 | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ | |
10027 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ | |
5b274ed7 | 10028 | msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ |
a1389542 AF |
10029 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |
10030 | msr |= (target_ulong)1 << MSR_PR; | |
cdcdda27 AK |
10031 | #if defined(TARGET_PPC64) |
10032 | msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ | |
10033 | #endif | |
e22c357b DK |
10034 | #if !defined(TARGET_WORDS_BIGENDIAN) |
10035 | msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ | |
a74029f6 RH |
10036 | if (!((env->msr_mask >> MSR_LE) & 1)) { |
10037 | fprintf(stderr, "Selected CPU does not support little-endian.\n"); | |
10038 | exit(1); | |
10039 | } | |
e22c357b | 10040 | #endif |
a1389542 | 10041 | #endif |
2cf3eb6d | 10042 | |
a1389542 AF |
10043 | #if defined(TARGET_PPC64) |
10044 | if (env->mmu_model & POWERPC_MMU_64) { | |
8b9f2118 | 10045 | msr |= (1ULL << MSR_SF); |
a1389542 AF |
10046 | } |
10047 | #endif | |
2cf3eb6d FC |
10048 | |
10049 | hreg_store_msr(env, msr, 1); | |
10050 | ||
10051 | #if !defined(CONFIG_USER_ONLY) | |
10052 | env->nip = env->hreset_vector | env->excp_prefix; | |
10053 | if (env->mmu_model != POWERPC_MMU_REAL) { | |
10054 | ppc_tlb_invalidate_all(env); | |
10055 | } | |
10056 | #endif | |
10057 | ||
a1389542 AF |
10058 | hreg_compute_hflags(env); |
10059 | env->reserve_addr = (target_ulong)-1ULL; | |
10060 | /* Be sure no exception or interrupt is pending */ | |
10061 | env->pending_interrupts = 0; | |
27103424 | 10062 | s->exception_index = POWERPC_EXCP_NONE; |
a1389542 | 10063 | env->error_code = 0; |
2b15811c DG |
10064 | |
10065 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
1bfb37d1 DG |
10066 | env->vpa_addr = 0; |
10067 | env->slb_shadow_addr = 0; | |
10068 | env->slb_shadow_size = 0; | |
10069 | env->dtl_addr = 0; | |
2b15811c DG |
10070 | env->dtl_size = 0; |
10071 | #endif /* TARGET_PPC64 */ | |
10072 | ||
d197fdbc AK |
10073 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { |
10074 | ppc_spr_t *spr = &env->spr_cb[i]; | |
10075 | ||
10076 | if (!spr->name) { | |
10077 | continue; | |
10078 | } | |
10079 | env->spr[i] = spr->default_value; | |
10080 | } | |
10081 | ||
a1389542 | 10082 | /* Flush all TLBs */ |
00c8cb0a | 10083 | tlb_flush(s, 1); |
1d0cb67d AF |
10084 | } |
10085 | ||
7826c2b2 GK |
10086 | #ifndef CONFIG_USER_ONLY |
10087 | static bool ppc_cpu_is_big_endian(CPUState *cs) | |
10088 | { | |
10089 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
10090 | CPUPPCState *env = &cpu->env; | |
10091 | ||
10092 | cpu_synchronize_state(cs); | |
10093 | ||
10094 | return !msr_le; | |
10095 | } | |
10096 | #endif | |
10097 | ||
6cca7ad6 AF |
10098 | static void ppc_cpu_initfn(Object *obj) |
10099 | { | |
c05efcb1 | 10100 | CPUState *cs = CPU(obj); |
6cca7ad6 | 10101 | PowerPCCPU *cpu = POWERPC_CPU(obj); |
2985b86b | 10102 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
6cca7ad6 AF |
10103 | CPUPPCState *env = &cpu->env; |
10104 | ||
c05efcb1 | 10105 | cs->env_ptr = env; |
2985b86b | 10106 | |
cfe34f44 AF |
10107 | env->msr_mask = pcc->msr_mask; |
10108 | env->mmu_model = pcc->mmu_model; | |
10109 | env->excp_model = pcc->excp_model; | |
10110 | env->bus_model = pcc->bus_model; | |
10111 | env->insns_flags = pcc->insns_flags; | |
10112 | env->insns_flags2 = pcc->insns_flags2; | |
10113 | env->flags = pcc->flags; | |
10114 | env->bfd_mach = pcc->bfd_mach; | |
10115 | env->check_pow = pcc->check_pow; | |
2985b86b | 10116 | |
932ccbdd BH |
10117 | /* Mark HV mode as supported if the CPU has an MSR_HV bit |
10118 | * in the msr_mask. The mask can later be cleared by PAPR | |
10119 | * mode but the hv mode support will remain, thus enforcing | |
10120 | * that we cannot use priv. instructions in guest in PAPR | |
10121 | * mode. For 970 we currently simply don't set HV in msr_mask | |
10122 | * thus simulating an "Apple mode" 970. If we ever want to | |
10123 | * support 970 HV mode, we'll have to add a processor attribute | |
10124 | * of some sort. | |
10125 | */ | |
10126 | #if !defined(CONFIG_USER_ONLY) | |
10127 | env->has_hv_mode = !!(env->msr_mask & MSR_HVB); | |
10128 | #endif | |
10129 | ||
2985b86b | 10130 | #if defined(TARGET_PPC64) |
cfe34f44 AF |
10131 | if (pcc->sps) { |
10132 | env->sps = *pcc->sps; | |
2985b86b AF |
10133 | } else if (env->mmu_model & POWERPC_MMU_64) { |
10134 | /* Use default sets of page sizes */ | |
10135 | static const struct ppc_segment_page_sizes defsps = { | |
10136 | .sps = { | |
10137 | { .page_shift = 12, /* 4K */ | |
10138 | .slb_enc = 0, | |
10139 | .enc = { { .page_shift = 12, .pte_enc = 0 } } | |
10140 | }, | |
10141 | { .page_shift = 24, /* 16M */ | |
10142 | .slb_enc = 0x100, | |
10143 | .enc = { { .page_shift = 24, .pte_enc = 0 } } | |
10144 | }, | |
10145 | }, | |
10146 | }; | |
10147 | env->sps = defsps; | |
10148 | } | |
10149 | #endif /* defined(TARGET_PPC64) */ | |
60925d26 AF |
10150 | |
10151 | if (tcg_enabled()) { | |
10152 | ppc_translate_init(); | |
10153 | } | |
6cca7ad6 AF |
10154 | } |
10155 | ||
03ae4133 AK |
10156 | static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) |
10157 | { | |
10158 | return pcc->pvr == pvr; | |
10159 | } | |
10160 | ||
b3820e6c DH |
10161 | static gchar *ppc_gdb_arch_name(CPUState *cs) |
10162 | { | |
10163 | #if defined(TARGET_PPC64) | |
10164 | return g_strdup("powerpc:common64"); | |
10165 | #else | |
10166 | return g_strdup("powerpc:common"); | |
10167 | #endif | |
10168 | } | |
10169 | ||
1d0cb67d AF |
10170 | static void ppc_cpu_class_init(ObjectClass *oc, void *data) |
10171 | { | |
10172 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
10173 | CPUClass *cc = CPU_CLASS(oc); | |
4776ce60 AF |
10174 | DeviceClass *dc = DEVICE_CLASS(oc); |
10175 | ||
10176 | pcc->parent_realize = dc->realize; | |
03ae4133 | 10177 | pcc->pvr_match = ppc_pvr_match_default; |
382d2db6 | 10178 | pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; |
4776ce60 | 10179 | dc->realize = ppc_cpu_realizefn; |
b048960f | 10180 | dc->unrealize = ppc_cpu_unrealizefn; |
1d0cb67d AF |
10181 | |
10182 | pcc->parent_reset = cc->reset; | |
10183 | cc->reset = ppc_cpu_reset; | |
2b8c2754 AF |
10184 | |
10185 | cc->class_by_name = ppc_cpu_class_by_name; | |
8c2e1b00 | 10186 | cc->has_work = ppc_cpu_has_work; |
97a8ea5a | 10187 | cc->do_interrupt = ppc_cpu_do_interrupt; |
458dd766 | 10188 | cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt; |
878096ee AF |
10189 | cc->dump_state = ppc_cpu_dump_state; |
10190 | cc->dump_statistics = ppc_cpu_dump_statistics; | |
f45748f1 | 10191 | cc->set_pc = ppc_cpu_set_pc; |
5b50e790 AF |
10192 | cc->gdb_read_register = ppc_cpu_gdb_read_register; |
10193 | cc->gdb_write_register = ppc_cpu_gdb_write_register; | |
7510454e AF |
10194 | #ifdef CONFIG_USER_ONLY |
10195 | cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault; | |
10196 | #else | |
00b941e5 | 10197 | cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; |
a90db158 | 10198 | cc->vmsd = &vmstate_ppc_cpu; |
e62fbc54 AK |
10199 | #if defined(TARGET_PPC64) |
10200 | cc->write_elf64_note = ppc64_cpu_write_elf64_note; | |
e62fbc54 | 10201 | #endif |
00b941e5 | 10202 | #endif |
774f0abe | 10203 | cc->cpu_exec_enter = ppc_cpu_exec_enter; |
a0e372f0 AF |
10204 | |
10205 | cc->gdb_num_core_regs = 71; | |
b3cad3ab AG |
10206 | |
10207 | #ifdef USE_APPLE_GDB | |
10208 | cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; | |
10209 | cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; | |
10210 | cc->gdb_num_core_regs = 71 + 32; | |
10211 | #endif | |
10212 | ||
b3820e6c | 10213 | cc->gdb_arch_name = ppc_gdb_arch_name; |
5b24c641 AF |
10214 | #if defined(TARGET_PPC64) |
10215 | cc->gdb_core_xml_file = "power64-core.xml"; | |
10216 | #else | |
10217 | cc->gdb_core_xml_file = "power-core.xml"; | |
10218 | #endif | |
7826c2b2 GK |
10219 | #ifndef CONFIG_USER_ONLY |
10220 | cc->virtio_is_big_endian = ppc_cpu_is_big_endian; | |
10221 | #endif | |
3bbf37f2 AF |
10222 | |
10223 | dc->fw_name = "PowerPC,UNKNOWN"; | |
1d0cb67d AF |
10224 | } |
10225 | ||
10226 | static const TypeInfo ppc_cpu_type_info = { | |
10227 | .name = TYPE_POWERPC_CPU, | |
10228 | .parent = TYPE_CPU, | |
10229 | .instance_size = sizeof(PowerPCCPU), | |
6cca7ad6 | 10230 | .instance_init = ppc_cpu_initfn, |
2985b86b | 10231 | .abstract = true, |
1d0cb67d AF |
10232 | .class_size = sizeof(PowerPCCPUClass), |
10233 | .class_init = ppc_cpu_class_init, | |
10234 | }; | |
10235 | ||
10236 | static void ppc_cpu_register_types(void) | |
10237 | { | |
10238 | type_register_static(&ppc_cpu_type_info); | |
10239 | } | |
10240 | ||
10241 | type_init(ppc_cpu_register_types) |