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cpu: Replace do_interrupt() by CPUClass::do_interrupt method
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
76cad711 21#include "disas/bfd.h"
022c62cb 22#include "exec/gdbstub.h"
9c17d615 23#include <sysemu/kvm.h>
a1e98583 24#include "kvm_ppc.h"
9c17d615 25#include "sysemu/arch_init.h"
fe828a4d 26#include "sysemu/cpus.h"
953af181 27#include "cpu-models.h"
237c0af0 28
3fc6c082
FB		 29//#define PPC_DUMP_CPU
30//#define PPC_DEBUG_SPR
80d11f44 31//#define PPC_DUMP_SPR_ACCESSES
3fc6c082 32
e9df014c
JM		 33/* For user-mode emulation, we don't emulate any IRQ controller */
34#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 35#define PPC_IRQ_INIT_FN(name) \
36static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
37{ \
e9df014c
JM		 38}
39#else
a750fc0b 40#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 41void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
42#endif
a750fc0b 43
4e290a0b 44PPC_IRQ_INIT_FN(40x);
e9df014c 45PPC_IRQ_INIT_FN(6xx);
d0dfae6e 46PPC_IRQ_INIT_FN(970);
9d52e907 47PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 48PPC_IRQ_INIT_FN(e500);
e9df014c 49
3fc6c082
FB		 50/* Generic callbacks:
51 * do nothing but store/retrieve spr value
52 */
91f477fd
AG		 53static void spr_load_dump_spr(int sprn)
54{
55#ifdef PPC_DUMP_SPR_ACCESSES
56 TCGv_i32 t0 = tcg_const_i32(sprn);
edbe35e0 57 gen_helper_load_dump_spr(cpu_env, t0);
91f477fd
AG		 58 tcg_temp_free_i32(t0);
59#endif
60}
61
45d827d2 62static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 63{
45d827d2 64 gen_load_spr(cpu_gpr[gprn], sprn);
91f477fd
AG		 65 spr_load_dump_spr(sprn);
66}
67
68static void spr_store_dump_spr(int sprn)
69{
45d827d2 70#ifdef PPC_DUMP_SPR_ACCESSES
91f477fd 71 TCGv_i32 t0 = tcg_const_i32(sprn);
edbe35e0 72 gen_helper_store_dump_spr(cpu_env, t0);
91f477fd 73 tcg_temp_free_i32(t0);
45d827d2 74#endif
a496775f
JM		 75}
76
45d827d2 77static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 78{
45d827d2 79 gen_store_spr(sprn, cpu_gpr[gprn]);
91f477fd 80 spr_store_dump_spr(sprn);
45d827d2 81}
a496775f
JM		 82
83#if !defined(CONFIG_USER_ONLY)
ba38ab8d
AG		 84static void spr_write_generic32(void *opaque, int sprn, int gprn)
85{
86#ifdef TARGET_PPC64
87 TCGv t0 = tcg_temp_new();
88 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
89 gen_store_spr(sprn, t0);
90 tcg_temp_free(t0);
91 spr_store_dump_spr(sprn);
92#else
93 spr_write_generic(opaque, sprn, gprn);
94#endif
95}
96
45d827d2 97static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 98{
45d827d2
AJ		 99 TCGv t0 = tcg_temp_new();
100 TCGv t1 = tcg_temp_new();
101 gen_load_spr(t0, sprn);
102 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
103 tcg_gen_and_tl(t0, t0, t1);
104 gen_store_spr(sprn, t0);
105 tcg_temp_free(t0);
106 tcg_temp_free(t1);
a496775f
JM		 107}
108#endif
109
76a66253 110/* SPR common to all PowerPC */
3fc6c082 111/* XER */
45d827d2 112static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 113{
da91a00f 114 gen_read_xer(cpu_gpr[gprn]);
3fc6c082
FB		 115}
116
45d827d2 117static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 118{
da91a00f 119 gen_write_xer(cpu_gpr[gprn]);
3fc6c082
FB		 120}
121
122/* LR */
45d827d2 123static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 124{
45d827d2 125 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 126}
127
45d827d2 128static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 129{
45d827d2 130 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 131}
132
697ab892
DG		 133/* CFAR */
134#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
135static void spr_read_cfar (void *opaque, int gprn, int sprn)
136{
137 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
138}
139
140static void spr_write_cfar (void *opaque, int sprn, int gprn)
141{
142 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
143}
144#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
145
3fc6c082 146/* CTR */
45d827d2 147static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 148{
45d827d2 149 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 150}
151
45d827d2 152static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 153{
45d827d2 154 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 155}
156
157/* User read access to SPR */
158/* USPRx */
159/* UMMCRx */
160/* UPMCx */
161/* USIA */
162/* UDECR */
45d827d2 163static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 164{
45d827d2 165 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 166}
167
76a66253 168/* SPR common to all non-embedded PowerPC */
3fc6c082 169/* DECR */
76a66253 170#if !defined(CONFIG_USER_ONLY)
45d827d2 171static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 172{
630ecca0
TG		 173 if (use_icount) {
174 gen_io_start();
175 }
d0f1562d 176 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 177 if (use_icount) {
178 gen_io_end();
179 gen_stop_exception(opaque);
180 }
3fc6c082
FB		 181}
182
45d827d2 183static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 184{
630ecca0
TG		 185 if (use_icount) {
186 gen_io_start();
187 }
d0f1562d 188 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 189 if (use_icount) {
190 gen_io_end();
191 gen_stop_exception(opaque);
192 }
3fc6c082 193}
76a66253 194#endif
3fc6c082 195
76a66253 196/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 197/* Time base */
45d827d2 198static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 199{
630ecca0
TG		 200 if (use_icount) {
201 gen_io_start();
202 }
d0f1562d 203 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 204 if (use_icount) {
205 gen_io_end();
206 gen_stop_exception(opaque);
207 }
3fc6c082
FB		 208}
209
45d827d2 210static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 211{
630ecca0
TG		 212 if (use_icount) {
213 gen_io_start();
214 }
d0f1562d 215 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 216 if (use_icount) {
217 gen_io_end();
218 gen_stop_exception(opaque);
219 }
3fc6c082
FB		 220}
221
a062e36c 222__attribute__ (( unused ))
45d827d2 223static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 224{
d0f1562d 225 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 226}
227
228__attribute__ (( unused ))
45d827d2 229static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 230{
d0f1562d 231 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 232}
233
76a66253 234#if !defined(CONFIG_USER_ONLY)
45d827d2 235static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 236{
630ecca0
TG		 237 if (use_icount) {
238 gen_io_start();
239 }
d0f1562d 240 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 241 if (use_icount) {
242 gen_io_end();
243 gen_stop_exception(opaque);
244 }
3fc6c082
FB		 245}
246
45d827d2 247static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 248{
630ecca0
TG		 249 if (use_icount) {
250 gen_io_start();
251 }
d0f1562d 252 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 253 if (use_icount) {
254 gen_io_end();
255 gen_stop_exception(opaque);
256 }
3fc6c082 257}
a062e36c
JM		 258
259__attribute__ (( unused ))
45d827d2 260static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 261{
d0f1562d 262 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
a062e36c
JM		 263}
264
265__attribute__ (( unused ))
45d827d2 266static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 267{
d0f1562d 268 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
a062e36c 269}
3a7f009a
DG		 270
271#if defined(TARGET_PPC64)
272__attribute__ (( unused ))
273static void spr_read_purr (void *opaque, int gprn, int sprn)
274{
d0f1562d 275 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
3a7f009a
DG		 276}
277#endif
76a66253 278#endif
3fc6c082 279
76a66253 280#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 281/* IBAT0U...IBAT0U */
282/* IBAT0L...IBAT7L */
45d827d2 283static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 284{
1328c2bf 285 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 286}
287
45d827d2 288static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 289{
1328c2bf 290 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 291}
292
45d827d2 293static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 294{
45d827d2 295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 296 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 297 tcg_temp_free_i32(t0);
3fc6c082
FB		 298}
299
45d827d2 300static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 301{
8daf1781 302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
c6c7cf05 303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 304 tcg_temp_free_i32(t0);
3fc6c082
FB		 305}
306
45d827d2 307static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 308{
45d827d2 309 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
c6c7cf05 310 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 311 tcg_temp_free_i32(t0);
3fc6c082
FB		 312}
313
45d827d2 314static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 315{
8daf1781 316 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
c6c7cf05 317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 318 tcg_temp_free_i32(t0);
3fc6c082
FB		 319}
320
321/* DBAT0U...DBAT7U */
322/* DBAT0L...DBAT7L */
45d827d2 323static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 324{
1328c2bf 325 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 326}
327
45d827d2 328static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 329{
1328c2bf 330 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 331}
332
45d827d2 333static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 334{
45d827d2 335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
c6c7cf05 336 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 337 tcg_temp_free_i32(t0);
3fc6c082
FB		 338}
339
45d827d2 340static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 341{
45d827d2 342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
c6c7cf05 343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 344 tcg_temp_free_i32(t0);
3fc6c082
FB		 345}
346
45d827d2 347static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 348{
45d827d2 349 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
c6c7cf05 350 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 351 tcg_temp_free_i32(t0);
3fc6c082
FB		 352}
353
45d827d2 354static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 355{
45d827d2 356 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
c6c7cf05 357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 358 tcg_temp_free_i32(t0);
3fc6c082
FB		 359}
360
361/* SDR1 */
45d827d2 362static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 363{
d523dd00 364 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
3fc6c082
FB		 365}
366
76a66253
JM		 367/* 64 bits PowerPC specific SPRs */
368/* ASR */
578bb252 369#if defined(TARGET_PPC64)
2adab7d6
BS		 370static void spr_read_hior (void *opaque, int gprn, int sprn)
371{
1328c2bf 372 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 373}
374
375static void spr_write_hior (void *opaque, int sprn, int gprn)
376{
377 TCGv t0 = tcg_temp_new();
378 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
1328c2bf 379 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 380 tcg_temp_free(t0);
381}
382
45d827d2 383static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 384{
1328c2bf 385 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
76a66253
JM		 386}
387
45d827d2 388static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 389{
d523dd00 390 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 391}
392#endif
a750fc0b 393#endif
76a66253
JM		 394
395/* PowerPC 601 specific registers */
396/* RTC */
45d827d2 397static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 398{
d0f1562d 399 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
76a66253
JM		 400}
401
45d827d2 402static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 403{
d0f1562d 404 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
76a66253
JM		 405}
406
407#if !defined(CONFIG_USER_ONLY)
45d827d2 408static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 409{
d0f1562d 410 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 411}
412
45d827d2 413static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 414{
d0f1562d 415 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
76a66253 416}
056401ea 417
45d827d2 418static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 419{
420 DisasContext *ctx = opaque;
421
d523dd00 422 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
056401ea 423 /* Must stop the translation as endianness may have changed */
e06fcd75 424 gen_stop_exception(ctx);
056401ea 425}
76a66253
JM		 426#endif
427
428/* Unified bats */
429#if !defined(CONFIG_USER_ONLY)
45d827d2 430static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 431{
1328c2bf 432 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 433}
434
45d827d2 435static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 436{
45d827d2 437 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 438 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 439 tcg_temp_free_i32(t0);
76a66253
JM		 440}
441
45d827d2 442static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 443{
45d827d2 444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 445 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 446 tcg_temp_free_i32(t0);
76a66253
JM		 447}
448#endif
449
450/* PowerPC 40x specific registers */
451#if !defined(CONFIG_USER_ONLY)
45d827d2 452static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 453{
d0f1562d 454 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
76a66253
JM		 455}
456
45d827d2 457static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 458{
d0f1562d 459 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 460}
461
45d827d2 462static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 463{
464 DisasContext *ctx = opaque;
465
d523dd00 466 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
8ecc7913 467 /* We must stop translation as we may have rebooted */
e06fcd75 468 gen_stop_exception(ctx);
8ecc7913
JM		 469}
470
45d827d2 471static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 472{
d523dd00 473 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
c294fc58
JM		 474}
475
45d827d2 476static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 477{
d0f1562d 478 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 479}
480
45d827d2 481static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 482{
d0f1562d 483 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 484}
485#endif
486
487/* PowerPC 403 specific registers */
488/* PBL1 / PBU1 / PBL2 / PBU2 */
489#if !defined(CONFIG_USER_ONLY)
45d827d2 490static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 491{
1328c2bf 492 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 493}
494
45d827d2 495static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 496{
45d827d2 497 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
d523dd00 498 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 499 tcg_temp_free_i32(t0);
76a66253
JM		 500}
501
45d827d2 502static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 503{
45d827d2
AJ		 504 TCGv t0 = tcg_temp_new();
505 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
506 gen_store_spr(SPR_PIR, t0);
507 tcg_temp_free(t0);
3fc6c082 508}
76a66253 509#endif
3fc6c082 510
d34defbc
AJ		 511/* SPE specific registers */
512static void spr_read_spefscr (void *opaque, int gprn, int sprn)
513{
514 TCGv_i32 t0 = tcg_temp_new_i32();
1328c2bf 515 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 516 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
517 tcg_temp_free_i32(t0);
518}
519
520static void spr_write_spefscr (void *opaque, int sprn, int gprn)
521{
522 TCGv_i32 t0 = tcg_temp_new_i32();
523 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1328c2bf 524 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 525 tcg_temp_free_i32(t0);
526}
527
6f5d427d
JM		 528#if !defined(CONFIG_USER_ONLY)
529/* Callback used to write the exception vector base */
45d827d2 530static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 531{
45d827d2 532 TCGv t0 = tcg_temp_new();
1328c2bf 533 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
45d827d2 534 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 535 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
45d827d2 536 gen_store_spr(sprn, t0);
69bd5820 537 tcg_temp_free(t0);
6f5d427d
JM		 538}
539
45d827d2 540static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 541{
542 DisasContext *ctx = opaque;
e9205258 543 int sprn_offs;
6f5d427d
JM		 544
545 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
e9205258 546 sprn_offs = sprn - SPR_BOOKE_IVOR0;
6f5d427d 547 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
e9205258
AG		 548 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
549 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
550 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
6f5d427d
JM		 551 } else {
552 printf("Trying to write an unknown exception vector %d %03x\n",
553 sprn, sprn);
e06fcd75 554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
e9205258 555 return;
6f5d427d 556 }
e9205258
AG		 557
558 TCGv t0 = tcg_temp_new();
1328c2bf 559 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
e9205258 560 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 561 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
e9205258
AG		 562 gen_store_spr(sprn, t0);
563 tcg_temp_free(t0);
6f5d427d
JM		 564}
565#endif
566
cf8358c8
AJ		 567static inline void vscr_init (CPUPPCState *env, uint32_t val)
568{
569 env->vscr = val;
570 /* Altivec always uses round-to-nearest */
571 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
572 set_flush_to_zero(vscr_nj, &env->vec_status);
573}
574
d67d40ea
DG		 575#ifdef CONFIG_USER_ONLY
576#define spr_register_kvm(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, one_reg_id, initial_value) \
578 _spr_register(env, num, name, uea_read, uea_write, initial_value)
579#else
580#if !defined(CONFIG_KVM)
581#define spr_register_kvm(env, num, name, uea_read, uea_write, \
582 oea_read, oea_write, one_reg_id, initial_value) \
583 _spr_register(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, initial_value)
76a66253 585#else
d67d40ea
DG		 586#define spr_register_kvm(env, num, name, uea_read, uea_write, \
587 oea_read, oea_write, one_reg_id, initial_value) \
588 _spr_register(env, num, name, uea_read, uea_write, \
589 oea_read, oea_write, one_reg_id, initial_value)
590#endif
591#endif
592
593#define spr_register(env, num, name, uea_read, uea_write, \
594 oea_read, oea_write, initial_value) \
595 spr_register_kvm(env, num, name, uea_read, uea_write, \
596 oea_read, oea_write, 0, initial_value)
597
598static inline void _spr_register(CPUPPCState *env, int num,
b55266b5 599 const char *name,
45d827d2
AJ		 600 void (*uea_read)(void *opaque, int gprn, int sprn),
601 void (*uea_write)(void *opaque, int sprn, int gprn),
d67d40ea
DG		 602#if !defined(CONFIG_USER_ONLY)
603
45d827d2
AJ		 604 void (*oea_read)(void *opaque, int gprn, int sprn),
605 void (*oea_write)(void *opaque, int sprn, int gprn),
76a66253 606#endif
d67d40ea
DG		 607#if defined(CONFIG_KVM)
608 uint64_t one_reg_id,
609#endif
610 target_ulong initial_value)
3fc6c082 611{
c227f099 612 ppc_spr_t *spr;
3fc6c082
FB		 613
614 spr = &env->spr_cb[num];
615 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 616#if !defined(CONFIG_USER_ONLY)
617 spr->oea_read != NULL || spr->oea_write != NULL ||
618#endif
619 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 620 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
621 exit(1);
622 }
623#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 624 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
625 name, initial_value);
3fc6c082
FB		 626#endif
627 spr->name = name;
628 spr->uea_read = uea_read;
629 spr->uea_write = uea_write;
76a66253 630#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 631 spr->oea_read = oea_read;
632 spr->oea_write = oea_write;
76a66253 633#endif
3fc6c082
FB		 634 env->spr[num] = initial_value;
635}
636
637/* Generic PowerPC SPRs */
638static void gen_spr_generic (CPUPPCState *env)
639{
640 /* Integer processing */
641 spr_register(env, SPR_XER, "XER",
642 &spr_read_xer, &spr_write_xer,
643 &spr_read_xer, &spr_write_xer,
644 0x00000000);
645 /* Branch contol */
646 spr_register(env, SPR_LR, "LR",
647 &spr_read_lr, &spr_write_lr,
648 &spr_read_lr, &spr_write_lr,
649 0x00000000);
650 spr_register(env, SPR_CTR, "CTR",
651 &spr_read_ctr, &spr_write_ctr,
652 &spr_read_ctr, &spr_write_ctr,
653 0x00000000);
654 /* Interrupt processing */
655 spr_register(env, SPR_SRR0, "SRR0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SRR1, "SRR1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Processor control */
664 spr_register(env, SPR_SPRG0, "SPRG0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SPRG1, "SPRG1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_SPRG2, "SPRG2",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SPRG3, "SPRG3",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680}
681
682/* SPR common to all non-embedded PowerPC, including 601 */
683static void gen_spr_ne_601 (CPUPPCState *env)
684{
685 /* Exception processing */
d67d40ea
DG		 686 spr_register_kvm(env, SPR_DSISR, "DSISR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 KVM_REG_PPC_DSISR, 0x00000000);
690 spr_register_kvm(env, SPR_DAR, "DAR",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_generic,
693 KVM_REG_PPC_DAR, 0x00000000);
3fc6c082
FB		 694 /* Timer */
695 spr_register(env, SPR_DECR, "DECR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_decr, &spr_write_decr,
698 0x00000000);
699 /* Memory management */
700 spr_register(env, SPR_SDR1, "SDR1",
701 SPR_NOACCESS, SPR_NOACCESS,
bb593904 702 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 703 0x00000000);
704}
705
706/* BATs 0-3 */
707static void gen_low_BATs (CPUPPCState *env)
708{
f2e63a42 709#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 710 spr_register(env, SPR_IBAT0U, "IBAT0U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT0L, "IBAT0L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT1U, "IBAT1U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT1L, "IBAT1L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_IBAT2U, "IBAT2U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_ibat, &spr_write_ibatu,
729 0x00000000);
730 spr_register(env, SPR_IBAT2L, "IBAT2L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_ibat, &spr_write_ibatl,
733 0x00000000);
734 spr_register(env, SPR_IBAT3U, "IBAT3U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_ibat, &spr_write_ibatu,
737 0x00000000);
738 spr_register(env, SPR_IBAT3L, "IBAT3L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_ibat, &spr_write_ibatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT0U, "DBAT0U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT0L, "DBAT0L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT1U, "DBAT1U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT1L, "DBAT1L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 spr_register(env, SPR_DBAT2U, "DBAT2U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_dbat, &spr_write_dbatu,
761 0x00000000);
762 spr_register(env, SPR_DBAT2L, "DBAT2L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_dbat, &spr_write_dbatl,
765 0x00000000);
766 spr_register(env, SPR_DBAT3U, "DBAT3U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_dbat, &spr_write_dbatu,
769 0x00000000);
770 spr_register(env, SPR_DBAT3L, "DBAT3L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_dbat, &spr_write_dbatl,
773 0x00000000);
a750fc0b 774 env->nb_BATs += 4;
f2e63a42 775#endif
3fc6c082
FB		 776}
777
778/* BATs 4-7 */
779static void gen_high_BATs (CPUPPCState *env)
780{
f2e63a42 781#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 782 spr_register(env, SPR_IBAT4U, "IBAT4U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT4L, "IBAT4L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT5U, "IBAT5U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT5L, "IBAT5L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_IBAT6U, "IBAT6U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat_h, &spr_write_ibatu_h,
801 0x00000000);
802 spr_register(env, SPR_IBAT6L, "IBAT6L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat_h, &spr_write_ibatl_h,
805 0x00000000);
806 spr_register(env, SPR_IBAT7U, "IBAT7U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat_h, &spr_write_ibatu_h,
809 0x00000000);
810 spr_register(env, SPR_IBAT7L, "IBAT7L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat_h, &spr_write_ibatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT4U, "DBAT4U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT4L, "DBAT4L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT5U, "DBAT5U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT5L, "DBAT5L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 spr_register(env, SPR_DBAT6U, "DBAT6U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat_h, &spr_write_dbatu_h,
833 0x00000000);
834 spr_register(env, SPR_DBAT6L, "DBAT6L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat_h, &spr_write_dbatl_h,
837 0x00000000);
838 spr_register(env, SPR_DBAT7U, "DBAT7U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat_h, &spr_write_dbatu_h,
841 0x00000000);
842 spr_register(env, SPR_DBAT7L, "DBAT7L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat_h, &spr_write_dbatl_h,
845 0x00000000);
a750fc0b 846 env->nb_BATs += 4;
f2e63a42 847#endif
3fc6c082
FB		 848}
849
850/* Generic PowerPC time base */
851static void gen_tbl (CPUPPCState *env)
852{
853 spr_register(env, SPR_VTBL, "TBL",
854 &spr_read_tbl, SPR_NOACCESS,
855 &spr_read_tbl, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 858 &spr_read_tbl, SPR_NOACCESS,
859 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 860 0x00000000);
861 spr_register(env, SPR_VTBU, "TBU",
862 &spr_read_tbu, SPR_NOACCESS,
863 &spr_read_tbu, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 866 &spr_read_tbu, SPR_NOACCESS,
867 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 868 0x00000000);
869}
870
76a66253
JM		 871/* Softare table search registers */
872static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
873{
f2e63a42 874#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 875 env->nb_tlb = nb_tlbs;
876 env->nb_ways = nb_ways;
877 env->id_tlbs = 1;
1c53accc 878 env->tlb_type = TLB_6XX;
76a66253
JM		 879 spr_register(env, SPR_DMISS, "DMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_DCMP, "DCMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_HASH1, "HASH1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 0x00000000);
891 spr_register(env, SPR_HASH2, "HASH2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, SPR_NOACCESS,
894 0x00000000);
895 spr_register(env, SPR_IMISS, "IMISS",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 spr_register(env, SPR_ICMP, "ICMP",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 0x00000000);
903 spr_register(env, SPR_RPA, "RPA",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
f2e63a42 907#endif
76a66253
JM		 908}
909
910/* SPR common to MPC755 and G2 */
911static void gen_spr_G2_755 (CPUPPCState *env)
912{
913 /* SGPRs */
914 spr_register(env, SPR_SPRG4, "SPRG4",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 spr_register(env, SPR_SPRG5, "SPRG5",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 spr_register(env, SPR_SPRG6, "SPRG6",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 spr_register(env, SPR_SPRG7, "SPRG7",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
76a66253
JM		 930}
931
3fc6c082
FB		 932/* SPR common to all 7xx PowerPC implementations */
933static void gen_spr_7xx (CPUPPCState *env)
934{
935 /* Breakpoints */
936 /* XXX : not implemented */
d67d40ea
DG		 937 spr_register_kvm(env, SPR_DABR, "DABR",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082
FB		 941 /* XXX : not implemented */
942 spr_register(env, SPR_IABR, "IABR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* Cache management */
947 /* XXX : not implemented */
948 spr_register(env, SPR_ICTC, "ICTC",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Performance monitors */
953 /* XXX : not implemented */
954 spr_register(env, SPR_MMCR0, "MMCR0",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_MMCR1, "MMCR1",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC1, "PMC1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC2, "PMC2",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_PMC3, "PMC3",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_PMC4, "PMC4",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
a750fc0b 984 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, SPR_NOACCESS,
987 0x00000000);
578bb252 988 /* XXX : not implemented */
3fc6c082
FB		 989 spr_register(env, SPR_UMMCR0, "UMMCR0",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
578bb252 993 /* XXX : not implemented */
3fc6c082
FB		 994 spr_register(env, SPR_UMMCR1, "UMMCR1",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
578bb252 998 /* XXX : not implemented */
3fc6c082
FB		 999 spr_register(env, SPR_UPMC1, "UPMC1",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
578bb252 1003 /* XXX : not implemented */
3fc6c082
FB		 1004 spr_register(env, SPR_UPMC2, "UPMC2",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
578bb252 1008 /* XXX : not implemented */
3fc6c082
FB		 1009 spr_register(env, SPR_UPMC3, "UPMC3",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
578bb252 1013 /* XXX : not implemented */
3fc6c082
FB		 1014 spr_register(env, SPR_UPMC4, "UPMC4",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
578bb252 1018 /* XXX : not implemented */
a750fc0b 1019 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
a750fc0b 1023 /* External access control */
3fc6c082 1024 /* XXX : not implemented */
a750fc0b 1025 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
a750fc0b
JM		 1029}
1030
1031static void gen_spr_thrm (CPUPPCState *env)
1032{
1033 /* Thermal management */
3fc6c082 1034 /* XXX : not implemented */
a750fc0b 1035 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* XXX : not implemented */
a750fc0b 1040 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
3fc6c082 1044 /* XXX : not implemented */
a750fc0b 1045 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049}
1050
1051/* SPR specific to PowerPC 604 implementation */
1052static void gen_spr_604 (CPUPPCState *env)
1053{
1054 /* Processor identification */
1055 spr_register(env, SPR_PIR, "PIR",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_pir,
1058 0x00000000);
1059 /* Breakpoints */
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_IABR, "IABR",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* XXX : not implemented */
d67d40ea
DG		 1066 spr_register_kvm(env, SPR_DABR, "DABR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082
FB		 1070 /* Performance counters */
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_MMCR0, "MMCR0",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
3fc6c082
FB		 1077 spr_register(env, SPR_PMC1, "PMC1",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_PMC2, "PMC2",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 /* XXX : not implemented */
a750fc0b 1087 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_generic, SPR_NOACCESS,
1090 0x00000000);
1091 /* XXX : not implemented */
1092 spr_register(env, SPR_SDA, "SDA",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, SPR_NOACCESS,
1095 0x00000000);
1096 /* External access control */
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_EAR, "EAR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102}
1103
76a66253
JM		 1104/* SPR specific to PowerPC 603 implementation */
1105static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1106{
76a66253
JM		 1107 /* External access control */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1110 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
3fc6c082
FB		 1113}
1114
76a66253
JM		 1115/* SPR specific to PowerPC G2 implementation */
1116static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1117{
76a66253
JM		 1118 /* Memory base address */
1119 /* MBAR */
578bb252 1120 /* XXX : not implemented */
76a66253
JM		 1121 spr_register(env, SPR_MBAR, "MBAR",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
76a66253 1125 /* Exception processing */
363be49c 1126 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
363be49c 1130 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* Breakpoints */
1135 /* XXX : not implemented */
1136 spr_register(env, SPR_DABR, "DABR",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_generic,
1139 0x00000000);
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_DABR2, "DABR2",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_IABR, "IABR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_IABR2, "IABR2",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_IBCR, "IBCR",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_DBCR, "DBCR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165}
1166
1167/* SPR specific to PowerPC 602 implementation */
1168static void gen_spr_602 (CPUPPCState *env)
1169{
1170 /* ESA registers */
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_SER, "SER",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_SEBR, "SEBR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* XXX : not implemented */
a750fc0b 1182 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* Floating point status */
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_SP, "SP",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_LT, "LT",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 /* Watchdog timer */
1198 /* XXX : not implemented */
1199 spr_register(env, SPR_TCR, "TCR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203 /* Interrupt base */
1204 spr_register(env, SPR_IBR, "IBR",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
a750fc0b
JM		 1208 /* XXX : not implemented */
1209 spr_register(env, SPR_IABR, "IABR",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
76a66253
JM		 1213}
1214
1215/* SPR specific to PowerPC 601 implementation */
1216static void gen_spr_601 (CPUPPCState *env)
1217{
1218 /* Multiplication/division register */
1219 /* MQ */
1220 spr_register(env, SPR_MQ, "MQ",
1221 &spr_read_generic, &spr_write_generic,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* RTC registers */
1225 spr_register(env, SPR_601_RTCU, "RTCU",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 SPR_NOACCESS, &spr_write_601_rtcu,
1228 0x00000000);
1229 spr_register(env, SPR_601_VRTCU, "RTCU",
1230 &spr_read_601_rtcu, SPR_NOACCESS,
1231 &spr_read_601_rtcu, SPR_NOACCESS,
1232 0x00000000);
1233 spr_register(env, SPR_601_RTCL, "RTCL",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 SPR_NOACCESS, &spr_write_601_rtcl,
1236 0x00000000);
1237 spr_register(env, SPR_601_VRTCL, "RTCL",
1238 &spr_read_601_rtcl, SPR_NOACCESS,
1239 &spr_read_601_rtcl, SPR_NOACCESS,
1240 0x00000000);
1241 /* Timer */
1242#if 0 /* ? */
1243 spr_register(env, SPR_601_UDECR, "UDECR",
1244 &spr_read_decr, SPR_NOACCESS,
1245 &spr_read_decr, SPR_NOACCESS,
1246 0x00000000);
1247#endif
1248 /* External access control */
1249 /* XXX : not implemented */
1250 spr_register(env, SPR_EAR, "EAR",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 /* Memory management */
f2e63a42 1255#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1256 spr_register(env, SPR_IBAT0U, "IBAT0U",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_601_ubat, &spr_write_601_ubatu,
1259 0x00000000);
1260 spr_register(env, SPR_IBAT0L, "IBAT0L",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_601_ubat, &spr_write_601_ubatl,
1263 0x00000000);
1264 spr_register(env, SPR_IBAT1U, "IBAT1U",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_601_ubat, &spr_write_601_ubatu,
1267 0x00000000);
1268 spr_register(env, SPR_IBAT1L, "IBAT1L",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_601_ubat, &spr_write_601_ubatl,
1271 0x00000000);
1272 spr_register(env, SPR_IBAT2U, "IBAT2U",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_601_ubat, &spr_write_601_ubatu,
1275 0x00000000);
1276 spr_register(env, SPR_IBAT2L, "IBAT2L",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_601_ubat, &spr_write_601_ubatl,
1279 0x00000000);
1280 spr_register(env, SPR_IBAT3U, "IBAT3U",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_601_ubat, &spr_write_601_ubatu,
1283 0x00000000);
1284 spr_register(env, SPR_IBAT3L, "IBAT3L",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_601_ubat, &spr_write_601_ubatl,
1287 0x00000000);
a750fc0b 1288 env->nb_BATs = 4;
f2e63a42 1289#endif
a750fc0b
JM		 1290}
1291
1292static void gen_spr_74xx (CPUPPCState *env)
1293{
1294 /* Processor identification */
1295 spr_register(env, SPR_PIR, "PIR",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_pir,
1298 0x00000000);
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_MMCR2, "MMCR2",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
578bb252 1304 /* XXX : not implemented */
a750fc0b
JM		 1305 spr_register(env, SPR_UMMCR2, "UMMCR2",
1306 &spr_read_ureg, SPR_NOACCESS,
1307 &spr_read_ureg, SPR_NOACCESS,
1308 0x00000000);
1309 /* XXX: not implemented */
1310 spr_register(env, SPR_BAMR, "BAMR",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
578bb252 1314 /* XXX : not implemented */
a750fc0b
JM		 1315 spr_register(env, SPR_MSSCR0, "MSSCR0",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* Hardware implementation registers */
1320 /* XXX : not implemented */
1321 spr_register(env, SPR_HID0, "HID0",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_HID1, "HID1",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 /* Altivec */
1331 spr_register(env, SPR_VRSAVE, "VRSAVE",
1332 &spr_read_generic, &spr_write_generic,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
bd928eba
JM		 1335 /* XXX : not implemented */
1336 spr_register(env, SPR_L2CR, "L2CR",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
cf8358c8
AJ		 1340 /* Not strictly an SPR */
1341 vscr_init(env, 0x00010000);
a750fc0b
JM		 1342}
1343
a750fc0b
JM		 1344static void gen_l3_ctrl (CPUPPCState *env)
1345{
1346 /* L3CR */
1347 /* XXX : not implemented */
1348 spr_register(env, SPR_L3CR, "L3CR",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 /* L3ITCR0 */
578bb252 1353 /* XXX : not implemented */
a750fc0b
JM		 1354 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
a750fc0b 1358 /* L3PM */
578bb252 1359 /* XXX : not implemented */
a750fc0b
JM		 1360 spr_register(env, SPR_L3PM, "L3PM",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364}
a750fc0b 1365
578bb252 1366static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1367{
f2e63a42 1368#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1369 env->nb_tlb = nb_tlbs;
1370 env->nb_ways = nb_ways;
1371 env->id_tlbs = 1;
1c53accc 1372 env->tlb_type = TLB_6XX;
578bb252 1373 /* XXX : not implemented */
a750fc0b
JM		 1374 spr_register(env, SPR_PTEHI, "PTEHI",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
578bb252 1378 /* XXX : not implemented */
a750fc0b
JM		 1379 spr_register(env, SPR_PTELO, "PTELO",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
578bb252 1383 /* XXX : not implemented */
a750fc0b
JM		 1384 spr_register(env, SPR_TLBMISS, "TLBMISS",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
f2e63a42 1388#endif
76a66253
JM		 1389}
1390
01662f3e
AG		 1391#if !defined(CONFIG_USER_ONLY)
1392static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1393{
1394 TCGv t0 = tcg_temp_new();
1395
1396 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1397 gen_store_spr(sprn, t0);
1398 tcg_temp_free(t0);
1399}
1400
1401static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1402{
1ff7854e 1403 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1404 gen_helper_booke206_tlbflush(cpu_env, t0);
1ff7854e 1405 tcg_temp_free_i32(t0);
01662f3e
AG		 1406}
1407
1408static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1409{
1ff7854e 1410 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1411 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1ff7854e 1412 tcg_temp_free_i32(t0);
01662f3e
AG		 1413}
1414#endif
1415
80d11f44 1416static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1417{
80d11f44
JM		 1418 spr_register(env, SPR_USPRG4, "USPRG4",
1419 &spr_read_ureg, SPR_NOACCESS,
1420 &spr_read_ureg, SPR_NOACCESS,
1421 0x00000000);
1422 spr_register(env, SPR_USPRG5, "USPRG5",
1423 &spr_read_ureg, SPR_NOACCESS,
1424 &spr_read_ureg, SPR_NOACCESS,
1425 0x00000000);
1426 spr_register(env, SPR_USPRG6, "USPRG6",
1427 &spr_read_ureg, SPR_NOACCESS,
1428 &spr_read_ureg, SPR_NOACCESS,
1429 0x00000000);
1430 spr_register(env, SPR_USPRG7, "USPRG7",
1431 &spr_read_ureg, SPR_NOACCESS,
1432 &spr_read_ureg, SPR_NOACCESS,
76a66253 1433 0x00000000);
80d11f44
JM		 1434}
1435
1436/* PowerPC BookE SPR */
1437static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1438{
b55266b5 1439 const char *ivor_names[64] = {
80d11f44
JM		 1440 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1441 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1442 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1443 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1444 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1445 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1446 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1447 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1448 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1449 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1450 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1451 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1452 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1453 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1454 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1455 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1456 };
1457#define SPR_BOOKE_IVORxx (-1)
1458 int ivor_sprn[64] = {
1459 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1460 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1461 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1462 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1466 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1467 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 1468 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1469 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 1470 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1471 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1472 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1473 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1474 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1475 };
1476 int i;
1477
76a66253 1478 /* Interrupt processing */
363be49c 1479 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
363be49c
JM		 1483 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
76a66253
JM		 1487 /* Debug */
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
76a66253
JM		 1499 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 /* XXX : not implemented */
1504 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 /* XXX : not implemented */
76a66253
JM		 1509 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1510 SPR_NOACCESS, SPR_NOACCESS,
e598a9c5 1511 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1512 0x00000000);
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 /* XXX : not implemented */
1519 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 /* XXX : not implemented */
1524 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1525 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1526 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1527 0x00000000);
1528 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 spr_register(env, SPR_BOOKE_ESR, "ESR",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
363be49c
JM		 1536 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1537 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1538 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1539 0x00000000);
1540 /* Exception vectors */
80d11f44
JM		 1541 for (i = 0; i < 64; i++) {
1542 if (ivor_mask & (1ULL << i)) {
1543 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1544 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1545 exit(1);
1546 }
1547 spr_register(env, ivor_sprn[i], ivor_names[i],
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_excp_vector,
1550 0x00000000);
1551 }
1552 }
76a66253
JM		 1553 spr_register(env, SPR_BOOKE_PID, "PID",
1554 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1555 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1556 0x00000000);
1557 spr_register(env, SPR_BOOKE_TCR, "TCR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_booke_tcr,
1560 0x00000000);
1561 spr_register(env, SPR_BOOKE_TSR, "TSR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_booke_tsr,
1564 0x00000000);
1565 /* Timer */
1566 spr_register(env, SPR_DECR, "DECR",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_decr, &spr_write_decr,
1569 0x00000000);
1570 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 SPR_NOACCESS, &spr_write_generic,
1573 0x00000000);
1574 /* SPRGs */
1575 spr_register(env, SPR_USPRG0, "USPRG0",
1576 &spr_read_generic, &spr_write_generic,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 spr_register(env, SPR_SPRG4, "SPRG4",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
76a66253
JM		 1583 spr_register(env, SPR_SPRG5, "SPRG5",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
76a66253
JM		 1587 spr_register(env, SPR_SPRG6, "SPRG6",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
76a66253
JM		 1591 spr_register(env, SPR_SPRG7, "SPRG7",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
76a66253
JM		 1595}
1596
01662f3e
AG		 1597static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1598 uint32_t maxsize, uint32_t flags,
1599 uint32_t nentries)
1600{
1601 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1602 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1603 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1604 flags | nentries;
1605}
1606
1607/* BookE 2.06 storage control registers */
1608static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1609 uint32_t *tlbncfg)
363be49c 1610{
f2e63a42 1611#if !defined(CONFIG_USER_ONLY)
b55266b5 1612 const char *mas_names[8] = {
80d11f44
JM		 1613 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1614 };
1615 int mas_sprn[8] = {
1616 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1617 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1618 };
1619 int i;
1620
363be49c 1621 /* TLB assist registers */
578bb252 1622 /* XXX : not implemented */
80d11f44 1623 for (i = 0; i < 8; i++) {
ba38ab8d
AG		 1624 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1625 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1626 uea_write = &spr_write_generic;
1627 }
80d11f44
JM		 1628 if (mas_mask & (1 << i)) {
1629 spr_register(env, mas_sprn[i], mas_names[i],
1630 SPR_NOACCESS, SPR_NOACCESS,
ba38ab8d 1631 &spr_read_generic, uea_write,
80d11f44
JM		 1632 0x00000000);
1633 }
1634 }
363be49c 1635 if (env->nb_pids > 1) {
578bb252 1636 /* XXX : not implemented */
363be49c
JM		 1637 spr_register(env, SPR_BOOKE_PID1, "PID1",
1638 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1639 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1640 0x00000000);
1641 }
1642 if (env->nb_pids > 2) {
578bb252 1643 /* XXX : not implemented */
363be49c
JM		 1644 spr_register(env, SPR_BOOKE_PID2, "PID2",
1645 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1646 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1647 0x00000000);
1648 }
578bb252 1649 /* XXX : not implemented */
65f9ee8d 1650 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, SPR_NOACCESS,
1653 0x00000000); /* TOFIX */
363be49c
JM		 1654 switch (env->nb_ways) {
1655 case 4:
1656 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, SPR_NOACCESS,
01662f3e 1659 tlbncfg[3]);
363be49c
JM		 1660 /* Fallthru */
1661 case 3:
1662 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, SPR_NOACCESS,
01662f3e 1665 tlbncfg[2]);
363be49c
JM		 1666 /* Fallthru */
1667 case 2:
1668 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, SPR_NOACCESS,
01662f3e 1671 tlbncfg[1]);
363be49c
JM		 1672 /* Fallthru */
1673 case 1:
1674 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, SPR_NOACCESS,
01662f3e 1677 tlbncfg[0]);
363be49c
JM		 1678 /* Fallthru */
1679 case 0:
1680 default:
1681 break;
1682 }
f2e63a42 1683#endif
01662f3e
AG		 1684
1685 gen_spr_usprgh(env);
363be49c
JM		 1686}
1687
76a66253
JM		 1688/* SPR specific to PowerPC 440 implementation */
1689static void gen_spr_440 (CPUPPCState *env)
1690{
1691 /* Cache control */
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DNV0, "DNV0",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DNV1, "DNV1",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_DNV2, "DNV2",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_DNV3, "DNV3",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
2662a059 1713 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
2662a059 1718 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
2662a059 1723 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
2662a059 1728 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_DVLIM, "DVLIM",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_INV0, "INV0",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_INV1, "INV1",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_INV2, "INV2",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_INV3, "INV3",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
2662a059 1758 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
2662a059 1763 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
2662a059 1768 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
2662a059 1773 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_440_IVLIM, "IVLIM",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* Cache debug */
1783 /* XXX : not implemented */
2662a059 1784 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* XXX : not implemented */
2662a059 1789 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, SPR_NOACCESS,
1792 0x00000000);
1793 /* XXX : not implemented */
2662a059 1794 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, SPR_NOACCESS,
1797 0x00000000);
1798 /* XXX : not implemented */
2662a059 1799 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, SPR_NOACCESS,
1802 0x00000000);
1803 /* XXX : not implemented */
2662a059 1804 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, SPR_NOACCESS,
1807 0x00000000);
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_440_DBDR, "DBDR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* Processor control */
1814 spr_register(env, SPR_4xx_CCR0, "CCR0",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, SPR_NOACCESS,
1821 0x00000000);
1822 /* Storage control */
1823 spr_register(env, SPR_440_MMUCR, "MMUCR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827}
1828
1829/* SPR shared between PowerPC 40x implementations */
1830static void gen_spr_40x (CPUPPCState *env)
1831{
1832 /* Cache */
5cbdb3a3 1833 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1834 spr_register(env, SPR_40x_DCCR, "DCCR",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, &spr_write_generic,
1837 0x00000000);
5cbdb3a3 1838 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1839 spr_register(env, SPR_40x_ICCR, "ICCR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
5cbdb3a3 1843 /* not emulated, as QEMU do not emulate caches */
2662a059 1844 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, SPR_NOACCESS,
1847 0x00000000);
76a66253
JM		 1848 /* Exception */
1849 spr_register(env, SPR_40x_DEAR, "DEAR",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 spr_register(env, SPR_40x_ESR, "ESR",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_40x_EVPR, "EVPR",
1858 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1859 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1860 0x00000000);
1861 spr_register(env, SPR_40x_SRR2, "SRR2",
1862 &spr_read_generic, &spr_write_generic,
1863 &spr_read_generic, &spr_write_generic,
1864 0x00000000);
1865 spr_register(env, SPR_40x_SRR3, "SRR3",
1866 &spr_read_generic, &spr_write_generic,
1867 &spr_read_generic, &spr_write_generic,
1868 0x00000000);
1869 /* Timers */
1870 spr_register(env, SPR_40x_PIT, "PIT",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_40x_pit, &spr_write_40x_pit,
1873 0x00000000);
1874 spr_register(env, SPR_40x_TCR, "TCR",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_booke_tcr,
1877 0x00000000);
1878 spr_register(env, SPR_40x_TSR, "TSR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_booke_tsr,
1881 0x00000000);
2662a059
JM		 1882}
1883
1884/* SPR specific to PowerPC 405 implementation */
1885static void gen_spr_405 (CPUPPCState *env)
1886{
1887 /* MMU */
1888 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
2662a059 1892 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1895 0x00700000);
1896 /* Debug interface */
76a66253
JM		 1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1899 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1900 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1901 0x00000000);
1902 /* XXX : not implemented */
2662a059
JM		 1903 spr_register(env, SPR_405_DBCR1, "DBCR1",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
76a66253
JM		 1908 spr_register(env, SPR_40x_DBSR, "DBSR",
1909 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1910 &spr_read_generic, &spr_write_clear,
1911 /* Last reset was system reset */
76a66253
JM		 1912 0x00000300);
1913 /* XXX : not implemented */
2662a059 1914 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
2662a059 1918 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
2662a059
JM		 1922 /* XXX : not implemented */
1923 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
2662a059 1926 0x00000000);
76a66253 1927 /* XXX : not implemented */
2662a059 1928 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
2662a059 1933 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
2662a059 1937 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_405_IAC3, "IAC3",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_405_IAC4, "IAC4",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951 /* Storage control */
035feb88 1952 /* XXX: TODO: not implemented */
76a66253
JM		 1953 spr_register(env, SPR_405_SLER, "SLER",
1954 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1955 &spr_read_generic, &spr_write_40x_sler,
76a66253 1956 0x00000000);
2662a059
JM		 1957 spr_register(env, SPR_40x_ZPR, "ZPR",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
76a66253
JM		 1961 /* XXX : not implemented */
1962 spr_register(env, SPR_405_SU0R, "SU0R",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 /* SPRG */
1967 spr_register(env, SPR_USPRG0, "USPRG0",
1968 &spr_read_ureg, SPR_NOACCESS,
1969 &spr_read_ureg, SPR_NOACCESS,
1970 0x00000000);
1971 spr_register(env, SPR_SPRG4, "SPRG4",
1972 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1973 &spr_read_generic, &spr_write_generic,
76a66253 1974 0x00000000);
76a66253
JM		 1975 spr_register(env, SPR_SPRG5, "SPRG5",
1976 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1977 spr_read_generic, &spr_write_generic,
76a66253 1978 0x00000000);
76a66253
JM		 1979 spr_register(env, SPR_SPRG6, "SPRG6",
1980 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1981 spr_read_generic, &spr_write_generic,
76a66253 1982 0x00000000);
76a66253
JM		 1983 spr_register(env, SPR_SPRG7, "SPRG7",
1984 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1985 spr_read_generic, &spr_write_generic,
76a66253 1986 0x00000000);
80d11f44 1987 gen_spr_usprgh(env);
76a66253
JM		 1988}
1989
1990/* SPR shared between PowerPC 401 & 403 implementations */
1991static void gen_spr_401_403 (CPUPPCState *env)
1992{
1993 /* Time base */
1994 spr_register(env, SPR_403_VTBL, "TBL",
1995 &spr_read_tbl, SPR_NOACCESS,
1996 &spr_read_tbl, SPR_NOACCESS,
1997 0x00000000);
1998 spr_register(env, SPR_403_TBL, "TBL",
1999 SPR_NOACCESS, SPR_NOACCESS,
2000 SPR_NOACCESS, &spr_write_tbl,
2001 0x00000000);
2002 spr_register(env, SPR_403_VTBU, "TBU",
2003 &spr_read_tbu, SPR_NOACCESS,
2004 &spr_read_tbu, SPR_NOACCESS,
2005 0x00000000);
2006 spr_register(env, SPR_403_TBU, "TBU",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 SPR_NOACCESS, &spr_write_tbu,
2009 0x00000000);
2010 /* Debug */
5cbdb3a3 2011 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2012 spr_register(env, SPR_403_CDBCR, "CDBCR",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016}
2017
2662a059
JM		 2018/* SPR specific to PowerPC 401 implementation */
2019static void gen_spr_401 (CPUPPCState *env)
2020{
2021 /* Debug interface */
2022 /* XXX : not implemented */
2023 spr_register(env, SPR_40x_DBCR0, "DBCR",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_40x_dbcr0,
2026 0x00000000);
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_40x_DBSR, "DBSR",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_clear,
2031 /* Last reset was system reset */
2032 0x00000300);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_40x_DAC1, "DAC",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_40x_IAC1, "IAC",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* Storage control */
035feb88 2044 /* XXX: TODO: not implemented */
2662a059
JM		 2045 spr_register(env, SPR_405_SLER, "SLER",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_40x_sler,
2048 0x00000000);
5cbdb3a3 2049 /* not emulated, as QEMU never does speculative access */
035feb88
JM		 2050 spr_register(env, SPR_40x_SGR, "SGR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0xFFFFFFFF);
5cbdb3a3 2054 /* not emulated, as QEMU do not emulate caches */
035feb88
JM		 2055 spr_register(env, SPR_40x_DCWR, "DCWR",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2662a059
JM		 2059}
2060
a750fc0b
JM		 2061static void gen_spr_401x2 (CPUPPCState *env)
2062{
2063 gen_spr_401(env);
2064 spr_register(env, SPR_40x_PID, "PID",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 spr_register(env, SPR_40x_ZPR, "ZPR",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072}
2073
76a66253
JM		 2074/* SPR specific to PowerPC 403 implementation */
2075static void gen_spr_403 (CPUPPCState *env)
2076{
2662a059
JM		 2077 /* Debug interface */
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_40x_dbcr0,
2082 0x00000000);
2083 /* XXX : not implemented */
2084 spr_register(env, SPR_40x_DBSR, "DBSR",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_clear,
2087 /* Last reset was system reset */
2088 0x00000300);
2089 /* XXX : not implemented */
2090 spr_register(env, SPR_40x_DAC1, "DAC1",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
578bb252 2094 /* XXX : not implemented */
2662a059
JM		 2095 spr_register(env, SPR_40x_DAC2, "DAC2",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
2099 /* XXX : not implemented */
2100 spr_register(env, SPR_40x_IAC1, "IAC1",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
578bb252 2104 /* XXX : not implemented */
2662a059
JM		 2105 spr_register(env, SPR_40x_IAC2, "IAC2",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
a750fc0b
JM		 2109}
2110
2111static void gen_spr_403_real (CPUPPCState *env)
2112{
76a66253
JM		 2113 spr_register(env, SPR_403_PBL1, "PBL1",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_403_pbr, &spr_write_403_pbr,
2116 0x00000000);
2117 spr_register(env, SPR_403_PBU1, "PBU1",
2118 SPR_NOACCESS, SPR_NOACCESS,
2119 &spr_read_403_pbr, &spr_write_403_pbr,
2120 0x00000000);
2121 spr_register(env, SPR_403_PBL2, "PBL2",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_403_pbr, &spr_write_403_pbr,
2124 0x00000000);
2125 spr_register(env, SPR_403_PBU2, "PBU2",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_403_pbr, &spr_write_403_pbr,
2128 0x00000000);
a750fc0b
JM		 2129}
2130
2131static void gen_spr_403_mmu (CPUPPCState *env)
2132{
2133 /* MMU */
2134 spr_register(env, SPR_40x_PID, "PID",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2662a059 2138 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142}
2143
2144/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2145static void gen_spr_compress (CPUPPCState *env)
2146{
578bb252 2147 /* XXX : not implemented */
76a66253
JM		 2148 spr_register(env, SPR_401_SKR, "SKR",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152}
a750fc0b
JM		 2153
2154#if defined (TARGET_PPC64)
a750fc0b
JM		 2155/* SPR specific to PowerPC 620 */
2156static void gen_spr_620 (CPUPPCState *env)
2157{
082c6681
JM		 2158 /* Processor identification */
2159 spr_register(env, SPR_PIR, "PIR",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_pir,
2162 0x00000000);
2163 spr_register(env, SPR_ASR, "ASR",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_asr, &spr_write_asr,
2166 0x00000000);
2167 /* Breakpoints */
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_IABR, "IABR",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_DABR, "DABR",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_SIAR, "SIAR",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, SPR_NOACCESS,
2182 0x00000000);
2183 /* XXX : not implemented */
2184 spr_register(env, SPR_SDA, "SDA",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, SPR_NOACCESS,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMC1R, "PMC1",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, SPR_NOACCESS,
2192 0x00000000);
2193 spr_register(env, SPR_620_PMC1W, "PMC1",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 SPR_NOACCESS, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_PMC2R, "PMC2",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, SPR_NOACCESS,
2201 0x00000000);
2202 spr_register(env, SPR_620_PMC2W, "PMC2",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 SPR_NOACCESS, &spr_write_generic,
2205 0x00000000);
2206 /* XXX : not implemented */
2207 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, SPR_NOACCESS,
2210 0x00000000);
2211 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 SPR_NOACCESS, &spr_write_generic,
2214 0x00000000);
2215 /* External access control */
2216 /* XXX : not implemented */
2217 spr_register(env, SPR_EAR, "EAR",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221#if 0 // XXX: check this
578bb252 2222 /* XXX : not implemented */
a750fc0b
JM		 2223 spr_register(env, SPR_620_PMR0, "PMR0",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
578bb252 2227 /* XXX : not implemented */
a750fc0b
JM		 2228 spr_register(env, SPR_620_PMR1, "PMR1",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
578bb252 2232 /* XXX : not implemented */
a750fc0b
JM		 2233 spr_register(env, SPR_620_PMR2, "PMR2",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
578bb252 2237 /* XXX : not implemented */
a750fc0b
JM		 2238 spr_register(env, SPR_620_PMR3, "PMR3",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
578bb252 2242 /* XXX : not implemented */
a750fc0b
JM		 2243 spr_register(env, SPR_620_PMR4, "PMR4",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
578bb252 2247 /* XXX : not implemented */
a750fc0b
JM		 2248 spr_register(env, SPR_620_PMR5, "PMR5",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
578bb252 2252 /* XXX : not implemented */
a750fc0b
JM		 2253 spr_register(env, SPR_620_PMR6, "PMR6",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
578bb252 2257 /* XXX : not implemented */
a750fc0b
JM		 2258 spr_register(env, SPR_620_PMR7, "PMR7",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
578bb252 2262 /* XXX : not implemented */
a750fc0b
JM		 2263 spr_register(env, SPR_620_PMR8, "PMR8",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
578bb252 2267 /* XXX : not implemented */
a750fc0b
JM		 2268 spr_register(env, SPR_620_PMR9, "PMR9",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
578bb252 2272 /* XXX : not implemented */
a750fc0b
JM		 2273 spr_register(env, SPR_620_PMRA, "PMR10",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
578bb252 2277 /* XXX : not implemented */
a750fc0b
JM		 2278 spr_register(env, SPR_620_PMRB, "PMR11",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
578bb252 2282 /* XXX : not implemented */
a750fc0b
JM		 2283 spr_register(env, SPR_620_PMRC, "PMR12",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
578bb252 2287 /* XXX : not implemented */
a750fc0b
JM		 2288 spr_register(env, SPR_620_PMRD, "PMR13",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
578bb252 2292 /* XXX : not implemented */
a750fc0b
JM		 2293 spr_register(env, SPR_620_PMRE, "PMR14",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
578bb252 2297 /* XXX : not implemented */
a750fc0b
JM		 2298 spr_register(env, SPR_620_PMRF, "PMR15",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
082c6681 2302#endif
578bb252 2303 /* XXX : not implemented */
082c6681 2304 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
578bb252 2308 /* XXX : not implemented */
082c6681
JM		 2309 spr_register(env, SPR_620_L2CR, "L2CR",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318}
a750fc0b 2319#endif /* defined (TARGET_PPC64) */
76a66253 2320
80d11f44 2321static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2322{
80d11f44 2323 /* Exception processing */
d67d40ea
DG		 2324 spr_register_kvm(env, SPR_DSISR, "DSISR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 KVM_REG_PPC_DSISR, 0x00000000);
2328 spr_register_kvm(env, SPR_DAR, "DAR",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 KVM_REG_PPC_DAR, 0x00000000);
80d11f44
JM		 2332 /* Timer */
2333 spr_register(env, SPR_DECR, "DECR",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_decr, &spr_write_decr,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_EIE, "EIE",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_EID, "EID",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_NRI, "NRI",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_CMPA, "CMPA",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPB, "CMPB",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_CMPC, "CMPC",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_CMPD, "CMPD",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_ECR, "ECR",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_DER, "DER",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_CMPE, "CMPE",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_CMPF, "CMPF",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_CMPG, "CMPG",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_CMPH, "CMPH",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_BAR, "BAR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_DPDR, "DPDR",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_IMMR, "IMMR",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437}
2438
2439static void gen_spr_5xx (CPUPPCState *env)
2440{
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546}
2547
2548static void gen_spr_8xx (CPUPPCState *env)
2549{
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 /* XXX : not implemented */
2656 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 /* XXX : not implemented */
2661 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665 /* XXX : not implemented */
2666 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670 /* XXX : not implemented */
2671 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675}
2676
2677// XXX: TODO
2678/*
2679 * AMR => SPR 29 (Power 2.04)
2680 * CTRL => SPR 136 (Power 2.04)
2681 * CTRL => SPR 152 (Power 2.04)
2682 * SCOMC => SPR 276 (64 bits ?)
2683 * SCOMD => SPR 277 (64 bits ?)
2684 * TBU40 => SPR 286 (Power 2.04 hypv)
2685 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2686 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2687 * HDSISR => SPR 306 (Power 2.04 hypv)
2688 * HDAR => SPR 307 (Power 2.04 hypv)
2689 * PURR => SPR 309 (Power 2.04 hypv)
2690 * HDEC => SPR 310 (Power 2.04 hypv)
2691 * HIOR => SPR 311 (hypv)
2692 * RMOR => SPR 312 (970)
2693 * HRMOR => SPR 313 (Power 2.04 hypv)
2694 * HSRR0 => SPR 314 (Power 2.04 hypv)
2695 * HSRR1 => SPR 315 (Power 2.04 hypv)
2696 * LPCR => SPR 316 (970)
2697 * LPIDR => SPR 317 (970)
80d11f44
JM		 2698 * EPR => SPR 702 (Power 2.04 emb)
2699 * perf => 768-783 (Power 2.04)
2700 * perf => 784-799 (Power 2.04)
2701 * PPR => SPR 896 (Power 2.04)
2702 * EPLC => SPR 947 (Power 2.04 emb)
2703 * EPSC => SPR 948 (Power 2.04 emb)
2704 * DABRX => 1015 (Power 2.04 hypv)
2705 * FPECR => SPR 1022 (?)
2706 * ... and more (thermal management, performance counters, ...)
2707 */
2708
2709/*****************************************************************************/
2710/* Exception vectors models */
2711static void init_excp_4xx_real (CPUPPCState *env)
2712{
2713#if !defined(CONFIG_USER_ONLY)
2714 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2715 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2716 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2717 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2718 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2719 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2720 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2721 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2722 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2723 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2724 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2725 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2726 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2727 /* Hardware reset vector */
2728 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2729#endif
2730}
2731
80d11f44
JM		 2732static void init_excp_4xx_softmmu (CPUPPCState *env)
2733{
2734#if !defined(CONFIG_USER_ONLY)
2735 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2736 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2737 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2738 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2739 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2740 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2741 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2742 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2743 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2744 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2745 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2746 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2747 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2748 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2749 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2750 env->ivor_mask = 0x0000FFF0UL;
2751 env->ivpr_mask = 0xFFFF0000UL;
2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
2754#endif
2755}
2756
2757static void init_excp_MPC5xx (CPUPPCState *env)
2758{
2759#if !defined(CONFIG_USER_ONLY)
2760 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2761 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2762 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2763 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2764 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2765 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2767 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2768 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2769 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2770 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2771 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2772 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2773 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2774 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2775 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2776 env->ivor_mask = 0x0000FFF0UL;
2777 env->ivpr_mask = 0xFFFF0000UL;
2778 /* Hardware reset vector */
2779 env->hreset_vector = 0xFFFFFFFCUL;
2780#endif
2781}
2782
2783static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2784{
2785#if !defined(CONFIG_USER_ONLY)
2786 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2787 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2788 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2789 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2790 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2791 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2792 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2793 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2795 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2796 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2797 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2798 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2799 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2800 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2801 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2802 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2803 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2804 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2805 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2806 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2807 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2808 env->ivor_mask = 0x0000FFF0UL;
2809 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2810 /* Hardware reset vector */
80d11f44 2811 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2812#endif
2813}
2814
80d11f44 2815static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2816{
2817#if !defined(CONFIG_USER_ONLY)
2818 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2819 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2820 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2821 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2822 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2823 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2824 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2825 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2826 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2827 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2828 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2829 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2830 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2831 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2832 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2833 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2834 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2835 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2836 /* Hardware reset vector */
2837 env->hreset_vector = 0xFFFFFFFCUL;
2838#endif
2839}
2840
e9cd84b9 2841static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
80d11f44
JM		 2842{
2843#if !defined(CONFIG_USER_ONLY)
2844 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2845 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2864 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2865 env->ivor_mask = 0x0000FFF7UL;
e9cd84b9 2866 env->ivpr_mask = ivpr_mask;
80d11f44
JM		 2867 /* Hardware reset vector */
2868 env->hreset_vector = 0xFFFFFFFCUL;
2869#endif
2870}
2871
2872static void init_excp_BookE (CPUPPCState *env)
2873{
2874#if !defined(CONFIG_USER_ONLY)
2875 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2883 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2884 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2885 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2886 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2887 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2888 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2889 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2890 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2891 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2892 env->ivor_mask = 0x0000FFE0UL;
2893 env->ivpr_mask = 0xFFFF0000UL;
2894 /* Hardware reset vector */
2895 env->hreset_vector = 0xFFFFFFFCUL;
2896#endif
2897}
2898
2899static void init_excp_601 (CPUPPCState *env)
2900{
2901#if !defined(CONFIG_USER_ONLY)
2902 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2910 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2911 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2912 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2913 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2914 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2915 /* Hardware reset vector */
80d11f44 2916 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2917#endif
2918}
2919
80d11f44 2920static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2921{
2922#if !defined(CONFIG_USER_ONLY)
082c6681 2923 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2924 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2925 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2926 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2927 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2928 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2929 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2930 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2931 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2932 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2933 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2934 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2935 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2936 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2937 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2938 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2939 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2940 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2941 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2942 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2943 /* Hardware reset vector */
2944 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2945#endif
2946}
2947
80d11f44 2948static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2949{
2950#if !defined(CONFIG_USER_ONLY)
2951 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2952 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2953 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2954 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2955 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2956 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2957 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2958 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2959 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2960 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2961 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2962 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2963 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2964 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2965 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2966 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2967 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2968 /* Hardware reset vector */
2969 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2970#endif
2971}
2972
2973static void init_excp_604 (CPUPPCState *env)
2974{
2975#if !defined(CONFIG_USER_ONLY)
2976 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2977 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2978 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2979 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2980 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2981 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2982 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2983 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2984 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2985 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2986 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2987 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2988 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2989 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2990 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2991 /* Hardware reset vector */
2d3eb7bf 2992 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2993#endif
2994}
2995
578bb252 2996#if defined(TARGET_PPC64)
e1833e1f
JM		 2997static void init_excp_620 (CPUPPCState *env)
2998{
2999#if !defined(CONFIG_USER_ONLY)
3000 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3001 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3002 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3003 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3004 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3005 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3006 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3007 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3008 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3009 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3010 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 3011 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3012 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3013 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3014 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 3015 /* Hardware reset vector */
faadf50e 3016 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3017#endif
3018}
578bb252 3019#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 3020
3021static void init_excp_7x0 (CPUPPCState *env)
3022{
3023#if !defined(CONFIG_USER_ONLY)
3024 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3025 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3026 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3027 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3033 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3034 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3035 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3036 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3037 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3038 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3039 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3040 /* Hardware reset vector */
3041 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3042#endif
3043}
3044
bd928eba 3045static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3046{
3047#if !defined(CONFIG_USER_ONLY)
3048 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3049 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3050 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3051 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3052 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3053 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3054 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3055 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3056 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3057 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3058 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3059 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3060 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3061 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3062 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3063 /* Hardware reset vector */
3064 env->hreset_vector = 0xFFFFFFFCUL;
3065#endif
3066}
3067
3068static void init_excp_750cx (CPUPPCState *env)
3069{
3070#if !defined(CONFIG_USER_ONLY)
3071 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3072 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3073 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3074 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3075 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3076 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3077 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3078 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3079 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3080 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3081 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3082 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3083 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3084 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3085 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3086 /* Hardware reset vector */
3087 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3088#endif
3089}
3090
7a3a6927
JM		 3091/* XXX: Check if this is correct */
3092static void init_excp_7x5 (CPUPPCState *env)
3093{
3094#if !defined(CONFIG_USER_ONLY)
3095 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3096 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3097 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3098 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3099 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3100 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3101 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3102 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3103 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3104 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3105 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3106 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3107 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3108 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3109 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3110 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3111 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3112 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3113 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3114 /* Hardware reset vector */
3115 env->hreset_vector = 0xFFFFFFFCUL;
3116#endif
3117}
3118
e1833e1f
JM		 3119static void init_excp_7400 (CPUPPCState *env)
3120{
3121#if !defined(CONFIG_USER_ONLY)
3122 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3123 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3124 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3125 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3126 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3127 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3128 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3129 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3130 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3131 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3132 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3133 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3134 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3135 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3136 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3137 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3138 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3139 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3140 /* Hardware reset vector */
3141 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3142#endif
3143}
3144
e1833e1f
JM		 3145static void init_excp_7450 (CPUPPCState *env)
3146{
3147#if !defined(CONFIG_USER_ONLY)
3148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3151 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3152 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3153 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3154 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3155 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3156 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3158 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3159 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3160 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3161 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3162 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3163 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3164 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3165 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3166 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3167 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3168 /* Hardware reset vector */
3169 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3170#endif
3171}
e1833e1f
JM		 3172
3173#if defined (TARGET_PPC64)
3174static void init_excp_970 (CPUPPCState *env)
3175{
3176#if !defined(CONFIG_USER_ONLY)
3177 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3178 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3179 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3180 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3181 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3182 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3183 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3184 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3185 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3186 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3187 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3188 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3191 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3192 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3193 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3194 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3195 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3196 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3197 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3198 /* Hardware reset vector */
3199 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3200#endif
3201}
9d52e907
DG		 3202
3203static void init_excp_POWER7 (CPUPPCState *env)
3204{
3205#if !defined(CONFIG_USER_ONLY)
3206 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3207 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3208 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3209 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3210 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3211 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3212 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3213 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3214 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3215 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3216 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3217 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3218 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3219 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3220 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3221 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3222 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3223 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3224 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3225 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3226 env->hreset_excp_prefix = 0;
3227 /* Hardware reset vector */
3228 env->hreset_vector = 0x0000000000000100ULL;
3229#endif
3230}
e1833e1f
JM		 3231#endif
3232
2f462816
JM		 3233/*****************************************************************************/
3234/* Power management enable checks */
3235static int check_pow_none (CPUPPCState *env)
3236{
3237 return 0;
3238}
3239
3240static int check_pow_nocheck (CPUPPCState *env)
3241{
3242 return 1;
3243}
3244
3245static int check_pow_hid0 (CPUPPCState *env)
3246{
3247 if (env->spr[SPR_HID0] & 0x00E00000)
3248 return 1;
3249
3250 return 0;
3251}
3252
4e777442
JM		 3253static int check_pow_hid0_74xx (CPUPPCState *env)
3254{
3255 if (env->spr[SPR_HID0] & 0x00600000)
3256 return 1;
3257
3258 return 0;
3259}
3260
a750fc0b
JM		 3261/*****************************************************************************/
3262/* PowerPC implementations definitions */
76a66253 3263
7856e3a4
AF		 3264#define POWERPC_FAMILY(_name) \
3265 static void \
3266 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3267 \
3268 static const TypeInfo \
3269 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3270 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3271 .parent = TYPE_POWERPC_CPU, \
3272 .abstract = true, \
3273 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3274 }; \
3275 \
3276 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3277 { \
3278 type_register_static( \
3279 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3280 } \
3281 \
3282 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3283 \
3284 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3285
a750fc0b
JM		 3286static void init_proc_401 (CPUPPCState *env)
3287{
3288 gen_spr_40x(env);
3289 gen_spr_401_403(env);
3290 gen_spr_401(env);
e1833e1f 3291 init_excp_4xx_real(env);
d63001d1
JM		 3292 env->dcache_line_size = 32;
3293 env->icache_line_size = 32;
4e290a0b
JM		 3294 /* Allocate hardware IRQ controller */
3295 ppc40x_irq_init(env);
ddd1055b
FC		 3296
3297 SET_FIT_PERIOD(12, 16, 20, 24);
3298 SET_WDT_PERIOD(16, 20, 24, 28);
a750fc0b 3299}
76a66253 3300
7856e3a4
AF		 3301POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3302{
ca5dff0a 3303 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3304 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3305
ca5dff0a 3306 dc->desc = "PowerPC 401";
7856e3a4
AF		 3307 pcc->init_proc = init_proc_401;
3308 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3309 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3310 PPC_WRTEE | PPC_DCR |
3311 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3312 PPC_CACHE_DCBZ |
3313 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3314 PPC_4xx_COMMON | PPC_40x_EXCP;
3315 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3316 pcc->msr_mask = 0x00000000000FD201ULL;
3317 pcc->mmu_model = POWERPC_MMU_REAL;
3318 pcc->excp_model = POWERPC_EXCP_40x;
3319 pcc->bus_model = PPC_FLAGS_INPUT_401;
3320 pcc->bfd_mach = bfd_mach_ppc_403;
3321 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3322 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3323}
3324
a750fc0b
JM		 3325static void init_proc_401x2 (CPUPPCState *env)
3326{
3327 gen_spr_40x(env);
3328 gen_spr_401_403(env);
3329 gen_spr_401x2(env);
3330 gen_spr_compress(env);
a750fc0b 3331 /* Memory management */
f2e63a42 3332#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3333 env->nb_tlb = 64;
3334 env->nb_ways = 1;
3335 env->id_tlbs = 0;
1c53accc 3336 env->tlb_type = TLB_EMB;
f2e63a42 3337#endif
e1833e1f 3338 init_excp_4xx_softmmu(env);
d63001d1
JM		 3339 env->dcache_line_size = 32;
3340 env->icache_line_size = 32;
4e290a0b
JM		 3341 /* Allocate hardware IRQ controller */
3342 ppc40x_irq_init(env);
ddd1055b
FC		 3343
3344 SET_FIT_PERIOD(12, 16, 20, 24);
3345 SET_WDT_PERIOD(16, 20, 24, 28);
76a66253
JM		 3346}
3347
7856e3a4
AF		 3348POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3349{
ca5dff0a 3350 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3351 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3352
ca5dff0a 3353 dc->desc = "PowerPC 401x2";
7856e3a4
AF		 3354 pcc->init_proc = init_proc_401x2;
3355 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3356 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3357 PPC_DCR | PPC_WRTEE |
3358 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3359 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3360 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3361 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3362 PPC_4xx_COMMON | PPC_40x_EXCP;
3363 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3364 pcc->msr_mask = 0x00000000001FD231ULL;
3365 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3366 pcc->excp_model = POWERPC_EXCP_40x;
3367 pcc->bus_model = PPC_FLAGS_INPUT_401;
3368 pcc->bfd_mach = bfd_mach_ppc_403;
3369 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3370 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3371}
3372
e1833e1f 3373static void init_proc_401x3 (CPUPPCState *env)
76a66253 3374{
4e290a0b
JM		 3375 gen_spr_40x(env);
3376 gen_spr_401_403(env);
3377 gen_spr_401(env);
3378 gen_spr_401x2(env);
3379 gen_spr_compress(env);
e1833e1f 3380 init_excp_4xx_softmmu(env);
d63001d1
JM		 3381 env->dcache_line_size = 32;
3382 env->icache_line_size = 32;
4e290a0b
JM		 3383 /* Allocate hardware IRQ controller */
3384 ppc40x_irq_init(env);
ddd1055b
FC		 3385
3386 SET_FIT_PERIOD(12, 16, 20, 24);
3387 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082 3388}
a750fc0b 3389
7856e3a4
AF		 3390POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3391{
ca5dff0a 3392 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3394
ca5dff0a 3395 dc->desc = "PowerPC 401x3";
7856e3a4
AF		 3396 pcc->init_proc = init_proc_401x3;
3397 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3399 PPC_DCR | PPC_WRTEE |
3400 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3401 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3402 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3403 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3404 PPC_4xx_COMMON | PPC_40x_EXCP;
3405 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3406 pcc->msr_mask = 0x00000000001FD631ULL;
3407 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3408 pcc->excp_model = POWERPC_EXCP_40x;
3409 pcc->bus_model = PPC_FLAGS_INPUT_401;
3410 pcc->bfd_mach = bfd_mach_ppc_403;
3411 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3412 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3413}
3414
a750fc0b 3415static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3416{
a750fc0b
JM		 3417 gen_spr_40x(env);
3418 gen_spr_401_403(env);
3419 gen_spr_401x2(env);
3420 gen_spr_compress(env);
a750fc0b 3421 /* Memory management */
f2e63a42 3422#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3423 env->nb_tlb = 64;
3424 env->nb_ways = 1;
3425 env->id_tlbs = 0;
1c53accc 3426 env->tlb_type = TLB_EMB;
f2e63a42 3427#endif
e1833e1f 3428 init_excp_4xx_softmmu(env);
d63001d1
JM		 3429 env->dcache_line_size = 32;
3430 env->icache_line_size = 32;
4e290a0b
JM		 3431 /* Allocate hardware IRQ controller */
3432 ppc40x_irq_init(env);
ddd1055b
FC		 3433
3434 SET_FIT_PERIOD(8, 12, 16, 20);
3435 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3436}
3437
7856e3a4
AF		 3438POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3439{
ca5dff0a 3440 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3442
ca5dff0a 3443 dc->desc = "IOP480";
7856e3a4
AF		 3444 pcc->init_proc = init_proc_IOP480;
3445 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3447 PPC_DCR | PPC_WRTEE |
3448 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3449 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3450 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3451 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3452 PPC_4xx_COMMON | PPC_40x_EXCP;
3453 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3454 pcc->msr_mask = 0x00000000001FD231ULL;
3455 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3456 pcc->excp_model = POWERPC_EXCP_40x;
3457 pcc->bus_model = PPC_FLAGS_INPUT_401;
3458 pcc->bfd_mach = bfd_mach_ppc_403;
3459 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3460 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3461}
3462
a750fc0b 3463static void init_proc_403 (CPUPPCState *env)
3fc6c082 3464{
a750fc0b
JM		 3465 gen_spr_40x(env);
3466 gen_spr_401_403(env);
3467 gen_spr_403(env);
3468 gen_spr_403_real(env);
e1833e1f 3469 init_excp_4xx_real(env);
d63001d1
JM		 3470 env->dcache_line_size = 32;
3471 env->icache_line_size = 32;
4e290a0b
JM		 3472 /* Allocate hardware IRQ controller */
3473 ppc40x_irq_init(env);
ddd1055b
FC		 3474
3475 SET_FIT_PERIOD(8, 12, 16, 20);
3476 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3477}
3478
7856e3a4
AF		 3479POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3480{
ca5dff0a 3481 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3482 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3483
ca5dff0a 3484 dc->desc = "PowerPC 403";
7856e3a4
AF		 3485 pcc->init_proc = init_proc_403;
3486 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3487 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3488 PPC_DCR | PPC_WRTEE |
3489 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3490 PPC_CACHE_DCBZ |
3491 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3492 PPC_4xx_COMMON | PPC_40x_EXCP;
3493 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3494 pcc->msr_mask = 0x000000000007D00DULL;
3495 pcc->mmu_model = POWERPC_MMU_REAL;
3496 pcc->excp_model = POWERPC_EXCP_40x;
3497 pcc->bus_model = PPC_FLAGS_INPUT_401;
3498 pcc->bfd_mach = bfd_mach_ppc_403;
3499 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3500 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3501}
3502
a750fc0b 3503static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3504{
a750fc0b
JM		 3505 gen_spr_40x(env);
3506 gen_spr_401_403(env);
3507 gen_spr_403(env);
3508 gen_spr_403_real(env);
3509 gen_spr_403_mmu(env);
3510 /* Bus access control */
5cbdb3a3 3511 /* not emulated, as QEMU never does speculative access */
a750fc0b
JM		 3512 spr_register(env, SPR_40x_SGR, "SGR",
3513 SPR_NOACCESS, SPR_NOACCESS,
3514 &spr_read_generic, &spr_write_generic,
3515 0xFFFFFFFF);
5cbdb3a3 3516 /* not emulated, as QEMU do not emulate caches */
a750fc0b
JM		 3517 spr_register(env, SPR_40x_DCWR, "DCWR",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_generic,
3520 0x00000000);
3521 /* Memory management */
f2e63a42 3522#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3523 env->nb_tlb = 64;
3524 env->nb_ways = 1;
3525 env->id_tlbs = 0;
1c53accc 3526 env->tlb_type = TLB_EMB;
f2e63a42 3527#endif
80d11f44
JM		 3528 init_excp_4xx_softmmu(env);
3529 env->dcache_line_size = 32;
3530 env->icache_line_size = 32;
3531 /* Allocate hardware IRQ controller */
3532 ppc40x_irq_init(env);
ddd1055b
FC		 3533
3534 SET_FIT_PERIOD(8, 12, 16, 20);
3535 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3536}
3537
7856e3a4
AF		 3538POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3539{
ca5dff0a 3540 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3542
ca5dff0a 3543 dc->desc = "PowerPC 403 GCX";
7856e3a4
AF		 3544 pcc->init_proc = init_proc_403GCX;
3545 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3546 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3547 PPC_DCR | PPC_WRTEE |
3548 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3549 PPC_CACHE_DCBZ |
3550 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3551 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3552 PPC_4xx_COMMON | PPC_40x_EXCP;
3553 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3554 pcc->msr_mask = 0x000000000007D00DULL;
3555 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3556 pcc->excp_model = POWERPC_EXCP_40x;
3557 pcc->bus_model = PPC_FLAGS_INPUT_401;
3558 pcc->bfd_mach = bfd_mach_ppc_403;
3559 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3560 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3561}
3562
80d11f44
JM		 3563static void init_proc_405 (CPUPPCState *env)
3564{
3565 /* Time base */
3566 gen_tbl(env);
3567 gen_spr_40x(env);
3568 gen_spr_405(env);
3569 /* Bus access control */
5cbdb3a3 3570 /* not emulated, as QEMU never does speculative access */
80d11f44
JM		 3571 spr_register(env, SPR_40x_SGR, "SGR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_generic,
3574 0xFFFFFFFF);
5cbdb3a3 3575 /* not emulated, as QEMU do not emulate caches */
80d11f44
JM		 3576 spr_register(env, SPR_40x_DCWR, "DCWR",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* Memory management */
3581#if !defined(CONFIG_USER_ONLY)
3582 env->nb_tlb = 64;
3583 env->nb_ways = 1;
3584 env->id_tlbs = 0;
1c53accc 3585 env->tlb_type = TLB_EMB;
80d11f44
JM		 3586#endif
3587 init_excp_4xx_softmmu(env);
3588 env->dcache_line_size = 32;
3589 env->icache_line_size = 32;
3590 /* Allocate hardware IRQ controller */
3591 ppc40x_irq_init(env);
ddd1055b
FC		 3592
3593 SET_FIT_PERIOD(8, 12, 16, 20);
3594 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3595}
3596
7856e3a4
AF		 3597POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3598{
ca5dff0a 3599 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3600 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3601
ca5dff0a 3602 dc->desc = "PowerPC 405";
7856e3a4
AF		 3603 pcc->init_proc = init_proc_405;
3604 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3605 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3606 PPC_DCR | PPC_WRTEE |
3607 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3608 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3609 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3610 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3611 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3612 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3613 pcc->msr_mask = 0x000000000006E630ULL;
3614 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3615 pcc->excp_model = POWERPC_EXCP_40x;
3616 pcc->bus_model = PPC_FLAGS_INPUT_405;
3617 pcc->bfd_mach = bfd_mach_ppc_403;
3618 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3619 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3620}
3621
80d11f44
JM		 3622static void init_proc_440EP (CPUPPCState *env)
3623{
3624 /* Time base */
3625 gen_tbl(env);
3626 gen_spr_BookE(env, 0x000000000000FFFFULL);
3627 gen_spr_440(env);
3628 gen_spr_usprgh(env);
3629 /* Processor identification */
3630 spr_register(env, SPR_BOOKE_PIR, "PIR",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_pir,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* XXX : not implemented */
3655 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3656 SPR_NOACCESS, SPR_NOACCESS,
3657 &spr_read_generic, &spr_write_generic,
3658 0x00000000);
3659 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_generic,
3666 0x00000000);
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_440_CCR1, "CCR1",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
3672 /* Memory management */
3673#if !defined(CONFIG_USER_ONLY)
3674 env->nb_tlb = 64;
3675 env->nb_ways = 1;
3676 env->id_tlbs = 0;
1c53accc 3677 env->tlb_type = TLB_EMB;
80d11f44
JM		 3678#endif
3679 init_excp_BookE(env);
3680 env->dcache_line_size = 32;
3681 env->icache_line_size = 32;
c0a7e81a 3682 ppc40x_irq_init(env);
ddd1055b
FC		 3683
3684 SET_FIT_PERIOD(12, 16, 20, 24);
3685 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3686}
3687
7856e3a4
AF		 3688POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3689{
ca5dff0a 3690 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3691 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3692
ca5dff0a 3693 dc->desc = "PowerPC 440 EP";
7856e3a4
AF		 3694 pcc->init_proc = init_proc_440EP;
3695 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3696 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3697 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3698 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3699 PPC_FLOAT_STFIWX |
3700 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3701 PPC_CACHE | PPC_CACHE_ICBI |
3702 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3703 PPC_MEM_TLBSYNC | PPC_MFTB |
3704 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3705 PPC_440_SPEC;
3706 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3707 pcc->msr_mask = 0x000000000006FF30ULL;
3708 pcc->mmu_model = POWERPC_MMU_BOOKE;
3709 pcc->excp_model = POWERPC_EXCP_BOOKE;
3710 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3711 pcc->bfd_mach = bfd_mach_ppc_403;
3712 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3713 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3714}
3715
80d11f44
JM		 3716static void init_proc_440GP (CPUPPCState *env)
3717{
3718 /* Time base */
3719 gen_tbl(env);
3720 gen_spr_BookE(env, 0x000000000000FFFFULL);
3721 gen_spr_440(env);
3722 gen_spr_usprgh(env);
3723 /* Processor identification */
3724 spr_register(env, SPR_BOOKE_PIR, "PIR",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_pir,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* XXX : not implemented */
3734 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
3743 /* XXX : not implemented */
3744 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 /* Memory management */
3749#if !defined(CONFIG_USER_ONLY)
3750 env->nb_tlb = 64;
3751 env->nb_ways = 1;
3752 env->id_tlbs = 0;
1c53accc 3753 env->tlb_type = TLB_EMB;
80d11f44
JM		 3754#endif
3755 init_excp_BookE(env);
3756 env->dcache_line_size = 32;
3757 env->icache_line_size = 32;
3758 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3759
3760 SET_FIT_PERIOD(12, 16, 20, 24);
3761 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3762}
3763
7856e3a4
AF		 3764POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3765{
ca5dff0a 3766 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3767 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3768
ca5dff0a 3769 dc->desc = "PowerPC 440 GP";
7856e3a4
AF		 3770 pcc->init_proc = init_proc_440GP;
3771 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3772 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3773 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3774 PPC_CACHE | PPC_CACHE_ICBI |
3775 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3776 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3777 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3778 PPC_440_SPEC;
3779 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3780 pcc->msr_mask = 0x000000000006FF30ULL;
3781 pcc->mmu_model = POWERPC_MMU_BOOKE;
3782 pcc->excp_model = POWERPC_EXCP_BOOKE;
3783 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3784 pcc->bfd_mach = bfd_mach_ppc_403;
3785 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3786 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3787}
3788
80d11f44
JM		 3789static void init_proc_440x4 (CPUPPCState *env)
3790{
3791 /* Time base */
3792 gen_tbl(env);
3793 gen_spr_BookE(env, 0x000000000000FFFFULL);
3794 gen_spr_440(env);
3795 gen_spr_usprgh(env);
3796 /* Processor identification */
3797 spr_register(env, SPR_BOOKE_PIR, "PIR",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_pir,
3800 0x00000000);
3801 /* XXX : not implemented */
3802 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 /* XXX : not implemented */
3807 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
3811 /* XXX : not implemented */
3812 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3813 SPR_NOACCESS, SPR_NOACCESS,
3814 &spr_read_generic, &spr_write_generic,
3815 0x00000000);
3816 /* XXX : not implemented */
3817 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3818 SPR_NOACCESS, SPR_NOACCESS,
3819 &spr_read_generic, &spr_write_generic,
3820 0x00000000);
3821 /* Memory management */
3822#if !defined(CONFIG_USER_ONLY)
3823 env->nb_tlb = 64;
3824 env->nb_ways = 1;
3825 env->id_tlbs = 0;
1c53accc 3826 env->tlb_type = TLB_EMB;
80d11f44
JM		 3827#endif
3828 init_excp_BookE(env);
d63001d1
JM		 3829 env->dcache_line_size = 32;
3830 env->icache_line_size = 32;
80d11f44 3831 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3832
3833 SET_FIT_PERIOD(12, 16, 20, 24);
3834 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3835}
3836
7856e3a4
AF		 3837POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3838{
ca5dff0a 3839 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3840 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3841
ca5dff0a 3842 dc->desc = "PowerPC 440x4";
7856e3a4
AF		 3843 pcc->init_proc = init_proc_440x4;
3844 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3845 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3846 PPC_DCR | PPC_WRTEE |
3847 PPC_CACHE | PPC_CACHE_ICBI |
3848 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3849 PPC_MEM_TLBSYNC | PPC_MFTB |
3850 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3851 PPC_440_SPEC;
3852 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3853 pcc->msr_mask = 0x000000000006FF30ULL;
3854 pcc->mmu_model = POWERPC_MMU_BOOKE;
3855 pcc->excp_model = POWERPC_EXCP_BOOKE;
3856 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3857 pcc->bfd_mach = bfd_mach_ppc_403;
3858 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3859 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3860}
3861
80d11f44 3862static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3863{
a750fc0b
JM		 3864 /* Time base */
3865 gen_tbl(env);
80d11f44
JM		 3866 gen_spr_BookE(env, 0x000000000000FFFFULL);
3867 gen_spr_440(env);
3868 gen_spr_usprgh(env);
3869 /* Processor identification */
3870 spr_register(env, SPR_BOOKE_PIR, "PIR",
3871 SPR_NOACCESS, SPR_NOACCESS,
3872 &spr_read_generic, &spr_write_pir,
3873 0x00000000);
3874 /* XXX : not implemented */
3875 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3878 0x00000000);
3879 /* XXX : not implemented */
3880 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3904 SPR_NOACCESS, SPR_NOACCESS,
3905 &spr_read_generic, &spr_write_generic,
3906 0x00000000);
3907 /* XXX : not implemented */
3908 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* Memory management */
f2e63a42 3913#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3914 env->nb_tlb = 64;
3915 env->nb_ways = 1;
3916 env->id_tlbs = 0;
1c53accc 3917 env->tlb_type = TLB_EMB;
f2e63a42 3918#endif
80d11f44 3919 init_excp_BookE(env);
d63001d1
JM		 3920 env->dcache_line_size = 32;
3921 env->icache_line_size = 32;
95070372 3922 ppc40x_irq_init(env);
ddd1055b
FC		 3923
3924 SET_FIT_PERIOD(12, 16, 20, 24);
3925 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3926}
3927
7856e3a4
AF		 3928POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3929{
ca5dff0a 3930 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3931 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3932
ca5dff0a 3933 dc->desc = "PowerPC 440x5";
7856e3a4
AF		 3934 pcc->init_proc = init_proc_440x5;
3935 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3936 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3937 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3938 PPC_CACHE | PPC_CACHE_ICBI |
3939 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3940 PPC_MEM_TLBSYNC | PPC_MFTB |
3941 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3942 PPC_440_SPEC;
3943 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 3944 pcc->msr_mask = 0x000000000006FF30ULL;
3945 pcc->mmu_model = POWERPC_MMU_BOOKE;
3946 pcc->excp_model = POWERPC_EXCP_BOOKE;
3947 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3948 pcc->bfd_mach = bfd_mach_ppc_403;
3949 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3950 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3951}
3952
80d11f44 3953static void init_proc_460 (CPUPPCState *env)
3fc6c082 3954{
a750fc0b
JM		 3955 /* Time base */
3956 gen_tbl(env);
80d11f44 3957 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3958 gen_spr_440(env);
80d11f44
JM		 3959 gen_spr_usprgh(env);
3960 /* Processor identification */
3961 spr_register(env, SPR_BOOKE_PIR, "PIR",
3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_pir,
3964 0x00000000);
3965 /* XXX : not implemented */
3966 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
3970 /* XXX : not implemented */
3971 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 /* XXX : not implemented */
3981 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
578bb252 3985 /* XXX : not implemented */
a750fc0b
JM		 3986 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
578bb252 3998 /* XXX : not implemented */
a750fc0b
JM		 3999 spr_register(env, SPR_440_CCR1, "CCR1",
4000 SPR_NOACCESS, SPR_NOACCESS,
4001 &spr_read_generic, &spr_write_generic,
4002 0x00000000);
80d11f44
JM		 4003 /* XXX : not implemented */
4004 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4005 &spr_read_generic, &spr_write_generic,
4006 &spr_read_generic, &spr_write_generic,
4007 0x00000000);
a750fc0b 4008 /* Memory management */
f2e63a42 4009#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4010 env->nb_tlb = 64;
4011 env->nb_ways = 1;
4012 env->id_tlbs = 0;
1c53accc 4013 env->tlb_type = TLB_EMB;
f2e63a42 4014#endif
e1833e1f 4015 init_excp_BookE(env);
d63001d1
JM		 4016 env->dcache_line_size = 32;
4017 env->icache_line_size = 32;
a750fc0b 4018 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4019
4020 SET_FIT_PERIOD(12, 16, 20, 24);
4021 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4022}
4023
7856e3a4
AF		 4024POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4025{
ca5dff0a 4026 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4028
ca5dff0a 4029 dc->desc = "PowerPC 460 (guessed)";
7856e3a4
AF		 4030 pcc->init_proc = init_proc_460;
4031 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4032 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4033 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4034 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4035 PPC_CACHE | PPC_CACHE_ICBI |
4036 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4037 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4038 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4039 PPC_440_SPEC;
4040 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4041 pcc->msr_mask = 0x000000000006FF30ULL;
4042 pcc->mmu_model = POWERPC_MMU_BOOKE;
4043 pcc->excp_model = POWERPC_EXCP_BOOKE;
4044 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4045 pcc->bfd_mach = bfd_mach_ppc_403;
4046 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4047 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4048}
4049
80d11f44 4050static void init_proc_460F (CPUPPCState *env)
3fc6c082 4051{
a750fc0b
JM		 4052 /* Time base */
4053 gen_tbl(env);
80d11f44 4054 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 4055 gen_spr_440(env);
80d11f44
JM		 4056 gen_spr_usprgh(env);
4057 /* Processor identification */
4058 spr_register(env, SPR_BOOKE_PIR, "PIR",
4059 SPR_NOACCESS, SPR_NOACCESS,
4060 &spr_read_generic, &spr_write_pir,
4061 0x00000000);
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 /* XXX : not implemented */
4083 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4084 SPR_NOACCESS, SPR_NOACCESS,
4085 &spr_read_generic, &spr_write_generic,
4086 0x00000000);
4087 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4088 SPR_NOACCESS, SPR_NOACCESS,
4089 &spr_read_generic, &spr_write_generic,
4090 0x00000000);
4091 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_440_CCR1, "CCR1",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4102 &spr_read_generic, &spr_write_generic,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
a750fc0b 4105 /* Memory management */
f2e63a42 4106#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4107 env->nb_tlb = 64;
4108 env->nb_ways = 1;
4109 env->id_tlbs = 0;
1c53accc 4110 env->tlb_type = TLB_EMB;
f2e63a42 4111#endif
e1833e1f 4112 init_excp_BookE(env);
d63001d1
JM		 4113 env->dcache_line_size = 32;
4114 env->icache_line_size = 32;
a750fc0b 4115 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4116
4117 SET_FIT_PERIOD(12, 16, 20, 24);
4118 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4119}
4120
7856e3a4
AF		 4121POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4122{
ca5dff0a 4123 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4125
ca5dff0a 4126 dc->desc = "PowerPC 460F (guessed)";
7856e3a4
AF		 4127 pcc->init_proc = init_proc_460F;
4128 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4129 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4130 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4131 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4132 PPC_FLOAT_STFIWX | PPC_MFTB |
4133 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4134 PPC_WRTEE | PPC_MFAPIDI |
4135 PPC_CACHE | PPC_CACHE_ICBI |
4136 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4137 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4138 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4139 PPC_440_SPEC;
4140 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4141 pcc->msr_mask = 0x000000000006FF30ULL;
4142 pcc->mmu_model = POWERPC_MMU_BOOKE;
4143 pcc->excp_model = POWERPC_EXCP_BOOKE;
4144 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4145 pcc->bfd_mach = bfd_mach_ppc_403;
4146 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4147 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4148}
4149
80d11f44
JM		 4150static void init_proc_MPC5xx (CPUPPCState *env)
4151{
4152 /* Time base */
4153 gen_tbl(env);
4154 gen_spr_5xx_8xx(env);
4155 gen_spr_5xx(env);
4156 init_excp_MPC5xx(env);
4157 env->dcache_line_size = 32;
4158 env->icache_line_size = 32;
4159 /* XXX: TODO: allocate internal IRQ controller */
4160}
4161
7856e3a4
AF		 4162POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4163{
ca5dff0a 4164 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4165 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4166
ca5dff0a 4167 dc->desc = "Freescale 5xx cores (aka RCPU)";
7856e3a4
AF		 4168 pcc->init_proc = init_proc_MPC5xx;
4169 pcc->check_pow = check_pow_none;
53116ebf
AF		 4170 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4171 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4172 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4173 PPC_MFTB;
4174 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4175 pcc->msr_mask = 0x000000000001FF43ULL;
4176 pcc->mmu_model = POWERPC_MMU_REAL;
4177 pcc->excp_model = POWERPC_EXCP_603;
4178 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4179 pcc->bfd_mach = bfd_mach_ppc_505;
4180 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4181 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4182}
4183
80d11f44
JM		 4184static void init_proc_MPC8xx (CPUPPCState *env)
4185{
4186 /* Time base */
4187 gen_tbl(env);
4188 gen_spr_5xx_8xx(env);
4189 gen_spr_8xx(env);
4190 init_excp_MPC8xx(env);
4191 env->dcache_line_size = 32;
4192 env->icache_line_size = 32;
4193 /* XXX: TODO: allocate internal IRQ controller */
4194}
4195
7856e3a4
AF		 4196POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4197{
ca5dff0a 4198 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4199 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4200
ca5dff0a 4201 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
7856e3a4
AF		 4202 pcc->init_proc = init_proc_MPC8xx;
4203 pcc->check_pow = check_pow_none;
53116ebf
AF		 4204 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4205 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4206 PPC_CACHE_ICBI | PPC_MFTB;
4207 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4208 pcc->msr_mask = 0x000000000001F673ULL;
4209 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4210 pcc->excp_model = POWERPC_EXCP_603;
4211 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4212 pcc->bfd_mach = bfd_mach_ppc_860;
4213 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4214 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4215}
4216
80d11f44 4217/* Freescale 82xx cores (aka PowerQUICC-II) */
ca5dff0a 4218
80d11f44 4219static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4220{
80d11f44
JM		 4221 gen_spr_ne_601(env);
4222 gen_spr_G2_755(env);
4223 gen_spr_G2(env);
a750fc0b
JM		 4224 /* Time base */
4225 gen_tbl(env);
bd928eba
JM		 4226 /* External access control */
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_EAR, "EAR",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
80d11f44
JM		 4232 /* Hardware implementation register */
4233 /* XXX : not implemented */
4234 spr_register(env, SPR_HID0, "HID0",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0x00000000);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_HID1, "HID1",
4240 SPR_NOACCESS, SPR_NOACCESS,
4241 &spr_read_generic, &spr_write_generic,
4242 0x00000000);
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_HID2, "HID2",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
a750fc0b 4248 /* Memory management */
80d11f44
JM		 4249 gen_low_BATs(env);
4250 gen_high_BATs(env);
4251 gen_6xx_7xx_soft_tlb(env, 64, 2);
4252 init_excp_G2(env);
d63001d1
JM		 4253 env->dcache_line_size = 32;
4254 env->icache_line_size = 32;
80d11f44
JM		 4255 /* Allocate hardware IRQ controller */
4256 ppc6xx_irq_init(env);
3fc6c082 4257}
a750fc0b 4258
7856e3a4
AF		 4259POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4260{
ca5dff0a 4261 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4262 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4263
ca5dff0a 4264 dc->desc = "PowerPC G2";
7856e3a4
AF		 4265 pcc->init_proc = init_proc_G2;
4266 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4267 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4268 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4269 PPC_FLOAT_STFIWX |
4270 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4271 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4272 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4273 PPC_SEGMENT | PPC_EXTERN;
4274 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4275 pcc->msr_mask = 0x000000000006FFF2ULL;
4276 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4277 pcc->excp_model = POWERPC_EXCP_G2;
4278 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4279 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4280 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4281 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4282}
4283
80d11f44 4284static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4285{
80d11f44
JM		 4286 gen_spr_ne_601(env);
4287 gen_spr_G2_755(env);
4288 gen_spr_G2(env);
a750fc0b
JM		 4289 /* Time base */
4290 gen_tbl(env);
bd928eba
JM		 4291 /* External access control */
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_EAR, "EAR",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
80d11f44 4297 /* Hardware implementation register */
578bb252 4298 /* XXX : not implemented */
80d11f44 4299 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4300 SPR_NOACCESS, SPR_NOACCESS,
4301 &spr_read_generic, &spr_write_generic,
4302 0x00000000);
80d11f44
JM		 4303 /* XXX : not implemented */
4304 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000);
578bb252 4308 /* XXX : not implemented */
80d11f44 4309 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4310 SPR_NOACCESS, SPR_NOACCESS,
4311 &spr_read_generic, &spr_write_generic,
4312 0x00000000);
4313 /* Memory management */
80d11f44
JM		 4314 gen_low_BATs(env);
4315 gen_high_BATs(env);
4316 gen_6xx_7xx_soft_tlb(env, 64, 2);
4317 init_excp_G2(env);
d63001d1
JM		 4318 env->dcache_line_size = 32;
4319 env->icache_line_size = 32;
80d11f44
JM		 4320 /* Allocate hardware IRQ controller */
4321 ppc6xx_irq_init(env);
3fc6c082
FB		 4322}
4323
7856e3a4
AF		 4324POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4325{
ca5dff0a 4326 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4328
ca5dff0a 4329 dc->desc = "PowerPC G2LE";
7856e3a4
AF		 4330 pcc->init_proc = init_proc_G2LE;
4331 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4332 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4333 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4334 PPC_FLOAT_STFIWX |
4335 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4336 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4337 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4338 PPC_SEGMENT | PPC_EXTERN;
4339 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4340 pcc->msr_mask = 0x000000000007FFF3ULL;
4341 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4342 pcc->excp_model = POWERPC_EXCP_G2;
4343 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4344 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4345 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4346 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4347}
4348
80d11f44 4349static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4350{
e1833e1f
JM		 4351 /* Time base */
4352 gen_tbl(env);
80d11f44 4353 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4354 /* XXX : not implemented */
80d11f44 4355 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4356 &spr_read_spefscr, &spr_write_spefscr,
4357 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4358 0x00000000);
80d11f44 4359 /* Memory management */
01662f3e 4360 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4361 /* XXX : not implemented */
4362 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4363 SPR_NOACCESS, SPR_NOACCESS,
4364 &spr_read_generic, &spr_write_generic,
4365 0x00000000);
80d11f44
JM		 4366 /* XXX : not implemented */
4367 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
578bb252 4371 /* XXX : not implemented */
80d11f44 4372 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
578bb252 4376 /* XXX : not implemented */
80d11f44
JM		 4377 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4378 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4379 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4380 0x00000000);
4381 /* XXX : not implemented */
4382 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4383 SPR_NOACCESS, SPR_NOACCESS,
4384 &spr_read_generic, &spr_write_generic,
4385 0x00000000);
4386 /* XXX : not implemented */
4387 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4388 SPR_NOACCESS, SPR_NOACCESS,
4389 &spr_read_generic, &spr_write_generic,
4390 0x00000000);
4391 /* XXX : not implemented */
4392 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4393 SPR_NOACCESS, SPR_NOACCESS,
4394 &spr_read_generic, &spr_write_generic,
4395 0x00000000);
4396 /* XXX : not implemented */
4397 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4398 SPR_NOACCESS, SPR_NOACCESS,
4399 &spr_read_generic, &spr_write_generic,
4400 0x00000000);
4401 /* XXX : not implemented */
4402 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4403 SPR_NOACCESS, SPR_NOACCESS,
4404 &spr_read_generic, &spr_write_generic,
4405 0x00000000);
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 0x00000000);
4411 /* XXX : not implemented */
4412 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* XXX : not implemented */
4417 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421 /* XXX : not implemented */
4422 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4423 SPR_NOACCESS, SPR_NOACCESS,
4424 &spr_read_generic, &spr_write_generic,
4425 0x00000000);
4426 /* XXX : not implemented */
4427 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4428 SPR_NOACCESS, SPR_NOACCESS,
4429 &spr_read_generic, &spr_write_generic,
4430 0x00000000);
01662f3e
AG		 4431 /* XXX : not implemented */
4432 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_generic,
4435 0x00000000); /* TOFIX */
80d11f44
JM		 4436 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4437 SPR_NOACCESS, SPR_NOACCESS,
4438 &spr_read_generic, &spr_write_generic,
4439 0x00000000);
4440 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4441 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4442 &spr_read_generic, &spr_write_generic,
4443 0x00000000);
f2e63a42 4444#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4445 env->nb_tlb = 64;
4446 env->nb_ways = 1;
4447 env->id_tlbs = 0;
1c53accc 4448 env->tlb_type = TLB_EMB;
f2e63a42 4449#endif
e9cd84b9 4450 init_excp_e200(env, 0xFFFF0000UL);
d63001d1
JM		 4451 env->dcache_line_size = 32;
4452 env->icache_line_size = 32;
e1833e1f 4453 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4454}
a750fc0b 4455
7856e3a4
AF		 4456POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4457{
ca5dff0a 4458 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4460
ca5dff0a 4461 dc->desc = "e200 core";
7856e3a4
AF		 4462 pcc->init_proc = init_proc_e200;
4463 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4464 /* XXX: unimplemented instructions:
4465 * dcblc
4466 * dcbtlst
4467 * dcbtstls
4468 * icblc
4469 * icbtls
4470 * tlbivax
4471 * all SPE multiply-accumulate instructions
4472 */
4473 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4474 PPC_SPE | PPC_SPE_SINGLE |
4475 PPC_WRTEE | PPC_RFDI |
4476 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4477 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4478 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4479 PPC_BOOKE;
4480 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4481 pcc->msr_mask = 0x000000000606FF30ULL;
4482 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4483 pcc->excp_model = POWERPC_EXCP_BOOKE;
4484 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4485 pcc->bfd_mach = bfd_mach_ppc_860;
4486 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4487 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4488 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4489}
4490
80d11f44 4491static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4492{
80d11f44
JM		 4493 gen_spr_ne_601(env);
4494 gen_spr_603(env);
a750fc0b
JM		 4495 /* Time base */
4496 gen_tbl(env);
80d11f44
JM		 4497 /* hardware implementation registers */
4498 /* XXX : not implemented */
4499 spr_register(env, SPR_HID0, "HID0",
4500 SPR_NOACCESS, SPR_NOACCESS,
4501 &spr_read_generic, &spr_write_generic,
4502 0x00000000);
4503 /* XXX : not implemented */
4504 spr_register(env, SPR_HID1, "HID1",
4505 SPR_NOACCESS, SPR_NOACCESS,
4506 &spr_read_generic, &spr_write_generic,
4507 0x00000000);
8daf1781
TM		 4508 /* XXX : not implemented */
4509 spr_register(env, SPR_HID2, "HID2",
4510 SPR_NOACCESS, SPR_NOACCESS,
4511 &spr_read_generic, &spr_write_generic,
4512 0x00000000);
80d11f44
JM		 4513 /* Memory management */
4514 gen_low_BATs(env);
8daf1781 4515 gen_high_BATs(env);
80d11f44
JM		 4516 gen_6xx_7xx_soft_tlb(env, 64, 2);
4517 init_excp_603(env);
4518 env->dcache_line_size = 32;
4519 env->icache_line_size = 32;
4520 /* Allocate hardware IRQ controller */
4521 ppc6xx_irq_init(env);
4522}
4523
7856e3a4
AF		 4524POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4525{
ca5dff0a 4526 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4527 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4528
ca5dff0a 4529 dc->desc = "e300 core";
7856e3a4
AF		 4530 pcc->init_proc = init_proc_e300;
4531 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4532 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4534 PPC_FLOAT_STFIWX |
4535 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4536 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4537 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4538 PPC_SEGMENT | PPC_EXTERN;
4539 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4540 pcc->msr_mask = 0x000000000007FFF3ULL;
4541 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4542 pcc->excp_model = POWERPC_EXCP_603;
4543 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4544 pcc->bfd_mach = bfd_mach_ppc_603;
4545 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4546 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4547}
4548
b81ccf8a
AG		 4549#if !defined(CONFIG_USER_ONLY)
4550static void spr_write_mas73(void *opaque, int sprn, int gprn)
4551{
4552 TCGv val = tcg_temp_new();
4553 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4554 gen_store_spr(SPR_BOOKE_MAS3, val);
cfee0218 4555 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
b81ccf8a
AG		 4556 gen_store_spr(SPR_BOOKE_MAS7, val);
4557 tcg_temp_free(val);
4558}
4559
4560static void spr_read_mas73(void *opaque, int gprn, int sprn)
4561{
4562 TCGv mas7 = tcg_temp_new();
4563 TCGv mas3 = tcg_temp_new();
4564 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4565 tcg_gen_shli_tl(mas7, mas7, 32);
4566 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4567 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4568 tcg_temp_free(mas3);
4569 tcg_temp_free(mas7);
4570}
4571
b81ccf8a
AG		 4572#endif
4573
f7aa5583
VS		 4574enum fsl_e500_version {
4575 fsl_e500v1,
4576 fsl_e500v2,
4577 fsl_e500mc,
b81ccf8a 4578 fsl_e5500,
f7aa5583
VS		 4579};
4580
01662f3e 4581static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4582{
01662f3e 4583 uint32_t tlbncfg[2];
b81ccf8a 4584 uint64_t ivor_mask;
e9cd84b9 4585 uint64_t ivpr_mask = 0xFFFF0000ULL;
a496e8ee
AG		 4586 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4587 | 0x0020; /* 32 kb */
01662f3e
AG		 4588#if !defined(CONFIG_USER_ONLY)
4589 int i;
4590#endif
4591
80d11f44
JM		 4592 /* Time base */
4593 gen_tbl(env);
01662f3e
AG		 4594 /*
4595 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4596 * complain when accessing them.
4597 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4598 */
b81ccf8a
AG		 4599 switch (version) {
4600 case fsl_e500v1:
4601 case fsl_e500v2:
4602 default:
4603 ivor_mask = 0x0000000F0000FFFFULL;
4604 break;
4605 case fsl_e500mc:
4606 case fsl_e5500:
4607 ivor_mask = 0x000003FE0000FFFFULL;
4608 break;
2c9732db
AG		 4609 }
4610 gen_spr_BookE(env, ivor_mask);
80d11f44
JM		 4611 /* Processor identification */
4612 spr_register(env, SPR_BOOKE_PIR, "PIR",
4613 SPR_NOACCESS, SPR_NOACCESS,
4614 &spr_read_generic, &spr_write_pir,
4615 0x00000000);
4616 /* XXX : not implemented */
4617 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4618 &spr_read_spefscr, &spr_write_spefscr,
4619 &spr_read_spefscr, &spr_write_spefscr,
80d11f44 4620 0x00000000);
892c587f 4621#if !defined(CONFIG_USER_ONLY)
80d11f44 4622 /* Memory management */
80d11f44 4623 env->nb_pids = 3;
01662f3e
AG		 4624 env->nb_ways = 2;
4625 env->id_tlbs = 0;
4626 switch (version) {
f7aa5583 4627 case fsl_e500v1:
01662f3e
AG		 4628 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4629 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4630 break;
f7aa5583 4631 case fsl_e500v2:
01662f3e
AG		 4632 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4633 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4634 break;
4635 case fsl_e500mc:
b81ccf8a 4636 case fsl_e5500:
f7aa5583
VS		 4637 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4638 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
892c587f
AG		 4639 break;
4640 default:
4641 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4642 }
4643#endif
4644 /* Cache sizes */
4645 switch (version) {
4646 case fsl_e500v1:
4647 case fsl_e500v2:
4648 env->dcache_line_size = 32;
4649 env->icache_line_size = 32;
4650 break;
4651 case fsl_e500mc:
b81ccf8a 4652 case fsl_e5500:
f7aa5583
VS		 4653 env->dcache_line_size = 64;
4654 env->icache_line_size = 64;
a496e8ee 4655 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
01662f3e
AG		 4656 break;
4657 default:
4658 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4659 }
01662f3e 4660 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4661 /* XXX : not implemented */
4662 spr_register(env, SPR_HID0, "HID0",
4663 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_generic, &spr_write_generic,
4665 0x00000000);
4666 /* XXX : not implemented */
4667 spr_register(env, SPR_HID1, "HID1",
4668 SPR_NOACCESS, SPR_NOACCESS,
4669 &spr_read_generic, &spr_write_generic,
4670 0x00000000);
4671 /* XXX : not implemented */
4672 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4673 SPR_NOACCESS, SPR_NOACCESS,
4674 &spr_read_generic, &spr_write_generic,
4675 0x00000000);
4676 /* XXX : not implemented */
4677 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4678 SPR_NOACCESS, SPR_NOACCESS,
4679 &spr_read_generic, &spr_write_generic,
4680 0x00000000);
4681 /* XXX : not implemented */
4682 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4683 SPR_NOACCESS, SPR_NOACCESS,
4684 &spr_read_generic, &spr_write_generic,
4685 0x00000000);
578bb252 4686 /* XXX : not implemented */
a750fc0b
JM		 4687 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4688 SPR_NOACCESS, SPR_NOACCESS,
4689 &spr_read_generic, &spr_write_generic,
4690 0x00000000);
80d11f44
JM		 4691 /* XXX : not implemented */
4692 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4693 SPR_NOACCESS, SPR_NOACCESS,
4694 &spr_read_generic, &spr_write_generic,
4695 0x00000000);
80d11f44
JM		 4696 /* XXX : not implemented */
4697 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4698 SPR_NOACCESS, SPR_NOACCESS,
4699 &spr_read_generic, &spr_write_generic,
4700 0x00000000);
578bb252 4701 /* XXX : not implemented */
80d11f44 4702 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4703 SPR_NOACCESS, SPR_NOACCESS,
4704 &spr_read_generic, &spr_write_generic,
a496e8ee 4705 l1cfg0);
578bb252 4706 /* XXX : not implemented */
80d11f44
JM		 4707 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4708 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4709 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4710 0x00000000);
4711 /* XXX : not implemented */
4712 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4713 SPR_NOACCESS, SPR_NOACCESS,
4714 &spr_read_generic, &spr_write_generic,
4715 0x00000000);
80d11f44
JM		 4716 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4717 SPR_NOACCESS, SPR_NOACCESS,
4718 &spr_read_generic, &spr_write_generic,
4719 0x00000000);
4720 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4721 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4722 &spr_read_generic, &spr_write_generic,
4723 0x00000000);
01662f3e
AG		 4724 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_booke206_mmucsr0,
4727 0x00000000);
b81ccf8a
AG		 4728 spr_register(env, SPR_BOOKE_EPR, "EPR",
4729 SPR_NOACCESS, SPR_NOACCESS,
68c2dd70 4730 &spr_read_generic, SPR_NOACCESS,
b81ccf8a
AG		 4731 0x00000000);
4732 /* XXX better abstract into Emb.xxx features */
4733 if (version == fsl_e5500) {
4734 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4735 SPR_NOACCESS, SPR_NOACCESS,
4736 &spr_read_generic, &spr_write_generic,
4737 0x00000000);
4738 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4739 SPR_NOACCESS, SPR_NOACCESS,
4740 &spr_read_mas73, &spr_write_mas73,
4741 0x00000000);
4742 ivpr_mask = (target_ulong)~0xFFFFULL;
4743 }
01662f3e 4744
f2e63a42 4745#if !defined(CONFIG_USER_ONLY)
01662f3e 4746 env->nb_tlb = 0;
1c53accc 4747 env->tlb_type = TLB_MAS;
01662f3e
AG		 4748 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4749 env->nb_tlb += booke206_tlb_size(env, i);
4750 }
f2e63a42 4751#endif
01662f3e 4752
e9cd84b9 4753 init_excp_e200(env, ivpr_mask);
9fdc60bf
AJ		 4754 /* Allocate hardware IRQ controller */
4755 ppce500_irq_init(env);
3fc6c082 4756}
a750fc0b 4757
01662f3e
AG		 4758static void init_proc_e500v1(CPUPPCState *env)
4759{
f7aa5583 4760 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 4761}
4762
7856e3a4
AF		 4763POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4764{
ca5dff0a 4765 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4767
ca5dff0a 4768 dc->desc = "e500v1 core";
7856e3a4
AF		 4769 pcc->init_proc = init_proc_e500v1;
4770 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4771 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4772 PPC_SPE | PPC_SPE_SINGLE |
4773 PPC_WRTEE | PPC_RFDI |
4774 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4775 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4776 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4777 pcc->insns_flags2 = PPC2_BOOKE206;
ba9fd9f1
AF		 4778 pcc->msr_mask = 0x000000000606FF30ULL;
4779 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4780 pcc->excp_model = POWERPC_EXCP_BOOKE;
4781 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4782 pcc->bfd_mach = bfd_mach_ppc_860;
4783 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4784 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4785 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4786}
4787
01662f3e
AG		 4788static void init_proc_e500v2(CPUPPCState *env)
4789{
f7aa5583
VS		 4790 init_proc_e500(env, fsl_e500v2);
4791}
4792
7856e3a4
AF		 4793POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4794{
ca5dff0a 4795 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4796 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4797
ca5dff0a 4798 dc->desc = "e500v2 core";
7856e3a4
AF		 4799 pcc->init_proc = init_proc_e500v2;
4800 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4801 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4802 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4803 PPC_WRTEE | PPC_RFDI |
4804 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4805 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4806 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4807 pcc->insns_flags2 = PPC2_BOOKE206;
ba9fd9f1
AF		 4808 pcc->msr_mask = 0x000000000606FF30ULL;
4809 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4810 pcc->excp_model = POWERPC_EXCP_BOOKE;
4811 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4812 pcc->bfd_mach = bfd_mach_ppc_860;
4813 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4814 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4815 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4816}
4817
f7aa5583
VS		 4818static void init_proc_e500mc(CPUPPCState *env)
4819{
4820 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 4821}
4822
7856e3a4
AF		 4823POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4824{
ca5dff0a 4825 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4826 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4827
ca5dff0a 4828 dc->desc = "e500mc core";
7856e3a4
AF		 4829 pcc->init_proc = init_proc_e500mc;
4830 pcc->check_pow = check_pow_none;
53116ebf
AF		 4831 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4832 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4833 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4834 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4835 PPC_FLOAT | PPC_FLOAT_FRES |
4836 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4837 PPC_FLOAT_STFIWX | PPC_WAIT |
4838 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4839 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
ba9fd9f1
AF		 4840 pcc->msr_mask = 0x000000001402FB36ULL;
4841 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4842 pcc->excp_model = POWERPC_EXCP_BOOKE;
4843 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4844 /* FIXME: figure out the correct flag for e500mc */
4845 pcc->bfd_mach = bfd_mach_ppc_e500;
4846 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4847 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4848}
4849
b81ccf8a
AG		 4850#ifdef TARGET_PPC64
4851static void init_proc_e5500(CPUPPCState *env)
4852{
4853 init_proc_e500(env, fsl_e5500);
4854}
7856e3a4
AF		 4855
4856POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4857{
ca5dff0a 4858 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4859 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4860
ca5dff0a 4861 dc->desc = "e5500 core";
7856e3a4
AF		 4862 pcc->init_proc = init_proc_e5500;
4863 pcc->check_pow = check_pow_none;
53116ebf
AF		 4864 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4865 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4866 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4867 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4868 PPC_FLOAT | PPC_FLOAT_FRES |
4869 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4870 PPC_FLOAT_STFIWX | PPC_WAIT |
4871 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4872 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4873 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
ba9fd9f1
AF		 4874 pcc->msr_mask = 0x000000009402FB36ULL;
4875 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4876 pcc->excp_model = POWERPC_EXCP_BOOKE;
4877 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4878 /* FIXME: figure out the correct flag for e5500 */
4879 pcc->bfd_mach = bfd_mach_ppc_e500;
4880 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4881 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4 4882}
b81ccf8a
AG		 4883#endif
4884
a750fc0b 4885/* Non-embedded PowerPC */
a750fc0b
JM		 4886
4887/* POWER : same as 601, without mfmsr, mfsr */
53116ebf
AF		 4888POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4889{
ca5dff0a 4890 DeviceClass *dc = DEVICE_CLASS(oc);
53116ebf
AF		 4891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4892
ca5dff0a 4893 dc->desc = "POWER";
953af181 4894 /* pcc->insns_flags = XXX_TODO; */
ba9fd9f1
AF		 4895 /* POWER RSC (from RAD6000) */
4896 pcc->msr_mask = 0x00000000FEF0ULL;
53116ebf 4897}
a750fc0b 4898
082c6681 4899#define POWERPC_MSRR_601 (0x0000000000001040ULL)
a750fc0b
JM		 4900
4901static void init_proc_601 (CPUPPCState *env)
3fc6c082 4902{
a750fc0b
JM		 4903 gen_spr_ne_601(env);
4904 gen_spr_601(env);
4905 /* Hardware implementation registers */
4906 /* XXX : not implemented */
4907 spr_register(env, SPR_HID0, "HID0",
4908 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4909 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4910 0x80010080);
a750fc0b
JM		 4911 /* XXX : not implemented */
4912 spr_register(env, SPR_HID1, "HID1",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* XXX : not implemented */
4917 spr_register(env, SPR_601_HID2, "HID2",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_601_HID5, "HID5",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
a750fc0b 4926 /* Memory management */
e1833e1f 4927 init_excp_601(env);
082c6681
JM		 4928 /* XXX: beware that dcache line size is 64
4929 * but dcbz uses 32 bytes "sectors"
4930 * XXX: this breaks clcs instruction !
4931 */
4932 env->dcache_line_size = 32;
d63001d1 4933 env->icache_line_size = 64;
faadf50e
JM		 4934 /* Allocate hardware IRQ controller */
4935 ppc6xx_irq_init(env);
3fc6c082
FB		 4936}
4937
7856e3a4
AF		 4938POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4939{
ca5dff0a 4940 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4941 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4942
ca5dff0a 4943 dc->desc = "PowerPC 601";
7856e3a4
AF		 4944 pcc->init_proc = init_proc_601;
4945 pcc->check_pow = check_pow_none;
53116ebf
AF		 4946 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4947 PPC_FLOAT |
4948 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4949 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4950 PPC_SEGMENT | PPC_EXTERN;
4951 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4952 pcc->msr_mask = 0x000000000000FD70ULL;
4953 pcc->mmu_model = POWERPC_MMU_601;
4954 pcc->excp_model = POWERPC_EXCP_601;
4955 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4956 pcc->bfd_mach = bfd_mach_ppc_601;
4957 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
7856e3a4
AF		 4958}
4959
082c6681 4960#define POWERPC_MSRR_601v (0x0000000000001040ULL)
082c6681
JM		 4961
4962static void init_proc_601v (CPUPPCState *env)
4963{
4964 init_proc_601(env);
4965 /* XXX : not implemented */
4966 spr_register(env, SPR_601_HID15, "HID15",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970}
4971
7856e3a4
AF		 4972POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4973{
ca5dff0a 4974 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4975 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4976
ca5dff0a 4977 dc->desc = "PowerPC 601v";
7856e3a4
AF		 4978 pcc->init_proc = init_proc_601v;
4979 pcc->check_pow = check_pow_none;
53116ebf
AF		 4980 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4981 PPC_FLOAT |
4982 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4983 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4984 PPC_SEGMENT | PPC_EXTERN;
4985 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 4986 pcc->msr_mask = 0x000000000000FD70ULL;
4987 pcc->mmu_model = POWERPC_MMU_601;
4988 pcc->excp_model = POWERPC_EXCP_601;
4989 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4990 pcc->bfd_mach = bfd_mach_ppc_601;
4991 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
7856e3a4
AF		 4992}
4993
a750fc0b 4994static void init_proc_602 (CPUPPCState *env)
3fc6c082 4995{
a750fc0b
JM		 4996 gen_spr_ne_601(env);
4997 gen_spr_602(env);
4998 /* Time base */
4999 gen_tbl(env);
5000 /* hardware implementation registers */
5001 /* XXX : not implemented */
5002 spr_register(env, SPR_HID0, "HID0",
5003 SPR_NOACCESS, SPR_NOACCESS,
5004 &spr_read_generic, &spr_write_generic,
5005 0x00000000);
5006 /* XXX : not implemented */
5007 spr_register(env, SPR_HID1, "HID1",
5008 SPR_NOACCESS, SPR_NOACCESS,
5009 &spr_read_generic, &spr_write_generic,
5010 0x00000000);
5011 /* Memory management */
5012 gen_low_BATs(env);
5013 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5014 init_excp_602(env);
d63001d1
JM		 5015 env->dcache_line_size = 32;
5016 env->icache_line_size = 32;
a750fc0b
JM		 5017 /* Allocate hardware IRQ controller */
5018 ppc6xx_irq_init(env);
5019}
3fc6c082 5020
7856e3a4
AF		 5021POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5022{
ca5dff0a 5023 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5024 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5025
ca5dff0a 5026 dc->desc = "PowerPC 602";
7856e3a4
AF		 5027 pcc->init_proc = init_proc_602;
5028 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5029 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5030 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5031 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5032 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5033 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5034 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5035 PPC_SEGMENT | PPC_602_SPEC;
5036 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5037 pcc->msr_mask = 0x0000000000C7FF73ULL;
5038 /* XXX: 602 MMU is quite specific. Should add a special case */
5039 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5040 pcc->excp_model = POWERPC_EXCP_602;
5041 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5042 pcc->bfd_mach = bfd_mach_ppc_602;
5043 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5044 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5045}
5046
a750fc0b
JM		 5047static void init_proc_603 (CPUPPCState *env)
5048{
5049 gen_spr_ne_601(env);
5050 gen_spr_603(env);
5051 /* Time base */
5052 gen_tbl(env);
5053 /* hardware implementation registers */
5054 /* XXX : not implemented */
5055 spr_register(env, SPR_HID0, "HID0",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0x00000000);
5059 /* XXX : not implemented */
5060 spr_register(env, SPR_HID1, "HID1",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_generic, &spr_write_generic,
5063 0x00000000);
5064 /* Memory management */
5065 gen_low_BATs(env);
5066 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5067 init_excp_603(env);
d63001d1
JM		 5068 env->dcache_line_size = 32;
5069 env->icache_line_size = 32;
a750fc0b
JM		 5070 /* Allocate hardware IRQ controller */
5071 ppc6xx_irq_init(env);
3fc6c082
FB		 5072}
5073
7856e3a4
AF		 5074POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5075{
ca5dff0a 5076 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5078
ca5dff0a 5079 dc->desc = "PowerPC 603";
7856e3a4
AF		 5080 pcc->init_proc = init_proc_603;
5081 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5084 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5086 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5088 PPC_SEGMENT | PPC_EXTERN;
5089 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5090 pcc->msr_mask = 0x000000000007FF73ULL;
5091 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5092 pcc->excp_model = POWERPC_EXCP_603;
5093 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5094 pcc->bfd_mach = bfd_mach_ppc_603;
5095 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5096 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5097}
5098
a750fc0b
JM		 5099static void init_proc_603E (CPUPPCState *env)
5100{
5101 gen_spr_ne_601(env);
5102 gen_spr_603(env);
5103 /* Time base */
5104 gen_tbl(env);
5105 /* hardware implementation registers */
5106 /* XXX : not implemented */
5107 spr_register(env, SPR_HID0, "HID0",
5108 SPR_NOACCESS, SPR_NOACCESS,
5109 &spr_read_generic, &spr_write_generic,
5110 0x00000000);
5111 /* XXX : not implemented */
5112 spr_register(env, SPR_HID1, "HID1",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
5115 0x00000000);
5116 /* XXX : not implemented */
5117 spr_register(env, SPR_IABR, "IABR",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 0x00000000);
5121 /* Memory management */
5122 gen_low_BATs(env);
5123 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5124 init_excp_603(env);
d63001d1
JM		 5125 env->dcache_line_size = 32;
5126 env->icache_line_size = 32;
a750fc0b
JM		 5127 /* Allocate hardware IRQ controller */
5128 ppc6xx_irq_init(env);
5129}
5130
7856e3a4
AF		 5131POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5132{
ca5dff0a 5133 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5134 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5135
ca5dff0a 5136 dc->desc = "PowerPC 603e";
7856e3a4
AF		 5137 pcc->init_proc = init_proc_603E;
5138 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5139 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5140 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5141 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5142 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5143 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5144 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5145 PPC_SEGMENT | PPC_EXTERN;
5146 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5147 pcc->msr_mask = 0x000000000007FF73ULL;
5148 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5149 pcc->excp_model = POWERPC_EXCP_603E;
5150 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5151 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5152 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5153 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5154}
5155
a750fc0b
JM		 5156static void init_proc_604 (CPUPPCState *env)
5157{
5158 gen_spr_ne_601(env);
5159 gen_spr_604(env);
5160 /* Time base */
5161 gen_tbl(env);
5162 /* Hardware implementation registers */
5163 /* XXX : not implemented */
082c6681
JM		 5164 spr_register(env, SPR_HID0, "HID0",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_generic,
5167 0x00000000);
5168 /* Memory management */
5169 gen_low_BATs(env);
5170 init_excp_604(env);
5171 env->dcache_line_size = 32;
5172 env->icache_line_size = 32;
5173 /* Allocate hardware IRQ controller */
5174 ppc6xx_irq_init(env);
5175}
5176
7856e3a4
AF		 5177POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5178{
ca5dff0a 5179 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5180 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5181
ca5dff0a 5182 dc->desc = "PowerPC 604";
7856e3a4
AF		 5183 pcc->init_proc = init_proc_604;
5184 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5185 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5186 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5187 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5188 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5189 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5190 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5191 PPC_SEGMENT | PPC_EXTERN;
5192 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5193 pcc->msr_mask = 0x000000000005FF77ULL;
5194 pcc->mmu_model = POWERPC_MMU_32B;
5195 pcc->excp_model = POWERPC_EXCP_604;
5196 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5197 pcc->bfd_mach = bfd_mach_ppc_604;
5198 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5199 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5200}
5201
082c6681
JM		 5202static void init_proc_604E (CPUPPCState *env)
5203{
5204 gen_spr_ne_601(env);
5205 gen_spr_604(env);
5206 /* XXX : not implemented */
5207 spr_register(env, SPR_MMCR1, "MMCR1",
5208 SPR_NOACCESS, SPR_NOACCESS,
5209 &spr_read_generic, &spr_write_generic,
5210 0x00000000);
5211 /* XXX : not implemented */
5212 spr_register(env, SPR_PMC3, "PMC3",
5213 SPR_NOACCESS, SPR_NOACCESS,
5214 &spr_read_generic, &spr_write_generic,
5215 0x00000000);
5216 /* XXX : not implemented */
5217 spr_register(env, SPR_PMC4, "PMC4",
5218 SPR_NOACCESS, SPR_NOACCESS,
5219 &spr_read_generic, &spr_write_generic,
5220 0x00000000);
5221 /* Time base */
5222 gen_tbl(env);
5223 /* Hardware implementation registers */
5224 /* XXX : not implemented */
a750fc0b
JM		 5225 spr_register(env, SPR_HID0, "HID0",
5226 SPR_NOACCESS, SPR_NOACCESS,
5227 &spr_read_generic, &spr_write_generic,
5228 0x00000000);
5229 /* XXX : not implemented */
5230 spr_register(env, SPR_HID1, "HID1",
5231 SPR_NOACCESS, SPR_NOACCESS,
5232 &spr_read_generic, &spr_write_generic,
5233 0x00000000);
5234 /* Memory management */
5235 gen_low_BATs(env);
e1833e1f 5236 init_excp_604(env);
d63001d1
JM		 5237 env->dcache_line_size = 32;
5238 env->icache_line_size = 32;
a750fc0b
JM		 5239 /* Allocate hardware IRQ controller */
5240 ppc6xx_irq_init(env);
5241}
5242
7856e3a4
AF		 5243POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5244{
ca5dff0a 5245 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5247
ca5dff0a 5248 dc->desc = "PowerPC 604E";
7856e3a4
AF		 5249 pcc->init_proc = init_proc_604E;
5250 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5251 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5252 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5253 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5254 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5255 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5256 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5257 PPC_SEGMENT | PPC_EXTERN;
5258 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5259 pcc->msr_mask = 0x000000000005FF77ULL;
5260 pcc->mmu_model = POWERPC_MMU_32B;
5261 pcc->excp_model = POWERPC_EXCP_604;
5262 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5263 pcc->bfd_mach = bfd_mach_ppc_604;
5264 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5265 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5266}
5267
bd928eba 5268static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 5269{
5270 gen_spr_ne_601(env);
5271 gen_spr_7xx(env);
5272 /* Time base */
5273 gen_tbl(env);
5274 /* Thermal management */
5275 gen_spr_thrm(env);
5276 /* Hardware implementation registers */
5277 /* XXX : not implemented */
5278 spr_register(env, SPR_HID0, "HID0",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 /* XXX : not implemented */
5283 spr_register(env, SPR_HID1, "HID1",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* Memory management */
5288 gen_low_BATs(env);
e1833e1f 5289 init_excp_7x0(env);
d63001d1
JM		 5290 env->dcache_line_size = 32;
5291 env->icache_line_size = 32;
a750fc0b
JM		 5292 /* Allocate hardware IRQ controller */
5293 ppc6xx_irq_init(env);
5294}
5295
7856e3a4
AF		 5296POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5297{
ca5dff0a 5298 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5299 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5300
ca5dff0a 5301 dc->desc = "PowerPC 740";
7856e3a4
AF		 5302 pcc->init_proc = init_proc_740;
5303 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5304 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5305 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5306 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5307 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5308 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5309 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5310 PPC_SEGMENT | PPC_EXTERN;
5311 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5312 pcc->msr_mask = 0x000000000005FF77ULL;
5313 pcc->mmu_model = POWERPC_MMU_32B;
5314 pcc->excp_model = POWERPC_EXCP_7x0;
5315 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5316 pcc->bfd_mach = bfd_mach_ppc_750;
5317 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5318 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5319}
5320
bd928eba
JM		 5321static void init_proc_750 (CPUPPCState *env)
5322{
5323 gen_spr_ne_601(env);
5324 gen_spr_7xx(env);
5325 /* XXX : not implemented */
5326 spr_register(env, SPR_L2CR, "L2CR",
5327 SPR_NOACCESS, SPR_NOACCESS,
5328 &spr_read_generic, &spr_write_generic,
5329 0x00000000);
5330 /* Time base */
5331 gen_tbl(env);
5332 /* Thermal management */
5333 gen_spr_thrm(env);
5334 /* Hardware implementation registers */
5335 /* XXX : not implemented */
5336 spr_register(env, SPR_HID0, "HID0",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 /* XXX : not implemented */
5341 spr_register(env, SPR_HID1, "HID1",
5342 SPR_NOACCESS, SPR_NOACCESS,
5343 &spr_read_generic, &spr_write_generic,
5344 0x00000000);
5345 /* Memory management */
5346 gen_low_BATs(env);
5347 /* XXX: high BATs are also present but are known to be bugged on
5348 * die version 1.x
5349 */
5350 init_excp_7x0(env);
5351 env->dcache_line_size = 32;
5352 env->icache_line_size = 32;
5353 /* Allocate hardware IRQ controller */
5354 ppc6xx_irq_init(env);
5355}
5356
7856e3a4
AF		 5357POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5358{
ca5dff0a 5359 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5361
ca5dff0a 5362 dc->desc = "PowerPC 750";
7856e3a4
AF		 5363 pcc->init_proc = init_proc_750;
5364 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5365 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5366 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5367 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5368 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5369 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5370 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5371 PPC_SEGMENT | PPC_EXTERN;
5372 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5373 pcc->msr_mask = 0x000000000005FF77ULL;
5374 pcc->mmu_model = POWERPC_MMU_32B;
5375 pcc->excp_model = POWERPC_EXCP_7x0;
5376 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5377 pcc->bfd_mach = bfd_mach_ppc_750;
5378 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5379 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5380}
5381
bd928eba
JM		 5382static void init_proc_750cl (CPUPPCState *env)
5383{
5384 gen_spr_ne_601(env);
5385 gen_spr_7xx(env);
5386 /* XXX : not implemented */
5387 spr_register(env, SPR_L2CR, "L2CR",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 /* Time base */
5392 gen_tbl(env);
5393 /* Thermal management */
5394 /* Those registers are fake on 750CL */
5395 spr_register(env, SPR_THRM1, "THRM1",
5396 SPR_NOACCESS, SPR_NOACCESS,
5397 &spr_read_generic, &spr_write_generic,
5398 0x00000000);
5399 spr_register(env, SPR_THRM2, "THRM2",
5400 SPR_NOACCESS, SPR_NOACCESS,
5401 &spr_read_generic, &spr_write_generic,
5402 0x00000000);
5403 spr_register(env, SPR_THRM3, "THRM3",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 /* XXX: not implemented */
5408 spr_register(env, SPR_750_TDCL, "TDCL",
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 &spr_read_generic, &spr_write_generic,
5411 0x00000000);
5412 spr_register(env, SPR_750_TDCH, "TDCH",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416 /* DMA */
5417 /* XXX : not implemented */
5418 spr_register(env, SPR_750_WPAR, "WPAR",
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 &spr_read_generic, &spr_write_generic,
5421 0x00000000);
5422 spr_register(env, SPR_750_DMAL, "DMAL",
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 &spr_read_generic, &spr_write_generic,
5425 0x00000000);
5426 spr_register(env, SPR_750_DMAU, "DMAU",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 /* Hardware implementation registers */
5431 /* XXX : not implemented */
5432 spr_register(env, SPR_HID0, "HID0",
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 &spr_read_generic, &spr_write_generic,
5435 0x00000000);
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_HID1, "HID1",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* XXX : not implemented */
5442 spr_register(env, SPR_750CL_HID2, "HID2",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_750CL_HID4, "HID4",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* Quantization registers */
5452 /* XXX : not implemented */
5453 spr_register(env, SPR_750_GQR0, "GQR0",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 /* XXX : not implemented */
5458 spr_register(env, SPR_750_GQR1, "GQR1",
5459 SPR_NOACCESS, SPR_NOACCESS,
5460 &spr_read_generic, &spr_write_generic,
5461 0x00000000);
5462 /* XXX : not implemented */
5463 spr_register(env, SPR_750_GQR2, "GQR2",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, &spr_write_generic,
5466 0x00000000);
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_750_GQR3, "GQR3",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_750_GQR4, "GQR4",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* XXX : not implemented */
5478 spr_register(env, SPR_750_GQR5, "GQR5",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* XXX : not implemented */
5483 spr_register(env, SPR_750_GQR6, "GQR6",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic,
5486 0x00000000);
5487 /* XXX : not implemented */
5488 spr_register(env, SPR_750_GQR7, "GQR7",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 &spr_read_generic, &spr_write_generic,
5491 0x00000000);
5492 /* Memory management */
5493 gen_low_BATs(env);
5494 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5495 gen_high_BATs(env);
5496 init_excp_750cl(env);
5497 env->dcache_line_size = 32;
5498 env->icache_line_size = 32;
5499 /* Allocate hardware IRQ controller */
5500 ppc6xx_irq_init(env);
5501}
5502
7856e3a4
AF		 5503POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5504{
ca5dff0a 5505 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5507
ca5dff0a 5508 dc->desc = "PowerPC 750 CL";
7856e3a4
AF		 5509 pcc->init_proc = init_proc_750cl;
5510 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5511 /* XXX: not implemented:
5512 * cache lock instructions:
5513 * dcbz_l
5514 * floating point paired instructions
5515 * psq_lux
5516 * psq_lx
5517 * psq_stux
5518 * psq_stx
5519 * ps_abs
5520 * ps_add
5521 * ps_cmpo0
5522 * ps_cmpo1
5523 * ps_cmpu0
5524 * ps_cmpu1
5525 * ps_div
5526 * ps_madd
5527 * ps_madds0
5528 * ps_madds1
5529 * ps_merge00
5530 * ps_merge01
5531 * ps_merge10
5532 * ps_merge11
5533 * ps_mr
5534 * ps_msub
5535 * ps_mul
5536 * ps_muls0
5537 * ps_muls1
5538 * ps_nabs
5539 * ps_neg
5540 * ps_nmadd
5541 * ps_nmsub
5542 * ps_res
5543 * ps_rsqrte
5544 * ps_sel
5545 * ps_sub
5546 * ps_sum0
5547 * ps_sum1
5548 */
5549 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5550 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5551 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5552 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5553 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5554 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5555 PPC_SEGMENT | PPC_EXTERN;
5556 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5557 pcc->msr_mask = 0x000000000005FF77ULL;
5558 pcc->mmu_model = POWERPC_MMU_32B;
5559 pcc->excp_model = POWERPC_EXCP_7x0;
5560 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5561 pcc->bfd_mach = bfd_mach_ppc_750;
5562 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5563 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5564}
5565
bd928eba
JM		 5566static void init_proc_750cx (CPUPPCState *env)
5567{
5568 gen_spr_ne_601(env);
5569 gen_spr_7xx(env);
5570 /* XXX : not implemented */
5571 spr_register(env, SPR_L2CR, "L2CR",
5572 SPR_NOACCESS, SPR_NOACCESS,
5573 &spr_read_generic, &spr_write_generic,
5574 0x00000000);
5575 /* Time base */
5576 gen_tbl(env);
5577 /* Thermal management */
5578 gen_spr_thrm(env);
5579 /* This register is not implemented but is present for compatibility */
5580 spr_register(env, SPR_SDA, "SDA",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, &spr_write_generic,
5583 0x00000000);
5584 /* Hardware implementation registers */
5585 /* XXX : not implemented */
5586 spr_register(env, SPR_HID0, "HID0",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 &spr_read_generic, &spr_write_generic,
5589 0x00000000);
5590 /* XXX : not implemented */
5591 spr_register(env, SPR_HID1, "HID1",
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_generic,
5594 0x00000000);
5595 /* Memory management */
5596 gen_low_BATs(env);
4e777442
JM		 5597 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5598 gen_high_BATs(env);
bd928eba
JM		 5599 init_excp_750cx(env);
5600 env->dcache_line_size = 32;
5601 env->icache_line_size = 32;
5602 /* Allocate hardware IRQ controller */
5603 ppc6xx_irq_init(env);
5604}
5605
7856e3a4
AF		 5606POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5607{
ca5dff0a 5608 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5610
ca5dff0a 5611 dc->desc = "PowerPC 750CX";
7856e3a4
AF		 5612 pcc->init_proc = init_proc_750cx;
5613 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5616 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5618 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5620 PPC_SEGMENT | PPC_EXTERN;
5621 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5622 pcc->msr_mask = 0x000000000005FF77ULL;
5623 pcc->mmu_model = POWERPC_MMU_32B;
5624 pcc->excp_model = POWERPC_EXCP_7x0;
5625 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5626 pcc->bfd_mach = bfd_mach_ppc_750;
5627 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5628 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5629}
5630
a750fc0b
JM		 5631static void init_proc_750fx (CPUPPCState *env)
5632{
5633 gen_spr_ne_601(env);
5634 gen_spr_7xx(env);
bd928eba
JM		 5635 /* XXX : not implemented */
5636 spr_register(env, SPR_L2CR, "L2CR",
5637 SPR_NOACCESS, SPR_NOACCESS,
5638 &spr_read_generic, &spr_write_generic,
5639 0x00000000);
a750fc0b
JM		 5640 /* Time base */
5641 gen_tbl(env);
5642 /* Thermal management */
5643 gen_spr_thrm(env);
bd928eba
JM		 5644 /* XXX : not implemented */
5645 spr_register(env, SPR_750_THRM4, "THRM4",
5646 SPR_NOACCESS, SPR_NOACCESS,
5647 &spr_read_generic, &spr_write_generic,
5648 0x00000000);
a750fc0b
JM		 5649 /* Hardware implementation registers */
5650 /* XXX : not implemented */
5651 spr_register(env, SPR_HID0, "HID0",
5652 SPR_NOACCESS, SPR_NOACCESS,
5653 &spr_read_generic, &spr_write_generic,
5654 0x00000000);
5655 /* XXX : not implemented */
5656 spr_register(env, SPR_HID1, "HID1",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_generic, &spr_write_generic,
5659 0x00000000);
5660 /* XXX : not implemented */
bd928eba 5661 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5662 SPR_NOACCESS, SPR_NOACCESS,
5663 &spr_read_generic, &spr_write_generic,
5664 0x00000000);
5665 /* Memory management */
5666 gen_low_BATs(env);
5667 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5668 gen_high_BATs(env);
bd928eba 5669 init_excp_7x0(env);
d63001d1
JM		 5670 env->dcache_line_size = 32;
5671 env->icache_line_size = 32;
a750fc0b
JM		 5672 /* Allocate hardware IRQ controller */
5673 ppc6xx_irq_init(env);
5674}
5675
7856e3a4
AF		 5676POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5677{
ca5dff0a 5678 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5679 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5680
ca5dff0a 5681 dc->desc = "PowerPC 750FX";
7856e3a4
AF		 5682 pcc->init_proc = init_proc_750fx;
5683 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5684 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5685 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5686 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5687 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5688 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5689 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5690 PPC_SEGMENT | PPC_EXTERN;
5691 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5692 pcc->msr_mask = 0x000000000005FF77ULL;
5693 pcc->mmu_model = POWERPC_MMU_32B;
5694 pcc->excp_model = POWERPC_EXCP_7x0;
5695 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5696 pcc->bfd_mach = bfd_mach_ppc_750;
5697 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5698 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5699}
5700
bd928eba
JM		 5701static void init_proc_750gx (CPUPPCState *env)
5702{
5703 gen_spr_ne_601(env);
5704 gen_spr_7xx(env);
5705 /* XXX : not implemented (XXX: different from 750fx) */
5706 spr_register(env, SPR_L2CR, "L2CR",
5707 SPR_NOACCESS, SPR_NOACCESS,
5708 &spr_read_generic, &spr_write_generic,
5709 0x00000000);
5710 /* Time base */
5711 gen_tbl(env);
5712 /* Thermal management */
5713 gen_spr_thrm(env);
5714 /* XXX : not implemented */
5715 spr_register(env, SPR_750_THRM4, "THRM4",
5716 SPR_NOACCESS, SPR_NOACCESS,
5717 &spr_read_generic, &spr_write_generic,
5718 0x00000000);
5719 /* Hardware implementation registers */
5720 /* XXX : not implemented (XXX: different from 750fx) */
5721 spr_register(env, SPR_HID0, "HID0",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_generic, &spr_write_generic,
5724 0x00000000);
5725 /* XXX : not implemented */
5726 spr_register(env, SPR_HID1, "HID1",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 /* XXX : not implemented (XXX: different from 750fx) */
5731 spr_register(env, SPR_750FX_HID2, "HID2",
5732 SPR_NOACCESS, SPR_NOACCESS,
5733 &spr_read_generic, &spr_write_generic,
5734 0x00000000);
5735 /* Memory management */
5736 gen_low_BATs(env);
5737 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5738 gen_high_BATs(env);
5739 init_excp_7x0(env);
5740 env->dcache_line_size = 32;
5741 env->icache_line_size = 32;
5742 /* Allocate hardware IRQ controller */
5743 ppc6xx_irq_init(env);
5744}
5745
7856e3a4
AF		 5746POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5747{
ca5dff0a 5748 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5749 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5750
ca5dff0a 5751 dc->desc = "PowerPC 750GX";
7856e3a4
AF		 5752 pcc->init_proc = init_proc_750gx;
5753 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5754 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5755 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5756 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5757 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5758 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5759 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5760 PPC_SEGMENT | PPC_EXTERN;
5761 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5762 pcc->msr_mask = 0x000000000005FF77ULL;
5763 pcc->mmu_model = POWERPC_MMU_32B;
5764 pcc->excp_model = POWERPC_EXCP_7x0;
5765 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5766 pcc->bfd_mach = bfd_mach_ppc_750;
5767 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5768 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5769}
5770
bd928eba
JM		 5771static void init_proc_745 (CPUPPCState *env)
5772{
5773 gen_spr_ne_601(env);
5774 gen_spr_7xx(env);
5775 gen_spr_G2_755(env);
5776 /* Time base */
5777 gen_tbl(env);
5778 /* Thermal management */
5779 gen_spr_thrm(env);
5780 /* Hardware implementation registers */
5781 /* XXX : not implemented */
5782 spr_register(env, SPR_HID0, "HID0",
5783 SPR_NOACCESS, SPR_NOACCESS,
5784 &spr_read_generic, &spr_write_generic,
5785 0x00000000);
5786 /* XXX : not implemented */
5787 spr_register(env, SPR_HID1, "HID1",
5788 SPR_NOACCESS, SPR_NOACCESS,
5789 &spr_read_generic, &spr_write_generic,
5790 0x00000000);
5791 /* XXX : not implemented */
5792 spr_register(env, SPR_HID2, "HID2",
5793 SPR_NOACCESS, SPR_NOACCESS,
5794 &spr_read_generic, &spr_write_generic,
5795 0x00000000);
5796 /* Memory management */
5797 gen_low_BATs(env);
5798 gen_high_BATs(env);
5799 gen_6xx_7xx_soft_tlb(env, 64, 2);
5800 init_excp_7x5(env);
5801 env->dcache_line_size = 32;
5802 env->icache_line_size = 32;
5803 /* Allocate hardware IRQ controller */
5804 ppc6xx_irq_init(env);
5805}
5806
7856e3a4
AF		 5807POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5808{
ca5dff0a 5809 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5810 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5811
ca5dff0a 5812 dc->desc = "PowerPC 745";
7856e3a4
AF		 5813 pcc->init_proc = init_proc_745;
5814 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5815 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5816 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5817 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5818 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5819 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5820 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5821 PPC_SEGMENT | PPC_EXTERN;
5822 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5823 pcc->msr_mask = 0x000000000005FF77ULL;
5824 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5825 pcc->excp_model = POWERPC_EXCP_7x5;
5826 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5827 pcc->bfd_mach = bfd_mach_ppc_750;
5828 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5829 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5830}
5831
bd928eba 5832static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5833{
5834 gen_spr_ne_601(env);
bd928eba 5835 gen_spr_7xx(env);
a750fc0b
JM		 5836 gen_spr_G2_755(env);
5837 /* Time base */
5838 gen_tbl(env);
5839 /* L2 cache control */
5840 /* XXX : not implemented */
bd928eba 5841 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5842 SPR_NOACCESS, SPR_NOACCESS,
5843 &spr_read_generic, &spr_write_generic,
5844 0x00000000);
5845 /* XXX : not implemented */
5846 spr_register(env, SPR_L2PMCR, "L2PMCR",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
bd928eba
JM		 5850 /* Thermal management */
5851 gen_spr_thrm(env);
a750fc0b
JM		 5852 /* Hardware implementation registers */
5853 /* XXX : not implemented */
5854 spr_register(env, SPR_HID0, "HID0",
5855 SPR_NOACCESS, SPR_NOACCESS,
5856 &spr_read_generic, &spr_write_generic,
5857 0x00000000);
5858 /* XXX : not implemented */
5859 spr_register(env, SPR_HID1, "HID1",
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 &spr_read_generic, &spr_write_generic,
5862 0x00000000);
5863 /* XXX : not implemented */
5864 spr_register(env, SPR_HID2, "HID2",
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 &spr_read_generic, &spr_write_generic,
5867 0x00000000);
5868 /* Memory management */
5869 gen_low_BATs(env);
5870 gen_high_BATs(env);
5871 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5872 init_excp_7x5(env);
d63001d1
JM		 5873 env->dcache_line_size = 32;
5874 env->icache_line_size = 32;
a750fc0b
JM		 5875 /* Allocate hardware IRQ controller */
5876 ppc6xx_irq_init(env);
5877}
5878
7856e3a4
AF		 5879POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5880{
ca5dff0a 5881 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5882 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5883
ca5dff0a 5884 dc->desc = "PowerPC 755";
7856e3a4
AF		 5885 pcc->init_proc = init_proc_755;
5886 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5887 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5888 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5889 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5890 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5891 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5892 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5893 PPC_SEGMENT | PPC_EXTERN;
5894 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5895 pcc->msr_mask = 0x000000000005FF77ULL;
5896 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5897 pcc->excp_model = POWERPC_EXCP_7x5;
5898 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5899 pcc->bfd_mach = bfd_mach_ppc_750;
5900 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5901 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5902}
5903
a750fc0b
JM		 5904static void init_proc_7400 (CPUPPCState *env)
5905{
5906 gen_spr_ne_601(env);
5907 gen_spr_7xx(env);
5908 /* Time base */
5909 gen_tbl(env);
5910 /* 74xx specific SPR */
5911 gen_spr_74xx(env);
4e777442
JM		 5912 /* XXX : not implemented */
5913 spr_register(env, SPR_UBAMR, "UBAMR",
5914 &spr_read_ureg, SPR_NOACCESS,
5915 &spr_read_ureg, SPR_NOACCESS,
5916 0x00000000);
5917 /* XXX: this seems not implemented on all revisions. */
5918 /* XXX : not implemented */
5919 spr_register(env, SPR_MSSCR1, "MSSCR1",
5920 SPR_NOACCESS, SPR_NOACCESS,
5921 &spr_read_generic, &spr_write_generic,
5922 0x00000000);
a750fc0b
JM		 5923 /* Thermal management */
5924 gen_spr_thrm(env);
5925 /* Memory management */
5926 gen_low_BATs(env);
e1833e1f 5927 init_excp_7400(env);
d63001d1
JM		 5928 env->dcache_line_size = 32;
5929 env->icache_line_size = 32;
a750fc0b
JM		 5930 /* Allocate hardware IRQ controller */
5931 ppc6xx_irq_init(env);
5932}
5933
7856e3a4
AF		 5934POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5935{
ca5dff0a 5936 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5938
ca5dff0a 5939 dc->desc = "PowerPC 7400 (aka G4)";
7856e3a4
AF		 5940 pcc->init_proc = init_proc_7400;
5941 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5943 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5944 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5945 PPC_FLOAT_STFIWX |
5946 PPC_CACHE | PPC_CACHE_ICBI |
5947 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5948 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5949 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5950 PPC_MEM_TLBIA |
5951 PPC_SEGMENT | PPC_EXTERN |
5952 PPC_ALTIVEC;
5953 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 5954 pcc->msr_mask = 0x000000000205FF77ULL;
5955 pcc->mmu_model = POWERPC_MMU_32B;
5956 pcc->excp_model = POWERPC_EXCP_74xx;
5957 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5958 pcc->bfd_mach = bfd_mach_ppc_7400;
5959 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5960 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5961 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5962}
5963
a750fc0b
JM		 5964static void init_proc_7410 (CPUPPCState *env)
5965{
5966 gen_spr_ne_601(env);
5967 gen_spr_7xx(env);
5968 /* Time base */
5969 gen_tbl(env);
5970 /* 74xx specific SPR */
5971 gen_spr_74xx(env);
4e777442
JM		 5972 /* XXX : not implemented */
5973 spr_register(env, SPR_UBAMR, "UBAMR",
5974 &spr_read_ureg, SPR_NOACCESS,
5975 &spr_read_ureg, SPR_NOACCESS,
5976 0x00000000);
a750fc0b
JM		 5977 /* Thermal management */
5978 gen_spr_thrm(env);
5979 /* L2PMCR */
5980 /* XXX : not implemented */
5981 spr_register(env, SPR_L2PMCR, "L2PMCR",
5982 SPR_NOACCESS, SPR_NOACCESS,
5983 &spr_read_generic, &spr_write_generic,
5984 0x00000000);
5985 /* LDSTDB */
5986 /* XXX : not implemented */
5987 spr_register(env, SPR_LDSTDB, "LDSTDB",
5988 SPR_NOACCESS, SPR_NOACCESS,
5989 &spr_read_generic, &spr_write_generic,
5990 0x00000000);
5991 /* Memory management */
5992 gen_low_BATs(env);
e1833e1f 5993 init_excp_7400(env);
d63001d1
JM		 5994 env->dcache_line_size = 32;
5995 env->icache_line_size = 32;
a750fc0b
JM		 5996 /* Allocate hardware IRQ controller */
5997 ppc6xx_irq_init(env);
5998}
5999
7856e3a4
AF		 6000POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6001{
ca5dff0a 6002 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6003 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6004
ca5dff0a 6005 dc->desc = "PowerPC 7410 (aka G4)";
7856e3a4
AF		 6006 pcc->init_proc = init_proc_7410;
6007 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6008 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6009 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6010 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6011 PPC_FLOAT_STFIWX |
6012 PPC_CACHE | PPC_CACHE_ICBI |
6013 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6014 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6015 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6016 PPC_MEM_TLBIA |
6017 PPC_SEGMENT | PPC_EXTERN |
6018 PPC_ALTIVEC;
6019 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6020 pcc->msr_mask = 0x000000000205FF77ULL;
6021 pcc->mmu_model = POWERPC_MMU_32B;
6022 pcc->excp_model = POWERPC_EXCP_74xx;
6023 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6024 pcc->bfd_mach = bfd_mach_ppc_7400;
6025 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6027 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6028}
6029
a750fc0b
JM		 6030static void init_proc_7440 (CPUPPCState *env)
6031{
6032 gen_spr_ne_601(env);
6033 gen_spr_7xx(env);
6034 /* Time base */
6035 gen_tbl(env);
6036 /* 74xx specific SPR */
6037 gen_spr_74xx(env);
4e777442
JM		 6038 /* XXX : not implemented */
6039 spr_register(env, SPR_UBAMR, "UBAMR",
6040 &spr_read_ureg, SPR_NOACCESS,
6041 &spr_read_ureg, SPR_NOACCESS,
6042 0x00000000);
a750fc0b
JM		 6043 /* LDSTCR */
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_LDSTCR, "LDSTCR",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 &spr_read_generic, &spr_write_generic,
6048 0x00000000);
6049 /* ICTRL */
6050 /* XXX : not implemented */
6051 spr_register(env, SPR_ICTRL, "ICTRL",
6052 SPR_NOACCESS, SPR_NOACCESS,
6053 &spr_read_generic, &spr_write_generic,
6054 0x00000000);
6055 /* MSSSR0 */
578bb252 6056 /* XXX : not implemented */
a750fc0b
JM		 6057 spr_register(env, SPR_MSSSR0, "MSSSR0",
6058 SPR_NOACCESS, SPR_NOACCESS,
6059 &spr_read_generic, &spr_write_generic,
6060 0x00000000);
6061 /* PMC */
6062 /* XXX : not implemented */
6063 spr_register(env, SPR_PMC5, "PMC5",
6064 SPR_NOACCESS, SPR_NOACCESS,
6065 &spr_read_generic, &spr_write_generic,
6066 0x00000000);
578bb252 6067 /* XXX : not implemented */
a750fc0b
JM		 6068 spr_register(env, SPR_UPMC5, "UPMC5",
6069 &spr_read_ureg, SPR_NOACCESS,
6070 &spr_read_ureg, SPR_NOACCESS,
6071 0x00000000);
578bb252 6072 /* XXX : not implemented */
a750fc0b
JM		 6073 spr_register(env, SPR_PMC6, "PMC6",
6074 SPR_NOACCESS, SPR_NOACCESS,
6075 &spr_read_generic, &spr_write_generic,
6076 0x00000000);
578bb252 6077 /* XXX : not implemented */
a750fc0b
JM		 6078 spr_register(env, SPR_UPMC6, "UPMC6",
6079 &spr_read_ureg, SPR_NOACCESS,
6080 &spr_read_ureg, SPR_NOACCESS,
6081 0x00000000);
6082 /* Memory management */
6083 gen_low_BATs(env);
578bb252 6084 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 6085 init_excp_7450(env);
d63001d1
JM		 6086 env->dcache_line_size = 32;
6087 env->icache_line_size = 32;
a750fc0b
JM		 6088 /* Allocate hardware IRQ controller */
6089 ppc6xx_irq_init(env);
6090}
a750fc0b 6091
7856e3a4
AF		 6092POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6093{
ca5dff0a 6094 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6095 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6096
ca5dff0a 6097 dc->desc = "PowerPC 7440 (aka G4)";
7856e3a4
AF		 6098 pcc->init_proc = init_proc_7440;
6099 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6100 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6101 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6102 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6103 PPC_FLOAT_STFIWX |
6104 PPC_CACHE | PPC_CACHE_ICBI |
6105 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6106 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6107 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6108 PPC_MEM_TLBIA | PPC_74xx_TLB |
6109 PPC_SEGMENT | PPC_EXTERN |
6110 PPC_ALTIVEC;
6111 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6112 pcc->msr_mask = 0x000000000205FF77ULL;
6113 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6114 pcc->excp_model = POWERPC_EXCP_74xx;
6115 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6116 pcc->bfd_mach = bfd_mach_ppc_7400;
6117 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6118 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6119 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6120}
6121
a750fc0b
JM		 6122static void init_proc_7450 (CPUPPCState *env)
6123{
6124 gen_spr_ne_601(env);
6125 gen_spr_7xx(env);
6126 /* Time base */
6127 gen_tbl(env);
6128 /* 74xx specific SPR */
6129 gen_spr_74xx(env);
6130 /* Level 3 cache control */
6131 gen_l3_ctrl(env);
4e777442
JM		 6132 /* L3ITCR1 */
6133 /* XXX : not implemented */
6134 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6135 SPR_NOACCESS, SPR_NOACCESS,
6136 &spr_read_generic, &spr_write_generic,
6137 0x00000000);
6138 /* L3ITCR2 */
6139 /* XXX : not implemented */
6140 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6141 SPR_NOACCESS, SPR_NOACCESS,
6142 &spr_read_generic, &spr_write_generic,
6143 0x00000000);
6144 /* L3ITCR3 */
6145 /* XXX : not implemented */
6146 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0x00000000);
6150 /* L3OHCR */
6151 /* XXX : not implemented */
6152 spr_register(env, SPR_L3OHCR, "L3OHCR",
6153 SPR_NOACCESS, SPR_NOACCESS,
6154 &spr_read_generic, &spr_write_generic,
6155 0x00000000);
6156 /* XXX : not implemented */
6157 spr_register(env, SPR_UBAMR, "UBAMR",
6158 &spr_read_ureg, SPR_NOACCESS,
6159 &spr_read_ureg, SPR_NOACCESS,
6160 0x00000000);
a750fc0b
JM		 6161 /* LDSTCR */
6162 /* XXX : not implemented */
6163 spr_register(env, SPR_LDSTCR, "LDSTCR",
6164 SPR_NOACCESS, SPR_NOACCESS,
6165 &spr_read_generic, &spr_write_generic,
6166 0x00000000);
6167 /* ICTRL */
6168 /* XXX : not implemented */
6169 spr_register(env, SPR_ICTRL, "ICTRL",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 0x00000000);
6173 /* MSSSR0 */
578bb252 6174 /* XXX : not implemented */
a750fc0b
JM		 6175 spr_register(env, SPR_MSSSR0, "MSSSR0",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 /* PMC */
6180 /* XXX : not implemented */
6181 spr_register(env, SPR_PMC5, "PMC5",
6182 SPR_NOACCESS, SPR_NOACCESS,
6183 &spr_read_generic, &spr_write_generic,
6184 0x00000000);
578bb252 6185 /* XXX : not implemented */
a750fc0b
JM		 6186 spr_register(env, SPR_UPMC5, "UPMC5",
6187 &spr_read_ureg, SPR_NOACCESS,
6188 &spr_read_ureg, SPR_NOACCESS,
6189 0x00000000);
578bb252 6190 /* XXX : not implemented */
a750fc0b
JM		 6191 spr_register(env, SPR_PMC6, "PMC6",
6192 SPR_NOACCESS, SPR_NOACCESS,
6193 &spr_read_generic, &spr_write_generic,
6194 0x00000000);
578bb252 6195 /* XXX : not implemented */
a750fc0b
JM		 6196 spr_register(env, SPR_UPMC6, "UPMC6",
6197 &spr_read_ureg, SPR_NOACCESS,
6198 &spr_read_ureg, SPR_NOACCESS,
6199 0x00000000);
6200 /* Memory management */
6201 gen_low_BATs(env);
578bb252 6202 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6203 init_excp_7450(env);
d63001d1
JM		 6204 env->dcache_line_size = 32;
6205 env->icache_line_size = 32;
a750fc0b
JM		 6206 /* Allocate hardware IRQ controller */
6207 ppc6xx_irq_init(env);
6208}
a750fc0b 6209
7856e3a4
AF		 6210POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6211{
ca5dff0a 6212 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6213 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6214
ca5dff0a 6215 dc->desc = "PowerPC 7450 (aka G4)";
7856e3a4
AF		 6216 pcc->init_proc = init_proc_7450;
6217 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6218 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6219 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6220 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6221 PPC_FLOAT_STFIWX |
6222 PPC_CACHE | PPC_CACHE_ICBI |
6223 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6224 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6225 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6226 PPC_MEM_TLBIA | PPC_74xx_TLB |
6227 PPC_SEGMENT | PPC_EXTERN |
6228 PPC_ALTIVEC;
6229 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6230 pcc->msr_mask = 0x000000000205FF77ULL;
6231 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6232 pcc->excp_model = POWERPC_EXCP_74xx;
6233 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6234 pcc->bfd_mach = bfd_mach_ppc_7400;
6235 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6236 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6237 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6238}
6239
a750fc0b
JM		 6240static void init_proc_7445 (CPUPPCState *env)
6241{
6242 gen_spr_ne_601(env);
6243 gen_spr_7xx(env);
6244 /* Time base */
6245 gen_tbl(env);
6246 /* 74xx specific SPR */
6247 gen_spr_74xx(env);
6248 /* LDSTCR */
6249 /* XXX : not implemented */
6250 spr_register(env, SPR_LDSTCR, "LDSTCR",
6251 SPR_NOACCESS, SPR_NOACCESS,
6252 &spr_read_generic, &spr_write_generic,
6253 0x00000000);
6254 /* ICTRL */
6255 /* XXX : not implemented */
6256 spr_register(env, SPR_ICTRL, "ICTRL",
6257 SPR_NOACCESS, SPR_NOACCESS,
6258 &spr_read_generic, &spr_write_generic,
6259 0x00000000);
6260 /* MSSSR0 */
578bb252 6261 /* XXX : not implemented */
a750fc0b
JM		 6262 spr_register(env, SPR_MSSSR0, "MSSSR0",
6263 SPR_NOACCESS, SPR_NOACCESS,
6264 &spr_read_generic, &spr_write_generic,
6265 0x00000000);
6266 /* PMC */
6267 /* XXX : not implemented */
6268 spr_register(env, SPR_PMC5, "PMC5",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_generic, &spr_write_generic,
6271 0x00000000);
578bb252 6272 /* XXX : not implemented */
a750fc0b
JM		 6273 spr_register(env, SPR_UPMC5, "UPMC5",
6274 &spr_read_ureg, SPR_NOACCESS,
6275 &spr_read_ureg, SPR_NOACCESS,
6276 0x00000000);
578bb252 6277 /* XXX : not implemented */
a750fc0b
JM		 6278 spr_register(env, SPR_PMC6, "PMC6",
6279 SPR_NOACCESS, SPR_NOACCESS,
6280 &spr_read_generic, &spr_write_generic,
6281 0x00000000);
578bb252 6282 /* XXX : not implemented */
a750fc0b
JM		 6283 spr_register(env, SPR_UPMC6, "UPMC6",
6284 &spr_read_ureg, SPR_NOACCESS,
6285 &spr_read_ureg, SPR_NOACCESS,
6286 0x00000000);
6287 /* SPRGs */
6288 spr_register(env, SPR_SPRG4, "SPRG4",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 spr_register(env, SPR_USPRG4, "USPRG4",
6293 &spr_read_ureg, SPR_NOACCESS,
6294 &spr_read_ureg, SPR_NOACCESS,
6295 0x00000000);
6296 spr_register(env, SPR_SPRG5, "SPRG5",
6297 SPR_NOACCESS, SPR_NOACCESS,
6298 &spr_read_generic, &spr_write_generic,
6299 0x00000000);
6300 spr_register(env, SPR_USPRG5, "USPRG5",
6301 &spr_read_ureg, SPR_NOACCESS,
6302 &spr_read_ureg, SPR_NOACCESS,
6303 0x00000000);
6304 spr_register(env, SPR_SPRG6, "SPRG6",
6305 SPR_NOACCESS, SPR_NOACCESS,
6306 &spr_read_generic, &spr_write_generic,
6307 0x00000000);
6308 spr_register(env, SPR_USPRG6, "USPRG6",
6309 &spr_read_ureg, SPR_NOACCESS,
6310 &spr_read_ureg, SPR_NOACCESS,
6311 0x00000000);
6312 spr_register(env, SPR_SPRG7, "SPRG7",
6313 SPR_NOACCESS, SPR_NOACCESS,
6314 &spr_read_generic, &spr_write_generic,
6315 0x00000000);
6316 spr_register(env, SPR_USPRG7, "USPRG7",
6317 &spr_read_ureg, SPR_NOACCESS,
6318 &spr_read_ureg, SPR_NOACCESS,
6319 0x00000000);
6320 /* Memory management */
6321 gen_low_BATs(env);
6322 gen_high_BATs(env);
578bb252 6323 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6324 init_excp_7450(env);
d63001d1
JM		 6325 env->dcache_line_size = 32;
6326 env->icache_line_size = 32;
a750fc0b
JM		 6327 /* Allocate hardware IRQ controller */
6328 ppc6xx_irq_init(env);
6329}
a750fc0b 6330
7856e3a4
AF		 6331POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6332{
ca5dff0a 6333 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6334 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6335
ca5dff0a 6336 dc->desc = "PowerPC 7445 (aka G4)";
7856e3a4
AF		 6337 pcc->init_proc = init_proc_7445;
6338 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6339 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6340 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6341 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6342 PPC_FLOAT_STFIWX |
6343 PPC_CACHE | PPC_CACHE_ICBI |
6344 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6345 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6346 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6347 PPC_MEM_TLBIA | PPC_74xx_TLB |
6348 PPC_SEGMENT | PPC_EXTERN |
6349 PPC_ALTIVEC;
6350 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6351 pcc->msr_mask = 0x000000000205FF77ULL;
6352 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6353 pcc->excp_model = POWERPC_EXCP_74xx;
6354 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6355 pcc->bfd_mach = bfd_mach_ppc_7400;
6356 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6358 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6359}
6360
a750fc0b
JM		 6361static void init_proc_7455 (CPUPPCState *env)
6362{
6363 gen_spr_ne_601(env);
6364 gen_spr_7xx(env);
6365 /* Time base */
6366 gen_tbl(env);
6367 /* 74xx specific SPR */
6368 gen_spr_74xx(env);
6369 /* Level 3 cache control */
6370 gen_l3_ctrl(env);
6371 /* LDSTCR */
6372 /* XXX : not implemented */
6373 spr_register(env, SPR_LDSTCR, "LDSTCR",
6374 SPR_NOACCESS, SPR_NOACCESS,
6375 &spr_read_generic, &spr_write_generic,
6376 0x00000000);
6377 /* ICTRL */
6378 /* XXX : not implemented */
6379 spr_register(env, SPR_ICTRL, "ICTRL",
6380 SPR_NOACCESS, SPR_NOACCESS,
6381 &spr_read_generic, &spr_write_generic,
6382 0x00000000);
6383 /* MSSSR0 */
578bb252 6384 /* XXX : not implemented */
a750fc0b
JM		 6385 spr_register(env, SPR_MSSSR0, "MSSSR0",
6386 SPR_NOACCESS, SPR_NOACCESS,
6387 &spr_read_generic, &spr_write_generic,
6388 0x00000000);
6389 /* PMC */
6390 /* XXX : not implemented */
6391 spr_register(env, SPR_PMC5, "PMC5",
6392 SPR_NOACCESS, SPR_NOACCESS,
6393 &spr_read_generic, &spr_write_generic,
6394 0x00000000);
578bb252 6395 /* XXX : not implemented */
a750fc0b
JM		 6396 spr_register(env, SPR_UPMC5, "UPMC5",
6397 &spr_read_ureg, SPR_NOACCESS,
6398 &spr_read_ureg, SPR_NOACCESS,
6399 0x00000000);
578bb252 6400 /* XXX : not implemented */
a750fc0b
JM		 6401 spr_register(env, SPR_PMC6, "PMC6",
6402 SPR_NOACCESS, SPR_NOACCESS,
6403 &spr_read_generic, &spr_write_generic,
6404 0x00000000);
578bb252 6405 /* XXX : not implemented */
a750fc0b
JM		 6406 spr_register(env, SPR_UPMC6, "UPMC6",
6407 &spr_read_ureg, SPR_NOACCESS,
6408 &spr_read_ureg, SPR_NOACCESS,
6409 0x00000000);
6410 /* SPRGs */
6411 spr_register(env, SPR_SPRG4, "SPRG4",
6412 SPR_NOACCESS, SPR_NOACCESS,
6413 &spr_read_generic, &spr_write_generic,
6414 0x00000000);
6415 spr_register(env, SPR_USPRG4, "USPRG4",
6416 &spr_read_ureg, SPR_NOACCESS,
6417 &spr_read_ureg, SPR_NOACCESS,
6418 0x00000000);
6419 spr_register(env, SPR_SPRG5, "SPRG5",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 0x00000000);
6423 spr_register(env, SPR_USPRG5, "USPRG5",
6424 &spr_read_ureg, SPR_NOACCESS,
6425 &spr_read_ureg, SPR_NOACCESS,
6426 0x00000000);
6427 spr_register(env, SPR_SPRG6, "SPRG6",
6428 SPR_NOACCESS, SPR_NOACCESS,
6429 &spr_read_generic, &spr_write_generic,
6430 0x00000000);
6431 spr_register(env, SPR_USPRG6, "USPRG6",
6432 &spr_read_ureg, SPR_NOACCESS,
6433 &spr_read_ureg, SPR_NOACCESS,
6434 0x00000000);
6435 spr_register(env, SPR_SPRG7, "SPRG7",
6436 SPR_NOACCESS, SPR_NOACCESS,
6437 &spr_read_generic, &spr_write_generic,
6438 0x00000000);
6439 spr_register(env, SPR_USPRG7, "USPRG7",
6440 &spr_read_ureg, SPR_NOACCESS,
6441 &spr_read_ureg, SPR_NOACCESS,
6442 0x00000000);
6443 /* Memory management */
6444 gen_low_BATs(env);
6445 gen_high_BATs(env);
578bb252 6446 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6447 init_excp_7450(env);
d63001d1
JM		 6448 env->dcache_line_size = 32;
6449 env->icache_line_size = 32;
a750fc0b
JM		 6450 /* Allocate hardware IRQ controller */
6451 ppc6xx_irq_init(env);
6452}
a750fc0b 6453
7856e3a4
AF		 6454POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6455{
ca5dff0a 6456 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6457 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6458
ca5dff0a 6459 dc->desc = "PowerPC 7455 (aka G4)";
7856e3a4
AF		 6460 pcc->init_proc = init_proc_7455;
6461 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6462 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6464 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6465 PPC_FLOAT_STFIWX |
6466 PPC_CACHE | PPC_CACHE_ICBI |
6467 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6468 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6469 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6470 PPC_MEM_TLBIA | PPC_74xx_TLB |
6471 PPC_SEGMENT | PPC_EXTERN |
6472 PPC_ALTIVEC;
6473 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6474 pcc->msr_mask = 0x000000000205FF77ULL;
6475 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6476 pcc->excp_model = POWERPC_EXCP_74xx;
6477 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6478 pcc->bfd_mach = bfd_mach_ppc_7400;
6479 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6480 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6481 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6482}
6483
4e777442
JM		 6484static void init_proc_7457 (CPUPPCState *env)
6485{
6486 gen_spr_ne_601(env);
6487 gen_spr_7xx(env);
6488 /* Time base */
6489 gen_tbl(env);
6490 /* 74xx specific SPR */
6491 gen_spr_74xx(env);
6492 /* Level 3 cache control */
6493 gen_l3_ctrl(env);
6494 /* L3ITCR1 */
6495 /* XXX : not implemented */
6496 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6497 SPR_NOACCESS, SPR_NOACCESS,
6498 &spr_read_generic, &spr_write_generic,
6499 0x00000000);
6500 /* L3ITCR2 */
6501 /* XXX : not implemented */
6502 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6503 SPR_NOACCESS, SPR_NOACCESS,
6504 &spr_read_generic, &spr_write_generic,
6505 0x00000000);
6506 /* L3ITCR3 */
6507 /* XXX : not implemented */
6508 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6509 SPR_NOACCESS, SPR_NOACCESS,
6510 &spr_read_generic, &spr_write_generic,
6511 0x00000000);
6512 /* L3OHCR */
6513 /* XXX : not implemented */
6514 spr_register(env, SPR_L3OHCR, "L3OHCR",
6515 SPR_NOACCESS, SPR_NOACCESS,
6516 &spr_read_generic, &spr_write_generic,
6517 0x00000000);
6518 /* LDSTCR */
6519 /* XXX : not implemented */
6520 spr_register(env, SPR_LDSTCR, "LDSTCR",
6521 SPR_NOACCESS, SPR_NOACCESS,
6522 &spr_read_generic, &spr_write_generic,
6523 0x00000000);
6524 /* ICTRL */
6525 /* XXX : not implemented */
6526 spr_register(env, SPR_ICTRL, "ICTRL",
6527 SPR_NOACCESS, SPR_NOACCESS,
6528 &spr_read_generic, &spr_write_generic,
6529 0x00000000);
6530 /* MSSSR0 */
6531 /* XXX : not implemented */
6532 spr_register(env, SPR_MSSSR0, "MSSSR0",
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 0x00000000);
6536 /* PMC */
6537 /* XXX : not implemented */
6538 spr_register(env, SPR_PMC5, "PMC5",
6539 SPR_NOACCESS, SPR_NOACCESS,
6540 &spr_read_generic, &spr_write_generic,
6541 0x00000000);
6542 /* XXX : not implemented */
6543 spr_register(env, SPR_UPMC5, "UPMC5",
6544 &spr_read_ureg, SPR_NOACCESS,
6545 &spr_read_ureg, SPR_NOACCESS,
6546 0x00000000);
6547 /* XXX : not implemented */
6548 spr_register(env, SPR_PMC6, "PMC6",
6549 SPR_NOACCESS, SPR_NOACCESS,
6550 &spr_read_generic, &spr_write_generic,
6551 0x00000000);
6552 /* XXX : not implemented */
6553 spr_register(env, SPR_UPMC6, "UPMC6",
6554 &spr_read_ureg, SPR_NOACCESS,
6555 &spr_read_ureg, SPR_NOACCESS,
6556 0x00000000);
6557 /* SPRGs */
6558 spr_register(env, SPR_SPRG4, "SPRG4",
6559 SPR_NOACCESS, SPR_NOACCESS,
6560 &spr_read_generic, &spr_write_generic,
6561 0x00000000);
6562 spr_register(env, SPR_USPRG4, "USPRG4",
6563 &spr_read_ureg, SPR_NOACCESS,
6564 &spr_read_ureg, SPR_NOACCESS,
6565 0x00000000);
6566 spr_register(env, SPR_SPRG5, "SPRG5",
6567 SPR_NOACCESS, SPR_NOACCESS,
6568 &spr_read_generic, &spr_write_generic,
6569 0x00000000);
6570 spr_register(env, SPR_USPRG5, "USPRG5",
6571 &spr_read_ureg, SPR_NOACCESS,
6572 &spr_read_ureg, SPR_NOACCESS,
6573 0x00000000);
6574 spr_register(env, SPR_SPRG6, "SPRG6",
6575 SPR_NOACCESS, SPR_NOACCESS,
6576 &spr_read_generic, &spr_write_generic,
6577 0x00000000);
6578 spr_register(env, SPR_USPRG6, "USPRG6",
6579 &spr_read_ureg, SPR_NOACCESS,
6580 &spr_read_ureg, SPR_NOACCESS,
6581 0x00000000);
6582 spr_register(env, SPR_SPRG7, "SPRG7",
6583 SPR_NOACCESS, SPR_NOACCESS,
6584 &spr_read_generic, &spr_write_generic,
6585 0x00000000);
6586 spr_register(env, SPR_USPRG7, "USPRG7",
6587 &spr_read_ureg, SPR_NOACCESS,
6588 &spr_read_ureg, SPR_NOACCESS,
6589 0x00000000);
6590 /* Memory management */
6591 gen_low_BATs(env);
6592 gen_high_BATs(env);
6593 gen_74xx_soft_tlb(env, 128, 2);
6594 init_excp_7450(env);
6595 env->dcache_line_size = 32;
6596 env->icache_line_size = 32;
6597 /* Allocate hardware IRQ controller */
6598 ppc6xx_irq_init(env);
6599}
6600
7856e3a4
AF		 6601POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6602{
ca5dff0a 6603 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6604 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6605
ca5dff0a 6606 dc->desc = "PowerPC 7457 (aka G4)";
7856e3a4
AF		 6607 pcc->init_proc = init_proc_7457;
6608 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6609 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6610 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6611 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6612 PPC_FLOAT_STFIWX |
6613 PPC_CACHE | PPC_CACHE_ICBI |
6614 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6615 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6616 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6617 PPC_MEM_TLBIA | PPC_74xx_TLB |
6618 PPC_SEGMENT | PPC_EXTERN |
6619 PPC_ALTIVEC;
6620 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6621 pcc->msr_mask = 0x000000000205FF77ULL;
6622 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6623 pcc->excp_model = POWERPC_EXCP_74xx;
6624 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6625 pcc->bfd_mach = bfd_mach_ppc_7400;
6626 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6627 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6628 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6629}
6630
a750fc0b 6631#if defined (TARGET_PPC64)
417bf010
JM		 6632#if defined(CONFIG_USER_ONLY)
6633#define POWERPC970_HID5_INIT 0x00000080
6634#else
6635#define POWERPC970_HID5_INIT 0x00000000
6636#endif
6637
2f462816
JM		 6638static int check_pow_970 (CPUPPCState *env)
6639{
6640 if (env->spr[SPR_HID0] & 0x00600000)
6641 return 1;
6642
6643 return 0;
6644}
6645
a750fc0b
JM		 6646static void init_proc_970 (CPUPPCState *env)
6647{
6648 gen_spr_ne_601(env);
6649 gen_spr_7xx(env);
6650 /* Time base */
6651 gen_tbl(env);
6652 /* Hardware implementation registers */
6653 /* XXX : not implemented */
6654 spr_register(env, SPR_HID0, "HID0",
6655 SPR_NOACCESS, SPR_NOACCESS,
06403421 6656 &spr_read_generic, &spr_write_clear,
d63001d1 6657 0x60000000);
a750fc0b
JM		 6658 /* XXX : not implemented */
6659 spr_register(env, SPR_HID1, "HID1",
6660 SPR_NOACCESS, SPR_NOACCESS,
6661 &spr_read_generic, &spr_write_generic,
6662 0x00000000);
6663 /* XXX : not implemented */
bd928eba 6664 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6665 SPR_NOACCESS, SPR_NOACCESS,
6666 &spr_read_generic, &spr_write_generic,
6667 0x00000000);
e57448f1
JM		 6668 /* XXX : not implemented */
6669 spr_register(env, SPR_970_HID5, "HID5",
6670 SPR_NOACCESS, SPR_NOACCESS,
6671 &spr_read_generic, &spr_write_generic,
417bf010 6672 POWERPC970_HID5_INIT);
bd928eba
JM		 6673 /* XXX : not implemented */
6674 spr_register(env, SPR_L2CR, "L2CR",
6675 SPR_NOACCESS, SPR_NOACCESS,
6676 &spr_read_generic, &spr_write_generic,
6677 0x00000000);
a750fc0b
JM		 6678 /* Memory management */
6679 /* XXX: not correct */
6680 gen_low_BATs(env);
12de9a39
JM		 6681 /* XXX : not implemented */
6682 spr_register(env, SPR_MMUCFG, "MMUCFG",
6683 SPR_NOACCESS, SPR_NOACCESS,
6684 &spr_read_generic, SPR_NOACCESS,
6685 0x00000000); /* TOFIX */
6686 /* XXX : not implemented */
6687 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6688 SPR_NOACCESS, SPR_NOACCESS,
6689 &spr_read_generic, &spr_write_generic,
6690 0x00000000); /* TOFIX */
6691 spr_register(env, SPR_HIOR, "SPR_HIOR",
6692 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6693 &spr_read_hior, &spr_write_hior,
6694 0x00000000);
f2e63a42 6695#if !defined(CONFIG_USER_ONLY)
12de9a39 6696 env->slb_nr = 32;
f2e63a42 6697#endif
e1833e1f 6698 init_excp_970(env);
d63001d1
JM		 6699 env->dcache_line_size = 128;
6700 env->icache_line_size = 128;
a750fc0b
JM		 6701 /* Allocate hardware IRQ controller */
6702 ppc970_irq_init(env);
cf8358c8
AJ		 6703 /* Can't find information on what this should be on reset. This
6704 * value is the one used by 74xx processors. */
6705 vscr_init(env, 0x00010000);
a750fc0b 6706}
a750fc0b 6707
7856e3a4
AF		 6708POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6709{
ca5dff0a 6710 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6712
ca5dff0a 6713 dc->desc = "PowerPC 970";
7856e3a4
AF		 6714 pcc->init_proc = init_proc_970;
6715 pcc->check_pow = check_pow_970;
53116ebf
AF		 6716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6718 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6719 PPC_FLOAT_STFIWX |
6720 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6721 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6722 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6723 PPC_64B | PPC_ALTIVEC |
6724 PPC_SEGMENT_64B | PPC_SLBI;
6725 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6726 pcc->msr_mask = 0x900000000204FF36ULL;
6727 pcc->mmu_model = POWERPC_MMU_64B;
6728 pcc->excp_model = POWERPC_EXCP_970;
6729 pcc->bus_model = PPC_FLAGS_INPUT_970;
6730 pcc->bfd_mach = bfd_mach_ppc64;
6731 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6732 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6733 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6734}
6735
2f462816
JM		 6736static int check_pow_970FX (CPUPPCState *env)
6737{
6738 if (env->spr[SPR_HID0] & 0x00600000)
6739 return 1;
6740
6741 return 0;
6742}
6743
a750fc0b
JM		 6744static void init_proc_970FX (CPUPPCState *env)
6745{
6746 gen_spr_ne_601(env);
6747 gen_spr_7xx(env);
6748 /* Time base */
6749 gen_tbl(env);
6750 /* Hardware implementation registers */
6751 /* XXX : not implemented */
6752 spr_register(env, SPR_HID0, "HID0",
6753 SPR_NOACCESS, SPR_NOACCESS,
06403421 6754 &spr_read_generic, &spr_write_clear,
d63001d1 6755 0x60000000);
a750fc0b
JM		 6756 /* XXX : not implemented */
6757 spr_register(env, SPR_HID1, "HID1",
6758 SPR_NOACCESS, SPR_NOACCESS,
6759 &spr_read_generic, &spr_write_generic,
6760 0x00000000);
6761 /* XXX : not implemented */
bd928eba 6762 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6763 SPR_NOACCESS, SPR_NOACCESS,
6764 &spr_read_generic, &spr_write_generic,
6765 0x00000000);
d63001d1
JM		 6766 /* XXX : not implemented */
6767 spr_register(env, SPR_970_HID5, "HID5",
6768 SPR_NOACCESS, SPR_NOACCESS,
6769 &spr_read_generic, &spr_write_generic,
417bf010 6770 POWERPC970_HID5_INIT);
bd928eba
JM		 6771 /* XXX : not implemented */
6772 spr_register(env, SPR_L2CR, "L2CR",
6773 SPR_NOACCESS, SPR_NOACCESS,
6774 &spr_read_generic, &spr_write_generic,
6775 0x00000000);
a750fc0b
JM		 6776 /* Memory management */
6777 /* XXX: not correct */
6778 gen_low_BATs(env);
12de9a39
JM		 6779 /* XXX : not implemented */
6780 spr_register(env, SPR_MMUCFG, "MMUCFG",
6781 SPR_NOACCESS, SPR_NOACCESS,
6782 &spr_read_generic, SPR_NOACCESS,
6783 0x00000000); /* TOFIX */
6784 /* XXX : not implemented */
6785 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6786 SPR_NOACCESS, SPR_NOACCESS,
6787 &spr_read_generic, &spr_write_generic,
6788 0x00000000); /* TOFIX */
6789 spr_register(env, SPR_HIOR, "SPR_HIOR",
6790 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6791 &spr_read_hior, &spr_write_hior,
6792 0x00000000);
4e98d8cf
BS		 6793 spr_register(env, SPR_CTRL, "SPR_CTRL",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 &spr_read_generic, &spr_write_generic,
6796 0x00000000);
6797 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6798 SPR_NOACCESS, SPR_NOACCESS,
6799 &spr_read_generic, &spr_write_generic,
6800 0x00000000);
6801 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6802 &spr_read_generic, &spr_write_generic,
6803 &spr_read_generic, &spr_write_generic,
6804 0x00000000);
f2e63a42 6805#if !defined(CONFIG_USER_ONLY)
8eee0af9 6806 env->slb_nr = 64;
f2e63a42 6807#endif
e1833e1f 6808 init_excp_970(env);
d63001d1
JM		 6809 env->dcache_line_size = 128;
6810 env->icache_line_size = 128;
a750fc0b
JM		 6811 /* Allocate hardware IRQ controller */
6812 ppc970_irq_init(env);
cf8358c8
AJ		 6813 /* Can't find information on what this should be on reset. This
6814 * value is the one used by 74xx processors. */
6815 vscr_init(env, 0x00010000);
a750fc0b 6816}
a750fc0b 6817
7856e3a4
AF		 6818POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6819{
ca5dff0a 6820 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6821 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6822
ca5dff0a 6823 dc->desc = "PowerPC 970FX (aka G5)";
7856e3a4
AF		 6824 pcc->init_proc = init_proc_970FX;
6825 pcc->check_pow = check_pow_970FX;
53116ebf
AF		 6826 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6827 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6828 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6829 PPC_FLOAT_STFIWX |
6830 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6831 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6832 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6833 PPC_64B | PPC_ALTIVEC |
6834 PPC_SEGMENT_64B | PPC_SLBI;
6835 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6836 pcc->msr_mask = 0x800000000204FF36ULL;
6837 pcc->mmu_model = POWERPC_MMU_64B;
6838 pcc->excp_model = POWERPC_EXCP_970;
6839 pcc->bus_model = PPC_FLAGS_INPUT_970;
6840 pcc->bfd_mach = bfd_mach_ppc64;
6841 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6842 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6843 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6844}
6845
2f462816
JM		 6846static int check_pow_970GX (CPUPPCState *env)
6847{
6848 if (env->spr[SPR_HID0] & 0x00600000)
6849 return 1;
6850
6851 return 0;
6852}
6853
a750fc0b
JM		 6854static void init_proc_970GX (CPUPPCState *env)
6855{
6856 gen_spr_ne_601(env);
6857 gen_spr_7xx(env);
6858 /* Time base */
6859 gen_tbl(env);
6860 /* Hardware implementation registers */
6861 /* XXX : not implemented */
6862 spr_register(env, SPR_HID0, "HID0",
6863 SPR_NOACCESS, SPR_NOACCESS,
06403421 6864 &spr_read_generic, &spr_write_clear,
d63001d1 6865 0x60000000);
a750fc0b
JM		 6866 /* XXX : not implemented */
6867 spr_register(env, SPR_HID1, "HID1",
6868 SPR_NOACCESS, SPR_NOACCESS,
6869 &spr_read_generic, &spr_write_generic,
6870 0x00000000);
6871 /* XXX : not implemented */
bd928eba 6872 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6873 SPR_NOACCESS, SPR_NOACCESS,
6874 &spr_read_generic, &spr_write_generic,
6875 0x00000000);
d63001d1
JM		 6876 /* XXX : not implemented */
6877 spr_register(env, SPR_970_HID5, "HID5",
6878 SPR_NOACCESS, SPR_NOACCESS,
6879 &spr_read_generic, &spr_write_generic,
417bf010 6880 POWERPC970_HID5_INIT);
bd928eba
JM		 6881 /* XXX : not implemented */
6882 spr_register(env, SPR_L2CR, "L2CR",
6883 SPR_NOACCESS, SPR_NOACCESS,
6884 &spr_read_generic, &spr_write_generic,
6885 0x00000000);
a750fc0b
JM		 6886 /* Memory management */
6887 /* XXX: not correct */
6888 gen_low_BATs(env);
12de9a39
JM		 6889 /* XXX : not implemented */
6890 spr_register(env, SPR_MMUCFG, "MMUCFG",
6891 SPR_NOACCESS, SPR_NOACCESS,
6892 &spr_read_generic, SPR_NOACCESS,
6893 0x00000000); /* TOFIX */
6894 /* XXX : not implemented */
6895 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000); /* TOFIX */
6899 spr_register(env, SPR_HIOR, "SPR_HIOR",
6900 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6901 &spr_read_hior, &spr_write_hior,
6902 0x00000000);
f2e63a42 6903#if !defined(CONFIG_USER_ONLY)
12de9a39 6904 env->slb_nr = 32;
f2e63a42 6905#endif
e1833e1f 6906 init_excp_970(env);
d63001d1
JM		 6907 env->dcache_line_size = 128;
6908 env->icache_line_size = 128;
a750fc0b
JM		 6909 /* Allocate hardware IRQ controller */
6910 ppc970_irq_init(env);
cf8358c8
AJ		 6911 /* Can't find information on what this should be on reset. This
6912 * value is the one used by 74xx processors. */
6913 vscr_init(env, 0x00010000);
a750fc0b 6914}
a750fc0b 6915
7856e3a4
AF		 6916POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6917{
ca5dff0a 6918 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6919 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6920
ca5dff0a 6921 dc->desc = "PowerPC 970 GX";
7856e3a4
AF		 6922 pcc->init_proc = init_proc_970GX;
6923 pcc->check_pow = check_pow_970GX;
53116ebf
AF		 6924 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6925 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6926 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6927 PPC_FLOAT_STFIWX |
6928 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6929 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6930 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6931 PPC_64B | PPC_ALTIVEC |
6932 PPC_SEGMENT_64B | PPC_SLBI;
6933 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 6934 pcc->msr_mask = 0x800000000204FF36ULL;
6935 pcc->mmu_model = POWERPC_MMU_64B;
6936 pcc->excp_model = POWERPC_EXCP_970;
6937 pcc->bus_model = PPC_FLAGS_INPUT_970;
6938 pcc->bfd_mach = bfd_mach_ppc64;
6939 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6941 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6942}
6943
2f462816
JM		 6944static int check_pow_970MP (CPUPPCState *env)
6945{
6946 if (env->spr[SPR_HID0] & 0x01C00000)
6947 return 1;
6948
6949 return 0;
6950}
6951
6952static void init_proc_970MP (CPUPPCState *env)
6953{
6954 gen_spr_ne_601(env);
6955 gen_spr_7xx(env);
6956 /* Time base */
6957 gen_tbl(env);
6958 /* Hardware implementation registers */
6959 /* XXX : not implemented */
6960 spr_register(env, SPR_HID0, "HID0",
6961 SPR_NOACCESS, SPR_NOACCESS,
6962 &spr_read_generic, &spr_write_clear,
6963 0x60000000);
6964 /* XXX : not implemented */
6965 spr_register(env, SPR_HID1, "HID1",
6966 SPR_NOACCESS, SPR_NOACCESS,
6967 &spr_read_generic, &spr_write_generic,
6968 0x00000000);
6969 /* XXX : not implemented */
bd928eba 6970 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6971 SPR_NOACCESS, SPR_NOACCESS,
6972 &spr_read_generic, &spr_write_generic,
6973 0x00000000);
6974 /* XXX : not implemented */
6975 spr_register(env, SPR_970_HID5, "HID5",
6976 SPR_NOACCESS, SPR_NOACCESS,
6977 &spr_read_generic, &spr_write_generic,
6978 POWERPC970_HID5_INIT);
bd928eba
JM		 6979 /* XXX : not implemented */
6980 spr_register(env, SPR_L2CR, "L2CR",
6981 SPR_NOACCESS, SPR_NOACCESS,
6982 &spr_read_generic, &spr_write_generic,
6983 0x00000000);
2f462816
JM		 6984 /* Memory management */
6985 /* XXX: not correct */
6986 gen_low_BATs(env);
6987 /* XXX : not implemented */
6988 spr_register(env, SPR_MMUCFG, "MMUCFG",
6989 SPR_NOACCESS, SPR_NOACCESS,
6990 &spr_read_generic, SPR_NOACCESS,
6991 0x00000000); /* TOFIX */
6992 /* XXX : not implemented */
6993 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6994 SPR_NOACCESS, SPR_NOACCESS,
6995 &spr_read_generic, &spr_write_generic,
6996 0x00000000); /* TOFIX */
6997 spr_register(env, SPR_HIOR, "SPR_HIOR",
6998 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6999 &spr_read_hior, &spr_write_hior,
7000 0x00000000);
2f462816
JM		 7001#if !defined(CONFIG_USER_ONLY)
7002 env->slb_nr = 32;
7003#endif
7004 init_excp_970(env);
7005 env->dcache_line_size = 128;
7006 env->icache_line_size = 128;
7007 /* Allocate hardware IRQ controller */
7008 ppc970_irq_init(env);
cf8358c8
AJ		 7009 /* Can't find information on what this should be on reset. This
7010 * value is the one used by 74xx processors. */
7011 vscr_init(env, 0x00010000);
2f462816
JM		 7012}
7013
7856e3a4
AF		 7014POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7015{
ca5dff0a 7016 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 7017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7018
ca5dff0a 7019 dc->desc = "PowerPC 970 MP";
7856e3a4
AF		 7020 pcc->init_proc = init_proc_970MP;
7021 pcc->check_pow = check_pow_970MP;
53116ebf
AF		 7022 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7023 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7024 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7025 PPC_FLOAT_STFIWX |
7026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7027 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7029 PPC_64B | PPC_ALTIVEC |
7030 PPC_SEGMENT_64B | PPC_SLBI;
7031 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 7032 pcc->msr_mask = 0x900000000204FF36ULL;
7033 pcc->mmu_model = POWERPC_MMU_64B;
7034 pcc->excp_model = POWERPC_EXCP_970;
7035 pcc->bus_model = PPC_FLAGS_INPUT_970;
7036 pcc->bfd_mach = bfd_mach_ppc64;
7037 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7038 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7039 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 7040}
7041
9d52e907
DG		 7042static void init_proc_POWER7 (CPUPPCState *env)
7043{
7044 gen_spr_ne_601(env);
7045 gen_spr_7xx(env);
7046 /* Time base */
7047 gen_tbl(env);
2e06214f
NW		 7048 /* Processor identification */
7049 spr_register(env, SPR_PIR, "PIR",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 &spr_read_generic, &spr_write_pir,
7052 0x00000000);
9d52e907
DG		 7053#if !defined(CONFIG_USER_ONLY)
7054 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
d67d40ea
DG		 7055 spr_register_kvm(env, SPR_PURR, "PURR",
7056 &spr_read_purr, SPR_NOACCESS,
7057 &spr_read_purr, SPR_NOACCESS,
7058 KVM_REG_PPC_PURR, 0x00000000);
7059 spr_register_kvm(env, SPR_SPURR, "SPURR",
7060 &spr_read_purr, SPR_NOACCESS,
7061 &spr_read_purr, SPR_NOACCESS,
7062 KVM_REG_PPC_SPURR, 0x00000000);
697ab892
DG		 7063 spr_register(env, SPR_CFAR, "SPR_CFAR",
7064 SPR_NOACCESS, SPR_NOACCESS,
7065 &spr_read_cfar, &spr_write_cfar,
7066 0x00000000);
d67d40ea
DG		 7067 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, &spr_write_generic,
7070 KVM_REG_PPC_DSCR, 0x00000000);
9d52e907
DG		 7071#endif /* !CONFIG_USER_ONLY */
7072 /* Memory management */
7073 /* XXX : not implemented */
7074 spr_register(env, SPR_MMUCFG, "MMUCFG",
7075 SPR_NOACCESS, SPR_NOACCESS,
7076 &spr_read_generic, SPR_NOACCESS,
7077 0x00000000); /* TOFIX */
7078 /* XXX : not implemented */
7079 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7080 SPR_NOACCESS, SPR_NOACCESS,
7081 &spr_read_generic, &spr_write_generic,
7082 0x80800000);
7083 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7084 SPR_NOACCESS, SPR_NOACCESS,
7085 &spr_read_generic, &spr_write_generic,
7086 0x80800000);
7087 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7088 &spr_read_generic, &spr_write_generic,
7089 &spr_read_generic, &spr_write_generic,
7090 0x00000000);
7091#if !defined(CONFIG_USER_ONLY)
7092 env->slb_nr = 32;
7093#endif
7094 init_excp_POWER7(env);
7095 env->dcache_line_size = 128;
7096 env->icache_line_size = 128;
7097 /* Allocate hardware IRQ controller */
7098 ppcPOWER7_irq_init(env);
7099 /* Can't find information on what this should be on reset. This
7100 * value is the one used by 74xx processors. */
7101 vscr_init(env, 0x00010000);
7102}
9d52e907 7103
7856e3a4
AF		 7104POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7105{
ca5dff0a 7106 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 7107 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7108
ca5dff0a 7109 dc->desc = "POWER7";
7856e3a4
AF		 7110 pcc->init_proc = init_proc_POWER7;
7111 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 7112 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7113 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7114 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7115 PPC_FLOAT_STFIWX |
7116 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7117 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7118 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7119 PPC_64B | PPC_ALTIVEC |
7120 PPC_SEGMENT_64B | PPC_SLBI |
7121 PPC_POPCNTB | PPC_POPCNTWD;
7122 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
ba9fd9f1
AF		 7123 pcc->msr_mask = 0x800000000204FF36ULL;
7124 pcc->mmu_model = POWERPC_MMU_2_06;
7125 pcc->excp_model = POWERPC_EXCP_POWER7;
7126 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7127 pcc->bfd_mach = bfd_mach_ppc64;
7128 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7129 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7130 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7856e3a4
AF		 7131}
7132
a750fc0b
JM		 7133static void init_proc_620 (CPUPPCState *env)
7134{
7135 gen_spr_ne_601(env);
7136 gen_spr_620(env);
7137 /* Time base */
7138 gen_tbl(env);
7139 /* Hardware implementation registers */
7140 /* XXX : not implemented */
7141 spr_register(env, SPR_HID0, "HID0",
7142 SPR_NOACCESS, SPR_NOACCESS,
7143 &spr_read_generic, &spr_write_generic,
7144 0x00000000);
7145 /* Memory management */
7146 gen_low_BATs(env);
e1833e1f 7147 init_excp_620(env);
d63001d1
JM		 7148 env->dcache_line_size = 64;
7149 env->icache_line_size = 64;
faadf50e
JM		 7150 /* Allocate hardware IRQ controller */
7151 ppc6xx_irq_init(env);
a750fc0b 7152}
7856e3a4
AF		 7153
7154POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
7155{
ca5dff0a 7156 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 7157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7158
ca5dff0a 7159 dc->desc = "PowerPC 620";
7856e3a4
AF		 7160 pcc->init_proc = init_proc_620;
7161 pcc->check_pow = check_pow_nocheck; /* Check this */
53116ebf
AF		 7162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7163 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7164 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7165 PPC_FLOAT_STFIWX |
7166 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7167 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7168 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7169 PPC_SEGMENT | PPC_EXTERN |
7170 PPC_64B | PPC_SLBI;
7171 pcc->insns_flags2 = PPC_NONE;
ba9fd9f1
AF		 7172 pcc->msr_mask = 0x800000000005FF77ULL;
7173 pcc->mmu_model = POWERPC_MMU_620;
7174 pcc->excp_model = POWERPC_EXCP_970;
7175 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7176 pcc->bfd_mach = bfd_mach_ppc64;
7177 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
7178 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 7179}
7180
a750fc0b
JM		 7181#endif /* defined (TARGET_PPC64) */
7182
fd5ed418 7183
a750fc0b 7184/*****************************************************************************/
60b14d95 7185/* Generic CPU instantiation routine */
cfe34f44 7186static void init_ppc_proc(PowerPCCPU *cpu)
a750fc0b 7187{
cfe34f44
AF		 7188 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7189 CPUPPCState *env = &cpu->env;
a750fc0b 7190#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 7191 int i;
7192
a750fc0b 7193 env->irq_inputs = NULL;
e1833e1f
JM		 7194 /* Set all exception vectors to an invalid address */
7195 for (i = 0; i < POWERPC_EXCP_NB; i++)
7196 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 7197 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 7198 env->ivor_mask = 0x00000000;
7199 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 7200 /* Default MMU definitions */
7201 env->nb_BATs = 0;
7202 env->nb_tlb = 0;
7203 env->nb_ways = 0;
1c53accc 7204 env->tlb_type = TLB_NONE;
f2e63a42 7205#endif
a750fc0b
JM		 7206 /* Register SPR common to all PowerPC implementations */
7207 gen_spr_generic(env);
7208 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 7209 /* Linux permits userspace to read PVR */
7210#if defined(CONFIG_LINUX_USER)
7211 &spr_read_generic,
7212#else
7213 SPR_NOACCESS,
7214#endif
7215 SPR_NOACCESS,
a750fc0b 7216 &spr_read_generic, SPR_NOACCESS,
cfe34f44 7217 pcc->pvr);
80d11f44 7218 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
cfe34f44
AF		 7219 if (pcc->svr != POWERPC_SVR_NONE) {
7220 if (pcc->svr & POWERPC_SVR_E500) {
80d11f44
JM		 7221 spr_register(env, SPR_E500_SVR, "SVR",
7222 SPR_NOACCESS, SPR_NOACCESS,
7223 &spr_read_generic, SPR_NOACCESS,
cfe34f44 7224 pcc->svr & ~POWERPC_SVR_E500);
80d11f44
JM		 7225 } else {
7226 spr_register(env, SPR_SVR, "SVR",
7227 SPR_NOACCESS, SPR_NOACCESS,
7228 &spr_read_generic, SPR_NOACCESS,
cfe34f44 7229 pcc->svr);
80d11f44
JM		 7230 }
7231 }
a750fc0b 7232 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
cfe34f44 7233 (*pcc->init_proc)(env);
fc1c67bc
BS		 7234#if !defined(CONFIG_USER_ONLY)
7235 env->excp_prefix = env->hreset_excp_prefix;
7236#endif
25ba3a68
JM		 7237 /* MSR bits & flags consistency checks */
7238 if (env->msr_mask & (1 << 25)) {
7239 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7240 case POWERPC_FLAG_SPE:
7241 case POWERPC_FLAG_VRE:
7242 break;
7243 default:
7244 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7245 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7246 exit(1);
7247 }
7248 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7249 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7250 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7251 exit(1);
7252 }
7253 if (env->msr_mask & (1 << 17)) {
7254 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7255 case POWERPC_FLAG_TGPR:
7256 case POWERPC_FLAG_CE:
7257 break;
7258 default:
7259 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7260 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7261 exit(1);
7262 }
7263 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7264 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7265 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7266 exit(1);
7267 }
7268 if (env->msr_mask & (1 << 10)) {
7269 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7270 POWERPC_FLAG_UBLE)) {
7271 case POWERPC_FLAG_SE:
7272 case POWERPC_FLAG_DWE:
7273 case POWERPC_FLAG_UBLE:
7274 break;
7275 default:
7276 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7277 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7278 "POWERPC_FLAG_UBLE\n");
7279 exit(1);
7280 }
7281 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7282 POWERPC_FLAG_UBLE)) {
7283 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7284 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7285 "POWERPC_FLAG_UBLE\n");
7286 exit(1);
7287 }
7288 if (env->msr_mask & (1 << 9)) {
7289 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7290 case POWERPC_FLAG_BE:
7291 case POWERPC_FLAG_DE:
7292 break;
7293 default:
7294 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7295 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7296 exit(1);
7297 }
7298 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7299 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7300 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7301 exit(1);
7302 }
7303 if (env->msr_mask & (1 << 2)) {
7304 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7305 case POWERPC_FLAG_PX:
7306 case POWERPC_FLAG_PMM:
7307 break;
7308 default:
7309 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7310 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7311 exit(1);
7312 }
7313 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7314 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7315 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7316 exit(1);
7317 }
4018bae9
JM		 7318 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7319 fprintf(stderr, "PowerPC flags inconsistency\n"
7320 "Should define the time-base and decrementer clock source\n");
7321 exit(1);
7322 }
a750fc0b 7323 /* Allocate TLBs buffer when needed */
f2e63a42 7324#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 7325 if (env->nb_tlb != 0) {
7326 int nb_tlb = env->nb_tlb;
7327 if (env->id_tlbs != 0)
7328 nb_tlb *= 2;
1c53accc
AG		 7329 switch (env->tlb_type) {
7330 case TLB_6XX:
7267c094 7331 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 7332 break;
7333 case TLB_EMB:
7267c094 7334 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 7335 break;
7336 case TLB_MAS:
7267c094 7337 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 7338 break;
7339 }
a750fc0b
JM		 7340 /* Pre-compute some useful values */
7341 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7342 }
a750fc0b
JM		 7343 if (env->irq_inputs == NULL) {
7344 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5cbdb3a3 7345 " Attempt QEMU to crash very soon !\n");
a750fc0b
JM		 7346 }
7347#endif
2f462816
JM		 7348 if (env->check_pow == NULL) {
7349 fprintf(stderr, "WARNING: no power management check handler "
7350 "registered.\n"
5cbdb3a3 7351 " Attempt QEMU to crash very soon !\n");
2f462816 7352 }
a750fc0b
JM		 7353}
7354
7355#if defined(PPC_DUMP_CPU)
7356static void dump_ppc_sprs (CPUPPCState *env)
7357{
7358 ppc_spr_t *spr;
7359#if !defined(CONFIG_USER_ONLY)
7360 uint32_t sr, sw;
7361#endif
7362 uint32_t ur, uw;
7363 int i, j, n;
7364
7365 printf("Special purpose registers:\n");
7366 for (i = 0; i < 32; i++) {
7367 for (j = 0; j < 32; j++) {
7368 n = (i << 5) | j;
7369 spr = &env->spr_cb[n];
7370 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7371 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7372#if !defined(CONFIG_USER_ONLY)
7373 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7374 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7375 if (sw || sr || uw || ur) {
7376 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7377 (i << 5) | j, (i << 5) | j, spr->name,
7378 sw ? 'w' : '-', sr ? 'r' : '-',
7379 uw ? 'w' : '-', ur ? 'r' : '-');
7380 }
7381#else
7382 if (uw || ur) {
7383 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7384 (i << 5) | j, (i << 5) | j, spr->name,
7385 uw ? 'w' : '-', ur ? 'r' : '-');
7386 }
7387#endif
7388 }
7389 }
7390 fflush(stdout);
7391 fflush(stderr);
7392}
7393#endif
7394
7395/*****************************************************************************/
7396#include <stdlib.h>
7397#include <string.h>
7398
a750fc0b
JM		 7399/* Opcode types */
7400enum {
7401 PPC_DIRECT = 0, /* Opcode routine */
7402 PPC_INDIRECT = 1, /* Indirect opcode table */
7403};
7404
7405static inline int is_indirect_opcode (void *handler)
7406{
5724753e 7407 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
a750fc0b
JM		 7408}
7409
c227f099 7410static inline opc_handler_t **ind_table(void *handler)
a750fc0b 7411{
5724753e 7412 return (opc_handler_t **)((uintptr_t)handler & ~3);
a750fc0b
JM		 7413}
7414
7415/* Instruction table creation */
7416/* Opcodes tables creation */
c227f099 7417static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 7418{
7419 int i;
7420
7421 for (i = 0; i < len; i++)
7422 table[i] = &invalid_handler;
7423}
7424
c227f099 7425static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 7426{
c227f099 7427 opc_handler_t **tmp;
a750fc0b 7428
c227f099 7429 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 7430 fill_new_table(tmp, 0x20);
5724753e 7431 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
a750fc0b
JM		 7432
7433 return 0;
7434}
7435
c227f099
AL		 7436static int insert_in_table (opc_handler_t **table, unsigned char idx,
7437 opc_handler_t *handler)
a750fc0b
JM		 7438{
7439 if (table[idx] != &invalid_handler)
7440 return -1;
7441 table[idx] = handler;
7442
7443 return 0;
7444}
7445
c227f099
AL		 7446static int register_direct_insn (opc_handler_t **ppc_opcodes,
7447 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 7448{
7449 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7450 printf("*** ERROR: opcode %02x already assigned in main "
7451 "opcode table\n", idx);
4c1b1bfe
JM		 7452#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7453 printf(" Registered handler '%s' - new handler '%s'\n",
7454 ppc_opcodes[idx]->oname, handler->oname);
7455#endif
a750fc0b
JM		 7456 return -1;
7457 }
7458
7459 return 0;
7460}
7461
c227f099 7462static int register_ind_in_table (opc_handler_t **table,
a750fc0b 7463 unsigned char idx1, unsigned char idx2,
c227f099 7464 opc_handler_t *handler)
a750fc0b
JM		 7465{
7466 if (table[idx1] == &invalid_handler) {
7467 if (create_new_table(table, idx1) < 0) {
7468 printf("*** ERROR: unable to create indirect table "
7469 "idx=%02x\n", idx1);
7470 return -1;
7471 }
7472 } else {
7473 if (!is_indirect_opcode(table[idx1])) {
7474 printf("*** ERROR: idx %02x already assigned to a direct "
7475 "opcode\n", idx1);
4c1b1bfe
JM		 7476#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7477 printf(" Registered handler '%s' - new handler '%s'\n",
7478 ind_table(table[idx1])[idx2]->oname, handler->oname);
7479#endif
a750fc0b
JM		 7480 return -1;
7481 }
3a607854 7482 }
a750fc0b
JM		 7483 if (handler != NULL &&
7484 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7485 printf("*** ERROR: opcode %02x already assigned in "
7486 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 7487#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7488 printf(" Registered handler '%s' - new handler '%s'\n",
7489 ind_table(table[idx1])[idx2]->oname, handler->oname);
7490#endif
a750fc0b 7491 return -1;
3a607854 7492 }
a750fc0b
JM		 7493
7494 return 0;
7495}
7496
c227f099 7497static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 7498 unsigned char idx1, unsigned char idx2,
c227f099 7499 opc_handler_t *handler)
a750fc0b
JM		 7500{
7501 int ret;
7502
7503 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7504
7505 return ret;
7506}
7507
c227f099 7508static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 7509 unsigned char idx1, unsigned char idx2,
c227f099 7510 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 7511{
7512 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7513 printf("*** ERROR: unable to join indirect table idx "
7514 "[%02x-%02x]\n", idx1, idx2);
7515 return -1;
7516 }
7517 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7518 handler) < 0) {
7519 printf("*** ERROR: unable to insert opcode "
7520 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7521 return -1;
7522 }
7523
7524 return 0;
7525}
7526
c227f099 7527static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 7528{
7529 if (insn->opc2 != 0xFF) {
7530 if (insn->opc3 != 0xFF) {
7531 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7532 insn->opc3, &insn->handler) < 0)
7533 return -1;
7534 } else {
7535 if (register_ind_insn(ppc_opcodes, insn->opc1,
7536 insn->opc2, &insn->handler) < 0)
7537 return -1;
7538 }
7539 } else {
7540 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7541 return -1;
7542 }
7543
7544 return 0;
7545}
7546
c227f099 7547static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 7548{
7549 int i, count, tmp;
7550
7551 for (i = 0, count = 0; i < len; i++) {
7552 /* Consistency fixup */
7553 if (table[i] == NULL)
7554 table[i] = &invalid_handler;
7555 if (table[i] != &invalid_handler) {
7556 if (is_indirect_opcode(table[i])) {
c227f099 7557 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 7558 if (tmp == 0) {
7559 free(table[i]);
7560 table[i] = &invalid_handler;
7561 } else {
7562 count++;
7563 }
7564 } else {
7565 count++;
7566 }
7567 }
7568 }
7569
7570 return count;
7571}
7572
c227f099 7573static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 7574{
c227f099 7575 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 7576 printf("*** WARNING: no opcode defined !\n");
7577}
7578
7579/*****************************************************************************/
2985b86b 7580static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
a750fc0b 7581{
2985b86b
AF		 7582 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7583 CPUPPCState *env = &cpu->env;
c227f099 7584 opcode_t *opc;
a750fc0b
JM		 7585
7586 fill_new_table(env->opcodes, 0x40);
5c55ff99 7587 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
cfe34f44
AF		 7588 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7589 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
a750fc0b 7590 if (register_insn(env->opcodes, opc) < 0) {
2985b86b 7591 error_setg(errp, "ERROR initializing PowerPC instruction "
312fd5f2 7592 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
2985b86b
AF		 7593 opc->opc3);
7594 return;
a750fc0b
JM		 7595 }
7596 }
7597 }
c227f099 7598 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 7599 fflush(stdout);
7600 fflush(stderr);
a750fc0b
JM		 7601}
7602
7603#if defined(PPC_DUMP_CPU)
25ba3a68 7604static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 7605{
c227f099 7606 opc_handler_t **table, *handler;
b55266b5 7607 const char *p, *q;
a750fc0b
JM		 7608 uint8_t opc1, opc2, opc3;
7609
7610 printf("Instructions set:\n");
7611 /* opc1 is 6 bits long */
7612 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7613 table = env->opcodes;
7614 handler = table[opc1];
7615 if (is_indirect_opcode(handler)) {
7616 /* opc2 is 5 bits long */
7617 for (opc2 = 0; opc2 < 0x20; opc2++) {
7618 table = env->opcodes;
7619 handler = env->opcodes[opc1];
7620 table = ind_table(handler);
7621 handler = table[opc2];
7622 if (is_indirect_opcode(handler)) {
7623 table = ind_table(handler);
7624 /* opc3 is 5 bits long */
7625 for (opc3 = 0; opc3 < 0x20; opc3++) {
7626 handler = table[opc3];
7627 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 7628 /* Special hack to properly dump SPE insns */
7629 p = strchr(handler->oname, '_');
7630 if (p == NULL) {
7631 printf("INSN: %02x %02x %02x (%02d %04d) : "
7632 "%s\n",
7633 opc1, opc2, opc3, opc1,
7634 (opc3 << 5) | opc2,
7635 handler->oname);
7636 } else {
7637 q = "speundef";
7638 if ((p - handler->oname) != strlen(q) ||
7639 memcmp(handler->oname, q, strlen(q)) != 0) {
7640 /* First instruction */
7641 printf("INSN: %02x %02x %02x (%02d %04d) : "
7642 "%.*s\n",
7643 opc1, opc2 << 1, opc3, opc1,
7644 (opc3 << 6) | (opc2 << 1),
7645 (int)(p - handler->oname),
7646 handler->oname);
7647 }
7648 if (strcmp(p + 1, q) != 0) {
7649 /* Second instruction */
7650 printf("INSN: %02x %02x %02x (%02d %04d) : "
7651 "%s\n",
7652 opc1, (opc2 << 1) | 1, opc3, opc1,
7653 (opc3 << 6) | (opc2 << 1) | 1,
7654 p + 1);
7655 }
7656 }
a750fc0b
JM		 7657 }
7658 }
7659 } else {
7660 if (handler->handler != &gen_invalid) {
7661 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7662 opc1, opc2, opc1, opc2, handler->oname);
7663 }
7664 }
7665 }
7666 } else {
7667 if (handler->handler != &gen_invalid) {
7668 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7669 opc1, opc1, handler->oname);
7670 }
7671 }
7672 }
7673}
3a607854 7674#endif
a750fc0b 7675
1328c2bf 7676static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 7677{
7678 if (n < 32) {
7679 stfq_p(mem_buf, env->fpr[n]);
7680 return 8;
7681 }
7682 if (n == 32) {
5a576fb3 7683 stl_p(mem_buf, env->fpscr);
24951522
AJ		 7684 return 4;
7685 }
7686 return 0;
7687}
7688
1328c2bf 7689static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 7690{
7691 if (n < 32) {
7692 env->fpr[n] = ldfq_p(mem_buf);
7693 return 8;
7694 }
7695 if (n == 32) {
7696 /* FPSCR not implemented */
7697 return 4;
7698 }
7699 return 0;
7700}
7701
1328c2bf 7702static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 7703{
7704 if (n < 32) {
e2542fe2 7705#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 7706 stq_p(mem_buf, env->avr[n].u64[0]);
7707 stq_p(mem_buf+8, env->avr[n].u64[1]);
7708#else
7709 stq_p(mem_buf, env->avr[n].u64[1]);
7710 stq_p(mem_buf+8, env->avr[n].u64[0]);
7711#endif
7712 return 16;
7713 }
70976a79 7714 if (n == 32) {
b4f8d821
AJ		 7715 stl_p(mem_buf, env->vscr);
7716 return 4;
7717 }
70976a79 7718 if (n == 33) {
b4f8d821
AJ		 7719 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7720 return 4;
7721 }
7722 return 0;
7723}
7724
1328c2bf 7725static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 7726{
7727 if (n < 32) {
e2542fe2 7728#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 7729 env->avr[n].u64[0] = ldq_p(mem_buf);
7730 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7731#else
7732 env->avr[n].u64[1] = ldq_p(mem_buf);
7733 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7734#endif
7735 return 16;
7736 }
70976a79 7737 if (n == 32) {
b4f8d821
AJ		 7738 env->vscr = ldl_p(mem_buf);
7739 return 4;
7740 }
70976a79 7741 if (n == 33) {
b4f8d821
AJ		 7742 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7743 return 4;
7744 }
7745 return 0;
7746}
7747
1328c2bf 7748static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 7749{
7750 if (n < 32) {
7751#if defined(TARGET_PPC64)
7752 stl_p(mem_buf, env->gpr[n] >> 32);
7753#else
7754 stl_p(mem_buf, env->gprh[n]);
7755#endif
7756 return 4;
7757 }
70976a79 7758 if (n == 32) {
688890f7
AJ		 7759 stq_p(mem_buf, env->spe_acc);
7760 return 8;
7761 }
70976a79 7762 if (n == 33) {
d34defbc 7763 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 7764 return 4;
7765 }
7766 return 0;
7767}
7768
1328c2bf 7769static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 7770{
7771 if (n < 32) {
7772#if defined(TARGET_PPC64)
7773 target_ulong lo = (uint32_t)env->gpr[n];
7774 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7775 env->gpr[n] = lo | hi;
7776#else
7777 env->gprh[n] = ldl_p(mem_buf);
7778#endif
7779 return 4;
7780 }
70976a79 7781 if (n == 32) {
688890f7
AJ		 7782 env->spe_acc = ldq_p(mem_buf);
7783 return 8;
7784 }
70976a79 7785 if (n == 33) {
d34defbc 7786 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 7787 return 4;
7788 }
7789 return 0;
7790}
7791
55e5c285 7792static int ppc_fixup_cpu(PowerPCCPU *cpu)
12b1143b 7793{
55e5c285
AF		 7794 CPUPPCState *env = &cpu->env;
7795
12b1143b
DG		 7796 /* TCG doesn't (yet) emulate some groups of instructions that
7797 * are implemented on some otherwise supported CPUs (e.g. VSX
7798 * and decimal floating point instructions on POWER7). We
7799 * remove unsupported instruction groups from the cpu state's
7800 * instruction masks and hope the guest can cope. For at
7801 * least the pseries machine, the unavailability of these
7802 * instructions can be advertised to the guest via the device
7803 * tree. */
7804 if ((env->insns_flags & ~PPC_TCG_INSNS)
7805 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7806 fprintf(stderr, "Warning: Disabling some instructions which are not "
7807 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7808 env->insns_flags & ~PPC_TCG_INSNS,
7809 env->insns_flags2 & ~PPC_TCG_INSNS2);
7810 }
7811 env->insns_flags &= PPC_TCG_INSNS;
7812 env->insns_flags2 &= PPC_TCG_INSNS2;
7813 return 0;
7814}
7815
4776ce60 7816static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
a750fc0b 7817{
4776ce60 7818 PowerPCCPU *cpu = POWERPC_CPU(dev);
2985b86b
AF		 7819 CPUPPCState *env = &cpu->env;
7820 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2985b86b 7821 Error *local_err = NULL;
fe828a4d
MQ		 7822#if !defined(CONFIG_USER_ONLY)
7823 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7824#endif
7825
7826#if !defined(CONFIG_USER_ONLY)
7827 if (smp_threads > max_smt) {
5e95acc8
AF		 7828 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7829 max_smt, kvm_enabled() ? "KVM" : "TCG");
7830 return;
fe828a4d
MQ		 7831 }
7832#endif
4656e1f0 7833
12b1143b 7834 if (kvm_enabled()) {
55e5c285 7835 if (kvmppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 7836 error_setg(errp, "Unable to virtualize selected CPU with KVM");
7837 return;
12b1143b
DG		 7838 }
7839 } else {
55e5c285 7840 if (ppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 7841 error_setg(errp, "Unable to emulate selected CPU with TCG");
7842 return;
12b1143b
DG		 7843 }
7844 }
7845
4d7fb187
AF		 7846#if defined(TARGET_PPCEMB)
7847 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
7848 error_setg(errp, "CPU does not possess a BookE MMU. "
7849 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7850 "or choose another CPU model.");
7851 return;
7852 }
7853#endif
7854
2985b86b
AF		 7855 create_ppc_opcodes(cpu, &local_err);
7856 if (local_err != NULL) {
7857 error_propagate(errp, local_err);
7858 return;
7859 }
cfe34f44 7860 init_ppc_proc(cpu);
24951522 7861
cfe34f44 7862 if (pcc->insns_flags & PPC_FLOAT) {
24951522
AJ		 7863 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
7864 33, "power-fpu.xml", 0);
7865 }
cfe34f44 7866 if (pcc->insns_flags & PPC_ALTIVEC) {
b4f8d821
AJ		 7867 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
7868 34, "power-altivec.xml", 0);
7869 }
cfe34f44 7870 if (pcc->insns_flags & PPC_SPE) {
688890f7
AJ		 7871 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
7872 34, "power-spe.xml", 0);
7873 }
7874
2985b86b
AF		 7875 qemu_init_vcpu(env);
7876
4776ce60
AF		 7877 pcc->parent_realize(dev, errp);
7878
a750fc0b 7879#if defined(PPC_DUMP_CPU)
3a607854 7880 {
b55266b5 7881 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 7882 switch (env->mmu_model) {
7883 case POWERPC_MMU_32B:
7884 mmu_model = "PowerPC 32";
7885 break;
a750fc0b
JM		 7886 case POWERPC_MMU_SOFT_6xx:
7887 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7888 break;
7889 case POWERPC_MMU_SOFT_74xx:
7890 mmu_model = "PowerPC 74xx with software driven TLBs";
7891 break;
7892 case POWERPC_MMU_SOFT_4xx:
7893 mmu_model = "PowerPC 4xx with software driven TLBs";
7894 break;
7895 case POWERPC_MMU_SOFT_4xx_Z:
7896 mmu_model = "PowerPC 4xx with software driven TLBs "
7897 "and zones protections";
7898 break;
b4095fed
JM		 7899 case POWERPC_MMU_REAL:
7900 mmu_model = "PowerPC real mode only";
7901 break;
7902 case POWERPC_MMU_MPC8xx:
7903 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 7904 break;
7905 case POWERPC_MMU_BOOKE:
7906 mmu_model = "PowerPC BookE";
7907 break;
01662f3e
AG		 7908 case POWERPC_MMU_BOOKE206:
7909 mmu_model = "PowerPC BookE 2.06";
a750fc0b 7910 break;
b4095fed
JM		 7911 case POWERPC_MMU_601:
7912 mmu_model = "PowerPC 601";
7913 break;
00af685f
JM		 7914#if defined (TARGET_PPC64)
7915 case POWERPC_MMU_64B:
7916 mmu_model = "PowerPC 64";
7917 break;
add78955
JM		 7918 case POWERPC_MMU_620:
7919 mmu_model = "PowerPC 620";
7920 break;
00af685f 7921#endif
a750fc0b
JM		 7922 default:
7923 mmu_model = "Unknown or invalid";
7924 break;
7925 }
7926 switch (env->excp_model) {
7927 case POWERPC_EXCP_STD:
7928 excp_model = "PowerPC";
7929 break;
7930 case POWERPC_EXCP_40x:
7931 excp_model = "PowerPC 40x";
7932 break;
7933 case POWERPC_EXCP_601:
7934 excp_model = "PowerPC 601";
7935 break;
7936 case POWERPC_EXCP_602:
7937 excp_model = "PowerPC 602";
7938 break;
7939 case POWERPC_EXCP_603:
7940 excp_model = "PowerPC 603";
7941 break;
7942 case POWERPC_EXCP_603E:
7943 excp_model = "PowerPC 603e";
7944 break;
7945 case POWERPC_EXCP_604:
7946 excp_model = "PowerPC 604";
7947 break;
7948 case POWERPC_EXCP_7x0:
7949 excp_model = "PowerPC 740/750";
7950 break;
7951 case POWERPC_EXCP_7x5:
7952 excp_model = "PowerPC 745/755";
7953 break;
7954 case POWERPC_EXCP_74xx:
7955 excp_model = "PowerPC 74xx";
7956 break;
a750fc0b
JM		 7957 case POWERPC_EXCP_BOOKE:
7958 excp_model = "PowerPC BookE";
7959 break;
00af685f
JM		 7960#if defined (TARGET_PPC64)
7961 case POWERPC_EXCP_970:
7962 excp_model = "PowerPC 970";
7963 break;
7964#endif
a750fc0b
JM		 7965 default:
7966 excp_model = "Unknown or invalid";
7967 break;
7968 }
7969 switch (env->bus_model) {
7970 case PPC_FLAGS_INPUT_6xx:
7971 bus_model = "PowerPC 6xx";
7972 break;
7973 case PPC_FLAGS_INPUT_BookE:
7974 bus_model = "PowerPC BookE";
7975 break;
7976 case PPC_FLAGS_INPUT_405:
7977 bus_model = "PowerPC 405";
7978 break;
a750fc0b
JM		 7979 case PPC_FLAGS_INPUT_401:
7980 bus_model = "PowerPC 401/403";
7981 break;
b4095fed
JM		 7982 case PPC_FLAGS_INPUT_RCPU:
7983 bus_model = "RCPU / MPC8xx";
7984 break;
00af685f
JM		 7985#if defined (TARGET_PPC64)
7986 case PPC_FLAGS_INPUT_970:
7987 bus_model = "PowerPC 970";
7988 break;
7989#endif
a750fc0b
JM		 7990 default:
7991 bus_model = "Unknown or invalid";
7992 break;
7993 }
7994 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
7995 " MMU model : %s\n",
cfe34f44 7996 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
f2e63a42 7997#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 7998 if (env->tlb != NULL) {
7999 printf(" %d %s TLB in %d ways\n",
8000 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8001 env->nb_ways);
8002 }
f2e63a42 8003#endif
a750fc0b
JM		 8004 printf(" Exceptions model : %s\n"
8005 " Bus model : %s\n",
8006 excp_model, bus_model);
25ba3a68
JM		 8007 printf(" MSR features :\n");
8008 if (env->flags & POWERPC_FLAG_SPE)
8009 printf(" signal processing engine enable"
8010 "\n");
8011 else if (env->flags & POWERPC_FLAG_VRE)
8012 printf(" vector processor enable\n");
8013 if (env->flags & POWERPC_FLAG_TGPR)
8014 printf(" temporary GPRs\n");
8015 else if (env->flags & POWERPC_FLAG_CE)
8016 printf(" critical input enable\n");
8017 if (env->flags & POWERPC_FLAG_SE)
8018 printf(" single-step trace mode\n");
8019 else if (env->flags & POWERPC_FLAG_DWE)
8020 printf(" debug wait enable\n");
8021 else if (env->flags & POWERPC_FLAG_UBLE)
8022 printf(" user BTB lock enable\n");
8023 if (env->flags & POWERPC_FLAG_BE)
8024 printf(" branch-step trace mode\n");
8025 else if (env->flags & POWERPC_FLAG_DE)
8026 printf(" debug interrupt enable\n");
8027 if (env->flags & POWERPC_FLAG_PX)
8028 printf(" inclusive protection\n");
8029 else if (env->flags & POWERPC_FLAG_PMM)
8030 printf(" performance monitor mark\n");
8031 if (env->flags == POWERPC_FLAG_NONE)
8032 printf(" none\n");
4018bae9
JM		 8033 printf(" Time-base/decrementer clock source: %s\n",
8034 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 8035 }
8036 dump_ppc_insns(env);
8037 dump_ppc_sprs(env);
8038 fflush(stdout);
3a607854 8039#endif
a750fc0b 8040}
3fc6c082 8041
2985b86b 8042static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
f0ad8c34 8043{
2985b86b
AF		 8044 ObjectClass *oc = (ObjectClass *)a;
8045 uint32_t pvr = *(uint32_t *)b;
8046 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8047
8048 /* -cpu host does a PVR lookup during construction */
8049 if (unlikely(strcmp(object_class_get_name(oc),
8050 TYPE_HOST_POWERPC_CPU) == 0)) {
8051 return -1;
f0ad8c34 8052 }
f0ad8c34 8053
4d7fb187
AF		 8054#if defined(TARGET_PPCEMB)
8055 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8056 return -1;
8057 }
8058#endif
8059
cfe34f44 8060 return pcc->pvr == pvr ? 0 : -1;
f0ad8c34
AG		 8061}
8062
2985b86b 8063PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
3fc6c082 8064{
2985b86b
AF		 8065 GSList *list, *item;
8066 PowerPCCPUClass *pcc = NULL;
be40edcd 8067
2985b86b
AF		 8068 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8069 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8070 if (item != NULL) {
8071 pcc = POWERPC_CPU_CLASS(item->data);
3fc6c082 8072 }
2985b86b
AF		 8073 g_slist_free(list);
8074
8075 return pcc;
8076}
8077
8078static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8079{
8080 ObjectClass *oc = (ObjectClass *)a;
8081 const char *name = b;
4d7fb187
AF		 8082#if defined(TARGET_PPCEMB)
8083 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8084#endif
ee4e83ed 8085
2985b86b 8086 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
4d7fb187
AF		 8087#if defined(TARGET_PPCEMB)
8088 pcc->mmu_model == POWERPC_MMU_BOOKE &&
8089#endif
2985b86b
AF		 8090 strcmp(object_class_get_name(oc) + strlen(name),
8091 "-" TYPE_POWERPC_CPU) == 0) {
8092 return 0;
8093 }
8094 return -1;
3fc6c082
FB		 8095}
8096
ee4e83ed 8097#include <ctype.h>
3fc6c082 8098
2985b86b 8099static ObjectClass *ppc_cpu_class_by_name(const char *name)
ee4e83ed 8100{
2985b86b
AF		 8101 GSList *list, *item;
8102 ObjectClass *ret = NULL;
b55266b5 8103 const char *p;
2985b86b 8104 int i, len;
ee4e83ed
JM		 8105
8106 /* Check if the given name is a PVR */
8107 len = strlen(name);
8108 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8109 p = name + 2;
8110 goto check_pvr;
8111 } else if (len == 8) {
8112 p = name;
8113 check_pvr:
8114 for (i = 0; i < 8; i++) {
cd390083 8115 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 8116 break;
8117 }
2985b86b
AF		 8118 if (i == 8) {
8119 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8120 return ret;
f0ad8c34 8121 }
2985b86b 8122 }
f0ad8c34 8123
e9a96075 8124 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
fd5ed418
AF		 8125 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8126 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
8127 }
8128 }
8129
2985b86b
AF		 8130 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8131 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8132 if (item != NULL) {
8133 ret = OBJECT_CLASS(item->data);
3fc6c082 8134 }
2985b86b 8135 g_slist_free(list);
ee4e83ed
JM		 8136
8137 return ret;
3fc6c082
FB		 8138}
8139
2985b86b 8140PowerPCCPU *cpu_ppc_init(const char *cpu_model)
3fc6c082 8141{
2985b86b
AF		 8142 PowerPCCPU *cpu;
8143 CPUPPCState *env;
8144 ObjectClass *oc;
8145 Error *err = NULL;
3fc6c082 8146
2985b86b
AF		 8147 oc = ppc_cpu_class_by_name(cpu_model);
8148 if (oc == NULL) {
8149 return NULL;
8150 }
f0ad8c34 8151
2985b86b
AF		 8152 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
8153 env = &cpu->env;
2985b86b
AF		 8154 env->cpu_model_str = cpu_model;
8155
4776ce60 8156 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
2985b86b
AF		 8157 if (err != NULL) {
8158 fprintf(stderr, "%s\n", error_get_pretty(err));
8159 error_free(err);
5c099537 8160 object_unref(OBJECT(cpu));
2985b86b
AF		 8161 return NULL;
8162 }
8163
8164 return cpu;
8165}
8166
8167/* Sort by PVR, ordering special case "host" last. */
8168static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8169{
8170 ObjectClass *oc_a = (ObjectClass *)a;
8171 ObjectClass *oc_b = (ObjectClass *)b;
8172 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8173 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8174 const char *name_a = object_class_get_name(oc_a);
8175 const char *name_b = object_class_get_name(oc_b);
8176
8177 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8178 return 1;
8179 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8180 return -1;
8181 } else {
8182 /* Avoid an integer overflow during subtraction */
cfe34f44 8183 if (pcc_a->pvr < pcc_b->pvr) {
2985b86b 8184 return -1;
cfe34f44 8185 } else if (pcc_a->pvr > pcc_b->pvr) {
2985b86b
AF		 8186 return 1;
8187 } else {
8188 return 0;
8189 }
8190 }
8191}
8192
8193static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8194{
8195 ObjectClass *oc = data;
8196 CPUListState *s = user_data;
8197 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
de400129
AF		 8198 const char *typename = object_class_get_name(oc);
8199 char *name;
55d3d1a4 8200 int i;
2985b86b 8201
4d7fb187
AF		 8202#if defined(TARGET_PPCEMB)
8203 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8204 return;
8205 }
8206#endif
5ba4576b
AF		 8207 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8208 return;
8209 }
4d7fb187 8210
de400129
AF		 8211 name = g_strndup(typename,
8212 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b 8213 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
cfe34f44 8214 name, pcc->pvr);
e9a96075 8215 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
55d3d1a4
AF		 8216 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8217 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8218
8219 if (alias_oc != oc) {
8220 continue;
8221 }
8222 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8223 alias->alias, name);
8224 }
de400129 8225 g_free(name);
2985b86b
AF		 8226}
8227
8228void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8229{
8230 CPUListState s = {
8231 .file = f,
8232 .cpu_fprintf = cpu_fprintf,
8233 };
8234 GSList *list;
8235
8236 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8237 list = g_slist_sort(list, ppc_cpu_list_compare);
8238 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8239 g_slist_free(list);
fd5ed418 8240
5ba4576b
AF		 8241#ifdef CONFIG_KVM
8242 cpu_fprintf(f, "\n");
8243 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8244#endif
2985b86b
AF		 8245}
8246
8247static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8248{
8249 ObjectClass *oc = data;
8250 CpuDefinitionInfoList **first = user_data;
de400129 8251 const char *typename;
2985b86b
AF		 8252 CpuDefinitionInfoList *entry;
8253 CpuDefinitionInfo *info;
4d7fb187
AF		 8254#if defined(TARGET_PPCEMB)
8255 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8256
8257 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8258 return;
8259 }
8260#endif
2985b86b 8261
de400129 8262 typename = object_class_get_name(oc);
2985b86b 8263 info = g_malloc0(sizeof(*info));
de400129
AF		 8264 info->name = g_strndup(typename,
8265 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b
AF		 8266
8267 entry = g_malloc0(sizeof(*entry));
8268 entry->value = info;
8269 entry->next = *first;
8270 *first = entry;
3fc6c082 8271}
1d0cb67d 8272
76b64a7a 8273CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
70b7660a
AL		 8274{
8275 CpuDefinitionInfoList *cpu_list = NULL;
2985b86b 8276 GSList *list;
35e21d3f 8277 int i;
70b7660a 8278
2985b86b
AF		 8279 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8280 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8281 g_slist_free(list);
70b7660a 8282
e9a96075 8283 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
35e21d3f
AF		 8284 const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8285 ObjectClass *oc;
8286 CpuDefinitionInfoList *entry;
8287 CpuDefinitionInfo *info;
8288
8289 oc = ppc_cpu_class_by_name(alias->model);
8290 if (oc == NULL) {
8291 continue;
8292 }
8293
8294 info = g_malloc0(sizeof(*info));
8295 info->name = g_strdup(alias->alias);
8296
8297 entry = g_malloc0(sizeof(*entry));
8298 entry->value = info;
8299 entry->next = cpu_list;
8300 cpu_list = entry;
8301 }
8302
2985b86b
AF		 8303 return cpu_list;
8304}
70b7660a 8305
1d0cb67d
AF		 8306/* CPUClass::reset() */
8307static void ppc_cpu_reset(CPUState *s)
8308{
8309 PowerPCCPU *cpu = POWERPC_CPU(s);
8310 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8311 CPUPPCState *env = &cpu->env;
a1389542
AF		 8312 target_ulong msr;
8313
8314 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 8315 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
a1389542
AF		 8316 log_cpu_state(env, 0);
8317 }
1d0cb67d
AF		 8318
8319 pcc->parent_reset(s);
8320
a1389542
AF		 8321 msr = (target_ulong)0;
8322 if (0) {
8323 /* XXX: find a suitable condition to enable the hypervisor mode */
8324 msr |= (target_ulong)MSR_HVB;
8325 }
8326 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8327 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8328 msr |= (target_ulong)1 << MSR_EP;
8329#if defined(DO_SINGLE_STEP) && 0
8330 /* Single step trace mode */
8331 msr |= (target_ulong)1 << MSR_SE;
8332 msr |= (target_ulong)1 << MSR_BE;
8333#endif
8334#if defined(CONFIG_USER_ONLY)
8335 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8336 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8337 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8338 msr |= (target_ulong)1 << MSR_PR;
8339#else
8340 env->excp_prefix = env->hreset_excp_prefix;
8341 env->nip = env->hreset_vector | env->excp_prefix;
8342 if (env->mmu_model != POWERPC_MMU_REAL) {
8343 ppc_tlb_invalidate_all(env);
8344 }
8345#endif
8346 env->msr = msr & env->msr_mask;
8347#if defined(TARGET_PPC64)
8348 if (env->mmu_model & POWERPC_MMU_64) {
8349 env->msr |= (1ULL << MSR_SF);
8350 }
8351#endif
8352 hreg_compute_hflags(env);
8353 env->reserve_addr = (target_ulong)-1ULL;
8354 /* Be sure no exception or interrupt is pending */
8355 env->pending_interrupts = 0;
8356 env->exception_index = POWERPC_EXCP_NONE;
8357 env->error_code = 0;
2b15811c
DG		 8358
8359#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1bfb37d1
DG		 8360 env->vpa_addr = 0;
8361 env->slb_shadow_addr = 0;
8362 env->slb_shadow_size = 0;
8363 env->dtl_addr = 0;
2b15811c
DG		 8364 env->dtl_size = 0;
8365#endif /* TARGET_PPC64 */
8366
a1389542
AF		 8367 /* Flush all TLBs */
8368 tlb_flush(env, 1);
1d0cb67d
AF		 8369}
8370
6cca7ad6
AF		 8371static void ppc_cpu_initfn(Object *obj)
8372{
c05efcb1 8373 CPUState *cs = CPU(obj);
6cca7ad6 8374 PowerPCCPU *cpu = POWERPC_CPU(obj);
2985b86b 8375 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6cca7ad6
AF		 8376 CPUPPCState *env = &cpu->env;
8377
c05efcb1 8378 cs->env_ptr = env;
6cca7ad6 8379 cpu_exec_init(env);
2985b86b 8380
cfe34f44
AF		 8381 env->msr_mask = pcc->msr_mask;
8382 env->mmu_model = pcc->mmu_model;
8383 env->excp_model = pcc->excp_model;
8384 env->bus_model = pcc->bus_model;
8385 env->insns_flags = pcc->insns_flags;
8386 env->insns_flags2 = pcc->insns_flags2;
8387 env->flags = pcc->flags;
8388 env->bfd_mach = pcc->bfd_mach;
8389 env->check_pow = pcc->check_pow;
2985b86b
AF		 8390
8391#if defined(TARGET_PPC64)
cfe34f44
AF		 8392 if (pcc->sps) {
8393 env->sps = *pcc->sps;
2985b86b
AF		 8394 } else if (env->mmu_model & POWERPC_MMU_64) {
8395 /* Use default sets of page sizes */
8396 static const struct ppc_segment_page_sizes defsps = {
8397 .sps = {
8398 { .page_shift = 12, /* 4K */
8399 .slb_enc = 0,
8400 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8401 },
8402 { .page_shift = 24, /* 16M */
8403 .slb_enc = 0x100,
8404 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8405 },
8406 },
8407 };
8408 env->sps = defsps;
8409 }
8410#endif /* defined(TARGET_PPC64) */
60925d26
AF		 8411
8412 if (tcg_enabled()) {
8413 ppc_translate_init();
8414 }
6cca7ad6
AF		 8415}
8416
1d0cb67d
AF		 8417static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8418{
8419 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8420 CPUClass *cc = CPU_CLASS(oc);
4776ce60
AF		 8421 DeviceClass *dc = DEVICE_CLASS(oc);
8422
8423 pcc->parent_realize = dc->realize;
8424 dc->realize = ppc_cpu_realizefn;
1d0cb67d
AF		 8425
8426 pcc->parent_reset = cc->reset;
8427 cc->reset = ppc_cpu_reset;
2b8c2754
AF		 8428
8429 cc->class_by_name = ppc_cpu_class_by_name;
97a8ea5a 8430 cc->do_interrupt = ppc_cpu_do_interrupt;
1d0cb67d
AF		 8431}
8432
8433static const TypeInfo ppc_cpu_type_info = {
8434 .name = TYPE_POWERPC_CPU,
8435 .parent = TYPE_CPU,
8436 .instance_size = sizeof(PowerPCCPU),
6cca7ad6 8437 .instance_init = ppc_cpu_initfn,
2985b86b 8438 .abstract = true,
1d0cb67d
AF		 8439 .class_size = sizeof(PowerPCCPUClass),
8440 .class_init = ppc_cpu_class_init,
8441};
8442
8443static void ppc_cpu_register_types(void)
8444{
8445 type_register_static(&ppc_cpu_type_info);
8446}
8447
8448type_init(ppc_cpu_register_types)
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