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3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26//#define PPC_DUMP_CPU
27//#define PPC_DEBUG_SPR
28
29struct ppc_def_t {
30 const unsigned char *name;
31 uint32_t pvr;
32 uint32_t pvr_mask;
0487d6a8 33 uint64_t insns_flags;
3fc6c082
FB		 34 uint32_t flags;
35 uint64_t msr_mask;
36};
37
e9df014c
JM		 38/* For user-mode emulation, we don't emulate any IRQ controller */
39#if defined(CONFIG_USER_ONLY)
40#define PPC_IRQ_INIT_FN(name) \
41static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42{ \
43}
44#else
45#define PPC_IRQ_INIT_FN(name) \
46void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47#endif
24be5ae3 48PPC_IRQ_INIT_FN(405);
e9df014c
JM		 49PPC_IRQ_INIT_FN(6xx);
50
3fc6c082
FB		 51/* Generic callbacks:
52 * do nothing but store/retrieve spr value
53 */
54static void spr_read_generic (void *opaque, int sprn)
55{
56 gen_op_load_spr(sprn);
57}
58
59static void spr_write_generic (void *opaque, int sprn)
60{
61 gen_op_store_spr(sprn);
62}
63
76a66253 64/* SPR common to all PowerPC */
3fc6c082
FB		 65/* XER */
66static void spr_read_xer (void *opaque, int sprn)
67{
68 gen_op_load_xer();
69}
70
71static void spr_write_xer (void *opaque, int sprn)
72{
73 gen_op_store_xer();
74}
75
76/* LR */
77static void spr_read_lr (void *opaque, int sprn)
78{
79 gen_op_load_lr();
80}
81
82static void spr_write_lr (void *opaque, int sprn)
83{
84 gen_op_store_lr();
85}
86
87/* CTR */
88static void spr_read_ctr (void *opaque, int sprn)
89{
90 gen_op_load_ctr();
91}
92
93static void spr_write_ctr (void *opaque, int sprn)
94{
95 gen_op_store_ctr();
96}
97
98/* User read access to SPR */
99/* USPRx */
100/* UMMCRx */
101/* UPMCx */
102/* USIA */
103/* UDECR */
104static void spr_read_ureg (void *opaque, int sprn)
105{
106 gen_op_load_spr(sprn + 0x10);
107}
108
76a66253 109/* SPR common to all non-embedded PowerPC */
3fc6c082 110/* DECR */
76a66253 111#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 112static void spr_read_decr (void *opaque, int sprn)
113{
114 gen_op_load_decr();
115}
116
117static void spr_write_decr (void *opaque, int sprn)
118{
119 gen_op_store_decr();
120}
76a66253 121#endif
3fc6c082 122
76a66253 123/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 124/* Time base */
125static void spr_read_tbl (void *opaque, int sprn)
126{
127 gen_op_load_tbl();
128}
129
76a66253 130static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 131{
76a66253 132 gen_op_load_tbu();
3fc6c082
FB		 133}
134
76a66253
JM		 135#if !defined(CONFIG_USER_ONLY)
136static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 137{
76a66253 138 gen_op_store_tbl();
3fc6c082
FB		 139}
140
141static void spr_write_tbu (void *opaque, int sprn)
142{
143 gen_op_store_tbu();
144}
76a66253 145#endif
3fc6c082 146
76a66253 147#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 148/* IBAT0U...IBAT0U */
149/* IBAT0L...IBAT7L */
150static void spr_read_ibat (void *opaque, int sprn)
151{
152 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
153}
154
155static void spr_read_ibat_h (void *opaque, int sprn)
156{
157 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
158}
159
160static void spr_write_ibatu (void *opaque, int sprn)
161{
162 DisasContext *ctx = opaque;
163
164 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
165 RET_STOP(ctx);
166}
167
168static void spr_write_ibatu_h (void *opaque, int sprn)
169{
170 DisasContext *ctx = opaque;
171
172 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
173 RET_STOP(ctx);
174}
175
176static void spr_write_ibatl (void *opaque, int sprn)
177{
178 DisasContext *ctx = opaque;
179
180 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
181 RET_STOP(ctx);
182}
183
184static void spr_write_ibatl_h (void *opaque, int sprn)
185{
186 DisasContext *ctx = opaque;
187
188 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
189 RET_STOP(ctx);
190}
191
192/* DBAT0U...DBAT7U */
193/* DBAT0L...DBAT7L */
194static void spr_read_dbat (void *opaque, int sprn)
195{
196 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
197}
198
199static void spr_read_dbat_h (void *opaque, int sprn)
200{
201 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
202}
203
204static void spr_write_dbatu (void *opaque, int sprn)
205{
206 DisasContext *ctx = opaque;
207
208 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
209 RET_STOP(ctx);
210}
211
212static void spr_write_dbatu_h (void *opaque, int sprn)
213{
214 DisasContext *ctx = opaque;
215
216 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
217 RET_STOP(ctx);
218}
219
220static void spr_write_dbatl (void *opaque, int sprn)
221{
222 DisasContext *ctx = opaque;
223
224 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
225 RET_STOP(ctx);
226}
227
228static void spr_write_dbatl_h (void *opaque, int sprn)
229{
230 DisasContext *ctx = opaque;
231
232 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
233 RET_STOP(ctx);
234}
235
236/* SDR1 */
237static void spr_read_sdr1 (void *opaque, int sprn)
238{
239 gen_op_load_sdr1();
240}
241
242static void spr_write_sdr1 (void *opaque, int sprn)
243{
244 DisasContext *ctx = opaque;
245
246 gen_op_store_sdr1();
247 RET_STOP(ctx);
248}
249
76a66253
JM		 250/* 64 bits PowerPC specific SPRs */
251/* ASR */
252#if defined(TARGET_PPC64)
253static void spr_read_asr (void *opaque, int sprn)
254{
255 gen_op_load_asr();
256}
257
258static void spr_write_asr (void *opaque, int sprn)
259{
260 DisasContext *ctx = opaque;
261
262 gen_op_store_asr();
263 RET_STOP(ctx);
264}
265#endif
266#endif /* !defined(CONFIG_USER_ONLY) */
267
268/* PowerPC 601 specific registers */
269/* RTC */
270static void spr_read_601_rtcl (void *opaque, int sprn)
271{
272 gen_op_load_601_rtcl();
273}
274
275static void spr_read_601_rtcu (void *opaque, int sprn)
276{
277 gen_op_load_601_rtcu();
278}
279
280#if !defined(CONFIG_USER_ONLY)
281static void spr_write_601_rtcu (void *opaque, int sprn)
282{
283 gen_op_store_601_rtcu();
284}
285
286static void spr_write_601_rtcl (void *opaque, int sprn)
287{
288 gen_op_store_601_rtcl();
289}
290#endif
291
292/* Unified bats */
293#if !defined(CONFIG_USER_ONLY)
294static void spr_read_601_ubat (void *opaque, int sprn)
295{
296 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
297}
298
299static void spr_write_601_ubatu (void *opaque, int sprn)
300{
301 DisasContext *ctx = opaque;
302
303 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
304 RET_STOP(ctx);
305}
306
307static void spr_write_601_ubatl (void *opaque, int sprn)
308{
309 DisasContext *ctx = opaque;
310
311 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
312 RET_STOP(ctx);
313}
314#endif
315
316/* PowerPC 40x specific registers */
317#if !defined(CONFIG_USER_ONLY)
318static void spr_read_40x_pit (void *opaque, int sprn)
319{
320 gen_op_load_40x_pit();
321}
322
323static void spr_write_40x_pit (void *opaque, int sprn)
324{
325 gen_op_store_40x_pit();
326}
327
328static void spr_write_booke_tcr (void *opaque, int sprn)
329{
330 gen_op_store_booke_tcr();
331}
332
333static void spr_write_booke_tsr (void *opaque, int sprn)
334{
335 gen_op_store_booke_tsr();
336}
337#endif
338
339/* PowerPC 403 specific registers */
340/* PBL1 / PBU1 / PBL2 / PBU2 */
341#if !defined(CONFIG_USER_ONLY)
342static void spr_read_403_pbr (void *opaque, int sprn)
343{
344 gen_op_load_403_pb(sprn - SPR_403_PBL1);
345}
346
347static void spr_write_403_pbr (void *opaque, int sprn)
348{
349 DisasContext *ctx = opaque;
350
351 gen_op_store_403_pb(sprn - SPR_403_PBL1);
352 RET_STOP(ctx);
353}
354
3fc6c082
FB		 355static void spr_write_pir (void *opaque, int sprn)
356{
357 gen_op_store_pir();
358}
76a66253 359#endif
3fc6c082 360
76a66253
JM		 361#if defined(CONFIG_USER_ONLY)
362#define spr_register(env, num, name, uea_read, uea_write, \
363 oea_read, oea_write, initial_value) \
364do { \
365 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
366} while (0)
367static inline void _spr_register (CPUPPCState *env, int num,
368 const unsigned char *name,
369 void (*uea_read)(void *opaque, int sprn),
370 void (*uea_write)(void *opaque, int sprn),
371 target_ulong initial_value)
372#else
3fc6c082
FB		 373static inline void spr_register (CPUPPCState *env, int num,
374 const unsigned char *name,
375 void (*uea_read)(void *opaque, int sprn),
376 void (*uea_write)(void *opaque, int sprn),
377 void (*oea_read)(void *opaque, int sprn),
378 void (*oea_write)(void *opaque, int sprn),
379 target_ulong initial_value)
76a66253 380#endif
3fc6c082
FB		 381{
382 ppc_spr_t *spr;
383
384 spr = &env->spr_cb[num];
385 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 386#if !defined(CONFIG_USER_ONLY)
387 spr->oea_read != NULL || spr->oea_write != NULL ||
388#endif
389 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 390 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
391 exit(1);
392 }
393#if defined(PPC_DEBUG_SPR)
1b9eb036 394 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 395 initial_value);
3fc6c082
FB		 396#endif
397 spr->name = name;
398 spr->uea_read = uea_read;
399 spr->uea_write = uea_write;
76a66253 400#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 401 spr->oea_read = oea_read;
402 spr->oea_write = oea_write;
76a66253 403#endif
3fc6c082
FB		 404 env->spr[num] = initial_value;
405}
406
407/* Generic PowerPC SPRs */
408static void gen_spr_generic (CPUPPCState *env)
409{
410 /* Integer processing */
411 spr_register(env, SPR_XER, "XER",
412 &spr_read_xer, &spr_write_xer,
413 &spr_read_xer, &spr_write_xer,
414 0x00000000);
415 /* Branch contol */
416 spr_register(env, SPR_LR, "LR",
417 &spr_read_lr, &spr_write_lr,
418 &spr_read_lr, &spr_write_lr,
419 0x00000000);
420 spr_register(env, SPR_CTR, "CTR",
421 &spr_read_ctr, &spr_write_ctr,
422 &spr_read_ctr, &spr_write_ctr,
423 0x00000000);
424 /* Interrupt processing */
425 spr_register(env, SPR_SRR0, "SRR0",
426 SPR_NOACCESS, SPR_NOACCESS,
427 &spr_read_generic, &spr_write_generic,
428 0x00000000);
429 spr_register(env, SPR_SRR1, "SRR1",
430 SPR_NOACCESS, SPR_NOACCESS,
431 &spr_read_generic, &spr_write_generic,
432 0x00000000);
433 /* Processor control */
434 spr_register(env, SPR_SPRG0, "SPRG0",
435 SPR_NOACCESS, SPR_NOACCESS,
436 &spr_read_generic, &spr_write_generic,
437 0x00000000);
438 spr_register(env, SPR_SPRG1, "SPRG1",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, &spr_write_generic,
441 0x00000000);
442 spr_register(env, SPR_SPRG2, "SPRG2",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, &spr_write_generic,
445 0x00000000);
446 spr_register(env, SPR_SPRG3, "SPRG3",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, &spr_write_generic,
449 0x00000000);
450}
451
452/* SPR common to all non-embedded PowerPC, including 601 */
453static void gen_spr_ne_601 (CPUPPCState *env)
454{
455 /* Exception processing */
456 spr_register(env, SPR_DSISR, "DSISR",
457 SPR_NOACCESS, SPR_NOACCESS,
458 &spr_read_generic, &spr_write_generic,
459 0x00000000);
460 spr_register(env, SPR_DAR, "DAR",
461 SPR_NOACCESS, SPR_NOACCESS,
462 &spr_read_generic, &spr_write_generic,
463 0x00000000);
464 /* Timer */
465 spr_register(env, SPR_DECR, "DECR",
466 SPR_NOACCESS, SPR_NOACCESS,
467 &spr_read_decr, &spr_write_decr,
468 0x00000000);
469 /* Memory management */
470 spr_register(env, SPR_SDR1, "SDR1",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_sdr1, &spr_write_sdr1,
473 0x00000000);
474}
475
476/* BATs 0-3 */
477static void gen_low_BATs (CPUPPCState *env)
478{
479 spr_register(env, SPR_IBAT0U, "IBAT0U",
480 SPR_NOACCESS, SPR_NOACCESS,
481 &spr_read_ibat, &spr_write_ibatu,
482 0x00000000);
483 spr_register(env, SPR_IBAT0L, "IBAT0L",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_ibat, &spr_write_ibatl,
486 0x00000000);
487 spr_register(env, SPR_IBAT1U, "IBAT1U",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_ibat, &spr_write_ibatu,
490 0x00000000);
491 spr_register(env, SPR_IBAT1L, "IBAT1L",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_ibat, &spr_write_ibatl,
494 0x00000000);
495 spr_register(env, SPR_IBAT2U, "IBAT2U",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_ibat, &spr_write_ibatu,
498 0x00000000);
499 spr_register(env, SPR_IBAT2L, "IBAT2L",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_ibat, &spr_write_ibatl,
502 0x00000000);
503 spr_register(env, SPR_IBAT3U, "IBAT3U",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_ibat, &spr_write_ibatu,
506 0x00000000);
507 spr_register(env, SPR_IBAT3L, "IBAT3L",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_ibat, &spr_write_ibatl,
510 0x00000000);
511 spr_register(env, SPR_DBAT0U, "DBAT0U",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_dbat, &spr_write_dbatu,
514 0x00000000);
515 spr_register(env, SPR_DBAT0L, "DBAT0L",
516 SPR_NOACCESS, SPR_NOACCESS,
517 &spr_read_dbat, &spr_write_dbatl,
518 0x00000000);
519 spr_register(env, SPR_DBAT1U, "DBAT1U",
520 SPR_NOACCESS, SPR_NOACCESS,
521 &spr_read_dbat, &spr_write_dbatu,
522 0x00000000);
523 spr_register(env, SPR_DBAT1L, "DBAT1L",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_dbat, &spr_write_dbatl,
526 0x00000000);
527 spr_register(env, SPR_DBAT2U, "DBAT2U",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_dbat, &spr_write_dbatu,
530 0x00000000);
531 spr_register(env, SPR_DBAT2L, "DBAT2L",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_dbat, &spr_write_dbatl,
534 0x00000000);
535 spr_register(env, SPR_DBAT3U, "DBAT3U",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_dbat, &spr_write_dbatu,
538 0x00000000);
539 spr_register(env, SPR_DBAT3L, "DBAT3L",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_dbat, &spr_write_dbatl,
542 0x00000000);
543 env->nb_BATs = 4;
544}
545
546/* BATs 4-7 */
547static void gen_high_BATs (CPUPPCState *env)
548{
549 spr_register(env, SPR_IBAT4U, "IBAT4U",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_ibat_h, &spr_write_ibatu_h,
552 0x00000000);
553 spr_register(env, SPR_IBAT4L, "IBAT4L",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_ibat_h, &spr_write_ibatl_h,
556 0x00000000);
557 spr_register(env, SPR_IBAT5U, "IBAT5U",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_ibat_h, &spr_write_ibatu_h,
560 0x00000000);
561 spr_register(env, SPR_IBAT5L, "IBAT5L",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_ibat_h, &spr_write_ibatl_h,
564 0x00000000);
565 spr_register(env, SPR_IBAT6U, "IBAT6U",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_ibat_h, &spr_write_ibatu_h,
568 0x00000000);
569 spr_register(env, SPR_IBAT6L, "IBAT6L",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_ibat_h, &spr_write_ibatl_h,
572 0x00000000);
573 spr_register(env, SPR_IBAT7U, "IBAT7U",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_ibat_h, &spr_write_ibatu_h,
576 0x00000000);
577 spr_register(env, SPR_IBAT7L, "IBAT7L",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_ibat_h, &spr_write_ibatl_h,
580 0x00000000);
581 spr_register(env, SPR_DBAT4U, "DBAT4U",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_dbat_h, &spr_write_dbatu_h,
584 0x00000000);
585 spr_register(env, SPR_DBAT4L, "DBAT4L",
586 SPR_NOACCESS, SPR_NOACCESS,
587 &spr_read_dbat_h, &spr_write_dbatl_h,
588 0x00000000);
589 spr_register(env, SPR_DBAT5U, "DBAT5U",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_dbat_h, &spr_write_dbatu_h,
592 0x00000000);
593 spr_register(env, SPR_DBAT5L, "DBAT5L",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_dbat_h, &spr_write_dbatl_h,
596 0x00000000);
597 spr_register(env, SPR_DBAT6U, "DBAT6U",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_dbat_h, &spr_write_dbatu_h,
600 0x00000000);
601 spr_register(env, SPR_DBAT6L, "DBAT6L",
602 SPR_NOACCESS, SPR_NOACCESS,
603 &spr_read_dbat_h, &spr_write_dbatl_h,
604 0x00000000);
605 spr_register(env, SPR_DBAT7U, "DBAT7U",
606 SPR_NOACCESS, SPR_NOACCESS,
607 &spr_read_dbat_h, &spr_write_dbatu_h,
608 0x00000000);
609 spr_register(env, SPR_DBAT7L, "DBAT7L",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_dbat_h, &spr_write_dbatl_h,
612 0x00000000);
613 env->nb_BATs = 8;
614}
615
616/* Generic PowerPC time base */
617static void gen_tbl (CPUPPCState *env)
618{
619 spr_register(env, SPR_VTBL, "TBL",
620 &spr_read_tbl, SPR_NOACCESS,
621 &spr_read_tbl, SPR_NOACCESS,
622 0x00000000);
623 spr_register(env, SPR_TBL, "TBL",
624 SPR_NOACCESS, SPR_NOACCESS,
625 SPR_NOACCESS, &spr_write_tbl,
626 0x00000000);
627 spr_register(env, SPR_VTBU, "TBU",
628 &spr_read_tbu, SPR_NOACCESS,
629 &spr_read_tbu, SPR_NOACCESS,
630 0x00000000);
631 spr_register(env, SPR_TBU, "TBU",
632 SPR_NOACCESS, SPR_NOACCESS,
633 SPR_NOACCESS, &spr_write_tbu,
634 0x00000000);
635}
636
76a66253
JM		 637/* Softare table search registers */
638static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
639{
640 env->nb_tlb = nb_tlbs;
641 env->nb_ways = nb_ways;
642 env->id_tlbs = 1;
643 spr_register(env, SPR_DMISS, "DMISS",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, SPR_NOACCESS,
646 0x00000000);
647 spr_register(env, SPR_DCMP, "DCMP",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_generic, SPR_NOACCESS,
650 0x00000000);
651 spr_register(env, SPR_HASH1, "HASH1",
652 SPR_NOACCESS, SPR_NOACCESS,
653 &spr_read_generic, SPR_NOACCESS,
654 0x00000000);
655 spr_register(env, SPR_HASH2, "HASH2",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, SPR_NOACCESS,
658 0x00000000);
659 spr_register(env, SPR_IMISS, "IMISS",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, SPR_NOACCESS,
662 0x00000000);
663 spr_register(env, SPR_ICMP, "ICMP",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, SPR_NOACCESS,
666 0x00000000);
667 spr_register(env, SPR_RPA, "RPA",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671}
672
673/* SPR common to MPC755 and G2 */
674static void gen_spr_G2_755 (CPUPPCState *env)
675{
676 /* SGPRs */
677 spr_register(env, SPR_SPRG4, "SPRG4",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 0x00000000);
681 spr_register(env, SPR_SPRG5, "SPRG5",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 spr_register(env, SPR_SPRG6, "SPRG6",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, &spr_write_generic,
688 0x00000000);
689 spr_register(env, SPR_SPRG7, "SPRG7",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, &spr_write_generic,
692 0x00000000);
693 /* External access control */
694 /* XXX : not implemented */
695 spr_register(env, SPR_EAR, "EAR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, &spr_write_generic,
698 0x00000000);
699}
700
3fc6c082
FB		 701/* SPR common to all 7xx PowerPC implementations */
702static void gen_spr_7xx (CPUPPCState *env)
703{
704 /* Breakpoints */
705 /* XXX : not implemented */
706 spr_register(env, SPR_DABR, "DABR",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, &spr_write_generic,
709 0x00000000);
710 /* XXX : not implemented */
711 spr_register(env, SPR_IABR, "IABR",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715 /* Cache management */
716 /* XXX : not implemented */
717 spr_register(env, SPR_ICTC, "ICTC",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, &spr_write_generic,
720 0x00000000);
76a66253
JM		 721 /* XXX : not implemented */
722 spr_register(env, SPR_L2CR, "L2CR",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, &spr_write_generic,
725 0x00000000);
3fc6c082
FB		 726 /* Performance monitors */
727 /* XXX : not implemented */
728 spr_register(env, SPR_MMCR0, "MMCR0",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_generic, &spr_write_generic,
731 0x00000000);
732 /* XXX : not implemented */
733 spr_register(env, SPR_MMCR1, "MMCR1",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 0x00000000);
737 /* XXX : not implemented */
738 spr_register(env, SPR_PMC1, "PMC1",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742 /* XXX : not implemented */
743 spr_register(env, SPR_PMC2, "PMC2",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_generic,
746 0x00000000);
747 /* XXX : not implemented */
748 spr_register(env, SPR_PMC3, "PMC3",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752 /* XXX : not implemented */
753 spr_register(env, SPR_PMC4, "PMC4",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 /* XXX : not implemented */
758 spr_register(env, SPR_SIA, "SIA",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, SPR_NOACCESS,
761 0x00000000);
762 spr_register(env, SPR_UMMCR0, "UMMCR0",
763 &spr_read_ureg, SPR_NOACCESS,
764 &spr_read_ureg, SPR_NOACCESS,
765 0x00000000);
766 spr_register(env, SPR_UMMCR1, "UMMCR1",
767 &spr_read_ureg, SPR_NOACCESS,
768 &spr_read_ureg, SPR_NOACCESS,
769 0x00000000);
770 spr_register(env, SPR_UPMC1, "UPMC1",
771 &spr_read_ureg, SPR_NOACCESS,
772 &spr_read_ureg, SPR_NOACCESS,
773 0x00000000);
774 spr_register(env, SPR_UPMC2, "UPMC2",
775 &spr_read_ureg, SPR_NOACCESS,
776 &spr_read_ureg, SPR_NOACCESS,
777 0x00000000);
778 spr_register(env, SPR_UPMC3, "UPMC3",
779 &spr_read_ureg, SPR_NOACCESS,
780 &spr_read_ureg, SPR_NOACCESS,
781 0x00000000);
782 spr_register(env, SPR_UPMC4, "UPMC4",
783 &spr_read_ureg, SPR_NOACCESS,
784 &spr_read_ureg, SPR_NOACCESS,
785 0x00000000);
786 spr_register(env, SPR_USIA, "USIA",
787 &spr_read_ureg, SPR_NOACCESS,
788 &spr_read_ureg, SPR_NOACCESS,
789 0x00000000);
790 /* Thermal management */
791 /* XXX : not implemented */
792 spr_register(env, SPR_THRM1, "THRM1",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_generic, &spr_write_generic,
795 0x00000000);
796 /* XXX : not implemented */
797 spr_register(env, SPR_THRM2, "THRM2",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 /* XXX : not implemented */
802 spr_register(env, SPR_THRM3, "THRM3",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 /* External access control */
807 /* XXX : not implemented */
808 spr_register(env, SPR_EAR, "EAR",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_generic, &spr_write_generic,
811 0x00000000);
812}
813
814/* SPR specific to PowerPC 604 implementation */
815static void gen_spr_604 (CPUPPCState *env)
816{
817 /* Processor identification */
818 spr_register(env, SPR_PIR, "PIR",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_pir,
821 0x00000000);
822 /* Breakpoints */
823 /* XXX : not implemented */
824 spr_register(env, SPR_IABR, "IABR",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828 /* XXX : not implemented */
829 spr_register(env, SPR_DABR, "DABR",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_generic, &spr_write_generic,
832 0x00000000);
833 /* Performance counters */
834 /* XXX : not implemented */
835 spr_register(env, SPR_MMCR0, "MMCR0",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_generic, &spr_write_generic,
838 0x00000000);
839 /* XXX : not implemented */
840 spr_register(env, SPR_MMCR1, "MMCR1",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_generic, &spr_write_generic,
843 0x00000000);
844 /* XXX : not implemented */
845 spr_register(env, SPR_PMC1, "PMC1",
846 SPR_NOACCESS, SPR_NOACCESS,
847 &spr_read_generic, &spr_write_generic,
848 0x00000000);
849 /* XXX : not implemented */
850 spr_register(env, SPR_PMC2, "PMC2",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_generic, &spr_write_generic,
853 0x00000000);
854 /* XXX : not implemented */
855 spr_register(env, SPR_PMC3, "PMC3",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, &spr_write_generic,
858 0x00000000);
859 /* XXX : not implemented */
860 spr_register(env, SPR_PMC4, "PMC4",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_generic,
863 0x00000000);
864 /* XXX : not implemented */
865 spr_register(env, SPR_SIA, "SIA",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, SPR_NOACCESS,
868 0x00000000);
869 /* XXX : not implemented */
870 spr_register(env, SPR_SDA, "SDA",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 /* External access control */
875 /* XXX : not implemented */
876 spr_register(env, SPR_EAR, "EAR",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, &spr_write_generic,
879 0x00000000);
880}
881
76a66253
JM		 882/* SPR specific to PowerPC 603 implementation */
883static void gen_spr_603 (CPUPPCState *env)
3fc6c082 884{
76a66253
JM		 885 /* External access control */
886 /* XXX : not implemented */
887 spr_register(env, SPR_EAR, "EAR",
3fc6c082 888 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
3fc6c082
FB		 891}
892
76a66253
JM		 893/* SPR specific to PowerPC G2 implementation */
894static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 895{
76a66253
JM		 896 /* Memory base address */
897 /* MBAR */
898 spr_register(env, SPR_MBAR, "MBAR",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 /* System version register */
903 /* SVR */
904 spr_register(env, SPR_SVR, "SVR",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, SPR_NOACCESS,
907 0x00000000);
908 /* Exception processing */
363be49c 909 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
363be49c 913 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 /* Breakpoints */
918 /* XXX : not implemented */
919 spr_register(env, SPR_DABR, "DABR",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_DABR2, "DABR2",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_IABR, "IABR",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_IABR2, "IABR2",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_IBCR, "IBCR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_DBCR, "DBCR",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948}
949
950/* SPR specific to PowerPC 602 implementation */
951static void gen_spr_602 (CPUPPCState *env)
952{
953 /* ESA registers */
954 /* XXX : not implemented */
955 spr_register(env, SPR_SER, "SER",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_SEBR, "SEBR",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_ESASR, "ESASR",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* Floating point status */
970 /* XXX : not implemented */
971 spr_register(env, SPR_SP, "SP",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_LT, "LT",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* Watchdog timer */
981 /* XXX : not implemented */
982 spr_register(env, SPR_TCR, "TCR",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 /* Interrupt base */
987 spr_register(env, SPR_IBR, "IBR",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
991}
992
993/* SPR specific to PowerPC 601 implementation */
994static void gen_spr_601 (CPUPPCState *env)
995{
996 /* Multiplication/division register */
997 /* MQ */
998 spr_register(env, SPR_MQ, "MQ",
999 &spr_read_generic, &spr_write_generic,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002 /* RTC registers */
1003 spr_register(env, SPR_601_RTCU, "RTCU",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 SPR_NOACCESS, &spr_write_601_rtcu,
1006 0x00000000);
1007 spr_register(env, SPR_601_VRTCU, "RTCU",
1008 &spr_read_601_rtcu, SPR_NOACCESS,
1009 &spr_read_601_rtcu, SPR_NOACCESS,
1010 0x00000000);
1011 spr_register(env, SPR_601_RTCL, "RTCL",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 SPR_NOACCESS, &spr_write_601_rtcl,
1014 0x00000000);
1015 spr_register(env, SPR_601_VRTCL, "RTCL",
1016 &spr_read_601_rtcl, SPR_NOACCESS,
1017 &spr_read_601_rtcl, SPR_NOACCESS,
1018 0x00000000);
1019 /* Timer */
1020#if 0 /* ? */
1021 spr_register(env, SPR_601_UDECR, "UDECR",
1022 &spr_read_decr, SPR_NOACCESS,
1023 &spr_read_decr, SPR_NOACCESS,
1024 0x00000000);
1025#endif
1026 /* External access control */
1027 /* XXX : not implemented */
1028 spr_register(env, SPR_EAR, "EAR",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, &spr_write_generic,
1031 0x00000000);
1032 /* Memory management */
1033 spr_register(env, SPR_IBAT0U, "IBAT0U",
1034 SPR_NOACCESS, SPR_NOACCESS,
1035 &spr_read_601_ubat, &spr_write_601_ubatu,
1036 0x00000000);
1037 spr_register(env, SPR_IBAT0L, "IBAT0L",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_601_ubat, &spr_write_601_ubatl,
1040 0x00000000);
1041 spr_register(env, SPR_IBAT1U, "IBAT1U",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_601_ubat, &spr_write_601_ubatu,
1044 0x00000000);
1045 spr_register(env, SPR_IBAT1L, "IBAT1L",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_601_ubat, &spr_write_601_ubatl,
1048 0x00000000);
1049 spr_register(env, SPR_IBAT2U, "IBAT2U",
1050 SPR_NOACCESS, SPR_NOACCESS,
1051 &spr_read_601_ubat, &spr_write_601_ubatu,
1052 0x00000000);
1053 spr_register(env, SPR_IBAT2L, "IBAT2L",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_601_ubat, &spr_write_601_ubatl,
1056 0x00000000);
1057 spr_register(env, SPR_IBAT3U, "IBAT3U",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_601_ubat, &spr_write_601_ubatu,
1060 0x00000000);
1061 spr_register(env, SPR_IBAT3L, "IBAT3L",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_601_ubat, &spr_write_601_ubatl,
1064 0x00000000);
1065}
1066
1067/* PowerPC BookE SPR */
1068static void gen_spr_BookE (CPUPPCState *env)
1069{
1070 /* Processor identification */
1071 spr_register(env, SPR_BOOKE_PIR, "PIR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_pir,
1074 0x00000000);
1075 /* Interrupt processing */
363be49c 1076 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
363be49c
JM		 1080 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
1096 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
76a66253
JM		 1097 SPR_NOACCESS, SPR_NOACCESS,
1098 &spr_read_generic, &spr_write_generic,
1099 0x00000000);
1100 /* Debug */
1101 /* XXX : not implemented */
1102 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 /* XXX : not implemented */
1107 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1108 SPR_NOACCESS, SPR_NOACCESS,
1109 &spr_read_generic, &spr_write_generic,
1110 0x00000000);
1111 /* XXX : not implemented */
1112 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* XXX : not implemented */
1117 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 /* XXX : not implemented */
1122 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 spr_register(env, SPR_BOOKE_ESR, "ESR",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
363be49c
JM		 1169 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Exception vectors */
1174 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
76a66253
JM		 1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_generic,
1201 0x00000000);
1202 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
1218 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_generic,
1225 0x00000000);
1226 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, &spr_write_generic,
1241 0x00000000);
363be49c
JM		 1242 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1249 0x00000000);
1250 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 0x00000000);
76a66253
JM		 1266 spr_register(env, SPR_BOOKE_PID, "PID",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270 spr_register(env, SPR_BOOKE_TCR, "TCR",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_booke_tcr,
1273 0x00000000);
1274 spr_register(env, SPR_BOOKE_TSR, "TSR",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_booke_tsr,
1277 0x00000000);
1278 /* Timer */
1279 spr_register(env, SPR_DECR, "DECR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_decr, &spr_write_decr,
1282 0x00000000);
1283 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 SPR_NOACCESS, &spr_write_generic,
1286 0x00000000);
1287 /* SPRGs */
1288 spr_register(env, SPR_USPRG0, "USPRG0",
1289 &spr_read_generic, &spr_write_generic,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 spr_register(env, SPR_SPRG4, "SPRG4",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 spr_register(env, SPR_USPRG4, "USPRG4",
1297 &spr_read_ureg, SPR_NOACCESS,
1298 &spr_read_ureg, SPR_NOACCESS,
1299 0x00000000);
1300 spr_register(env, SPR_SPRG5, "SPRG5",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 spr_register(env, SPR_USPRG5, "USPRG5",
1305 &spr_read_ureg, SPR_NOACCESS,
1306 &spr_read_ureg, SPR_NOACCESS,
1307 0x00000000);
1308 spr_register(env, SPR_SPRG6, "SPRG6",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312 spr_register(env, SPR_USPRG6, "USPRG6",
1313 &spr_read_ureg, SPR_NOACCESS,
1314 &spr_read_ureg, SPR_NOACCESS,
1315 0x00000000);
1316 spr_register(env, SPR_SPRG7, "SPRG7",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 spr_register(env, SPR_USPRG7, "USPRG7",
1321 &spr_read_ureg, SPR_NOACCESS,
1322 &spr_read_ureg, SPR_NOACCESS,
1323 0x00000000);
1324}
1325
363be49c
JM		 1326/* FSL storage control registers */
1327static void gen_spr_BookE_FSL (CPUPPCState *env)
1328{
1329 /* TLB assist registers */
1330 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 if (env->nb_pids > 1) {
1359 spr_register(env, SPR_BOOKE_PID1, "PID1",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 }
1364 if (env->nb_pids > 2) {
1365 spr_register(env, SPR_BOOKE_PID2, "PID2",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 }
1370 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, SPR_NOACCESS,
1373 0x00000000); /* TOFIX */
1374 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000); /* TOFIX */
1378 switch (env->nb_ways) {
1379 case 4:
1380 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, SPR_NOACCESS,
1383 0x00000000); /* TOFIX */
1384 /* Fallthru */
1385 case 3:
1386 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, SPR_NOACCESS,
1389 0x00000000); /* TOFIX */
1390 /* Fallthru */
1391 case 2:
1392 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, SPR_NOACCESS,
1395 0x00000000); /* TOFIX */
1396 /* Fallthru */
1397 case 1:
1398 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1399 SPR_NOACCESS, SPR_NOACCESS,
1400 &spr_read_generic, SPR_NOACCESS,
1401 0x00000000); /* TOFIX */
1402 /* Fallthru */
1403 case 0:
1404 default:
1405 break;
1406 }
1407}
1408
76a66253
JM		 1409/* SPR specific to PowerPC 440 implementation */
1410static void gen_spr_440 (CPUPPCState *env)
1411{
1412 /* Cache control */
1413 /* XXX : not implemented */
1414 spr_register(env, SPR_440_DNV0, "DNV0",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_440_DNV1, "DNV1",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 /* XXX : not implemented */
1424 spr_register(env, SPR_440_DNV2, "DNV2",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 /* XXX : not implemented */
1429 spr_register(env, SPR_440_DNV3, "DNV3",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_440_DVT0, "DVT0",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_440_DVT1, "DVT1",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 /* XXX : not implemented */
1444 spr_register(env, SPR_440_DVT2, "DVT2",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 /* XXX : not implemented */
1449 spr_register(env, SPR_440_DVT3, "DVT3",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 /* XXX : not implemented */
1454 spr_register(env, SPR_440_DVLIM, "DVLIM",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 /* XXX : not implemented */
1459 spr_register(env, SPR_440_INV0, "INV0",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 /* XXX : not implemented */
1464 spr_register(env, SPR_440_INV1, "INV1",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* XXX : not implemented */
1469 spr_register(env, SPR_440_INV2, "INV2",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 /* XXX : not implemented */
1474 spr_register(env, SPR_440_INV3, "INV3",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_440_IVT0, "IVT0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_440_IVT1, "IVT1",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_440_IVT2, "IVT2",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_440_IVT3, "IVT3",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
1499 spr_register(env, SPR_440_IVLIM, "IVLIM",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 /* Cache debug */
1504 /* XXX : not implemented */
363be49c 1505 spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
76a66253
JM		 1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, SPR_NOACCESS,
1508 0x00000000);
1509 /* XXX : not implemented */
363be49c 1510 spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
76a66253
JM		 1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, SPR_NOACCESS,
1513 0x00000000);
1514 /* XXX : not implemented */
363be49c 1515 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
76a66253
JM		 1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, SPR_NOACCESS,
1518 0x00000000);
1519 /* XXX : not implemented */
363be49c 1520 spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
76a66253
JM		 1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, SPR_NOACCESS,
1523 0x00000000);
1524 /* XXX : not implemented */
363be49c 1525 spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
76a66253
JM		 1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, SPR_NOACCESS,
1528 0x00000000);
1529 /* XXX : not implemented */
1530 spr_register(env, SPR_440_DBDR, "DBDR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
1534 /* Processor control */
1535 spr_register(env, SPR_4xx_CCR0, "CCR0",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, SPR_NOACCESS,
1542 0x00000000);
1543 /* Storage control */
1544 spr_register(env, SPR_440_MMUCR, "MMUCR",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548}
1549
1550/* SPR shared between PowerPC 40x implementations */
1551static void gen_spr_40x (CPUPPCState *env)
1552{
1553 /* Cache */
1554 /* XXX : not implemented */
1555 spr_register(env, SPR_40x_DCCR, "DCCR",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559 /* XXX : not implemented */
1560 spr_register(env, SPR_40x_DCWR, "DCWR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 /* XXX : not implemented */
1565 spr_register(env, SPR_40x_ICCR, "ICCR",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 /* XXX : not implemented */
363be49c 1570 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
76a66253
JM		 1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, SPR_NOACCESS,
1573 0x00000000);
1574 /* Bus access control */
1575 spr_register(env, SPR_40x_SGR, "SGR",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0xFFFFFFFF);
1579 spr_register(env, SPR_40x_ZPR, "ZPR",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* MMU */
1584 spr_register(env, SPR_40x_PID, "PID",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 /* Exception */
1589 spr_register(env, SPR_40x_DEAR, "DEAR",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 spr_register(env, SPR_40x_ESR, "ESR",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597 spr_register(env, SPR_40x_EVPR, "EVPR",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, &spr_write_generic,
1600 0x00000000);
1601 spr_register(env, SPR_40x_SRR2, "SRR2",
1602 &spr_read_generic, &spr_write_generic,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605 spr_register(env, SPR_40x_SRR3, "SRR3",
1606 &spr_read_generic, &spr_write_generic,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609 /* Timers */
1610 spr_register(env, SPR_40x_PIT, "PIT",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_40x_pit, &spr_write_40x_pit,
1613 0x00000000);
1614 spr_register(env, SPR_40x_TCR, "TCR",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_booke_tcr,
1617 0x00000000);
1618 spr_register(env, SPR_40x_TSR, "TSR",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_booke_tsr,
1621 0x00000000);
1622 /* Debug interface */
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_40x_DAC1, "DAC1",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 spr_register(env, SPR_40x_DAC2, "DAC2",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632 /* XXX : not implemented */
1633 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637 /* XXX : not implemented */
1638 spr_register(env, SPR_40x_DBSR, "DBSR",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 /* Last reset was system reset (system boot */
1642 0x00000300);
1643 /* XXX : not implemented */
1644 spr_register(env, SPR_40x_IAC1, "IAC1",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 spr_register(env, SPR_40x_IAC2, "IAC2",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652}
1653
1654/* SPR specific to PowerPC 405 implementation */
1655static void gen_spr_405 (CPUPPCState *env)
1656{
1657 spr_register(env, SPR_4xx_CCR0, "CCR0",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00700000);
1661 /* Debug */
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_405_DBCR1, "DBCR1",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_405_DVC1, "DVC1",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_405_DVC2, "DVC2",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_405_IAC3, "IAC3",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_405_IAC4, "IAC4",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* Storage control */
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_405_SLER, "SLER",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_405_SU0R, "SU0R",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* SPRG */
1699 spr_register(env, SPR_USPRG0, "USPRG0",
1700 &spr_read_ureg, SPR_NOACCESS,
1701 &spr_read_ureg, SPR_NOACCESS,
1702 0x00000000);
1703 spr_register(env, SPR_SPRG4, "SPRG4",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 SPR_NOACCESS, &spr_write_generic,
1706 0x00000000);
1707 spr_register(env, SPR_USPRG4, "USPRG4",
1708 &spr_read_ureg, SPR_NOACCESS,
1709 &spr_read_ureg, SPR_NOACCESS,
1710 0x00000000);
1711 spr_register(env, SPR_SPRG5, "SPRG5",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 SPR_NOACCESS, &spr_write_generic,
1714 0x00000000);
1715 spr_register(env, SPR_USPRG5, "USPRG5",
1716 &spr_read_ureg, SPR_NOACCESS,
1717 &spr_read_ureg, SPR_NOACCESS,
1718 0x00000000);
1719 spr_register(env, SPR_SPRG6, "SPRG6",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 SPR_NOACCESS, &spr_write_generic,
1722 0x00000000);
1723 spr_register(env, SPR_USPRG6, "USPRG6",
1724 &spr_read_ureg, SPR_NOACCESS,
1725 &spr_read_ureg, SPR_NOACCESS,
1726 0x00000000);
1727 spr_register(env, SPR_SPRG7, "SPRG7",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 SPR_NOACCESS, &spr_write_generic,
1730 0x00000000);
1731 spr_register(env, SPR_USPRG7, "USPRG7",
1732 &spr_read_ureg, SPR_NOACCESS,
1733 &spr_read_ureg, SPR_NOACCESS,
1734 0x00000000);
1735 /* Debug */
1736 /* XXX : not implemented */
1737 spr_register(env, SPR_40x_DAC2, "DAC2",
1738 SPR_NOACCESS, SPR_NOACCESS,
1739 &spr_read_generic, &spr_write_generic,
1740 0x00000000);
1741 /* XXX : not implemented */
1742 spr_register(env, SPR_40x_IAC2, "IAC2",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, &spr_write_generic,
1745 0x00000000);
1746}
1747
1748/* SPR shared between PowerPC 401 & 403 implementations */
1749static void gen_spr_401_403 (CPUPPCState *env)
1750{
1751 /* Time base */
1752 spr_register(env, SPR_403_VTBL, "TBL",
1753 &spr_read_tbl, SPR_NOACCESS,
1754 &spr_read_tbl, SPR_NOACCESS,
1755 0x00000000);
1756 spr_register(env, SPR_403_TBL, "TBL",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 SPR_NOACCESS, &spr_write_tbl,
1759 0x00000000);
1760 spr_register(env, SPR_403_VTBU, "TBU",
1761 &spr_read_tbu, SPR_NOACCESS,
1762 &spr_read_tbu, SPR_NOACCESS,
1763 0x00000000);
1764 spr_register(env, SPR_403_TBU, "TBU",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 SPR_NOACCESS, &spr_write_tbu,
1767 0x00000000);
1768 /* Debug */
1769 /* XXX: not implemented */
1770 spr_register(env, SPR_403_CDBCR, "CDBCR",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774}
1775
1776/* SPR specific to PowerPC 403 implementation */
1777static void gen_spr_403 (CPUPPCState *env)
1778{
1779 /* MMU */
1780 spr_register(env, SPR_403_PBL1, "PBL1",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_403_pbr, &spr_write_403_pbr,
1783 0x00000000);
1784 spr_register(env, SPR_403_PBU1, "PBU1",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_403_pbr, &spr_write_403_pbr,
1787 0x00000000);
1788 spr_register(env, SPR_403_PBL2, "PBL2",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_403_pbr, &spr_write_403_pbr,
1791 0x00000000);
1792 spr_register(env, SPR_403_PBU2, "PBU2",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_403_pbr, &spr_write_403_pbr,
1795 0x00000000);
1796 /* Debug */
1797 /* XXX : not implemented */
1798 spr_register(env, SPR_40x_DAC2, "DAC2",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 /* XXX : not implemented */
1803 spr_register(env, SPR_40x_IAC2, "IAC2",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807}
1808
1809/* SPR specific to PowerPC compression coprocessor extension */
1810#if defined (TODO)
1811static void gen_spr_compress (CPUPPCState *env)
1812{
1813 spr_register(env, SPR_401_SKR, "SKR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817}
1818#endif
1819
1820// XXX: TODO (64 bits PowerPC SPRs)
1821/*
1822 * ASR => SPR 280 (64 bits)
1823 * FPECR => SPR 1022 (?)
1824 * VRSAVE => SPR 256 (Altivec)
1825 * SCOMC => SPR 276 (64 bits ?)
1826 * SCOMD => SPR 277 (64 bits ?)
1827 * HSPRG0 => SPR 304 (hypervisor)
1828 * HSPRG1 => SPR 305 (hypervisor)
1829 * HDEC => SPR 310 (hypervisor)
1830 * HIOR => SPR 311 (hypervisor)
1831 * RMOR => SPR 312 (970)
1832 * HRMOR => SPR 313 (hypervisor)
1833 * HSRR0 => SPR 314 (hypervisor)
1834 * HSRR1 => SPR 315 (hypervisor)
1835 * LPCR => SPR 316 (970)
1836 * LPIDR => SPR 317 (970)
1837 * ... and more (thermal management, performance counters, ...)
1838 */
1839
1840static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1841{
1842 env->reserve = -1;
1843 /* Default MMU definitions */
1844 env->nb_BATs = -1;
1845 env->nb_tlb = 0;
1846 env->nb_ways = 0;
1847 /* XXX: missing:
1848 * 32 bits PowerPC:
1849 * - MPC5xx(x)
1850 * - MPC8xx(x)
1851 * - RCPU (same as MPC5xx ?)
1852 */
1853 spr_register(env, SPR_PVR, "PVR",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, SPR_NOACCESS,
1856 def->pvr);
1857 printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1858 def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1859 switch (def->pvr & def->pvr_mask) {
426613db 1860 /* Embedded PowerPC from IBM */
76a66253
JM		 1861 case CPU_PPC_401A1: /* 401 A1 family */
1862 case CPU_PPC_401B2: /* 401 B2 family */
1863 case CPU_PPC_401C2: /* 401 C2 family */
1864 case CPU_PPC_401D2: /* 401 D2 family */
1865 case CPU_PPC_401E2: /* 401 E2 family */
1866 case CPU_PPC_401F2: /* 401 F2 family */
1867 case CPU_PPC_401G2: /* 401 G2 family */
1868 case CPU_PPC_IOP480: /* IOP 480 family */
1869 case CPU_PPC_COBRA: /* IBM Processor for Network Resources */
1870 gen_spr_generic(env);
1871 gen_spr_40x(env);
1872 gen_spr_401_403(env);
1873#if defined (TODO)
1874 /* XXX: optional ? */
1875 gen_spr_compress(env);
1876#endif
1877 env->nb_BATs = 0;
1878 env->nb_tlb = 64;
1879 env->nb_ways = 1;
1880 env->id_tlbs = 0;
e9df014c 1881 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 1882 break;
1883
1884 case CPU_PPC_403GA: /* 403 GA family */
1885 case CPU_PPC_403GB: /* 403 GB family */
1886 case CPU_PPC_403GC: /* 403 GC family */
1887 case CPU_PPC_403GCX: /* 403 GCX family */
1888 gen_spr_generic(env);
1889 gen_spr_40x(env);
1890 gen_spr_401_403(env);
1891 gen_spr_403(env);
1892 env->nb_BATs = 0;
1893 env->nb_tlb = 64;
1894 env->nb_ways = 1;
1895 env->id_tlbs = 0;
e9df014c 1896 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 1897 break;
1898
1899 case CPU_PPC_405CR: /* 405 GP/CR family */
1900 case CPU_PPC_405EP: /* 405 EP family */
1901 case CPU_PPC_405GPR: /* 405 GPR family */
1902 case CPU_PPC_405D2: /* 405 D2 family */
1903 case CPU_PPC_405D4: /* 405 D4 family */
1904 gen_spr_generic(env);
1905 /* Time base */
1906 gen_tbl(env);
1907 gen_spr_40x(env);
1908 gen_spr_405(env);
1909 env->nb_BATs = 0;
1910 env->nb_tlb = 64;
1911 env->nb_ways = 1;
1912 env->id_tlbs = 0;
24be5ae3
JM		 1913 /* Allocate hardware IRQ controller */
1914 ppc405_irq_init(env);
76a66253
JM		 1915 break;
1916
1917 case CPU_PPC_NPE405H: /* NPe405 H family */
1918 case CPU_PPC_NPE405H2:
1919 case CPU_PPC_NPE405L: /* Npe405 L family */
1920 gen_spr_generic(env);
1921 /* Time base */
1922 gen_tbl(env);
1923 gen_spr_40x(env);
1924 gen_spr_405(env);
1925 env->nb_BATs = 0;
1926 env->nb_tlb = 64;
1927 env->nb_ways = 1;
1928 env->id_tlbs = 0;
24be5ae3
JM		 1929 /* Allocate hardware IRQ controller */
1930 ppc405_irq_init(env);
76a66253
JM		 1931 break;
1932
1933#if defined (TODO)
1934 case CPU_PPC_STB01000:
1935#endif
1936#if defined (TODO)
1937 case CPU_PPC_STB01010:
1938#endif
1939#if defined (TODO)
1940 case CPU_PPC_STB0210:
1941#endif
1942 case CPU_PPC_STB03: /* STB03 family */
1943#if defined (TODO)
1944 case CPU_PPC_STB043: /* STB043 family */
1945#endif
1946#if defined (TODO)
1947 case CPU_PPC_STB045: /* STB045 family */
1948#endif
1949 case CPU_PPC_STB25: /* STB25 family */
1950#if defined (TODO)
1951 case CPU_PPC_STB130: /* STB130 family */
1952#endif
1953 gen_spr_generic(env);
1954 /* Time base */
1955 gen_tbl(env);
1956 gen_spr_40x(env);
1957 gen_spr_405(env);
1958 env->nb_BATs = 0;
1959 env->nb_tlb = 64;
1960 env->nb_ways = 1;
1961 env->id_tlbs = 0;
24be5ae3
JM		 1962 /* Allocate hardware IRQ controller */
1963 ppc405_irq_init(env);
76a66253
JM		 1964 break;
1965
1966 case CPU_PPC_440EP: /* 440 EP family */
1967 case CPU_PPC_440GP: /* 440 GP family */
1968 case CPU_PPC_440GX: /* 440 GX family */
1969 case CPU_PPC_440GXc: /* 440 GXc family */
1970 case CPU_PPC_440GXf: /* 440 GXf family */
1971 case CPU_PPC_440SP: /* 440 SP family */
1972 case CPU_PPC_440SP2:
1973 case CPU_PPC_440SPE: /* 440 SPE family */
1974 gen_spr_generic(env);
1975 /* Time base */
1976 gen_tbl(env);
1977 gen_spr_BookE(env);
1978 gen_spr_440(env);
1979 env->nb_BATs = 0;
1980 env->nb_tlb = 64;
1981 env->nb_ways = 1;
1982 env->id_tlbs = 0;
e9df014c 1983 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 1984 break;
1985
426613db 1986 /* Embedded PowerPC from Freescale */
76a66253
JM		 1987#if defined (TODO)
1988 case CPU_PPC_5xx:
1989 break;
1990#endif
1991#if defined (TODO)
1992 case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */
1993 break;
1994#endif
1995#if defined (TODO)
1996 case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */
1997 case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */
1998 break;
1999#endif
2000#if defined (TODO)
2001 case CPU_PPC_827x: /* MPC 827x / 828x */
2002 break;
2003#endif
2004
426613db 2005 /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
76a66253
JM		 2006 case CPU_PPC_e500v110:
2007 case CPU_PPC_e500v120:
2008 case CPU_PPC_e500v210:
2009 case CPU_PPC_e500v220:
2010 gen_spr_generic(env);
2011 /* Time base */
2012 gen_tbl(env);
2013 gen_spr_BookE(env);
363be49c 2014 gen_spr_BookE_FSL(env);
76a66253
JM		 2015 env->nb_BATs = 0;
2016 env->nb_tlb = 64;
2017 env->nb_ways = 1;
2018 env->id_tlbs = 0;
e9df014c 2019 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2020 break;
2021
2022#if defined (TODO)
2023 case CPU_PPC_e600:
2024 break;
2025#endif
2026
426613db 2027 /* 32 bits PowerPC */
76a66253
JM		 2028 case CPU_PPC_601: /* PowerPC 601 */
2029 gen_spr_generic(env);
2030 gen_spr_ne_601(env);
2031 gen_spr_601(env);
2032 /* Hardware implementation registers */
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_HID0, "HID0",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_HID1, "HID1",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_601_HID2, "HID2",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_601_HID5, "HID5",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 /* XXX : not implemented */
2054#if 0 /* ? */
2055 spr_register(env, SPR_601_HID15, "HID15",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059#endif
2060 env->nb_tlb = 64;
2061 env->nb_ways = 2;
2062 env->id_tlbs = 0;
2063 env->id_tlbs = 0;
e9df014c 2064 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2065 break;
2066
2067 case CPU_PPC_602: /* PowerPC 602 */
2068 gen_spr_generic(env);
2069 gen_spr_ne_601(env);
2070 /* Memory management */
2071 gen_low_BATs(env);
2072 /* Time base */
2073 gen_tbl(env);
2074 gen_6xx_7xx_soft_tlb(env, 64, 2);
2075 gen_spr_602(env);
2076 /* hardware implementation registers */
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_HID0, "HID0",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_generic,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_HID1, "HID1",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
e9df014c
JM		 2087 /* Allocate hardware IRQ controller */
2088 ppc6xx_irq_init(env);
76a66253
JM		 2089 break;
2090
2091 case CPU_PPC_603: /* PowerPC 603 */
2092 case CPU_PPC_603E: /* PowerPC 603e */
2093 case CPU_PPC_603E7v:
2094 case CPU_PPC_603E7v2:
2095 case CPU_PPC_603P: /* PowerPC 603p */
2096 case CPU_PPC_603R: /* PowerPC 603r */
2097 gen_spr_generic(env);
2098 gen_spr_ne_601(env);
2099 /* Memory management */
2100 gen_low_BATs(env);
2101 /* Time base */
2102 gen_tbl(env);
2103 gen_6xx_7xx_soft_tlb(env, 64, 2);
2104 gen_spr_603(env);
2105 /* hardware implementation registers */
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_HID0, "HID0",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 /* XXX : not implemented */
2112 spr_register(env, SPR_HID1, "HID1",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, &spr_write_generic,
2115 0x00000000);
e9df014c
JM		 2116 /* Allocate hardware IRQ controller */
2117 ppc6xx_irq_init(env);
76a66253
JM		 2118 break;
2119
2120 case CPU_PPC_G2: /* PowerPC G2 family */
2121 case CPU_PPC_G2H4:
2122 case CPU_PPC_G2gp:
2123 case CPU_PPC_G2ls:
2124 case CPU_PPC_G2LE: /* PowerPC G2LE family */
2125 case CPU_PPC_G2LEgp:
2126 case CPU_PPC_G2LEls:
2127 gen_spr_generic(env);
2128 gen_spr_ne_601(env);
2129 /* Memory management */
2130 gen_low_BATs(env);
2131 /* Time base */
2132 gen_tbl(env);
2133 /* Memory management */
2134 gen_high_BATs(env);
2135 gen_6xx_7xx_soft_tlb(env, 64, 2);
2136 gen_spr_G2_755(env);
2137 gen_spr_G2(env);
2138 /* Hardware implementation register */
2139 /* XXX : not implemented */
2140 spr_register(env, SPR_HID0, "HID0",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_HID1, "HID1",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_HID2, "HID2",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
e9df014c
JM		 2154 /* Allocate hardware IRQ controller */
2155 ppc6xx_irq_init(env);
76a66253
JM		 2156 break;
2157
2158 case CPU_PPC_604: /* PowerPC 604 */
2159 case CPU_PPC_604E: /* PowerPC 604e */
2160 case CPU_PPC_604R: /* PowerPC 604r */
2161 gen_spr_generic(env);
2162 gen_spr_ne_601(env);
2163 /* Memory management */
2164 gen_low_BATs(env);
2165 /* Time base */
2166 gen_tbl(env);
2167 gen_spr_604(env);
2168 /* Hardware implementation registers */
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_HID0, "HID0",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
2174 /* XXX : not implemented */
2175 spr_register(env, SPR_HID1, "HID1",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
e9df014c
JM		 2179 /* Allocate hardware IRQ controller */
2180 ppc6xx_irq_init(env);
76a66253
JM		 2181 break;
2182
2183 case CPU_PPC_74x: /* PowerPC 740 / 750 */
2184 case CPU_PPC_740E:
2185 case CPU_PPC_750E:
2186 case CPU_PPC_74xP: /* PowerPC 740P / 750P */
2187 case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */
2188 case CPU_PPC_750CXE22:
2189 case CPU_PPC_750CXE23:
2190 case CPU_PPC_750CXE24:
2191 case CPU_PPC_750CXE24b:
2192 case CPU_PPC_750CXE31:
2193 case CPU_PPC_750CXE31b:
2194 case CPU_PPC_750CXR:
2195 gen_spr_generic(env);
2196 gen_spr_ne_601(env);
2197 /* Memory management */
2198 gen_low_BATs(env);
2199 /* Time base */
2200 gen_tbl(env);
2201 gen_spr_7xx(env);
2202 /* Hardware implementation registers */
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_HID0, "HID0",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
2208 /* XXX : not implemented */
2209 spr_register(env, SPR_HID1, "HID1",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
e9df014c
JM		 2213 /* Allocate hardware IRQ controller */
2214 ppc6xx_irq_init(env);
76a66253
JM		 2215 break;
2216
2217 case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */
2218 case CPU_PPC_750FX20:
2219 case CPU_PPC_750FX21:
2220 case CPU_PPC_750FX22:
2221 case CPU_PPC_750FX23:
2222 case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */
2223 case CPU_PPC_750GX11:
2224 case CPU_PPC_750GX12:
2225 gen_spr_generic(env);
2226 gen_spr_ne_601(env);
2227 /* Memory management */
2228 gen_low_BATs(env);
2229 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2230 gen_high_BATs(env);
2231 /* Time base */
2232 gen_tbl(env);
2233 gen_spr_7xx(env);
2234 /* Hardware implementation registers */
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_HID0, "HID0",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_HID1, "HID1",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_750_HID2, "HID2",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
e9df014c
JM		 2250 /* Allocate hardware IRQ controller */
2251 ppc6xx_irq_init(env);
76a66253
JM		 2252 break;
2253
2254 case CPU_PPC_755_10: /* PowerPC 755 */
2255 case CPU_PPC_755_11:
2256 case CPU_PPC_755_20:
2257 case CPU_PPC_755D:
2258 case CPU_PPC_755E:
2259 gen_spr_generic(env);
2260 gen_spr_ne_601(env);
2261 /* Memory management */
2262 gen_low_BATs(env);
2263 /* Time base */
2264 gen_tbl(env);
2265 /* Memory management */
2266 gen_high_BATs(env);
2267 gen_6xx_7xx_soft_tlb(env, 64, 2);
2268 gen_spr_G2_755(env);
2269 /* L2 cache control */
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_ICTC, "ICTC",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_L2PM, "L2PM",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* Hardware implementation registers */
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_HID0, "HID0",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_HID1, "HID1",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_HID2, "HID2",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
e9df014c
JM		 2296 /* Allocate hardware IRQ controller */
2297 ppc6xx_irq_init(env);
76a66253
JM		 2298 break;
2299
2300#if defined (TODO)
426613db 2301 /* G4 family */
76a66253
JM		 2302 case CPU_PPC_7400: /* PowerPC 7400 */
2303 case CPU_PPC_7410C: /* PowerPC 7410 */
2304 case CPU_PPC_7410D:
2305 case CPU_PPC_7410E:
2306 case CPU_PPC_7441: /* PowerPC 7441 */
2307 case CPU_PPC_7445: /* PowerPC 7445 */
2308 case CPU_PPC_7447: /* PowerPC 7447 */
2309 case CPU_PPC_7447A: /* PowerPC 7447A */
2310 case CPU_PPC_7448: /* PowerPC 7448 */
2311 case CPU_PPC_7450: /* PowerPC 7450 */
2312 case CPU_PPC_7450b:
2313 case CPU_PPC_7451: /* PowerPC 7451 */
2314 case CPU_PPC_7451G:
2315 case CPU_PPC_7455: /* PowerPC 7455 */
2316 case CPU_PPC_7455F:
2317 case CPU_PPC_7455G:
2318 case CPU_PPC_7457: /* PowerPC 7457 */
2319 case CPU_PPC_7457C:
2320 case CPU_PPC_7457A: /* PowerPC 7457A */
2321 break;
2322#endif
2323
426613db
JM		 2324 /* 64 bits PowerPC */
2325#if defined (TARGET_PPC64)
76a66253 2326#if defined (TODO)
76a66253
JM		 2327 case CPU_PPC_620: /* PowerPC 620 */
2328 case CPU_PPC_630: /* PowerPC 630 (Power 3) */
2329 case CPU_PPC_631: /* PowerPC 631 (Power 3+) */
2330 case CPU_PPC_POWER4: /* Power 4 */
2331 case CPU_PPC_POWER4P: /* Power 4+ */
2332 case CPU_PPC_POWER5: /* Power 5 */
2333 case CPU_PPC_POWER5P: /* Power 5+ */
426613db 2334#endif
76a66253
JM		 2335 case CPU_PPC_970: /* PowerPC 970 */
2336 case CPU_PPC_970FX10: /* PowerPC 970 FX */
2337 case CPU_PPC_970FX20:
2338 case CPU_PPC_970FX21:
2339 case CPU_PPC_970FX30:
2340 case CPU_PPC_970FX31:
2341 case CPU_PPC_970MP10: /* PowerPC 970 MP */
2342 case CPU_PPC_970MP11:
426613db 2343#if defined (TODO)
76a66253
JM		 2344 case CPU_PPC_CELL10: /* Cell family */
2345 case CPU_PPC_CELL20:
2346 case CPU_PPC_CELL30:
2347 case CPU_PPC_CELL31:
426613db
JM		 2348#endif
2349#if defined (TODO)
76a66253
JM		 2350 case CPU_PPC_RS64: /* Apache (RS64/A35) */
2351 case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
2352 case CPU_PPC_RS64III: /* Pulsar (RS64-III) */
2353 case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */
76a66253 2354#endif
426613db
JM		 2355 break;
2356#endif /* defined (TARGET_PPC64) */
76a66253
JM		 2357
2358#if defined (TODO)
2359 /* POWER */
2360 case CPU_POWER: /* POWER */
2361 case CPU_POWER2: /* POWER2 */
2362 break;
2363#endif
2364
2365 default:
2366 gen_spr_generic(env);
e9df014c 2367 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2368 break;
2369 }
2370 if (env->nb_BATs == -1)
2371 env->nb_BATs = 4;
2372 /* Allocate TLBs buffer when needed */
2373 if (env->nb_tlb != 0) {
2374 int nb_tlb = env->nb_tlb;
2375 if (env->id_tlbs != 0)
2376 nb_tlb *= 2;
2377 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2378 /* Pre-compute some useful values */
2379 env->tlb_per_way = env->nb_tlb / env->nb_ways;
2380 }
2381}
2382
2383#if defined(PPC_DUMP_CPU)
2384static void dump_sprs (CPUPPCState *env)
2385{
2386 ppc_spr_t *spr;
2387 uint32_t pvr = env->spr[SPR_PVR];
2388 uint32_t sr, sw, ur, uw;
2389 int i, j, n;
2390
2391 printf("* SPRs for PVR=%08x\n", pvr);
2392 for (i = 0; i < 32; i++) {
2393 for (j = 0; j < 32; j++) {
2394 n = (i << 5) | j;
2395 spr = &env->spr_cb[n];
2396#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 2397 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2398 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
76a66253
JM		 2399#else
2400 sw = 0;
2401 sr = 0;
2402#endif
3fc6c082
FB		 2403 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2404 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2405 if (sw || sr || uw || ur) {
2406 printf("%4d (%03x) %8s s%c%c u%c%c\n",
2407 (i << 5) | j, (i << 5) | j, spr->name,
2408 sw ? 'w' : '-', sr ? 'r' : '-',
2409 uw ? 'w' : '-', ur ? 'r' : '-');
2410 }
2411 }
2412 }
2413 fflush(stdout);
2414 fflush(stderr);
2415}
2416#endif
2417
2418/*****************************************************************************/
2419#include <stdlib.h>
2420#include <string.h>
2421
2422int fflush (FILE *stream);
2423
2424/* Opcode types */
2425enum {
2426 PPC_DIRECT = 0, /* Opcode routine */
2427 PPC_INDIRECT = 1, /* Indirect opcode table */
2428};
2429
2430static inline int is_indirect_opcode (void *handler)
2431{
2432 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2433}
2434
2435static inline opc_handler_t **ind_table(void *handler)
2436{
2437 return (opc_handler_t **)((unsigned long)handler & ~3);
2438}
2439
2440/* Instruction table creation */
2441/* Opcodes tables creation */
2442static void fill_new_table (opc_handler_t **table, int len)
2443{
2444 int i;
2445
2446 for (i = 0; i < len; i++)
2447 table[i] = &invalid_handler;
2448}
2449
2450static int create_new_table (opc_handler_t **table, unsigned char idx)
2451{
2452 opc_handler_t **tmp;
2453
2454 tmp = malloc(0x20 * sizeof(opc_handler_t));
2455 if (tmp == NULL)
2456 return -1;
2457 fill_new_table(tmp, 0x20);
2458 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2459
2460 return 0;
2461}
2462
2463static int insert_in_table (opc_handler_t **table, unsigned char idx,
2464 opc_handler_t *handler)
2465{
2466 if (table[idx] != &invalid_handler)
2467 return -1;
2468 table[idx] = handler;
2469
2470 return 0;
2471}
2472
2473static int register_direct_insn (opc_handler_t **ppc_opcodes,
2474 unsigned char idx, opc_handler_t *handler)
2475{
2476 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2477 printf("*** ERROR: opcode %02x already assigned in main "
76a66253 2478 "opcode table\n", idx);
3fc6c082
FB		 2479 return -1;
2480 }
2481
2482 return 0;
2483}
2484
2485static int register_ind_in_table (opc_handler_t **table,
2486 unsigned char idx1, unsigned char idx2,
2487 opc_handler_t *handler)
2488{
2489 if (table[idx1] == &invalid_handler) {
2490 if (create_new_table(table, idx1) < 0) {
2491 printf("*** ERROR: unable to create indirect table "
76a66253 2492 "idx=%02x\n", idx1);
3fc6c082
FB		 2493 return -1;
2494 }
2495 } else {
2496 if (!is_indirect_opcode(table[idx1])) {
2497 printf("*** ERROR: idx %02x already assigned to a direct "
76a66253 2498 "opcode\n", idx1);
3fc6c082
FB		 2499 return -1;
2500 }
2501 }
2502 if (handler != NULL &&
2503 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2504 printf("*** ERROR: opcode %02x already assigned in "
76a66253 2505 "opcode table %02x\n", idx2, idx1);
3fc6c082
FB		 2506 return -1;
2507 }
2508
2509 return 0;
2510}
2511
2512static int register_ind_insn (opc_handler_t **ppc_opcodes,
2513 unsigned char idx1, unsigned char idx2,
76a66253 2514 opc_handler_t *handler)
3fc6c082
FB		 2515{
2516 int ret;
2517
2518 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2519
2520 return ret;
2521}
2522
2523static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2524 unsigned char idx1, unsigned char idx2,
76a66253 2525 unsigned char idx3, opc_handler_t *handler)
3fc6c082
FB		 2526{
2527 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2528 printf("*** ERROR: unable to join indirect table idx "
76a66253 2529 "[%02x-%02x]\n", idx1, idx2);
3fc6c082
FB		 2530 return -1;
2531 }
2532 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2533 handler) < 0) {
2534 printf("*** ERROR: unable to insert opcode "
76a66253 2535 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
3fc6c082
FB		 2536 return -1;
2537 }
2538
2539 return 0;
2540}
2541
2542static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2543{
2544 if (insn->opc2 != 0xFF) {
2545 if (insn->opc3 != 0xFF) {
2546 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2547 insn->opc3, &insn->handler) < 0)
2548 return -1;
2549 } else {
2550 if (register_ind_insn(ppc_opcodes, insn->opc1,
2551 insn->opc2, &insn->handler) < 0)
2552 return -1;
2553 }
2554 } else {
2555 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2556 return -1;
2557 }
2558
2559 return 0;
2560}
2561
2562static int test_opcode_table (opc_handler_t **table, int len)
2563{
2564 int i, count, tmp;
2565
2566 for (i = 0, count = 0; i < len; i++) {
2567 /* Consistency fixup */
2568 if (table[i] == NULL)
2569 table[i] = &invalid_handler;
2570 if (table[i] != &invalid_handler) {
2571 if (is_indirect_opcode(table[i])) {
2572 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2573 if (tmp == 0) {
2574 free(table[i]);
2575 table[i] = &invalid_handler;
2576 } else {
2577 count++;
2578 }
2579 } else {
2580 count++;
2581 }
2582 }
2583 }
2584
2585 return count;
2586}
2587
2588static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2589{
2590 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2591 printf("*** WARNING: no opcode defined !\n");
2592}
2593
2594/*****************************************************************************/
2595static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2596{
2597 opcode_t *opc, *start, *end;
2598
2599 fill_new_table(env->opcodes, 0x40);
2600#if defined(PPC_DUMP_CPU)
1b9eb036 2601 printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
0487d6a8 2602 " %08x\n",
76a66253 2603 def->pvr, def->name, def->insns_flags, def->flags);
3fc6c082
FB		 2604#endif
2605 if (&opc_start < &opc_end) {
76a66253
JM		 2606 start = &opc_start;
2607 end = &opc_end;
3fc6c082 2608 } else {
76a66253
JM		 2609 start = &opc_end;
2610 end = &opc_start;
3fc6c082
FB		 2611 }
2612 for (opc = start + 1; opc != end; opc++) {
2613 if ((opc->handler.type & def->insns_flags) != 0) {
2614 if (register_insn(env->opcodes, opc) < 0) {
76a66253
JM		 2615 printf("*** ERROR initializing PowerPC instruction "
2616 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2617 opc->opc3);
3fc6c082
FB		 2618 return -1;
2619 }
2620#if defined(PPC_DUMP_CPU)
2621 if (opc1 != 0x00) {
2622 if (opc->opc3 == 0xFF) {
2623 if (opc->opc2 == 0xFF) {
2624 printf(" %02x -- -- (%2d ----) : %s\n",
2625 opc->opc1, opc->opc1, opc->oname);
2626 } else {
2627 printf(" %02x %02x -- (%2d %4d) : %s\n",
2628 opc->opc1, opc->opc2, opc->opc1, opc->opc2,
76a66253 2629 opc->oname);
3fc6c082
FB		 2630 }
2631 } else {
2632 printf(" %02x %02x %02x (%2d %4d) : %s\n",
2633 opc->opc1, opc->opc2, opc->opc3,
2634 opc->opc1, (opc->opc3 << 5) | opc->opc2,
2635 opc->oname);
2636 }
2637 }
2638#endif
2639 }
2640 }
2641 fix_opcode_tables(env->opcodes);
2642 fflush(stdout);
2643 fflush(stderr);
2644
2645 return 0;
2646}
2647
2648int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2649{
2650 env->msr_mask = def->msr_mask;
2651 env->flags = def->flags;
76a66253 2652 if (create_ppc_opcodes(env, def) < 0)
3fc6c082 2653 return -1;
3fc6c082
FB		 2654 init_ppc_proc(env, def);
2655#if defined(PPC_DUMP_CPU)
2656 dump_sprs(env);
76a66253
JM		 2657 if (env->tlb != NULL) {
2658 printf("%d %s TLB in %d ways\n", env->nb_tlb,
2659 env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2660 }
3fc6c082 2661#endif
3fc6c082
FB		 2662
2663 return 0;
2664}
2665
76a66253
JM		 2666void do_compute_hflags (CPUPPCState *env);
2667CPUPPCState *cpu_ppc_init (void)
3fc6c082
FB		 2668{
2669 CPUPPCState *env;
2670
3fc6c082
FB		 2671 env = qemu_mallocz(sizeof(CPUPPCState));
2672 if (!env)
2673 return NULL;
173d6cfe 2674 cpu_exec_init(env);
3fc6c082
FB		 2675 tlb_flush(env, 1);
2676#if defined (DO_SINGLE_STEP) && 0
2677 /* Single step trace mode */
2678 msr_se = 1;
2679 msr_be = 1;
2680#endif
2681 msr_fp = 1; /* Allow floating point exceptions */
2682 msr_me = 1; /* Allow machine check exceptions */
2683#if defined(CONFIG_USER_ONLY)
2684 msr_pr = 1;
2685#else
2686 env->nip = 0xFFFFFFFC;
2687#endif
2688 do_compute_hflags(env);
2689 env->reserve = -1;
3fc6c082
FB		 2690 return env;
2691}
2692
2693void cpu_ppc_close(CPUPPCState *env)
2694{
2695 /* Should also remove all opcode tables... */
2696 free(env);
2697}
2698
2699/*****************************************************************************/
2700/* PowerPC CPU definitions */
2701static ppc_def_t ppc_defs[] =
3fc6c082 2702 {
76a66253
JM		 2703 /* Embedded PowerPC */
2704#if defined (TODO)
2705 /* PowerPC 401 */
2706 {
2707 .name = "401",
2708 .pvr = CPU_PPC_401,
2709 .pvr_mask = 0xFFFF0000,
2710 .insns_flags = PPC_INSNS_401,
2711 .flags = PPC_FLAGS_401,
2712 .msr_mask = xxx,
2713 },
3fc6c082
FB		 2714#endif
2715#if defined (TODO)
76a66253
JM		 2716 /* IOP480 (401 microcontroler) */
2717 {
2718 .name = "iop480",
2719 .pvr = CPU_PPC_IOP480,
2720 .pvr_mask = 0xFFFF0000,
2721 .insns_flags = PPC_INSNS_401,
2722 .flags = PPC_FLAGS_401,
2723 .msr_mask = xxx,
2724 },
3fc6c082
FB		 2725#endif
2726#if defined (TODO)
76a66253
JM		 2727 /* IBM Processor for Network Resources */
2728 {
2729 .name = "Cobra",
2730 .pvr = CPU_PPC_COBRA,
2731 .pvr_mask = 0xFFFF0000,
2732 .insns_flags = PPC_INSNS_401,
2733 .flags = PPC_FLAGS_401,
2734 .msr_mask = xxx,
2735 },
3fc6c082
FB		 2736#endif
2737#if defined (TODO)
76a66253
JM		 2738 /* Generic PowerPC 403 */
2739 {
2740 .name = "403",
2741 .pvr = CPU_PPC_403,
2742 .pvr_mask = 0xFFFFFF00,
2743 .insns_flags = PPC_INSNS_403,
2744 .flags = PPC_FLAGS_403,
2745 .msr_mask = 0x000000000007D23D,
2746 },
3fc6c082
FB		 2747#endif
2748#if defined (TODO)
76a66253
JM		 2749 /* PowerPC 403 GA */
2750 {
2751 .name = "403ga",
2752 .pvr = CPU_PPC_403GA,
2753 .pvr_mask = 0xFFFFFF00,
2754 .insns_flags = PPC_INSNS_403,
2755 .flags = PPC_FLAGS_403,
2756 .msr_mask = 0x000000000007D23D,
2757 },
3fc6c082
FB		 2758#endif
2759#if defined (TODO)
76a66253
JM		 2760 /* PowerPC 403 GB */
2761 {
2762 .name = "403gb",
2763 .pvr = CPU_PPC_403GB,
2764 .pvr_mask = 0xFFFFFF00,
2765 .insns_flags = PPC_INSNS_403,
2766 .flags = PPC_FLAGS_403,
2767 .msr_mask = 0x000000000007D23D,
2768 },
3fc6c082
FB		 2769#endif
2770#if defined (TODO)
76a66253
JM		 2771 /* PowerPC 403 GC */
2772 {
2773 .name = "403gc",
2774 .pvr = CPU_PPC_403GC,
2775 .pvr_mask = 0xFFFFFF00,
2776 .insns_flags = PPC_INSNS_403,
2777 .flags = PPC_FLAGS_403,
2778 .msr_mask = 0x000000000007D23D,
2779 },
3fc6c082
FB		 2780#endif
2781#if defined (TODO)
76a66253
JM		 2782 /* PowerPC 403 GCX */
2783 {
2784 .name = "403gcx",
2785 .pvr = CPU_PPC_403GCX,
2786 .pvr_mask = 0xFFFFFF00,
2787 .insns_flags = PPC_INSNS_403,
2788 .flags = PPC_FLAGS_403,
2789 .msr_mask = 0x000000000007D23D,
2790 },
3fc6c082
FB		 2791#endif
2792#if defined (TODO)
76a66253
JM		 2793 /* Generic PowerPC 405 */
2794 {
2795 .name = "405",
2796 .pvr = CPU_PPC_405,
2797 .pvr_mask = 0xFFFF0000,
2798 .insns_flags = PPC_INSNS_405,
2799 .flags = PPC_FLAGS_405,
2800 .msr_mask = 0x00000000020EFF30,
2801 },
3fc6c082
FB		 2802#endif
2803#if defined (TODO)
76a66253
JM		 2804 /* PowerPC 405 CR */
2805 {
2806 .name = "405cr",
2807 .pvr = CPU_PPC_405,
2808 .pvr_mask = 0xFFFF0000,
2809 .insns_flags = PPC_INSNS_405,
2810 .flags = PPC_FLAGS_405,
2811 .msr_mask = 0x00000000020EFF30,
2812 },
3fc6c082
FB		 2813#endif
2814#if defined (TODO)
76a66253
JM		 2815 /* PowerPC 405 GP */
2816 {
2817 .name = "405gp",
2818 .pvr = CPU_PPC_405,
2819 .pvr_mask = 0xFFFF0000,
2820 .insns_flags = PPC_INSNS_405,
2821 .flags = PPC_FLAGS_405,
2822 .msr_mask = 0x00000000020EFF30,
2823 },
3fc6c082
FB		 2824#endif
2825#if defined (TODO)
76a66253
JM		 2826 /* PowerPC 405 EP */
2827 {
2828 .name = "405ep",
2829 .pvr = CPU_PPC_405EP,
2830 .pvr_mask = 0xFFFF0000,
2831 .insns_flags = PPC_INSNS_405,
2832 .flags = PPC_FLAGS_405,
2833 .msr_mask = 0x00000000020EFF30,
2834 },
3fc6c082
FB		 2835#endif
2836#if defined (TODO)
76a66253
JM		 2837 /* PowerPC 405 GPR */
2838 {
2839 .name = "405gpr",
2840 .pvr = CPU_PPC_405GPR,
2841 .pvr_mask = 0xFFFF0000,
2842 .insns_flags = PPC_INSNS_405,
2843 .flags = PPC_FLAGS_405,
2844 .msr_mask = 0x00000000020EFF30,
2845 },
3fc6c082
FB		 2846#endif
2847#if defined (TODO)
76a66253
JM		 2848 /* PowerPC 405 D2 */
2849 {
2850 .name = "405d2",
2851 .pvr = CPU_PPC_405D2,
2852 .pvr_mask = 0xFFFF0000,
2853 .insns_flags = PPC_INSNS_405,
2854 .flags = PPC_FLAGS_405,
2855 .msr_mask = 0x00000000020EFF30,
2856 },
3fc6c082
FB		 2857#endif
2858#if defined (TODO)
76a66253
JM		 2859 /* PowerPC 405 D4 */
2860 {
2861 .name = "405d4",
2862 .pvr = CPU_PPC_405D4,
2863 .pvr_mask = 0xFFFF0000,
2864 .insns_flags = PPC_INSNS_405,
2865 .flags = PPC_FLAGS_405,
2866 .msr_mask = 0x00000000020EFF30,
2867 },
3fc6c082
FB		 2868#endif
2869#if defined (TODO)
76a66253
JM		 2870 /* Npe405 H */
2871 {
2872 .name = "Npe405H",
2873 .pvr = CPU_PPC_NPE405H,
2874 .pvr_mask = 0xFFFF0000,
2875 .insns_flags = PPC_INSNS_405,
2876 .flags = PPC_FLAGS_405,
2877 .msr_mask = 0x00000000020EFF30,
2878 },
3fc6c082
FB		 2879#endif
2880#if defined (TODO)
76a66253
JM		 2881 /* Npe405 L */
2882 {
2883 .name = "Npe405L",
2884 .pvr = CPU_PPC_NPE405L,
2885 .pvr_mask = 0xFFFF0000,
2886 .insns_flags = PPC_INSNS_405,
2887 .flags = PPC_FLAGS_405,
2888 .msr_mask = 0x00000000020EFF30,
2889 },
3fc6c082
FB		 2890#endif
2891#if defined (TODO)
76a66253
JM		 2892 /* STB010000 */
2893 {
2894 .name = "STB01000",
2895 .pvr = CPU_PPC_STB01000,
2896 .pvr_mask = 0xFFFF0000,
2897 .insns_flags = PPC_INSNS_405,
2898 .flags = PPC_FLAGS_405,
2899 .msr_mask = 0x00000000020EFF30,
2900 },
3fc6c082
FB		 2901#endif
2902#if defined (TODO)
76a66253
JM		 2903 /* STB01010 */
2904 {
2905 .name = "STB01010",
2906 .pvr = CPU_PPC_STB01010,
2907 .pvr_mask = 0xFFFF0000,
2908 .insns_flags = PPC_INSNS_405,
2909 .flags = PPC_FLAGS_405,
2910 .msr_mask = 0x00000000020EFF30,
2911 },
3fc6c082
FB		 2912#endif
2913#if defined (TODO)
76a66253
JM		 2914 /* STB0210 */
2915 {
2916 .name = "STB0210",
2917 .pvr = CPU_PPC_STB0210,
2918 .pvr_mask = 0xFFFF0000,
2919 .insns_flags = PPC_INSNS_405,
2920 .flags = PPC_FLAGS_405,
2921 .msr_mask = 0x00000000020EFF30,
2922 },
3fc6c082 2923#endif
3fc6c082 2924#if defined (TODO)
76a66253
JM		 2925 /* STB03xx */
2926 {
2927 .name = "STB03",
2928 .pvr = CPU_PPC_STB03,
2929 .pvr_mask = 0xFFFF0000,
2930 .insns_flags = PPC_INSNS_405,
2931 .flags = PPC_FLAGS_405,
2932 .msr_mask = 0x00000000020EFF30,
2933 },
3fc6c082
FB		 2934#endif
2935#if defined (TODO)
76a66253
JM		 2936 /* STB043x */
2937 {
2938 .name = "STB043",
2939 .pvr = CPU_PPC_STB043,
2940 .pvr_mask = 0xFFFF0000,
2941 .insns_flags = PPC_INSNS_405,
2942 .flags = PPC_FLAGS_405,
2943 .msr_mask = 0x00000000020EFF30,
2944 },
3fc6c082
FB		 2945#endif
2946#if defined (TODO)
76a66253
JM		 2947 /* STB045x */
2948 {
2949 .name = "STB045",
2950 .pvr = CPU_PPC_STB045,
2951 .pvr_mask = 0xFFFF0000,
2952 .insns_flags = PPC_INSNS_405,
2953 .flags = PPC_FLAGS_405,
2954 .msr_mask = 0x00000000020EFF30,
2955 },
3fc6c082
FB		 2956#endif
2957#if defined (TODO)
76a66253
JM		 2958 /* STB25xx */
2959 {
2960 .name = "STB25",
2961 .pvr = CPU_PPC_STB25,
2962 .pvr_mask = 0xFFFF0000,
2963 .insns_flags = PPC_INSNS_405,
2964 .flags = PPC_FLAGS_405,
2965 .msr_mask = 0x00000000020EFF30,
2966 },
3fc6c082
FB		 2967#endif
2968#if defined (TODO)
76a66253
JM		 2969 /* STB130 */
2970 {
2971 .name = "STB130",
2972 .pvr = CPU_PPC_STB130,
2973 .pvr_mask = 0xFFFF0000,
2974 .insns_flags = PPC_INSNS_405,
2975 .flags = PPC_FLAGS_405,
2976 .msr_mask = 0x00000000020EFF30,
2977 },
3fc6c082 2978#endif
76a66253 2979 /* Xilinx PowerPC 405 cores */
3fc6c082 2980#if defined (TODO)
76a66253
JM		 2981 {
2982 .name = "x2vp4",
2983 .pvr = CPU_PPC_X2VP4,
2984 .pvr_mask = 0xFFFF0000,
2985 .insns_flags = PPC_INSNS_405,
2986 .flags = PPC_FLAGS_405,
2987 .msr_mask = 0x00000000020EFF30,
2988 },
2989 {
2990 .name = "x2vp7",
2991 .pvr = CPU_PPC_X2VP7,
2992 .pvr_mask = 0xFFFF0000,
2993 .insns_flags = PPC_INSNS_405,
2994 .flags = PPC_FLAGS_405,
2995 .msr_mask = 0x00000000020EFF30,
2996 },
2997 {
2998 .name = "x2vp20",
2999 .pvr = CPU_PPC_X2VP20,
3000 .pvr_mask = 0xFFFF0000,
3001 .insns_flags = PPC_INSNS_405,
3002 .flags = PPC_FLAGS_405,
3003 .msr_mask = 0x00000000020EFF30,
3004 },
3005 {
3006 .name = "x2vp50",
3007 .pvr = CPU_PPC_X2VP50,
3008 .pvr_mask = 0xFFFF0000,
3009 .insns_flags = PPC_INSNS_405,
3010 .flags = PPC_FLAGS_405,
3011 .msr_mask = 0x00000000020EFF30,
3012 },
3fc6c082
FB		 3013#endif
3014#if defined (TODO)
76a66253
JM		 3015 /* PowerPC 440 EP */
3016 {
3017 .name = "440ep",
3018 .pvr = CPU_PPC_440EP,
3019 .pvr_mask = 0xFFFF0000,
3020 .insns_flags = PPC_INSNS_440,
3021 .flags = PPC_FLAGS_440,
3022 .msr_mask = 0x000000000006D630,
3023 },
3fc6c082
FB		 3024#endif
3025#if defined (TODO)
76a66253
JM		 3026 /* PowerPC 440 GR */
3027 {
3028 .name = "440gr",
3029 .pvr = CPU_PPC_440GR,
3030 .pvr_mask = 0xFFFF0000,
3031 .insns_flags = PPC_INSNS_440,
3032 .flags = PPC_FLAGS_440,
3033 .msr_mask = 0x000000000006D630,
3034 },
3fc6c082
FB		 3035#endif
3036#if defined (TODO)
76a66253
JM		 3037 /* PowerPC 440 GP */
3038 {
3039 .name = "440gp",
3040 .pvr = CPU_PPC_440GP,
3041 .pvr_mask = 0xFFFFFF00,
3042 .insns_flags = PPC_INSNS_440,
3043 .flags = PPC_FLAGS_440,
3044 .msr_mask = 0x000000000006D630,
3045 },
3fc6c082
FB		 3046#endif
3047#if defined (TODO)
76a66253
JM		 3048 /* PowerPC 440 GX */
3049 {
3050 .name = "440gx",
3051 .pvr = CPU_PPC_440GX,
3052 .pvr_mask = 0xFFFF0000,
3053 .insns_flags = PPC_INSNS_405,
3054 .flags = PPC_FLAGS_440,
3055 .msr_mask = 0x000000000006D630,
3056 },
3fc6c082
FB		 3057#endif
3058#if defined (TODO)
76a66253
JM		 3059 /* PowerPC 440 GXc */
3060 {
3061 .name = "440gxc",
3062 .pvr = CPU_PPC_440GXC,
3063 .pvr_mask = 0xFFFF0000,
3064 .insns_flags = PPC_INSNS_405,
3065 .flags = PPC_FLAGS_440,
3066 .msr_mask = 0x000000000006D630,
3067 },
3fc6c082
FB		 3068#endif
3069#if defined (TODO)
76a66253
JM		 3070 /* PowerPC 440 GXf */
3071 {
3072 .name = "440gxf",
3073 .pvr = CPU_PPC_440GXF,
3074 .pvr_mask = 0xFFFF0000,
3075 .insns_flags = PPC_INSNS_405,
3076 .flags = PPC_FLAGS_440,
3077 .msr_mask = 0x000000000006D630,
3078 },
3fc6c082 3079#endif
3fc6c082 3080#if defined (TODO)
76a66253
JM		 3081 /* PowerPC 440 SP */
3082 {
3083 .name = "440sp",
3084 .pvr = CPU_PPC_440SP,
3085 .pvr_mask = 0xFFFF0000,
3086 .insns_flags = PPC_INSNS_405,
3087 .flags = PPC_FLAGS_440,
3088 .msr_mask = 0x000000000006D630,
3089 },
3fc6c082
FB		 3090#endif
3091#if defined (TODO)
76a66253
JM		 3092 /* PowerPC 440 SP2 */
3093 {
3094 .name = "440sp2",
3095 .pvr = CPU_PPC_440SP2,
3096 .pvr_mask = 0xFFFF0000,
3097 .insns_flags = PPC_INSNS_405,
3098 .flags = PPC_FLAGS_440,
3099 .msr_mask = 0x000000000006D630,
3100 },
3fc6c082
FB		 3101#endif
3102#if defined (TODO)
76a66253
JM		 3103 /* PowerPC 440 SPE */
3104 {
3105 .name = "440spe",
3106 .pvr = CPU_PPC_440SPE,
3107 .pvr_mask = 0xFFFF0000,
3108 .insns_flags = PPC_INSNS_405,
3109 .flags = PPC_FLAGS_440,
3110 .msr_mask = 0x000000000006D630,
3111 },
3fc6c082 3112#endif
76a66253
JM		 3113 /* Fake generic BookE PowerPC */
3114 {
3115 .name = "BookE",
3116 .pvr = CPU_PPC_e500,
3117 .pvr_mask = 0xFFFFFFFF,
3118 .insns_flags = PPC_INSNS_BOOKE,
3119 .flags = PPC_FLAGS_BOOKE,
3120 .msr_mask = 0x000000000006D630,
3121 },
3122 /* PowerPC 460 cores - TODO */
3123 /* PowerPC MPC 5xx cores - TODO */
3124 /* PowerPC MPC 8xx cores - TODO */
3125 /* PowerPC MPC 8xxx cores - TODO */
3126 /* e200 cores - TODO */
3127 /* e500 cores - TODO */
3128 /* e600 cores - TODO */
3129
3130 /* 32 bits "classic" PowerPC */
3fc6c082 3131#if defined (TODO)
76a66253
JM		 3132 /* PowerPC 601 */
3133 {
3134 .name = "601",
3135 .pvr = CPU_PPC_601,
3136 .pvr_mask = 0xFFFF0000,
3137 .insns_flags = PPC_INSNS_601,
3138 .flags = PPC_FLAGS_601,
3139 .msr_mask = 0x000000000000FD70,
3140 },
3fc6c082
FB		 3141#endif
3142#if defined (TODO)
76a66253
JM		 3143 /* PowerPC 602 */
3144 {
3145 .name = "602",
3146 .pvr = CPU_PPC_602,
3147 .pvr_mask = 0xFFFF0000,
3148 .insns_flags = PPC_INSNS_602,
3149 .flags = PPC_FLAGS_602,
3150 .msr_mask = 0x0000000000C7FF73,
3151 },
3fc6c082 3152#endif
76a66253
JM		 3153 /* PowerPC 603 */
3154 {
3155 .name = "603",
3156 .pvr = CPU_PPC_603,
3157 .pvr_mask = 0xFFFFFFFF,
3158 .insns_flags = PPC_INSNS_603,
3159 .flags = PPC_FLAGS_603,
3160 .msr_mask = 0x000000000007FF73,
3161 },
3162 /* PowerPC 603e */
3163 {
3164 .name = "603e",
3165 .pvr = CPU_PPC_603E,
3166 .pvr_mask = 0xFFFFFFFF,
3167 .insns_flags = PPC_INSNS_603,
3168 .flags = PPC_FLAGS_603,
3169 .msr_mask = 0x000000000007FF73,
3170 },
3171 {
3172 .name = "Stretch",
3173 .pvr = CPU_PPC_603E,
3174 .pvr_mask = 0xFFFFFFFF,
3175 .insns_flags = PPC_INSNS_603,
3176 .flags = PPC_FLAGS_603,
3177 .msr_mask = 0x000000000007FF73,
3178 },
3179 /* PowerPC 603p */
3180 {
3181 .name = "603p",
3182 .pvr = CPU_PPC_603P,
3183 .pvr_mask = 0xFFFFFFFF,
3184 .insns_flags = PPC_INSNS_603,
3185 .flags = PPC_FLAGS_603,
3186 .msr_mask = 0x000000000007FF73,
3187 },
3188 /* PowerPC 603e7 */
3189 {
3190 .name = "603e7",
3191 .pvr = CPU_PPC_603E7,
3192 .pvr_mask = 0xFFFFFFFF,
3193 .insns_flags = PPC_INSNS_603,
3194 .flags = PPC_FLAGS_603,
3195 .msr_mask = 0x000000000007FF73,
3196 },
3197 /* PowerPC 603e7v */
3198 {
3199 .name = "603e7v",
3200 .pvr = CPU_PPC_603E7v,
3201 .pvr_mask = 0xFFFFFFFF,
3202 .insns_flags = PPC_INSNS_603,
3203 .flags = PPC_FLAGS_603,
3204 .msr_mask = 0x000000000007FF73,
3205 },
3206 /* PowerPC 603e7v2 */
3207 {
3208 .name = "603e7v2",
3209 .pvr = CPU_PPC_603E7v2,
3210 .pvr_mask = 0xFFFFFFFF,
3211 .insns_flags = PPC_INSNS_603,
3212 .flags = PPC_FLAGS_603,
3213 .msr_mask = 0x000000000007FF73,
3214 },
3215 /* PowerPC 603r */
3216 {
3217 .name = "603r",
3218 .pvr = CPU_PPC_603R,
3219 .pvr_mask = 0xFFFFFFFF,
3220 .insns_flags = PPC_INSNS_603,
3221 .flags = PPC_FLAGS_603,
3222 .msr_mask = 0x000000000007FF73,
3223 },
3224 {
3225 .name = "Goldeneye",
3226 .pvr = CPU_PPC_603R,
3227 .pvr_mask = 0xFFFFFFFF,
3228 .insns_flags = PPC_INSNS_603,
3229 .flags = PPC_FLAGS_603,
3230 .msr_mask = 0x000000000007FF73,
3231 },
3fc6c082 3232#if defined (TODO)
76a66253
JM		 3233 /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3234 {
3235 .name = "G2",
3236 .pvr = CPU_PPC_G2,
3237 .pvr_mask = 0xFFFF0000,
3238 .insns_flags = PPC_INSNS_G2,
3239 .flags = PPC_FLAGS_G2,
3240 .msr_mask = 0x000000000006FFF2,
3241 },
3242 {
3243 .name = "G2h4",
3244 .pvr = CPU_PPC_G2H4,
3245 .pvr_mask = 0xFFFF0000,
3246 .insns_flags = PPC_INSNS_G2,
3247 .flags = PPC_FLAGS_G2,
3248 .msr_mask = 0x000000000006FFF2,
3249 },
3250 {
3251 .name = "G2gp",
3252 .pvr = CPU_PPC_G2gp,
3253 .pvr_mask = 0xFFFF0000,
3254 .insns_flags = PPC_INSNS_G2,
3255 .flags = PPC_FLAGS_G2,
3256 .msr_mask = 0x000000000006FFF2,
3257 },
3258 {
3259 .name = "G2ls",
3260 .pvr = CPU_PPC_G2ls,
3261 .pvr_mask = 0xFFFF0000,
3262 .insns_flags = PPC_INSNS_G2,
3263 .flags = PPC_FLAGS_G2,
3264 .msr_mask = 0x000000000006FFF2,
3265 },
3266 { /* Same as G2, with LE mode support */
3267 .name = "G2le",
3268 .pvr = CPU_PPC_G2LE,
3269 .pvr_mask = 0xFFFF0000,
3270 .insns_flags = PPC_INSNS_G2,
3271 .flags = PPC_FLAGS_G2,
3272 .msr_mask = 0x000000000007FFF3,
3273 },
3274 {
3275 .name = "G2legp",
3276 .pvr = CPU_PPC_G2LEgp,
3277 .pvr_mask = 0xFFFF0000,
3278 .insns_flags = PPC_INSNS_G2,
3279 .flags = PPC_FLAGS_G2,
3280 .msr_mask = 0x000000000007FFF3,
3281 },
3282 {
3283 .name = "G2lels",
3284 .pvr = CPU_PPC_G2LEls,
3285 .pvr_mask = 0xFFFF0000,
3286 .insns_flags = PPC_INSNS_G2,
3287 .flags = PPC_FLAGS_G2,
3288 .msr_mask = 0x000000000007FFF3,
3289 },
3fc6c082 3290#endif
76a66253
JM		 3291 /* PowerPC 604 */
3292 {
3293 .name = "604",
3294 .pvr = CPU_PPC_604,
3295 .pvr_mask = 0xFFFFFFFF,
3296 .insns_flags = PPC_INSNS_604,
3297 .flags = PPC_FLAGS_604,
3298 .msr_mask = 0x000000000005FF77,
3299 },
3300 /* PowerPC 604e */
3301 {
3302 .name = "604e",
3303 .pvr = CPU_PPC_604E,
3304 .pvr_mask = 0xFFFFFFFF,
3305 .insns_flags = PPC_INSNS_604,
3306 .flags = PPC_FLAGS_604,
3307 .msr_mask = 0x000000000005FF77,
3308 },
3309 /* PowerPC 604r */
3310 {
3311 .name = "604r",
3312 .pvr = CPU_PPC_604R,
3313 .pvr_mask = 0xFFFFFFFF,
3314 .insns_flags = PPC_INSNS_604,
3315 .flags = PPC_FLAGS_604,
3316 .msr_mask = 0x000000000005FF77,
3317 },
3318 /* generic G3 */
3319 {
3320 .name = "G3",
3321 .pvr = CPU_PPC_74x,
3322 .pvr_mask = 0xFFFFFFFF,
3323 .insns_flags = PPC_INSNS_7x0,
3324 .flags = PPC_FLAGS_7x0,
3325 .msr_mask = 0x000000000007FF77,
3326 },
3327 /* MPC740 (G3) */
3328 {
3329 .name = "740",
3330 .pvr = CPU_PPC_74x,
3331 .pvr_mask = 0xFFFFFFFF,
3332 .insns_flags = PPC_INSNS_7x0,
3333 .flags = PPC_FLAGS_7x0,
3334 .msr_mask = 0x000000000007FF77,
3335 },
3336 {
3337 .name = "Arthur",
3338 .pvr = CPU_PPC_74x,
3339 .pvr_mask = 0xFFFFFFFF,
3340 .insns_flags = PPC_INSNS_7x0,
3341 .flags = PPC_FLAGS_7x0,
3342 .msr_mask = 0x000000000007FF77,
3343 },
3fc6c082 3344#if defined (TODO)
76a66253
JM		 3345 /* MPC745 (G3) */
3346 {
3347 .name = "745",
3348 .pvr = CPU_PPC_74x,
3349 .pvr_mask = 0xFFFFF000,
3350 .insns_flags = PPC_INSNS_7x5,
3351 .flags = PPC_FLAGS_7x5,
3352 .msr_mask = 0x000000000007FF77,
3353 },
3354 {
3355 .name = "Goldfinger",
3356 .pvr = CPU_PPC_74x,
3357 .pvr_mask = 0xFFFFF000,
3358 .insns_flags = PPC_INSNS_7x5,
3359 .flags = PPC_FLAGS_7x5,
3360 .msr_mask = 0x000000000007FF77,
3361 },
3fc6c082 3362#endif
76a66253
JM		 3363 /* MPC750 (G3) */
3364 {
3365 .name = "750",
3366 .pvr = CPU_PPC_74x,
3367 .pvr_mask = 0xFFFFFFFF,
3368 .insns_flags = PPC_INSNS_7x0,
3369 .flags = PPC_FLAGS_7x0,
3370 .msr_mask = 0x000000000007FF77,
3371 },
3fc6c082 3372#if defined (TODO)
76a66253
JM		 3373 /* MPC755 (G3) */
3374 {
3375 .name = "755",
3376 .pvr = CPU_PPC_755,
3377 .pvr_mask = 0xFFFFF000,
3378 .insns_flags = PPC_INSNS_7x5,
3379 .flags = PPC_FLAGS_7x5,
3380 .msr_mask = 0x000000000007FF77,
3381 },
3fc6c082 3382#endif
76a66253
JM		 3383 /* MPC740P (G3) */
3384 {
3385 .name = "740p",
3386 .pvr = CPU_PPC_74xP,
3387 .pvr_mask = 0xFFFFFFFF,
3388 .insns_flags = PPC_INSNS_7x0,
3389 .flags = PPC_FLAGS_7x0,
3390 .msr_mask = 0x000000000007FF77,
3391 },
3392 {
3393 .name = "Conan/Doyle",
3394 .pvr = CPU_PPC_74xP,
3395 .pvr_mask = 0xFFFFFFFF,
3396 .insns_flags = PPC_INSNS_7x0,
3397 .flags = PPC_FLAGS_7x0,
3398 .msr_mask = 0x000000000007FF77,
3399 },
3fc6c082 3400#if defined (TODO)
76a66253
JM		 3401 /* MPC745P (G3) */
3402 {
3403 .name = "745p",
3404 .pvr = CPU_PPC_74xP,
3405 .pvr_mask = 0xFFFFF000,
3406 .insns_flags = PPC_INSNS_7x5,
3407 .flags = PPC_FLAGS_7x5,
3408 .msr_mask = 0x000000000007FF77,
3409 },
3fc6c082 3410#endif
76a66253
JM		 3411 /* MPC750P (G3) */
3412 {
3413 .name = "750p",
3414 .pvr = CPU_PPC_74xP,
3415 .pvr_mask = 0xFFFFFFFF,
3416 .insns_flags = PPC_INSNS_7x0,
3417 .flags = PPC_FLAGS_7x0,
3418 .msr_mask = 0x000000000007FF77,
3419 },
3fc6c082 3420#if defined (TODO)
76a66253
JM		 3421 /* MPC755P (G3) */
3422 {
3423 .name = "755p",
3424 .pvr = CPU_PPC_74xP,
3425 .pvr_mask = 0xFFFFF000,
3426 .insns_flags = PPC_INSNS_7x5,
3427 .flags = PPC_FLAGS_7x5,
3428 .msr_mask = 0x000000000007FF77,
3429 },
3fc6c082 3430#endif
76a66253
JM		 3431 /* IBM 750CXe (G3 embedded) */
3432 {
3433 .name = "750cxe",
3434 .pvr = CPU_PPC_750CXE,
3435 .pvr_mask = 0xFFFFFFFF,
3436 .insns_flags = PPC_INSNS_7x0,
3437 .flags = PPC_FLAGS_7x0,
3438 .msr_mask = 0x000000000007FF77,
3439 },
3440 /* IBM 750FX (G3 embedded) */
3441 {
3442 .name = "750fx",
3443 .pvr = CPU_PPC_750FX,
3444 .pvr_mask = 0xFFFFFFFF,
3445 .insns_flags = PPC_INSNS_7x0,
3446 .flags = PPC_FLAGS_7x0,
3447 .msr_mask = 0x000000000007FF77,
3448 },
3449 /* IBM 750GX (G3 embedded) */
3450 {
3451 .name = "750gx",
3452 .pvr = CPU_PPC_750GX,
3453 .pvr_mask = 0xFFFFFFFF,
3454 .insns_flags = PPC_INSNS_7x0,
3455 .flags = PPC_FLAGS_7x0,
3456 .msr_mask = 0x000000000007FF77,
3457 },
3fc6c082 3458#if defined (TODO)
76a66253
JM		 3459 /* generic G4 */
3460 {
3461 .name = "G4",
3462 .pvr = CPU_PPC_7400,
3463 .pvr_mask = 0xFFFF0000,
3464 .insns_flags = PPC_INSNS_74xx,
3465 .flags = PPC_FLAGS_74xx,
3466 .msr_mask = 0x000000000205FF77,
3467 },
3fc6c082
FB		 3468#endif
3469#if defined (TODO)
76a66253
JM		 3470 /* PowerPC 7400 (G4) */
3471 {
3472 .name = "7400",
3473 .pvr = CPU_PPC_7400,
3474 .pvr_mask = 0xFFFF0000,
3475 .insns_flags = PPC_INSNS_74xx,
3476 .flags = PPC_FLAGS_74xx,
3477 .msr_mask = 0x000000000205FF77,
3478 },
3479 {
3480 .name = "Max",
3481 .pvr = CPU_PPC_7400,
3482 .pvr_mask = 0xFFFF0000,
3483 .insns_flags = PPC_INSNS_74xx,
3484 .flags = PPC_FLAGS_74xx,
3485 .msr_mask = 0x000000000205FF77,
3486 },
3fc6c082
FB		 3487#endif
3488#if defined (TODO)
76a66253
JM		 3489 /* PowerPC 7410 (G4) */
3490 {
3491 .name = "7410",
3492 .pvr = CPU_PPC_7410,
3493 .pvr_mask = 0xFFFF0000,
3494 .insns_flags = PPC_INSNS_74xx,
3495 .flags = PPC_FLAGS_74xx,
3496 .msr_mask = 0x000000000205FF77,
3497 },
3498 {
3499 .name = "Nitro",
3500 .pvr = CPU_PPC_7410,
3501 .pvr_mask = 0xFFFF0000,
3502 .insns_flags = PPC_INSNS_74xx,
3503 .flags = PPC_FLAGS_74xx,
3504 .msr_mask = 0x000000000205FF77,
3505 },
3fc6c082 3506#endif
76a66253
JM		 3507 /* XXX: 7441 */
3508 /* XXX: 7445 */
3509 /* XXX: 7447 */
3510 /* XXX: 7447A */
3fc6c082 3511#if defined (TODO)
76a66253
JM		 3512 /* PowerPC 7450 (G4) */
3513 {
3514 .name = "7450",
3515 .pvr = CPU_PPC_7450,
3516 .pvr_mask = 0xFFFF0000,
3517 .insns_flags = PPC_INSNS_74xx,
3518 .flags = PPC_FLAGS_74xx,
3519 .msr_mask = 0x000000000205FF77,
3520 },
3521 {
3522 .name = "Vger",
3523 .pvr = CPU_PPC_7450,
3524 .pvr_mask = 0xFFFF0000,
3525 .insns_flags = PPC_INSNS_74xx,
3526 .flags = PPC_FLAGS_74xx,
3527 .msr_mask = 0x000000000205FF77,
3528 },
3fc6c082 3529#endif
76a66253 3530 /* XXX: 7451 */
3fc6c082 3531#if defined (TODO)
76a66253
JM		 3532 /* PowerPC 7455 (G4) */
3533 {
3534 .name = "7455",
3535 .pvr = CPU_PPC_7455,
3536 .pvr_mask = 0xFFFF0000,
3537 .insns_flags = PPC_INSNS_74xx,
3538 .flags = PPC_FLAGS_74xx,
3539 .msr_mask = 0x000000000205FF77,
3540 },
3541 {
3542 .name = "Apollo 6",
3543 .pvr = CPU_PPC_7455,
3544 .pvr_mask = 0xFFFF0000,
3545 .insns_flags = PPC_INSNS_74xx,
3546 .flags = PPC_FLAGS_74xx,
3547 .msr_mask = 0x000000000205FF77,
3548 },
3fc6c082 3549#endif
3fc6c082 3550#if defined (TODO)
76a66253
JM		 3551 /* PowerPC 7457 (G4) */
3552 {
3553 .name = "7457",
3554 .pvr = CPU_PPC_7457,
3555 .pvr_mask = 0xFFFF0000,
3556 .insns_flags = PPC_INSNS_74xx,
3557 .flags = PPC_FLAGS_74xx,
3558 .msr_mask = 0x000000000205FF77,
3559 },
3560 {
3561 .name = "Apollo 7",
3562 .pvr = CPU_PPC_7457,
3563 .pvr_mask = 0xFFFF0000,
3564 .insns_flags = PPC_INSNS_74xx,
3565 .flags = PPC_FLAGS_74xx,
3566 .msr_mask = 0x000000000205FF77,
3567 },
3fc6c082
FB		 3568#endif
3569#if defined (TODO)
76a66253
JM		 3570 /* PowerPC 7457A (G4) */
3571 {
3572 .name = "7457A",
3573 .pvr = CPU_PPC_7457A,
3574 .pvr_mask = 0xFFFF0000,
3575 .insns_flags = PPC_INSNS_74xx,
3576 .flags = PPC_FLAGS_74xx,
3577 .msr_mask = 0x000000000205FF77,
3578 },
3579 {
3580 .name = "Apollo 7 PM",
3581 .pvr = CPU_PPC_7457A,
3582 .pvr_mask = 0xFFFF0000,
3583 .insns_flags = PPC_INSNS_74xx,
3584 .flags = PPC_FLAGS_74xx,
3585 .msr_mask = 0x000000000205FF77,
3586 },
3fc6c082 3587#endif
76a66253 3588 /* 64 bits PowerPC */
426613db 3589#if defined (TARGET_PPC64)
3fc6c082 3590#if defined (TODO)
76a66253
JM		 3591 /* PowerPC 620 */
3592 {
3593 .name = "620",
3594 .pvr = CPU_PPC_620,
3595 .pvr_mask = 0xFFFF0000,
3596 .insns_flags = PPC_INSNS_620,
3597 .flags = PPC_FLAGS_620,
3598 .msr_mask = 0x800000000005FF73,
3599 },
3fc6c082 3600#endif
76a66253
JM		 3601#if defined (TODO)
3602 /* PowerPC 630 (POWER3) */
3603 {
3604 .name = "630",
3605 .pvr = CPU_PPC_630,
3606 .pvr_mask = 0xFFFF0000,
3607 .insns_flags = PPC_INSNS_630,
3608 .flags = PPC_FLAGS_630,
3609 .msr_mask = xxx,
3610 }
3611 {
3612 .name = "POWER3",
3613 .pvr = CPU_PPC_630,
3614 .pvr_mask = 0xFFFF0000,
3615 .insns_flags = PPC_INSNS_630,
3616 .flags = PPC_FLAGS_630,
3617 .msr_mask = xxx,
3618 }
3619#endif
3620#if defined (TODO)
3621 /* PowerPC 631 (Power 3+)*/
3622 {
3623 .name = "631",
3624 .pvr = CPU_PPC_631,
3625 .pvr_mask = 0xFFFF0000,
3626 .insns_flags = PPC_INSNS_631,
3627 .flags = PPC_FLAGS_631,
3628 .msr_mask = xxx,
3629 },
3630 {
3631 .name = "POWER3+",
3632 .pvr = CPU_PPC_631,
3633 .pvr_mask = 0xFFFF0000,
3634 .insns_flags = PPC_INSNS_631,
3635 .flags = PPC_FLAGS_631,
3636 .msr_mask = xxx,
3637 },
3638#endif
3639#if defined (TODO)
3640 /* POWER4 */
3641 {
3642 .name = "POWER4",
3643 .pvr = CPU_PPC_POWER4,
3644 .pvr_mask = 0xFFFF0000,
3645 .insns_flags = PPC_INSNS_POWER4,
3646 .flags = PPC_FLAGS_POWER4,
3647 .msr_mask = xxx,
3648 },
3649#endif
3650#if defined (TODO)
3651 /* POWER4p */
3652 {
3653 .name = "POWER4+",
3654 .pvr = CPU_PPC_POWER4P,
3655 .pvr_mask = 0xFFFF0000,
3656 .insns_flags = PPC_INSNS_POWER4,
3657 .flags = PPC_FLAGS_POWER4,
3658 .msr_mask = xxx,
3659 },
3660#endif
3661#if defined (TODO)
3662 /* POWER5 */
3663 {
3664 .name = "POWER5",
3665 .pvr = CPU_PPC_POWER5,
3666 .pvr_mask = 0xFFFF0000,
3667 .insns_flags = PPC_INSNS_POWER5,
3668 .flags = PPC_FLAGS_POWER5,
3669 .msr_mask = xxx,
3670 },
3671#endif
3672#if defined (TODO)
3673 /* POWER5+ */
3674 {
3675 .name = "POWER5+",
3676 .pvr = CPU_PPC_POWER5P,
3677 .pvr_mask = 0xFFFF0000,
3678 .insns_flags = PPC_INSNS_POWER5,
3679 .flags = PPC_FLAGS_POWER5,
3680 .msr_mask = xxx,
3681 },
3682#endif
3683#if defined (TODO)
3684 /* PowerPC 970 */
3685 {
3686 .name = "970",
3687 .pvr = CPU_PPC_970,
3688 .pvr_mask = 0xFFFF0000,
3689 .insns_flags = PPC_INSNS_970,
3690 .flags = PPC_FLAGS_970,
3691 .msr_mask = 0x900000000204FF36,
3692 },
3693#endif
3694#if defined (TODO)
3695 /* PowerPC 970FX (G5) */
3696 {
3697 .name = "970fx",
3698 .pvr = CPU_PPC_970FX,
3699 .pvr_mask = 0xFFFF0000,
3700 .insns_flags = PPC_INSNS_970FX,
3701 .flags = PPC_FLAGS_970FX,
3702 .msr_mask = 0x800000000204FF36,
3703 },
3704#endif
3705#if defined (TODO)
3706 /* RS64 (Apache/A35) */
3707 /* This one seems to support the whole POWER2 instruction set
3708 * and the PowerPC 64 one.
3709 */
3710 {
3711 .name = "RS64",
3712 .pvr = CPU_PPC_RS64,
3713 .pvr_mask = 0xFFFF0000,
3714 .insns_flags = PPC_INSNS_RS64,
3715 .flags = PPC_FLAGS_RS64,
3716 .msr_mask = xxx,
3717 },
3718 {
3719 .name = "Apache",
3720 .pvr = CPU_PPC_RS64,
3721 .pvr_mask = 0xFFFF0000,
3722 .insns_flags = PPC_INSNS_RS64,
3723 .flags = PPC_FLAGS_RS64,
3724 .msr_mask = xxx,
3725 },
3726 {
3727 .name = "A35",
3728 .pvr = CPU_PPC_RS64,
3729 .pvr_mask = 0xFFFF0000,
3730 .insns_flags = PPC_INSNS_RS64,
3731 .flags = PPC_FLAGS_RS64,
3732 .msr_mask = xxx,
3733 },
3734#endif
3735#if defined (TODO)
3736 /* RS64-II (NorthStar/A50) */
3737 {
3738 .name = "RS64-II",
3739 .pvr = CPU_PPC_RS64II,
3740 .pvr_mask = 0xFFFF0000,
3741 .insns_flags = PPC_INSNS_RS64,
3742 .flags = PPC_FLAGS_RS64,
3743 .msr_mask = xxx,
3744 },
3745 {
3746 .name = "NortStar",
3747 .pvr = CPU_PPC_RS64II,
3748 .pvr_mask = 0xFFFF0000,
3749 .insns_flags = PPC_INSNS_RS64,
3750 .flags = PPC_FLAGS_RS64,
3751 .msr_mask = xxx,
3752 },
3753 {
3754 .name = "A50",
3755 .pvr = CPU_PPC_RS64II,
3756 .pvr_mask = 0xFFFF0000,
3757 .insns_flags = PPC_INSNS_RS64,
3758 .flags = PPC_FLAGS_RS64,
3759 .msr_mask = xxx,
3760 },
3761#endif
3762#if defined (TODO)
3763 /* RS64-III (Pulsar) */
3764 {
3765 .name = "RS64-III",
3766 .pvr = CPU_PPC_RS64III,
3767 .pvr_mask = 0xFFFF0000,
3768 .insns_flags = PPC_INSNS_RS64,
3769 .flags = PPC_FLAGS_RS64,
3770 .msr_mask = xxx,
3771 },
3772 {
3773 .name = "Pulsar",
3774 .pvr = CPU_PPC_RS64III,
3775 .pvr_mask = 0xFFFF0000,
3776 .insns_flags = PPC_INSNS_RS64,
3777 .flags = PPC_FLAGS_RS64,
3778 .msr_mask = xxx,
3779 },
3780#endif
3781#if defined (TODO)
3782 /* RS64-IV (IceStar/IStar/SStar) */
3783 {
3784 .name = "RS64-IV",
3785 .pvr = CPU_PPC_RS64IV,
3786 .pvr_mask = 0xFFFF0000,
3787 .insns_flags = PPC_INSNS_RS64,
3788 .flags = PPC_FLAGS_RS64,
3789 .msr_mask = xxx,
3790 },
3791 {
3792 .name = "IceStar",
3793 .pvr = CPU_PPC_RS64IV,
3794 .pvr_mask = 0xFFFF0000,
3795 .insns_flags = PPC_INSNS_RS64,
3796 .flags = PPC_FLAGS_RS64,
3797 .msr_mask = xxx,
3798 },
3799 {
3800 .name = "IStar",
3801 .pvr = CPU_PPC_RS64IV,
3802 .pvr_mask = 0xFFFF0000,
3803 .insns_flags = PPC_INSNS_RS64,
3804 .flags = PPC_FLAGS_RS64,
3805 .msr_mask = xxx,
3806 },
3807 {
3808 .name = "SStar",
3809 .pvr = CPU_PPC_RS64IV,
3810 .pvr_mask = 0xFFFF0000,
3811 .insns_flags = PPC_INSNS_RS64,
3812 .flags = PPC_FLAGS_RS64,
3813 .msr_mask = xxx,
3814 },
3815#endif
3816 /* POWER */
3817#if defined (TODO)
3818 /* Original POWER */
3819 {
3820 .name = "POWER",
3821 .pvr = CPU_POWER,
3822 .pvr_mask = 0xFFFF0000,
3823 .insns_flags = PPC_INSNS_POWER,
3824 .flags = PPC_FLAGS_POWER,
3825 .msr_mask = xxx,
3826 },
3827#endif
426613db 3828#endif /* defined (TARGET_PPC64) */
76a66253
JM		 3829#if defined (TODO)
3830 /* POWER2 */
3831 {
3832 .name = "POWER2",
3833 .pvr = CPU_POWER2,
3834 .pvr_mask = 0xFFFF0000,
3835 .insns_flags = PPC_INSNS_POWER,
3836 .flags = PPC_FLAGS_POWER,
3837 .msr_mask = xxx,
3838 },
3839#endif
3840 /* Generic PowerPCs */
3841#if defined (TODO)
3842 {
3843 .name = "ppc64",
3844 .pvr = CPU_PPC_970,
3845 .pvr_mask = 0xFFFF0000,
3846 .insns_flags = PPC_INSNS_PPC64,
3847 .flags = PPC_FLAGS_PPC64,
3848 .msr_mask = 0xA00000000204FF36,
3849 },
3850#endif
3851 {
3852 .name = "ppc32",
3853 .pvr = CPU_PPC_604,
3854 .pvr_mask = 0xFFFFFFFF,
3855 .insns_flags = PPC_INSNS_PPC32,
3856 .flags = PPC_FLAGS_PPC32,
3857 .msr_mask = 0x000000000005FF77,
3858 },
3859 /* Fallback */
3860 {
3861 .name = "ppc",
3862 .pvr = CPU_PPC_604,
3863 .pvr_mask = 0xFFFFFFFF,
3864 .insns_flags = PPC_INSNS_PPC32,
3865 .flags = PPC_FLAGS_PPC32,
3866 .msr_mask = 0x000000000005FF77,
3867 },
3868 };
3fc6c082
FB		 3869
3870int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3871{
3872 int i, ret;
3873
3874 ret = -1;
3875 *def = NULL;
3876 for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3877 if (strcasecmp(name, ppc_defs[i].name) == 0) {
3878 *def = &ppc_defs[i];
3879 ret = 0;
3880 break;
3881 }
3882 }
3883
3884 return ret;
3885}
3886
3887int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3888{
3889 int i, ret;
3890
3891 ret = -1;
3892 *def = NULL;
3893 for (i = 0; ppc_defs[i].name != NULL; i++) {
3894 if ((pvr & ppc_defs[i].pvr_mask) ==
3895 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3896 *def = &ppc_defs[i];
3897 ret = 0;
3898 break;
3899 }
3900 }
3901
3902 return ret;
3903}
3904
3905void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3906{
3907 int i;
3908
3909 for (i = 0; ; i++) {
76a66253 3910 (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3fc6c082
FB		 3911 ppc_defs[i].name,
3912 ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3913 if (strcmp(ppc_defs[i].name, "ppc") == 0)
3914 break;
3915 }
3916}
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