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target-ppc: Add Altivec register read/write using XML
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
3fc6c082
FB		 19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0 26#include "dis-asm.h"
ee4e83ed 27#include "host-utils.h"
4e47ea67 28#include "gdbstub.h"
237c0af0 29
3fc6c082
FB		 30//#define PPC_DUMP_CPU
31//#define PPC_DEBUG_SPR
80d11f44
JM		 32//#define PPC_DUMP_SPR_ACCESSES
33#if defined(CONFIG_USER_ONLY)
34#define TODO_USER_ONLY 1
35#endif
3fc6c082
FB		 36
37struct ppc_def_t {
b55266b5 38 const char *name;
3fc6c082 39 uint32_t pvr;
80d11f44 40 uint32_t svr;
0487d6a8 41 uint64_t insns_flags;
3fc6c082 42 uint64_t msr_mask;
7820dbf3
JM		 43 powerpc_mmu_t mmu_model;
44 powerpc_excp_t excp_model;
45 powerpc_input_t bus_model;
d26bfc9a 46 uint32_t flags;
237c0af0 47 int bfd_mach;
a750fc0b 48 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 49 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 50};
51
e9df014c
JM		 52/* For user-mode emulation, we don't emulate any IRQ controller */
53#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 54#define PPC_IRQ_INIT_FN(name) \
55static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
56{ \
e9df014c
JM		 57}
58#else
a750fc0b 59#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 60void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
61#endif
a750fc0b 62
4e290a0b 63PPC_IRQ_INIT_FN(40x);
e9df014c 64PPC_IRQ_INIT_FN(6xx);
d0dfae6e 65PPC_IRQ_INIT_FN(970);
e9df014c 66
3fc6c082
FB		 67/* Generic callbacks:
68 * do nothing but store/retrieve spr value
69 */
45d827d2 70static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 71{
45d827d2
AJ		 72 gen_load_spr(cpu_gpr[gprn], sprn);
73#ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv t0 = tcg_const_i32(sprn);
76 gen_helper_load_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79#endif
a496775f
JM		 80}
81
45d827d2 82static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 83{
45d827d2
AJ		 84 gen_store_spr(sprn, cpu_gpr[gprn]);
85#ifdef PPC_DUMP_SPR_ACCESSES
86 {
87 TCGv t0 = tcg_const_i32(sprn);
88 gen_helper_store_dump_spr(t0);
89 tcg_temp_free_i32(t0);
90 }
04f20795 91#endif
45d827d2 92}
a496775f
JM		 93
94#if !defined(CONFIG_USER_ONLY)
45d827d2 95static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 96{
45d827d2
AJ		 97 TCGv t0 = tcg_temp_new();
98 TCGv t1 = tcg_temp_new();
99 gen_load_spr(t0, sprn);
100 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
101 tcg_gen_and_tl(t0, t0, t1);
102 gen_store_spr(sprn, t0);
103 tcg_temp_free(t0);
104 tcg_temp_free(t1);
a496775f
JM		 105}
106#endif
107
76a66253 108/* SPR common to all PowerPC */
3fc6c082 109/* XER */
45d827d2 110static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 111{
45d827d2 112 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 113}
114
45d827d2 115static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 116{
45d827d2 117 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 118}
119
120/* LR */
45d827d2 121static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 122{
45d827d2 123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 124}
125
45d827d2 126static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 127{
45d827d2 128 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 129}
130
131/* CTR */
45d827d2 132static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 133{
45d827d2 134 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 135}
136
45d827d2 137static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 138{
45d827d2 139 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 140}
141
142/* User read access to SPR */
143/* USPRx */
144/* UMMCRx */
145/* UPMCx */
146/* USIA */
147/* UDECR */
45d827d2 148static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 149{
45d827d2 150 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 151}
152
76a66253 153/* SPR common to all non-embedded PowerPC */
3fc6c082 154/* DECR */
76a66253 155#if !defined(CONFIG_USER_ONLY)
45d827d2 156static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 157{
45d827d2 158 gen_helper_load_decr(cpu_gpr[gprn]);
3fc6c082
FB		 159}
160
45d827d2 161static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 162{
45d827d2 163 gen_helper_store_decr(cpu_gpr[gprn]);
3fc6c082 164}
76a66253 165#endif
3fc6c082 166
76a66253 167/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 168/* Time base */
45d827d2 169static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 170{
45d827d2 171 gen_helper_load_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 172}
173
45d827d2 174static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 175{
45d827d2 176 gen_helper_load_tbu(cpu_gpr[gprn]);
3fc6c082
FB		 177}
178
a062e36c 179__attribute__ (( unused ))
45d827d2 180static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 181{
45d827d2 182 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 183}
184
185__attribute__ (( unused ))
45d827d2 186static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 187{
45d827d2 188 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 189}
190
76a66253 191#if !defined(CONFIG_USER_ONLY)
45d827d2 192static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 193{
45d827d2 194 gen_helper_store_tbl(cpu_gpr[gprn]);
3fc6c082
FB		 195}
196
45d827d2 197static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 198{
45d827d2 199 gen_helper_store_tbu(cpu_gpr[gprn]);
3fc6c082 200}
a062e36c
JM		 201
202__attribute__ (( unused ))
45d827d2 203static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 204{
45d827d2 205 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 206}
207
208__attribute__ (( unused ))
45d827d2 209static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 210{
45d827d2 211 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 212}
76a66253 213#endif
3fc6c082 214
76a66253 215#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 216/* IBAT0U...IBAT0U */
217/* IBAT0L...IBAT7L */
45d827d2 218static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 219{
45d827d2 220 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 221}
222
45d827d2 223static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 224{
45d827d2 225 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 226}
227
45d827d2 228static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 229{
45d827d2
AJ		 230 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
231 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
232 tcg_temp_free_i32(t0);
3fc6c082
FB		 233}
234
45d827d2 235static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 236{
45d827d2
AJ		 237 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
238 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
239 tcg_temp_free_i32(t0);
3fc6c082
FB		 240}
241
45d827d2 242static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 243{
45d827d2
AJ		 244 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
245 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
246 tcg_temp_free_i32(t0);
3fc6c082
FB		 247}
248
45d827d2 249static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 250{
45d827d2
AJ		 251 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
252 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
253 tcg_temp_free_i32(t0);
3fc6c082
FB		 254}
255
256/* DBAT0U...DBAT7U */
257/* DBAT0L...DBAT7L */
45d827d2 258static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 259{
45d827d2 260 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 261}
262
45d827d2 263static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 264{
45d827d2 265 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 266}
267
45d827d2 268static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 269{
45d827d2
AJ		 270 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
271 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
272 tcg_temp_free_i32(t0);
3fc6c082
FB		 273}
274
45d827d2 275static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 276{
45d827d2
AJ		 277 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
278 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
279 tcg_temp_free_i32(t0);
3fc6c082
FB		 280}
281
45d827d2 282static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 283{
45d827d2
AJ		 284 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
285 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
286 tcg_temp_free_i32(t0);
3fc6c082
FB		 287}
288
45d827d2 289static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 290{
45d827d2
AJ		 291 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
292 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
293 tcg_temp_free_i32(t0);
3fc6c082
FB		 294}
295
296/* SDR1 */
45d827d2 297static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
3fc6c082 298{
45d827d2 299 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
3fc6c082
FB		 300}
301
45d827d2 302static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 303{
45d827d2 304 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 305}
306
76a66253
JM		 307/* 64 bits PowerPC specific SPRs */
308/* ASR */
578bb252 309#if defined(TARGET_PPC64)
45d827d2 310static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 311{
45d827d2 312 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 313}
314
45d827d2 315static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 316{
45d827d2 317 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 318}
319#endif
a750fc0b 320#endif
76a66253
JM		 321
322/* PowerPC 601 specific registers */
323/* RTC */
45d827d2 324static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 325{
45d827d2 326 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 327}
328
45d827d2 329static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 330{
45d827d2 331 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 332}
333
334#if !defined(CONFIG_USER_ONLY)
45d827d2 335static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 336{
45d827d2 337 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 338}
339
45d827d2 340static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 341{
45d827d2 342 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 343}
056401ea 344
45d827d2 345static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 346{
347 DisasContext *ctx = opaque;
348
45d827d2 349 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 350 /* Must stop the translation as endianness may have changed */
e06fcd75 351 gen_stop_exception(ctx);
056401ea 352}
76a66253
JM		 353#endif
354
355/* Unified bats */
356#if !defined(CONFIG_USER_ONLY)
45d827d2 357static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 358{
45d827d2 359 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 360}
361
45d827d2 362static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 363{
45d827d2
AJ		 364 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
365 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
76a66253
JM		 367}
368
45d827d2 369static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 370{
45d827d2
AJ		 371 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
372 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
373 tcg_temp_free_i32(t0);
76a66253
JM		 374}
375#endif
376
377/* PowerPC 40x specific registers */
378#if !defined(CONFIG_USER_ONLY)
45d827d2 379static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 380{
45d827d2 381 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 382}
383
45d827d2 384static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 385{
45d827d2 386 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 387}
388
45d827d2 389static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 390{
391 DisasContext *ctx = opaque;
392
45d827d2 393 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 394 /* We must stop translation as we may have rebooted */
e06fcd75 395 gen_stop_exception(ctx);
8ecc7913
JM		 396}
397
45d827d2 398static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 399{
45d827d2 400 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 401}
402
45d827d2 403static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 404{
45d827d2 405 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 406}
407
45d827d2 408static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 409{
45d827d2 410 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 411}
412#endif
413
414/* PowerPC 403 specific registers */
415/* PBL1 / PBU1 / PBL2 / PBU2 */
416#if !defined(CONFIG_USER_ONLY)
45d827d2 417static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 418{
45d827d2 419 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 420}
421
45d827d2 422static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 423{
45d827d2
AJ		 424 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
425 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
426 tcg_temp_free_i32(t0);
76a66253
JM		 427}
428
45d827d2 429static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 430{
45d827d2
AJ		 431 TCGv t0 = tcg_temp_new();
432 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
433 gen_store_spr(SPR_PIR, t0);
434 tcg_temp_free(t0);
3fc6c082 435}
76a66253 436#endif
3fc6c082 437
6f5d427d
JM		 438#if !defined(CONFIG_USER_ONLY)
439/* Callback used to write the exception vector base */
45d827d2 440static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 441{
45d827d2
AJ		 442 TCGv t0 = tcg_temp_new();
443 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
444 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
445 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
446 gen_store_spr(sprn, t0);
6f5d427d
JM		 447}
448
45d827d2 449static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 450{
451 DisasContext *ctx = opaque;
452
453 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 454 TCGv t0 = tcg_temp_new();
455 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
456 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
457 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
458 gen_store_spr(sprn, t0);
459 tcg_temp_free(t0);
6f5d427d 460 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 461 TCGv t0 = tcg_temp_new();
462 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
463 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
464 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
465 gen_store_spr(sprn, t0);
466 tcg_temp_free(t0);
6f5d427d
JM		 467 } else {
468 printf("Trying to write an unknown exception vector %d %03x\n",
469 sprn, sprn);
e06fcd75 470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 471 }
472}
473#endif
474
76a66253
JM		 475#if defined(CONFIG_USER_ONLY)
476#define spr_register(env, num, name, uea_read, uea_write, \
477 oea_read, oea_write, initial_value) \
478do { \
479 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
480} while (0)
481static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 482 const char *name,
45d827d2
AJ		 483 void (*uea_read)(void *opaque, int gprn, int sprn),
484 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 485 target_ulong initial_value)
486#else
3fc6c082 487static inline void spr_register (CPUPPCState *env, int num,
b55266b5 488 const char *name,
45d827d2
AJ		 489 void (*uea_read)(void *opaque, int gprn, int sprn),
490 void (*uea_write)(void *opaque, int sprn, int gprn),
491 void (*oea_read)(void *opaque, int gprn, int sprn),
492 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 493 target_ulong initial_value)
76a66253 494#endif
3fc6c082
FB		 495{
496 ppc_spr_t *spr;
497
498 spr = &env->spr_cb[num];
499 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 500#if !defined(CONFIG_USER_ONLY)
501 spr->oea_read != NULL || spr->oea_write != NULL ||
502#endif
503 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 504 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
505 exit(1);
506 }
507#if defined(PPC_DEBUG_SPR)
1b9eb036 508 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 509 initial_value);
3fc6c082
FB		 510#endif
511 spr->name = name;
512 spr->uea_read = uea_read;
513 spr->uea_write = uea_write;
76a66253 514#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 515 spr->oea_read = oea_read;
516 spr->oea_write = oea_write;
76a66253 517#endif
3fc6c082
FB		 518 env->spr[num] = initial_value;
519}
520
521/* Generic PowerPC SPRs */
522static void gen_spr_generic (CPUPPCState *env)
523{
524 /* Integer processing */
525 spr_register(env, SPR_XER, "XER",
526 &spr_read_xer, &spr_write_xer,
527 &spr_read_xer, &spr_write_xer,
528 0x00000000);
529 /* Branch contol */
530 spr_register(env, SPR_LR, "LR",
531 &spr_read_lr, &spr_write_lr,
532 &spr_read_lr, &spr_write_lr,
533 0x00000000);
534 spr_register(env, SPR_CTR, "CTR",
535 &spr_read_ctr, &spr_write_ctr,
536 &spr_read_ctr, &spr_write_ctr,
537 0x00000000);
538 /* Interrupt processing */
539 spr_register(env, SPR_SRR0, "SRR0",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_generic, &spr_write_generic,
542 0x00000000);
543 spr_register(env, SPR_SRR1, "SRR1",
544 SPR_NOACCESS, SPR_NOACCESS,
545 &spr_read_generic, &spr_write_generic,
546 0x00000000);
547 /* Processor control */
548 spr_register(env, SPR_SPRG0, "SPRG0",
549 SPR_NOACCESS, SPR_NOACCESS,
550 &spr_read_generic, &spr_write_generic,
551 0x00000000);
552 spr_register(env, SPR_SPRG1, "SPRG1",
553 SPR_NOACCESS, SPR_NOACCESS,
554 &spr_read_generic, &spr_write_generic,
555 0x00000000);
556 spr_register(env, SPR_SPRG2, "SPRG2",
557 SPR_NOACCESS, SPR_NOACCESS,
558 &spr_read_generic, &spr_write_generic,
559 0x00000000);
560 spr_register(env, SPR_SPRG3, "SPRG3",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_generic, &spr_write_generic,
563 0x00000000);
564}
565
566/* SPR common to all non-embedded PowerPC, including 601 */
567static void gen_spr_ne_601 (CPUPPCState *env)
568{
569 /* Exception processing */
570 spr_register(env, SPR_DSISR, "DSISR",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_generic, &spr_write_generic,
573 0x00000000);
574 spr_register(env, SPR_DAR, "DAR",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_generic, &spr_write_generic,
577 0x00000000);
578 /* Timer */
579 spr_register(env, SPR_DECR, "DECR",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_decr, &spr_write_decr,
582 0x00000000);
583 /* Memory management */
584 spr_register(env, SPR_SDR1, "SDR1",
585 SPR_NOACCESS, SPR_NOACCESS,
586 &spr_read_sdr1, &spr_write_sdr1,
587 0x00000000);
588}
589
590/* BATs 0-3 */
591static void gen_low_BATs (CPUPPCState *env)
592{
f2e63a42 593#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 594 spr_register(env, SPR_IBAT0U, "IBAT0U",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_ibat, &spr_write_ibatu,
597 0x00000000);
598 spr_register(env, SPR_IBAT0L, "IBAT0L",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_ibat, &spr_write_ibatl,
601 0x00000000);
602 spr_register(env, SPR_IBAT1U, "IBAT1U",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_ibat, &spr_write_ibatu,
605 0x00000000);
606 spr_register(env, SPR_IBAT1L, "IBAT1L",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_ibat, &spr_write_ibatl,
609 0x00000000);
610 spr_register(env, SPR_IBAT2U, "IBAT2U",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat, &spr_write_ibatu,
613 0x00000000);
614 spr_register(env, SPR_IBAT2L, "IBAT2L",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat, &spr_write_ibatl,
617 0x00000000);
618 spr_register(env, SPR_IBAT3U, "IBAT3U",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat, &spr_write_ibatu,
621 0x00000000);
622 spr_register(env, SPR_IBAT3L, "IBAT3L",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat, &spr_write_ibatl,
625 0x00000000);
626 spr_register(env, SPR_DBAT0U, "DBAT0U",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_dbat, &spr_write_dbatu,
629 0x00000000);
630 spr_register(env, SPR_DBAT0L, "DBAT0L",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_dbat, &spr_write_dbatl,
633 0x00000000);
634 spr_register(env, SPR_DBAT1U, "DBAT1U",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_dbat, &spr_write_dbatu,
637 0x00000000);
638 spr_register(env, SPR_DBAT1L, "DBAT1L",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_dbat, &spr_write_dbatl,
641 0x00000000);
642 spr_register(env, SPR_DBAT2U, "DBAT2U",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat, &spr_write_dbatu,
645 0x00000000);
646 spr_register(env, SPR_DBAT2L, "DBAT2L",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat, &spr_write_dbatl,
649 0x00000000);
650 spr_register(env, SPR_DBAT3U, "DBAT3U",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat, &spr_write_dbatu,
653 0x00000000);
654 spr_register(env, SPR_DBAT3L, "DBAT3L",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat, &spr_write_dbatl,
657 0x00000000);
a750fc0b 658 env->nb_BATs += 4;
f2e63a42 659#endif
3fc6c082
FB		 660}
661
662/* BATs 4-7 */
663static void gen_high_BATs (CPUPPCState *env)
664{
f2e63a42 665#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 666 spr_register(env, SPR_IBAT4U, "IBAT4U",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_ibat_h, &spr_write_ibatu_h,
669 0x00000000);
670 spr_register(env, SPR_IBAT4L, "IBAT4L",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_ibat_h, &spr_write_ibatl_h,
673 0x00000000);
674 spr_register(env, SPR_IBAT5U, "IBAT5U",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_ibat_h, &spr_write_ibatu_h,
677 0x00000000);
678 spr_register(env, SPR_IBAT5L, "IBAT5L",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_ibat_h, &spr_write_ibatl_h,
681 0x00000000);
682 spr_register(env, SPR_IBAT6U, "IBAT6U",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_ibat_h, &spr_write_ibatu_h,
685 0x00000000);
686 spr_register(env, SPR_IBAT6L, "IBAT6L",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_ibat_h, &spr_write_ibatl_h,
689 0x00000000);
690 spr_register(env, SPR_IBAT7U, "IBAT7U",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_ibat_h, &spr_write_ibatu_h,
693 0x00000000);
694 spr_register(env, SPR_IBAT7L, "IBAT7L",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_ibat_h, &spr_write_ibatl_h,
697 0x00000000);
698 spr_register(env, SPR_DBAT4U, "DBAT4U",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_dbat_h, &spr_write_dbatu_h,
701 0x00000000);
702 spr_register(env, SPR_DBAT4L, "DBAT4L",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_dbat_h, &spr_write_dbatl_h,
705 0x00000000);
706 spr_register(env, SPR_DBAT5U, "DBAT5U",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_dbat_h, &spr_write_dbatu_h,
709 0x00000000);
710 spr_register(env, SPR_DBAT5L, "DBAT5L",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_dbat_h, &spr_write_dbatl_h,
713 0x00000000);
714 spr_register(env, SPR_DBAT6U, "DBAT6U",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_dbat_h, &spr_write_dbatu_h,
717 0x00000000);
718 spr_register(env, SPR_DBAT6L, "DBAT6L",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_dbat_h, &spr_write_dbatl_h,
721 0x00000000);
722 spr_register(env, SPR_DBAT7U, "DBAT7U",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_dbat_h, &spr_write_dbatu_h,
725 0x00000000);
726 spr_register(env, SPR_DBAT7L, "DBAT7L",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_dbat_h, &spr_write_dbatl_h,
729 0x00000000);
a750fc0b 730 env->nb_BATs += 4;
f2e63a42 731#endif
3fc6c082
FB		 732}
733
734/* Generic PowerPC time base */
735static void gen_tbl (CPUPPCState *env)
736{
737 spr_register(env, SPR_VTBL, "TBL",
738 &spr_read_tbl, SPR_NOACCESS,
739 &spr_read_tbl, SPR_NOACCESS,
740 0x00000000);
741 spr_register(env, SPR_TBL, "TBL",
742 SPR_NOACCESS, SPR_NOACCESS,
743 SPR_NOACCESS, &spr_write_tbl,
744 0x00000000);
745 spr_register(env, SPR_VTBU, "TBU",
746 &spr_read_tbu, SPR_NOACCESS,
747 &spr_read_tbu, SPR_NOACCESS,
748 0x00000000);
749 spr_register(env, SPR_TBU, "TBU",
750 SPR_NOACCESS, SPR_NOACCESS,
751 SPR_NOACCESS, &spr_write_tbu,
752 0x00000000);
753}
754
76a66253
JM		 755/* Softare table search registers */
756static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
757{
f2e63a42 758#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 759 env->nb_tlb = nb_tlbs;
760 env->nb_ways = nb_ways;
761 env->id_tlbs = 1;
762 spr_register(env, SPR_DMISS, "DMISS",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_generic, SPR_NOACCESS,
765 0x00000000);
766 spr_register(env, SPR_DCMP, "DCMP",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_generic, SPR_NOACCESS,
769 0x00000000);
770 spr_register(env, SPR_HASH1, "HASH1",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, SPR_NOACCESS,
773 0x00000000);
774 spr_register(env, SPR_HASH2, "HASH2",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, SPR_NOACCESS,
777 0x00000000);
778 spr_register(env, SPR_IMISS, "IMISS",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, SPR_NOACCESS,
781 0x00000000);
782 spr_register(env, SPR_ICMP, "ICMP",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, SPR_NOACCESS,
785 0x00000000);
786 spr_register(env, SPR_RPA, "RPA",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_generic,
789 0x00000000);
f2e63a42 790#endif
76a66253
JM		 791}
792
793/* SPR common to MPC755 and G2 */
794static void gen_spr_G2_755 (CPUPPCState *env)
795{
796 /* SGPRs */
797 spr_register(env, SPR_SPRG4, "SPRG4",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 spr_register(env, SPR_SPRG5, "SPRG5",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 spr_register(env, SPR_SPRG6, "SPRG6",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_generic, &spr_write_generic,
808 0x00000000);
809 spr_register(env, SPR_SPRG7, "SPRG7",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_generic, &spr_write_generic,
812 0x00000000);
76a66253
JM		 813}
814
3fc6c082
FB		 815/* SPR common to all 7xx PowerPC implementations */
816static void gen_spr_7xx (CPUPPCState *env)
817{
818 /* Breakpoints */
819 /* XXX : not implemented */
820 spr_register(env, SPR_DABR, "DABR",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_generic, &spr_write_generic,
823 0x00000000);
824 /* XXX : not implemented */
825 spr_register(env, SPR_IABR, "IABR",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_generic, &spr_write_generic,
828 0x00000000);
829 /* Cache management */
830 /* XXX : not implemented */
831 spr_register(env, SPR_ICTC, "ICTC",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_generic, &spr_write_generic,
834 0x00000000);
835 /* Performance monitors */
836 /* XXX : not implemented */
837 spr_register(env, SPR_MMCR0, "MMCR0",
838 SPR_NOACCESS, SPR_NOACCESS,
839 &spr_read_generic, &spr_write_generic,
840 0x00000000);
841 /* XXX : not implemented */
842 spr_register(env, SPR_MMCR1, "MMCR1",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_generic, &spr_write_generic,
845 0x00000000);
846 /* XXX : not implemented */
847 spr_register(env, SPR_PMC1, "PMC1",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, &spr_write_generic,
850 0x00000000);
851 /* XXX : not implemented */
852 spr_register(env, SPR_PMC2, "PMC2",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, &spr_write_generic,
855 0x00000000);
856 /* XXX : not implemented */
857 spr_register(env, SPR_PMC3, "PMC3",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic, &spr_write_generic,
860 0x00000000);
861 /* XXX : not implemented */
862 spr_register(env, SPR_PMC4, "PMC4",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
866 /* XXX : not implemented */
a750fc0b 867 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
578bb252 871 /* XXX : not implemented */
3fc6c082
FB		 872 spr_register(env, SPR_UMMCR0, "UMMCR0",
873 &spr_read_ureg, SPR_NOACCESS,
874 &spr_read_ureg, SPR_NOACCESS,
875 0x00000000);
578bb252 876 /* XXX : not implemented */
3fc6c082
FB		 877 spr_register(env, SPR_UMMCR1, "UMMCR1",
878 &spr_read_ureg, SPR_NOACCESS,
879 &spr_read_ureg, SPR_NOACCESS,
880 0x00000000);
578bb252 881 /* XXX : not implemented */
3fc6c082
FB		 882 spr_register(env, SPR_UPMC1, "UPMC1",
883 &spr_read_ureg, SPR_NOACCESS,
884 &spr_read_ureg, SPR_NOACCESS,
885 0x00000000);
578bb252 886 /* XXX : not implemented */
3fc6c082
FB		 887 spr_register(env, SPR_UPMC2, "UPMC2",
888 &spr_read_ureg, SPR_NOACCESS,
889 &spr_read_ureg, SPR_NOACCESS,
890 0x00000000);
578bb252 891 /* XXX : not implemented */
3fc6c082
FB		 892 spr_register(env, SPR_UPMC3, "UPMC3",
893 &spr_read_ureg, SPR_NOACCESS,
894 &spr_read_ureg, SPR_NOACCESS,
895 0x00000000);
578bb252 896 /* XXX : not implemented */
3fc6c082
FB		 897 spr_register(env, SPR_UPMC4, "UPMC4",
898 &spr_read_ureg, SPR_NOACCESS,
899 &spr_read_ureg, SPR_NOACCESS,
900 0x00000000);
578bb252 901 /* XXX : not implemented */
a750fc0b 902 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 903 &spr_read_ureg, SPR_NOACCESS,
904 &spr_read_ureg, SPR_NOACCESS,
905 0x00000000);
a750fc0b 906 /* External access control */
3fc6c082 907 /* XXX : not implemented */
a750fc0b 908 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
a750fc0b
JM		 912}
913
914static void gen_spr_thrm (CPUPPCState *env)
915{
916 /* Thermal management */
3fc6c082 917 /* XXX : not implemented */
a750fc0b 918 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* XXX : not implemented */
a750fc0b 923 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
3fc6c082 927 /* XXX : not implemented */
a750fc0b 928 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932}
933
934/* SPR specific to PowerPC 604 implementation */
935static void gen_spr_604 (CPUPPCState *env)
936{
937 /* Processor identification */
938 spr_register(env, SPR_PIR, "PIR",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_pir,
941 0x00000000);
942 /* Breakpoints */
943 /* XXX : not implemented */
944 spr_register(env, SPR_IABR, "IABR",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_DABR, "DABR",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* Performance counters */
954 /* XXX : not implemented */
955 spr_register(env, SPR_MMCR0, "MMCR0",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
3fc6c082
FB		 960 spr_register(env, SPR_PMC1, "PMC1",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC2, "PMC2",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
a750fc0b 970 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, SPR_NOACCESS,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_SDA, "SDA",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 /* External access control */
980 /* XXX : not implemented */
981 spr_register(env, SPR_EAR, "EAR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985}
986
76a66253
JM		 987/* SPR specific to PowerPC 603 implementation */
988static void gen_spr_603 (CPUPPCState *env)
3fc6c082 989{
76a66253
JM		 990 /* External access control */
991 /* XXX : not implemented */
992 spr_register(env, SPR_EAR, "EAR",
3fc6c082 993 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
3fc6c082
FB		 996}
997
76a66253
JM		 998/* SPR specific to PowerPC G2 implementation */
999static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1000{
76a66253
JM		 1001 /* Memory base address */
1002 /* MBAR */
578bb252 1003 /* XXX : not implemented */
76a66253
JM		 1004 spr_register(env, SPR_MBAR, "MBAR",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
76a66253 1008 /* Exception processing */
363be49c 1009 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
363be49c 1013 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017 /* Breakpoints */
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_DABR, "DABR",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_DABR2, "DABR2",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1027 0x00000000);
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_IABR, "IABR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_IABR2, "IABR2",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* XXX : not implemented */
1039 spr_register(env, SPR_IBCR, "IBCR",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, &spr_write_generic,
1042 0x00000000);
1043 /* XXX : not implemented */
1044 spr_register(env, SPR_DBCR, "DBCR",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048}
1049
1050/* SPR specific to PowerPC 602 implementation */
1051static void gen_spr_602 (CPUPPCState *env)
1052{
1053 /* ESA registers */
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_SER, "SER",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_SEBR, "SEBR",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 /* XXX : not implemented */
a750fc0b 1065 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, &spr_write_generic,
1068 0x00000000);
1069 /* Floating point status */
1070 /* XXX : not implemented */
1071 spr_register(env, SPR_SP, "SP",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 0x00000000);
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_LT, "LT",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
1080 /* Watchdog timer */
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_TCR, "TCR",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 /* Interrupt base */
1087 spr_register(env, SPR_IBR, "IBR",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_generic, &spr_write_generic,
1090 0x00000000);
a750fc0b
JM		 1091 /* XXX : not implemented */
1092 spr_register(env, SPR_IABR, "IABR",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
76a66253
JM		 1096}
1097
1098/* SPR specific to PowerPC 601 implementation */
1099static void gen_spr_601 (CPUPPCState *env)
1100{
1101 /* Multiplication/division register */
1102 /* MQ */
1103 spr_register(env, SPR_MQ, "MQ",
1104 &spr_read_generic, &spr_write_generic,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 /* RTC registers */
1108 spr_register(env, SPR_601_RTCU, "RTCU",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 SPR_NOACCESS, &spr_write_601_rtcu,
1111 0x00000000);
1112 spr_register(env, SPR_601_VRTCU, "RTCU",
1113 &spr_read_601_rtcu, SPR_NOACCESS,
1114 &spr_read_601_rtcu, SPR_NOACCESS,
1115 0x00000000);
1116 spr_register(env, SPR_601_RTCL, "RTCL",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 SPR_NOACCESS, &spr_write_601_rtcl,
1119 0x00000000);
1120 spr_register(env, SPR_601_VRTCL, "RTCL",
1121 &spr_read_601_rtcl, SPR_NOACCESS,
1122 &spr_read_601_rtcl, SPR_NOACCESS,
1123 0x00000000);
1124 /* Timer */
1125#if 0 /* ? */
1126 spr_register(env, SPR_601_UDECR, "UDECR",
1127 &spr_read_decr, SPR_NOACCESS,
1128 &spr_read_decr, SPR_NOACCESS,
1129 0x00000000);
1130#endif
1131 /* External access control */
1132 /* XXX : not implemented */
1133 spr_register(env, SPR_EAR, "EAR",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137 /* Memory management */
f2e63a42 1138#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1139 spr_register(env, SPR_IBAT0U, "IBAT0U",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_601_ubat, &spr_write_601_ubatu,
1142 0x00000000);
1143 spr_register(env, SPR_IBAT0L, "IBAT0L",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_601_ubat, &spr_write_601_ubatl,
1146 0x00000000);
1147 spr_register(env, SPR_IBAT1U, "IBAT1U",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_601_ubat, &spr_write_601_ubatu,
1150 0x00000000);
1151 spr_register(env, SPR_IBAT1L, "IBAT1L",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_601_ubat, &spr_write_601_ubatl,
1154 0x00000000);
1155 spr_register(env, SPR_IBAT2U, "IBAT2U",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_601_ubat, &spr_write_601_ubatu,
1158 0x00000000);
1159 spr_register(env, SPR_IBAT2L, "IBAT2L",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_601_ubat, &spr_write_601_ubatl,
1162 0x00000000);
1163 spr_register(env, SPR_IBAT3U, "IBAT3U",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_601_ubat, &spr_write_601_ubatu,
1166 0x00000000);
1167 spr_register(env, SPR_IBAT3L, "IBAT3L",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_601_ubat, &spr_write_601_ubatl,
1170 0x00000000);
a750fc0b 1171 env->nb_BATs = 4;
f2e63a42 1172#endif
a750fc0b
JM		 1173}
1174
1175static void gen_spr_74xx (CPUPPCState *env)
1176{
1177 /* Processor identification */
1178 spr_register(env, SPR_PIR, "PIR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_pir,
1181 0x00000000);
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_MMCR2, "MMCR2",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
578bb252 1187 /* XXX : not implemented */
a750fc0b
JM		 1188 spr_register(env, SPR_UMMCR2, "UMMCR2",
1189 &spr_read_ureg, SPR_NOACCESS,
1190 &spr_read_ureg, SPR_NOACCESS,
1191 0x00000000);
1192 /* XXX: not implemented */
1193 spr_register(env, SPR_BAMR, "BAMR",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
578bb252 1197 /* XXX : not implemented */
a750fc0b
JM		 1198 spr_register(env, SPR_MSSCR0, "MSSCR0",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_generic,
1201 0x00000000);
1202 /* Hardware implementation registers */
1203 /* XXX : not implemented */
1204 spr_register(env, SPR_HID0, "HID0",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 /* XXX : not implemented */
1209 spr_register(env, SPR_HID1, "HID1",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
1213 /* Altivec */
1214 spr_register(env, SPR_VRSAVE, "VRSAVE",
1215 &spr_read_generic, &spr_write_generic,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
bd928eba
JM		 1218 /* XXX : not implemented */
1219 spr_register(env, SPR_L2CR, "L2CR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
a750fc0b
JM		 1223}
1224
a750fc0b
JM		 1225static void gen_l3_ctrl (CPUPPCState *env)
1226{
1227 /* L3CR */
1228 /* XXX : not implemented */
1229 spr_register(env, SPR_L3CR, "L3CR",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* L3ITCR0 */
578bb252 1234 /* XXX : not implemented */
a750fc0b
JM		 1235 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
a750fc0b 1239 /* L3PM */
578bb252 1240 /* XXX : not implemented */
a750fc0b
JM		 1241 spr_register(env, SPR_L3PM, "L3PM",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245}
a750fc0b 1246
578bb252 1247static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1248{
f2e63a42 1249#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1250 env->nb_tlb = nb_tlbs;
1251 env->nb_ways = nb_ways;
1252 env->id_tlbs = 1;
1253 /* XXX : not implemented */
a750fc0b
JM		 1254 spr_register(env, SPR_PTEHI, "PTEHI",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
578bb252 1258 /* XXX : not implemented */
a750fc0b
JM		 1259 spr_register(env, SPR_PTELO, "PTELO",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
578bb252 1263 /* XXX : not implemented */
a750fc0b
JM		 1264 spr_register(env, SPR_TLBMISS, "TLBMISS",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
f2e63a42 1268#endif
76a66253
JM		 1269}
1270
80d11f44 1271static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1272{
80d11f44
JM		 1273 spr_register(env, SPR_USPRG4, "USPRG4",
1274 &spr_read_ureg, SPR_NOACCESS,
1275 &spr_read_ureg, SPR_NOACCESS,
1276 0x00000000);
1277 spr_register(env, SPR_USPRG5, "USPRG5",
1278 &spr_read_ureg, SPR_NOACCESS,
1279 &spr_read_ureg, SPR_NOACCESS,
1280 0x00000000);
1281 spr_register(env, SPR_USPRG6, "USPRG6",
1282 &spr_read_ureg, SPR_NOACCESS,
1283 &spr_read_ureg, SPR_NOACCESS,
1284 0x00000000);
1285 spr_register(env, SPR_USPRG7, "USPRG7",
1286 &spr_read_ureg, SPR_NOACCESS,
1287 &spr_read_ureg, SPR_NOACCESS,
76a66253 1288 0x00000000);
80d11f44
JM		 1289}
1290
1291/* PowerPC BookE SPR */
1292static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1293{
b55266b5 1294 const char *ivor_names[64] = {
80d11f44
JM		 1295 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1296 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1297 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1298 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1299 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1300 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1301 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1302 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1303 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1304 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1305 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1306 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1307 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1308 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1309 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1310 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1311 };
1312#define SPR_BOOKE_IVORxx (-1)
1313 int ivor_sprn[64] = {
1314 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1315 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1316 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1317 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1318 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1319 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1320 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1321 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1322 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1323 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1324 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1325 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1326 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1327 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1328 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1329 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1330 };
1331 int i;
1332
76a66253 1333 /* Interrupt processing */
363be49c 1334 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
363be49c
JM		 1338 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
76a66253
JM		 1342 /* Debug */
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
76a66253
JM		 1354 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* XXX : not implemented */
1359 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 /* XXX : not implemented */
76a66253
JM		 1364 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 /* XXX : not implemented */
1369 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373 /* XXX : not implemented */
1374 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 /* XXX : not implemented */
1379 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1380 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1381 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1382 0x00000000);
1383 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 spr_register(env, SPR_BOOKE_ESR, "ESR",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
363be49c
JM		 1391 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1392 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1393 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1394 0x00000000);
1395 /* Exception vectors */
80d11f44
JM		 1396 for (i = 0; i < 64; i++) {
1397 if (ivor_mask & (1ULL << i)) {
1398 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1399 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1400 exit(1);
1401 }
1402 spr_register(env, ivor_sprn[i], ivor_names[i],
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_excp_vector,
1405 0x00000000);
1406 }
1407 }
76a66253
JM		 1408 spr_register(env, SPR_BOOKE_PID, "PID",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 spr_register(env, SPR_BOOKE_TCR, "TCR",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_booke_tcr,
1415 0x00000000);
1416 spr_register(env, SPR_BOOKE_TSR, "TSR",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_booke_tsr,
1419 0x00000000);
1420 /* Timer */
1421 spr_register(env, SPR_DECR, "DECR",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_decr, &spr_write_decr,
1424 0x00000000);
1425 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 SPR_NOACCESS, &spr_write_generic,
1428 0x00000000);
1429 /* SPRGs */
1430 spr_register(env, SPR_USPRG0, "USPRG0",
1431 &spr_read_generic, &spr_write_generic,
1432 &spr_read_generic, &spr_write_generic,
1433 0x00000000);
1434 spr_register(env, SPR_SPRG4, "SPRG4",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
76a66253
JM		 1438 spr_register(env, SPR_SPRG5, "SPRG5",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_generic,
1441 0x00000000);
76a66253
JM		 1442 spr_register(env, SPR_SPRG6, "SPRG6",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_generic,
1445 0x00000000);
76a66253
JM		 1446 spr_register(env, SPR_SPRG7, "SPRG7",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
76a66253
JM		 1450}
1451
363be49c 1452/* FSL storage control registers */
80d11f44 1453static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
363be49c 1454{
f2e63a42 1455#if !defined(CONFIG_USER_ONLY)
b55266b5 1456 const char *mas_names[8] = {
80d11f44
JM		 1457 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1458 };
1459 int mas_sprn[8] = {
1460 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1461 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1462 };
1463 int i;
1464
363be49c 1465 /* TLB assist registers */
578bb252 1466 /* XXX : not implemented */
80d11f44
JM		 1467 for (i = 0; i < 8; i++) {
1468 if (mas_mask & (1 << i)) {
1469 spr_register(env, mas_sprn[i], mas_names[i],
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 }
1474 }
363be49c 1475 if (env->nb_pids > 1) {
578bb252 1476 /* XXX : not implemented */
363be49c
JM		 1477 spr_register(env, SPR_BOOKE_PID1, "PID1",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1480 0x00000000);
1481 }
1482 if (env->nb_pids > 2) {
578bb252 1483 /* XXX : not implemented */
363be49c
JM		 1484 spr_register(env, SPR_BOOKE_PID2, "PID2",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 }
578bb252 1489 /* XXX : not implemented */
65f9ee8d 1490 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, SPR_NOACCESS,
1493 0x00000000); /* TOFIX */
578bb252 1494 /* XXX : not implemented */
65f9ee8d 1495 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000); /* TOFIX */
1499 switch (env->nb_ways) {
1500 case 4:
578bb252 1501 /* XXX : not implemented */
363be49c
JM		 1502 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, SPR_NOACCESS,
1505 0x00000000); /* TOFIX */
1506 /* Fallthru */
1507 case 3:
578bb252 1508 /* XXX : not implemented */
363be49c
JM		 1509 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, SPR_NOACCESS,
1512 0x00000000); /* TOFIX */
1513 /* Fallthru */
1514 case 2:
578bb252 1515 /* XXX : not implemented */
363be49c
JM		 1516 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, SPR_NOACCESS,
1519 0x00000000); /* TOFIX */
1520 /* Fallthru */
1521 case 1:
578bb252 1522 /* XXX : not implemented */
363be49c
JM		 1523 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, SPR_NOACCESS,
1526 0x00000000); /* TOFIX */
1527 /* Fallthru */
1528 case 0:
1529 default:
1530 break;
1531 }
f2e63a42 1532#endif
363be49c
JM		 1533}
1534
76a66253
JM		 1535/* SPR specific to PowerPC 440 implementation */
1536static void gen_spr_440 (CPUPPCState *env)
1537{
1538 /* Cache control */
1539 /* XXX : not implemented */
1540 spr_register(env, SPR_440_DNV0, "DNV0",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 &spr_read_generic, &spr_write_generic,
1543 0x00000000);
1544 /* XXX : not implemented */
1545 spr_register(env, SPR_440_DNV1, "DNV1",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 /* XXX : not implemented */
1550 spr_register(env, SPR_440_DNV2, "DNV2",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* XXX : not implemented */
1555 spr_register(env, SPR_440_DNV3, "DNV3",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559 /* XXX : not implemented */
2662a059 1560 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 /* XXX : not implemented */
2662a059 1565 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 /* XXX : not implemented */
2662a059 1570 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 /* XXX : not implemented */
2662a059 1575 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 /* XXX : not implemented */
1580 spr_register(env, SPR_440_DVLIM, "DVLIM",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584 /* XXX : not implemented */
1585 spr_register(env, SPR_440_INV0, "INV0",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589 /* XXX : not implemented */
1590 spr_register(env, SPR_440_INV1, "INV1",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594 /* XXX : not implemented */
1595 spr_register(env, SPR_440_INV2, "INV2",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 /* XXX : not implemented */
1600 spr_register(env, SPR_440_INV3, "INV3",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604 /* XXX : not implemented */
2662a059 1605 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609 /* XXX : not implemented */
2662a059 1610 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 /* XXX : not implemented */
2662a059 1615 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 /* XXX : not implemented */
2662a059 1620 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, &spr_write_generic,
1623 0x00000000);
1624 /* XXX : not implemented */
1625 spr_register(env, SPR_440_IVLIM, "IVLIM",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_generic,
1628 0x00000000);
1629 /* Cache debug */
1630 /* XXX : not implemented */
2662a059 1631 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, SPR_NOACCESS,
1634 0x00000000);
1635 /* XXX : not implemented */
2662a059 1636 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1637 SPR_NOACCESS, SPR_NOACCESS,
1638 &spr_read_generic, SPR_NOACCESS,
1639 0x00000000);
1640 /* XXX : not implemented */
2662a059 1641 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, SPR_NOACCESS,
1644 0x00000000);
1645 /* XXX : not implemented */
2662a059 1646 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
1649 0x00000000);
1650 /* XXX : not implemented */
2662a059 1651 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, SPR_NOACCESS,
1654 0x00000000);
1655 /* XXX : not implemented */
1656 spr_register(env, SPR_440_DBDR, "DBDR",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_generic,
1659 0x00000000);
1660 /* Processor control */
1661 spr_register(env, SPR_4xx_CCR0, "CCR0",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, SPR_NOACCESS,
1668 0x00000000);
1669 /* Storage control */
1670 spr_register(env, SPR_440_MMUCR, "MMUCR",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
1674}
1675
1676/* SPR shared between PowerPC 40x implementations */
1677static void gen_spr_40x (CPUPPCState *env)
1678{
1679 /* Cache */
035feb88 1680 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1681 spr_register(env, SPR_40x_DCCR, "DCCR",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
035feb88 1685 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1686 spr_register(env, SPR_40x_ICCR, "ICCR",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
578bb252 1690 /* not emulated, as Qemu do not emulate caches */
2662a059 1691 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, SPR_NOACCESS,
1694 0x00000000);
76a66253
JM		 1695 /* Exception */
1696 spr_register(env, SPR_40x_DEAR, "DEAR",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 spr_register(env, SPR_40x_ESR, "ESR",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, &spr_write_generic,
1703 0x00000000);
1704 spr_register(env, SPR_40x_EVPR, "EVPR",
1705 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1706 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1707 0x00000000);
1708 spr_register(env, SPR_40x_SRR2, "SRR2",
1709 &spr_read_generic, &spr_write_generic,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 spr_register(env, SPR_40x_SRR3, "SRR3",
1713 &spr_read_generic, &spr_write_generic,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* Timers */
1717 spr_register(env, SPR_40x_PIT, "PIT",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_40x_pit, &spr_write_40x_pit,
1720 0x00000000);
1721 spr_register(env, SPR_40x_TCR, "TCR",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_booke_tcr,
1724 0x00000000);
1725 spr_register(env, SPR_40x_TSR, "TSR",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_booke_tsr,
1728 0x00000000);
2662a059
JM		 1729}
1730
1731/* SPR specific to PowerPC 405 implementation */
1732static void gen_spr_405 (CPUPPCState *env)
1733{
1734 /* MMU */
1735 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
2662a059 1739 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1742 0x00700000);
1743 /* Debug interface */
76a66253
JM		 1744 /* XXX : not implemented */
1745 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1746 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1747 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1748 0x00000000);
1749 /* XXX : not implemented */
2662a059
JM		 1750 spr_register(env, SPR_405_DBCR1, "DBCR1",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754 /* XXX : not implemented */
76a66253
JM		 1755 spr_register(env, SPR_40x_DBSR, "DBSR",
1756 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1757 &spr_read_generic, &spr_write_clear,
1758 /* Last reset was system reset */
76a66253
JM		 1759 0x00000300);
1760 /* XXX : not implemented */
2662a059 1761 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_generic,
1764 0x00000000);
2662a059 1765 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
2662a059
JM		 1769 /* XXX : not implemented */
1770 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
2662a059 1773 0x00000000);
76a66253 1774 /* XXX : not implemented */
2662a059 1775 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* XXX : not implemented */
2662a059 1780 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
2662a059 1784 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_405_IAC3, "IAC3",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_405_IAC4, "IAC4",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 /* Storage control */
035feb88 1799 /* XXX: TODO: not implemented */
76a66253
JM		 1800 spr_register(env, SPR_405_SLER, "SLER",
1801 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1802 &spr_read_generic, &spr_write_40x_sler,
76a66253 1803 0x00000000);
2662a059
JM		 1804 spr_register(env, SPR_40x_ZPR, "ZPR",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
76a66253
JM		 1808 /* XXX : not implemented */
1809 spr_register(env, SPR_405_SU0R, "SU0R",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* SPRG */
1814 spr_register(env, SPR_USPRG0, "USPRG0",
1815 &spr_read_ureg, SPR_NOACCESS,
1816 &spr_read_ureg, SPR_NOACCESS,
1817 0x00000000);
1818 spr_register(env, SPR_SPRG4, "SPRG4",
1819 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1820 &spr_read_generic, &spr_write_generic,
76a66253 1821 0x00000000);
76a66253
JM		 1822 spr_register(env, SPR_SPRG5, "SPRG5",
1823 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1824 spr_read_generic, &spr_write_generic,
76a66253 1825 0x00000000);
76a66253
JM		 1826 spr_register(env, SPR_SPRG6, "SPRG6",
1827 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1828 spr_read_generic, &spr_write_generic,
76a66253 1829 0x00000000);
76a66253
JM		 1830 spr_register(env, SPR_SPRG7, "SPRG7",
1831 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1832 spr_read_generic, &spr_write_generic,
76a66253 1833 0x00000000);
80d11f44 1834 gen_spr_usprgh(env);
76a66253
JM		 1835}
1836
1837/* SPR shared between PowerPC 401 & 403 implementations */
1838static void gen_spr_401_403 (CPUPPCState *env)
1839{
1840 /* Time base */
1841 spr_register(env, SPR_403_VTBL, "TBL",
1842 &spr_read_tbl, SPR_NOACCESS,
1843 &spr_read_tbl, SPR_NOACCESS,
1844 0x00000000);
1845 spr_register(env, SPR_403_TBL, "TBL",
1846 SPR_NOACCESS, SPR_NOACCESS,
1847 SPR_NOACCESS, &spr_write_tbl,
1848 0x00000000);
1849 spr_register(env, SPR_403_VTBU, "TBU",
1850 &spr_read_tbu, SPR_NOACCESS,
1851 &spr_read_tbu, SPR_NOACCESS,
1852 0x00000000);
1853 spr_register(env, SPR_403_TBU, "TBU",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 SPR_NOACCESS, &spr_write_tbu,
1856 0x00000000);
1857 /* Debug */
578bb252 1858 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1859 spr_register(env, SPR_403_CDBCR, "CDBCR",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 &spr_read_generic, &spr_write_generic,
1862 0x00000000);
1863}
1864
2662a059
JM		 1865/* SPR specific to PowerPC 401 implementation */
1866static void gen_spr_401 (CPUPPCState *env)
1867{
1868 /* Debug interface */
1869 /* XXX : not implemented */
1870 spr_register(env, SPR_40x_DBCR0, "DBCR",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, &spr_write_40x_dbcr0,
1873 0x00000000);
1874 /* XXX : not implemented */
1875 spr_register(env, SPR_40x_DBSR, "DBSR",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, &spr_write_clear,
1878 /* Last reset was system reset */
1879 0x00000300);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_40x_DAC1, "DAC",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_40x_IAC1, "IAC",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 /* Storage control */
035feb88 1891 /* XXX: TODO: not implemented */
2662a059
JM		 1892 spr_register(env, SPR_405_SLER, "SLER",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_40x_sler,
1895 0x00000000);
035feb88
JM		 1896 /* not emulated, as Qemu never does speculative access */
1897 spr_register(env, SPR_40x_SGR, "SGR",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, &spr_write_generic,
1900 0xFFFFFFFF);
1901 /* not emulated, as Qemu do not emulate caches */
1902 spr_register(env, SPR_40x_DCWR, "DCWR",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
2662a059
JM		 1906}
1907
a750fc0b
JM		 1908static void gen_spr_401x2 (CPUPPCState *env)
1909{
1910 gen_spr_401(env);
1911 spr_register(env, SPR_40x_PID, "PID",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915 spr_register(env, SPR_40x_ZPR, "ZPR",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, &spr_write_generic,
1918 0x00000000);
1919}
1920
76a66253
JM		 1921/* SPR specific to PowerPC 403 implementation */
1922static void gen_spr_403 (CPUPPCState *env)
1923{
2662a059
JM		 1924 /* Debug interface */
1925 /* XXX : not implemented */
1926 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_40x_dbcr0,
1929 0x00000000);
1930 /* XXX : not implemented */
1931 spr_register(env, SPR_40x_DBSR, "DBSR",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_clear,
1934 /* Last reset was system reset */
1935 0x00000300);
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_40x_DAC1, "DAC1",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
578bb252 1941 /* XXX : not implemented */
2662a059
JM		 1942 spr_register(env, SPR_40x_DAC2, "DAC2",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_40x_IAC1, "IAC1",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
578bb252 1951 /* XXX : not implemented */
2662a059
JM		 1952 spr_register(env, SPR_40x_IAC2, "IAC2",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
a750fc0b
JM		 1956}
1957
1958static void gen_spr_403_real (CPUPPCState *env)
1959{
76a66253
JM		 1960 spr_register(env, SPR_403_PBL1, "PBL1",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_403_pbr, &spr_write_403_pbr,
1963 0x00000000);
1964 spr_register(env, SPR_403_PBU1, "PBU1",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_403_pbr, &spr_write_403_pbr,
1967 0x00000000);
1968 spr_register(env, SPR_403_PBL2, "PBL2",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_403_pbr, &spr_write_403_pbr,
1971 0x00000000);
1972 spr_register(env, SPR_403_PBU2, "PBU2",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_403_pbr, &spr_write_403_pbr,
1975 0x00000000);
a750fc0b
JM		 1976}
1977
1978static void gen_spr_403_mmu (CPUPPCState *env)
1979{
1980 /* MMU */
1981 spr_register(env, SPR_40x_PID, "PID",
1982 SPR_NOACCESS, SPR_NOACCESS,
1983 &spr_read_generic, &spr_write_generic,
1984 0x00000000);
2662a059 1985 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989}
1990
1991/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 1992static void gen_spr_compress (CPUPPCState *env)
1993{
578bb252 1994 /* XXX : not implemented */
76a66253
JM		 1995 spr_register(env, SPR_401_SKR, "SKR",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999}
a750fc0b
JM		 2000
2001#if defined (TARGET_PPC64)
a750fc0b
JM		 2002/* SPR specific to PowerPC 620 */
2003static void gen_spr_620 (CPUPPCState *env)
2004{
082c6681
JM		 2005 /* Processor identification */
2006 spr_register(env, SPR_PIR, "PIR",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 &spr_read_generic, &spr_write_pir,
2009 0x00000000);
2010 spr_register(env, SPR_ASR, "ASR",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_asr, &spr_write_asr,
2013 0x00000000);
2014 /* Breakpoints */
2015 /* XXX : not implemented */
2016 spr_register(env, SPR_IABR, "IABR",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_generic,
2019 0x00000000);
2020 /* XXX : not implemented */
2021 spr_register(env, SPR_DABR, "DABR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_SIAR, "SIAR",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, SPR_NOACCESS,
2029 0x00000000);
2030 /* XXX : not implemented */
2031 spr_register(env, SPR_SDA, "SDA",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, SPR_NOACCESS,
2034 0x00000000);
2035 /* XXX : not implemented */
2036 spr_register(env, SPR_620_PMC1R, "PMC1",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, SPR_NOACCESS,
2039 0x00000000);
2040 spr_register(env, SPR_620_PMC1W, "PMC1",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 SPR_NOACCESS, &spr_write_generic,
2043 0x00000000);
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_620_PMC2R, "PMC2",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, SPR_NOACCESS,
2048 0x00000000);
2049 spr_register(env, SPR_620_PMC2W, "PMC2",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 SPR_NOACCESS, &spr_write_generic,
2052 0x00000000);
2053 /* XXX : not implemented */
2054 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, SPR_NOACCESS,
2057 0x00000000);
2058 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 SPR_NOACCESS, &spr_write_generic,
2061 0x00000000);
2062 /* External access control */
2063 /* XXX : not implemented */
2064 spr_register(env, SPR_EAR, "EAR",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068#if 0 // XXX: check this
578bb252 2069 /* XXX : not implemented */
a750fc0b
JM		 2070 spr_register(env, SPR_620_PMR0, "PMR0",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
578bb252 2074 /* XXX : not implemented */
a750fc0b
JM		 2075 spr_register(env, SPR_620_PMR1, "PMR1",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_generic,
2078 0x00000000);
578bb252 2079 /* XXX : not implemented */
a750fc0b
JM		 2080 spr_register(env, SPR_620_PMR2, "PMR2",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
578bb252 2084 /* XXX : not implemented */
a750fc0b
JM		 2085 spr_register(env, SPR_620_PMR3, "PMR3",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
578bb252 2089 /* XXX : not implemented */
a750fc0b
JM		 2090 spr_register(env, SPR_620_PMR4, "PMR4",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
578bb252 2094 /* XXX : not implemented */
a750fc0b
JM		 2095 spr_register(env, SPR_620_PMR5, "PMR5",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
578bb252 2099 /* XXX : not implemented */
a750fc0b
JM		 2100 spr_register(env, SPR_620_PMR6, "PMR6",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
578bb252 2104 /* XXX : not implemented */
a750fc0b
JM		 2105 spr_register(env, SPR_620_PMR7, "PMR7",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
578bb252 2109 /* XXX : not implemented */
a750fc0b
JM		 2110 spr_register(env, SPR_620_PMR8, "PMR8",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
578bb252 2114 /* XXX : not implemented */
a750fc0b
JM		 2115 spr_register(env, SPR_620_PMR9, "PMR9",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_generic, &spr_write_generic,
2118 0x00000000);
578bb252 2119 /* XXX : not implemented */
a750fc0b
JM		 2120 spr_register(env, SPR_620_PMRA, "PMR10",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_generic,
2123 0x00000000);
578bb252 2124 /* XXX : not implemented */
a750fc0b
JM		 2125 spr_register(env, SPR_620_PMRB, "PMR11",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
578bb252 2129 /* XXX : not implemented */
a750fc0b
JM		 2130 spr_register(env, SPR_620_PMRC, "PMR12",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 &spr_read_generic, &spr_write_generic,
2133 0x00000000);
578bb252 2134 /* XXX : not implemented */
a750fc0b
JM		 2135 spr_register(env, SPR_620_PMRD, "PMR13",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
578bb252 2139 /* XXX : not implemented */
a750fc0b
JM		 2140 spr_register(env, SPR_620_PMRE, "PMR14",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
578bb252 2144 /* XXX : not implemented */
a750fc0b
JM		 2145 spr_register(env, SPR_620_PMRF, "PMR15",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
082c6681 2149#endif
578bb252 2150 /* XXX : not implemented */
082c6681 2151 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
578bb252 2155 /* XXX : not implemented */
082c6681
JM		 2156 spr_register(env, SPR_620_L2CR, "L2CR",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_generic, &spr_write_generic,
2159 0x00000000);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, &spr_write_generic,
2164 0x00000000);
2165}
a750fc0b 2166#endif /* defined (TARGET_PPC64) */
76a66253 2167
80d11f44 2168static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2169{
80d11f44
JM		 2170 /* Exception processing */
2171 spr_register(env, SPR_DSISR, "DSISR",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_DAR, "DAR",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179 /* Timer */
2180 spr_register(env, SPR_DECR, "DECR",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_decr, &spr_write_decr,
2183 0x00000000);
2184 /* XXX : not implemented */
2185 spr_register(env, SPR_MPC_EIE, "EIE",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_generic, &spr_write_generic,
2188 0x00000000);
2189 /* XXX : not implemented */
2190 spr_register(env, SPR_MPC_EID, "EID",
2191 SPR_NOACCESS, SPR_NOACCESS,
2192 &spr_read_generic, &spr_write_generic,
2193 0x00000000);
2194 /* XXX : not implemented */
2195 spr_register(env, SPR_MPC_NRI, "NRI",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 /* XXX : not implemented */
2200 spr_register(env, SPR_MPC_CMPA, "CMPA",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 0x00000000);
2204 /* XXX : not implemented */
2205 spr_register(env, SPR_MPC_CMPB, "CMPB",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_generic, &spr_write_generic,
2208 0x00000000);
2209 /* XXX : not implemented */
2210 spr_register(env, SPR_MPC_CMPC, "CMPC",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 /* XXX : not implemented */
2215 spr_register(env, SPR_MPC_CMPD, "CMPD",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_MPC_ECR, "ECR",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 /* XXX : not implemented */
2225 spr_register(env, SPR_MPC_DER, "DER",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_CMPE, "CMPE",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_CMPF, "CMPF",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_CMPG, "CMPG",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_CMPH, "CMPH",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_BAR, "BAR",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_DPDR, "DPDR",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_IMMR, "IMMR",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284}
2285
2286static void gen_spr_5xx (CPUPPCState *env)
2287{
2288 /* XXX : not implemented */
2289 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 /* XXX : not implemented */
2294 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* XXX : not implemented */
2299 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393}
2394
2395static void gen_spr_8xx (CPUPPCState *env)
2396{
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522}
2523
2524// XXX: TODO
2525/*
2526 * AMR => SPR 29 (Power 2.04)
2527 * CTRL => SPR 136 (Power 2.04)
2528 * CTRL => SPR 152 (Power 2.04)
2529 * SCOMC => SPR 276 (64 bits ?)
2530 * SCOMD => SPR 277 (64 bits ?)
2531 * TBU40 => SPR 286 (Power 2.04 hypv)
2532 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2533 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2534 * HDSISR => SPR 306 (Power 2.04 hypv)
2535 * HDAR => SPR 307 (Power 2.04 hypv)
2536 * PURR => SPR 309 (Power 2.04 hypv)
2537 * HDEC => SPR 310 (Power 2.04 hypv)
2538 * HIOR => SPR 311 (hypv)
2539 * RMOR => SPR 312 (970)
2540 * HRMOR => SPR 313 (Power 2.04 hypv)
2541 * HSRR0 => SPR 314 (Power 2.04 hypv)
2542 * HSRR1 => SPR 315 (Power 2.04 hypv)
2543 * LPCR => SPR 316 (970)
2544 * LPIDR => SPR 317 (970)
2545 * SPEFSCR => SPR 512 (Power 2.04 emb)
2546 * EPR => SPR 702 (Power 2.04 emb)
2547 * perf => 768-783 (Power 2.04)
2548 * perf => 784-799 (Power 2.04)
2549 * PPR => SPR 896 (Power 2.04)
2550 * EPLC => SPR 947 (Power 2.04 emb)
2551 * EPSC => SPR 948 (Power 2.04 emb)
2552 * DABRX => 1015 (Power 2.04 hypv)
2553 * FPECR => SPR 1022 (?)
2554 * ... and more (thermal management, performance counters, ...)
2555 */
2556
2557/*****************************************************************************/
2558/* Exception vectors models */
2559static void init_excp_4xx_real (CPUPPCState *env)
2560{
2561#if !defined(CONFIG_USER_ONLY)
2562 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2563 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2564 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2565 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2566 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2567 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2568 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2569 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2570 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2571 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
faadf50e 2572 env->excp_prefix = 0x00000000UL;
80d11f44 2573 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2574 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2575 /* Hardware reset vector */
2576 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2577#endif
2578}
2579
80d11f44
JM		 2580static void init_excp_4xx_softmmu (CPUPPCState *env)
2581{
2582#if !defined(CONFIG_USER_ONLY)
2583 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2584 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2585 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2586 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2587 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2588 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2589 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2590 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2591 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2592 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2593 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2594 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2595 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2596 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2597 env->excp_prefix = 0x00000000UL;
2598 env->ivor_mask = 0x0000FFF0UL;
2599 env->ivpr_mask = 0xFFFF0000UL;
2600 /* Hardware reset vector */
2601 env->hreset_vector = 0xFFFFFFFCUL;
2602#endif
2603}
2604
2605static void init_excp_MPC5xx (CPUPPCState *env)
2606{
2607#if !defined(CONFIG_USER_ONLY)
2608 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2609 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2610 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2611 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2612 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2613 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2614 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2615 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2616 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2617 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2618 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2619 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2620 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2621 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2622 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2623 env->excp_prefix = 0x00000000UL;
2624 env->ivor_mask = 0x0000FFF0UL;
2625 env->ivpr_mask = 0xFFFF0000UL;
2626 /* Hardware reset vector */
2627 env->hreset_vector = 0xFFFFFFFCUL;
2628#endif
2629}
2630
2631static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2632{
2633#if !defined(CONFIG_USER_ONLY)
2634 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2635 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2636 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2637 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2638 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2639 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2640 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2641 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2642 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2643 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2644 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2645 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2646 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2647 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2648 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2649 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2650 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2651 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2652 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2653 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2654 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2655 env->excp_prefix = 0x00000000UL;
2656 env->ivor_mask = 0x0000FFF0UL;
2657 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2658 /* Hardware reset vector */
80d11f44 2659 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2660#endif
2661}
2662
80d11f44 2663static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2664{
2665#if !defined(CONFIG_USER_ONLY)
2666 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2667 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2668 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2669 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2670 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2671 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2672 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2673 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2674 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2675 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2676 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2677 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2678 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2679 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2680 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2681 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2682 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2683 env->excp_prefix = 0x00000000UL;
2684 /* Hardware reset vector */
2685 env->hreset_vector = 0xFFFFFFFCUL;
2686#endif
2687}
2688
2689static void init_excp_e200 (CPUPPCState *env)
2690{
2691#if !defined(CONFIG_USER_ONLY)
2692 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2693 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2694 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2695 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2696 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2697 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2698 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2699 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2700 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2701 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2702 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2703 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2704 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2705 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2706 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2707 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2708 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2709 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2710 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2711 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2712 env->excp_prefix = 0x00000000UL;
2713 env->ivor_mask = 0x0000FFF7UL;
2714 env->ivpr_mask = 0xFFFF0000UL;
2715 /* Hardware reset vector */
2716 env->hreset_vector = 0xFFFFFFFCUL;
2717#endif
2718}
2719
2720static void init_excp_BookE (CPUPPCState *env)
2721{
2722#if !defined(CONFIG_USER_ONLY)
2723 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2724 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2725 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2739 env->excp_prefix = 0x00000000UL;
2740 env->ivor_mask = 0x0000FFE0UL;
2741 env->ivpr_mask = 0xFFFF0000UL;
2742 /* Hardware reset vector */
2743 env->hreset_vector = 0xFFFFFFFCUL;
2744#endif
2745}
2746
2747static void init_excp_601 (CPUPPCState *env)
2748{
2749#if !defined(CONFIG_USER_ONLY)
2750 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2751 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2752 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2753 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2754 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2755 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2756 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2757 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2758 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2759 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2760 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2761 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
faadf50e 2762 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2763 /* Hardware reset vector */
80d11f44 2764 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2765#endif
2766}
2767
80d11f44 2768static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2769{
2770#if !defined(CONFIG_USER_ONLY)
082c6681 2771 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2772 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2773 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2774 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2775 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2776 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2777 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2778 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2779 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2780 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2781 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2782 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2783 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2784 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2785 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2786 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2787 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2788 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2789 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2790 env->excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2791 /* Hardware reset vector */
2792 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2793#endif
2794}
2795
80d11f44 2796static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2797{
2798#if !defined(CONFIG_USER_ONLY)
2799 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2800 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2801 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2802 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2803 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2804 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2805 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2806 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2807 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2808 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2809 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2810 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2811 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2812 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2813 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2814 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2815 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2816 /* Hardware reset vector */
2817 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2818#endif
2819}
2820
2821static void init_excp_604 (CPUPPCState *env)
2822{
2823#if !defined(CONFIG_USER_ONLY)
2824 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2825 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2826 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2827 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2828 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2829 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2830 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2831 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2832 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2833 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2834 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2835 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2836 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2837 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2838 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2839 /* Hardware reset vector */
2840 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2841#endif
2842}
2843
578bb252 2844#if defined(TARGET_PPC64)
e1833e1f
JM		 2845static void init_excp_620 (CPUPPCState *env)
2846{
2847#if !defined(CONFIG_USER_ONLY)
2848 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2849 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2850 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2851 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2852 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2853 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2854 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2855 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2856 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2857 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2858 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2859 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2860 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2861 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
faadf50e 2862 env->excp_prefix = 0xFFF00000UL;
1c27f8fb 2863 /* Hardware reset vector */
faadf50e 2864 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2865#endif
2866}
578bb252 2867#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2868
2869static void init_excp_7x0 (CPUPPCState *env)
2870{
2871#if !defined(CONFIG_USER_ONLY)
2872 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2873 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2874 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2875 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2876 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2877 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2878 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2879 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2880 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2881 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2882 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2883 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2884 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 2885 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 2886 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2887 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2888 /* Hardware reset vector */
2889 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2890#endif
2891}
2892
bd928eba 2893static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 2894{
2895#if !defined(CONFIG_USER_ONLY)
2896 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2897 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2898 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2899 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2900 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2901 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2902 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2903 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2904 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2905 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2906 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2907 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2908 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2909 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba
JM		 2910 env->excp_prefix = 0x00000000UL;
2911 /* Hardware reset vector */
2912 env->hreset_vector = 0xFFFFFFFCUL;
2913#endif
2914}
2915
2916static void init_excp_750cx (CPUPPCState *env)
2917{
2918#if !defined(CONFIG_USER_ONLY)
2919 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2920 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2921 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2922 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2923 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2924 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2925 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2926 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2927 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2928 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2929 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2930 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2931 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 2932 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2933 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2936#endif
2937}
2938
7a3a6927
JM		 2939/* XXX: Check if this is correct */
2940static void init_excp_7x5 (CPUPPCState *env)
2941{
2942#if !defined(CONFIG_USER_ONLY)
2943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 2955 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2956 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2957 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 2958 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2959 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 2960 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2961 env->excp_prefix = 0x00000000UL;
7a3a6927
JM		 2962 /* Hardware reset vector */
2963 env->hreset_vector = 0xFFFFFFFCUL;
2964#endif
2965}
2966
e1833e1f
JM		 2967static void init_excp_7400 (CPUPPCState *env)
2968{
2969#if !defined(CONFIG_USER_ONLY)
2970 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2971 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2972 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2973 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2974 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2975 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2976 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2977 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2978 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2979 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2980 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2981 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2982 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2983 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2984 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2985 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2986 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
faadf50e 2987 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2988 /* Hardware reset vector */
2989 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2990#endif
2991}
2992
e1833e1f
JM		 2993static void init_excp_7450 (CPUPPCState *env)
2994{
2995#if !defined(CONFIG_USER_ONLY)
2996 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2997 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2998 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2999 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3000 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3001 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3002 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3003 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3004 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3005 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3006 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3007 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3008 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3009 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3010 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3011 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3012 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3013 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3014 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
faadf50e 3015 env->excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3016 /* Hardware reset vector */
3017 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3018#endif
3019}
e1833e1f
JM		 3020
3021#if defined (TARGET_PPC64)
3022static void init_excp_970 (CPUPPCState *env)
3023{
3024#if !defined(CONFIG_USER_ONLY)
3025 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3026 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3027 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3028 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3029 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3030 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3031 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3032 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3033 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3034 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3035 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3036 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3037 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3038 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3039 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3040 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3041 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3042 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3043 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3044 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
faadf50e 3045 env->excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3046 /* Hardware reset vector */
3047 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3048#endif
3049}
3050#endif
3051
2f462816
JM		 3052/*****************************************************************************/
3053/* Power management enable checks */
3054static int check_pow_none (CPUPPCState *env)
3055{
3056 return 0;
3057}
3058
3059static int check_pow_nocheck (CPUPPCState *env)
3060{
3061 return 1;
3062}
3063
3064static int check_pow_hid0 (CPUPPCState *env)
3065{
3066 if (env->spr[SPR_HID0] & 0x00E00000)
3067 return 1;
3068
3069 return 0;
3070}
3071
4e777442
JM		 3072static int check_pow_hid0_74xx (CPUPPCState *env)
3073{
3074 if (env->spr[SPR_HID0] & 0x00600000)
3075 return 1;
3076
3077 return 0;
3078}
3079
a750fc0b
JM		 3080/*****************************************************************************/
3081/* PowerPC implementations definitions */
76a66253 3082
a750fc0b 3083/* PowerPC 401 */
082c6681
JM		 3084#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3085 PPC_WRTEE | PPC_DCR | \
3086 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3087 PPC_CACHE_DCBZ | \
a750fc0b 3088 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3089 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3090#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3091#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3092#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3093#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3094#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3095#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3096 POWERPC_FLAG_BUS_CLK)
2f462816 3097#define check_pow_401 check_pow_nocheck
76a66253 3098
a750fc0b
JM		 3099static void init_proc_401 (CPUPPCState *env)
3100{
3101 gen_spr_40x(env);
3102 gen_spr_401_403(env);
3103 gen_spr_401(env);
e1833e1f 3104 init_excp_4xx_real(env);
d63001d1
JM		 3105 env->dcache_line_size = 32;
3106 env->icache_line_size = 32;
4e290a0b
JM		 3107 /* Allocate hardware IRQ controller */
3108 ppc40x_irq_init(env);
a750fc0b 3109}
76a66253 3110
a750fc0b 3111/* PowerPC 401x2 */
082c6681
JM		 3112#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3113 PPC_DCR | PPC_WRTEE | \
3114 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3115 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3116 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3117 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3118 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3119#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3120#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3121#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3122#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3123#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3124#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3125 POWERPC_FLAG_BUS_CLK)
2f462816 3126#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3127
3128static void init_proc_401x2 (CPUPPCState *env)
3129{
3130 gen_spr_40x(env);
3131 gen_spr_401_403(env);
3132 gen_spr_401x2(env);
3133 gen_spr_compress(env);
a750fc0b 3134 /* Memory management */
f2e63a42 3135#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3136 env->nb_tlb = 64;
3137 env->nb_ways = 1;
3138 env->id_tlbs = 0;
f2e63a42 3139#endif
e1833e1f 3140 init_excp_4xx_softmmu(env);
d63001d1
JM		 3141 env->dcache_line_size = 32;
3142 env->icache_line_size = 32;
4e290a0b
JM		 3143 /* Allocate hardware IRQ controller */
3144 ppc40x_irq_init(env);
76a66253
JM		 3145}
3146
a750fc0b 3147/* PowerPC 401x3 */
082c6681
JM		 3148#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3149 PPC_DCR | PPC_WRTEE | \
3150 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3151 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3152 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3153 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3154 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3155#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3156#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3157#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3158#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3159#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3160#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3161 POWERPC_FLAG_BUS_CLK)
2f462816 3162#define check_pow_401x3 check_pow_nocheck
a750fc0b 3163
578bb252 3164__attribute__ (( unused ))
e1833e1f 3165static void init_proc_401x3 (CPUPPCState *env)
76a66253 3166{
4e290a0b
JM		 3167 gen_spr_40x(env);
3168 gen_spr_401_403(env);
3169 gen_spr_401(env);
3170 gen_spr_401x2(env);
3171 gen_spr_compress(env);
e1833e1f 3172 init_excp_4xx_softmmu(env);
d63001d1
JM		 3173 env->dcache_line_size = 32;
3174 env->icache_line_size = 32;
4e290a0b
JM		 3175 /* Allocate hardware IRQ controller */
3176 ppc40x_irq_init(env);
3fc6c082 3177}
a750fc0b
JM		 3178
3179/* IOP480 */
082c6681
JM		 3180#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3181 PPC_DCR | PPC_WRTEE | \
3182 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3183 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3184 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3185 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3186 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3187#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3188#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3189#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3190#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3191#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3192#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3193 POWERPC_FLAG_BUS_CLK)
2f462816 3194#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3195
3196static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3197{
a750fc0b
JM		 3198 gen_spr_40x(env);
3199 gen_spr_401_403(env);
3200 gen_spr_401x2(env);
3201 gen_spr_compress(env);
a750fc0b 3202 /* Memory management */
f2e63a42 3203#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3204 env->nb_tlb = 64;
3205 env->nb_ways = 1;
3206 env->id_tlbs = 0;
f2e63a42 3207#endif
e1833e1f 3208 init_excp_4xx_softmmu(env);
d63001d1
JM		 3209 env->dcache_line_size = 32;
3210 env->icache_line_size = 32;
4e290a0b
JM		 3211 /* Allocate hardware IRQ controller */
3212 ppc40x_irq_init(env);
3fc6c082
FB		 3213}
3214
a750fc0b 3215/* PowerPC 403 */
082c6681
JM		 3216#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3217 PPC_DCR | PPC_WRTEE | \
3218 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3219 PPC_CACHE_DCBZ | \
a750fc0b 3220 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3221 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b 3222#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3223#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3224#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3225#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3226#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3227#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3228 POWERPC_FLAG_BUS_CLK)
2f462816 3229#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3230
3231static void init_proc_403 (CPUPPCState *env)
3fc6c082 3232{
a750fc0b
JM		 3233 gen_spr_40x(env);
3234 gen_spr_401_403(env);
3235 gen_spr_403(env);
3236 gen_spr_403_real(env);
e1833e1f 3237 init_excp_4xx_real(env);
d63001d1
JM		 3238 env->dcache_line_size = 32;
3239 env->icache_line_size = 32;
4e290a0b
JM		 3240 /* Allocate hardware IRQ controller */
3241 ppc40x_irq_init(env);
3fc6c082
FB		 3242}
3243
a750fc0b 3244/* PowerPC 403 GCX */
082c6681
JM		 3245#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3246 PPC_DCR | PPC_WRTEE | \
3247 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3248 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3249 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3250 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3251 PPC_4xx_COMMON | PPC_40x_EXCP)
a750fc0b
JM		 3252#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3253#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3254#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3255#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3256#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3257#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3258 POWERPC_FLAG_BUS_CLK)
2f462816 3259#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3260
3261static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3262{
a750fc0b
JM		 3263 gen_spr_40x(env);
3264 gen_spr_401_403(env);
3265 gen_spr_403(env);
3266 gen_spr_403_real(env);
3267 gen_spr_403_mmu(env);
3268 /* Bus access control */
035feb88 3269 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3270 spr_register(env, SPR_40x_SGR, "SGR",
3271 SPR_NOACCESS, SPR_NOACCESS,
3272 &spr_read_generic, &spr_write_generic,
3273 0xFFFFFFFF);
035feb88 3274 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3275 spr_register(env, SPR_40x_DCWR, "DCWR",
3276 SPR_NOACCESS, SPR_NOACCESS,
3277 &spr_read_generic, &spr_write_generic,
3278 0x00000000);
3279 /* Memory management */
f2e63a42 3280#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3281 env->nb_tlb = 64;
3282 env->nb_ways = 1;
3283 env->id_tlbs = 0;
f2e63a42 3284#endif
80d11f44
JM		 3285 init_excp_4xx_softmmu(env);
3286 env->dcache_line_size = 32;
3287 env->icache_line_size = 32;
3288 /* Allocate hardware IRQ controller */
3289 ppc40x_irq_init(env);
3290}
3291
3292/* PowerPC 405 */
082c6681
JM		 3293#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3294 PPC_DCR | PPC_WRTEE | \
3295 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3296 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3297 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3298 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3299 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
80d11f44
JM		 3300#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3301#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3302#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3303#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3304#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3305#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3306 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3307#define check_pow_405 check_pow_nocheck
3308
3309static void init_proc_405 (CPUPPCState *env)
3310{
3311 /* Time base */
3312 gen_tbl(env);
3313 gen_spr_40x(env);
3314 gen_spr_405(env);
3315 /* Bus access control */
3316 /* not emulated, as Qemu never does speculative access */
3317 spr_register(env, SPR_40x_SGR, "SGR",
3318 SPR_NOACCESS, SPR_NOACCESS,
3319 &spr_read_generic, &spr_write_generic,
3320 0xFFFFFFFF);
3321 /* not emulated, as Qemu do not emulate caches */
3322 spr_register(env, SPR_40x_DCWR, "DCWR",
3323 SPR_NOACCESS, SPR_NOACCESS,
3324 &spr_read_generic, &spr_write_generic,
3325 0x00000000);
3326 /* Memory management */
3327#if !defined(CONFIG_USER_ONLY)
3328 env->nb_tlb = 64;
3329 env->nb_ways = 1;
3330 env->id_tlbs = 0;
3331#endif
3332 init_excp_4xx_softmmu(env);
3333 env->dcache_line_size = 32;
3334 env->icache_line_size = 32;
3335 /* Allocate hardware IRQ controller */
3336 ppc40x_irq_init(env);
3337}
3338
3339/* PowerPC 440 EP */
082c6681
JM		 3340#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3341 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3342 PPC_CACHE | PPC_CACHE_ICBI | \
3343 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3344 PPC_MEM_TLBSYNC | \
80d11f44 3345 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3346 PPC_440_SPEC)
80d11f44
JM		 3347#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3348#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3349#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3350#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3351#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3352#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3353 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3354#define check_pow_440EP check_pow_nocheck
3355
3356__attribute__ (( unused ))
3357static void init_proc_440EP (CPUPPCState *env)
3358{
3359 /* Time base */
3360 gen_tbl(env);
3361 gen_spr_BookE(env, 0x000000000000FFFFULL);
3362 gen_spr_440(env);
3363 gen_spr_usprgh(env);
3364 /* Processor identification */
3365 spr_register(env, SPR_BOOKE_PIR, "PIR",
3366 SPR_NOACCESS, SPR_NOACCESS,
3367 &spr_read_generic, &spr_write_pir,
3368 0x00000000);
3369 /* XXX : not implemented */
3370 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3371 SPR_NOACCESS, SPR_NOACCESS,
3372 &spr_read_generic, &spr_write_generic,
3373 0x00000000);
3374 /* XXX : not implemented */
3375 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3376 SPR_NOACCESS, SPR_NOACCESS,
3377 &spr_read_generic, &spr_write_generic,
3378 0x00000000);
3379 /* XXX : not implemented */
3380 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3381 SPR_NOACCESS, SPR_NOACCESS,
3382 &spr_read_generic, &spr_write_generic,
3383 0x00000000);
3384 /* XXX : not implemented */
3385 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3386 SPR_NOACCESS, SPR_NOACCESS,
3387 &spr_read_generic, &spr_write_generic,
3388 0x00000000);
3389 /* XXX : not implemented */
3390 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3391 SPR_NOACCESS, SPR_NOACCESS,
3392 &spr_read_generic, &spr_write_generic,
3393 0x00000000);
3394 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3395 SPR_NOACCESS, SPR_NOACCESS,
3396 &spr_read_generic, &spr_write_generic,
3397 0x00000000);
3398 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3399 SPR_NOACCESS, SPR_NOACCESS,
3400 &spr_read_generic, &spr_write_generic,
3401 0x00000000);
3402 /* XXX : not implemented */
3403 spr_register(env, SPR_440_CCR1, "CCR1",
3404 SPR_NOACCESS, SPR_NOACCESS,
3405 &spr_read_generic, &spr_write_generic,
3406 0x00000000);
3407 /* Memory management */
3408#if !defined(CONFIG_USER_ONLY)
3409 env->nb_tlb = 64;
3410 env->nb_ways = 1;
3411 env->id_tlbs = 0;
3412#endif
3413 init_excp_BookE(env);
3414 env->dcache_line_size = 32;
3415 env->icache_line_size = 32;
3416 /* XXX: TODO: allocate internal IRQ controller */
3417}
3418
3419/* PowerPC 440 GP */
082c6681
JM		 3420#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3421 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3422 PPC_CACHE | PPC_CACHE_ICBI | \
3423 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3424 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3425 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3426 PPC_440_SPEC)
80d11f44
JM		 3427#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3428#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3429#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3430#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3431#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3432#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3433 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3434#define check_pow_440GP check_pow_nocheck
3435
3436__attribute__ (( unused ))
3437static void init_proc_440GP (CPUPPCState *env)
3438{
3439 /* Time base */
3440 gen_tbl(env);
3441 gen_spr_BookE(env, 0x000000000000FFFFULL);
3442 gen_spr_440(env);
3443 gen_spr_usprgh(env);
3444 /* Processor identification */
3445 spr_register(env, SPR_BOOKE_PIR, "PIR",
3446 SPR_NOACCESS, SPR_NOACCESS,
3447 &spr_read_generic, &spr_write_pir,
3448 0x00000000);
3449 /* XXX : not implemented */
3450 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3451 SPR_NOACCESS, SPR_NOACCESS,
3452 &spr_read_generic, &spr_write_generic,
3453 0x00000000);
3454 /* XXX : not implemented */
3455 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3456 SPR_NOACCESS, SPR_NOACCESS,
3457 &spr_read_generic, &spr_write_generic,
3458 0x00000000);
3459 /* XXX : not implemented */
3460 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3461 SPR_NOACCESS, SPR_NOACCESS,
3462 &spr_read_generic, &spr_write_generic,
3463 0x00000000);
3464 /* XXX : not implemented */
3465 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, &spr_write_generic,
3468 0x00000000);
3469 /* Memory management */
3470#if !defined(CONFIG_USER_ONLY)
3471 env->nb_tlb = 64;
3472 env->nb_ways = 1;
3473 env->id_tlbs = 0;
3474#endif
3475 init_excp_BookE(env);
3476 env->dcache_line_size = 32;
3477 env->icache_line_size = 32;
3478 /* XXX: TODO: allocate internal IRQ controller */
3479}
3480
3481/* PowerPC 440x4 */
082c6681
JM		 3482#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3483 PPC_DCR | PPC_WRTEE | \
3484 PPC_CACHE | PPC_CACHE_ICBI | \
3485 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3486 PPC_MEM_TLBSYNC | \
80d11f44
JM		 3487 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3488 PPC_440_SPEC)
3489#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3490#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3491#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3492#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3493#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3494#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3495 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3496#define check_pow_440x4 check_pow_nocheck
3497
3498__attribute__ (( unused ))
3499static void init_proc_440x4 (CPUPPCState *env)
3500{
3501 /* Time base */
3502 gen_tbl(env);
3503 gen_spr_BookE(env, 0x000000000000FFFFULL);
3504 gen_spr_440(env);
3505 gen_spr_usprgh(env);
3506 /* Processor identification */
3507 spr_register(env, SPR_BOOKE_PIR, "PIR",
3508 SPR_NOACCESS, SPR_NOACCESS,
3509 &spr_read_generic, &spr_write_pir,
3510 0x00000000);
3511 /* XXX : not implemented */
3512 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3513 SPR_NOACCESS, SPR_NOACCESS,
3514 &spr_read_generic, &spr_write_generic,
3515 0x00000000);
3516 /* XXX : not implemented */
3517 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_generic,
3520 0x00000000);
3521 /* XXX : not implemented */
3522 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3523 SPR_NOACCESS, SPR_NOACCESS,
3524 &spr_read_generic, &spr_write_generic,
3525 0x00000000);
3526 /* XXX : not implemented */
3527 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3528 SPR_NOACCESS, SPR_NOACCESS,
3529 &spr_read_generic, &spr_write_generic,
3530 0x00000000);
3531 /* Memory management */
3532#if !defined(CONFIG_USER_ONLY)
3533 env->nb_tlb = 64;
3534 env->nb_ways = 1;
3535 env->id_tlbs = 0;
3536#endif
3537 init_excp_BookE(env);
d63001d1
JM		 3538 env->dcache_line_size = 32;
3539 env->icache_line_size = 32;
80d11f44 3540 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3541}
3542
80d11f44 3543/* PowerPC 440x5 */
082c6681
JM		 3544#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3545 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3546 PPC_CACHE | PPC_CACHE_ICBI | \
3547 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3548 PPC_MEM_TLBSYNC | \
80d11f44 3549 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3550 PPC_440_SPEC)
80d11f44
JM		 3551#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3552#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3553#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3554#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3555#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3556#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3557 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3558#define check_pow_440x5 check_pow_nocheck
a750fc0b 3559
80d11f44
JM		 3560__attribute__ (( unused ))
3561static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3562{
a750fc0b
JM		 3563 /* Time base */
3564 gen_tbl(env);
80d11f44
JM		 3565 gen_spr_BookE(env, 0x000000000000FFFFULL);
3566 gen_spr_440(env);
3567 gen_spr_usprgh(env);
3568 /* Processor identification */
3569 spr_register(env, SPR_BOOKE_PIR, "PIR",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_pir,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3577 0x00000000);
3578 /* XXX : not implemented */
3579 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
3587 0x00000000);
3588 /* XXX : not implemented */
3589 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3590 SPR_NOACCESS, SPR_NOACCESS,
3591 &spr_read_generic, &spr_write_generic,
3592 0x00000000);
3593 /* XXX : not implemented */
3594 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3595 SPR_NOACCESS, SPR_NOACCESS,
3596 &spr_read_generic, &spr_write_generic,
3597 0x00000000);
3598 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3599 SPR_NOACCESS, SPR_NOACCESS,
3600 &spr_read_generic, &spr_write_generic,
3601 0x00000000);
3602 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3603 SPR_NOACCESS, SPR_NOACCESS,
3604 &spr_read_generic, &spr_write_generic,
3605 0x00000000);
3606 /* XXX : not implemented */
3607 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3608 SPR_NOACCESS, SPR_NOACCESS,
3609 &spr_read_generic, &spr_write_generic,
3610 0x00000000);
3611 /* Memory management */
f2e63a42 3612#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3613 env->nb_tlb = 64;
3614 env->nb_ways = 1;
3615 env->id_tlbs = 0;
f2e63a42 3616#endif
80d11f44 3617 init_excp_BookE(env);
d63001d1
JM		 3618 env->dcache_line_size = 32;
3619 env->icache_line_size = 32;
80d11f44 3620 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3621}
3622
80d11f44 3623/* PowerPC 460 (guessed) */
082c6681 3624#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3625 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
082c6681
JM		 3626 PPC_WRTEE | PPC_MFAPIDI | \
3627 PPC_CACHE | PPC_CACHE_ICBI | \
3628 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3629 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3630 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3631 PPC_440_SPEC)
80d11f44
JM		 3632#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3633#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3634#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3635#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3636#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3637#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3638 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3639#define check_pow_460 check_pow_nocheck
a750fc0b 3640
80d11f44
JM		 3641__attribute__ (( unused ))
3642static void init_proc_460 (CPUPPCState *env)
3fc6c082 3643{
a750fc0b
JM		 3644 /* Time base */
3645 gen_tbl(env);
80d11f44 3646 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3647 gen_spr_440(env);
80d11f44
JM		 3648 gen_spr_usprgh(env);
3649 /* Processor identification */
3650 spr_register(env, SPR_BOOKE_PIR, "PIR",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_pir,
3653 0x00000000);
3654 /* XXX : not implemented */
3655 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3656 SPR_NOACCESS, SPR_NOACCESS,
3657 &spr_read_generic, &spr_write_generic,
3658 0x00000000);
3659 /* XXX : not implemented */
3660 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3661 SPR_NOACCESS, SPR_NOACCESS,
3662 &spr_read_generic, &spr_write_generic,
3663 0x00000000);
3664 /* XXX : not implemented */
3665 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_generic,
3668 0x00000000);
3669 /* XXX : not implemented */
3670 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
578bb252 3674 /* XXX : not implemented */
a750fc0b
JM		 3675 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3686 0x00000000);
578bb252 3687 /* XXX : not implemented */
a750fc0b
JM		 3688 spr_register(env, SPR_440_CCR1, "CCR1",
3689 SPR_NOACCESS, SPR_NOACCESS,
3690 &spr_read_generic, &spr_write_generic,
3691 0x00000000);
80d11f44
JM		 3692 /* XXX : not implemented */
3693 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3694 &spr_read_generic, &spr_write_generic,
3695 &spr_read_generic, &spr_write_generic,
3696 0x00000000);
a750fc0b 3697 /* Memory management */
f2e63a42 3698#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3699 env->nb_tlb = 64;
3700 env->nb_ways = 1;
3701 env->id_tlbs = 0;
f2e63a42 3702#endif
e1833e1f 3703 init_excp_BookE(env);
d63001d1
JM		 3704 env->dcache_line_size = 32;
3705 env->icache_line_size = 32;
a750fc0b 3706 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3707}
3708
80d11f44 3709/* PowerPC 460F (guessed) */
082c6681
JM		 3710#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3711 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3712 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
80d11f44 3713 PPC_FLOAT_STFIWX | \
082c6681
JM		 3714 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3715 PPC_WRTEE | PPC_MFAPIDI | \
3716 PPC_CACHE | PPC_CACHE_ICBI | \
3717 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3718 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3719 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3720 PPC_440_SPEC)
80d11f44
JM		 3721#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3722#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3723#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3724#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3725#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3726#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3727 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3728#define check_pow_460F check_pow_nocheck
a750fc0b 3729
80d11f44
JM		 3730__attribute__ (( unused ))
3731static void init_proc_460F (CPUPPCState *env)
3fc6c082 3732{
a750fc0b
JM		 3733 /* Time base */
3734 gen_tbl(env);
80d11f44 3735 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3736 gen_spr_440(env);
80d11f44
JM		 3737 gen_spr_usprgh(env);
3738 /* Processor identification */
3739 spr_register(env, SPR_BOOKE_PIR, "PIR",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_pir,
3742 0x00000000);
3743 /* XXX : not implemented */
3744 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 /* XXX : not implemented */
3749 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3750 SPR_NOACCESS, SPR_NOACCESS,
3751 &spr_read_generic, &spr_write_generic,
3752 0x00000000);
3753 /* XXX : not implemented */
3754 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3755 SPR_NOACCESS, SPR_NOACCESS,
3756 &spr_read_generic, &spr_write_generic,
3757 0x00000000);
3758 /* XXX : not implemented */
3759 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3760 SPR_NOACCESS, SPR_NOACCESS,
3761 &spr_read_generic, &spr_write_generic,
3762 0x00000000);
3763 /* XXX : not implemented */
3764 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3765 SPR_NOACCESS, SPR_NOACCESS,
3766 &spr_read_generic, &spr_write_generic,
3767 0x00000000);
3768 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3769 SPR_NOACCESS, SPR_NOACCESS,
3770 &spr_read_generic, &spr_write_generic,
3771 0x00000000);
3772 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3773 SPR_NOACCESS, SPR_NOACCESS,
3774 &spr_read_generic, &spr_write_generic,
3775 0x00000000);
3776 /* XXX : not implemented */
3777 spr_register(env, SPR_440_CCR1, "CCR1",
3778 SPR_NOACCESS, SPR_NOACCESS,
3779 &spr_read_generic, &spr_write_generic,
3780 0x00000000);
3781 /* XXX : not implemented */
3782 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3783 &spr_read_generic, &spr_write_generic,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
a750fc0b 3786 /* Memory management */
f2e63a42 3787#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3788 env->nb_tlb = 64;
3789 env->nb_ways = 1;
3790 env->id_tlbs = 0;
f2e63a42 3791#endif
e1833e1f 3792 init_excp_BookE(env);
d63001d1
JM		 3793 env->dcache_line_size = 32;
3794 env->icache_line_size = 32;
a750fc0b 3795 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3796}
3797
80d11f44
JM		 3798/* Freescale 5xx cores (aka RCPU) */
3799#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3800 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3801 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3802 PPC_MFTB)
3803#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3804#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3805#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3806#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3807#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3808#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3809 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3810#define check_pow_MPC5xx check_pow_none
3811
3812__attribute__ (( unused ))
3813static void init_proc_MPC5xx (CPUPPCState *env)
3814{
3815 /* Time base */
3816 gen_tbl(env);
3817 gen_spr_5xx_8xx(env);
3818 gen_spr_5xx(env);
3819 init_excp_MPC5xx(env);
3820 env->dcache_line_size = 32;
3821 env->icache_line_size = 32;
3822 /* XXX: TODO: allocate internal IRQ controller */
3823}
3824
3825/* Freescale 8xx cores (aka PowerQUICC) */
3826#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3827 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3828 PPC_CACHE_ICBI | PPC_MFTB)
3829#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3830#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3831#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3832#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3833#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3834#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3835 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3836#define check_pow_MPC8xx check_pow_none
3837
3838__attribute__ (( unused ))
3839static void init_proc_MPC8xx (CPUPPCState *env)
3840{
3841 /* Time base */
3842 gen_tbl(env);
3843 gen_spr_5xx_8xx(env);
3844 gen_spr_8xx(env);
3845 init_excp_MPC8xx(env);
3846 env->dcache_line_size = 32;
3847 env->icache_line_size = 32;
3848 /* XXX: TODO: allocate internal IRQ controller */
3849}
3850
3851/* Freescale 82xx cores (aka PowerQUICC-II) */
3852/* PowerPC G2 */
082c6681
JM		 3853#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3854 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3855 PPC_FLOAT_STFIWX | \
3856 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3857 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3858 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3859 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3860#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3861#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3862//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3863#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3864#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3865#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3866 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3867#define check_pow_G2 check_pow_hid0
a750fc0b 3868
80d11f44 3869static void init_proc_G2 (CPUPPCState *env)
3fc6c082 3870{
80d11f44
JM		 3871 gen_spr_ne_601(env);
3872 gen_spr_G2_755(env);
3873 gen_spr_G2(env);
a750fc0b
JM		 3874 /* Time base */
3875 gen_tbl(env);
bd928eba
JM		 3876 /* External access control */
3877 /* XXX : not implemented */
3878 spr_register(env, SPR_EAR, "EAR",
3879 SPR_NOACCESS, SPR_NOACCESS,
3880 &spr_read_generic, &spr_write_generic,
3881 0x00000000);
80d11f44
JM		 3882 /* Hardware implementation register */
3883 /* XXX : not implemented */
3884 spr_register(env, SPR_HID0, "HID0",
3885 SPR_NOACCESS, SPR_NOACCESS,
3886 &spr_read_generic, &spr_write_generic,
3887 0x00000000);
3888 /* XXX : not implemented */
3889 spr_register(env, SPR_HID1, "HID1",
3890 SPR_NOACCESS, SPR_NOACCESS,
3891 &spr_read_generic, &spr_write_generic,
3892 0x00000000);
3893 /* XXX : not implemented */
3894 spr_register(env, SPR_HID2, "HID2",
3895 SPR_NOACCESS, SPR_NOACCESS,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
a750fc0b 3898 /* Memory management */
80d11f44
JM		 3899 gen_low_BATs(env);
3900 gen_high_BATs(env);
3901 gen_6xx_7xx_soft_tlb(env, 64, 2);
3902 init_excp_G2(env);
d63001d1
JM		 3903 env->dcache_line_size = 32;
3904 env->icache_line_size = 32;
80d11f44
JM		 3905 /* Allocate hardware IRQ controller */
3906 ppc6xx_irq_init(env);
3fc6c082 3907}
a750fc0b 3908
80d11f44 3909/* PowerPC G2LE */
082c6681
JM		 3910#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3911 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3912 PPC_FLOAT_STFIWX | \
3913 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3914 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3915 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3916 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 3917#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3918#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3919#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3920#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3921#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3922#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 3923 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 3924#define check_pow_G2LE check_pow_hid0
a750fc0b 3925
80d11f44 3926static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 3927{
80d11f44
JM		 3928 gen_spr_ne_601(env);
3929 gen_spr_G2_755(env);
3930 gen_spr_G2(env);
a750fc0b
JM		 3931 /* Time base */
3932 gen_tbl(env);
bd928eba
JM		 3933 /* External access control */
3934 /* XXX : not implemented */
3935 spr_register(env, SPR_EAR, "EAR",
3936 SPR_NOACCESS, SPR_NOACCESS,
3937 &spr_read_generic, &spr_write_generic,
3938 0x00000000);
80d11f44 3939 /* Hardware implementation register */
578bb252 3940 /* XXX : not implemented */
80d11f44 3941 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 3942 SPR_NOACCESS, SPR_NOACCESS,
3943 &spr_read_generic, &spr_write_generic,
3944 0x00000000);
80d11f44
JM		 3945 /* XXX : not implemented */
3946 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 3947 SPR_NOACCESS, SPR_NOACCESS,
3948 &spr_read_generic, &spr_write_generic,
3949 0x00000000);
578bb252 3950 /* XXX : not implemented */
80d11f44 3951 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 3952 SPR_NOACCESS, SPR_NOACCESS,
3953 &spr_read_generic, &spr_write_generic,
3954 0x00000000);
3955 /* Memory management */
80d11f44
JM		 3956 gen_low_BATs(env);
3957 gen_high_BATs(env);
3958 gen_6xx_7xx_soft_tlb(env, 64, 2);
3959 init_excp_G2(env);
d63001d1
JM		 3960 env->dcache_line_size = 32;
3961 env->icache_line_size = 32;
80d11f44
JM		 3962 /* Allocate hardware IRQ controller */
3963 ppc6xx_irq_init(env);
3fc6c082
FB		 3964}
3965
80d11f44
JM		 3966/* e200 core */
3967/* XXX: unimplemented instructions:
3968 * dcblc
3969 * dcbtlst
3970 * dcbtstls
3971 * icblc
3972 * icbtls
3973 * tlbivax
3974 * all SPE multiply-accumulate instructions
3975 */
082c6681 3976#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
80d11f44 3977 PPC_SPE | PPC_SPEFPU | \
082c6681
JM		 3978 PPC_WRTEE | PPC_RFDI | \
3979 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
3980 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 3981 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 3982 PPC_BOOKE)
80d11f44
JM		 3983#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3984#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3985#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3986#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3987#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3988#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 3989 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
3990 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3991#define check_pow_e200 check_pow_hid0
3992
578bb252 3993__attribute__ (( unused ))
80d11f44 3994static void init_proc_e200 (CPUPPCState *env)
3fc6c082 3995{
e1833e1f
JM		 3996 /* Time base */
3997 gen_tbl(env);
80d11f44 3998 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 3999 /* XXX : not implemented */
80d11f44 4000 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
e1833e1f
JM		 4001 SPR_NOACCESS, SPR_NOACCESS,
4002 &spr_read_generic, &spr_write_generic,
4003 0x00000000);
80d11f44
JM		 4004 /* Memory management */
4005 gen_spr_BookE_FSL(env, 0x0000005D);
4006 /* XXX : not implemented */
4007 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4008 SPR_NOACCESS, SPR_NOACCESS,
4009 &spr_read_generic, &spr_write_generic,
4010 0x00000000);
80d11f44
JM		 4011 /* XXX : not implemented */
4012 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4013 SPR_NOACCESS, SPR_NOACCESS,
4014 &spr_read_generic, &spr_write_generic,
4015 0x00000000);
578bb252 4016 /* XXX : not implemented */
80d11f44 4017 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4018 SPR_NOACCESS, SPR_NOACCESS,
4019 &spr_read_generic, &spr_write_generic,
4020 0x00000000);
578bb252 4021 /* XXX : not implemented */
80d11f44
JM		 4022 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4023 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4024 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4025 0x00000000);
4026 /* XXX : not implemented */
4027 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4028 SPR_NOACCESS, SPR_NOACCESS,
4029 &spr_read_generic, &spr_write_generic,
4030 0x00000000);
4031 /* XXX : not implemented */
4032 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4033 SPR_NOACCESS, SPR_NOACCESS,
4034 &spr_read_generic, &spr_write_generic,
4035 0x00000000);
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, &spr_write_generic,
4040 0x00000000);
4041 /* XXX : not implemented */
4042 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_generic,
4045 0x00000000);
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
4051 /* XXX : not implemented */
4052 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4053 SPR_NOACCESS, SPR_NOACCESS,
4054 &spr_read_generic, &spr_write_generic,
4055 0x00000000);
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* XXX : not implemented */
4067 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071 /* XXX : not implemented */
4072 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4073 SPR_NOACCESS, SPR_NOACCESS,
4074 &spr_read_generic, &spr_write_generic,
4075 0x00000000);
4076 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4077 SPR_NOACCESS, SPR_NOACCESS,
4078 &spr_read_generic, &spr_write_generic,
4079 0x00000000);
4080 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4081 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
f2e63a42 4084#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4085 env->nb_tlb = 64;
4086 env->nb_ways = 1;
4087 env->id_tlbs = 0;
f2e63a42 4088#endif
80d11f44 4089 init_excp_e200(env);
d63001d1
JM		 4090 env->dcache_line_size = 32;
4091 env->icache_line_size = 32;
e1833e1f 4092 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4093}
a750fc0b 4094
80d11f44 4095/* e300 core */
082c6681
JM		 4096#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4098 PPC_FLOAT_STFIWX | \
4099 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4100 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4102 PPC_SEGMENT | PPC_EXTERN)
80d11f44
JM		 4103#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4104#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4105#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4106#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4107#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4108#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4109 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4110#define check_pow_e300 check_pow_hid0
a750fc0b 4111
578bb252 4112__attribute__ (( unused ))
80d11f44 4113static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4114{
80d11f44
JM		 4115 gen_spr_ne_601(env);
4116 gen_spr_603(env);
a750fc0b
JM		 4117 /* Time base */
4118 gen_tbl(env);
80d11f44
JM		 4119 /* hardware implementation registers */
4120 /* XXX : not implemented */
4121 spr_register(env, SPR_HID0, "HID0",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
4125 /* XXX : not implemented */
4126 spr_register(env, SPR_HID1, "HID1",
4127 SPR_NOACCESS, SPR_NOACCESS,
4128 &spr_read_generic, &spr_write_generic,
4129 0x00000000);
4130 /* Memory management */
4131 gen_low_BATs(env);
4132 gen_6xx_7xx_soft_tlb(env, 64, 2);
4133 init_excp_603(env);
4134 env->dcache_line_size = 32;
4135 env->icache_line_size = 32;
4136 /* Allocate hardware IRQ controller */
4137 ppc6xx_irq_init(env);
4138}
4139
4140/* e500 core */
082c6681 4141#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
80d11f44 4142 PPC_SPE | PPC_SPEFPU | \
082c6681
JM		 4143 PPC_WRTEE | PPC_RFDI | \
4144 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4145 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4146 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4147 PPC_BOOKE)
80d11f44
JM		 4148#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
4149#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
4150#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
4151#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
4152#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
4153#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4154 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4155 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4156#define check_pow_e500 check_pow_hid0
4157
4158__attribute__ (( unused ))
4159static void init_proc_e500 (CPUPPCState *env)
4160{
4161 /* Time base */
4162 gen_tbl(env);
4163 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4164 /* Processor identification */
4165 spr_register(env, SPR_BOOKE_PIR, "PIR",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_pir,
4168 0x00000000);
4169 /* XXX : not implemented */
4170 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_generic,
4173 0x00000000);
4174 /* Memory management */
4175#if !defined(CONFIG_USER_ONLY)
4176 env->nb_pids = 3;
4177#endif
4178 gen_spr_BookE_FSL(env, 0x0000005F);
4179 /* XXX : not implemented */
4180 spr_register(env, SPR_HID0, "HID0",
4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_HID1, "HID1",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 0x00000000);
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
4194 /* XXX : not implemented */
4195 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4196 SPR_NOACCESS, SPR_NOACCESS,
4197 &spr_read_generic, &spr_write_generic,
4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4201 SPR_NOACCESS, SPR_NOACCESS,
4202 &spr_read_generic, &spr_write_generic,
4203 0x00000000);
578bb252 4204 /* XXX : not implemented */
a750fc0b
JM		 4205 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4206 SPR_NOACCESS, SPR_NOACCESS,
4207 &spr_read_generic, &spr_write_generic,
4208 0x00000000);
80d11f44
JM		 4209 /* XXX : not implemented */
4210 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
80d11f44
JM		 4214 /* XXX : not implemented */
4215 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4216 SPR_NOACCESS, SPR_NOACCESS,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
578bb252 4219 /* XXX : not implemented */
80d11f44 4220 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4221 SPR_NOACCESS, SPR_NOACCESS,
4222 &spr_read_generic, &spr_write_generic,
4223 0x00000000);
578bb252 4224 /* XXX : not implemented */
80d11f44
JM		 4225 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4226 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b 4227 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4228 0x00000000);
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
4234 /* XXX : not implemented */
4235 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_generic, &spr_write_generic,
4238 0x00000000);
4239 /* XXX : not implemented */
4240 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
4248 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4249 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
f2e63a42 4252#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4253 env->nb_tlb = 64;
4254 env->nb_ways = 1;
4255 env->id_tlbs = 0;
f2e63a42 4256#endif
80d11f44 4257 init_excp_e200(env);
d63001d1
JM		 4258 env->dcache_line_size = 32;
4259 env->icache_line_size = 32;
a750fc0b 4260 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4261}
a750fc0b 4262
a750fc0b 4263/* Non-embedded PowerPC */
a750fc0b
JM		 4264
4265/* POWER : same as 601, without mfmsr, mfsr */
4266#if defined(TODO)
4267#define POWERPC_INSNS_POWER (XXX_TODO)
4268/* POWER RSC (from RAD6000) */
4269#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4270#endif /* TODO */
4271
4272/* PowerPC 601 */
082c6681
JM		 4273#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4274 PPC_FLOAT | \
4275 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4276 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4277 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4278#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4279#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4280//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4281//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4282#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4283#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4284#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4285#define check_pow_601 check_pow_none
a750fc0b
JM		 4286
4287static void init_proc_601 (CPUPPCState *env)
3fc6c082 4288{
a750fc0b
JM		 4289 gen_spr_ne_601(env);
4290 gen_spr_601(env);
4291 /* Hardware implementation registers */
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_HID0, "HID0",
4294 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4295 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4296 0x80010080);
a750fc0b
JM		 4297 /* XXX : not implemented */
4298 spr_register(env, SPR_HID1, "HID1",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302 /* XXX : not implemented */
4303 spr_register(env, SPR_601_HID2, "HID2",
4304 SPR_NOACCESS, SPR_NOACCESS,
4305 &spr_read_generic, &spr_write_generic,
4306 0x00000000);
4307 /* XXX : not implemented */
4308 spr_register(env, SPR_601_HID5, "HID5",
4309 SPR_NOACCESS, SPR_NOACCESS,
4310 &spr_read_generic, &spr_write_generic,
4311 0x00000000);
a750fc0b 4312 /* Memory management */
e1833e1f 4313 init_excp_601(env);
082c6681
JM		 4314 /* XXX: beware that dcache line size is 64
4315 * but dcbz uses 32 bytes "sectors"
4316 * XXX: this breaks clcs instruction !
4317 */
4318 env->dcache_line_size = 32;
d63001d1 4319 env->icache_line_size = 64;
faadf50e
JM		 4320 /* Allocate hardware IRQ controller */
4321 ppc6xx_irq_init(env);
3fc6c082
FB		 4322}
4323
082c6681
JM		 4324/* PowerPC 601v */
4325#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4326 PPC_FLOAT | \
4327 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4328 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4329 PPC_SEGMENT | PPC_EXTERN)
4330#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4331#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4332#define POWERPC_MMU_601v (POWERPC_MMU_601)
4333#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4334#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4335#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4336#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4337#define check_pow_601v check_pow_none
4338
4339static void init_proc_601v (CPUPPCState *env)
4340{
4341 init_proc_601(env);
4342 /* XXX : not implemented */
4343 spr_register(env, SPR_601_HID15, "HID15",
4344 SPR_NOACCESS, SPR_NOACCESS,
4345 &spr_read_generic, &spr_write_generic,
4346 0x00000000);
4347}
4348
a750fc0b 4349/* PowerPC 602 */
082c6681
JM		 4350#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4351 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4352 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4353 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4354 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4355 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4356 PPC_SEGMENT | PPC_602_SPEC)
082c6681
JM		 4357#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4358/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4359#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4360//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4361#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4362#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4363#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4364 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4365#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4366
4367static void init_proc_602 (CPUPPCState *env)
3fc6c082 4368{
a750fc0b
JM		 4369 gen_spr_ne_601(env);
4370 gen_spr_602(env);
4371 /* Time base */
4372 gen_tbl(env);
4373 /* hardware implementation registers */
4374 /* XXX : not implemented */
4375 spr_register(env, SPR_HID0, "HID0",
4376 SPR_NOACCESS, SPR_NOACCESS,
4377 &spr_read_generic, &spr_write_generic,
4378 0x00000000);
4379 /* XXX : not implemented */
4380 spr_register(env, SPR_HID1, "HID1",
4381 SPR_NOACCESS, SPR_NOACCESS,
4382 &spr_read_generic, &spr_write_generic,
4383 0x00000000);
4384 /* Memory management */
4385 gen_low_BATs(env);
4386 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4387 init_excp_602(env);
d63001d1
JM		 4388 env->dcache_line_size = 32;
4389 env->icache_line_size = 32;
a750fc0b
JM		 4390 /* Allocate hardware IRQ controller */
4391 ppc6xx_irq_init(env);
4392}
3fc6c082 4393
a750fc0b 4394/* PowerPC 603 */
082c6681
JM		 4395#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4396 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4397 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4398 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4399 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4400 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4401 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4402#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4403#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4404//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4405#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4406#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4407#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4408 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4409#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4410
4411static void init_proc_603 (CPUPPCState *env)
4412{
4413 gen_spr_ne_601(env);
4414 gen_spr_603(env);
4415 /* Time base */
4416 gen_tbl(env);
4417 /* hardware implementation registers */
4418 /* XXX : not implemented */
4419 spr_register(env, SPR_HID0, "HID0",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423 /* XXX : not implemented */
4424 spr_register(env, SPR_HID1, "HID1",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428 /* Memory management */
4429 gen_low_BATs(env);
4430 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4431 init_excp_603(env);
d63001d1
JM		 4432 env->dcache_line_size = 32;
4433 env->icache_line_size = 32;
a750fc0b
JM		 4434 /* Allocate hardware IRQ controller */
4435 ppc6xx_irq_init(env);
3fc6c082
FB		 4436}
4437
a750fc0b 4438/* PowerPC 603e */
082c6681
JM		 4439#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4441 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4442 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4443 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4444 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4445 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4446#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4447#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4448//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4449#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4450#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4451#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4452 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4453#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4454
4455static void init_proc_603E (CPUPPCState *env)
4456{
4457 gen_spr_ne_601(env);
4458 gen_spr_603(env);
4459 /* Time base */
4460 gen_tbl(env);
4461 /* hardware implementation registers */
4462 /* XXX : not implemented */
4463 spr_register(env, SPR_HID0, "HID0",
4464 SPR_NOACCESS, SPR_NOACCESS,
4465 &spr_read_generic, &spr_write_generic,
4466 0x00000000);
4467 /* XXX : not implemented */
4468 spr_register(env, SPR_HID1, "HID1",
4469 SPR_NOACCESS, SPR_NOACCESS,
4470 &spr_read_generic, &spr_write_generic,
4471 0x00000000);
4472 /* XXX : not implemented */
4473 spr_register(env, SPR_IABR, "IABR",
4474 SPR_NOACCESS, SPR_NOACCESS,
4475 &spr_read_generic, &spr_write_generic,
4476 0x00000000);
4477 /* Memory management */
4478 gen_low_BATs(env);
4479 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4480 init_excp_603(env);
d63001d1
JM		 4481 env->dcache_line_size = 32;
4482 env->icache_line_size = 32;
a750fc0b
JM		 4483 /* Allocate hardware IRQ controller */
4484 ppc6xx_irq_init(env);
4485}
4486
a750fc0b 4487/* PowerPC 604 */
082c6681
JM		 4488#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4489 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4490 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4491 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4492 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4493 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4494 PPC_SEGMENT | PPC_EXTERN)
a750fc0b
JM		 4495#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4496#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4497//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4498#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4499#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4500#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4501 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4502#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4503
4504static void init_proc_604 (CPUPPCState *env)
4505{
4506 gen_spr_ne_601(env);
4507 gen_spr_604(env);
4508 /* Time base */
4509 gen_tbl(env);
4510 /* Hardware implementation registers */
4511 /* XXX : not implemented */
082c6681
JM		 4512 spr_register(env, SPR_HID0, "HID0",
4513 SPR_NOACCESS, SPR_NOACCESS,
4514 &spr_read_generic, &spr_write_generic,
4515 0x00000000);
4516 /* Memory management */
4517 gen_low_BATs(env);
4518 init_excp_604(env);
4519 env->dcache_line_size = 32;
4520 env->icache_line_size = 32;
4521 /* Allocate hardware IRQ controller */
4522 ppc6xx_irq_init(env);
4523}
4524
4525/* PowerPC 604E */
4526#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4527 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4528 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4529 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4530 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4531 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4532 PPC_SEGMENT | PPC_EXTERN)
4533#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4534#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4535#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4536#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4537#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4538#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4539 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4540#define check_pow_604E check_pow_nocheck
4541
4542static void init_proc_604E (CPUPPCState *env)
4543{
4544 gen_spr_ne_601(env);
4545 gen_spr_604(env);
4546 /* XXX : not implemented */
4547 spr_register(env, SPR_MMCR1, "MMCR1",
4548 SPR_NOACCESS, SPR_NOACCESS,
4549 &spr_read_generic, &spr_write_generic,
4550 0x00000000);
4551 /* XXX : not implemented */
4552 spr_register(env, SPR_PMC3, "PMC3",
4553 SPR_NOACCESS, SPR_NOACCESS,
4554 &spr_read_generic, &spr_write_generic,
4555 0x00000000);
4556 /* XXX : not implemented */
4557 spr_register(env, SPR_PMC4, "PMC4",
4558 SPR_NOACCESS, SPR_NOACCESS,
4559 &spr_read_generic, &spr_write_generic,
4560 0x00000000);
4561 /* Time base */
4562 gen_tbl(env);
4563 /* Hardware implementation registers */
4564 /* XXX : not implemented */
a750fc0b
JM		 4565 spr_register(env, SPR_HID0, "HID0",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_generic,
4568 0x00000000);
4569 /* XXX : not implemented */
4570 spr_register(env, SPR_HID1, "HID1",
4571 SPR_NOACCESS, SPR_NOACCESS,
4572 &spr_read_generic, &spr_write_generic,
4573 0x00000000);
4574 /* Memory management */
4575 gen_low_BATs(env);
e1833e1f 4576 init_excp_604(env);
d63001d1
JM		 4577 env->dcache_line_size = 32;
4578 env->icache_line_size = 32;
a750fc0b
JM		 4579 /* Allocate hardware IRQ controller */
4580 ppc6xx_irq_init(env);
4581}
4582
bd928eba
JM		 4583/* PowerPC 740 */
4584#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4585 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4586 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4587 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4588 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4589 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4590 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 4591#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4592#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4593#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4594#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4595#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4596#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4597 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4598#define check_pow_740 check_pow_hid0
a750fc0b 4599
bd928eba 4600static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4601{
4602 gen_spr_ne_601(env);
4603 gen_spr_7xx(env);
4604 /* Time base */
4605 gen_tbl(env);
4606 /* Thermal management */
4607 gen_spr_thrm(env);
4608 /* Hardware implementation registers */
4609 /* XXX : not implemented */
4610 spr_register(env, SPR_HID0, "HID0",
4611 SPR_NOACCESS, SPR_NOACCESS,
4612 &spr_read_generic, &spr_write_generic,
4613 0x00000000);
4614 /* XXX : not implemented */
4615 spr_register(env, SPR_HID1, "HID1",
4616 SPR_NOACCESS, SPR_NOACCESS,
4617 &spr_read_generic, &spr_write_generic,
4618 0x00000000);
4619 /* Memory management */
4620 gen_low_BATs(env);
e1833e1f 4621 init_excp_7x0(env);
d63001d1
JM		 4622 env->dcache_line_size = 32;
4623 env->icache_line_size = 32;
a750fc0b
JM		 4624 /* Allocate hardware IRQ controller */
4625 ppc6xx_irq_init(env);
4626}
4627
bd928eba
JM		 4628/* PowerPC 750 */
4629#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4630 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4631 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4632 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4633 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4634 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4635 PPC_SEGMENT | PPC_EXTERN)
4636#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4637#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4638#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4639#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4640#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4641#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4642 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4643#define check_pow_750 check_pow_hid0
4644
4645static void init_proc_750 (CPUPPCState *env)
4646{
4647 gen_spr_ne_601(env);
4648 gen_spr_7xx(env);
4649 /* XXX : not implemented */
4650 spr_register(env, SPR_L2CR, "L2CR",
4651 SPR_NOACCESS, SPR_NOACCESS,
4652 &spr_read_generic, &spr_write_generic,
4653 0x00000000);
4654 /* Time base */
4655 gen_tbl(env);
4656 /* Thermal management */
4657 gen_spr_thrm(env);
4658 /* Hardware implementation registers */
4659 /* XXX : not implemented */
4660 spr_register(env, SPR_HID0, "HID0",
4661 SPR_NOACCESS, SPR_NOACCESS,
4662 &spr_read_generic, &spr_write_generic,
4663 0x00000000);
4664 /* XXX : not implemented */
4665 spr_register(env, SPR_HID1, "HID1",
4666 SPR_NOACCESS, SPR_NOACCESS,
4667 &spr_read_generic, &spr_write_generic,
4668 0x00000000);
4669 /* Memory management */
4670 gen_low_BATs(env);
4671 /* XXX: high BATs are also present but are known to be bugged on
4672 * die version 1.x
4673 */
4674 init_excp_7x0(env);
4675 env->dcache_line_size = 32;
4676 env->icache_line_size = 32;
4677 /* Allocate hardware IRQ controller */
4678 ppc6xx_irq_init(env);
4679}
4680
4681/* PowerPC 750 CL */
4682/* XXX: not implemented:
4683 * cache lock instructions:
4684 * dcbz_l
4685 * floating point paired instructions
4686 * psq_lux
4687 * psq_lx
4688 * psq_stux
4689 * psq_stx
4690 * ps_abs
4691 * ps_add
4692 * ps_cmpo0
4693 * ps_cmpo1
4694 * ps_cmpu0
4695 * ps_cmpu1
4696 * ps_div
4697 * ps_madd
4698 * ps_madds0
4699 * ps_madds1
4700 * ps_merge00
4701 * ps_merge01
4702 * ps_merge10
4703 * ps_merge11
4704 * ps_mr
4705 * ps_msub
4706 * ps_mul
4707 * ps_muls0
4708 * ps_muls1
4709 * ps_nabs
4710 * ps_neg
4711 * ps_nmadd
4712 * ps_nmsub
4713 * ps_res
4714 * ps_rsqrte
4715 * ps_sel
4716 * ps_sub
4717 * ps_sum0
4718 * ps_sum1
4719 */
4720#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4721 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4722 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4723 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4724 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4725 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4726 PPC_SEGMENT | PPC_EXTERN)
4727#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4728#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4729#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4730#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4731#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4732#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4733 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4734#define check_pow_750cl check_pow_hid0
4735
4736static void init_proc_750cl (CPUPPCState *env)
4737{
4738 gen_spr_ne_601(env);
4739 gen_spr_7xx(env);
4740 /* XXX : not implemented */
4741 spr_register(env, SPR_L2CR, "L2CR",
4742 SPR_NOACCESS, SPR_NOACCESS,
4743 &spr_read_generic, &spr_write_generic,
4744 0x00000000);
4745 /* Time base */
4746 gen_tbl(env);
4747 /* Thermal management */
4748 /* Those registers are fake on 750CL */
4749 spr_register(env, SPR_THRM1, "THRM1",
4750 SPR_NOACCESS, SPR_NOACCESS,
4751 &spr_read_generic, &spr_write_generic,
4752 0x00000000);
4753 spr_register(env, SPR_THRM2, "THRM2",
4754 SPR_NOACCESS, SPR_NOACCESS,
4755 &spr_read_generic, &spr_write_generic,
4756 0x00000000);
4757 spr_register(env, SPR_THRM3, "THRM3",
4758 SPR_NOACCESS, SPR_NOACCESS,
4759 &spr_read_generic, &spr_write_generic,
4760 0x00000000);
4761 /* XXX: not implemented */
4762 spr_register(env, SPR_750_TDCL, "TDCL",
4763 SPR_NOACCESS, SPR_NOACCESS,
4764 &spr_read_generic, &spr_write_generic,
4765 0x00000000);
4766 spr_register(env, SPR_750_TDCH, "TDCH",
4767 SPR_NOACCESS, SPR_NOACCESS,
4768 &spr_read_generic, &spr_write_generic,
4769 0x00000000);
4770 /* DMA */
4771 /* XXX : not implemented */
4772 spr_register(env, SPR_750_WPAR, "WPAR",
4773 SPR_NOACCESS, SPR_NOACCESS,
4774 &spr_read_generic, &spr_write_generic,
4775 0x00000000);
4776 spr_register(env, SPR_750_DMAL, "DMAL",
4777 SPR_NOACCESS, SPR_NOACCESS,
4778 &spr_read_generic, &spr_write_generic,
4779 0x00000000);
4780 spr_register(env, SPR_750_DMAU, "DMAU",
4781 SPR_NOACCESS, SPR_NOACCESS,
4782 &spr_read_generic, &spr_write_generic,
4783 0x00000000);
4784 /* Hardware implementation registers */
4785 /* XXX : not implemented */
4786 spr_register(env, SPR_HID0, "HID0",
4787 SPR_NOACCESS, SPR_NOACCESS,
4788 &spr_read_generic, &spr_write_generic,
4789 0x00000000);
4790 /* XXX : not implemented */
4791 spr_register(env, SPR_HID1, "HID1",
4792 SPR_NOACCESS, SPR_NOACCESS,
4793 &spr_read_generic, &spr_write_generic,
4794 0x00000000);
4795 /* XXX : not implemented */
4796 spr_register(env, SPR_750CL_HID2, "HID2",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800 /* XXX : not implemented */
4801 spr_register(env, SPR_750CL_HID4, "HID4",
4802 SPR_NOACCESS, SPR_NOACCESS,
4803 &spr_read_generic, &spr_write_generic,
4804 0x00000000);
4805 /* Quantization registers */
4806 /* XXX : not implemented */
4807 spr_register(env, SPR_750_GQR0, "GQR0",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 /* XXX : not implemented */
4812 spr_register(env, SPR_750_GQR1, "GQR1",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* XXX : not implemented */
4817 spr_register(env, SPR_750_GQR2, "GQR2",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* XXX : not implemented */
4822 spr_register(env, SPR_750_GQR3, "GQR3",
4823 SPR_NOACCESS, SPR_NOACCESS,
4824 &spr_read_generic, &spr_write_generic,
4825 0x00000000);
4826 /* XXX : not implemented */
4827 spr_register(env, SPR_750_GQR4, "GQR4",
4828 SPR_NOACCESS, SPR_NOACCESS,
4829 &spr_read_generic, &spr_write_generic,
4830 0x00000000);
4831 /* XXX : not implemented */
4832 spr_register(env, SPR_750_GQR5, "GQR5",
4833 SPR_NOACCESS, SPR_NOACCESS,
4834 &spr_read_generic, &spr_write_generic,
4835 0x00000000);
4836 /* XXX : not implemented */
4837 spr_register(env, SPR_750_GQR6, "GQR6",
4838 SPR_NOACCESS, SPR_NOACCESS,
4839 &spr_read_generic, &spr_write_generic,
4840 0x00000000);
4841 /* XXX : not implemented */
4842 spr_register(env, SPR_750_GQR7, "GQR7",
4843 SPR_NOACCESS, SPR_NOACCESS,
4844 &spr_read_generic, &spr_write_generic,
4845 0x00000000);
4846 /* Memory management */
4847 gen_low_BATs(env);
4848 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4849 gen_high_BATs(env);
4850 init_excp_750cl(env);
4851 env->dcache_line_size = 32;
4852 env->icache_line_size = 32;
4853 /* Allocate hardware IRQ controller */
4854 ppc6xx_irq_init(env);
4855}
4856
4e777442 4857/* PowerPC 750CX */
bd928eba
JM		 4858#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4859 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4860 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4861 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4862 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4863 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4864 PPC_SEGMENT | PPC_EXTERN)
4865#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4866#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4867#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4868#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4869#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4870#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4871 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4872#define check_pow_750cx check_pow_hid0
4873
4874static void init_proc_750cx (CPUPPCState *env)
4875{
4876 gen_spr_ne_601(env);
4877 gen_spr_7xx(env);
4878 /* XXX : not implemented */
4879 spr_register(env, SPR_L2CR, "L2CR",
4880 SPR_NOACCESS, SPR_NOACCESS,
4881 &spr_read_generic, &spr_write_generic,
4882 0x00000000);
4883 /* Time base */
4884 gen_tbl(env);
4885 /* Thermal management */
4886 gen_spr_thrm(env);
4887 /* This register is not implemented but is present for compatibility */
4888 spr_register(env, SPR_SDA, "SDA",
4889 SPR_NOACCESS, SPR_NOACCESS,
4890 &spr_read_generic, &spr_write_generic,
4891 0x00000000);
4892 /* Hardware implementation registers */
4893 /* XXX : not implemented */
4894 spr_register(env, SPR_HID0, "HID0",
4895 SPR_NOACCESS, SPR_NOACCESS,
4896 &spr_read_generic, &spr_write_generic,
4897 0x00000000);
4898 /* XXX : not implemented */
4899 spr_register(env, SPR_HID1, "HID1",
4900 SPR_NOACCESS, SPR_NOACCESS,
4901 &spr_read_generic, &spr_write_generic,
4902 0x00000000);
4903 /* Memory management */
4904 gen_low_BATs(env);
4e777442
JM		 4905 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4906 gen_high_BATs(env);
bd928eba
JM		 4907 init_excp_750cx(env);
4908 env->dcache_line_size = 32;
4909 env->icache_line_size = 32;
4910 /* Allocate hardware IRQ controller */
4911 ppc6xx_irq_init(env);
4912}
4913
4914/* PowerPC 750FX */
082c6681
JM		 4915#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4916 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4917 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4918 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4919 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4920 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4921 PPC_SEGMENT | PPC_EXTERN)
25ba3a68 4922#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 4923#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4924#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4925#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 4926#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 4927#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4928 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4929#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 4930
4931static void init_proc_750fx (CPUPPCState *env)
4932{
4933 gen_spr_ne_601(env);
4934 gen_spr_7xx(env);
bd928eba
JM		 4935 /* XXX : not implemented */
4936 spr_register(env, SPR_L2CR, "L2CR",
4937 SPR_NOACCESS, SPR_NOACCESS,
4938 &spr_read_generic, &spr_write_generic,
4939 0x00000000);
a750fc0b
JM		 4940 /* Time base */
4941 gen_tbl(env);
4942 /* Thermal management */
4943 gen_spr_thrm(env);
bd928eba
JM		 4944 /* XXX : not implemented */
4945 spr_register(env, SPR_750_THRM4, "THRM4",
4946 SPR_NOACCESS, SPR_NOACCESS,
4947 &spr_read_generic, &spr_write_generic,
4948 0x00000000);
a750fc0b
JM		 4949 /* Hardware implementation registers */
4950 /* XXX : not implemented */
4951 spr_register(env, SPR_HID0, "HID0",
4952 SPR_NOACCESS, SPR_NOACCESS,
4953 &spr_read_generic, &spr_write_generic,
4954 0x00000000);
4955 /* XXX : not implemented */
4956 spr_register(env, SPR_HID1, "HID1",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_generic,
4959 0x00000000);
4960 /* XXX : not implemented */
bd928eba 4961 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 4962 SPR_NOACCESS, SPR_NOACCESS,
4963 &spr_read_generic, &spr_write_generic,
4964 0x00000000);
4965 /* Memory management */
4966 gen_low_BATs(env);
4967 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4968 gen_high_BATs(env);
bd928eba 4969 init_excp_7x0(env);
d63001d1
JM		 4970 env->dcache_line_size = 32;
4971 env->icache_line_size = 32;
a750fc0b
JM		 4972 /* Allocate hardware IRQ controller */
4973 ppc6xx_irq_init(env);
4974}
4975
bd928eba
JM		 4976/* PowerPC 750GX */
4977#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4978 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 4979 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4980 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4981 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4982 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4983 PPC_SEGMENT | PPC_EXTERN)
4984#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
4985#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
4986#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
4987#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
4988#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
4989#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4990 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4991#define check_pow_750gx check_pow_hid0
4992
4993static void init_proc_750gx (CPUPPCState *env)
4994{
4995 gen_spr_ne_601(env);
4996 gen_spr_7xx(env);
4997 /* XXX : not implemented (XXX: different from 750fx) */
4998 spr_register(env, SPR_L2CR, "L2CR",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 /* Time base */
5003 gen_tbl(env);
5004 /* Thermal management */
5005 gen_spr_thrm(env);
5006 /* XXX : not implemented */
5007 spr_register(env, SPR_750_THRM4, "THRM4",
5008 SPR_NOACCESS, SPR_NOACCESS,
5009 &spr_read_generic, &spr_write_generic,
5010 0x00000000);
5011 /* Hardware implementation registers */
5012 /* XXX : not implemented (XXX: different from 750fx) */
5013 spr_register(env, SPR_HID0, "HID0",
5014 SPR_NOACCESS, SPR_NOACCESS,
5015 &spr_read_generic, &spr_write_generic,
5016 0x00000000);
5017 /* XXX : not implemented */
5018 spr_register(env, SPR_HID1, "HID1",
5019 SPR_NOACCESS, SPR_NOACCESS,
5020 &spr_read_generic, &spr_write_generic,
5021 0x00000000);
5022 /* XXX : not implemented (XXX: different from 750fx) */
5023 spr_register(env, SPR_750FX_HID2, "HID2",
5024 SPR_NOACCESS, SPR_NOACCESS,
5025 &spr_read_generic, &spr_write_generic,
5026 0x00000000);
5027 /* Memory management */
5028 gen_low_BATs(env);
5029 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5030 gen_high_BATs(env);
5031 init_excp_7x0(env);
5032 env->dcache_line_size = 32;
5033 env->icache_line_size = 32;
5034 /* Allocate hardware IRQ controller */
5035 ppc6xx_irq_init(env);
5036}
5037
5038/* PowerPC 745 */
5039#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5040 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5041 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5042 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5043 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5044 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5045 PPC_SEGMENT | PPC_EXTERN)
5046#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5047#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5048#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5049#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5050#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5051#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5052 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5053#define check_pow_745 check_pow_hid0
5054
5055static void init_proc_745 (CPUPPCState *env)
5056{
5057 gen_spr_ne_601(env);
5058 gen_spr_7xx(env);
5059 gen_spr_G2_755(env);
5060 /* Time base */
5061 gen_tbl(env);
5062 /* Thermal management */
5063 gen_spr_thrm(env);
5064 /* Hardware implementation registers */
5065 /* XXX : not implemented */
5066 spr_register(env, SPR_HID0, "HID0",
5067 SPR_NOACCESS, SPR_NOACCESS,
5068 &spr_read_generic, &spr_write_generic,
5069 0x00000000);
5070 /* XXX : not implemented */
5071 spr_register(env, SPR_HID1, "HID1",
5072 SPR_NOACCESS, SPR_NOACCESS,
5073 &spr_read_generic, &spr_write_generic,
5074 0x00000000);
5075 /* XXX : not implemented */
5076 spr_register(env, SPR_HID2, "HID2",
5077 SPR_NOACCESS, SPR_NOACCESS,
5078 &spr_read_generic, &spr_write_generic,
5079 0x00000000);
5080 /* Memory management */
5081 gen_low_BATs(env);
5082 gen_high_BATs(env);
5083 gen_6xx_7xx_soft_tlb(env, 64, 2);
5084 init_excp_7x5(env);
5085 env->dcache_line_size = 32;
5086 env->icache_line_size = 32;
5087 /* Allocate hardware IRQ controller */
5088 ppc6xx_irq_init(env);
5089}
5090
5091/* PowerPC 755 */
5092#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5093 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5094 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5095 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5096 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5097 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5098 PPC_SEGMENT | PPC_EXTERN)
bd928eba
JM		 5099#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5100#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5101#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5102#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5103#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5104#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5105 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5106#define check_pow_755 check_pow_hid0
a750fc0b 5107
bd928eba 5108static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5109{
5110 gen_spr_ne_601(env);
bd928eba 5111 gen_spr_7xx(env);
a750fc0b
JM		 5112 gen_spr_G2_755(env);
5113 /* Time base */
5114 gen_tbl(env);
5115 /* L2 cache control */
5116 /* XXX : not implemented */
bd928eba 5117 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 0x00000000);
5121 /* XXX : not implemented */
5122 spr_register(env, SPR_L2PMCR, "L2PMCR",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 &spr_read_generic, &spr_write_generic,
5125 0x00000000);
bd928eba
JM		 5126 /* Thermal management */
5127 gen_spr_thrm(env);
a750fc0b
JM		 5128 /* Hardware implementation registers */
5129 /* XXX : not implemented */
5130 spr_register(env, SPR_HID0, "HID0",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, &spr_write_generic,
5133 0x00000000);
5134 /* XXX : not implemented */
5135 spr_register(env, SPR_HID1, "HID1",
5136 SPR_NOACCESS, SPR_NOACCESS,
5137 &spr_read_generic, &spr_write_generic,
5138 0x00000000);
5139 /* XXX : not implemented */
5140 spr_register(env, SPR_HID2, "HID2",
5141 SPR_NOACCESS, SPR_NOACCESS,
5142 &spr_read_generic, &spr_write_generic,
5143 0x00000000);
5144 /* Memory management */
5145 gen_low_BATs(env);
5146 gen_high_BATs(env);
5147 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5148 init_excp_7x5(env);
d63001d1
JM		 5149 env->dcache_line_size = 32;
5150 env->icache_line_size = 32;
a750fc0b
JM		 5151 /* Allocate hardware IRQ controller */
5152 ppc6xx_irq_init(env);
5153}
5154
5155/* PowerPC 7400 (aka G4) */
082c6681
JM		 5156#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5157 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5158 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5159 PPC_FLOAT_STFIWX | \
5160 PPC_CACHE | PPC_CACHE_ICBI | \
5161 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5162 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5163 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5164 PPC_MEM_TLBIA | \
5165 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5166 PPC_ALTIVEC)
5167#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5168#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5169#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5170#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5171#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5172#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5173 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5174 POWERPC_FLAG_BUS_CLK)
4e777442 5175#define check_pow_7400 check_pow_hid0_74xx
a750fc0b
JM		 5176
5177static void init_proc_7400 (CPUPPCState *env)
5178{
5179 gen_spr_ne_601(env);
5180 gen_spr_7xx(env);
5181 /* Time base */
5182 gen_tbl(env);
5183 /* 74xx specific SPR */
5184 gen_spr_74xx(env);
4e777442
JM		 5185 /* XXX : not implemented */
5186 spr_register(env, SPR_UBAMR, "UBAMR",
5187 &spr_read_ureg, SPR_NOACCESS,
5188 &spr_read_ureg, SPR_NOACCESS,
5189 0x00000000);
5190 /* XXX: this seems not implemented on all revisions. */
5191 /* XXX : not implemented */
5192 spr_register(env, SPR_MSSCR1, "MSSCR1",
5193 SPR_NOACCESS, SPR_NOACCESS,
5194 &spr_read_generic, &spr_write_generic,
5195 0x00000000);
a750fc0b
JM		 5196 /* Thermal management */
5197 gen_spr_thrm(env);
5198 /* Memory management */
5199 gen_low_BATs(env);
e1833e1f 5200 init_excp_7400(env);
d63001d1
JM		 5201 env->dcache_line_size = 32;
5202 env->icache_line_size = 32;
a750fc0b
JM		 5203 /* Allocate hardware IRQ controller */
5204 ppc6xx_irq_init(env);
5205}
5206
5207/* PowerPC 7410 (aka G4) */
082c6681
JM		 5208#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5209 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5210 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5211 PPC_FLOAT_STFIWX | \
5212 PPC_CACHE | PPC_CACHE_ICBI | \
5213 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5214 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5215 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5216 PPC_MEM_TLBIA | \
5217 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5218 PPC_ALTIVEC)
5219#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5220#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5221#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5222#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5223#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5224#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5225 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5226 POWERPC_FLAG_BUS_CLK)
4e777442 5227#define check_pow_7410 check_pow_hid0_74xx
a750fc0b
JM		 5228
5229static void init_proc_7410 (CPUPPCState *env)
5230{
5231 gen_spr_ne_601(env);
5232 gen_spr_7xx(env);
5233 /* Time base */
5234 gen_tbl(env);
5235 /* 74xx specific SPR */
5236 gen_spr_74xx(env);
4e777442
JM		 5237 /* XXX : not implemented */
5238 spr_register(env, SPR_UBAMR, "UBAMR",
5239 &spr_read_ureg, SPR_NOACCESS,
5240 &spr_read_ureg, SPR_NOACCESS,
5241 0x00000000);
a750fc0b
JM		 5242 /* Thermal management */
5243 gen_spr_thrm(env);
5244 /* L2PMCR */
5245 /* XXX : not implemented */
5246 spr_register(env, SPR_L2PMCR, "L2PMCR",
5247 SPR_NOACCESS, SPR_NOACCESS,
5248 &spr_read_generic, &spr_write_generic,
5249 0x00000000);
5250 /* LDSTDB */
5251 /* XXX : not implemented */
5252 spr_register(env, SPR_LDSTDB, "LDSTDB",
5253 SPR_NOACCESS, SPR_NOACCESS,
5254 &spr_read_generic, &spr_write_generic,
5255 0x00000000);
5256 /* Memory management */
5257 gen_low_BATs(env);
e1833e1f 5258 init_excp_7400(env);
d63001d1
JM		 5259 env->dcache_line_size = 32;
5260 env->icache_line_size = 32;
a750fc0b
JM		 5261 /* Allocate hardware IRQ controller */
5262 ppc6xx_irq_init(env);
5263}
5264
5265/* PowerPC 7440 (aka G4) */
082c6681
JM		 5266#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5267 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5268 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5269 PPC_FLOAT_STFIWX | \
5270 PPC_CACHE | PPC_CACHE_ICBI | \
5271 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5272 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5273 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5274 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5275 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5276 PPC_ALTIVEC)
5277#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5278#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5279#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5280#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5281#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5282#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5283 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5284 POWERPC_FLAG_BUS_CLK)
4e777442 5285#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5286
578bb252 5287__attribute__ (( unused ))
a750fc0b
JM		 5288static void init_proc_7440 (CPUPPCState *env)
5289{
5290 gen_spr_ne_601(env);
5291 gen_spr_7xx(env);
5292 /* Time base */
5293 gen_tbl(env);
5294 /* 74xx specific SPR */
5295 gen_spr_74xx(env);
4e777442
JM		 5296 /* XXX : not implemented */
5297 spr_register(env, SPR_UBAMR, "UBAMR",
5298 &spr_read_ureg, SPR_NOACCESS,
5299 &spr_read_ureg, SPR_NOACCESS,
5300 0x00000000);
a750fc0b
JM		 5301 /* LDSTCR */
5302 /* XXX : not implemented */
5303 spr_register(env, SPR_LDSTCR, "LDSTCR",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 /* ICTRL */
5308 /* XXX : not implemented */
5309 spr_register(env, SPR_ICTRL, "ICTRL",
5310 SPR_NOACCESS, SPR_NOACCESS,
5311 &spr_read_generic, &spr_write_generic,
5312 0x00000000);
5313 /* MSSSR0 */
578bb252 5314 /* XXX : not implemented */
a750fc0b
JM		 5315 spr_register(env, SPR_MSSSR0, "MSSSR0",
5316 SPR_NOACCESS, SPR_NOACCESS,
5317 &spr_read_generic, &spr_write_generic,
5318 0x00000000);
5319 /* PMC */
5320 /* XXX : not implemented */
5321 spr_register(env, SPR_PMC5, "PMC5",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
5324 0x00000000);
578bb252 5325 /* XXX : not implemented */
a750fc0b
JM		 5326 spr_register(env, SPR_UPMC5, "UPMC5",
5327 &spr_read_ureg, SPR_NOACCESS,
5328 &spr_read_ureg, SPR_NOACCESS,
5329 0x00000000);
578bb252 5330 /* XXX : not implemented */
a750fc0b
JM		 5331 spr_register(env, SPR_PMC6, "PMC6",
5332 SPR_NOACCESS, SPR_NOACCESS,
5333 &spr_read_generic, &spr_write_generic,
5334 0x00000000);
578bb252 5335 /* XXX : not implemented */
a750fc0b
JM		 5336 spr_register(env, SPR_UPMC6, "UPMC6",
5337 &spr_read_ureg, SPR_NOACCESS,
5338 &spr_read_ureg, SPR_NOACCESS,
5339 0x00000000);
5340 /* Memory management */
5341 gen_low_BATs(env);
578bb252 5342 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5343 init_excp_7450(env);
d63001d1
JM		 5344 env->dcache_line_size = 32;
5345 env->icache_line_size = 32;
a750fc0b
JM		 5346 /* Allocate hardware IRQ controller */
5347 ppc6xx_irq_init(env);
5348}
a750fc0b
JM		 5349
5350/* PowerPC 7450 (aka G4) */
082c6681
JM		 5351#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5352 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5353 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5354 PPC_FLOAT_STFIWX | \
5355 PPC_CACHE | PPC_CACHE_ICBI | \
5356 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5357 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5358 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5359 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5360 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5361 PPC_ALTIVEC)
5362#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5363#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5364#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5365#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5366#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5367#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5368 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5369 POWERPC_FLAG_BUS_CLK)
4e777442 5370#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5371
578bb252 5372__attribute__ (( unused ))
a750fc0b
JM		 5373static void init_proc_7450 (CPUPPCState *env)
5374{
5375 gen_spr_ne_601(env);
5376 gen_spr_7xx(env);
5377 /* Time base */
5378 gen_tbl(env);
5379 /* 74xx specific SPR */
5380 gen_spr_74xx(env);
5381 /* Level 3 cache control */
5382 gen_l3_ctrl(env);
4e777442
JM		 5383 /* L3ITCR1 */
5384 /* XXX : not implemented */
5385 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5386 SPR_NOACCESS, SPR_NOACCESS,
5387 &spr_read_generic, &spr_write_generic,
5388 0x00000000);
5389 /* L3ITCR2 */
5390 /* XXX : not implemented */
5391 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5392 SPR_NOACCESS, SPR_NOACCESS,
5393 &spr_read_generic, &spr_write_generic,
5394 0x00000000);
5395 /* L3ITCR3 */
5396 /* XXX : not implemented */
5397 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 &spr_read_generic, &spr_write_generic,
5400 0x00000000);
5401 /* L3OHCR */
5402 /* XXX : not implemented */
5403 spr_register(env, SPR_L3OHCR, "L3OHCR",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 /* XXX : not implemented */
5408 spr_register(env, SPR_UBAMR, "UBAMR",
5409 &spr_read_ureg, SPR_NOACCESS,
5410 &spr_read_ureg, SPR_NOACCESS,
5411 0x00000000);
a750fc0b
JM		 5412 /* LDSTCR */
5413 /* XXX : not implemented */
5414 spr_register(env, SPR_LDSTCR, "LDSTCR",
5415 SPR_NOACCESS, SPR_NOACCESS,
5416 &spr_read_generic, &spr_write_generic,
5417 0x00000000);
5418 /* ICTRL */
5419 /* XXX : not implemented */
5420 spr_register(env, SPR_ICTRL, "ICTRL",
5421 SPR_NOACCESS, SPR_NOACCESS,
5422 &spr_read_generic, &spr_write_generic,
5423 0x00000000);
5424 /* MSSSR0 */
578bb252 5425 /* XXX : not implemented */
a750fc0b
JM		 5426 spr_register(env, SPR_MSSSR0, "MSSSR0",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 /* PMC */
5431 /* XXX : not implemented */
5432 spr_register(env, SPR_PMC5, "PMC5",
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 &spr_read_generic, &spr_write_generic,
5435 0x00000000);
578bb252 5436 /* XXX : not implemented */
a750fc0b
JM		 5437 spr_register(env, SPR_UPMC5, "UPMC5",
5438 &spr_read_ureg, SPR_NOACCESS,
5439 &spr_read_ureg, SPR_NOACCESS,
5440 0x00000000);
578bb252 5441 /* XXX : not implemented */
a750fc0b
JM		 5442 spr_register(env, SPR_PMC6, "PMC6",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
578bb252 5446 /* XXX : not implemented */
a750fc0b
JM		 5447 spr_register(env, SPR_UPMC6, "UPMC6",
5448 &spr_read_ureg, SPR_NOACCESS,
5449 &spr_read_ureg, SPR_NOACCESS,
5450 0x00000000);
5451 /* Memory management */
5452 gen_low_BATs(env);
578bb252 5453 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5454 init_excp_7450(env);
d63001d1
JM		 5455 env->dcache_line_size = 32;
5456 env->icache_line_size = 32;
a750fc0b
JM		 5457 /* Allocate hardware IRQ controller */
5458 ppc6xx_irq_init(env);
5459}
a750fc0b
JM		 5460
5461/* PowerPC 7445 (aka G4) */
082c6681
JM		 5462#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5464 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5465 PPC_FLOAT_STFIWX | \
5466 PPC_CACHE | PPC_CACHE_ICBI | \
5467 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5468 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5469 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5470 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5471 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5472 PPC_ALTIVEC)
5473#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5474#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5475#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5476#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5477#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5478#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5479 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5480 POWERPC_FLAG_BUS_CLK)
4e777442 5481#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5482
578bb252 5483__attribute__ (( unused ))
a750fc0b
JM		 5484static void init_proc_7445 (CPUPPCState *env)
5485{
5486 gen_spr_ne_601(env);
5487 gen_spr_7xx(env);
5488 /* Time base */
5489 gen_tbl(env);
5490 /* 74xx specific SPR */
5491 gen_spr_74xx(env);
5492 /* LDSTCR */
5493 /* XXX : not implemented */
5494 spr_register(env, SPR_LDSTCR, "LDSTCR",
5495 SPR_NOACCESS, SPR_NOACCESS,
5496 &spr_read_generic, &spr_write_generic,
5497 0x00000000);
5498 /* ICTRL */
5499 /* XXX : not implemented */
5500 spr_register(env, SPR_ICTRL, "ICTRL",
5501 SPR_NOACCESS, SPR_NOACCESS,
5502 &spr_read_generic, &spr_write_generic,
5503 0x00000000);
5504 /* MSSSR0 */
578bb252 5505 /* XXX : not implemented */
a750fc0b
JM		 5506 spr_register(env, SPR_MSSSR0, "MSSSR0",
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 0x00000000);
5510 /* PMC */
5511 /* XXX : not implemented */
5512 spr_register(env, SPR_PMC5, "PMC5",
5513 SPR_NOACCESS, SPR_NOACCESS,
5514 &spr_read_generic, &spr_write_generic,
5515 0x00000000);
578bb252 5516 /* XXX : not implemented */
a750fc0b
JM		 5517 spr_register(env, SPR_UPMC5, "UPMC5",
5518 &spr_read_ureg, SPR_NOACCESS,
5519 &spr_read_ureg, SPR_NOACCESS,
5520 0x00000000);
578bb252 5521 /* XXX : not implemented */
a750fc0b
JM		 5522 spr_register(env, SPR_PMC6, "PMC6",
5523 SPR_NOACCESS, SPR_NOACCESS,
5524 &spr_read_generic, &spr_write_generic,
5525 0x00000000);
578bb252 5526 /* XXX : not implemented */
a750fc0b
JM		 5527 spr_register(env, SPR_UPMC6, "UPMC6",
5528 &spr_read_ureg, SPR_NOACCESS,
5529 &spr_read_ureg, SPR_NOACCESS,
5530 0x00000000);
5531 /* SPRGs */
5532 spr_register(env, SPR_SPRG4, "SPRG4",
5533 SPR_NOACCESS, SPR_NOACCESS,
5534 &spr_read_generic, &spr_write_generic,
5535 0x00000000);
5536 spr_register(env, SPR_USPRG4, "USPRG4",
5537 &spr_read_ureg, SPR_NOACCESS,
5538 &spr_read_ureg, SPR_NOACCESS,
5539 0x00000000);
5540 spr_register(env, SPR_SPRG5, "SPRG5",
5541 SPR_NOACCESS, SPR_NOACCESS,
5542 &spr_read_generic, &spr_write_generic,
5543 0x00000000);
5544 spr_register(env, SPR_USPRG5, "USPRG5",
5545 &spr_read_ureg, SPR_NOACCESS,
5546 &spr_read_ureg, SPR_NOACCESS,
5547 0x00000000);
5548 spr_register(env, SPR_SPRG6, "SPRG6",
5549 SPR_NOACCESS, SPR_NOACCESS,
5550 &spr_read_generic, &spr_write_generic,
5551 0x00000000);
5552 spr_register(env, SPR_USPRG6, "USPRG6",
5553 &spr_read_ureg, SPR_NOACCESS,
5554 &spr_read_ureg, SPR_NOACCESS,
5555 0x00000000);
5556 spr_register(env, SPR_SPRG7, "SPRG7",
5557 SPR_NOACCESS, SPR_NOACCESS,
5558 &spr_read_generic, &spr_write_generic,
5559 0x00000000);
5560 spr_register(env, SPR_USPRG7, "USPRG7",
5561 &spr_read_ureg, SPR_NOACCESS,
5562 &spr_read_ureg, SPR_NOACCESS,
5563 0x00000000);
5564 /* Memory management */
5565 gen_low_BATs(env);
5566 gen_high_BATs(env);
578bb252 5567 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5568 init_excp_7450(env);
d63001d1
JM		 5569 env->dcache_line_size = 32;
5570 env->icache_line_size = 32;
a750fc0b
JM		 5571 /* Allocate hardware IRQ controller */
5572 ppc6xx_irq_init(env);
5573}
a750fc0b
JM		 5574
5575/* PowerPC 7455 (aka G4) */
082c6681
JM		 5576#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5577 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5578 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5579 PPC_FLOAT_STFIWX | \
5580 PPC_CACHE | PPC_CACHE_ICBI | \
5581 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5582 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5584 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5585 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b
JM		 5586 PPC_ALTIVEC)
5587#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5588#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5589#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5590#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5591#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5592#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5593 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5594 POWERPC_FLAG_BUS_CLK)
4e777442 5595#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5596
578bb252 5597__attribute__ (( unused ))
a750fc0b
JM		 5598static void init_proc_7455 (CPUPPCState *env)
5599{
5600 gen_spr_ne_601(env);
5601 gen_spr_7xx(env);
5602 /* Time base */
5603 gen_tbl(env);
5604 /* 74xx specific SPR */
5605 gen_spr_74xx(env);
5606 /* Level 3 cache control */
5607 gen_l3_ctrl(env);
5608 /* LDSTCR */
5609 /* XXX : not implemented */
5610 spr_register(env, SPR_LDSTCR, "LDSTCR",
5611 SPR_NOACCESS, SPR_NOACCESS,
5612 &spr_read_generic, &spr_write_generic,
5613 0x00000000);
5614 /* ICTRL */
5615 /* XXX : not implemented */
5616 spr_register(env, SPR_ICTRL, "ICTRL",
5617 SPR_NOACCESS, SPR_NOACCESS,
5618 &spr_read_generic, &spr_write_generic,
5619 0x00000000);
5620 /* MSSSR0 */
578bb252 5621 /* XXX : not implemented */
a750fc0b
JM		 5622 spr_register(env, SPR_MSSSR0, "MSSSR0",
5623 SPR_NOACCESS, SPR_NOACCESS,
5624 &spr_read_generic, &spr_write_generic,
5625 0x00000000);
5626 /* PMC */
5627 /* XXX : not implemented */
5628 spr_register(env, SPR_PMC5, "PMC5",
5629 SPR_NOACCESS, SPR_NOACCESS,
5630 &spr_read_generic, &spr_write_generic,
5631 0x00000000);
578bb252 5632 /* XXX : not implemented */
a750fc0b
JM		 5633 spr_register(env, SPR_UPMC5, "UPMC5",
5634 &spr_read_ureg, SPR_NOACCESS,
5635 &spr_read_ureg, SPR_NOACCESS,
5636 0x00000000);
578bb252 5637 /* XXX : not implemented */
a750fc0b
JM		 5638 spr_register(env, SPR_PMC6, "PMC6",
5639 SPR_NOACCESS, SPR_NOACCESS,
5640 &spr_read_generic, &spr_write_generic,
5641 0x00000000);
578bb252 5642 /* XXX : not implemented */
a750fc0b
JM		 5643 spr_register(env, SPR_UPMC6, "UPMC6",
5644 &spr_read_ureg, SPR_NOACCESS,
5645 &spr_read_ureg, SPR_NOACCESS,
5646 0x00000000);
5647 /* SPRGs */
5648 spr_register(env, SPR_SPRG4, "SPRG4",
5649 SPR_NOACCESS, SPR_NOACCESS,
5650 &spr_read_generic, &spr_write_generic,
5651 0x00000000);
5652 spr_register(env, SPR_USPRG4, "USPRG4",
5653 &spr_read_ureg, SPR_NOACCESS,
5654 &spr_read_ureg, SPR_NOACCESS,
5655 0x00000000);
5656 spr_register(env, SPR_SPRG5, "SPRG5",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_generic, &spr_write_generic,
5659 0x00000000);
5660 spr_register(env, SPR_USPRG5, "USPRG5",
5661 &spr_read_ureg, SPR_NOACCESS,
5662 &spr_read_ureg, SPR_NOACCESS,
5663 0x00000000);
5664 spr_register(env, SPR_SPRG6, "SPRG6",
5665 SPR_NOACCESS, SPR_NOACCESS,
5666 &spr_read_generic, &spr_write_generic,
5667 0x00000000);
5668 spr_register(env, SPR_USPRG6, "USPRG6",
5669 &spr_read_ureg, SPR_NOACCESS,
5670 &spr_read_ureg, SPR_NOACCESS,
5671 0x00000000);
5672 spr_register(env, SPR_SPRG7, "SPRG7",
5673 SPR_NOACCESS, SPR_NOACCESS,
5674 &spr_read_generic, &spr_write_generic,
5675 0x00000000);
5676 spr_register(env, SPR_USPRG7, "USPRG7",
5677 &spr_read_ureg, SPR_NOACCESS,
5678 &spr_read_ureg, SPR_NOACCESS,
5679 0x00000000);
5680 /* Memory management */
5681 gen_low_BATs(env);
5682 gen_high_BATs(env);
578bb252 5683 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5684 init_excp_7450(env);
d63001d1
JM		 5685 env->dcache_line_size = 32;
5686 env->icache_line_size = 32;
a750fc0b
JM		 5687 /* Allocate hardware IRQ controller */
5688 ppc6xx_irq_init(env);
5689}
a750fc0b 5690
4e777442
JM		 5691/* PowerPC 7457 (aka G4) */
5692#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5694 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5695 PPC_FLOAT_STFIWX | \
5696 PPC_CACHE | PPC_CACHE_ICBI | \
5697 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5698 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5699 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5700 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5701 PPC_SEGMENT | PPC_EXTERN | \
5702 PPC_ALTIVEC)
5703#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5704#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5705#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5706#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5707#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5708#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5709 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5710 POWERPC_FLAG_BUS_CLK)
5711#define check_pow_7457 check_pow_hid0_74xx
5712
5713__attribute__ (( unused ))
5714static void init_proc_7457 (CPUPPCState *env)
5715{
5716 gen_spr_ne_601(env);
5717 gen_spr_7xx(env);
5718 /* Time base */
5719 gen_tbl(env);
5720 /* 74xx specific SPR */
5721 gen_spr_74xx(env);
5722 /* Level 3 cache control */
5723 gen_l3_ctrl(env);
5724 /* L3ITCR1 */
5725 /* XXX : not implemented */
5726 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 /* L3ITCR2 */
5731 /* XXX : not implemented */
5732 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5733 SPR_NOACCESS, SPR_NOACCESS,
5734 &spr_read_generic, &spr_write_generic,
5735 0x00000000);
5736 /* L3ITCR3 */
5737 /* XXX : not implemented */
5738 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5739 SPR_NOACCESS, SPR_NOACCESS,
5740 &spr_read_generic, &spr_write_generic,
5741 0x00000000);
5742 /* L3OHCR */
5743 /* XXX : not implemented */
5744 spr_register(env, SPR_L3OHCR, "L3OHCR",
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_read_generic, &spr_write_generic,
5747 0x00000000);
5748 /* LDSTCR */
5749 /* XXX : not implemented */
5750 spr_register(env, SPR_LDSTCR, "LDSTCR",
5751 SPR_NOACCESS, SPR_NOACCESS,
5752 &spr_read_generic, &spr_write_generic,
5753 0x00000000);
5754 /* ICTRL */
5755 /* XXX : not implemented */
5756 spr_register(env, SPR_ICTRL, "ICTRL",
5757 SPR_NOACCESS, SPR_NOACCESS,
5758 &spr_read_generic, &spr_write_generic,
5759 0x00000000);
5760 /* MSSSR0 */
5761 /* XXX : not implemented */
5762 spr_register(env, SPR_MSSSR0, "MSSSR0",
5763 SPR_NOACCESS, SPR_NOACCESS,
5764 &spr_read_generic, &spr_write_generic,
5765 0x00000000);
5766 /* PMC */
5767 /* XXX : not implemented */
5768 spr_register(env, SPR_PMC5, "PMC5",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 &spr_read_generic, &spr_write_generic,
5771 0x00000000);
5772 /* XXX : not implemented */
5773 spr_register(env, SPR_UPMC5, "UPMC5",
5774 &spr_read_ureg, SPR_NOACCESS,
5775 &spr_read_ureg, SPR_NOACCESS,
5776 0x00000000);
5777 /* XXX : not implemented */
5778 spr_register(env, SPR_PMC6, "PMC6",
5779 SPR_NOACCESS, SPR_NOACCESS,
5780 &spr_read_generic, &spr_write_generic,
5781 0x00000000);
5782 /* XXX : not implemented */
5783 spr_register(env, SPR_UPMC6, "UPMC6",
5784 &spr_read_ureg, SPR_NOACCESS,
5785 &spr_read_ureg, SPR_NOACCESS,
5786 0x00000000);
5787 /* SPRGs */
5788 spr_register(env, SPR_SPRG4, "SPRG4",
5789 SPR_NOACCESS, SPR_NOACCESS,
5790 &spr_read_generic, &spr_write_generic,
5791 0x00000000);
5792 spr_register(env, SPR_USPRG4, "USPRG4",
5793 &spr_read_ureg, SPR_NOACCESS,
5794 &spr_read_ureg, SPR_NOACCESS,
5795 0x00000000);
5796 spr_register(env, SPR_SPRG5, "SPRG5",
5797 SPR_NOACCESS, SPR_NOACCESS,
5798 &spr_read_generic, &spr_write_generic,
5799 0x00000000);
5800 spr_register(env, SPR_USPRG5, "USPRG5",
5801 &spr_read_ureg, SPR_NOACCESS,
5802 &spr_read_ureg, SPR_NOACCESS,
5803 0x00000000);
5804 spr_register(env, SPR_SPRG6, "SPRG6",
5805 SPR_NOACCESS, SPR_NOACCESS,
5806 &spr_read_generic, &spr_write_generic,
5807 0x00000000);
5808 spr_register(env, SPR_USPRG6, "USPRG6",
5809 &spr_read_ureg, SPR_NOACCESS,
5810 &spr_read_ureg, SPR_NOACCESS,
5811 0x00000000);
5812 spr_register(env, SPR_SPRG7, "SPRG7",
5813 SPR_NOACCESS, SPR_NOACCESS,
5814 &spr_read_generic, &spr_write_generic,
5815 0x00000000);
5816 spr_register(env, SPR_USPRG7, "USPRG7",
5817 &spr_read_ureg, SPR_NOACCESS,
5818 &spr_read_ureg, SPR_NOACCESS,
5819 0x00000000);
5820 /* Memory management */
5821 gen_low_BATs(env);
5822 gen_high_BATs(env);
5823 gen_74xx_soft_tlb(env, 128, 2);
5824 init_excp_7450(env);
5825 env->dcache_line_size = 32;
5826 env->icache_line_size = 32;
5827 /* Allocate hardware IRQ controller */
5828 ppc6xx_irq_init(env);
5829}
5830
a750fc0b
JM		 5831#if defined (TARGET_PPC64)
5832/* PowerPC 970 */
082c6681
JM		 5833#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5834 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5835 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5836 PPC_FLOAT_STFIWX | \
5837 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5838 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5839 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5840 PPC_64B | PPC_ALTIVEC | \
12de9a39 5841 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5842#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 5843#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 5844//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5845#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 5846#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 5847#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5848 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5849 POWERPC_FLAG_BUS_CLK)
a750fc0b 5850
417bf010
JM		 5851#if defined(CONFIG_USER_ONLY)
5852#define POWERPC970_HID5_INIT 0x00000080
5853#else
5854#define POWERPC970_HID5_INIT 0x00000000
5855#endif
5856
2f462816
JM		 5857static int check_pow_970 (CPUPPCState *env)
5858{
5859 if (env->spr[SPR_HID0] & 0x00600000)
5860 return 1;
5861
5862 return 0;
5863}
5864
a750fc0b
JM		 5865static void init_proc_970 (CPUPPCState *env)
5866{
5867 gen_spr_ne_601(env);
5868 gen_spr_7xx(env);
5869 /* Time base */
5870 gen_tbl(env);
5871 /* Hardware implementation registers */
5872 /* XXX : not implemented */
5873 spr_register(env, SPR_HID0, "HID0",
5874 SPR_NOACCESS, SPR_NOACCESS,
06403421 5875 &spr_read_generic, &spr_write_clear,
d63001d1 5876 0x60000000);
a750fc0b
JM		 5877 /* XXX : not implemented */
5878 spr_register(env, SPR_HID1, "HID1",
5879 SPR_NOACCESS, SPR_NOACCESS,
5880 &spr_read_generic, &spr_write_generic,
5881 0x00000000);
5882 /* XXX : not implemented */
bd928eba 5883 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, &spr_write_generic,
5886 0x00000000);
e57448f1
JM		 5887 /* XXX : not implemented */
5888 spr_register(env, SPR_970_HID5, "HID5",
5889 SPR_NOACCESS, SPR_NOACCESS,
5890 &spr_read_generic, &spr_write_generic,
417bf010 5891 POWERPC970_HID5_INIT);
bd928eba
JM		 5892 /* XXX : not implemented */
5893 spr_register(env, SPR_L2CR, "L2CR",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 &spr_read_generic, &spr_write_generic,
5896 0x00000000);
a750fc0b
JM		 5897 /* Memory management */
5898 /* XXX: not correct */
5899 gen_low_BATs(env);
12de9a39
JM		 5900 /* XXX : not implemented */
5901 spr_register(env, SPR_MMUCFG, "MMUCFG",
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 &spr_read_generic, SPR_NOACCESS,
5904 0x00000000); /* TOFIX */
5905 /* XXX : not implemented */
5906 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 0x00000000); /* TOFIX */
5910 spr_register(env, SPR_HIOR, "SPR_HIOR",
5911 SPR_NOACCESS, SPR_NOACCESS,
5912 &spr_read_generic, &spr_write_generic,
5913 0xFFF00000); /* XXX: This is a hack */
f2e63a42 5914#if !defined(CONFIG_USER_ONLY)
12de9a39 5915 env->slb_nr = 32;
f2e63a42 5916#endif
e1833e1f 5917 init_excp_970(env);
d63001d1
JM		 5918 env->dcache_line_size = 128;
5919 env->icache_line_size = 128;
a750fc0b
JM		 5920 /* Allocate hardware IRQ controller */
5921 ppc970_irq_init(env);
5922}
a750fc0b
JM		 5923
5924/* PowerPC 970FX (aka G5) */
082c6681
JM		 5925#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5926 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5927 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5928 PPC_FLOAT_STFIWX | \
5929 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5930 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5931 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 5932 PPC_64B | PPC_ALTIVEC | \
12de9a39 5933 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 5934#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 5935#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 5936#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5937#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 5938#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 5939#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5941 POWERPC_FLAG_BUS_CLK)
a750fc0b 5942
2f462816
JM		 5943static int check_pow_970FX (CPUPPCState *env)
5944{
5945 if (env->spr[SPR_HID0] & 0x00600000)
5946 return 1;
5947
5948 return 0;
5949}
5950
a750fc0b
JM		 5951static void init_proc_970FX (CPUPPCState *env)
5952{
5953 gen_spr_ne_601(env);
5954 gen_spr_7xx(env);
5955 /* Time base */
5956 gen_tbl(env);
5957 /* Hardware implementation registers */
5958 /* XXX : not implemented */
5959 spr_register(env, SPR_HID0, "HID0",
5960 SPR_NOACCESS, SPR_NOACCESS,
06403421 5961 &spr_read_generic, &spr_write_clear,
d63001d1 5962 0x60000000);
a750fc0b
JM		 5963 /* XXX : not implemented */
5964 spr_register(env, SPR_HID1, "HID1",
5965 SPR_NOACCESS, SPR_NOACCESS,
5966 &spr_read_generic, &spr_write_generic,
5967 0x00000000);
5968 /* XXX : not implemented */
bd928eba 5969 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5970 SPR_NOACCESS, SPR_NOACCESS,
5971 &spr_read_generic, &spr_write_generic,
5972 0x00000000);
d63001d1
JM		 5973 /* XXX : not implemented */
5974 spr_register(env, SPR_970_HID5, "HID5",
5975 SPR_NOACCESS, SPR_NOACCESS,
5976 &spr_read_generic, &spr_write_generic,
417bf010 5977 POWERPC970_HID5_INIT);
bd928eba
JM		 5978 /* XXX : not implemented */
5979 spr_register(env, SPR_L2CR, "L2CR",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, &spr_write_generic,
5982 0x00000000);
a750fc0b
JM		 5983 /* Memory management */
5984 /* XXX: not correct */
5985 gen_low_BATs(env);
12de9a39
JM		 5986 /* XXX : not implemented */
5987 spr_register(env, SPR_MMUCFG, "MMUCFG",
5988 SPR_NOACCESS, SPR_NOACCESS,
5989 &spr_read_generic, SPR_NOACCESS,
5990 0x00000000); /* TOFIX */
5991 /* XXX : not implemented */
5992 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5993 SPR_NOACCESS, SPR_NOACCESS,
5994 &spr_read_generic, &spr_write_generic,
5995 0x00000000); /* TOFIX */
5996 spr_register(env, SPR_HIOR, "SPR_HIOR",
5997 SPR_NOACCESS, SPR_NOACCESS,
5998 &spr_read_generic, &spr_write_generic,
5999 0xFFF00000); /* XXX: This is a hack */
f2e63a42 6000#if !defined(CONFIG_USER_ONLY)
12de9a39 6001 env->slb_nr = 32;
f2e63a42 6002#endif
e1833e1f 6003 init_excp_970(env);
d63001d1
JM		 6004 env->dcache_line_size = 128;
6005 env->icache_line_size = 128;
a750fc0b
JM		 6006 /* Allocate hardware IRQ controller */
6007 ppc970_irq_init(env);
6008}
a750fc0b
JM		 6009
6010/* PowerPC 970 GX */
082c6681
JM		 6011#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6012 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6013 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6014 PPC_FLOAT_STFIWX | \
6015 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6016 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6017 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6018 PPC_64B | PPC_ALTIVEC | \
12de9a39 6019 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 6020#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6021#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6022#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6023#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6024#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6025#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6027 POWERPC_FLAG_BUS_CLK)
a750fc0b 6028
2f462816
JM		 6029static int check_pow_970GX (CPUPPCState *env)
6030{
6031 if (env->spr[SPR_HID0] & 0x00600000)
6032 return 1;
6033
6034 return 0;
6035}
6036
a750fc0b
JM		 6037static void init_proc_970GX (CPUPPCState *env)
6038{
6039 gen_spr_ne_601(env);
6040 gen_spr_7xx(env);
6041 /* Time base */
6042 gen_tbl(env);
6043 /* Hardware implementation registers */
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_HID0, "HID0",
6046 SPR_NOACCESS, SPR_NOACCESS,
06403421 6047 &spr_read_generic, &spr_write_clear,
d63001d1 6048 0x60000000);
a750fc0b
JM		 6049 /* XXX : not implemented */
6050 spr_register(env, SPR_HID1, "HID1",
6051 SPR_NOACCESS, SPR_NOACCESS,
6052 &spr_read_generic, &spr_write_generic,
6053 0x00000000);
6054 /* XXX : not implemented */
bd928eba 6055 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6056 SPR_NOACCESS, SPR_NOACCESS,
6057 &spr_read_generic, &spr_write_generic,
6058 0x00000000);
d63001d1
JM		 6059 /* XXX : not implemented */
6060 spr_register(env, SPR_970_HID5, "HID5",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 &spr_read_generic, &spr_write_generic,
417bf010 6063 POWERPC970_HID5_INIT);
bd928eba
JM		 6064 /* XXX : not implemented */
6065 spr_register(env, SPR_L2CR, "L2CR",
6066 SPR_NOACCESS, SPR_NOACCESS,
6067 &spr_read_generic, &spr_write_generic,
6068 0x00000000);
a750fc0b
JM		 6069 /* Memory management */
6070 /* XXX: not correct */
6071 gen_low_BATs(env);
12de9a39
JM		 6072 /* XXX : not implemented */
6073 spr_register(env, SPR_MMUCFG, "MMUCFG",
6074 SPR_NOACCESS, SPR_NOACCESS,
6075 &spr_read_generic, SPR_NOACCESS,
6076 0x00000000); /* TOFIX */
6077 /* XXX : not implemented */
6078 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6079 SPR_NOACCESS, SPR_NOACCESS,
6080 &spr_read_generic, &spr_write_generic,
6081 0x00000000); /* TOFIX */
6082 spr_register(env, SPR_HIOR, "SPR_HIOR",
6083 SPR_NOACCESS, SPR_NOACCESS,
6084 &spr_read_generic, &spr_write_generic,
6085 0xFFF00000); /* XXX: This is a hack */
f2e63a42 6086#if !defined(CONFIG_USER_ONLY)
12de9a39 6087 env->slb_nr = 32;
f2e63a42 6088#endif
e1833e1f 6089 init_excp_970(env);
d63001d1
JM		 6090 env->dcache_line_size = 128;
6091 env->icache_line_size = 128;
a750fc0b
JM		 6092 /* Allocate hardware IRQ controller */
6093 ppc970_irq_init(env);
6094}
a750fc0b 6095
2f462816 6096/* PowerPC 970 MP */
082c6681
JM		 6097#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6098 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6099 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6100 PPC_FLOAT_STFIWX | \
6101 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6102 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6103 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6104 PPC_64B | PPC_ALTIVEC | \
6105 PPC_SEGMENT_64B | PPC_SLBI)
6106#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6107#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6108#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6109#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6110#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6111#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6112 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6113 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6114
6115static int check_pow_970MP (CPUPPCState *env)
6116{
6117 if (env->spr[SPR_HID0] & 0x01C00000)
6118 return 1;
6119
6120 return 0;
6121}
6122
6123static void init_proc_970MP (CPUPPCState *env)
6124{
6125 gen_spr_ne_601(env);
6126 gen_spr_7xx(env);
6127 /* Time base */
6128 gen_tbl(env);
6129 /* Hardware implementation registers */
6130 /* XXX : not implemented */
6131 spr_register(env, SPR_HID0, "HID0",
6132 SPR_NOACCESS, SPR_NOACCESS,
6133 &spr_read_generic, &spr_write_clear,
6134 0x60000000);
6135 /* XXX : not implemented */
6136 spr_register(env, SPR_HID1, "HID1",
6137 SPR_NOACCESS, SPR_NOACCESS,
6138 &spr_read_generic, &spr_write_generic,
6139 0x00000000);
6140 /* XXX : not implemented */
bd928eba 6141 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
6145 /* XXX : not implemented */
6146 spr_register(env, SPR_970_HID5, "HID5",
6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 POWERPC970_HID5_INIT);
bd928eba
JM		 6150 /* XXX : not implemented */
6151 spr_register(env, SPR_L2CR, "L2CR",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
6154 0x00000000);
2f462816
JM		 6155 /* Memory management */
6156 /* XXX: not correct */
6157 gen_low_BATs(env);
6158 /* XXX : not implemented */
6159 spr_register(env, SPR_MMUCFG, "MMUCFG",
6160 SPR_NOACCESS, SPR_NOACCESS,
6161 &spr_read_generic, SPR_NOACCESS,
6162 0x00000000); /* TOFIX */
6163 /* XXX : not implemented */
6164 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6165 SPR_NOACCESS, SPR_NOACCESS,
6166 &spr_read_generic, &spr_write_generic,
6167 0x00000000); /* TOFIX */
6168 spr_register(env, SPR_HIOR, "SPR_HIOR",
6169 SPR_NOACCESS, SPR_NOACCESS,
6170 &spr_read_generic, &spr_write_generic,
6171 0xFFF00000); /* XXX: This is a hack */
2f462816
JM		 6172#if !defined(CONFIG_USER_ONLY)
6173 env->slb_nr = 32;
6174#endif
6175 init_excp_970(env);
6176 env->dcache_line_size = 128;
6177 env->icache_line_size = 128;
6178 /* Allocate hardware IRQ controller */
6179 ppc970_irq_init(env);
6180}
6181
a750fc0b 6182/* PowerPC 620 */
082c6681
JM		 6183#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6184 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6185 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6186 PPC_FLOAT_STFIWX | \
6187 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6188 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6189 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6190 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6191 PPC_64B | PPC_SLBI)
add78955
JM		 6192#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6193//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6194#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6195#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6196#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6197#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6198 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6199#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6200
578bb252 6201__attribute__ (( unused ))
a750fc0b
JM		 6202static void init_proc_620 (CPUPPCState *env)
6203{
6204 gen_spr_ne_601(env);
6205 gen_spr_620(env);
6206 /* Time base */
6207 gen_tbl(env);
6208 /* Hardware implementation registers */
6209 /* XXX : not implemented */
6210 spr_register(env, SPR_HID0, "HID0",
6211 SPR_NOACCESS, SPR_NOACCESS,
6212 &spr_read_generic, &spr_write_generic,
6213 0x00000000);
6214 /* Memory management */
6215 gen_low_BATs(env);
e1833e1f 6216 init_excp_620(env);
d63001d1
JM		 6217 env->dcache_line_size = 64;
6218 env->icache_line_size = 64;
faadf50e
JM		 6219 /* Allocate hardware IRQ controller */
6220 ppc6xx_irq_init(env);
a750fc0b 6221}
a750fc0b
JM		 6222#endif /* defined (TARGET_PPC64) */
6223
6224/* Default 32 bits PowerPC target will be 604 */
6225#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6226#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6227#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6228#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6229#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6230#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6231#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6232#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6233#define check_pow_PPC32 check_pow_604
6234#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6235
6236/* Default 64 bits PowerPC target will be 970 FX */
6237#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6238#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6239#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6240#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6241#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6242#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6243#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6244#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6245#define check_pow_PPC64 check_pow_970FX
6246#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6247
6248/* Default PowerPC target will be PowerPC 32 */
6249#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 6250#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6251#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6252#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6253#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6254#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6255#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 6256#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 6257#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 6258#define check_pow_DEFAULT check_pow_PPC64
6259#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6260#else
d12f4c38
JM		 6261#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6262#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6263#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6264#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6265#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6266#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 6267#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 6268#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 6269#define check_pow_DEFAULT check_pow_PPC32
6270#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6271#endif
6272
6273/*****************************************************************************/
6274/* PVR definitions for most known PowerPC */
6275enum {
6276 /* PowerPC 401 family */
6277 /* Generic PowerPC 401 */
80d11f44 6278#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6279 /* PowerPC 401 cores */
80d11f44
JM		 6280 CPU_POWERPC_401A1 = 0x00210000,
6281 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6282#if 0
80d11f44 6283 CPU_POWERPC_401B3 = xxx,
a750fc0b 6284#endif
80d11f44
JM		 6285 CPU_POWERPC_401C2 = 0x00230000,
6286 CPU_POWERPC_401D2 = 0x00240000,
6287 CPU_POWERPC_401E2 = 0x00250000,
6288 CPU_POWERPC_401F2 = 0x00260000,
6289 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6290 /* PowerPC 401 microcontrolers */
6291#if 0
80d11f44 6292 CPU_POWERPC_401GF = xxx,
a750fc0b 6293#endif
80d11f44 6294#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6295 /* IBM Processor for Network Resources */
80d11f44 6296 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6297#if 0
80d11f44 6298 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6299#endif
6300 /* PowerPC 403 family */
6301 /* Generic PowerPC 403 */
80d11f44 6302#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6303 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6304 CPU_POWERPC_403GA = 0x00200011,
6305 CPU_POWERPC_403GB = 0x00200100,
6306 CPU_POWERPC_403GC = 0x00200200,
6307 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6308#if 0
80d11f44 6309 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6310#endif
6311 /* PowerPC 405 family */
6312 /* Generic PowerPC 405 */
80d11f44 6313#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6314 /* PowerPC 405 cores */
6315#if 0
80d11f44 6316 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6317#endif
6318#if 0
80d11f44 6319 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6320#endif
6321#if 0
80d11f44 6322 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6323#endif
6324#if 0
80d11f44 6325 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6326#endif
6327#if 0
80d11f44 6328 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6329#endif
6330#if 0
80d11f44 6331 CPU_POWERPC_405C4 = xxx,
a750fc0b 6332#endif
80d11f44 6333 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6334#if 0
80d11f44 6335 CPU_POWERPC_405D3 = xxx,
a750fc0b 6336#endif
80d11f44 6337 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6338#if 0
80d11f44 6339 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6340#endif
6341#if 0
80d11f44 6342 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6343#endif
6344#if 0
80d11f44 6345 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6346#endif
6347#if 0
80d11f44 6348 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6349#endif
6350#if 0
80d11f44 6351 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6352#endif
6353 /* PowerPC 405 microcontrolers */
6354 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6355#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6356 CPU_POWERPC_405CRa = 0x40110041,
6357 CPU_POWERPC_405CRb = 0x401100C5,
6358 CPU_POWERPC_405CRc = 0x40110145,
6359 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6360#if 0
80d11f44 6361 CPU_POWERPC_405EXr = xxx,
a750fc0b 6362#endif
80d11f44 6363 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6364#if 0
80d11f44
JM		 6365 CPU_POWERPC_405FX = xxx,
6366#endif
6367#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6368 CPU_POWERPC_405GPa = 0x40110000,
6369 CPU_POWERPC_405GPb = 0x40110040,
6370 CPU_POWERPC_405GPc = 0x40110082,
6371 CPU_POWERPC_405GPd = 0x401100C4,
6372#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6373 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6374#if 0
80d11f44 6375 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6376#endif
6377#if 0
80d11f44 6378 CPU_POWERPC_405L = xxx,
a750fc0b 6379#endif
80d11f44 6380 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6381#if 0
80d11f44 6382 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6383#endif
6384#if 0
80d11f44 6385 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6386#endif
6387#if 0
80d11f44 6388 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6389#endif
6390 /* IBM network processors */
80d11f44
JM		 6391 CPU_POWERPC_NPE405H = 0x414100C0,
6392 CPU_POWERPC_NPE405H2 = 0x41410140,
6393 CPU_POWERPC_NPE405L = 0x416100C0,
6394 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6395#if 0
80d11f44 6396 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6397#endif
6398#if 0
80d11f44 6399 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6400#endif
6401#if 0
80d11f44 6402 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6403#endif
6404 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6405#if 0
80d11f44 6406 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6407#endif
6408#if 0
80d11f44 6409 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6410#endif
6411#if 0
80d11f44 6412 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6413#endif
80d11f44 6414 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6415#if 0
80d11f44 6416 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6417#endif
6418#if 0
80d11f44 6419 CPU_POWERPC_STB045 = xxx,
a750fc0b 6420#endif
80d11f44
JM		 6421 CPU_POWERPC_STB04 = 0x41810000,
6422 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6423#if 0
80d11f44 6424 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6425#endif
6426 /* Xilinx cores */
80d11f44
JM		 6427 CPU_POWERPC_X2VP4 = 0x20010820,
6428#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6429 CPU_POWERPC_X2VP20 = 0x20010860,
6430#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6431#if 0
80d11f44 6432 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6433#endif
6434#if 0
80d11f44 6435 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6436#endif
6437#if 0
80d11f44 6438 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6439#endif
6440#if 0
80d11f44 6441 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6442#endif
6443 /* PowerPC 440 family */
6444 /* Generic PowerPC 440 */
80d11f44 6445#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6446 /* PowerPC 440 cores */
6447#if 0
80d11f44 6448 CPU_POWERPC_440A4 = xxx,
a750fc0b
JM		 6449#endif
6450#if 0
80d11f44 6451 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6452#endif
6453#if 0
80d11f44 6454 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6455#endif
6456#if 0
80d11f44 6457 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6458#endif
6459#if 0
80d11f44 6460 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6461#endif
6462#if 0
80d11f44 6463 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6464#endif
6465#if 0
80d11f44 6466 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6467#endif
6468 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6469#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6470 CPU_POWERPC_440EPa = 0x42221850,
6471 CPU_POWERPC_440EPb = 0x422218D3,
6472#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6473 CPU_POWERPC_440GPb = 0x40120440,
6474 CPU_POWERPC_440GPc = 0x40120481,
6475#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6476#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6477 CPU_POWERPC_440GRX = 0x200008D0,
6478#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6479#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6480 CPU_POWERPC_440GXa = 0x51B21850,
6481 CPU_POWERPC_440GXb = 0x51B21851,
6482 CPU_POWERPC_440GXc = 0x51B21892,
6483 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6484#if 0
80d11f44 6485 CPU_POWERPC_440S = xxx,
a750fc0b 6486#endif
80d11f44
JM		 6487 CPU_POWERPC_440SP = 0x53221850,
6488 CPU_POWERPC_440SP2 = 0x53221891,
6489 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6490 /* PowerPC 460 family */
6491#if 0
6492 /* Generic PowerPC 464 */
80d11f44 6493#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6494#endif
6495 /* PowerPC 464 microcontrolers */
6496#if 0
80d11f44 6497 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6498#endif
6499#if 0
80d11f44 6500 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6501#endif
6502 /* Freescale embedded PowerPC cores */
c3e36823 6503 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6504 CPU_POWERPC_MPC5xx = 0x00020020,
6505#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6506#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6507#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6508#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6509#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6510#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6511#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6512#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6513#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6514#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6515#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6516#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6517#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6518 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6519 CPU_POWERPC_MPC8xx = 0x00500000,
6520#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6521#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6522#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6523#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6524#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6525#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6526#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6527#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6528#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6529#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6530#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6531#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6532#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6533#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6534#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6535 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6536 CPU_POWERPC_G2 = 0x00810011,
6537 CPU_POWERPC_G2H4 = 0x80811010,
6538 CPU_POWERPC_G2gp = 0x80821010,
6539 CPU_POWERPC_G2ls = 0x90810010,
6540 CPU_POWERPC_MPC603 = 0x00810100,
6541 CPU_POWERPC_G2_HIP3 = 0x00810101,
6542 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6543 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6544 CPU_POWERPC_G2LE = 0x80820010,
6545 CPU_POWERPC_G2LEgp = 0x80822010,
6546 CPU_POWERPC_G2LEls = 0xA0822010,
6547 CPU_POWERPC_G2LEgp1 = 0x80822011,
6548 CPU_POWERPC_G2LEgp3 = 0x80822013,
6549 /* MPC52xx microcontrollers */
c3e36823 6550 /* XXX: MPC 5121 ? */
80d11f44
JM		 6551#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6552#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6553#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6554#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6555#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6556#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6557#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6558#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6559 /* MPC82xx microcontrollers */
6560#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6561#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6562#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6563#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6564#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6565#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6566#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6567#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6568#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6569#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6570#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6571#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6572#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6573#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6574#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6575#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6576#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6577#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6578#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6579#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6580#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6581#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6582#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6583#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6584#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6585#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6586#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6587#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6588#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6589 /* e200 family */
80d11f44
JM		 6590 /* e200 cores */
6591#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6592#if 0
80d11f44 6593 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6594#endif
6595#if 0
80d11f44 6596 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6597#endif
6598#if 0 /* ? */
80d11f44
JM		 6599 CPU_POWERPC_e200z3 = 0x81120000,
6600#endif
6601 CPU_POWERPC_e200z5 = 0x81000000,
6602 CPU_POWERPC_e200z6 = 0x81120000,
6603 /* MPC55xx microcontrollers */
6604#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6605#if 0
6606#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6607#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6608#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6609#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6610#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6611#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6612#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6613#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6614#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6615#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6616#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6617#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6618#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6619#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6620#endif
6621#if 0
6622#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6623#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6624#endif
6625#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6626#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6627#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6628#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6629#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6630#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 6631 /* e300 family */
80d11f44
JM		 6632 /* e300 cores */
6633#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6634 CPU_POWERPC_e300c1 = 0x00830010,
6635 CPU_POWERPC_e300c2 = 0x00840010,
6636 CPU_POWERPC_e300c3 = 0x00850010,
6637 CPU_POWERPC_e300c4 = 0x00860010,
6638 /* MPC83xx microcontrollers */
6639#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
6640#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
6641#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
6642#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
6643#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
6644#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
6645#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
6646#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
6647#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
6648#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
6649#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
6650#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
6651#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
6652#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
6653#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
6654#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
6655#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
6656#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
6657#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
6658#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
6659#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
6660#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
6661#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
6662#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
6663#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
6664#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
6665#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
6666#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
6667#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6668#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
a750fc0b 6669 /* e500 family */
80d11f44
JM		 6670 /* e500 cores */
6671#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
6672#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
6673 CPU_POWERPC_e500_v10 = 0x80200010,
6674 CPU_POWERPC_e500_v20 = 0x80200020,
6675 CPU_POWERPC_e500v2_v10 = 0x80210010,
6676 CPU_POWERPC_e500v2_v11 = 0x80210011,
6677 CPU_POWERPC_e500v2_v20 = 0x80210020,
6678 CPU_POWERPC_e500v2_v21 = 0x80210021,
6679 CPU_POWERPC_e500v2_v22 = 0x80210022,
6680 CPU_POWERPC_e500v2_v30 = 0x80210030,
6681 /* MPC85xx microcontrollers */
6682#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6683#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6684#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6685#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6686#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6687#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6688#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
6689#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
6690#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
6691#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
6692#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
6693#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
6694#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
6695#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
6696#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
6697#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
6698#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6699#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6700#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6701#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6702#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6703#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6704#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6705#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6706#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6707#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6708#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6709#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6710#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6711#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6712#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6713#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6714#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6715#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6716#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6717#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6718#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6719#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6720#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6721#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6722#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6723#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6724#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6725#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6726#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6727#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6728#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6729#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6730#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6731#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6732#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6733#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6734#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6735#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6736#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6737#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6738#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6739#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6740#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6741#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6742#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6743#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6744#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6745#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6746#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6747#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6748#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6749#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6750#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6751#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 6752 /* e600 family */
80d11f44
JM		 6753 /* e600 cores */
6754 CPU_POWERPC_e600 = 0x80040010,
6755 /* MPC86xx microcontrollers */
6756#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6757#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6758#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 6759 /* PowerPC 6xx cores */
80d11f44
JM		 6760#define CPU_POWERPC_601 CPU_POWERPC_601_v2
6761 CPU_POWERPC_601_v0 = 0x00010001,
6762 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 6763#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 6764 CPU_POWERPC_601_v2 = 0x00010002,
6765 CPU_POWERPC_602 = 0x00050100,
6766 CPU_POWERPC_603 = 0x00030100,
6767#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6768 CPU_POWERPC_603E_v11 = 0x00060101,
6769 CPU_POWERPC_603E_v12 = 0x00060102,
6770 CPU_POWERPC_603E_v13 = 0x00060103,
6771 CPU_POWERPC_603E_v14 = 0x00060104,
6772 CPU_POWERPC_603E_v22 = 0x00060202,
6773 CPU_POWERPC_603E_v3 = 0x00060300,
6774 CPU_POWERPC_603E_v4 = 0x00060400,
6775 CPU_POWERPC_603E_v41 = 0x00060401,
6776 CPU_POWERPC_603E7t = 0x00071201,
6777 CPU_POWERPC_603E7v = 0x00070100,
6778 CPU_POWERPC_603E7v1 = 0x00070101,
6779 CPU_POWERPC_603E7v2 = 0x00070201,
6780 CPU_POWERPC_603E7 = 0x00070200,
6781 CPU_POWERPC_603P = 0x00070000,
6782#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 6783 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 6784 CPU_POWERPC_604 = 0x00040103,
6785#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 6786 /* XXX: missing 0x00091203 */
6787 /* XXX: missing 0x00092110 */
6788 /* XXX: missing 0x00092120 */
80d11f44
JM		 6789 CPU_POWERPC_604E_v10 = 0x00090100,
6790 CPU_POWERPC_604E_v22 = 0x00090202,
6791 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 6792 /* XXX: missing 0x000a0100 */
6793 /* XXX: missing 0x00093102 */
80d11f44 6794 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 6795#if 0
80d11f44 6796 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 6797#endif
6798 /* PowerPC 740/750 cores (aka G3) */
6799 /* XXX: missing 0x00084202 */
80d11f44 6800#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 6801 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 6802 CPU_POWERPC_7x0_v20 = 0x00080200,
6803 CPU_POWERPC_7x0_v21 = 0x00080201,
6804 CPU_POWERPC_7x0_v22 = 0x00080202,
6805 CPU_POWERPC_7x0_v30 = 0x00080300,
6806 CPU_POWERPC_7x0_v31 = 0x00080301,
6807 CPU_POWERPC_740E = 0x00080100,
bd928eba 6808 CPU_POWERPC_750E = 0x00080200,
80d11f44 6809 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 6810 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 6811#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6812 CPU_POWERPC_750CL_v10 = 0x00087200,
6813 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 6814#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 6815 CPU_POWERPC_750CX_v10 = 0x00082100,
6816 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 6817 CPU_POWERPC_750CX_v21 = 0x00082201,
6818 CPU_POWERPC_750CX_v22 = 0x00082202,
6819#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6820 CPU_POWERPC_750CXE_v21 = 0x00082211,
6821 CPU_POWERPC_750CXE_v22 = 0x00082212,
6822 CPU_POWERPC_750CXE_v23 = 0x00082213,
6823 CPU_POWERPC_750CXE_v24 = 0x00082214,
6824 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 6825 CPU_POWERPC_750CXE_v30 = 0x00082310,
6826 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 6827 CPU_POWERPC_750CXE_v31b = 0x00083311,
6828 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 6829 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 6830#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6831 CPU_POWERPC_750FX_v10 = 0x70000100,
6832 CPU_POWERPC_750FX_v20 = 0x70000200,
6833 CPU_POWERPC_750FX_v21 = 0x70000201,
6834 CPU_POWERPC_750FX_v22 = 0x70000202,
6835 CPU_POWERPC_750FX_v23 = 0x70000203,
6836 CPU_POWERPC_750GL = 0x70020102,
6837#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6838 CPU_POWERPC_750GX_v10 = 0x70020100,
6839 CPU_POWERPC_750GX_v11 = 0x70020101,
6840 CPU_POWERPC_750GX_v12 = 0x70020102,
6841#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 6842 CPU_POWERPC_750L_v20 = 0x00088200,
6843 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 6844 CPU_POWERPC_750L_v22 = 0x00088202,
6845 CPU_POWERPC_750L_v30 = 0x00088300,
6846 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 6847 /* PowerPC 745/755 cores */
80d11f44
JM		 6848#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6849 CPU_POWERPC_7x5_v10 = 0x00083100,
6850 CPU_POWERPC_7x5_v11 = 0x00083101,
6851 CPU_POWERPC_7x5_v20 = 0x00083200,
6852 CPU_POWERPC_7x5_v21 = 0x00083201,
6853 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6854 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6855 CPU_POWERPC_7x5_v24 = 0x00083204,
6856 CPU_POWERPC_7x5_v25 = 0x00083205,
6857 CPU_POWERPC_7x5_v26 = 0x00083206,
6858 CPU_POWERPC_7x5_v27 = 0x00083207,
6859 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 6860#if 0
80d11f44 6861 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 6862#endif
6863 /* PowerPC 74xx cores (aka G4) */
6864 /* XXX: missing 0x000C1101 */
80d11f44
JM		 6865#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6866 CPU_POWERPC_7400_v10 = 0x000C0100,
6867 CPU_POWERPC_7400_v11 = 0x000C0101,
6868 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 6869 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 6870 CPU_POWERPC_7400_v22 = 0x000C0202,
6871 CPU_POWERPC_7400_v26 = 0x000C0206,
6872 CPU_POWERPC_7400_v27 = 0x000C0207,
6873 CPU_POWERPC_7400_v28 = 0x000C0208,
6874 CPU_POWERPC_7400_v29 = 0x000C0209,
6875#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6876 CPU_POWERPC_7410_v10 = 0x800C1100,
6877 CPU_POWERPC_7410_v11 = 0x800C1101,
6878 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6879 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6880 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6881#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6882 CPU_POWERPC_7448_v10 = 0x80040100,
6883 CPU_POWERPC_7448_v11 = 0x80040101,
6884 CPU_POWERPC_7448_v20 = 0x80040200,
6885 CPU_POWERPC_7448_v21 = 0x80040201,
6886#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6887 CPU_POWERPC_7450_v10 = 0x80000100,
6888 CPU_POWERPC_7450_v11 = 0x80000101,
6889 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 6890 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 6891 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 6892#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
6893 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
6894 /* XXX: this entry might be a bug in some documentation */
6895 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 6896#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6897 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 6898 /* XXX: missing 0x80010200 */
80d11f44
JM		 6899 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6900 CPU_POWERPC_74x5_v32 = 0x80010302,
6901 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6902 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6903#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 6904 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 6905 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 6906 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 6907#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6908 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6909 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6910 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 6911 /* 64 bits PowerPC */
00af685f 6912#if defined(TARGET_PPC64)
80d11f44
JM		 6913 CPU_POWERPC_620 = 0x00140000,
6914 CPU_POWERPC_630 = 0x00400000,
6915 CPU_POWERPC_631 = 0x00410104,
6916 CPU_POWERPC_POWER4 = 0x00350000,
6917 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 6918 /* XXX: missing 0x003A0201 */
80d11f44
JM		 6919 CPU_POWERPC_POWER5 = 0x003A0203,
6920#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6921 CPU_POWERPC_POWER5P = 0x003B0000,
6922#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6923 CPU_POWERPC_POWER6 = 0x003E0000,
6924 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6925 CPU_POWERPC_POWER6A = 0x0F000002,
6926 CPU_POWERPC_970 = 0x00390202,
6927#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6928 CPU_POWERPC_970FX_v10 = 0x00391100,
6929 CPU_POWERPC_970FX_v20 = 0x003C0200,
6930 CPU_POWERPC_970FX_v21 = 0x003C0201,
6931 CPU_POWERPC_970FX_v30 = 0x003C0300,
6932 CPU_POWERPC_970FX_v31 = 0x003C0301,
6933 CPU_POWERPC_970GX = 0x00450000,
6934#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6935 CPU_POWERPC_970MP_v10 = 0x00440100,
6936 CPU_POWERPC_970MP_v11 = 0x00440101,
6937#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6938 CPU_POWERPC_CELL_v10 = 0x00700100,
6939 CPU_POWERPC_CELL_v20 = 0x00700400,
6940 CPU_POWERPC_CELL_v30 = 0x00700500,
6941 CPU_POWERPC_CELL_v31 = 0x00700501,
6942#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
6943 CPU_POWERPC_RS64 = 0x00330000,
6944 CPU_POWERPC_RS64II = 0x00340000,
6945 CPU_POWERPC_RS64III = 0x00360000,
6946 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 6947#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 6948 /* Original POWER */
6949 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6950 * POWER2 (RIOS2) & RSC2 (P2SC) here
6951 */
6952#if 0
80d11f44 6953 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 6954#endif
6955#if 0
80d11f44 6956 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 6957#endif
6958 /* PA Semi core */
80d11f44 6959 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 6960};
6961
6962/* System version register (used on MPC 8xxx) */
6963enum {
80d11f44
JM		 6964 POWERPC_SVR_NONE = 0x00000000,
6965#define POWERPC_SVR_52xx POWERPC_SVR_5200
6966#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
6967 POWERPC_SVR_5200_v10 = 0x80110010,
6968 POWERPC_SVR_5200_v11 = 0x80110011,
6969 POWERPC_SVR_5200_v12 = 0x80110012,
6970#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
6971 POWERPC_SVR_5200B_v20 = 0x80110020,
6972 POWERPC_SVR_5200B_v21 = 0x80110021,
6973#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 6974#if 0
80d11f44 6975 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 6976#endif
6977#if 0
80d11f44 6978 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 6979#endif
6980#if 0
80d11f44 6981 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 6982#endif
6983#if 0
80d11f44 6984 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 6985#endif
6986#if 0
80d11f44 6987 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 6988#endif
6989#if 0
80d11f44 6990 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 6991#endif
6992#if 0
80d11f44 6993 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 6994#endif
6995#if 0
80d11f44 6996 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 6997#endif
6998#if 0
80d11f44 6999 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7000#endif
7001#if 0
80d11f44 7002 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7003#endif
7004#if 0
80d11f44 7005 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7006#endif
7007#if 0
80d11f44 7008 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7009#endif
7010#if 0
80d11f44 7011 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7012#endif
7013#if 0
80d11f44 7014 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7015#endif
7016#if 0
80d11f44 7017 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7018#endif
7019#if 0
80d11f44 7020 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7021#endif
7022#if 0
80d11f44 7023 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7024#endif
7025#if 0
80d11f44
JM		 7026 POWERPC_SVR_8323E = xxx,
7027#endif
7028 POWERPC_SVR_8343A = 0x80570030,
7029 POWERPC_SVR_8343EA = 0x80560030,
7030#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7031 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7032 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7033#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7034 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7035 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7036 POWERPC_SVR_8349 = 0x80510010,
7037 POWERPC_SVR_8349A = 0x80510030,
7038 POWERPC_SVR_8349E = 0x80500010,
7039 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7040#if 0
80d11f44 7041 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7042#endif
7043#if 0
80d11f44
JM		 7044 POWERPC_SVR_8360E = xxx,
7045#endif
7046#define POWERPC_SVR_E500 0x40000000
7047 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7048 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7049 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7050 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7051 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7052 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7053#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7054 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7055 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7056#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7057 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7058 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7059#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7060 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7061 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7062 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7063#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7064 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7065 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7066#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7067 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7068 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7069#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7070 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7071 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7072 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7073 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7074#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7075 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7076 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7077 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7078 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7079#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7080 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7081 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7082#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7083 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7084 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7085#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7086 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7087 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7088#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7089 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7090 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7091#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7092 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7093 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7094#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7095 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7096 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7097 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7098 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7099#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7100 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7101 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7102 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7103 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7104#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7105 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7106 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7107#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7108 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7109 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7110#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7111 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7112 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7113 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7114 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7115 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7116 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7117 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7118 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7119 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7120#if 0
80d11f44 7121 POWERPC_SVR_8610 = xxx,
c3e36823 7122#endif
80d11f44
JM		 7123 POWERPC_SVR_8641 = 0x80900021,
7124 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7125};
7126
3fc6c082 7127/*****************************************************************************/
a750fc0b 7128/* PowerPC CPU definitions */
80d11f44 7129#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b
JM		 7130 { \
7131 .name = _name, \
7132 .pvr = _pvr, \
80d11f44 7133 .svr = _svr, \
a750fc0b
JM		 7134 .insns_flags = glue(POWERPC_INSNS_,_type), \
7135 .msr_mask = glue(POWERPC_MSRM_,_type), \
7136 .mmu_model = glue(POWERPC_MMU_,_type), \
7137 .excp_model = glue(POWERPC_EXCP_,_type), \
7138 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 7139 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 7140 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 7141 .init_proc = &glue(init_proc_,_type), \
2f462816 7142 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7143 }
80d11f44
JM		 7144#define POWERPC_DEF(_name, _pvr, _type) \
7145POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7146
ee4e83ed 7147static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7148 /* Embedded PowerPC */
7149 /* PowerPC 401 family */
2662a059 7150 /* Generic PowerPC 401 */
80d11f44 7151 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7152 /* PowerPC 401 cores */
2662a059 7153 /* PowerPC 401A1 */
80d11f44 7154 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7155 /* PowerPC 401B2 */
80d11f44 7156 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7157#if defined (TODO)
a750fc0b 7158 /* PowerPC 401B3 */
80d11f44 7159 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7160#endif
7161 /* PowerPC 401C2 */
80d11f44 7162 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7163 /* PowerPC 401D2 */
80d11f44 7164 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7165 /* PowerPC 401E2 */
80d11f44 7166 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7167 /* PowerPC 401F2 */
80d11f44 7168 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7169 /* PowerPC 401G2 */
7170 /* XXX: to be checked */
80d11f44 7171 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7172 /* PowerPC 401 microcontrolers */
2662a059 7173#if defined (TODO)
a750fc0b 7174 /* PowerPC 401GF */
80d11f44 7175 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7176#endif
a750fc0b 7177 /* IOP480 (401 microcontroler) */
80d11f44 7178 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7179 /* IBM Processor for Network Resources */
80d11f44 7180 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7181#if defined (TODO)
80d11f44 7182 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7183#endif
a750fc0b
JM		 7184 /* PowerPC 403 family */
7185 /* Generic PowerPC 403 */
80d11f44 7186 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7187 /* PowerPC 403 microcontrolers */
7188 /* PowerPC 403 GA */
80d11f44 7189 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7190 /* PowerPC 403 GB */
80d11f44 7191 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7192 /* PowerPC 403 GC */
80d11f44 7193 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7194 /* PowerPC 403 GCX */
80d11f44 7195 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7196#if defined (TODO)
a750fc0b 7197 /* PowerPC 403 GP */
80d11f44 7198 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7199#endif
a750fc0b
JM		 7200 /* PowerPC 405 family */
7201 /* Generic PowerPC 405 */
80d11f44 7202 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7203 /* PowerPC 405 cores */
2662a059 7204#if defined (TODO)
a750fc0b 7205 /* PowerPC 405 A3 */
80d11f44 7206 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7207#endif
3a607854 7208#if defined (TODO)
a750fc0b 7209 /* PowerPC 405 A4 */
80d11f44 7210 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7211#endif
3a607854 7212#if defined (TODO)
a750fc0b 7213 /* PowerPC 405 B3 */
80d11f44 7214 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7215#endif
7216#if defined (TODO)
a750fc0b 7217 /* PowerPC 405 B4 */
80d11f44 7218 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7219#endif
7220#if defined (TODO)
7221 /* PowerPC 405 C3 */
80d11f44 7222 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7223#endif
7224#if defined (TODO)
7225 /* PowerPC 405 C4 */
80d11f44 7226 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7227#endif
7228 /* PowerPC 405 D2 */
80d11f44 7229 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7230#if defined (TODO)
7231 /* PowerPC 405 D3 */
80d11f44 7232 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7233#endif
7234 /* PowerPC 405 D4 */
80d11f44 7235 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7236#if defined (TODO)
7237 /* PowerPC 405 D5 */
80d11f44 7238 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7239#endif
7240#if defined (TODO)
7241 /* PowerPC 405 E4 */
80d11f44 7242 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7243#endif
7244#if defined (TODO)
7245 /* PowerPC 405 F4 */
80d11f44 7246 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7247#endif
7248#if defined (TODO)
7249 /* PowerPC 405 F5 */
80d11f44 7250 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7251#endif
7252#if defined (TODO)
7253 /* PowerPC 405 F6 */
80d11f44 7254 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7255#endif
7256 /* PowerPC 405 microcontrolers */
7257 /* PowerPC 405 CR */
80d11f44 7258 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7259 /* PowerPC 405 CRa */
80d11f44 7260 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7261 /* PowerPC 405 CRb */
80d11f44 7262 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7263 /* PowerPC 405 CRc */
80d11f44 7264 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7265 /* PowerPC 405 EP */
80d11f44 7266 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7267#if defined(TODO)
7268 /* PowerPC 405 EXr */
80d11f44 7269 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7270#endif
7271 /* PowerPC 405 EZ */
80d11f44 7272 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7273#if defined(TODO)
7274 /* PowerPC 405 FX */
80d11f44 7275 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7276#endif
7277 /* PowerPC 405 GP */
80d11f44 7278 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7279 /* PowerPC 405 GPa */
80d11f44 7280 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7281 /* PowerPC 405 GPb */
80d11f44 7282 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7283 /* PowerPC 405 GPc */
80d11f44 7284 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7285 /* PowerPC 405 GPd */
80d11f44 7286 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7287 /* PowerPC 405 GPe */
80d11f44 7288 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7289 /* PowerPC 405 GPR */
80d11f44 7290 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7291#if defined(TODO)
7292 /* PowerPC 405 H */
80d11f44 7293 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7294#endif
7295#if defined(TODO)
7296 /* PowerPC 405 L */
80d11f44 7297 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7298#endif
7299 /* PowerPC 405 LP */
80d11f44 7300 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7301#if defined(TODO)
7302 /* PowerPC 405 PM */
80d11f44 7303 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7304#endif
7305#if defined(TODO)
7306 /* PowerPC 405 PS */
80d11f44 7307 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7308#endif
7309#if defined(TODO)
7310 /* PowerPC 405 S */
80d11f44 7311 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7312#endif
7313 /* Npe405 H */
80d11f44 7314 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7315 /* Npe405 H2 */
80d11f44 7316 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7317 /* Npe405 L */
80d11f44 7318 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7319 /* Npe4GS3 */
80d11f44 7320 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7321#if defined (TODO)
80d11f44 7322 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7323#endif
7324#if defined (TODO)
80d11f44 7325 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7326#endif
7327#if defined (TODO)
7328 /* PowerPC LC77700 (Sanyo) */
80d11f44 7329 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7330#endif
7331 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7332#if defined (TODO)
7333 /* STB010000 */
80d11f44 7334 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7335#endif
7336#if defined (TODO)
7337 /* STB01010 */
80d11f44 7338 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7339#endif
7340#if defined (TODO)
7341 /* STB0210 */
80d11f44 7342 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7343#endif
7344 /* STB03xx */
80d11f44 7345 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7346#if defined (TODO)
7347 /* STB043x */
80d11f44 7348 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7349#endif
7350#if defined (TODO)
7351 /* STB045x */
80d11f44 7352 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7353#endif
7354 /* STB04xx */
80d11f44 7355 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7356 /* STB25xx */
80d11f44 7357 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7358#if defined (TODO)
7359 /* STB130 */
80d11f44 7360 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7361#endif
7362 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7363 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7364 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7365 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7366 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7367#if defined (TODO)
7368 /* Zarlink ZL10310 */
80d11f44 7369 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7370#endif
7371#if defined (TODO)
7372 /* Zarlink ZL10311 */
80d11f44 7373 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7374#endif
7375#if defined (TODO)
7376 /* Zarlink ZL10320 */
80d11f44 7377 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7378#endif
7379#if defined (TODO)
7380 /* Zarlink ZL10321 */
80d11f44 7381 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7382#endif
7383 /* PowerPC 440 family */
80d11f44 7384#if defined(TODO_USER_ONLY)
a750fc0b 7385 /* Generic PowerPC 440 */
80d11f44
JM		 7386 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7387#endif
a750fc0b
JM		 7388 /* PowerPC 440 cores */
7389#if defined (TODO)
7390 /* PowerPC 440 A4 */
80d11f44 7391 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b
JM		 7392#endif
7393#if defined (TODO)
7394 /* PowerPC 440 A5 */
80d11f44 7395 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7396#endif
7397#if defined (TODO)
7398 /* PowerPC 440 B4 */
80d11f44 7399 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7400#endif
7401#if defined (TODO)
7402 /* PowerPC 440 G4 */
80d11f44 7403 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7404#endif
7405#if defined (TODO)
7406 /* PowerPC 440 F5 */
80d11f44 7407 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7408#endif
7409#if defined (TODO)
7410 /* PowerPC 440 G5 */
80d11f44 7411 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7412#endif
7413#if defined (TODO)
7414 /* PowerPC 440H4 */
80d11f44 7415 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7416#endif
7417#if defined (TODO)
7418 /* PowerPC 440H6 */
80d11f44 7419 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7420#endif
7421 /* PowerPC 440 microcontrolers */
80d11f44 7422#if defined(TODO_USER_ONLY)
a750fc0b 7423 /* PowerPC 440 EP */
80d11f44
JM		 7424 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7425#endif
7426#if defined(TODO_USER_ONLY)
a750fc0b 7427 /* PowerPC 440 EPa */
80d11f44
JM		 7428 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7429#endif
7430#if defined(TODO_USER_ONLY)
a750fc0b 7431 /* PowerPC 440 EPb */
80d11f44
JM		 7432 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7433#endif
7434#if defined(TODO_USER_ONLY)
a750fc0b 7435 /* PowerPC 440 EPX */
80d11f44
JM		 7436 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7437#endif
7438#if defined(TODO_USER_ONLY)
a750fc0b 7439 /* PowerPC 440 GP */
80d11f44
JM		 7440 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7441#endif
7442#if defined(TODO_USER_ONLY)
a750fc0b 7443 /* PowerPC 440 GPb */
80d11f44
JM		 7444 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7445#endif
7446#if defined(TODO_USER_ONLY)
a750fc0b 7447 /* PowerPC 440 GPc */
80d11f44
JM		 7448 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7449#endif
7450#if defined(TODO_USER_ONLY)
a750fc0b 7451 /* PowerPC 440 GR */
80d11f44
JM		 7452 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7453#endif
7454#if defined(TODO_USER_ONLY)
a750fc0b 7455 /* PowerPC 440 GRa */
80d11f44
JM		 7456 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7457#endif
7458#if defined(TODO_USER_ONLY)
a750fc0b 7459 /* PowerPC 440 GRX */
80d11f44
JM		 7460 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7461#endif
7462#if defined(TODO_USER_ONLY)
a750fc0b 7463 /* PowerPC 440 GX */
80d11f44
JM		 7464 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7465#endif
7466#if defined(TODO_USER_ONLY)
a750fc0b 7467 /* PowerPC 440 GXa */
80d11f44
JM		 7468 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7469#endif
7470#if defined(TODO_USER_ONLY)
a750fc0b 7471 /* PowerPC 440 GXb */
80d11f44
JM		 7472 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7473#endif
7474#if defined(TODO_USER_ONLY)
a750fc0b 7475 /* PowerPC 440 GXc */
80d11f44
JM		 7476 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7477#endif
7478#if defined(TODO_USER_ONLY)
a750fc0b 7479 /* PowerPC 440 GXf */
80d11f44
JM		 7480 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7481#endif
a750fc0b
JM		 7482#if defined(TODO)
7483 /* PowerPC 440 S */
80d11f44 7484 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7485#endif
80d11f44 7486#if defined(TODO_USER_ONLY)
a750fc0b 7487 /* PowerPC 440 SP */
80d11f44
JM		 7488 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7489#endif
7490#if defined(TODO_USER_ONLY)
a750fc0b 7491 /* PowerPC 440 SP2 */
80d11f44
JM		 7492 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7493#endif
7494#if defined(TODO_USER_ONLY)
a750fc0b 7495 /* PowerPC 440 SPE */
80d11f44
JM		 7496 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7497#endif
a750fc0b
JM		 7498 /* PowerPC 460 family */
7499#if defined (TODO)
7500 /* Generic PowerPC 464 */
80d11f44 7501 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7502#endif
7503 /* PowerPC 464 microcontrolers */
7504#if defined (TODO)
7505 /* PowerPC 464H90 */
80d11f44 7506 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7507#endif
7508#if defined (TODO)
7509 /* PowerPC 464H90F */
80d11f44 7510 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7511#endif
7512 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7513 /* MPC5xx family (aka RCPU) */
7514#if defined(TODO_USER_ONLY)
7515 /* Generic MPC5xx core */
7516 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7517#endif
7518#if defined(TODO_USER_ONLY)
7519 /* Codename for MPC5xx core */
7520 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7521#endif
7522 /* MPC5xx microcontrollers */
7523#if defined(TODO_USER_ONLY)
7524 /* MGT560 */
7525 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7526#endif
7527#if defined(TODO_USER_ONLY)
7528 /* MPC509 */
7529 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7530#endif
7531#if defined(TODO_USER_ONLY)
7532 /* MPC533 */
7533 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7534#endif
7535#if defined(TODO_USER_ONLY)
7536 /* MPC534 */
7537 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7538#endif
7539#if defined(TODO_USER_ONLY)
7540 /* MPC555 */
7541 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7542#endif
7543#if defined(TODO_USER_ONLY)
7544 /* MPC556 */
7545 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7546#endif
7547#if defined(TODO_USER_ONLY)
7548 /* MPC560 */
7549 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7550#endif
7551#if defined(TODO_USER_ONLY)
7552 /* MPC561 */
7553 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7554#endif
7555#if defined(TODO_USER_ONLY)
7556 /* MPC562 */
7557 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7558#endif
7559#if defined(TODO_USER_ONLY)
7560 /* MPC563 */
7561 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7562#endif
7563#if defined(TODO_USER_ONLY)
7564 /* MPC564 */
7565 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7566#endif
7567#if defined(TODO_USER_ONLY)
7568 /* MPC565 */
7569 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7570#endif
7571#if defined(TODO_USER_ONLY)
7572 /* MPC566 */
7573 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7574#endif
7575 /* MPC8xx family (aka PowerQUICC) */
7576#if defined(TODO_USER_ONLY)
7577 /* Generic MPC8xx core */
7578 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7579#endif
7580#if defined(TODO_USER_ONLY)
7581 /* Codename for MPC8xx core */
7582 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7583#endif
7584 /* MPC8xx microcontrollers */
7585#if defined(TODO_USER_ONLY)
7586 /* MGT823 */
7587 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7588#endif
7589#if defined(TODO_USER_ONLY)
7590 /* MPC821 */
7591 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7592#endif
7593#if defined(TODO_USER_ONLY)
7594 /* MPC823 */
7595 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7596#endif
7597#if defined(TODO_USER_ONLY)
7598 /* MPC850 */
7599 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7600#endif
7601#if defined(TODO_USER_ONLY)
7602 /* MPC852T */
7603 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7604#endif
7605#if defined(TODO_USER_ONLY)
7606 /* MPC855T */
7607 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7608#endif
7609#if defined(TODO_USER_ONLY)
7610 /* MPC857 */
7611 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7612#endif
7613#if defined(TODO_USER_ONLY)
7614 /* MPC859 */
7615 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7616#endif
7617#if defined(TODO_USER_ONLY)
7618 /* MPC860 */
7619 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7620#endif
7621#if defined(TODO_USER_ONLY)
7622 /* MPC862 */
7623 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7624#endif
7625#if defined(TODO_USER_ONLY)
7626 /* MPC866 */
7627 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7628#endif
7629#if defined(TODO_USER_ONLY)
7630 /* MPC870 */
7631 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7632#endif
7633#if defined(TODO_USER_ONLY)
7634 /* MPC875 */
7635 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7636#endif
7637#if defined(TODO_USER_ONLY)
7638 /* MPC880 */
7639 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7640#endif
7641#if defined(TODO_USER_ONLY)
7642 /* MPC885 */
7643 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7644#endif
7645 /* MPC82xx family (aka PowerQUICC-II) */
7646 /* Generic MPC52xx core */
7647 POWERPC_DEF_SVR("MPC52xx",
7648 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7649 /* Generic MPC82xx core */
7650 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7651 /* Codename for MPC82xx */
7652 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7653 /* PowerPC G2 core */
7654 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7655 /* PowerPC G2 H4 core */
7656 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7657 /* PowerPC G2 GP core */
7658 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7659 /* PowerPC G2 LS core */
7660 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7661 /* PowerPC G2 HiP3 core */
7662 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7663 /* PowerPC G2 HiP4 core */
7664 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7665 /* PowerPC MPC603 core */
7666 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7667 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7668 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7669 /* PowerPC G2LE GP core */
7670 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7671 /* PowerPC G2LE LS core */
7672 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7673 /* PowerPC G2LE GP1 core */
7674 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7675 /* PowerPC G2LE GP3 core */
7676 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7677 /* PowerPC MPC603 microcontrollers */
7678 /* MPC8240 */
7679 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7680 /* PowerPC G2 microcontrollers */
082c6681 7681#if defined(TODO)
80d11f44
JM		 7682 /* MPC5121 */
7683 POWERPC_DEF_SVR("MPC5121",
7684 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7685#endif
7686 /* MPC5200 */
7687 POWERPC_DEF_SVR("MPC5200",
7688 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7689 /* MPC5200 v1.0 */
7690 POWERPC_DEF_SVR("MPC5200_v10",
7691 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7692 /* MPC5200 v1.1 */
7693 POWERPC_DEF_SVR("MPC5200_v11",
7694 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7695 /* MPC5200 v1.2 */
7696 POWERPC_DEF_SVR("MPC5200_v12",
7697 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7698 /* MPC5200B */
7699 POWERPC_DEF_SVR("MPC5200B",
7700 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7701 /* MPC5200B v2.0 */
7702 POWERPC_DEF_SVR("MPC5200B_v20",
7703 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7704 /* MPC5200B v2.1 */
7705 POWERPC_DEF_SVR("MPC5200B_v21",
7706 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7707 /* MPC8241 */
7708 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7709 /* MPC8245 */
7710 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7711 /* MPC8247 */
7712 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7713 /* MPC8248 */
7714 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7715 /* MPC8250 */
7716 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7717 /* MPC8250 HiP3 */
7718 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7719 /* MPC8250 HiP4 */
7720 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7721 /* MPC8255 */
7722 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7723 /* MPC8255 HiP3 */
7724 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7725 /* MPC8255 HiP4 */
7726 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7727 /* MPC8260 */
7728 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7729 /* MPC8260 HiP3 */
7730 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7731 /* MPC8260 HiP4 */
7732 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7733 /* MPC8264 */
7734 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7735 /* MPC8264 HiP3 */
7736 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7737 /* MPC8264 HiP4 */
7738 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7739 /* MPC8265 */
7740 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7741 /* MPC8265 HiP3 */
7742 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7743 /* MPC8265 HiP4 */
7744 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7745 /* MPC8266 */
7746 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7747 /* MPC8266 HiP3 */
7748 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7749 /* MPC8266 HiP4 */
7750 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7751 /* MPC8270 */
7752 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7753 /* MPC8271 */
7754 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7755 /* MPC8272 */
7756 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7757 /* MPC8275 */
7758 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7759 /* MPC8280 */
7760 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 7761 /* e200 family */
a750fc0b 7762 /* Generic PowerPC e200 core */
80d11f44
JM		 7763 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7764 /* Generic MPC55xx core */
7765#if defined (TODO)
7766 POWERPC_DEF_SVR("MPC55xx",
7767 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 7768#endif
7769#if defined (TODO)
80d11f44
JM		 7770 /* PowerPC e200z0 core */
7771 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 7772#endif
7773#if defined (TODO)
80d11f44
JM		 7774 /* PowerPC e200z1 core */
7775 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7776#endif
7777#if defined (TODO)
7778 /* PowerPC e200z3 core */
7779 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7780#endif
7781 /* PowerPC e200z5 core */
7782 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 7783 /* PowerPC e200z6 core */
80d11f44
JM		 7784 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7785 /* PowerPC e200 microcontrollers */
7786#if defined (TODO)
7787 /* MPC5514E */
7788 POWERPC_DEF_SVR("MPC5514E",
7789 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 7790#endif
a750fc0b 7791#if defined (TODO)
80d11f44
JM		 7792 /* MPC5514E v0 */
7793 POWERPC_DEF_SVR("MPC5514E_v0",
7794 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 7795#endif
7796#if defined (TODO)
80d11f44
JM		 7797 /* MPC5514E v1 */
7798 POWERPC_DEF_SVR("MPC5514E_v1",
7799 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 7800#endif
7801#if defined (TODO)
80d11f44
JM		 7802 /* MPC5514G */
7803 POWERPC_DEF_SVR("MPC5514G",
7804 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 7805#endif
7806#if defined (TODO)
80d11f44
JM		 7807 /* MPC5514G v0 */
7808 POWERPC_DEF_SVR("MPC5514G_v0",
7809 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 7810#endif
a750fc0b 7811#if defined (TODO)
80d11f44
JM		 7812 /* MPC5514G v1 */
7813 POWERPC_DEF_SVR("MPC5514G_v1",
7814 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 7815#endif
7816#if defined (TODO)
80d11f44
JM		 7817 /* MPC5515S */
7818 POWERPC_DEF_SVR("MPC5515S",
7819 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 7820#endif
7821#if defined (TODO)
80d11f44
JM		 7822 /* MPC5516E */
7823 POWERPC_DEF_SVR("MPC5516E",
7824 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 7825#endif
7826#if defined (TODO)
80d11f44
JM		 7827 /* MPC5516E v0 */
7828 POWERPC_DEF_SVR("MPC5516E_v0",
7829 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 7830#endif
7831#if defined (TODO)
80d11f44
JM		 7832 /* MPC5516E v1 */
7833 POWERPC_DEF_SVR("MPC5516E_v1",
7834 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 7835#endif
a750fc0b 7836#if defined (TODO)
80d11f44
JM		 7837 /* MPC5516G */
7838 POWERPC_DEF_SVR("MPC5516G",
7839 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 7840#endif
a750fc0b 7841#if defined (TODO)
80d11f44
JM		 7842 /* MPC5516G v0 */
7843 POWERPC_DEF_SVR("MPC5516G_v0",
7844 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 7845#endif
a750fc0b 7846#if defined (TODO)
80d11f44
JM		 7847 /* MPC5516G v1 */
7848 POWERPC_DEF_SVR("MPC5516G_v1",
7849 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 7850#endif
a750fc0b 7851#if defined (TODO)
80d11f44
JM		 7852 /* MPC5516S */
7853 POWERPC_DEF_SVR("MPC5516S",
7854 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 7855#endif
7856#if defined (TODO)
80d11f44
JM		 7857 /* MPC5533 */
7858 POWERPC_DEF_SVR("MPC5533",
7859 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 7860#endif
7861#if defined (TODO)
80d11f44
JM		 7862 /* MPC5534 */
7863 POWERPC_DEF_SVR("MPC5534",
7864 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 7865#endif
80d11f44
JM		 7866#if defined (TODO)
7867 /* MPC5553 */
7868 POWERPC_DEF_SVR("MPC5553",
7869 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7870#endif
7871#if defined (TODO)
7872 /* MPC5554 */
7873 POWERPC_DEF_SVR("MPC5554",
7874 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7875#endif
7876#if defined (TODO)
7877 /* MPC5561 */
7878 POWERPC_DEF_SVR("MPC5561",
7879 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7880#endif
7881#if defined (TODO)
7882 /* MPC5565 */
7883 POWERPC_DEF_SVR("MPC5565",
7884 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7885#endif
7886#if defined (TODO)
7887 /* MPC5566 */
7888 POWERPC_DEF_SVR("MPC5566",
7889 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7890#endif
7891#if defined (TODO)
7892 /* MPC5567 */
7893 POWERPC_DEF_SVR("MPC5567",
7894 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7895#endif
7896 /* e300 family */
7897 /* Generic PowerPC e300 core */
7898 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7899 /* PowerPC e300c1 core */
7900 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7901 /* PowerPC e300c2 core */
7902 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7903 /* PowerPC e300c3 core */
7904 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7905 /* PowerPC e300c4 core */
7906 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7907 /* PowerPC e300 microcontrollers */
7908#if defined (TODO)
7909 /* MPC8313 */
7910 POWERPC_DEF_SVR("MPC8313",
7911 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
7912#endif
7913#if defined (TODO)
7914 /* MPC8313E */
7915 POWERPC_DEF_SVR("MPC8313E",
7916 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
7917#endif
7918#if defined (TODO)
7919 /* MPC8314 */
7920 POWERPC_DEF_SVR("MPC8314",
7921 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
7922#endif
7923#if defined (TODO)
7924 /* MPC8314E */
7925 POWERPC_DEF_SVR("MPC8314E",
7926 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
7927#endif
7928#if defined (TODO)
7929 /* MPC8315 */
7930 POWERPC_DEF_SVR("MPC8315",
7931 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
7932#endif
7933#if defined (TODO)
7934 /* MPC8315E */
7935 POWERPC_DEF_SVR("MPC8315E",
7936 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
7937#endif
7938#if defined (TODO)
7939 /* MPC8321 */
7940 POWERPC_DEF_SVR("MPC8321",
7941 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
7942#endif
7943#if defined (TODO)
7944 /* MPC8321E */
7945 POWERPC_DEF_SVR("MPC8321E",
7946 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
7947#endif
7948#if defined (TODO)
7949 /* MPC8323 */
7950 POWERPC_DEF_SVR("MPC8323",
7951 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
7952#endif
7953#if defined (TODO)
7954 /* MPC8323E */
7955 POWERPC_DEF_SVR("MPC8323E",
7956 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
7957#endif
7958 /* MPC8343A */
7959 POWERPC_DEF_SVR("MPC8343A",
7960 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
7961 /* MPC8343EA */
7962 POWERPC_DEF_SVR("MPC8343EA",
7963 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
7964 /* MPC8347A */
7965 POWERPC_DEF_SVR("MPC8347A",
7966 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
7967 /* MPC8347AT */
7968 POWERPC_DEF_SVR("MPC8347AT",
7969 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
7970 /* MPC8347AP */
7971 POWERPC_DEF_SVR("MPC8347AP",
7972 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
7973 /* MPC8347EA */
7974 POWERPC_DEF_SVR("MPC8347EA",
7975 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
7976 /* MPC8347EAT */
7977 POWERPC_DEF_SVR("MPC8347EAT",
7978 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
7979 /* MPC8343EAP */
7980 POWERPC_DEF_SVR("MPC8347EAP",
7981 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
7982 /* MPC8349 */
7983 POWERPC_DEF_SVR("MPC8349",
7984 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
7985 /* MPC8349A */
7986 POWERPC_DEF_SVR("MPC8349A",
7987 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
7988 /* MPC8349E */
7989 POWERPC_DEF_SVR("MPC8349E",
7990 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
7991 /* MPC8349EA */
7992 POWERPC_DEF_SVR("MPC8349EA",
7993 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
7994#if defined (TODO)
7995 /* MPC8358E */
7996 POWERPC_DEF_SVR("MPC8358E",
7997 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
7998#endif
7999#if defined (TODO)
8000 /* MPC8360E */
8001 POWERPC_DEF_SVR("MPC8360E",
8002 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
8003#endif
8004 /* MPC8377 */
8005 POWERPC_DEF_SVR("MPC8377",
8006 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
8007 /* MPC8377E */
8008 POWERPC_DEF_SVR("MPC8377E",
8009 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
8010 /* MPC8378 */
8011 POWERPC_DEF_SVR("MPC8378",
8012 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
8013 /* MPC8378E */
8014 POWERPC_DEF_SVR("MPC8378E",
8015 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
8016 /* MPC8379 */
8017 POWERPC_DEF_SVR("MPC8379",
8018 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
8019 /* MPC8379E */
8020 POWERPC_DEF_SVR("MPC8379E",
8021 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
8022 /* e500 family */
8023 /* PowerPC e500 core */
8024 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
8025 /* PowerPC e500 v1.0 core */
8026 POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
8027 /* PowerPC e500 v2.0 core */
8028 POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
8029 /* PowerPC e500v2 core */
8030 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
8031 /* PowerPC e500v2 v1.0 core */
8032 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
8033 /* PowerPC e500v2 v2.0 core */
8034 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
8035 /* PowerPC e500v2 v2.1 core */
8036 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
8037 /* PowerPC e500v2 v2.2 core */
8038 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
8039 /* PowerPC e500v2 v3.0 core */
8040 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
8041 /* PowerPC e500 microcontrollers */
8042 /* MPC8533 */
8043 POWERPC_DEF_SVR("MPC8533",
8044 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
8045 /* MPC8533 v1.0 */
8046 POWERPC_DEF_SVR("MPC8533_v10",
8047 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
8048 /* MPC8533 v1.1 */
8049 POWERPC_DEF_SVR("MPC8533_v11",
8050 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
8051 /* MPC8533E */
8052 POWERPC_DEF_SVR("MPC8533E",
8053 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
8054 /* MPC8533E v1.0 */
8055 POWERPC_DEF_SVR("MPC8533E_v10",
8056 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
8057 POWERPC_DEF_SVR("MPC8533E_v11",
8058 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
8059 /* MPC8540 */
8060 POWERPC_DEF_SVR("MPC8540",
8061 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
8062 /* MPC8540 v1.0 */
8063 POWERPC_DEF_SVR("MPC8540_v10",
8064 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
8065 /* MPC8540 v2.0 */
8066 POWERPC_DEF_SVR("MPC8540_v20",
8067 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
8068 /* MPC8540 v2.1 */
8069 POWERPC_DEF_SVR("MPC8540_v21",
8070 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
8071 /* MPC8541 */
8072 POWERPC_DEF_SVR("MPC8541",
8073 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
8074 /* MPC8541 v1.0 */
8075 POWERPC_DEF_SVR("MPC8541_v10",
8076 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
8077 /* MPC8541 v1.1 */
8078 POWERPC_DEF_SVR("MPC8541_v11",
8079 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
8080 /* MPC8541E */
8081 POWERPC_DEF_SVR("MPC8541E",
8082 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
8083 /* MPC8541E v1.0 */
8084 POWERPC_DEF_SVR("MPC8541E_v10",
8085 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
8086 /* MPC8541E v1.1 */
8087 POWERPC_DEF_SVR("MPC8541E_v11",
8088 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
8089 /* MPC8543 */
8090 POWERPC_DEF_SVR("MPC8543",
8091 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
8092 /* MPC8543 v1.0 */
8093 POWERPC_DEF_SVR("MPC8543_v10",
8094 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
8095 /* MPC8543 v1.1 */
8096 POWERPC_DEF_SVR("MPC8543_v11",
8097 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
8098 /* MPC8543 v2.0 */
8099 POWERPC_DEF_SVR("MPC8543_v20",
8100 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
8101 /* MPC8543 v2.1 */
8102 POWERPC_DEF_SVR("MPC8543_v21",
8103 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
8104 /* MPC8543E */
8105 POWERPC_DEF_SVR("MPC8543E",
8106 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
8107 /* MPC8543E v1.0 */
8108 POWERPC_DEF_SVR("MPC8543E_v10",
8109 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
8110 /* MPC8543E v1.1 */
8111 POWERPC_DEF_SVR("MPC8543E_v11",
8112 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
8113 /* MPC8543E v2.0 */
8114 POWERPC_DEF_SVR("MPC8543E_v20",
8115 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
8116 /* MPC8543E v2.1 */
8117 POWERPC_DEF_SVR("MPC8543E_v21",
8118 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
8119 /* MPC8544 */
8120 POWERPC_DEF_SVR("MPC8544",
8121 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
8122 /* MPC8544 v1.0 */
8123 POWERPC_DEF_SVR("MPC8544_v10",
8124 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
8125 /* MPC8544 v1.1 */
8126 POWERPC_DEF_SVR("MPC8544_v11",
8127 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
8128 /* MPC8544E */
8129 POWERPC_DEF_SVR("MPC8544E",
8130 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
8131 /* MPC8544E v1.0 */
8132 POWERPC_DEF_SVR("MPC8544E_v10",
8133 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
8134 /* MPC8544E v1.1 */
8135 POWERPC_DEF_SVR("MPC8544E_v11",
8136 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
8137 /* MPC8545 */
8138 POWERPC_DEF_SVR("MPC8545",
8139 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
8140 /* MPC8545 v2.0 */
8141 POWERPC_DEF_SVR("MPC8545_v20",
8142 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
8143 /* MPC8545 v2.1 */
8144 POWERPC_DEF_SVR("MPC8545_v21",
8145 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
8146 /* MPC8545E */
8147 POWERPC_DEF_SVR("MPC8545E",
8148 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
8149 /* MPC8545E v2.0 */
8150 POWERPC_DEF_SVR("MPC8545E_v20",
8151 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
8152 /* MPC8545E v2.1 */
8153 POWERPC_DEF_SVR("MPC8545E_v21",
8154 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
8155 /* MPC8547E */
8156 POWERPC_DEF_SVR("MPC8547E",
8157 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
8158 /* MPC8547E v2.0 */
8159 POWERPC_DEF_SVR("MPC8547E_v20",
8160 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
8161 /* MPC8547E v2.1 */
8162 POWERPC_DEF_SVR("MPC8547E_v21",
8163 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
8164 /* MPC8548 */
8165 POWERPC_DEF_SVR("MPC8548",
8166 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
8167 /* MPC8548 v1.0 */
8168 POWERPC_DEF_SVR("MPC8548_v10",
8169 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
8170 /* MPC8548 v1.1 */
8171 POWERPC_DEF_SVR("MPC8548_v11",
8172 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
8173 /* MPC8548 v2.0 */
8174 POWERPC_DEF_SVR("MPC8548_v20",
8175 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
8176 /* MPC8548 v2.1 */
8177 POWERPC_DEF_SVR("MPC8548_v21",
8178 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
8179 /* MPC8548E */
8180 POWERPC_DEF_SVR("MPC8548E",
8181 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
8182 /* MPC8548E v1.0 */
8183 POWERPC_DEF_SVR("MPC8548E_v10",
8184 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
8185 /* MPC8548E v1.1 */
8186 POWERPC_DEF_SVR("MPC8548E_v11",
8187 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
8188 /* MPC8548E v2.0 */
8189 POWERPC_DEF_SVR("MPC8548E_v20",
8190 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
8191 /* MPC8548E v2.1 */
8192 POWERPC_DEF_SVR("MPC8548E_v21",
8193 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
8194 /* MPC8555 */
8195 POWERPC_DEF_SVR("MPC8555",
8196 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
8197 /* MPC8555 v1.0 */
8198 POWERPC_DEF_SVR("MPC8555_v10",
8199 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
8200 /* MPC8555 v1.1 */
8201 POWERPC_DEF_SVR("MPC8555_v11",
8202 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
8203 /* MPC8555E */
8204 POWERPC_DEF_SVR("MPC8555E",
8205 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
8206 /* MPC8555E v1.0 */
8207 POWERPC_DEF_SVR("MPC8555E_v10",
8208 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
8209 /* MPC8555E v1.1 */
8210 POWERPC_DEF_SVR("MPC8555E_v11",
8211 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
8212 /* MPC8560 */
8213 POWERPC_DEF_SVR("MPC8560",
8214 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
8215 /* MPC8560 v1.0 */
8216 POWERPC_DEF_SVR("MPC8560_v10",
8217 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
8218 /* MPC8560 v2.0 */
8219 POWERPC_DEF_SVR("MPC8560_v20",
8220 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
8221 /* MPC8560 v2.1 */
8222 POWERPC_DEF_SVR("MPC8560_v21",
8223 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
8224 /* MPC8567 */
8225 POWERPC_DEF_SVR("MPC8567",
8226 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
8227 /* MPC8567E */
8228 POWERPC_DEF_SVR("MPC8567E",
8229 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
8230 /* MPC8568 */
8231 POWERPC_DEF_SVR("MPC8568",
8232 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
8233 /* MPC8568E */
8234 POWERPC_DEF_SVR("MPC8568E",
8235 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
8236 /* MPC8572 */
8237 POWERPC_DEF_SVR("MPC8572",
8238 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
8239 /* MPC8572E */
8240 POWERPC_DEF_SVR("MPC8572E",
8241 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
8242 /* e600 family */
8243 /* PowerPC e600 core */
8244 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8245 /* PowerPC e600 microcontrollers */
8246#if defined (TODO)
8247 /* MPC8610 */
8248 POWERPC_DEF_SVR("MPC8610",
8249 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8250#endif
8251 /* MPC8641 */
8252 POWERPC_DEF_SVR("MPC8641",
8253 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8254 /* MPC8641D */
8255 POWERPC_DEF_SVR("MPC8641D",
8256 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8257 /* 32 bits "classic" PowerPC */
8258 /* PowerPC 6xx family */
8259 /* PowerPC 601 */
bd928eba 8260 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8261 /* PowerPC 601v0 */
082c6681 8262 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8263 /* PowerPC 601v1 */
082c6681
JM		 8264 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8265 /* PowerPC 601v */
bd928eba 8266 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8267 /* PowerPC 601v2 */
082c6681 8268 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8269 /* PowerPC 602 */
80d11f44 8270 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8271 /* PowerPC 603 */
80d11f44 8272 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8273 /* Code name for PowerPC 603 */
80d11f44 8274 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8275 /* PowerPC 603e (aka PID6) */
80d11f44 8276 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8277 /* Code name for PowerPC 603e */
80d11f44 8278 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8279 /* PowerPC 603e v1.1 */
80d11f44 8280 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8281 /* PowerPC 603e v1.2 */
80d11f44 8282 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8283 /* PowerPC 603e v1.3 */
80d11f44 8284 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8285 /* PowerPC 603e v1.4 */
80d11f44 8286 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8287 /* PowerPC 603e v2.2 */
80d11f44 8288 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8289 /* PowerPC 603e v3 */
80d11f44 8290 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8291 /* PowerPC 603e v4 */
80d11f44 8292 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8293 /* PowerPC 603e v4.1 */
80d11f44 8294 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8295 /* PowerPC 603e (aka PID7) */
80d11f44 8296 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8297 /* PowerPC 603e7t */
80d11f44 8298 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8299 /* PowerPC 603e7v */
80d11f44 8300 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8301 /* Code name for PowerPC 603ev */
80d11f44 8302 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8303 /* PowerPC 603e7v1 */
80d11f44 8304 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8305 /* PowerPC 603e7v2 */
80d11f44 8306 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8307 /* PowerPC 603p (aka PID7v) */
8308 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8309 /* PowerPC 603r (aka PID7t) */
80d11f44 8310 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8311 /* Code name for PowerPC 603r */
80d11f44 8312 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8313 /* PowerPC 604 */
80d11f44 8314 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8315 /* PowerPC 604e (aka PID9) */
8316 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8317 /* Code name for PowerPC 604e */
8318 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8319 /* PowerPC 604e v1.0 */
082c6681 8320 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8321 /* PowerPC 604e v2.2 */
082c6681 8322 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8323 /* PowerPC 604e v2.4 */
082c6681
JM		 8324 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8325 /* PowerPC 604r (aka PIDA) */
8326 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8327 /* Code name for PowerPC 604r */
8328 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8329#if defined(TODO)
8330 /* PowerPC 604ev */
082c6681 8331 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8332#endif
8333 /* PowerPC 7xx family */
8334 /* Generic PowerPC 740 (G3) */
bd928eba 8335 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8336 /* Code name for PowerPC 740 */
bd928eba 8337 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8338 /* Generic PowerPC 750 (G3) */
bd928eba 8339 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8340 /* Code name for PowerPC 750 */
bd928eba 8341 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8342 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8343 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8344 /* PowerPC 740 v1.0 (G3) */
8345 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8346 /* PowerPC 750 v1.0 (G3) */
8347 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8348 /* PowerPC 740 v2.0 (G3) */
bd928eba 8349 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8350 /* PowerPC 750 v2.0 (G3) */
bd928eba 8351 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8352 /* PowerPC 740 v2.1 (G3) */
bd928eba 8353 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8354 /* PowerPC 750 v2.1 (G3) */
bd928eba 8355 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8356 /* PowerPC 740 v2.2 (G3) */
bd928eba 8357 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8358 /* PowerPC 750 v2.2 (G3) */
bd928eba 8359 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8360 /* PowerPC 740 v3.0 (G3) */
bd928eba 8361 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8362 /* PowerPC 750 v3.0 (G3) */
bd928eba 8363 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8364 /* PowerPC 740 v3.1 (G3) */
bd928eba 8365 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8366 /* PowerPC 750 v3.1 (G3) */
bd928eba 8367 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8368 /* PowerPC 740E (G3) */
bd928eba
JM		 8369 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8370 /* PowerPC 750E (G3) */
8371 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8372 /* PowerPC 740P (G3) */
bd928eba 8373 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8374 /* PowerPC 750P (G3) */
bd928eba 8375 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8376 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8377 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8378 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8379 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8380 /* PowerPC 750CL v1.0 */
8381 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8382 /* PowerPC 750CL v2.0 */
8383 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8384 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8385 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8386 /* PowerPC 750CX v1.0 (G3 embedded) */
8387 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8388 /* PowerPC 750CX v2.1 (G3 embedded) */
8389 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8390 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8391 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8392 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8393 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8394 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8395 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8396 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8397 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8398 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8399 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8400 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8401 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8402 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8403 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8404 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8405 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8406 /* PowerPC 750CXe v3.0 (G3 embedded) */
8407 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8408 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8409 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8410 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8411 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8412 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8413 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8414 /* PowerPC 750FL (G3 embedded) */
80d11f44 8415 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8416 /* PowerPC 750FX (G3 embedded) */
80d11f44 8417 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8418 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8419 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8420 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8421 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8422 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8423 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8424 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8425 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8426 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8427 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8428 /* PowerPC 750GL (G3 embedded) */
bd928eba 8429 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8430 /* PowerPC 750GX (G3 embedded) */
bd928eba 8431 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8432 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8433 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8434 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8435 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8436 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8437 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8438 /* PowerPC 750L (G3 embedded) */
bd928eba 8439 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8440 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8441 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8442 /* PowerPC 750L v2.0 (G3 embedded) */
8443 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8444 /* PowerPC 750L v2.1 (G3 embedded) */
8445 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8446 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8447 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8448 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8449 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8450 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8451 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8452 /* Generic PowerPC 745 */
bd928eba 8453 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8454 /* Generic PowerPC 755 */
bd928eba 8455 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8456 /* Code name for PowerPC 745/755 */
bd928eba 8457 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8458 /* PowerPC 745 v1.0 */
bd928eba 8459 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8460 /* PowerPC 755 v1.0 */
bd928eba 8461 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8462 /* PowerPC 745 v1.1 */
bd928eba 8463 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8464 /* PowerPC 755 v1.1 */
bd928eba 8465 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8466 /* PowerPC 745 v2.0 */
bd928eba 8467 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8468 /* PowerPC 755 v2.0 */
bd928eba 8469 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8470 /* PowerPC 745 v2.1 */
bd928eba 8471 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8472 /* PowerPC 755 v2.1 */
bd928eba 8473 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8474 /* PowerPC 745 v2.2 */
bd928eba 8475 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8476 /* PowerPC 755 v2.2 */
bd928eba 8477 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8478 /* PowerPC 745 v2.3 */
bd928eba 8479 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8480 /* PowerPC 755 v2.3 */
bd928eba 8481 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8482 /* PowerPC 745 v2.4 */
bd928eba 8483 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8484 /* PowerPC 755 v2.4 */
bd928eba 8485 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8486 /* PowerPC 745 v2.5 */
bd928eba 8487 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8488 /* PowerPC 755 v2.5 */
bd928eba 8489 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8490 /* PowerPC 745 v2.6 */
bd928eba 8491 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8492 /* PowerPC 755 v2.6 */
bd928eba 8493 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8494 /* PowerPC 745 v2.7 */
bd928eba 8495 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8496 /* PowerPC 755 v2.7 */
bd928eba 8497 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8498 /* PowerPC 745 v2.8 */
bd928eba 8499 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8500 /* PowerPC 755 v2.8 */
bd928eba 8501 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8502#if defined (TODO)
8503 /* PowerPC 745P (G3) */
bd928eba 8504 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8505 /* PowerPC 755P (G3) */
bd928eba 8506 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8507#endif
8508 /* PowerPC 74xx family */
8509 /* PowerPC 7400 (G4) */
80d11f44 8510 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8511 /* Code name for PowerPC 7400 */
80d11f44 8512 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8513 /* PowerPC 74xx is also well known as G4 */
80d11f44 8514 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8515 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8516 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8517 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8518 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8519 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8520 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8521 /* PowerPC 7400 v2.1 (G4) */
8522 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8523 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8524 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8525 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8526 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8527 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8528 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8529 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8530 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8531 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8532 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8533 /* PowerPC 7410 (G4) */
80d11f44 8534 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8535 /* Code name for PowerPC 7410 */
80d11f44 8536 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8537 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8538 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8539 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8540 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8541 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8542 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8543 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8544 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8545 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8546 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8547 /* PowerPC 7448 (G4) */
80d11f44 8548 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8549 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8550 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8551 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8552 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8553 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8554 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8555 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8556 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8557 /* PowerPC 7450 (G4) */
80d11f44 8558 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8559 /* Code name for PowerPC 7450 */
80d11f44 8560 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8561 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8562 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8563 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8564 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8565 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8566 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8567 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8568 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8569 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8570 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8571 /* PowerPC 7441 (G4) */
80d11f44 8572 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8573 /* PowerPC 7451 (G4) */
80d11f44 8574 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8575 /* PowerPC 7441 v2.1 (G4) */
8576 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8577 /* PowerPC 7441 v2.3 (G4) */
8578 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8579 /* PowerPC 7451 v2.3 (G4) */
8580 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8581 /* PowerPC 7441 v2.10 (G4) */
8582 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8583 /* PowerPC 7451 v2.10 (G4) */
8584 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8585 /* PowerPC 7445 (G4) */
80d11f44 8586 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8587 /* PowerPC 7455 (G4) */
80d11f44 8588 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8589 /* Code name for PowerPC 7445/7455 */
80d11f44 8590 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8591 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8592 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8593 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8594 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8595 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8596 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8597 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8598 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8599 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8600 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8601 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8602 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8603 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8604 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8605 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8606 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8607 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8608 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8609 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8610 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8611 /* PowerPC 7447 (G4) */
80d11f44 8612 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8613 /* PowerPC 7457 (G4) */
80d11f44 8614 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 8615 /* Code name for PowerPC 7447/7457 */
80d11f44 8616 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 8617 /* PowerPC 7447 v1.0 (G4) */
80d11f44 8618 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 8619 /* PowerPC 7457 v1.0 (G4) */
80d11f44 8620 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 8621 /* PowerPC 7447 v1.1 (G4) */
80d11f44 8622 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 8623 /* PowerPC 7457 v1.1 (G4) */
80d11f44 8624 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 8625 /* PowerPC 7457 v1.2 (G4) */
80d11f44 8626 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 8627 /* PowerPC 7447A (G4) */
8628 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8629 /* PowerPC 7457A (G4) */
8630 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8631 /* PowerPC 7447A v1.0 (G4) */
8632 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8633 /* PowerPC 7457A v1.0 (G4) */
8634 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8635 /* Code name for PowerPC 7447A/7457A */
8636 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8637 /* PowerPC 7447A v1.1 (G4) */
8638 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8639 /* PowerPC 7457A v1.1 (G4) */
8640 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8641 /* PowerPC 7447A v1.2 (G4) */
8642 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8643 /* PowerPC 7457A v1.2 (G4) */
8644 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 8645 /* 64 bits PowerPC */
8646#if defined (TARGET_PPC64)
a750fc0b 8647 /* PowerPC 620 */
80d11f44 8648 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 8649 /* Code name for PowerPC 620 */
8650 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 8651#if defined (TODO)
a750fc0b 8652 /* PowerPC 630 (POWER3) */
80d11f44
JM		 8653 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8654 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 8655 /* Code names for POWER3 */
8656 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8657 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 8658#endif
3a607854 8659#if defined (TODO)
a750fc0b 8660 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 8661 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8662 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 8663#endif
8664#if defined (TODO)
a750fc0b 8665 /* POWER4 */
80d11f44 8666 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 8667#endif
3a607854 8668#if defined (TODO)
a750fc0b 8669 /* POWER4p */
80d11f44 8670 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 8671#endif
2662a059 8672#if defined (TODO)
a750fc0b 8673 /* POWER5 */
80d11f44 8674 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 8675 /* POWER5GR */
80d11f44 8676 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 8677#endif
3a607854 8678#if defined (TODO)
a750fc0b 8679 /* POWER5+ */
80d11f44 8680 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 8681 /* POWER5GS */
80d11f44 8682 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 8683#endif
2662a059 8684#if defined (TODO)
a750fc0b 8685 /* POWER6 */
80d11f44 8686 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 8687 /* POWER6 running in POWER5 mode */
80d11f44 8688 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 8689 /* POWER6A */
80d11f44 8690 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 8691#endif
a750fc0b 8692 /* PowerPC 970 */
80d11f44 8693 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 8694 /* PowerPC 970FX (G5) */
80d11f44 8695 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 8696 /* PowerPC 970FX v1.0 (G5) */
80d11f44 8697 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 8698 /* PowerPC 970FX v2.0 (G5) */
80d11f44 8699 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 8700 /* PowerPC 970FX v2.1 (G5) */
80d11f44 8701 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 8702 /* PowerPC 970FX v3.0 (G5) */
80d11f44 8703 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 8704 /* PowerPC 970FX v3.1 (G5) */
80d11f44 8705 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 8706 /* PowerPC 970GX (G5) */
80d11f44 8707 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 8708 /* PowerPC 970MP */
80d11f44 8709 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 8710 /* PowerPC 970MP v1.0 */
80d11f44 8711 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 8712 /* PowerPC 970MP v1.1 */
80d11f44 8713 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 8714#if defined (TODO)
a750fc0b 8715 /* PowerPC Cell */
80d11f44 8716 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 8717#endif
8718#if defined (TODO)
a750fc0b 8719 /* PowerPC Cell v1.0 */
80d11f44 8720 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 8721#endif
8722#if defined (TODO)
a750fc0b 8723 /* PowerPC Cell v2.0 */
80d11f44 8724 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 8725#endif
8726#if defined (TODO)
a750fc0b 8727 /* PowerPC Cell v3.0 */
80d11f44 8728 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 8729#endif
3a607854 8730#if defined (TODO)
a750fc0b 8731 /* PowerPC Cell v3.1 */
80d11f44 8732 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 8733#endif
8734#if defined (TODO)
a750fc0b 8735 /* PowerPC Cell v3.2 */
80d11f44 8736 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 8737#endif
8738#if defined (TODO)
a750fc0b
JM		 8739 /* RS64 (Apache/A35) */
8740 /* This one seems to support the whole POWER2 instruction set
8741 * and the PowerPC 64 one.
8742 */
8743 /* What about A10 & A30 ? */
80d11f44
JM		 8744 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8745 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8746 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 8747#endif
8748#if defined (TODO)
a750fc0b 8749 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 8750 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8751 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8752 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 8753#endif
8754#if defined (TODO)
a750fc0b 8755 /* RS64-III (Pulsar) */
80d11f44
JM		 8756 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8757 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 8758#endif
8759#if defined (TODO)
a750fc0b 8760 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 8761 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8762 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8763 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8764 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 8765#endif
a750fc0b
JM		 8766#endif /* defined (TARGET_PPC64) */
8767 /* POWER */
3fc6c082 8768#if defined (TODO)
a750fc0b 8769 /* Original POWER */
80d11f44
JM		 8770 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8771 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8772 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8773 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8774 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 8775#endif
8776#if defined (TODO)
a750fc0b 8777 /* POWER2 */
80d11f44
JM		 8778 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8779 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8780 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 8781#endif
8782 /* PA semi cores */
8783#if defined (TODO)
8784 /* PA PA6T */
80d11f44 8785 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 8786#endif
8787 /* Generic PowerPCs */
8788#if defined (TARGET_PPC64)
80d11f44 8789 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 8790#endif
80d11f44
JM		 8791 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8792 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 8793 /* Fallback */
80d11f44 8794 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 8795};
8796
8797/*****************************************************************************/
8798/* Generic CPU instanciation routine */
aaed909a 8799static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 8800{
8801#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 8802 int i;
8803
a750fc0b 8804 env->irq_inputs = NULL;
e1833e1f
JM		 8805 /* Set all exception vectors to an invalid address */
8806 for (i = 0; i < POWERPC_EXCP_NB; i++)
8807 env->excp_vectors[i] = (target_ulong)(-1ULL);
8808 env->excp_prefix = 0x00000000;
8809 env->ivor_mask = 0x00000000;
8810 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 8811 /* Default MMU definitions */
8812 env->nb_BATs = 0;
8813 env->nb_tlb = 0;
8814 env->nb_ways = 0;
f2e63a42 8815#endif
a750fc0b
JM		 8816 /* Register SPR common to all PowerPC implementations */
8817 gen_spr_generic(env);
8818 spr_register(env, SPR_PVR, "PVR",
8819 SPR_NOACCESS, SPR_NOACCESS,
8820 &spr_read_generic, SPR_NOACCESS,
8821 def->pvr);
80d11f44
JM		 8822 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8823 if (def->svr != POWERPC_SVR_NONE) {
8824 if (def->svr & POWERPC_SVR_E500) {
8825 spr_register(env, SPR_E500_SVR, "SVR",
8826 SPR_NOACCESS, SPR_NOACCESS,
8827 &spr_read_generic, SPR_NOACCESS,
8828 def->svr & ~POWERPC_SVR_E500);
8829 } else {
8830 spr_register(env, SPR_SVR, "SVR",
8831 SPR_NOACCESS, SPR_NOACCESS,
8832 &spr_read_generic, SPR_NOACCESS,
8833 def->svr);
8834 }
8835 }
a750fc0b
JM		 8836 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8837 (*def->init_proc)(env);
25ba3a68
JM		 8838 /* MSR bits & flags consistency checks */
8839 if (env->msr_mask & (1 << 25)) {
8840 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8841 case POWERPC_FLAG_SPE:
8842 case POWERPC_FLAG_VRE:
8843 break;
8844 default:
8845 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8846 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8847 exit(1);
8848 }
8849 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8850 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8851 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8852 exit(1);
8853 }
8854 if (env->msr_mask & (1 << 17)) {
8855 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8856 case POWERPC_FLAG_TGPR:
8857 case POWERPC_FLAG_CE:
8858 break;
8859 default:
8860 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8861 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8862 exit(1);
8863 }
8864 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8865 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8866 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8867 exit(1);
8868 }
8869 if (env->msr_mask & (1 << 10)) {
8870 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8871 POWERPC_FLAG_UBLE)) {
8872 case POWERPC_FLAG_SE:
8873 case POWERPC_FLAG_DWE:
8874 case POWERPC_FLAG_UBLE:
8875 break;
8876 default:
8877 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8878 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8879 "POWERPC_FLAG_UBLE\n");
8880 exit(1);
8881 }
8882 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8883 POWERPC_FLAG_UBLE)) {
8884 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8885 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8886 "POWERPC_FLAG_UBLE\n");
8887 exit(1);
8888 }
8889 if (env->msr_mask & (1 << 9)) {
8890 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8891 case POWERPC_FLAG_BE:
8892 case POWERPC_FLAG_DE:
8893 break;
8894 default:
8895 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8896 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8897 exit(1);
8898 }
8899 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8900 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8901 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8902 exit(1);
8903 }
8904 if (env->msr_mask & (1 << 2)) {
8905 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8906 case POWERPC_FLAG_PX:
8907 case POWERPC_FLAG_PMM:
8908 break;
8909 default:
8910 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8911 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8912 exit(1);
8913 }
8914 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8915 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8916 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8917 exit(1);
8918 }
4018bae9
JM		 8919 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8920 fprintf(stderr, "PowerPC flags inconsistency\n"
8921 "Should define the time-base and decrementer clock source\n");
8922 exit(1);
8923 }
a750fc0b 8924 /* Allocate TLBs buffer when needed */
f2e63a42 8925#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 8926 if (env->nb_tlb != 0) {
8927 int nb_tlb = env->nb_tlb;
8928 if (env->id_tlbs != 0)
8929 nb_tlb *= 2;
8930 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8931 /* Pre-compute some useful values */
8932 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8933 }
a750fc0b
JM		 8934 if (env->irq_inputs == NULL) {
8935 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8936 " Attempt Qemu to crash very soon !\n");
8937 }
8938#endif
2f462816
JM		 8939 if (env->check_pow == NULL) {
8940 fprintf(stderr, "WARNING: no power management check handler "
8941 "registered.\n"
8942 " Attempt Qemu to crash very soon !\n");
8943 }
a750fc0b
JM		 8944}
8945
8946#if defined(PPC_DUMP_CPU)
8947static void dump_ppc_sprs (CPUPPCState *env)
8948{
8949 ppc_spr_t *spr;
8950#if !defined(CONFIG_USER_ONLY)
8951 uint32_t sr, sw;
8952#endif
8953 uint32_t ur, uw;
8954 int i, j, n;
8955
8956 printf("Special purpose registers:\n");
8957 for (i = 0; i < 32; i++) {
8958 for (j = 0; j < 32; j++) {
8959 n = (i << 5) | j;
8960 spr = &env->spr_cb[n];
8961 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8962 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8963#if !defined(CONFIG_USER_ONLY)
8964 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8965 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8966 if (sw || sr || uw || ur) {
8967 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8968 (i << 5) | j, (i << 5) | j, spr->name,
8969 sw ? 'w' : '-', sr ? 'r' : '-',
8970 uw ? 'w' : '-', ur ? 'r' : '-');
8971 }
8972#else
8973 if (uw || ur) {
8974 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8975 (i << 5) | j, (i << 5) | j, spr->name,
8976 uw ? 'w' : '-', ur ? 'r' : '-');
8977 }
8978#endif
8979 }
8980 }
8981 fflush(stdout);
8982 fflush(stderr);
8983}
8984#endif
8985
8986/*****************************************************************************/
8987#include <stdlib.h>
8988#include <string.h>
8989
a750fc0b
JM		 8990/* Opcode types */
8991enum {
8992 PPC_DIRECT = 0, /* Opcode routine */
8993 PPC_INDIRECT = 1, /* Indirect opcode table */
8994};
8995
8996static inline int is_indirect_opcode (void *handler)
8997{
8998 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
8999}
9000
9001static inline opc_handler_t **ind_table(void *handler)
9002{
9003 return (opc_handler_t **)((unsigned long)handler & ~3);
9004}
9005
9006/* Instruction table creation */
9007/* Opcodes tables creation */
9008static void fill_new_table (opc_handler_t **table, int len)
9009{
9010 int i;
9011
9012 for (i = 0; i < len; i++)
9013 table[i] = &invalid_handler;
9014}
9015
9016static int create_new_table (opc_handler_t **table, unsigned char idx)
9017{
9018 opc_handler_t **tmp;
9019
9020 tmp = malloc(0x20 * sizeof(opc_handler_t));
9021 if (tmp == NULL)
9022 return -1;
9023 fill_new_table(tmp, 0x20);
9024 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9025
9026 return 0;
9027}
9028
9029static int insert_in_table (opc_handler_t **table, unsigned char idx,
9030 opc_handler_t *handler)
9031{
9032 if (table[idx] != &invalid_handler)
9033 return -1;
9034 table[idx] = handler;
9035
9036 return 0;
9037}
9038
9039static int register_direct_insn (opc_handler_t **ppc_opcodes,
9040 unsigned char idx, opc_handler_t *handler)
9041{
9042 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9043 printf("*** ERROR: opcode %02x already assigned in main "
9044 "opcode table\n", idx);
4c1b1bfe
JM		 9045#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9046 printf(" Registered handler '%s' - new handler '%s'\n",
9047 ppc_opcodes[idx]->oname, handler->oname);
9048#endif
a750fc0b
JM		 9049 return -1;
9050 }
9051
9052 return 0;
9053}
9054
9055static int register_ind_in_table (opc_handler_t **table,
9056 unsigned char idx1, unsigned char idx2,
9057 opc_handler_t *handler)
9058{
9059 if (table[idx1] == &invalid_handler) {
9060 if (create_new_table(table, idx1) < 0) {
9061 printf("*** ERROR: unable to create indirect table "
9062 "idx=%02x\n", idx1);
9063 return -1;
9064 }
9065 } else {
9066 if (!is_indirect_opcode(table[idx1])) {
9067 printf("*** ERROR: idx %02x already assigned to a direct "
9068 "opcode\n", idx1);
4c1b1bfe
JM		 9069#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9070 printf(" Registered handler '%s' - new handler '%s'\n",
9071 ind_table(table[idx1])[idx2]->oname, handler->oname);
9072#endif
a750fc0b
JM		 9073 return -1;
9074 }
3a607854 9075 }
a750fc0b
JM		 9076 if (handler != NULL &&
9077 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9078 printf("*** ERROR: opcode %02x already assigned in "
9079 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9080#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9081 printf(" Registered handler '%s' - new handler '%s'\n",
9082 ind_table(table[idx1])[idx2]->oname, handler->oname);
9083#endif
a750fc0b 9084 return -1;
3a607854 9085 }
a750fc0b
JM		 9086
9087 return 0;
9088}
9089
9090static int register_ind_insn (opc_handler_t **ppc_opcodes,
9091 unsigned char idx1, unsigned char idx2,
9092 opc_handler_t *handler)
9093{
9094 int ret;
9095
9096 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9097
9098 return ret;
9099}
9100
9101static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9102 unsigned char idx1, unsigned char idx2,
9103 unsigned char idx3, opc_handler_t *handler)
9104{
9105 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9106 printf("*** ERROR: unable to join indirect table idx "
9107 "[%02x-%02x]\n", idx1, idx2);
9108 return -1;
9109 }
9110 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9111 handler) < 0) {
9112 printf("*** ERROR: unable to insert opcode "
9113 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9114 return -1;
9115 }
9116
9117 return 0;
9118}
9119
9120static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9121{
9122 if (insn->opc2 != 0xFF) {
9123 if (insn->opc3 != 0xFF) {
9124 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9125 insn->opc3, &insn->handler) < 0)
9126 return -1;
9127 } else {
9128 if (register_ind_insn(ppc_opcodes, insn->opc1,
9129 insn->opc2, &insn->handler) < 0)
9130 return -1;
9131 }
9132 } else {
9133 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9134 return -1;
9135 }
9136
9137 return 0;
9138}
9139
9140static int test_opcode_table (opc_handler_t **table, int len)
9141{
9142 int i, count, tmp;
9143
9144 for (i = 0, count = 0; i < len; i++) {
9145 /* Consistency fixup */
9146 if (table[i] == NULL)
9147 table[i] = &invalid_handler;
9148 if (table[i] != &invalid_handler) {
9149 if (is_indirect_opcode(table[i])) {
9150 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9151 if (tmp == 0) {
9152 free(table[i]);
9153 table[i] = &invalid_handler;
9154 } else {
9155 count++;
9156 }
9157 } else {
9158 count++;
9159 }
9160 }
9161 }
9162
9163 return count;
9164}
9165
9166static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9167{
9168 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9169 printf("*** WARNING: no opcode defined !\n");
9170}
9171
9172/*****************************************************************************/
aaed909a 9173static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9174{
9175 opcode_t *opc, *start, *end;
9176
9177 fill_new_table(env->opcodes, 0x40);
9178 if (&opc_start < &opc_end) {
9179 start = &opc_start;
9180 end = &opc_end;
9181 } else {
9182 start = &opc_end;
9183 end = &opc_start;
9184 }
9185 for (opc = start + 1; opc != end; opc++) {
9186 if ((opc->handler.type & def->insns_flags) != 0) {
9187 if (register_insn(env->opcodes, opc) < 0) {
9188 printf("*** ERROR initializing PowerPC instruction "
9189 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9190 opc->opc3);
9191 return -1;
9192 }
9193 }
9194 }
9195 fix_opcode_tables(env->opcodes);
9196 fflush(stdout);
9197 fflush(stderr);
9198
9199 return 0;
9200}
9201
9202#if defined(PPC_DUMP_CPU)
25ba3a68 9203static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 9204{
9205 opc_handler_t **table, *handler;
b55266b5 9206 const char *p, *q;
a750fc0b
JM		 9207 uint8_t opc1, opc2, opc3;
9208
9209 printf("Instructions set:\n");
9210 /* opc1 is 6 bits long */
9211 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9212 table = env->opcodes;
9213 handler = table[opc1];
9214 if (is_indirect_opcode(handler)) {
9215 /* opc2 is 5 bits long */
9216 for (opc2 = 0; opc2 < 0x20; opc2++) {
9217 table = env->opcodes;
9218 handler = env->opcodes[opc1];
9219 table = ind_table(handler);
9220 handler = table[opc2];
9221 if (is_indirect_opcode(handler)) {
9222 table = ind_table(handler);
9223 /* opc3 is 5 bits long */
9224 for (opc3 = 0; opc3 < 0x20; opc3++) {
9225 handler = table[opc3];
9226 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9227 /* Special hack to properly dump SPE insns */
9228 p = strchr(handler->oname, '_');
9229 if (p == NULL) {
9230 printf("INSN: %02x %02x %02x (%02d %04d) : "
9231 "%s\n",
9232 opc1, opc2, opc3, opc1,
9233 (opc3 << 5) | opc2,
9234 handler->oname);
9235 } else {
9236 q = "speundef";
9237 if ((p - handler->oname) != strlen(q) ||
9238 memcmp(handler->oname, q, strlen(q)) != 0) {
9239 /* First instruction */
9240 printf("INSN: %02x %02x %02x (%02d %04d) : "
9241 "%.*s\n",
9242 opc1, opc2 << 1, opc3, opc1,
9243 (opc3 << 6) | (opc2 << 1),
9244 (int)(p - handler->oname),
9245 handler->oname);
9246 }
9247 if (strcmp(p + 1, q) != 0) {
9248 /* Second instruction */
9249 printf("INSN: %02x %02x %02x (%02d %04d) : "
9250 "%s\n",
9251 opc1, (opc2 << 1) | 1, opc3, opc1,
9252 (opc3 << 6) | (opc2 << 1) | 1,
9253 p + 1);
9254 }
9255 }
a750fc0b
JM		 9256 }
9257 }
9258 } else {
9259 if (handler->handler != &gen_invalid) {
9260 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9261 opc1, opc2, opc1, opc2, handler->oname);
9262 }
9263 }
9264 }
9265 } else {
9266 if (handler->handler != &gen_invalid) {
9267 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9268 opc1, opc1, handler->oname);
9269 }
9270 }
9271 }
9272}
3a607854 9273#endif
a750fc0b 9274
24951522
AJ		 9275static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9276{
9277 if (n < 32) {
9278 stfq_p(mem_buf, env->fpr[n]);
9279 return 8;
9280 }
9281 if (n == 32) {
9282 /* FPSCR not implemented */
9283 memset(mem_buf, 0, 4);
9284 return 4;
9285 }
9286 return 0;
9287}
9288
9289static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9290{
9291 if (n < 32) {
9292 env->fpr[n] = ldfq_p(mem_buf);
9293 return 8;
9294 }
9295 if (n == 32) {
9296 /* FPSCR not implemented */
9297 return 4;
9298 }
9299 return 0;
9300}
9301
b4f8d821
AJ		 9302static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9303{
9304 if (n < 32) {
9305#ifdef WORDS_BIGENDIAN
9306 stq_p(mem_buf, env->avr[n].u64[0]);
9307 stq_p(mem_buf+8, env->avr[n].u64[1]);
9308#else
9309 stq_p(mem_buf, env->avr[n].u64[1]);
9310 stq_p(mem_buf+8, env->avr[n].u64[0]);
9311#endif
9312 return 16;
9313 }
9314 if (n == 33) {
9315 stl_p(mem_buf, env->vscr);
9316 return 4;
9317 }
9318 if (n == 34) {
9319 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9320 return 4;
9321 }
9322 return 0;
9323}
9324
9325static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9326{
9327 if (n < 32) {
9328#ifdef WORDS_BIGENDIAN
9329 env->avr[n].u64[0] = ldq_p(mem_buf);
9330 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9331#else
9332 env->avr[n].u64[1] = ldq_p(mem_buf);
9333 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9334#endif
9335 return 16;
9336 }
9337 if (n == 33) {
9338 env->vscr = ldl_p(mem_buf);
9339 return 4;
9340 }
9341 if (n == 34) {
9342 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9343 return 4;
9344 }
9345 return 0;
9346}
9347
aaed909a 9348int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9349{
9350 env->msr_mask = def->msr_mask;
9351 env->mmu_model = def->mmu_model;
9352 env->excp_model = def->excp_model;
9353 env->bus_model = def->bus_model;
d26bfc9a 9354 env->flags = def->flags;
237c0af0 9355 env->bfd_mach = def->bfd_mach;
2f462816 9356 env->check_pow = def->check_pow;
a750fc0b
JM		 9357 if (create_ppc_opcodes(env, def) < 0)
9358 return -1;
9359 init_ppc_proc(env, def);
24951522
AJ		 9360
9361 if (def->insns_flags & PPC_FLOAT) {
9362 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9363 33, "power-fpu.xml", 0);
9364 }
b4f8d821
AJ		 9365 if (def->insns_flags & PPC_ALTIVEC) {
9366 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9367 34, "power-altivec.xml", 0);
9368 }
a750fc0b 9369#if defined(PPC_DUMP_CPU)
3a607854 9370 {
b55266b5 9371 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9372 switch (env->mmu_model) {
9373 case POWERPC_MMU_32B:
9374 mmu_model = "PowerPC 32";
9375 break;
a750fc0b
JM		 9376 case POWERPC_MMU_SOFT_6xx:
9377 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9378 break;
9379 case POWERPC_MMU_SOFT_74xx:
9380 mmu_model = "PowerPC 74xx with software driven TLBs";
9381 break;
9382 case POWERPC_MMU_SOFT_4xx:
9383 mmu_model = "PowerPC 4xx with software driven TLBs";
9384 break;
9385 case POWERPC_MMU_SOFT_4xx_Z:
9386 mmu_model = "PowerPC 4xx with software driven TLBs "
9387 "and zones protections";
9388 break;
b4095fed
JM		 9389 case POWERPC_MMU_REAL:
9390 mmu_model = "PowerPC real mode only";
9391 break;
9392 case POWERPC_MMU_MPC8xx:
9393 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9394 break;
9395 case POWERPC_MMU_BOOKE:
9396 mmu_model = "PowerPC BookE";
9397 break;
9398 case POWERPC_MMU_BOOKE_FSL:
9399 mmu_model = "PowerPC BookE FSL";
9400 break;
b4095fed
JM		 9401 case POWERPC_MMU_601:
9402 mmu_model = "PowerPC 601";
9403 break;
00af685f
JM		 9404#if defined (TARGET_PPC64)
9405 case POWERPC_MMU_64B:
9406 mmu_model = "PowerPC 64";
9407 break;
add78955
JM		 9408 case POWERPC_MMU_620:
9409 mmu_model = "PowerPC 620";
9410 break;
00af685f 9411#endif
a750fc0b
JM		 9412 default:
9413 mmu_model = "Unknown or invalid";
9414 break;
9415 }
9416 switch (env->excp_model) {
9417 case POWERPC_EXCP_STD:
9418 excp_model = "PowerPC";
9419 break;
9420 case POWERPC_EXCP_40x:
9421 excp_model = "PowerPC 40x";
9422 break;
9423 case POWERPC_EXCP_601:
9424 excp_model = "PowerPC 601";
9425 break;
9426 case POWERPC_EXCP_602:
9427 excp_model = "PowerPC 602";
9428 break;
9429 case POWERPC_EXCP_603:
9430 excp_model = "PowerPC 603";
9431 break;
9432 case POWERPC_EXCP_603E:
9433 excp_model = "PowerPC 603e";
9434 break;
9435 case POWERPC_EXCP_604:
9436 excp_model = "PowerPC 604";
9437 break;
9438 case POWERPC_EXCP_7x0:
9439 excp_model = "PowerPC 740/750";
9440 break;
9441 case POWERPC_EXCP_7x5:
9442 excp_model = "PowerPC 745/755";
9443 break;
9444 case POWERPC_EXCP_74xx:
9445 excp_model = "PowerPC 74xx";
9446 break;
a750fc0b
JM		 9447 case POWERPC_EXCP_BOOKE:
9448 excp_model = "PowerPC BookE";
9449 break;
00af685f
JM		 9450#if defined (TARGET_PPC64)
9451 case POWERPC_EXCP_970:
9452 excp_model = "PowerPC 970";
9453 break;
9454#endif
a750fc0b
JM		 9455 default:
9456 excp_model = "Unknown or invalid";
9457 break;
9458 }
9459 switch (env->bus_model) {
9460 case PPC_FLAGS_INPUT_6xx:
9461 bus_model = "PowerPC 6xx";
9462 break;
9463 case PPC_FLAGS_INPUT_BookE:
9464 bus_model = "PowerPC BookE";
9465 break;
9466 case PPC_FLAGS_INPUT_405:
9467 bus_model = "PowerPC 405";
9468 break;
a750fc0b
JM		 9469 case PPC_FLAGS_INPUT_401:
9470 bus_model = "PowerPC 401/403";
9471 break;
b4095fed
JM		 9472 case PPC_FLAGS_INPUT_RCPU:
9473 bus_model = "RCPU / MPC8xx";
9474 break;
00af685f
JM		 9475#if defined (TARGET_PPC64)
9476 case PPC_FLAGS_INPUT_970:
9477 bus_model = "PowerPC 970";
9478 break;
9479#endif
a750fc0b
JM		 9480 default:
9481 bus_model = "Unknown or invalid";
9482 break;
9483 }
9484 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9485 " MMU model : %s\n",
9486 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9487#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9488 if (env->tlb != NULL) {
9489 printf(" %d %s TLB in %d ways\n",
9490 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9491 env->nb_ways);
9492 }
f2e63a42 9493#endif
a750fc0b
JM		 9494 printf(" Exceptions model : %s\n"
9495 " Bus model : %s\n",
9496 excp_model, bus_model);
25ba3a68
JM		 9497 printf(" MSR features :\n");
9498 if (env->flags & POWERPC_FLAG_SPE)
9499 printf(" signal processing engine enable"
9500 "\n");
9501 else if (env->flags & POWERPC_FLAG_VRE)
9502 printf(" vector processor enable\n");
9503 if (env->flags & POWERPC_FLAG_TGPR)
9504 printf(" temporary GPRs\n");
9505 else if (env->flags & POWERPC_FLAG_CE)
9506 printf(" critical input enable\n");
9507 if (env->flags & POWERPC_FLAG_SE)
9508 printf(" single-step trace mode\n");
9509 else if (env->flags & POWERPC_FLAG_DWE)
9510 printf(" debug wait enable\n");
9511 else if (env->flags & POWERPC_FLAG_UBLE)
9512 printf(" user BTB lock enable\n");
9513 if (env->flags & POWERPC_FLAG_BE)
9514 printf(" branch-step trace mode\n");
9515 else if (env->flags & POWERPC_FLAG_DE)
9516 printf(" debug interrupt enable\n");
9517 if (env->flags & POWERPC_FLAG_PX)
9518 printf(" inclusive protection\n");
9519 else if (env->flags & POWERPC_FLAG_PMM)
9520 printf(" performance monitor mark\n");
9521 if (env->flags == POWERPC_FLAG_NONE)
9522 printf(" none\n");
4018bae9
JM		 9523 printf(" Time-base/decrementer clock source: %s\n",
9524 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9525 }
9526 dump_ppc_insns(env);
9527 dump_ppc_sprs(env);
9528 fflush(stdout);
3a607854 9529#endif
a750fc0b
JM		 9530
9531 return 0;
9532}
3fc6c082 9533
ee4e83ed 9534static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9535{
ee4e83ed
JM		 9536 const ppc_def_t *ret;
9537 uint32_t pvr_rev;
9538 int i, best, match, best_match, max;
3fc6c082 9539
ee4e83ed 9540 ret = NULL;
b1503cda 9541 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9542 best = -1;
9543 pvr_rev = pvr & 0xFFFF;
9544 /* We want all specified bits to match */
9545 best_match = 32 - ctz32(pvr_rev);
068abdc8 9546 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9547 /* We check that the 16 higher bits are the same to ensure the CPU
9548 * model will be the choosen one.
9549 */
9550 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9551 /* We want as much as possible of the low-level 16 bits
9552 * to be the same but we allow inexact matches.
9553 */
9554 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9555 /* We check '>=' instead of '>' because the PPC_defs table
9556 * is ordered by increasing revision.
4c1b1bfe 9557 * Then, we will match the higher revision compatible
ee4e83ed
JM		 9558 * with the requested PVR
9559 */
9560 if (match >= best_match) {
9561 best = i;
9562 best_match = match;
9563 }
3fc6c082
FB		 9564 }
9565 }
ee4e83ed
JM		 9566 if (best != -1)
9567 ret = &ppc_defs[best];
9568
9569 return ret;
3fc6c082
FB		 9570}
9571
ee4e83ed 9572#include <ctype.h>
3fc6c082 9573
b55266b5 9574const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed
JM		 9575{
9576 const ppc_def_t *ret;
b55266b5 9577 const char *p;
ee4e83ed
JM		 9578 int i, max, len;
9579
9580 /* Check if the given name is a PVR */
9581 len = strlen(name);
9582 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9583 p = name + 2;
9584 goto check_pvr;
9585 } else if (len == 8) {
9586 p = name;
9587 check_pvr:
9588 for (i = 0; i < 8; i++) {
cd390083 9589 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 9590 break;
9591 }
9592 if (i == 8)
9593 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9594 }
9595 ret = NULL;
b1503cda 9596 max = ARRAY_SIZE(ppc_defs);
068abdc8 9597 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9598 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9599 ret = &ppc_defs[i];
9600 break;
3fc6c082
FB		 9601 }
9602 }
ee4e83ed
JM		 9603
9604 return ret;
3fc6c082
FB		 9605}
9606
9607void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9608{
068abdc8 9609 int i, max;
3fc6c082 9610
b1503cda 9611 max = ARRAY_SIZE(ppc_defs);
068abdc8 9612 for (i = 0; i < max; i++) {
a750fc0b
JM		 9613 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9614 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 9615 }
9616}
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