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Add MSR bits signification per PowerPC implementation flags (to be continued).
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0
JM		 26#include "dis-asm.h"
27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
a496775f 30//#define PPC_DEBUG_IRQ
3fc6c082
FB		 31
32struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
0487d6a8 36 uint64_t insns_flags;
3fc6c082 37 uint64_t msr_mask;
a750fc0b
JM		 38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
d26bfc9a 42 uint32_t flags;
237c0af0 43 int bfd_mach;
a750fc0b 44 void (*init_proc)(CPUPPCState *env);
3fc6c082
FB		 45};
46
e9df014c
JM		 47/* For user-mode emulation, we don't emulate any IRQ controller */
48#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 49#define PPC_IRQ_INIT_FN(name) \
50static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
51{ \
e9df014c
JM		 52}
53#else
a750fc0b 54#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 55void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56#endif
a750fc0b 57
4e290a0b 58PPC_IRQ_INIT_FN(40x);
e9df014c 59PPC_IRQ_INIT_FN(6xx);
d0dfae6e 60PPC_IRQ_INIT_FN(970);
e9df014c 61
3fc6c082
FB		 62/* Generic callbacks:
63 * do nothing but store/retrieve spr value
64 */
04f20795 65#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 66static void spr_read_generic (void *opaque, int sprn)
67{
04f20795 68 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 69}
70
71static void spr_write_generic (void *opaque, int sprn)
72{
04f20795 73 gen_op_store_dump_spr(sprn);
3fc6c082 74}
04f20795
JM		 75#else
76static void spr_read_generic (void *opaque, int sprn)
a496775f 77{
04f20795 78 gen_op_load_spr(sprn);
a496775f
JM		 79}
80
04f20795 81static void spr_write_generic (void *opaque, int sprn)
a496775f 82{
04f20795 83 gen_op_store_spr(sprn);
a496775f 84}
04f20795 85#endif
a496775f
JM		 86
87#if !defined(CONFIG_USER_ONLY)
88static void spr_write_clear (void *opaque, int sprn)
89{
90 gen_op_mask_spr(sprn);
91}
92#endif
93
76a66253 94/* SPR common to all PowerPC */
3fc6c082
FB		 95/* XER */
96static void spr_read_xer (void *opaque, int sprn)
97{
98 gen_op_load_xer();
99}
100
101static void spr_write_xer (void *opaque, int sprn)
102{
103 gen_op_store_xer();
104}
105
106/* LR */
107static void spr_read_lr (void *opaque, int sprn)
108{
109 gen_op_load_lr();
110}
111
112static void spr_write_lr (void *opaque, int sprn)
113{
114 gen_op_store_lr();
115}
116
117/* CTR */
118static void spr_read_ctr (void *opaque, int sprn)
119{
120 gen_op_load_ctr();
121}
122
123static void spr_write_ctr (void *opaque, int sprn)
124{
125 gen_op_store_ctr();
126}
127
128/* User read access to SPR */
129/* USPRx */
130/* UMMCRx */
131/* UPMCx */
132/* USIA */
133/* UDECR */
134static void spr_read_ureg (void *opaque, int sprn)
135{
136 gen_op_load_spr(sprn + 0x10);
137}
138
76a66253 139/* SPR common to all non-embedded PowerPC */
3fc6c082 140/* DECR */
76a66253 141#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 142static void spr_read_decr (void *opaque, int sprn)
143{
144 gen_op_load_decr();
145}
146
147static void spr_write_decr (void *opaque, int sprn)
148{
149 gen_op_store_decr();
150}
76a66253 151#endif
3fc6c082 152
76a66253 153/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 154/* Time base */
155static void spr_read_tbl (void *opaque, int sprn)
156{
157 gen_op_load_tbl();
158}
159
76a66253 160static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 161{
76a66253 162 gen_op_load_tbu();
3fc6c082
FB		 163}
164
a062e36c
JM		 165__attribute__ (( unused ))
166static void spr_read_atbl (void *opaque, int sprn)
167{
168 gen_op_load_atbl();
169}
170
171__attribute__ (( unused ))
172static void spr_read_atbu (void *opaque, int sprn)
173{
174 gen_op_load_atbu();
175}
176
76a66253
JM		 177#if !defined(CONFIG_USER_ONLY)
178static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 179{
76a66253 180 gen_op_store_tbl();
3fc6c082
FB		 181}
182
183static void spr_write_tbu (void *opaque, int sprn)
184{
185 gen_op_store_tbu();
186}
a062e36c
JM		 187
188__attribute__ (( unused ))
189static void spr_write_atbl (void *opaque, int sprn)
190{
191 gen_op_store_atbl();
192}
193
194__attribute__ (( unused ))
195static void spr_write_atbu (void *opaque, int sprn)
196{
197 gen_op_store_atbu();
198}
76a66253 199#endif
3fc6c082 200
76a66253 201#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 202/* IBAT0U...IBAT0U */
203/* IBAT0L...IBAT7L */
204static void spr_read_ibat (void *opaque, int sprn)
205{
206 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207}
208
209static void spr_read_ibat_h (void *opaque, int sprn)
210{
211 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212}
213
214static void spr_write_ibatu (void *opaque, int sprn)
215{
3fc6c082 216 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 217}
218
219static void spr_write_ibatu_h (void *opaque, int sprn)
220{
3fc6c082 221 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 222}
223
224static void spr_write_ibatl (void *opaque, int sprn)
225{
3fc6c082 226 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 227}
228
229static void spr_write_ibatl_h (void *opaque, int sprn)
230{
3fc6c082 231 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 232}
233
234/* DBAT0U...DBAT7U */
235/* DBAT0L...DBAT7L */
236static void spr_read_dbat (void *opaque, int sprn)
237{
238 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239}
240
241static void spr_read_dbat_h (void *opaque, int sprn)
242{
243 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
244}
245
246static void spr_write_dbatu (void *opaque, int sprn)
247{
3fc6c082 248 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 249}
250
251static void spr_write_dbatu_h (void *opaque, int sprn)
252{
3fc6c082 253 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
3fc6c082
FB		 254}
255
256static void spr_write_dbatl (void *opaque, int sprn)
257{
3fc6c082 258 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 259}
260
261static void spr_write_dbatl_h (void *opaque, int sprn)
262{
3fc6c082 263 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
3fc6c082
FB		 264}
265
266/* SDR1 */
267static void spr_read_sdr1 (void *opaque, int sprn)
268{
269 gen_op_load_sdr1();
270}
271
272static void spr_write_sdr1 (void *opaque, int sprn)
273{
3fc6c082 274 gen_op_store_sdr1();
3fc6c082
FB		 275}
276
76a66253
JM		 277/* 64 bits PowerPC specific SPRs */
278/* ASR */
578bb252
JM		 279#if defined(TARGET_PPC64)
280__attribute__ (( unused ))
76a66253
JM		 281static void spr_read_asr (void *opaque, int sprn)
282{
283 gen_op_load_asr();
284}
285
578bb252 286__attribute__ (( unused ))
76a66253
JM		 287static void spr_write_asr (void *opaque, int sprn)
288{
76a66253 289 gen_op_store_asr();
76a66253
JM		 290}
291#endif
a750fc0b 292#endif
76a66253
JM		 293
294/* PowerPC 601 specific registers */
295/* RTC */
296static void spr_read_601_rtcl (void *opaque, int sprn)
297{
298 gen_op_load_601_rtcl();
299}
300
301static void spr_read_601_rtcu (void *opaque, int sprn)
302{
303 gen_op_load_601_rtcu();
304}
305
306#if !defined(CONFIG_USER_ONLY)
307static void spr_write_601_rtcu (void *opaque, int sprn)
308{
309 gen_op_store_601_rtcu();
310}
311
312static void spr_write_601_rtcl (void *opaque, int sprn)
313{
314 gen_op_store_601_rtcl();
315}
316#endif
317
318/* Unified bats */
319#if !defined(CONFIG_USER_ONLY)
320static void spr_read_601_ubat (void *opaque, int sprn)
321{
322 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
323}
324
325static void spr_write_601_ubatu (void *opaque, int sprn)
326{
76a66253 327 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 328}
329
330static void spr_write_601_ubatl (void *opaque, int sprn)
331{
76a66253 332 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 333}
334#endif
335
336/* PowerPC 40x specific registers */
337#if !defined(CONFIG_USER_ONLY)
338static void spr_read_40x_pit (void *opaque, int sprn)
339{
340 gen_op_load_40x_pit();
341}
342
343static void spr_write_40x_pit (void *opaque, int sprn)
344{
345 gen_op_store_40x_pit();
346}
347
8ecc7913
JM		 348static void spr_write_40x_dbcr0 (void *opaque, int sprn)
349{
350 DisasContext *ctx = opaque;
351
352 gen_op_store_40x_dbcr0();
353 /* We must stop translation as we may have rebooted */
e1833e1f 354 GEN_STOP(ctx);
8ecc7913
JM		 355}
356
c294fc58
JM		 357static void spr_write_40x_sler (void *opaque, int sprn)
358{
c294fc58 359 gen_op_store_40x_sler();
c294fc58
JM		 360}
361
76a66253
JM		 362static void spr_write_booke_tcr (void *opaque, int sprn)
363{
364 gen_op_store_booke_tcr();
365}
366
367static void spr_write_booke_tsr (void *opaque, int sprn)
368{
369 gen_op_store_booke_tsr();
370}
371#endif
372
373/* PowerPC 403 specific registers */
374/* PBL1 / PBU1 / PBL2 / PBU2 */
375#if !defined(CONFIG_USER_ONLY)
376static void spr_read_403_pbr (void *opaque, int sprn)
377{
378 gen_op_load_403_pb(sprn - SPR_403_PBL1);
379}
380
381static void spr_write_403_pbr (void *opaque, int sprn)
382{
76a66253 383 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 384}
385
3fc6c082
FB		 386static void spr_write_pir (void *opaque, int sprn)
387{
388 gen_op_store_pir();
389}
76a66253 390#endif
3fc6c082 391
6f5d427d
JM		 392#if !defined(CONFIG_USER_ONLY)
393/* Callback used to write the exception vector base */
394static void spr_write_excp_prefix (void *opaque, int sprn)
395{
396 gen_op_store_excp_prefix();
397 gen_op_store_spr(sprn);
398}
399
400static void spr_write_excp_vector (void *opaque, int sprn)
401{
402 DisasContext *ctx = opaque;
403
404 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
405 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
406 gen_op_store_spr(sprn);
407 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
408 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
409 gen_op_store_spr(sprn);
410 } else {
411 printf("Trying to write an unknown exception vector %d %03x\n",
412 sprn, sprn);
413 GEN_EXCP_PRIVREG(ctx);
414 }
415}
416#endif
417
76a66253
JM		 418#if defined(CONFIG_USER_ONLY)
419#define spr_register(env, num, name, uea_read, uea_write, \
420 oea_read, oea_write, initial_value) \
421do { \
422 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
423} while (0)
424static inline void _spr_register (CPUPPCState *env, int num,
425 const unsigned char *name,
426 void (*uea_read)(void *opaque, int sprn),
427 void (*uea_write)(void *opaque, int sprn),
428 target_ulong initial_value)
429#else
3fc6c082
FB		 430static inline void spr_register (CPUPPCState *env, int num,
431 const unsigned char *name,
432 void (*uea_read)(void *opaque, int sprn),
433 void (*uea_write)(void *opaque, int sprn),
434 void (*oea_read)(void *opaque, int sprn),
435 void (*oea_write)(void *opaque, int sprn),
436 target_ulong initial_value)
76a66253 437#endif
3fc6c082
FB		 438{
439 ppc_spr_t *spr;
440
441 spr = &env->spr_cb[num];
442 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 443#if !defined(CONFIG_USER_ONLY)
444 spr->oea_read != NULL || spr->oea_write != NULL ||
445#endif
446 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 447 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
448 exit(1);
449 }
450#if defined(PPC_DEBUG_SPR)
1b9eb036 451 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 452 initial_value);
3fc6c082
FB		 453#endif
454 spr->name = name;
455 spr->uea_read = uea_read;
456 spr->uea_write = uea_write;
76a66253 457#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 458 spr->oea_read = oea_read;
459 spr->oea_write = oea_write;
76a66253 460#endif
3fc6c082
FB		 461 env->spr[num] = initial_value;
462}
463
464/* Generic PowerPC SPRs */
465static void gen_spr_generic (CPUPPCState *env)
466{
467 /* Integer processing */
468 spr_register(env, SPR_XER, "XER",
469 &spr_read_xer, &spr_write_xer,
470 &spr_read_xer, &spr_write_xer,
471 0x00000000);
472 /* Branch contol */
473 spr_register(env, SPR_LR, "LR",
474 &spr_read_lr, &spr_write_lr,
475 &spr_read_lr, &spr_write_lr,
476 0x00000000);
477 spr_register(env, SPR_CTR, "CTR",
478 &spr_read_ctr, &spr_write_ctr,
479 &spr_read_ctr, &spr_write_ctr,
480 0x00000000);
481 /* Interrupt processing */
482 spr_register(env, SPR_SRR0, "SRR0",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 spr_register(env, SPR_SRR1, "SRR1",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 /* Processor control */
491 spr_register(env, SPR_SPRG0, "SPRG0",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 spr_register(env, SPR_SPRG1, "SPRG1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 spr_register(env, SPR_SPRG2, "SPRG2",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 spr_register(env, SPR_SPRG3, "SPRG3",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_generic, &spr_write_generic,
506 0x00000000);
507}
508
509/* SPR common to all non-embedded PowerPC, including 601 */
510static void gen_spr_ne_601 (CPUPPCState *env)
511{
512 /* Exception processing */
513 spr_register(env, SPR_DSISR, "DSISR",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517 spr_register(env, SPR_DAR, "DAR",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521 /* Timer */
522 spr_register(env, SPR_DECR, "DECR",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_decr, &spr_write_decr,
525 0x00000000);
526 /* Memory management */
527 spr_register(env, SPR_SDR1, "SDR1",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_sdr1, &spr_write_sdr1,
530 0x00000000);
531}
532
533/* BATs 0-3 */
534static void gen_low_BATs (CPUPPCState *env)
535{
536 spr_register(env, SPR_IBAT0U, "IBAT0U",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_ibat, &spr_write_ibatu,
539 0x00000000);
540 spr_register(env, SPR_IBAT0L, "IBAT0L",
541 SPR_NOACCESS, SPR_NOACCESS,
542 &spr_read_ibat, &spr_write_ibatl,
543 0x00000000);
544 spr_register(env, SPR_IBAT1U, "IBAT1U",
545 SPR_NOACCESS, SPR_NOACCESS,
546 &spr_read_ibat, &spr_write_ibatu,
547 0x00000000);
548 spr_register(env, SPR_IBAT1L, "IBAT1L",
549 SPR_NOACCESS, SPR_NOACCESS,
550 &spr_read_ibat, &spr_write_ibatl,
551 0x00000000);
552 spr_register(env, SPR_IBAT2U, "IBAT2U",
553 SPR_NOACCESS, SPR_NOACCESS,
554 &spr_read_ibat, &spr_write_ibatu,
555 0x00000000);
556 spr_register(env, SPR_IBAT2L, "IBAT2L",
557 SPR_NOACCESS, SPR_NOACCESS,
558 &spr_read_ibat, &spr_write_ibatl,
559 0x00000000);
560 spr_register(env, SPR_IBAT3U, "IBAT3U",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_ibat, &spr_write_ibatu,
563 0x00000000);
564 spr_register(env, SPR_IBAT3L, "IBAT3L",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_ibat, &spr_write_ibatl,
567 0x00000000);
568 spr_register(env, SPR_DBAT0U, "DBAT0U",
569 SPR_NOACCESS, SPR_NOACCESS,
570 &spr_read_dbat, &spr_write_dbatu,
571 0x00000000);
572 spr_register(env, SPR_DBAT0L, "DBAT0L",
573 SPR_NOACCESS, SPR_NOACCESS,
574 &spr_read_dbat, &spr_write_dbatl,
575 0x00000000);
576 spr_register(env, SPR_DBAT1U, "DBAT1U",
577 SPR_NOACCESS, SPR_NOACCESS,
578 &spr_read_dbat, &spr_write_dbatu,
579 0x00000000);
580 spr_register(env, SPR_DBAT1L, "DBAT1L",
581 SPR_NOACCESS, SPR_NOACCESS,
582 &spr_read_dbat, &spr_write_dbatl,
583 0x00000000);
584 spr_register(env, SPR_DBAT2U, "DBAT2U",
585 SPR_NOACCESS, SPR_NOACCESS,
586 &spr_read_dbat, &spr_write_dbatu,
587 0x00000000);
588 spr_register(env, SPR_DBAT2L, "DBAT2L",
589 SPR_NOACCESS, SPR_NOACCESS,
590 &spr_read_dbat, &spr_write_dbatl,
591 0x00000000);
592 spr_register(env, SPR_DBAT3U, "DBAT3U",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_dbat, &spr_write_dbatu,
595 0x00000000);
596 spr_register(env, SPR_DBAT3L, "DBAT3L",
597 SPR_NOACCESS, SPR_NOACCESS,
598 &spr_read_dbat, &spr_write_dbatl,
599 0x00000000);
a750fc0b 600 env->nb_BATs += 4;
3fc6c082
FB		 601}
602
603/* BATs 4-7 */
604static void gen_high_BATs (CPUPPCState *env)
605{
606 spr_register(env, SPR_IBAT4U, "IBAT4U",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_ibat_h, &spr_write_ibatu_h,
609 0x00000000);
610 spr_register(env, SPR_IBAT4L, "IBAT4L",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat_h, &spr_write_ibatl_h,
613 0x00000000);
614 spr_register(env, SPR_IBAT5U, "IBAT5U",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat_h, &spr_write_ibatu_h,
617 0x00000000);
618 spr_register(env, SPR_IBAT5L, "IBAT5L",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat_h, &spr_write_ibatl_h,
621 0x00000000);
622 spr_register(env, SPR_IBAT6U, "IBAT6U",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatu_h,
625 0x00000000);
626 spr_register(env, SPR_IBAT6L, "IBAT6L",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatl_h,
629 0x00000000);
630 spr_register(env, SPR_IBAT7U, "IBAT7U",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat_h, &spr_write_ibatu_h,
633 0x00000000);
634 spr_register(env, SPR_IBAT7L, "IBAT7L",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_ibat_h, &spr_write_ibatl_h,
637 0x00000000);
638 spr_register(env, SPR_DBAT4U, "DBAT4U",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_dbat_h, &spr_write_dbatu_h,
641 0x00000000);
642 spr_register(env, SPR_DBAT4L, "DBAT4L",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat_h, &spr_write_dbatl_h,
645 0x00000000);
646 spr_register(env, SPR_DBAT5U, "DBAT5U",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat_h, &spr_write_dbatu_h,
649 0x00000000);
650 spr_register(env, SPR_DBAT5L, "DBAT5L",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat_h, &spr_write_dbatl_h,
653 0x00000000);
654 spr_register(env, SPR_DBAT6U, "DBAT6U",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatu_h,
657 0x00000000);
658 spr_register(env, SPR_DBAT6L, "DBAT6L",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatl_h,
661 0x00000000);
662 spr_register(env, SPR_DBAT7U, "DBAT7U",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat_h, &spr_write_dbatu_h,
665 0x00000000);
666 spr_register(env, SPR_DBAT7L, "DBAT7L",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_dbat_h, &spr_write_dbatl_h,
669 0x00000000);
a750fc0b 670 env->nb_BATs += 4;
3fc6c082
FB		 671}
672
673/* Generic PowerPC time base */
674static void gen_tbl (CPUPPCState *env)
675{
676 spr_register(env, SPR_VTBL, "TBL",
677 &spr_read_tbl, SPR_NOACCESS,
678 &spr_read_tbl, SPR_NOACCESS,
679 0x00000000);
680 spr_register(env, SPR_TBL, "TBL",
681 SPR_NOACCESS, SPR_NOACCESS,
682 SPR_NOACCESS, &spr_write_tbl,
683 0x00000000);
684 spr_register(env, SPR_VTBU, "TBU",
685 &spr_read_tbu, SPR_NOACCESS,
686 &spr_read_tbu, SPR_NOACCESS,
687 0x00000000);
688 spr_register(env, SPR_TBU, "TBU",
689 SPR_NOACCESS, SPR_NOACCESS,
690 SPR_NOACCESS, &spr_write_tbu,
691 0x00000000);
692}
693
76a66253
JM		 694/* Softare table search registers */
695static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
696{
697 env->nb_tlb = nb_tlbs;
698 env->nb_ways = nb_ways;
699 env->id_tlbs = 1;
700 spr_register(env, SPR_DMISS, "DMISS",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, SPR_NOACCESS,
703 0x00000000);
704 spr_register(env, SPR_DCMP, "DCMP",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, SPR_NOACCESS,
707 0x00000000);
708 spr_register(env, SPR_HASH1, "HASH1",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_generic, SPR_NOACCESS,
711 0x00000000);
712 spr_register(env, SPR_HASH2, "HASH2",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_generic, SPR_NOACCESS,
715 0x00000000);
716 spr_register(env, SPR_IMISS, "IMISS",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, SPR_NOACCESS,
719 0x00000000);
720 spr_register(env, SPR_ICMP, "ICMP",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, SPR_NOACCESS,
723 0x00000000);
724 spr_register(env, SPR_RPA, "RPA",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, &spr_write_generic,
727 0x00000000);
728}
729
730/* SPR common to MPC755 and G2 */
731static void gen_spr_G2_755 (CPUPPCState *env)
732{
733 /* SGPRs */
734 spr_register(env, SPR_SPRG4, "SPRG4",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738 spr_register(env, SPR_SPRG5, "SPRG5",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742 spr_register(env, SPR_SPRG6, "SPRG6",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 0x00000000);
746 spr_register(env, SPR_SPRG7, "SPRG7",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_generic, &spr_write_generic,
749 0x00000000);
750 /* External access control */
751 /* XXX : not implemented */
752 spr_register(env, SPR_EAR, "EAR",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756}
757
3fc6c082
FB		 758/* SPR common to all 7xx PowerPC implementations */
759static void gen_spr_7xx (CPUPPCState *env)
760{
761 /* Breakpoints */
762 /* XXX : not implemented */
763 spr_register(env, SPR_DABR, "DABR",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
767 /* XXX : not implemented */
768 spr_register(env, SPR_IABR, "IABR",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_generic, &spr_write_generic,
771 0x00000000);
772 /* Cache management */
773 /* XXX : not implemented */
774 spr_register(env, SPR_ICTC, "ICTC",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
76a66253
JM		 778 /* XXX : not implemented */
779 spr_register(env, SPR_L2CR, "L2CR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
3fc6c082
FB		 783 /* Performance monitors */
784 /* XXX : not implemented */
785 spr_register(env, SPR_MMCR0, "MMCR0",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
789 /* XXX : not implemented */
790 spr_register(env, SPR_MMCR1, "MMCR1",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, &spr_write_generic,
793 0x00000000);
794 /* XXX : not implemented */
795 spr_register(env, SPR_PMC1, "PMC1",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_generic, &spr_write_generic,
798 0x00000000);
799 /* XXX : not implemented */
800 spr_register(env, SPR_PMC2, "PMC2",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, &spr_write_generic,
803 0x00000000);
804 /* XXX : not implemented */
805 spr_register(env, SPR_PMC3, "PMC3",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_generic, &spr_write_generic,
808 0x00000000);
809 /* XXX : not implemented */
810 spr_register(env, SPR_PMC4, "PMC4",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
814 /* XXX : not implemented */
a750fc0b 815 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_generic, SPR_NOACCESS,
818 0x00000000);
578bb252 819 /* XXX : not implemented */
3fc6c082
FB		 820 spr_register(env, SPR_UMMCR0, "UMMCR0",
821 &spr_read_ureg, SPR_NOACCESS,
822 &spr_read_ureg, SPR_NOACCESS,
823 0x00000000);
578bb252 824 /* XXX : not implemented */
3fc6c082
FB		 825 spr_register(env, SPR_UMMCR1, "UMMCR1",
826 &spr_read_ureg, SPR_NOACCESS,
827 &spr_read_ureg, SPR_NOACCESS,
828 0x00000000);
578bb252 829 /* XXX : not implemented */
3fc6c082
FB		 830 spr_register(env, SPR_UPMC1, "UPMC1",
831 &spr_read_ureg, SPR_NOACCESS,
832 &spr_read_ureg, SPR_NOACCESS,
833 0x00000000);
578bb252 834 /* XXX : not implemented */
3fc6c082
FB		 835 spr_register(env, SPR_UPMC2, "UPMC2",
836 &spr_read_ureg, SPR_NOACCESS,
837 &spr_read_ureg, SPR_NOACCESS,
838 0x00000000);
578bb252 839 /* XXX : not implemented */
3fc6c082
FB		 840 spr_register(env, SPR_UPMC3, "UPMC3",
841 &spr_read_ureg, SPR_NOACCESS,
842 &spr_read_ureg, SPR_NOACCESS,
843 0x00000000);
578bb252 844 /* XXX : not implemented */
3fc6c082
FB		 845 spr_register(env, SPR_UPMC4, "UPMC4",
846 &spr_read_ureg, SPR_NOACCESS,
847 &spr_read_ureg, SPR_NOACCESS,
848 0x00000000);
578bb252 849 /* XXX : not implemented */
a750fc0b 850 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 851 &spr_read_ureg, SPR_NOACCESS,
852 &spr_read_ureg, SPR_NOACCESS,
853 0x00000000);
a750fc0b 854 /* External access control */
3fc6c082 855 /* XXX : not implemented */
a750fc0b 856 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic, &spr_write_generic,
859 0x00000000);
a750fc0b
JM		 860}
861
862static void gen_spr_thrm (CPUPPCState *env)
863{
864 /* Thermal management */
3fc6c082 865 /* XXX : not implemented */
a750fc0b 866 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, &spr_write_generic,
869 0x00000000);
870 /* XXX : not implemented */
a750fc0b 871 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
874 0x00000000);
3fc6c082 875 /* XXX : not implemented */
a750fc0b 876 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, &spr_write_generic,
879 0x00000000);
880}
881
882/* SPR specific to PowerPC 604 implementation */
883static void gen_spr_604 (CPUPPCState *env)
884{
885 /* Processor identification */
886 spr_register(env, SPR_PIR, "PIR",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_pir,
889 0x00000000);
890 /* Breakpoints */
891 /* XXX : not implemented */
892 spr_register(env, SPR_IABR, "IABR",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 /* XXX : not implemented */
897 spr_register(env, SPR_DABR, "DABR",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, &spr_write_generic,
900 0x00000000);
901 /* Performance counters */
902 /* XXX : not implemented */
903 spr_register(env, SPR_MMCR0, "MMCR0",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 /* XXX : not implemented */
908 spr_register(env, SPR_MMCR1, "MMCR1",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 /* XXX : not implemented */
913 spr_register(env, SPR_PMC1, "PMC1",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 /* XXX : not implemented */
918 spr_register(env, SPR_PMC2, "PMC2",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* XXX : not implemented */
923 spr_register(env, SPR_PMC3, "PMC3",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 /* XXX : not implemented */
928 spr_register(env, SPR_PMC4, "PMC4",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
a750fc0b 933 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, SPR_NOACCESS,
936 0x00000000);
937 /* XXX : not implemented */
938 spr_register(env, SPR_SDA, "SDA",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, SPR_NOACCESS,
941 0x00000000);
942 /* External access control */
943 /* XXX : not implemented */
944 spr_register(env, SPR_EAR, "EAR",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948}
949
76a66253
JM		 950/* SPR specific to PowerPC 603 implementation */
951static void gen_spr_603 (CPUPPCState *env)
3fc6c082 952{
76a66253
JM		 953 /* External access control */
954 /* XXX : not implemented */
955 spr_register(env, SPR_EAR, "EAR",
3fc6c082 956 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
3fc6c082
FB		 959}
960
76a66253
JM		 961/* SPR specific to PowerPC G2 implementation */
962static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 963{
76a66253
JM		 964 /* Memory base address */
965 /* MBAR */
578bb252 966 /* XXX : not implemented */
76a66253
JM		 967 spr_register(env, SPR_MBAR, "MBAR",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, &spr_write_generic,
970 0x00000000);
971 /* System version register */
972 /* SVR */
578bb252 973 /* XXX : TODO: initialize it to an appropriate value */
76a66253
JM		 974 spr_register(env, SPR_SVR, "SVR",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, SPR_NOACCESS,
977 0x00000000);
978 /* Exception processing */
363be49c 979 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
363be49c 983 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, &spr_write_generic,
986 0x00000000);
987 /* Breakpoints */
988 /* XXX : not implemented */
989 spr_register(env, SPR_DABR, "DABR",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_DABR2, "DABR2",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_IABR, "IABR",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_IABR2, "IABR2",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_IBCR, "IBCR",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_DBCR, "DBCR",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018}
1019
1020/* SPR specific to PowerPC 602 implementation */
1021static void gen_spr_602 (CPUPPCState *env)
1022{
1023 /* ESA registers */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_SER, "SER",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_SEBR, "SEBR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
a750fc0b 1035 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* Floating point status */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_SP, "SP",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_LT, "LT",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* Watchdog timer */
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_TCR, "TCR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* Interrupt base */
1057 spr_register(env, SPR_IBR, "IBR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
a750fc0b
JM		 1061 /* XXX : not implemented */
1062 spr_register(env, SPR_IABR, "IABR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 0x00000000);
76a66253
JM		 1066}
1067
1068/* SPR specific to PowerPC 601 implementation */
1069static void gen_spr_601 (CPUPPCState *env)
1070{
1071 /* Multiplication/division register */
1072 /* MQ */
1073 spr_register(env, SPR_MQ, "MQ",
1074 &spr_read_generic, &spr_write_generic,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077 /* RTC registers */
1078 spr_register(env, SPR_601_RTCU, "RTCU",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 SPR_NOACCESS, &spr_write_601_rtcu,
1081 0x00000000);
1082 spr_register(env, SPR_601_VRTCU, "RTCU",
1083 &spr_read_601_rtcu, SPR_NOACCESS,
1084 &spr_read_601_rtcu, SPR_NOACCESS,
1085 0x00000000);
1086 spr_register(env, SPR_601_RTCL, "RTCL",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 SPR_NOACCESS, &spr_write_601_rtcl,
1089 0x00000000);
1090 spr_register(env, SPR_601_VRTCL, "RTCL",
1091 &spr_read_601_rtcl, SPR_NOACCESS,
1092 &spr_read_601_rtcl, SPR_NOACCESS,
1093 0x00000000);
1094 /* Timer */
1095#if 0 /* ? */
1096 spr_register(env, SPR_601_UDECR, "UDECR",
1097 &spr_read_decr, SPR_NOACCESS,
1098 &spr_read_decr, SPR_NOACCESS,
1099 0x00000000);
1100#endif
1101 /* External access control */
1102 /* XXX : not implemented */
1103 spr_register(env, SPR_EAR, "EAR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 /* Memory management */
1108 spr_register(env, SPR_IBAT0U, "IBAT0U",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_601_ubat, &spr_write_601_ubatu,
1111 0x00000000);
1112 spr_register(env, SPR_IBAT0L, "IBAT0L",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_601_ubat, &spr_write_601_ubatl,
1115 0x00000000);
1116 spr_register(env, SPR_IBAT1U, "IBAT1U",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_601_ubat, &spr_write_601_ubatu,
1119 0x00000000);
1120 spr_register(env, SPR_IBAT1L, "IBAT1L",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_601_ubat, &spr_write_601_ubatl,
1123 0x00000000);
1124 spr_register(env, SPR_IBAT2U, "IBAT2U",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_601_ubat, &spr_write_601_ubatu,
1127 0x00000000);
1128 spr_register(env, SPR_IBAT2L, "IBAT2L",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_601_ubat, &spr_write_601_ubatl,
1131 0x00000000);
1132 spr_register(env, SPR_IBAT3U, "IBAT3U",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_601_ubat, &spr_write_601_ubatu,
1135 0x00000000);
1136 spr_register(env, SPR_IBAT3L, "IBAT3L",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_601_ubat, &spr_write_601_ubatl,
1139 0x00000000);
a750fc0b
JM		 1140 env->nb_BATs = 4;
1141}
1142
1143static void gen_spr_74xx (CPUPPCState *env)
1144{
1145 /* Processor identification */
1146 spr_register(env, SPR_PIR, "PIR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_pir,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_MMCR2, "MMCR2",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
578bb252 1155 /* XXX : not implemented */
a750fc0b
JM		 1156 spr_register(env, SPR_UMMCR2, "UMMCR2",
1157 &spr_read_ureg, SPR_NOACCESS,
1158 &spr_read_ureg, SPR_NOACCESS,
1159 0x00000000);
1160 /* XXX: not implemented */
1161 spr_register(env, SPR_BAMR, "BAMR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
578bb252 1165 /* XXX : not implemented */
a750fc0b
JM		 1166 spr_register(env, SPR_UBAMR, "UBAMR",
1167 &spr_read_ureg, SPR_NOACCESS,
1168 &spr_read_ureg, SPR_NOACCESS,
1169 0x00000000);
578bb252 1170 /* XXX : not implemented */
a750fc0b
JM		 1171 spr_register(env, SPR_MSSCR0, "MSSCR0",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175 /* Hardware implementation registers */
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_HID0, "HID0",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* XXX : not implemented */
1182 spr_register(env, SPR_HID1, "HID1",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* Altivec */
1187 spr_register(env, SPR_VRSAVE, "VRSAVE",
1188 &spr_read_generic, &spr_write_generic,
1189 &spr_read_generic, &spr_write_generic,
1190 0x00000000);
1191}
1192
a750fc0b
JM		 1193static void gen_l3_ctrl (CPUPPCState *env)
1194{
1195 /* L3CR */
1196 /* XXX : not implemented */
1197 spr_register(env, SPR_L3CR, "L3CR",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_generic, &spr_write_generic,
1200 0x00000000);
1201 /* L3ITCR0 */
578bb252 1202 /* XXX : not implemented */
a750fc0b
JM		 1203 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1206 0x00000000);
1207 /* L3ITCR1 */
578bb252 1208 /* XXX : not implemented */
a750fc0b
JM		 1209 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
1213 /* L3ITCR2 */
578bb252 1214 /* XXX : not implemented */
a750fc0b
JM		 1215 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 /* L3ITCR3 */
578bb252 1220 /* XXX : not implemented */
a750fc0b
JM		 1221 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* L3OHCR */
578bb252 1226 /* XXX : not implemented */
a750fc0b
JM		 1227 spr_register(env, SPR_L3OHCR, "L3OHCR",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* L3PM */
578bb252 1232 /* XXX : not implemented */
a750fc0b
JM		 1233 spr_register(env, SPR_L3PM, "L3PM",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_generic, &spr_write_generic,
1236 0x00000000);
1237}
a750fc0b 1238
578bb252 1239static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1240{
578bb252
JM		 1241 env->nb_tlb = nb_tlbs;
1242 env->nb_ways = nb_ways;
1243 env->id_tlbs = 1;
1244 /* XXX : not implemented */
a750fc0b
JM		 1245 spr_register(env, SPR_PTEHI, "PTEHI",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
578bb252 1249 /* XXX : not implemented */
a750fc0b
JM		 1250 spr_register(env, SPR_PTELO, "PTELO",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
578bb252 1254 /* XXX : not implemented */
a750fc0b
JM		 1255 spr_register(env, SPR_TLBMISS, "TLBMISS",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
76a66253
JM		 1259}
1260
1261/* PowerPC BookE SPR */
1262static void gen_spr_BookE (CPUPPCState *env)
1263{
1264 /* Processor identification */
1265 spr_register(env, SPR_BOOKE_PIR, "PIR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_pir,
1268 0x00000000);
1269 /* Interrupt processing */
363be49c 1270 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
363be49c
JM		 1274 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
2662a059 1278#if 0
363be49c
JM		 1279 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
2662a059 1287#endif
76a66253
JM		 1288 /* Debug */
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* XXX : not implemented */
1345 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1346 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1347 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1348 0x00000000);
1349 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 spr_register(env, SPR_BOOKE_ESR, "ESR",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
363be49c
JM		 1357 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1358 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1359 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1360 0x00000000);
1361 /* Exception vectors */
76a66253
JM		 1362 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1363 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1364 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1365 0x00000000);
1366 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1367 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1368 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1369 0x00000000);
1370 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1371 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1372 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1373 0x00000000);
1374 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1375 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1376 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1377 0x00000000);
1378 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1379 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1380 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1381 0x00000000);
1382 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1383 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1384 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1385 0x00000000);
1386 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1387 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1388 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1389 0x00000000);
1390 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1391 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1392 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1393 0x00000000);
1394 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1395 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1396 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1397 0x00000000);
1398 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1399 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1400 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1401 0x00000000);
1402 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1403 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1404 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1405 0x00000000);
1406 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1407 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1408 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1409 0x00000000);
1410 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1411 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1412 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1413 0x00000000);
1414 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1415 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1416 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1417 0x00000000);
1418 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1419 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1420 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1421 0x00000000);
1422 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1423 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1424 &spr_read_generic, &spr_write_excp_vector,
76a66253 1425 0x00000000);
2662a059 1426#if 0
363be49c
JM		 1427 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1428 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1429 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1430 0x00000000);
1431 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1432 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1433 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1434 0x00000000);
1435 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1436 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1437 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1438 0x00000000);
1439 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1440 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1441 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1442 0x00000000);
1443 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1444 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1445 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1446 0x00000000);
1447 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1448 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1449 &spr_read_generic, &spr_write_excp_vector,
363be49c 1450 0x00000000);
2662a059 1451#endif
76a66253
JM		 1452 spr_register(env, SPR_BOOKE_PID, "PID",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456 spr_register(env, SPR_BOOKE_TCR, "TCR",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_booke_tcr,
1459 0x00000000);
1460 spr_register(env, SPR_BOOKE_TSR, "TSR",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 &spr_read_generic, &spr_write_booke_tsr,
1463 0x00000000);
1464 /* Timer */
1465 spr_register(env, SPR_DECR, "DECR",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_decr, &spr_write_decr,
1468 0x00000000);
1469 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 SPR_NOACCESS, &spr_write_generic,
1472 0x00000000);
1473 /* SPRGs */
1474 spr_register(env, SPR_USPRG0, "USPRG0",
1475 &spr_read_generic, &spr_write_generic,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 spr_register(env, SPR_SPRG4, "SPRG4",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 spr_register(env, SPR_USPRG4, "USPRG4",
1483 &spr_read_ureg, SPR_NOACCESS,
1484 &spr_read_ureg, SPR_NOACCESS,
1485 0x00000000);
1486 spr_register(env, SPR_SPRG5, "SPRG5",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 spr_register(env, SPR_USPRG5, "USPRG5",
1491 &spr_read_ureg, SPR_NOACCESS,
1492 &spr_read_ureg, SPR_NOACCESS,
1493 0x00000000);
1494 spr_register(env, SPR_SPRG6, "SPRG6",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 spr_register(env, SPR_USPRG6, "USPRG6",
1499 &spr_read_ureg, SPR_NOACCESS,
1500 &spr_read_ureg, SPR_NOACCESS,
1501 0x00000000);
1502 spr_register(env, SPR_SPRG7, "SPRG7",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506 spr_register(env, SPR_USPRG7, "USPRG7",
1507 &spr_read_ureg, SPR_NOACCESS,
1508 &spr_read_ureg, SPR_NOACCESS,
1509 0x00000000);
1510}
1511
363be49c
JM		 1512/* FSL storage control registers */
1513static void gen_spr_BookE_FSL (CPUPPCState *env)
1514{
1515 /* TLB assist registers */
578bb252 1516 /* XXX : not implemented */
363be49c
JM		 1517 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000);
578bb252 1521 /* XXX : not implemented */
363be49c
JM		 1522 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
578bb252 1526 /* XXX : not implemented */
363be49c
JM		 1527 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic,
1530 0x00000000);
578bb252 1531 /* XXX : not implemented */
363be49c
JM		 1532 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
578bb252 1536 /* XXX : not implemented */
363be49c
JM		 1537 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
578bb252 1541 /* XXX : not implemented */
363be49c
JM		 1542 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
578bb252 1546 /* XXX : not implemented */
363be49c
JM		 1547 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551 if (env->nb_pids > 1) {
578bb252 1552 /* XXX : not implemented */
363be49c
JM		 1553 spr_register(env, SPR_BOOKE_PID1, "PID1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 }
1558 if (env->nb_pids > 2) {
578bb252 1559 /* XXX : not implemented */
363be49c
JM		 1560 spr_register(env, SPR_BOOKE_PID2, "PID2",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 }
578bb252 1565 /* XXX : not implemented */
65f9ee8d 1566 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, SPR_NOACCESS,
1569 0x00000000); /* TOFIX */
578bb252 1570 /* XXX : not implemented */
65f9ee8d 1571 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000); /* TOFIX */
1575 switch (env->nb_ways) {
1576 case 4:
578bb252 1577 /* XXX : not implemented */
363be49c
JM		 1578 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, SPR_NOACCESS,
1581 0x00000000); /* TOFIX */
1582 /* Fallthru */
1583 case 3:
578bb252 1584 /* XXX : not implemented */
363be49c
JM		 1585 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, SPR_NOACCESS,
1588 0x00000000); /* TOFIX */
1589 /* Fallthru */
1590 case 2:
578bb252 1591 /* XXX : not implemented */
363be49c
JM		 1592 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, SPR_NOACCESS,
1595 0x00000000); /* TOFIX */
1596 /* Fallthru */
1597 case 1:
578bb252 1598 /* XXX : not implemented */
363be49c
JM		 1599 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, SPR_NOACCESS,
1602 0x00000000); /* TOFIX */
1603 /* Fallthru */
1604 case 0:
1605 default:
1606 break;
1607 }
1608}
1609
76a66253
JM		 1610/* SPR specific to PowerPC 440 implementation */
1611static void gen_spr_440 (CPUPPCState *env)
1612{
1613 /* Cache control */
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_440_DNV0, "DNV0",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 /* XXX : not implemented */
1620 spr_register(env, SPR_440_DNV1, "DNV1",
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, &spr_write_generic,
1623 0x00000000);
1624 /* XXX : not implemented */
1625 spr_register(env, SPR_440_DNV2, "DNV2",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_generic,
1628 0x00000000);
1629 /* XXX : not implemented */
1630 spr_register(env, SPR_440_DNV3, "DNV3",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 /* XXX : not implemented */
2662a059 1635 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_generic,
1638 0x00000000);
1639 /* XXX : not implemented */
2662a059 1640 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, &spr_write_generic,
1643 0x00000000);
1644 /* XXX : not implemented */
2662a059 1645 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1646 SPR_NOACCESS, SPR_NOACCESS,
1647 &spr_read_generic, &spr_write_generic,
1648 0x00000000);
1649 /* XXX : not implemented */
2662a059 1650 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, &spr_write_generic,
1653 0x00000000);
1654 /* XXX : not implemented */
1655 spr_register(env, SPR_440_DVLIM, "DVLIM",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 /* XXX : not implemented */
1660 spr_register(env, SPR_440_INV0, "INV0",
1661 SPR_NOACCESS, SPR_NOACCESS,
1662 &spr_read_generic, &spr_write_generic,
1663 0x00000000);
1664 /* XXX : not implemented */
1665 spr_register(env, SPR_440_INV1, "INV1",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_generic,
1668 0x00000000);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_440_INV2, "INV2",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_440_INV3, "INV3",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, &spr_write_generic,
1678 0x00000000);
1679 /* XXX : not implemented */
2662a059 1680 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 /* XXX : not implemented */
2662a059 1685 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689 /* XXX : not implemented */
2662a059 1690 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1691 SPR_NOACCESS, SPR_NOACCESS,
1692 &spr_read_generic, &spr_write_generic,
1693 0x00000000);
1694 /* XXX : not implemented */
2662a059 1695 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1698 0x00000000);
1699 /* XXX : not implemented */
1700 spr_register(env, SPR_440_IVLIM, "IVLIM",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, &spr_write_generic,
1703 0x00000000);
1704 /* Cache debug */
1705 /* XXX : not implemented */
2662a059 1706 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, SPR_NOACCESS,
1709 0x00000000);
1710 /* XXX : not implemented */
2662a059 1711 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, SPR_NOACCESS,
1714 0x00000000);
1715 /* XXX : not implemented */
2662a059 1716 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, SPR_NOACCESS,
1719 0x00000000);
1720 /* XXX : not implemented */
2662a059 1721 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, SPR_NOACCESS,
1724 0x00000000);
1725 /* XXX : not implemented */
2662a059 1726 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, SPR_NOACCESS,
1729 0x00000000);
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_440_DBDR, "DBDR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* Processor control */
1736 spr_register(env, SPR_4xx_CCR0, "CCR0",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, SPR_NOACCESS,
1743 0x00000000);
1744 /* Storage control */
1745 spr_register(env, SPR_440_MMUCR, "MMUCR",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749}
1750
1751/* SPR shared between PowerPC 40x implementations */
1752static void gen_spr_40x (CPUPPCState *env)
1753{
1754 /* Cache */
035feb88 1755 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1756 spr_register(env, SPR_40x_DCCR, "DCCR",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
035feb88 1760 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1761 spr_register(env, SPR_40x_ICCR, "ICCR",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_generic,
1764 0x00000000);
578bb252 1765 /* not emulated, as Qemu do not emulate caches */
2662a059 1766 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1767 SPR_NOACCESS, SPR_NOACCESS,
1768 &spr_read_generic, SPR_NOACCESS,
1769 0x00000000);
76a66253
JM		 1770 /* Exception */
1771 spr_register(env, SPR_40x_DEAR, "DEAR",
1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_generic,
1774 0x00000000);
1775 spr_register(env, SPR_40x_ESR, "ESR",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 spr_register(env, SPR_40x_EVPR, "EVPR",
1780 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1781 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1782 0x00000000);
1783 spr_register(env, SPR_40x_SRR2, "SRR2",
1784 &spr_read_generic, &spr_write_generic,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 spr_register(env, SPR_40x_SRR3, "SRR3",
1788 &spr_read_generic, &spr_write_generic,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* Timers */
1792 spr_register(env, SPR_40x_PIT, "PIT",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_40x_pit, &spr_write_40x_pit,
1795 0x00000000);
1796 spr_register(env, SPR_40x_TCR, "TCR",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, &spr_write_booke_tcr,
1799 0x00000000);
1800 spr_register(env, SPR_40x_TSR, "TSR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_booke_tsr,
1803 0x00000000);
2662a059
JM		 1804}
1805
1806/* SPR specific to PowerPC 405 implementation */
1807static void gen_spr_405 (CPUPPCState *env)
1808{
1809 /* MMU */
1810 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
2662a059 1814 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1817 0x00700000);
1818 /* Debug interface */
76a66253
JM		 1819 /* XXX : not implemented */
1820 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1821 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1822 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1823 0x00000000);
1824 /* XXX : not implemented */
2662a059
JM		 1825 spr_register(env, SPR_405_DBCR1, "DBCR1",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 /* XXX : not implemented */
76a66253
JM		 1830 spr_register(env, SPR_40x_DBSR, "DBSR",
1831 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1832 &spr_read_generic, &spr_write_clear,
1833 /* Last reset was system reset */
76a66253
JM		 1834 0x00000300);
1835 /* XXX : not implemented */
2662a059 1836 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00000000);
2662a059 1840 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
2662a059
JM		 1844 /* XXX : not implemented */
1845 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1846 SPR_NOACCESS, SPR_NOACCESS,
1847 &spr_read_generic, &spr_write_generic,
2662a059 1848 0x00000000);
76a66253 1849 /* XXX : not implemented */
2662a059 1850 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_generic, &spr_write_generic,
1853 0x00000000);
1854 /* XXX : not implemented */
2662a059 1855 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, &spr_write_generic,
1858 0x00000000);
2662a059 1859 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1860 SPR_NOACCESS, SPR_NOACCESS,
1861 &spr_read_generic, &spr_write_generic,
1862 0x00000000);
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_405_IAC3, "IAC3",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_generic,
1867 0x00000000);
1868 /* XXX : not implemented */
1869 spr_register(env, SPR_405_IAC4, "IAC4",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 /* Storage control */
035feb88 1874 /* XXX: TODO: not implemented */
76a66253
JM		 1875 spr_register(env, SPR_405_SLER, "SLER",
1876 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1877 &spr_read_generic, &spr_write_40x_sler,
76a66253 1878 0x00000000);
2662a059
JM		 1879 spr_register(env, SPR_40x_ZPR, "ZPR",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
76a66253
JM		 1883 /* XXX : not implemented */
1884 spr_register(env, SPR_405_SU0R, "SU0R",
1885 SPR_NOACCESS, SPR_NOACCESS,
1886 &spr_read_generic, &spr_write_generic,
1887 0x00000000);
1888 /* SPRG */
1889 spr_register(env, SPR_USPRG0, "USPRG0",
1890 &spr_read_ureg, SPR_NOACCESS,
1891 &spr_read_ureg, SPR_NOACCESS,
1892 0x00000000);
1893 spr_register(env, SPR_SPRG4, "SPRG4",
1894 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1895 &spr_read_generic, &spr_write_generic,
76a66253
JM		 1896 0x00000000);
1897 spr_register(env, SPR_USPRG4, "USPRG4",
1898 &spr_read_ureg, SPR_NOACCESS,
1899 &spr_read_ureg, SPR_NOACCESS,
1900 0x00000000);
1901 spr_register(env, SPR_SPRG5, "SPRG5",
1902 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1903 spr_read_generic, &spr_write_generic,
76a66253
JM		 1904 0x00000000);
1905 spr_register(env, SPR_USPRG5, "USPRG5",
1906 &spr_read_ureg, SPR_NOACCESS,
1907 &spr_read_ureg, SPR_NOACCESS,
1908 0x00000000);
1909 spr_register(env, SPR_SPRG6, "SPRG6",
1910 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1911 spr_read_generic, &spr_write_generic,
76a66253
JM		 1912 0x00000000);
1913 spr_register(env, SPR_USPRG6, "USPRG6",
1914 &spr_read_ureg, SPR_NOACCESS,
1915 &spr_read_ureg, SPR_NOACCESS,
1916 0x00000000);
1917 spr_register(env, SPR_SPRG7, "SPRG7",
1918 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1919 spr_read_generic, &spr_write_generic,
76a66253
JM		 1920 0x00000000);
1921 spr_register(env, SPR_USPRG7, "USPRG7",
1922 &spr_read_ureg, SPR_NOACCESS,
1923 &spr_read_ureg, SPR_NOACCESS,
1924 0x00000000);
76a66253
JM		 1925}
1926
1927/* SPR shared between PowerPC 401 & 403 implementations */
1928static void gen_spr_401_403 (CPUPPCState *env)
1929{
1930 /* Time base */
1931 spr_register(env, SPR_403_VTBL, "TBL",
1932 &spr_read_tbl, SPR_NOACCESS,
1933 &spr_read_tbl, SPR_NOACCESS,
1934 0x00000000);
1935 spr_register(env, SPR_403_TBL, "TBL",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 SPR_NOACCESS, &spr_write_tbl,
1938 0x00000000);
1939 spr_register(env, SPR_403_VTBU, "TBU",
1940 &spr_read_tbu, SPR_NOACCESS,
1941 &spr_read_tbu, SPR_NOACCESS,
1942 0x00000000);
1943 spr_register(env, SPR_403_TBU, "TBU",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 SPR_NOACCESS, &spr_write_tbu,
1946 0x00000000);
1947 /* Debug */
578bb252 1948 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1949 spr_register(env, SPR_403_CDBCR, "CDBCR",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953}
1954
2662a059
JM		 1955/* SPR specific to PowerPC 401 implementation */
1956static void gen_spr_401 (CPUPPCState *env)
1957{
1958 /* Debug interface */
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_40x_DBCR0, "DBCR",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_40x_dbcr0,
1963 0x00000000);
1964 /* XXX : not implemented */
1965 spr_register(env, SPR_40x_DBSR, "DBSR",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_clear,
1968 /* Last reset was system reset */
1969 0x00000300);
1970 /* XXX : not implemented */
1971 spr_register(env, SPR_40x_DAC1, "DAC",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1974 0x00000000);
1975 /* XXX : not implemented */
1976 spr_register(env, SPR_40x_IAC1, "IAC",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_generic,
1979 0x00000000);
1980 /* Storage control */
035feb88 1981 /* XXX: TODO: not implemented */
2662a059
JM		 1982 spr_register(env, SPR_405_SLER, "SLER",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_40x_sler,
1985 0x00000000);
035feb88
JM		 1986 /* not emulated, as Qemu never does speculative access */
1987 spr_register(env, SPR_40x_SGR, "SGR",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0xFFFFFFFF);
1991 /* not emulated, as Qemu do not emulate caches */
1992 spr_register(env, SPR_40x_DCWR, "DCWR",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
2662a059
JM		 1996}
1997
a750fc0b
JM		 1998static void gen_spr_401x2 (CPUPPCState *env)
1999{
2000 gen_spr_401(env);
2001 spr_register(env, SPR_40x_PID, "PID",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 spr_register(env, SPR_40x_ZPR, "ZPR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009}
2010
76a66253
JM		 2011/* SPR specific to PowerPC 403 implementation */
2012static void gen_spr_403 (CPUPPCState *env)
2013{
2662a059
JM		 2014 /* Debug interface */
2015 /* XXX : not implemented */
2016 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_40x_dbcr0,
2019 0x00000000);
2020 /* XXX : not implemented */
2021 spr_register(env, SPR_40x_DBSR, "DBSR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_clear,
2024 /* Last reset was system reset */
2025 0x00000300);
2026 /* XXX : not implemented */
2027 spr_register(env, SPR_40x_DAC1, "DAC1",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
578bb252 2031 /* XXX : not implemented */
2662a059
JM		 2032 spr_register(env, SPR_40x_DAC2, "DAC2",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2035 0x00000000);
2036 /* XXX : not implemented */
2037 spr_register(env, SPR_40x_IAC1, "IAC1",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_generic,
2040 0x00000000);
578bb252 2041 /* XXX : not implemented */
2662a059
JM		 2042 spr_register(env, SPR_40x_IAC2, "IAC2",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
a750fc0b
JM		 2046}
2047
2048static void gen_spr_403_real (CPUPPCState *env)
2049{
76a66253
JM		 2050 spr_register(env, SPR_403_PBL1, "PBL1",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_403_pbr, &spr_write_403_pbr,
2053 0x00000000);
2054 spr_register(env, SPR_403_PBU1, "PBU1",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_403_pbr, &spr_write_403_pbr,
2057 0x00000000);
2058 spr_register(env, SPR_403_PBL2, "PBL2",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_403_pbr, &spr_write_403_pbr,
2061 0x00000000);
2062 spr_register(env, SPR_403_PBU2, "PBU2",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_403_pbr, &spr_write_403_pbr,
2065 0x00000000);
a750fc0b
JM		 2066}
2067
2068static void gen_spr_403_mmu (CPUPPCState *env)
2069{
2070 /* MMU */
2071 spr_register(env, SPR_40x_PID, "PID",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2662a059 2075 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_generic,
2078 0x00000000);
2079}
2080
2081/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2082static void gen_spr_compress (CPUPPCState *env)
2083{
578bb252 2084 /* XXX : not implemented */
76a66253
JM		 2085 spr_register(env, SPR_401_SKR, "SKR",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089}
a750fc0b
JM		 2090
2091#if defined (TARGET_PPC64)
a750fc0b
JM		 2092/* SPR specific to PowerPC 620 */
2093static void gen_spr_620 (CPUPPCState *env)
2094{
578bb252 2095 /* XXX : not implemented */
a750fc0b
JM		 2096 spr_register(env, SPR_620_PMR0, "PMR0",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
578bb252 2100 /* XXX : not implemented */
a750fc0b
JM		 2101 spr_register(env, SPR_620_PMR1, "PMR1",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_generic, &spr_write_generic,
2104 0x00000000);
578bb252 2105 /* XXX : not implemented */
a750fc0b
JM		 2106 spr_register(env, SPR_620_PMR2, "PMR2",
2107 SPR_NOACCESS, SPR_NOACCESS,
2108 &spr_read_generic, &spr_write_generic,
2109 0x00000000);
578bb252 2110 /* XXX : not implemented */
a750fc0b
JM		 2111 spr_register(env, SPR_620_PMR3, "PMR3",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
578bb252 2115 /* XXX : not implemented */
a750fc0b
JM		 2116 spr_register(env, SPR_620_PMR4, "PMR4",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_generic,
2119 0x00000000);
578bb252 2120 /* XXX : not implemented */
a750fc0b
JM		 2121 spr_register(env, SPR_620_PMR5, "PMR5",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, &spr_write_generic,
2124 0x00000000);
578bb252 2125 /* XXX : not implemented */
a750fc0b
JM		 2126 spr_register(env, SPR_620_PMR6, "PMR6",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, &spr_write_generic,
2129 0x00000000);
578bb252 2130 /* XXX : not implemented */
a750fc0b
JM		 2131 spr_register(env, SPR_620_PMR7, "PMR7",
2132 SPR_NOACCESS, SPR_NOACCESS,
2133 &spr_read_generic, &spr_write_generic,
2134 0x00000000);
578bb252 2135 /* XXX : not implemented */
a750fc0b
JM		 2136 spr_register(env, SPR_620_PMR8, "PMR8",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
578bb252 2140 /* XXX : not implemented */
a750fc0b
JM		 2141 spr_register(env, SPR_620_PMR9, "PMR9",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
578bb252 2145 /* XXX : not implemented */
a750fc0b
JM		 2146 spr_register(env, SPR_620_PMRA, "PMR10",
2147 SPR_NOACCESS, SPR_NOACCESS,
2148 &spr_read_generic, &spr_write_generic,
2149 0x00000000);
578bb252 2150 /* XXX : not implemented */
a750fc0b
JM		 2151 spr_register(env, SPR_620_PMRB, "PMR11",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
578bb252 2155 /* XXX : not implemented */
a750fc0b
JM		 2156 spr_register(env, SPR_620_PMRC, "PMR12",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_generic, &spr_write_generic,
2159 0x00000000);
578bb252 2160 /* XXX : not implemented */
a750fc0b
JM		 2161 spr_register(env, SPR_620_PMRD, "PMR13",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, &spr_write_generic,
2164 0x00000000);
578bb252 2165 /* XXX : not implemented */
a750fc0b
JM		 2166 spr_register(env, SPR_620_PMRE, "PMR14",
2167 SPR_NOACCESS, SPR_NOACCESS,
2168 &spr_read_generic, &spr_write_generic,
2169 0x00000000);
578bb252 2170 /* XXX : not implemented */
a750fc0b
JM		 2171 spr_register(env, SPR_620_PMRF, "PMR15",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
578bb252 2175 /* XXX : not implemented */
a750fc0b
JM		 2176 spr_register(env, SPR_620_HID8, "HID8",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, &spr_write_generic,
2179 0x00000000);
578bb252 2180 /* XXX : not implemented */
a750fc0b
JM		 2181 spr_register(env, SPR_620_HID9, "HID9",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_generic, &spr_write_generic,
2184 0x00000000);
2185}
a750fc0b 2186#endif /* defined (TARGET_PPC64) */
76a66253 2187
2662a059 2188// XXX: TODO
76a66253 2189/*
2662a059
JM		 2190 * AMR => SPR 29 (Power 2.04)
2191 * CTRL => SPR 136 (Power 2.04)
2192 * CTRL => SPR 152 (Power 2.04)
2662a059
JM		 2193 * SCOMC => SPR 276 (64 bits ?)
2194 * SCOMD => SPR 277 (64 bits ?)
2662a059
JM		 2195 * TBU40 => SPR 286 (Power 2.04 hypv)
2196 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2197 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2198 * HDSISR => SPR 306 (Power 2.04 hypv)
2199 * HDAR => SPR 307 (Power 2.04 hypv)
2200 * PURR => SPR 309 (Power 2.04 hypv)
2201 * HDEC => SPR 310 (Power 2.04 hypv)
2202 * HIOR => SPR 311 (hypv)
2203 * RMOR => SPR 312 (970)
2204 * HRMOR => SPR 313 (Power 2.04 hypv)
2205 * HSRR0 => SPR 314 (Power 2.04 hypv)
2206 * HSRR1 => SPR 315 (Power 2.04 hypv)
2207 * LPCR => SPR 316 (970)
2208 * LPIDR => SPR 317 (970)
2209 * SPEFSCR => SPR 512 (Power 2.04 emb)
2662a059
JM		 2210 * EPR => SPR 702 (Power 2.04 emb)
2211 * perf => 768-783 (Power 2.04)
2212 * perf => 784-799 (Power 2.04)
2213 * PPR => SPR 896 (Power 2.04)
2214 * EPLC => SPR 947 (Power 2.04 emb)
2215 * EPSC => SPR 948 (Power 2.04 emb)
2216 * DABRX => 1015 (Power 2.04 hypv)
2217 * FPECR => SPR 1022 (?)
76a66253
JM		 2218 * ... and more (thermal management, performance counters, ...)
2219 */
2220
e1833e1f
JM		 2221/*****************************************************************************/
2222/* Exception vectors models */
2223static void init_excp_4xx_real (CPUPPCState *env)
2224{
2225#if !defined(CONFIG_USER_ONLY)
2226 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2227 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2228 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2229 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2230 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2231 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2232 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2233 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2234 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2235 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2236 env->excp_prefix = 0x00000000;
2237 env->ivor_mask = 0x0000FFF0;
2238 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2239 /* Hardware reset vector */
2240 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2241#endif
2242}
2243
2244static void init_excp_4xx_softmmu (CPUPPCState *env)
2245{
2246#if !defined(CONFIG_USER_ONLY)
2247 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2248 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2249 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2250 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2251 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2252 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2253 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2254 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2255 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2256 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2257 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2258 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2259 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2260 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2261 env->excp_prefix = 0x00000000;
2262 env->ivor_mask = 0x0000FFF0;
2263 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2264 /* Hardware reset vector */
2265 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2266#endif
2267}
2268
2269static void init_excp_BookE (CPUPPCState *env)
2270{
2271#if !defined(CONFIG_USER_ONLY)
2272 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2273 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2274 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2275 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2276 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2277 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2278 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2279 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2280 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2281 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2282 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2283 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2284 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2285 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2288 env->excp_prefix = 0x00000000;
2289 env->ivor_mask = 0x0000FFE0;
2290 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2291 /* Hardware reset vector */
2292 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2293#endif
2294}
2295
2296static void init_excp_601 (CPUPPCState *env)
2297{
2298#if !defined(CONFIG_USER_ONLY)
2299 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2300 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2301 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2302 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2303 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2304 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2305 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2306 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2307 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2308 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2309 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2310 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2311 env->excp_prefix = 0xFFF00000;
1c27f8fb
JM		 2312 /* Hardware reset vector */
2313 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2314#endif
2315}
2316
2317static void init_excp_602 (CPUPPCState *env)
2318{
2319#if !defined(CONFIG_USER_ONLY)
2320 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2321 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2322 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2323 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2324 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2325 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2326 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2327 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2328 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2329 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2330 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2331 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2332 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2333 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2334 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2335 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2336 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2337 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2338 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2339 env->excp_prefix = 0xFFF00000;
1c27f8fb
JM		 2340 /* Hardware reset vector */
2341 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2342#endif
2343}
2344
2345static void init_excp_603 (CPUPPCState *env)
2346{
2347#if !defined(CONFIG_USER_ONLY)
2348 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2349 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2350 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2351 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2352 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2353 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2354 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2355 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2356 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2357 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2358 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2359 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2360 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2361 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2362 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2363 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2364 /* Hardware reset vector */
2365 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2366#endif
2367}
2368
2369static void init_excp_G2 (CPUPPCState *env)
2370{
2371#if !defined(CONFIG_USER_ONLY)
2372 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2373 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2374 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2375 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2376 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2377 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2378 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2379 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2380 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2381 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2382 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2383 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2384 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2385 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2386 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2387 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2388 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2389 /* Hardware reset vector */
2390 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2391#endif
2392}
2393
2394static void init_excp_604 (CPUPPCState *env)
2395{
2396#if !defined(CONFIG_USER_ONLY)
2397 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2398 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2399 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2400 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2401 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2402 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2403 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2404 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2405 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2406 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2407 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2408 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2409 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2410 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2411 /* Hardware reset vector */
2412 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2413#endif
2414}
2415
578bb252 2416#if defined(TARGET_PPC64)
e1833e1f
JM		 2417static void init_excp_620 (CPUPPCState *env)
2418{
2419#if !defined(CONFIG_USER_ONLY)
2420 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2421 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2422 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2423 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2424 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2425 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2426 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2427 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2428 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2429 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2430 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2431 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2432 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2433 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2434 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2435 /* Hardware reset vector */
2436 env->hreset_vector = 0x0000000000000100ULL; /* ? */
e1833e1f
JM		 2437#endif
2438}
578bb252 2439#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2440
2441static void init_excp_7x0 (CPUPPCState *env)
2442{
2443#if !defined(CONFIG_USER_ONLY)
2444 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2445 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2446 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2447 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2448 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2449 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2450 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2451 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2452 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2453 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2454 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2455 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2456 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2457 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2458 /* Hardware reset vector */
2459 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2460#endif
2461}
2462
2463static void init_excp_750FX (CPUPPCState *env)
2464{
2465#if !defined(CONFIG_USER_ONLY)
2466 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2467 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2468 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2469 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2470 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2471 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2472 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2473 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2474 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2475 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2476 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2477 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2478 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2479 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2480 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2481 /* Hardware reset vector */
2482 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2483#endif
2484}
2485
2486static void init_excp_7400 (CPUPPCState *env)
2487{
2488#if !defined(CONFIG_USER_ONLY)
2489 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2490 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2491 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2492 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2493 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2494 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2495 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2496 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2497 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2498 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2499 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2500 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2501 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2502 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2503 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2504 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2505 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2506 /* Hardware reset vector */
2507 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2508#endif
2509}
2510
e1833e1f
JM		 2511static void init_excp_7450 (CPUPPCState *env)
2512{
2513#if !defined(CONFIG_USER_ONLY)
2514 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2515 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2516 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2517 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2518 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2519 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2520 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2521 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2522 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2523 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2524 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2525 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2526 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2527 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2528 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2529 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2530 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2531 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2532 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb
JM		 2533 /* Hardware reset vector */
2534 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2535#endif
2536}
e1833e1f
JM		 2537
2538#if defined (TARGET_PPC64)
2539static void init_excp_970 (CPUPPCState *env)
2540{
2541#if !defined(CONFIG_USER_ONLY)
2542 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2543 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2544 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2545 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2546 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2547 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2548 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2549 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2550 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2551 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2552 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2553#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2554 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2555#endif
2556 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2557 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2558 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2559 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2560 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2561 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2562 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2563 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 2564 /* Hardware reset vector */
2565 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2566#endif
2567}
2568#endif
2569
a750fc0b
JM		 2570/*****************************************************************************/
2571/* PowerPC implementations definitions */
76a66253 2572
a750fc0b 2573/* PowerPC 40x instruction set */
d63001d1 2574#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
76a66253 2575
a750fc0b
JM		 2576/* PowerPC 401 */
2577#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2578 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2579 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2580#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2581#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2582#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2583#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 2584#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
d26bfc9a 2585#define POWERPC_FLAG_401 (POWERPC_FLAG_NONE)
76a66253 2586
a750fc0b
JM		 2587static void init_proc_401 (CPUPPCState *env)
2588{
2589 gen_spr_40x(env);
2590 gen_spr_401_403(env);
2591 gen_spr_401(env);
e1833e1f 2592 init_excp_4xx_real(env);
d63001d1
JM		 2593 env->dcache_line_size = 32;
2594 env->icache_line_size = 32;
4e290a0b
JM		 2595 /* Allocate hardware IRQ controller */
2596 ppc40x_irq_init(env);
a750fc0b 2597}
76a66253 2598
a750fc0b
JM		 2599/* PowerPC 401x2 */
2600#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2601 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2602 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2603 PPC_CACHE_DCBA | PPC_MFTB | \
2604 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2605#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2606#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2607#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2608#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 2609#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
d26bfc9a 2610#define POWERPC_FLAG_401x2 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2611
2612static void init_proc_401x2 (CPUPPCState *env)
2613{
2614 gen_spr_40x(env);
2615 gen_spr_401_403(env);
2616 gen_spr_401x2(env);
2617 gen_spr_compress(env);
a750fc0b
JM		 2618 /* Memory management */
2619 env->nb_tlb = 64;
2620 env->nb_ways = 1;
2621 env->id_tlbs = 0;
e1833e1f 2622 init_excp_4xx_softmmu(env);
d63001d1
JM		 2623 env->dcache_line_size = 32;
2624 env->icache_line_size = 32;
4e290a0b
JM		 2625 /* Allocate hardware IRQ controller */
2626 ppc40x_irq_init(env);
76a66253
JM		 2627}
2628
a750fc0b 2629/* PowerPC 401x3 */
a750fc0b
JM		 2630#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2631 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2632 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2633 PPC_CACHE_DCBA | PPC_MFTB | \
2634 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2635#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2636#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2637#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2638#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 2639#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
d26bfc9a 2640#define POWERPC_FLAG_401x3 (POWERPC_FLAG_NONE)
a750fc0b 2641
578bb252 2642__attribute__ (( unused ))
e1833e1f 2643static void init_proc_401x3 (CPUPPCState *env)
76a66253 2644{
4e290a0b
JM		 2645 gen_spr_40x(env);
2646 gen_spr_401_403(env);
2647 gen_spr_401(env);
2648 gen_spr_401x2(env);
2649 gen_spr_compress(env);
e1833e1f 2650 init_excp_4xx_softmmu(env);
d63001d1
JM		 2651 env->dcache_line_size = 32;
2652 env->icache_line_size = 32;
4e290a0b
JM		 2653 /* Allocate hardware IRQ controller */
2654 ppc40x_irq_init(env);
3fc6c082 2655}
a750fc0b
JM		 2656
2657/* IOP480 */
2658#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2659 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2660 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2661 PPC_CACHE_DCBA | \
2662 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2663#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2664#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2665#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2666#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 2667#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
d26bfc9a 2668#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2669
2670static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 2671{
a750fc0b
JM		 2672 gen_spr_40x(env);
2673 gen_spr_401_403(env);
2674 gen_spr_401x2(env);
2675 gen_spr_compress(env);
a750fc0b
JM		 2676 /* Memory management */
2677 env->nb_tlb = 64;
2678 env->nb_ways = 1;
2679 env->id_tlbs = 0;
e1833e1f 2680 init_excp_4xx_softmmu(env);
d63001d1
JM		 2681 env->dcache_line_size = 32;
2682 env->icache_line_size = 32;
4e290a0b
JM		 2683 /* Allocate hardware IRQ controller */
2684 ppc40x_irq_init(env);
3fc6c082
FB		 2685}
2686
a750fc0b
JM		 2687/* PowerPC 403 */
2688#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2689 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2690 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2691 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2692#define POWERPC_MSRM_403 (0x000000000007D00DULL)
2693#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2694#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2695#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 2696#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
d26bfc9a 2697#define POWERPC_FLAG_403 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2698
2699static void init_proc_403 (CPUPPCState *env)
3fc6c082 2700{
a750fc0b
JM		 2701 gen_spr_40x(env);
2702 gen_spr_401_403(env);
2703 gen_spr_403(env);
2704 gen_spr_403_real(env);
e1833e1f 2705 init_excp_4xx_real(env);
d63001d1
JM		 2706 env->dcache_line_size = 32;
2707 env->icache_line_size = 32;
4e290a0b
JM		 2708 /* Allocate hardware IRQ controller */
2709 ppc40x_irq_init(env);
d63001d1
JM		 2710#if !defined(CONFIG_USER_ONLY)
2711 /* Hardware reset vector */
2712 env->hreset_vector = 0xFFFFFFFCUL;
2713#endif
3fc6c082
FB		 2714}
2715
a750fc0b
JM		 2716/* PowerPC 403 GCX */
2717#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2718 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2719 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2720 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2721#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2722#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2723#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2724#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 2725#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
d26bfc9a 2726#define POWERPC_FLAG_403GCX (POWERPC_FLAG_NONE)
a750fc0b
JM		 2727
2728static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 2729{
a750fc0b
JM		 2730 gen_spr_40x(env);
2731 gen_spr_401_403(env);
2732 gen_spr_403(env);
2733 gen_spr_403_real(env);
2734 gen_spr_403_mmu(env);
2735 /* Bus access control */
035feb88 2736 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2737 spr_register(env, SPR_40x_SGR, "SGR",
2738 SPR_NOACCESS, SPR_NOACCESS,
2739 &spr_read_generic, &spr_write_generic,
2740 0xFFFFFFFF);
035feb88 2741 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2742 spr_register(env, SPR_40x_DCWR, "DCWR",
2743 SPR_NOACCESS, SPR_NOACCESS,
2744 &spr_read_generic, &spr_write_generic,
2745 0x00000000);
2746 /* Memory management */
2747 env->nb_tlb = 64;
2748 env->nb_ways = 1;
2749 env->id_tlbs = 0;
e1833e1f 2750 init_excp_4xx_softmmu(env);
d63001d1
JM		 2751 env->dcache_line_size = 32;
2752 env->icache_line_size = 32;
4e290a0b
JM		 2753 /* Allocate hardware IRQ controller */
2754 ppc40x_irq_init(env);
3fc6c082
FB		 2755}
2756
a750fc0b
JM		 2757/* PowerPC 405 */
2758#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2759 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2760 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2761 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2762 PPC_405_MAC)
2763#define POWERPC_MSRM_405 (0x000000000006E630ULL)
2764#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2765#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2766#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
237c0af0 2767#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
d26bfc9a 2768#define POWERPC_FLAG_405 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2769
2770static void init_proc_405 (CPUPPCState *env)
3fc6c082 2771{
a750fc0b
JM		 2772 /* Time base */
2773 gen_tbl(env);
2774 gen_spr_40x(env);
2775 gen_spr_405(env);
2776 /* Bus access control */
035feb88 2777 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2778 spr_register(env, SPR_40x_SGR, "SGR",
2779 SPR_NOACCESS, SPR_NOACCESS,
2780 &spr_read_generic, &spr_write_generic,
2781 0xFFFFFFFF);
035feb88 2782 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2783 spr_register(env, SPR_40x_DCWR, "DCWR",
2784 SPR_NOACCESS, SPR_NOACCESS,
2785 &spr_read_generic, &spr_write_generic,
2786 0x00000000);
2787 /* Memory management */
2788 env->nb_tlb = 64;
2789 env->nb_ways = 1;
2790 env->id_tlbs = 0;
e1833e1f 2791 init_excp_4xx_softmmu(env);
d63001d1
JM		 2792 env->dcache_line_size = 32;
2793 env->icache_line_size = 32;
a750fc0b 2794 /* Allocate hardware IRQ controller */
4e290a0b 2795 ppc40x_irq_init(env);
3fc6c082
FB		 2796}
2797
a750fc0b
JM		 2798/* PowerPC 440 EP */
2799#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2800 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2801 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2802 PPC_440_SPEC | PPC_RFMCI)
2803#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2804#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2805#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2806#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
237c0af0 2807#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
d26bfc9a 2808#define POWERPC_FLAG_440EP (POWERPC_FLAG_NONE)
a750fc0b
JM		 2809
2810static void init_proc_440EP (CPUPPCState *env)
3fc6c082 2811{
a750fc0b
JM		 2812 /* Time base */
2813 gen_tbl(env);
2814 gen_spr_BookE(env);
2815 gen_spr_440(env);
578bb252 2816 /* XXX : not implemented */
a750fc0b
JM		 2817 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2818 SPR_NOACCESS, SPR_NOACCESS,
2819 &spr_read_generic, &spr_write_generic,
2820 0x00000000);
2821 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2822 SPR_NOACCESS, SPR_NOACCESS,
2823 &spr_read_generic, &spr_write_generic,
2824 0x00000000);
2825 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2826 SPR_NOACCESS, SPR_NOACCESS,
2827 &spr_read_generic, &spr_write_generic,
2828 0x00000000);
578bb252 2829 /* XXX : not implemented */
a750fc0b
JM		 2830 spr_register(env, SPR_440_CCR1, "CCR1",
2831 SPR_NOACCESS, SPR_NOACCESS,
2832 &spr_read_generic, &spr_write_generic,
2833 0x00000000);
2834 /* Memory management */
2835 env->nb_tlb = 64;
2836 env->nb_ways = 1;
2837 env->id_tlbs = 0;
e1833e1f 2838 init_excp_BookE(env);
d63001d1
JM		 2839 env->dcache_line_size = 32;
2840 env->icache_line_size = 32;
a750fc0b 2841 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2842}
2843
a750fc0b
JM		 2844/* PowerPC 440 GP */
2845#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2846 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2847 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2848 PPC_405_MAC | PPC_440_SPEC)
2849#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2850#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2851#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2852#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
237c0af0 2853#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
d26bfc9a 2854#define POWERPC_FLAG_440GP (POWERPC_FLAG_NONE)
a750fc0b
JM		 2855
2856static void init_proc_440GP (CPUPPCState *env)
3fc6c082 2857{
a750fc0b
JM		 2858 /* Time base */
2859 gen_tbl(env);
2860 gen_spr_BookE(env);
2861 gen_spr_440(env);
2862 /* Memory management */
2863 env->nb_tlb = 64;
2864 env->nb_ways = 1;
2865 env->id_tlbs = 0;
e1833e1f 2866 init_excp_BookE(env);
d63001d1
JM		 2867 env->dcache_line_size = 32;
2868 env->icache_line_size = 32;
a750fc0b 2869 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2870}
2871
a750fc0b 2872/* PowerPC 440x4 */
a750fc0b
JM		 2873#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2874 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2875 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2876 PPC_440_SPEC)
2877#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2878#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2879#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2880#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
237c0af0 2881#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
d26bfc9a 2882#define POWERPC_FLAG_440x4 (POWERPC_FLAG_NONE)
a750fc0b 2883
578bb252 2884__attribute__ (( unused ))
a750fc0b 2885static void init_proc_440x4 (CPUPPCState *env)
3fc6c082 2886{
a750fc0b
JM		 2887 /* Time base */
2888 gen_tbl(env);
2889 gen_spr_BookE(env);
2890 gen_spr_440(env);
2891 /* Memory management */
2892 env->nb_tlb = 64;
2893 env->nb_ways = 1;
2894 env->id_tlbs = 0;
e1833e1f 2895 init_excp_BookE(env);
d63001d1
JM		 2896 env->dcache_line_size = 32;
2897 env->icache_line_size = 32;
a750fc0b 2898 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2899}
a750fc0b
JM		 2900
2901/* PowerPC 440x5 */
2902#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2903 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2904 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2905 PPC_440_SPEC | PPC_RFMCI)
2906#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2907#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2908#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2909#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
237c0af0 2910#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
d26bfc9a 2911#define POWERPC_FLAG_440x5 (POWERPC_FLAG_NONE)
a750fc0b
JM		 2912
2913static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 2914{
a750fc0b
JM		 2915 /* Time base */
2916 gen_tbl(env);
2917 gen_spr_BookE(env);
2918 gen_spr_440(env);
578bb252 2919 /* XXX : not implemented */
a750fc0b
JM		 2920 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2921 SPR_NOACCESS, SPR_NOACCESS,
2922 &spr_read_generic, &spr_write_generic,
2923 0x00000000);
2924 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2925 SPR_NOACCESS, SPR_NOACCESS,
2926 &spr_read_generic, &spr_write_generic,
2927 0x00000000);
2928 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2929 SPR_NOACCESS, SPR_NOACCESS,
2930 &spr_read_generic, &spr_write_generic,
2931 0x00000000);
578bb252 2932 /* XXX : not implemented */
a750fc0b
JM		 2933 spr_register(env, SPR_440_CCR1, "CCR1",
2934 SPR_NOACCESS, SPR_NOACCESS,
2935 &spr_read_generic, &spr_write_generic,
2936 0x00000000);
2937 /* Memory management */
2938 env->nb_tlb = 64;
2939 env->nb_ways = 1;
2940 env->id_tlbs = 0;
e1833e1f 2941 init_excp_BookE(env);
d63001d1
JM		 2942 env->dcache_line_size = 32;
2943 env->icache_line_size = 32;
a750fc0b 2944 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2945}
2946
a750fc0b 2947/* PowerPC 460 (guessed) */
578bb252 2948#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
a750fc0b
JM		 2949 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2950 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2951 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2952#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2953#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2954#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2955#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
237c0af0 2956#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
d26bfc9a 2957#define POWERPC_FLAG_460 (POWERPC_FLAG_NONE)
a750fc0b 2958
578bb252 2959__attribute__ (( unused ))
a750fc0b 2960static void init_proc_460 (CPUPPCState *env)
3fc6c082 2961{
e1833e1f
JM		 2962 /* Time base */
2963 gen_tbl(env);
2964 gen_spr_BookE(env);
2965 gen_spr_440(env);
578bb252 2966 /* XXX : not implemented */
e1833e1f
JM		 2967 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2968 SPR_NOACCESS, SPR_NOACCESS,
2969 &spr_read_generic, &spr_write_generic,
2970 0x00000000);
2971 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2972 SPR_NOACCESS, SPR_NOACCESS,
2973 &spr_read_generic, &spr_write_generic,
2974 0x00000000);
2975 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2976 SPR_NOACCESS, SPR_NOACCESS,
2977 &spr_read_generic, &spr_write_generic,
2978 0x00000000);
578bb252 2979 /* XXX : not implemented */
e1833e1f
JM		 2980 spr_register(env, SPR_440_CCR1, "CCR1",
2981 SPR_NOACCESS, SPR_NOACCESS,
2982 &spr_read_generic, &spr_write_generic,
2983 0x00000000);
578bb252 2984 /* XXX : not implemented */
e1833e1f
JM		 2985 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2986 &spr_read_generic, &spr_write_generic,
2987 &spr_read_generic, &spr_write_generic,
2988 0x00000000);
2989 /* Memory management */
2990 env->nb_tlb = 64;
2991 env->nb_ways = 1;
2992 env->id_tlbs = 0;
2993 init_excp_BookE(env);
d63001d1
JM		 2994 env->dcache_line_size = 32;
2995 env->icache_line_size = 32;
e1833e1f 2996 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2997}
a750fc0b
JM		 2998
2999/* PowerPC 460F (guessed) */
a750fc0b
JM		 3000#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3001 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3002 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3003 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3004 PPC_FLOAT_STFIWX | \
3005 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3006 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3007#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3008#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3009#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3010#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
237c0af0 3011#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
d26bfc9a 3012#define POWERPC_FLAG_460F (POWERPC_FLAG_NONE)
a750fc0b 3013
578bb252 3014__attribute__ (( unused ))
e1833e1f 3015static void init_proc_460F (CPUPPCState *env)
3fc6c082 3016{
a750fc0b
JM		 3017 /* Time base */
3018 gen_tbl(env);
3019 gen_spr_BookE(env);
3020 gen_spr_440(env);
578bb252 3021 /* XXX : not implemented */
a750fc0b
JM		 3022 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3023 SPR_NOACCESS, SPR_NOACCESS,
3024 &spr_read_generic, &spr_write_generic,
3025 0x00000000);
3026 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3027 SPR_NOACCESS, SPR_NOACCESS,
3028 &spr_read_generic, &spr_write_generic,
3029 0x00000000);
3030 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3031 SPR_NOACCESS, SPR_NOACCESS,
3032 &spr_read_generic, &spr_write_generic,
3033 0x00000000);
578bb252 3034 /* XXX : not implemented */
a750fc0b
JM		 3035 spr_register(env, SPR_440_CCR1, "CCR1",
3036 SPR_NOACCESS, SPR_NOACCESS,
3037 &spr_read_generic, &spr_write_generic,
3038 0x00000000);
578bb252 3039 /* XXX : not implemented */
a750fc0b
JM		 3040 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3041 &spr_read_generic, &spr_write_generic,
3042 &spr_read_generic, &spr_write_generic,
3043 0x00000000);
3044 /* Memory management */
3045 env->nb_tlb = 64;
3046 env->nb_ways = 1;
3047 env->id_tlbs = 0;
e1833e1f 3048 init_excp_BookE(env);
d63001d1
JM		 3049 env->dcache_line_size = 32;
3050 env->icache_line_size = 32;
a750fc0b 3051 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3052}
a750fc0b
JM		 3053
3054/* Generic BookE PowerPC */
a750fc0b
JM		 3055#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3056 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3057 PPC_CACHE_DCBA | \
3058 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3059 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3060 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3061 PPC_BOOKE)
3062#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3063#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3064#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3065#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
237c0af0 3066#define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
d26bfc9a 3067#define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
a750fc0b 3068
578bb252 3069__attribute__ (( unused ))
a750fc0b 3070static void init_proc_BookE (CPUPPCState *env)
3fc6c082 3071{
e1833e1f 3072 init_excp_BookE(env);
d63001d1
JM		 3073 env->dcache_line_size = 32;
3074 env->icache_line_size = 32;
3fc6c082 3075}
a750fc0b
JM		 3076
3077/* e200 core */
a750fc0b
JM		 3078
3079/* e300 core */
a750fc0b
JM		 3080
3081/* e500 core */
a750fc0b
JM		 3082#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3083 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3084 PPC_CACHE_DCBA | \
3085 PPC_BOOKE | PPC_E500_VECTOR)
3086#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3087#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3088#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
237c0af0 3089#define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
d26bfc9a 3090#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
a750fc0b 3091
578bb252 3092__attribute__ (( unused ))
a750fc0b 3093static void init_proc_e500 (CPUPPCState *env)
3fc6c082 3094{
a750fc0b
JM		 3095 /* Time base */
3096 gen_tbl(env);
3097 gen_spr_BookE(env);
3098 /* Memory management */
3099 gen_spr_BookE_FSL(env);
3100 env->nb_tlb = 64;
3101 env->nb_ways = 1;
3102 env->id_tlbs = 0;
e1833e1f 3103 init_excp_BookE(env);
d63001d1
JM		 3104 env->dcache_line_size = 32;
3105 env->icache_line_size = 32;
a750fc0b 3106 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3107}
a750fc0b
JM		 3108
3109/* e600 core */
a750fc0b
JM		 3110
3111/* Non-embedded PowerPC */
3112/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3113#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
12de9a39 3114 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
a750fc0b
JM		 3115/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3116#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3117 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3118 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
12de9a39
JM		 3119 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3120 PPC_SEGMENT)
a750fc0b
JM		 3121
3122/* POWER : same as 601, without mfmsr, mfsr */
3123#if defined(TODO)
3124#define POWERPC_INSNS_POWER (XXX_TODO)
3125/* POWER RSC (from RAD6000) */
3126#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3127#endif /* TODO */
3128
3129/* PowerPC 601 */
d63001d1 3130#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
12de9a39 3131 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
a750fc0b
JM		 3132#define POWERPC_MSRM_601 (0x000000000000FE70ULL)
3133//#define POWERPC_MMU_601 (POWERPC_MMU_601)
3134//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3135#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 3136#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
d26bfc9a 3137#define POWERPC_FLAG_601 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3138
3139static void init_proc_601 (CPUPPCState *env)
3fc6c082 3140{
a750fc0b
JM		 3141 gen_spr_ne_601(env);
3142 gen_spr_601(env);
3143 /* Hardware implementation registers */
3144 /* XXX : not implemented */
3145 spr_register(env, SPR_HID0, "HID0",
3146 SPR_NOACCESS, SPR_NOACCESS,
3147 &spr_read_generic, &spr_write_generic,
3148 0x00000000);
3149 /* XXX : not implemented */
3150 spr_register(env, SPR_HID1, "HID1",
3151 SPR_NOACCESS, SPR_NOACCESS,
3152 &spr_read_generic, &spr_write_generic,
3153 0x00000000);
3154 /* XXX : not implemented */
3155 spr_register(env, SPR_601_HID2, "HID2",
3156 SPR_NOACCESS, SPR_NOACCESS,
3157 &spr_read_generic, &spr_write_generic,
3158 0x00000000);
3159 /* XXX : not implemented */
3160 spr_register(env, SPR_601_HID5, "HID5",
3161 SPR_NOACCESS, SPR_NOACCESS,
3162 &spr_read_generic, &spr_write_generic,
3163 0x00000000);
3164 /* XXX : not implemented */
3165 spr_register(env, SPR_601_HID15, "HID15",
3166 SPR_NOACCESS, SPR_NOACCESS,
3167 &spr_read_generic, &spr_write_generic,
3168 0x00000000);
3169 /* Memory management */
3170 env->nb_tlb = 64;
3171 env->nb_ways = 2;
3172 env->id_tlbs = 0;
3173 env->id_tlbs = 0;
e1833e1f 3174 init_excp_601(env);
d63001d1
JM		 3175 env->dcache_line_size = 64;
3176 env->icache_line_size = 64;
a750fc0b 3177 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3178}
3179
a750fc0b
JM		 3180/* PowerPC 602 */
3181#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3182 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3183 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
d63001d1 3184 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
12de9a39 3185 PPC_SEGMENT | PPC_602_SPEC)
a750fc0b
JM		 3186#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3187#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3188//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3189#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 3190#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
d26bfc9a 3191#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3192
3193static void init_proc_602 (CPUPPCState *env)
3fc6c082 3194{
a750fc0b
JM		 3195 gen_spr_ne_601(env);
3196 gen_spr_602(env);
3197 /* Time base */
3198 gen_tbl(env);
3199 /* hardware implementation registers */
3200 /* XXX : not implemented */
3201 spr_register(env, SPR_HID0, "HID0",
3202 SPR_NOACCESS, SPR_NOACCESS,
3203 &spr_read_generic, &spr_write_generic,
3204 0x00000000);
3205 /* XXX : not implemented */
3206 spr_register(env, SPR_HID1, "HID1",
3207 SPR_NOACCESS, SPR_NOACCESS,
3208 &spr_read_generic, &spr_write_generic,
3209 0x00000000);
3210 /* Memory management */
3211 gen_low_BATs(env);
3212 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3213 init_excp_602(env);
d63001d1
JM		 3214 env->dcache_line_size = 32;
3215 env->icache_line_size = 32;
a750fc0b
JM		 3216 /* Allocate hardware IRQ controller */
3217 ppc6xx_irq_init(env);
3218}
3fc6c082 3219
a750fc0b
JM		 3220/* PowerPC 603 */
3221#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3222#define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3223#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3224//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3225#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 3226#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
d26bfc9a 3227#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3228
3229static void init_proc_603 (CPUPPCState *env)
3230{
3231 gen_spr_ne_601(env);
3232 gen_spr_603(env);
3233 /* Time base */
3234 gen_tbl(env);
3235 /* hardware implementation registers */
3236 /* XXX : not implemented */
3237 spr_register(env, SPR_HID0, "HID0",
3238 SPR_NOACCESS, SPR_NOACCESS,
3239 &spr_read_generic, &spr_write_generic,
3240 0x00000000);
3241 /* XXX : not implemented */
3242 spr_register(env, SPR_HID1, "HID1",
3243 SPR_NOACCESS, SPR_NOACCESS,
3244 &spr_read_generic, &spr_write_generic,
3245 0x00000000);
3246 /* Memory management */
3247 gen_low_BATs(env);
3248 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3249 init_excp_603(env);
d63001d1
JM		 3250 env->dcache_line_size = 32;
3251 env->icache_line_size = 32;
a750fc0b
JM		 3252 /* Allocate hardware IRQ controller */
3253 ppc6xx_irq_init(env);
3fc6c082
FB		 3254}
3255
a750fc0b
JM		 3256/* PowerPC 603e */
3257#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3258#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3259#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3260//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3261#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 3262#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
d26bfc9a 3263#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3264
3265static void init_proc_603E (CPUPPCState *env)
3266{
3267 gen_spr_ne_601(env);
3268 gen_spr_603(env);
3269 /* Time base */
3270 gen_tbl(env);
3271 /* hardware implementation registers */
3272 /* XXX : not implemented */
3273 spr_register(env, SPR_HID0, "HID0",
3274 SPR_NOACCESS, SPR_NOACCESS,
3275 &spr_read_generic, &spr_write_generic,
3276 0x00000000);
3277 /* XXX : not implemented */
3278 spr_register(env, SPR_HID1, "HID1",
3279 SPR_NOACCESS, SPR_NOACCESS,
3280 &spr_read_generic, &spr_write_generic,
3281 0x00000000);
3282 /* XXX : not implemented */
3283 spr_register(env, SPR_IABR, "IABR",
3284 SPR_NOACCESS, SPR_NOACCESS,
3285 &spr_read_generic, &spr_write_generic,
3286 0x00000000);
3287 /* Memory management */
3288 gen_low_BATs(env);
3289 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3290 init_excp_603(env);
d63001d1
JM		 3291 env->dcache_line_size = 32;
3292 env->icache_line_size = 32;
a750fc0b
JM		 3293 /* Allocate hardware IRQ controller */
3294 ppc6xx_irq_init(env);
3295}
3296
3297/* PowerPC G2 */
3298#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3299#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3300#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3301//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3302#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
237c0af0 3303#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
d26bfc9a 3304#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3305
3306static void init_proc_G2 (CPUPPCState *env)
3307{
3308 gen_spr_ne_601(env);
3309 gen_spr_G2_755(env);
3310 gen_spr_G2(env);
3311 /* Time base */
3312 gen_tbl(env);
3313 /* Hardware implementation register */
3314 /* XXX : not implemented */
3315 spr_register(env, SPR_HID0, "HID0",
3316 SPR_NOACCESS, SPR_NOACCESS,
3317 &spr_read_generic, &spr_write_generic,
3318 0x00000000);
3319 /* XXX : not implemented */
3320 spr_register(env, SPR_HID1, "HID1",
3321 SPR_NOACCESS, SPR_NOACCESS,
3322 &spr_read_generic, &spr_write_generic,
3323 0x00000000);
3324 /* XXX : not implemented */
3325 spr_register(env, SPR_HID2, "HID2",
3326 SPR_NOACCESS, SPR_NOACCESS,
3327 &spr_read_generic, &spr_write_generic,
3328 0x00000000);
3329 /* Memory management */
3330 gen_low_BATs(env);
3331 gen_high_BATs(env);
3332 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3333 init_excp_G2(env);
d63001d1
JM		 3334 env->dcache_line_size = 32;
3335 env->icache_line_size = 32;
a750fc0b
JM		 3336 /* Allocate hardware IRQ controller */
3337 ppc6xx_irq_init(env);
3338}
3339
3340/* PowerPC G2LE */
3341#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3342#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3343#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3344#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3345#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
237c0af0 3346#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
d26bfc9a 3347#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR)
a750fc0b
JM		 3348
3349static void init_proc_G2LE (CPUPPCState *env)
3350{
3351 gen_spr_ne_601(env);
3352 gen_spr_G2_755(env);
3353 gen_spr_G2(env);
3354 /* Time base */
3355 gen_tbl(env);
3356 /* Hardware implementation register */
3357 /* XXX : not implemented */
3358 spr_register(env, SPR_HID0, "HID0",
3359 SPR_NOACCESS, SPR_NOACCESS,
3360 &spr_read_generic, &spr_write_generic,
3361 0x00000000);
3362 /* XXX : not implemented */
3363 spr_register(env, SPR_HID1, "HID1",
3364 SPR_NOACCESS, SPR_NOACCESS,
3365 &spr_read_generic, &spr_write_generic,
3366 0x00000000);
3367 /* XXX : not implemented */
3368 spr_register(env, SPR_HID2, "HID2",
3369 SPR_NOACCESS, SPR_NOACCESS,
3370 &spr_read_generic, &spr_write_generic,
3371 0x00000000);
3372 /* Memory management */
3373 gen_low_BATs(env);
3374 gen_high_BATs(env);
3375 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3376 init_excp_G2(env);
d63001d1
JM		 3377 env->dcache_line_size = 32;
3378 env->icache_line_size = 32;
a750fc0b
JM		 3379 /* Allocate hardware IRQ controller */
3380 ppc6xx_irq_init(env);
3381}
3382
3383/* PowerPC 604 */
3384#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3385#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3386#define POWERPC_MMU_604 (POWERPC_MMU_32B)
3387//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3388#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 3389#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
d26bfc9a 3390#define POWERPC_FLAG_604 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3391
3392static void init_proc_604 (CPUPPCState *env)
3393{
3394 gen_spr_ne_601(env);
3395 gen_spr_604(env);
3396 /* Time base */
3397 gen_tbl(env);
3398 /* Hardware implementation registers */
3399 /* XXX : not implemented */
3400 spr_register(env, SPR_HID0, "HID0",
3401 SPR_NOACCESS, SPR_NOACCESS,
3402 &spr_read_generic, &spr_write_generic,
3403 0x00000000);
3404 /* XXX : not implemented */
3405 spr_register(env, SPR_HID1, "HID1",
3406 SPR_NOACCESS, SPR_NOACCESS,
3407 &spr_read_generic, &spr_write_generic,
3408 0x00000000);
3409 /* Memory management */
3410 gen_low_BATs(env);
e1833e1f 3411 init_excp_604(env);
d63001d1
JM		 3412 env->dcache_line_size = 32;
3413 env->icache_line_size = 32;
a750fc0b
JM		 3414 /* Allocate hardware IRQ controller */
3415 ppc6xx_irq_init(env);
3416}
3417
3418/* PowerPC 740/750 (aka G3) */
3419#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3420#define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3421#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3422//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3423#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 3424#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
d26bfc9a 3425#define POWERPC_FLAG_7x0 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3426
3427static void init_proc_7x0 (CPUPPCState *env)
3428{
3429 gen_spr_ne_601(env);
3430 gen_spr_7xx(env);
3431 /* Time base */
3432 gen_tbl(env);
3433 /* Thermal management */
3434 gen_spr_thrm(env);
3435 /* Hardware implementation registers */
3436 /* XXX : not implemented */
3437 spr_register(env, SPR_HID0, "HID0",
3438 SPR_NOACCESS, SPR_NOACCESS,
3439 &spr_read_generic, &spr_write_generic,
3440 0x00000000);
3441 /* XXX : not implemented */
3442 spr_register(env, SPR_HID1, "HID1",
3443 SPR_NOACCESS, SPR_NOACCESS,
3444 &spr_read_generic, &spr_write_generic,
3445 0x00000000);
3446 /* Memory management */
3447 gen_low_BATs(env);
e1833e1f 3448 init_excp_7x0(env);
d63001d1
JM		 3449 env->dcache_line_size = 32;
3450 env->icache_line_size = 32;
a750fc0b
JM		 3451 /* Allocate hardware IRQ controller */
3452 ppc6xx_irq_init(env);
3453}
3454
3455/* PowerPC 750FX/GX */
3456#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3457#define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3458#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3459#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3460#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 3461#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
d26bfc9a 3462#define POWERPC_FLAG_750fx (POWERPC_FLAG_NONE)
a750fc0b
JM		 3463
3464static void init_proc_750fx (CPUPPCState *env)
3465{
3466 gen_spr_ne_601(env);
3467 gen_spr_7xx(env);
3468 /* Time base */
3469 gen_tbl(env);
3470 /* Thermal management */
3471 gen_spr_thrm(env);
3472 /* Hardware implementation registers */
3473 /* XXX : not implemented */
3474 spr_register(env, SPR_HID0, "HID0",
3475 SPR_NOACCESS, SPR_NOACCESS,
3476 &spr_read_generic, &spr_write_generic,
3477 0x00000000);
3478 /* XXX : not implemented */
3479 spr_register(env, SPR_HID1, "HID1",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, &spr_write_generic,
3482 0x00000000);
3483 /* XXX : not implemented */
3484 spr_register(env, SPR_750_HID2, "HID2",
3485 SPR_NOACCESS, SPR_NOACCESS,
3486 &spr_read_generic, &spr_write_generic,
3487 0x00000000);
3488 /* Memory management */
3489 gen_low_BATs(env);
3490 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3491 gen_high_BATs(env);
e1833e1f 3492 init_excp_750FX(env);
d63001d1
JM		 3493 env->dcache_line_size = 32;
3494 env->icache_line_size = 32;
a750fc0b
JM		 3495 /* Allocate hardware IRQ controller */
3496 ppc6xx_irq_init(env);
3497}
3498
3499/* PowerPC 745/755 */
3500#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3501#define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3502#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3503//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3504#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 3505#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
d26bfc9a 3506#define POWERPC_FLAG_7x5 (POWERPC_FLAG_NONE)
a750fc0b
JM		 3507
3508static void init_proc_7x5 (CPUPPCState *env)
3509{
3510 gen_spr_ne_601(env);
3511 gen_spr_G2_755(env);
3512 /* Time base */
3513 gen_tbl(env);
3514 /* L2 cache control */
3515 /* XXX : not implemented */
3516 spr_register(env, SPR_ICTC, "ICTC",
3517 SPR_NOACCESS, SPR_NOACCESS,
3518 &spr_read_generic, &spr_write_generic,
3519 0x00000000);
3520 /* XXX : not implemented */
3521 spr_register(env, SPR_L2PMCR, "L2PMCR",
3522 SPR_NOACCESS, SPR_NOACCESS,
3523 &spr_read_generic, &spr_write_generic,
3524 0x00000000);
3525 /* Hardware implementation registers */
3526 /* XXX : not implemented */
3527 spr_register(env, SPR_HID0, "HID0",
3528 SPR_NOACCESS, SPR_NOACCESS,
3529 &spr_read_generic, &spr_write_generic,
3530 0x00000000);
3531 /* XXX : not implemented */
3532 spr_register(env, SPR_HID1, "HID1",
3533 SPR_NOACCESS, SPR_NOACCESS,
3534 &spr_read_generic, &spr_write_generic,
3535 0x00000000);
3536 /* XXX : not implemented */
3537 spr_register(env, SPR_HID2, "HID2",
3538 SPR_NOACCESS, SPR_NOACCESS,
3539 &spr_read_generic, &spr_write_generic,
3540 0x00000000);
3541 /* Memory management */
3542 gen_low_BATs(env);
3543 gen_high_BATs(env);
3544 gen_6xx_7xx_soft_tlb(env, 64, 2);
1c27f8fb 3545 /* XXX: exception vectors ? */
d63001d1
JM		 3546 env->dcache_line_size = 32;
3547 env->icache_line_size = 32;
a750fc0b
JM		 3548 /* Allocate hardware IRQ controller */
3549 ppc6xx_irq_init(env);
d63001d1
JM		 3550#if !defined(CONFIG_USER_ONLY)
3551 /* Hardware reset vector */
3552 env->hreset_vector = 0xFFFFFFFCUL;
3553#endif
a750fc0b
JM		 3554}
3555
3556/* PowerPC 7400 (aka G4) */
3557#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3558 PPC_EXTERN | PPC_MEM_TLBIA | \
3559 PPC_ALTIVEC)
3560#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3561#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3562#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3563#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 3564#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
d26bfc9a 3565#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE)
a750fc0b
JM		 3566
3567static void init_proc_7400 (CPUPPCState *env)
3568{
3569 gen_spr_ne_601(env);
3570 gen_spr_7xx(env);
3571 /* Time base */
3572 gen_tbl(env);
3573 /* 74xx specific SPR */
3574 gen_spr_74xx(env);
3575 /* Thermal management */
3576 gen_spr_thrm(env);
3577 /* Memory management */
3578 gen_low_BATs(env);
e1833e1f 3579 init_excp_7400(env);
d63001d1
JM		 3580 env->dcache_line_size = 32;
3581 env->icache_line_size = 32;
a750fc0b
JM		 3582 /* Allocate hardware IRQ controller */
3583 ppc6xx_irq_init(env);
3584}
3585
3586/* PowerPC 7410 (aka G4) */
3587#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3588 PPC_EXTERN | PPC_MEM_TLBIA | \
3589 PPC_ALTIVEC)
3590#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3591#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3592#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3593#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 3594#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
d26bfc9a 3595#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE)
a750fc0b
JM		 3596
3597static void init_proc_7410 (CPUPPCState *env)
3598{
3599 gen_spr_ne_601(env);
3600 gen_spr_7xx(env);
3601 /* Time base */
3602 gen_tbl(env);
3603 /* 74xx specific SPR */
3604 gen_spr_74xx(env);
3605 /* Thermal management */
3606 gen_spr_thrm(env);
3607 /* L2PMCR */
3608 /* XXX : not implemented */
3609 spr_register(env, SPR_L2PMCR, "L2PMCR",
3610 SPR_NOACCESS, SPR_NOACCESS,
3611 &spr_read_generic, &spr_write_generic,
3612 0x00000000);
3613 /* LDSTDB */
3614 /* XXX : not implemented */
3615 spr_register(env, SPR_LDSTDB, "LDSTDB",
3616 SPR_NOACCESS, SPR_NOACCESS,
3617 &spr_read_generic, &spr_write_generic,
3618 0x00000000);
3619 /* Memory management */
3620 gen_low_BATs(env);
e1833e1f 3621 init_excp_7400(env);
d63001d1
JM		 3622 env->dcache_line_size = 32;
3623 env->icache_line_size = 32;
a750fc0b
JM		 3624 /* Allocate hardware IRQ controller */
3625 ppc6xx_irq_init(env);
3626}
3627
3628/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 3629#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3630 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3631 PPC_ALTIVEC)
3632#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3633#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3634#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3635#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 3636#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
d26bfc9a 3637#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE)
a750fc0b 3638
578bb252 3639__attribute__ (( unused ))
a750fc0b
JM		 3640static void init_proc_7440 (CPUPPCState *env)
3641{
3642 gen_spr_ne_601(env);
3643 gen_spr_7xx(env);
3644 /* Time base */
3645 gen_tbl(env);
3646 /* 74xx specific SPR */
3647 gen_spr_74xx(env);
3648 /* LDSTCR */
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_LDSTCR, "LDSTCR",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* ICTRL */
3655 /* XXX : not implemented */
3656 spr_register(env, SPR_ICTRL, "ICTRL",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_generic,
3659 0x00000000);
3660 /* MSSSR0 */
578bb252 3661 /* XXX : not implemented */
a750fc0b
JM		 3662 spr_register(env, SPR_MSSSR0, "MSSSR0",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 /* PMC */
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_PMC5, "PMC5",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
578bb252 3672 /* XXX : not implemented */
a750fc0b
JM		 3673 spr_register(env, SPR_UPMC5, "UPMC5",
3674 &spr_read_ureg, SPR_NOACCESS,
3675 &spr_read_ureg, SPR_NOACCESS,
3676 0x00000000);
578bb252 3677 /* XXX : not implemented */
a750fc0b
JM		 3678 spr_register(env, SPR_PMC6, "PMC6",
3679 SPR_NOACCESS, SPR_NOACCESS,
3680 &spr_read_generic, &spr_write_generic,
3681 0x00000000);
578bb252 3682 /* XXX : not implemented */
a750fc0b
JM		 3683 spr_register(env, SPR_UPMC6, "UPMC6",
3684 &spr_read_ureg, SPR_NOACCESS,
3685 &spr_read_ureg, SPR_NOACCESS,
3686 0x00000000);
3687 /* Memory management */
3688 gen_low_BATs(env);
578bb252 3689 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 3690 init_excp_7450(env);
d63001d1
JM		 3691 env->dcache_line_size = 32;
3692 env->icache_line_size = 32;
a750fc0b
JM		 3693 /* Allocate hardware IRQ controller */
3694 ppc6xx_irq_init(env);
3695}
a750fc0b
JM		 3696
3697/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 3698#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3699 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3700 PPC_ALTIVEC)
3701#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3702#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3703#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3704#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 3705#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
d26bfc9a 3706#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE)
a750fc0b 3707
578bb252 3708__attribute__ (( unused ))
a750fc0b
JM		 3709static void init_proc_7450 (CPUPPCState *env)
3710{
3711 gen_spr_ne_601(env);
3712 gen_spr_7xx(env);
3713 /* Time base */
3714 gen_tbl(env);
3715 /* 74xx specific SPR */
3716 gen_spr_74xx(env);
3717 /* Level 3 cache control */
3718 gen_l3_ctrl(env);
3719 /* LDSTCR */
3720 /* XXX : not implemented */
3721 spr_register(env, SPR_LDSTCR, "LDSTCR",
3722 SPR_NOACCESS, SPR_NOACCESS,
3723 &spr_read_generic, &spr_write_generic,
3724 0x00000000);
3725 /* ICTRL */
3726 /* XXX : not implemented */
3727 spr_register(env, SPR_ICTRL, "ICTRL",
3728 SPR_NOACCESS, SPR_NOACCESS,
3729 &spr_read_generic, &spr_write_generic,
3730 0x00000000);
3731 /* MSSSR0 */
578bb252 3732 /* XXX : not implemented */
a750fc0b
JM		 3733 spr_register(env, SPR_MSSSR0, "MSSSR0",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 /* PMC */
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_PMC5, "PMC5",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
578bb252 3743 /* XXX : not implemented */
a750fc0b
JM		 3744 spr_register(env, SPR_UPMC5, "UPMC5",
3745 &spr_read_ureg, SPR_NOACCESS,
3746 &spr_read_ureg, SPR_NOACCESS,
3747 0x00000000);
578bb252 3748 /* XXX : not implemented */
a750fc0b
JM		 3749 spr_register(env, SPR_PMC6, "PMC6",
3750 SPR_NOACCESS, SPR_NOACCESS,
3751 &spr_read_generic, &spr_write_generic,
3752 0x00000000);
578bb252 3753 /* XXX : not implemented */
a750fc0b
JM		 3754 spr_register(env, SPR_UPMC6, "UPMC6",
3755 &spr_read_ureg, SPR_NOACCESS,
3756 &spr_read_ureg, SPR_NOACCESS,
3757 0x00000000);
3758 /* Memory management */
3759 gen_low_BATs(env);
578bb252 3760 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3761 init_excp_7450(env);
d63001d1
JM		 3762 env->dcache_line_size = 32;
3763 env->icache_line_size = 32;
a750fc0b
JM		 3764 /* Allocate hardware IRQ controller */
3765 ppc6xx_irq_init(env);
3766}
a750fc0b
JM		 3767
3768/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 3769#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3770 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3771 PPC_ALTIVEC)
3772#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3773#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3774#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3775#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 3776#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
d26bfc9a 3777#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE)
a750fc0b 3778
578bb252 3779__attribute__ (( unused ))
a750fc0b
JM		 3780static void init_proc_7445 (CPUPPCState *env)
3781{
3782 gen_spr_ne_601(env);
3783 gen_spr_7xx(env);
3784 /* Time base */
3785 gen_tbl(env);
3786 /* 74xx specific SPR */
3787 gen_spr_74xx(env);
3788 /* LDSTCR */
3789 /* XXX : not implemented */
3790 spr_register(env, SPR_LDSTCR, "LDSTCR",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_generic,
3793 0x00000000);
3794 /* ICTRL */
3795 /* XXX : not implemented */
3796 spr_register(env, SPR_ICTRL, "ICTRL",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
3800 /* MSSSR0 */
578bb252 3801 /* XXX : not implemented */
a750fc0b
JM		 3802 spr_register(env, SPR_MSSSR0, "MSSSR0",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 /* PMC */
3807 /* XXX : not implemented */
3808 spr_register(env, SPR_PMC5, "PMC5",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_generic,
3811 0x00000000);
578bb252 3812 /* XXX : not implemented */
a750fc0b
JM		 3813 spr_register(env, SPR_UPMC5, "UPMC5",
3814 &spr_read_ureg, SPR_NOACCESS,
3815 &spr_read_ureg, SPR_NOACCESS,
3816 0x00000000);
578bb252 3817 /* XXX : not implemented */
a750fc0b
JM		 3818 spr_register(env, SPR_PMC6, "PMC6",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
578bb252 3822 /* XXX : not implemented */
a750fc0b
JM		 3823 spr_register(env, SPR_UPMC6, "UPMC6",
3824 &spr_read_ureg, SPR_NOACCESS,
3825 &spr_read_ureg, SPR_NOACCESS,
3826 0x00000000);
3827 /* SPRGs */
3828 spr_register(env, SPR_SPRG4, "SPRG4",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832 spr_register(env, SPR_USPRG4, "USPRG4",
3833 &spr_read_ureg, SPR_NOACCESS,
3834 &spr_read_ureg, SPR_NOACCESS,
3835 0x00000000);
3836 spr_register(env, SPR_SPRG5, "SPRG5",
3837 SPR_NOACCESS, SPR_NOACCESS,
3838 &spr_read_generic, &spr_write_generic,
3839 0x00000000);
3840 spr_register(env, SPR_USPRG5, "USPRG5",
3841 &spr_read_ureg, SPR_NOACCESS,
3842 &spr_read_ureg, SPR_NOACCESS,
3843 0x00000000);
3844 spr_register(env, SPR_SPRG6, "SPRG6",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 spr_register(env, SPR_USPRG6, "USPRG6",
3849 &spr_read_ureg, SPR_NOACCESS,
3850 &spr_read_ureg, SPR_NOACCESS,
3851 0x00000000);
3852 spr_register(env, SPR_SPRG7, "SPRG7",
3853 SPR_NOACCESS, SPR_NOACCESS,
3854 &spr_read_generic, &spr_write_generic,
3855 0x00000000);
3856 spr_register(env, SPR_USPRG7, "USPRG7",
3857 &spr_read_ureg, SPR_NOACCESS,
3858 &spr_read_ureg, SPR_NOACCESS,
3859 0x00000000);
3860 /* Memory management */
3861 gen_low_BATs(env);
3862 gen_high_BATs(env);
578bb252 3863 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3864 init_excp_7450(env);
d63001d1
JM		 3865 env->dcache_line_size = 32;
3866 env->icache_line_size = 32;
a750fc0b
JM		 3867 /* Allocate hardware IRQ controller */
3868 ppc6xx_irq_init(env);
3869}
a750fc0b
JM		 3870
3871/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 3872#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3873 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3874 PPC_ALTIVEC)
3875#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3876#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3877#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3878#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 3879#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
d26bfc9a 3880#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE)
a750fc0b 3881
578bb252 3882__attribute__ (( unused ))
a750fc0b
JM		 3883static void init_proc_7455 (CPUPPCState *env)
3884{
3885 gen_spr_ne_601(env);
3886 gen_spr_7xx(env);
3887 /* Time base */
3888 gen_tbl(env);
3889 /* 74xx specific SPR */
3890 gen_spr_74xx(env);
3891 /* Level 3 cache control */
3892 gen_l3_ctrl(env);
3893 /* LDSTCR */
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_LDSTCR, "LDSTCR",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 /* ICTRL */
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_ICTRL, "ICTRL",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 /* MSSSR0 */
578bb252 3906 /* XXX : not implemented */
a750fc0b
JM		 3907 spr_register(env, SPR_MSSSR0, "MSSSR0",
3908 SPR_NOACCESS, SPR_NOACCESS,
3909 &spr_read_generic, &spr_write_generic,
3910 0x00000000);
3911 /* PMC */
3912 /* XXX : not implemented */
3913 spr_register(env, SPR_PMC5, "PMC5",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
578bb252 3917 /* XXX : not implemented */
a750fc0b
JM		 3918 spr_register(env, SPR_UPMC5, "UPMC5",
3919 &spr_read_ureg, SPR_NOACCESS,
3920 &spr_read_ureg, SPR_NOACCESS,
3921 0x00000000);
578bb252 3922 /* XXX : not implemented */
a750fc0b
JM		 3923 spr_register(env, SPR_PMC6, "PMC6",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
578bb252 3927 /* XXX : not implemented */
a750fc0b
JM		 3928 spr_register(env, SPR_UPMC6, "UPMC6",
3929 &spr_read_ureg, SPR_NOACCESS,
3930 &spr_read_ureg, SPR_NOACCESS,
3931 0x00000000);
3932 /* SPRGs */
3933 spr_register(env, SPR_SPRG4, "SPRG4",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 spr_register(env, SPR_USPRG4, "USPRG4",
3938 &spr_read_ureg, SPR_NOACCESS,
3939 &spr_read_ureg, SPR_NOACCESS,
3940 0x00000000);
3941 spr_register(env, SPR_SPRG5, "SPRG5",
3942 SPR_NOACCESS, SPR_NOACCESS,
3943 &spr_read_generic, &spr_write_generic,
3944 0x00000000);
3945 spr_register(env, SPR_USPRG5, "USPRG5",
3946 &spr_read_ureg, SPR_NOACCESS,
3947 &spr_read_ureg, SPR_NOACCESS,
3948 0x00000000);
3949 spr_register(env, SPR_SPRG6, "SPRG6",
3950 SPR_NOACCESS, SPR_NOACCESS,
3951 &spr_read_generic, &spr_write_generic,
3952 0x00000000);
3953 spr_register(env, SPR_USPRG6, "USPRG6",
3954 &spr_read_ureg, SPR_NOACCESS,
3955 &spr_read_ureg, SPR_NOACCESS,
3956 0x00000000);
3957 spr_register(env, SPR_SPRG7, "SPRG7",
3958 SPR_NOACCESS, SPR_NOACCESS,
3959 &spr_read_generic, &spr_write_generic,
3960 0x00000000);
3961 spr_register(env, SPR_USPRG7, "USPRG7",
3962 &spr_read_ureg, SPR_NOACCESS,
3963 &spr_read_ureg, SPR_NOACCESS,
3964 0x00000000);
3965 /* Memory management */
3966 gen_low_BATs(env);
3967 gen_high_BATs(env);
578bb252 3968 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3969 init_excp_7450(env);
d63001d1
JM		 3970 env->dcache_line_size = 32;
3971 env->icache_line_size = 32;
a750fc0b
JM		 3972 /* Allocate hardware IRQ controller */
3973 ppc6xx_irq_init(env);
3974}
a750fc0b
JM		 3975
3976#if defined (TARGET_PPC64)
d63001d1 3977#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
12de9a39
JM		 3978 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3979 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3980 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
a750fc0b 3981/* PowerPC 970 */
d63001d1 3982#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 3983 PPC_64B | PPC_ALTIVEC | \
12de9a39 3984 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 3985#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 3986#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 3987//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3988#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 3989#define POWERPC_BFDM_970 (bfd_mach_ppc64)
d26bfc9a 3990#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE)
a750fc0b
JM		 3991
3992static void init_proc_970 (CPUPPCState *env)
3993{
3994 gen_spr_ne_601(env);
3995 gen_spr_7xx(env);
3996 /* Time base */
3997 gen_tbl(env);
3998 /* Hardware implementation registers */
3999 /* XXX : not implemented */
4000 spr_register(env, SPR_HID0, "HID0",
4001 SPR_NOACCESS, SPR_NOACCESS,
06403421 4002 &spr_read_generic, &spr_write_clear,
d63001d1 4003 0x60000000);
a750fc0b
JM		 4004 /* XXX : not implemented */
4005 spr_register(env, SPR_HID1, "HID1",
4006 SPR_NOACCESS, SPR_NOACCESS,
4007 &spr_read_generic, &spr_write_generic,
4008 0x00000000);
4009 /* XXX : not implemented */
4010 spr_register(env, SPR_750_HID2, "HID2",
4011 SPR_NOACCESS, SPR_NOACCESS,
4012 &spr_read_generic, &spr_write_generic,
4013 0x00000000);
e57448f1
JM		 4014 /* XXX : not implemented */
4015 spr_register(env, SPR_970_HID5, "HID5",
4016 SPR_NOACCESS, SPR_NOACCESS,
4017 &spr_read_generic, &spr_write_generic,
4018#if defined(CONFIG_USER_ONLY)
4019 0x00000080
4020#else
4021 0x00000000
4022#endif
4023 );
a750fc0b
JM		 4024 /* Memory management */
4025 /* XXX: not correct */
4026 gen_low_BATs(env);
12de9a39
JM		 4027 /* XXX : not implemented */
4028 spr_register(env, SPR_MMUCFG, "MMUCFG",
4029 SPR_NOACCESS, SPR_NOACCESS,
4030 &spr_read_generic, SPR_NOACCESS,
4031 0x00000000); /* TOFIX */
4032 /* XXX : not implemented */
4033 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4034 SPR_NOACCESS, SPR_NOACCESS,
4035 &spr_read_generic, &spr_write_generic,
4036 0x00000000); /* TOFIX */
4037 spr_register(env, SPR_HIOR, "SPR_HIOR",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, &spr_write_generic,
4040 0xFFF00000); /* XXX: This is a hack */
4041#if !defined(CONFIG_USER_ONLY)
4042 env->excp_prefix = 0xFFF00000;
a750fc0b 4043#endif
12de9a39 4044 env->slb_nr = 32;
e1833e1f 4045 init_excp_970(env);
d63001d1
JM		 4046 env->dcache_line_size = 128;
4047 env->icache_line_size = 128;
a750fc0b
JM		 4048 /* Allocate hardware IRQ controller */
4049 ppc970_irq_init(env);
4050}
a750fc0b
JM		 4051
4052/* PowerPC 970FX (aka G5) */
d63001d1 4053#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4054 PPC_64B | PPC_ALTIVEC | \
12de9a39 4055 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4056#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 4057#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 4058#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4059#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 4060#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
d26bfc9a 4061#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE)
a750fc0b
JM		 4062
4063static void init_proc_970FX (CPUPPCState *env)
4064{
4065 gen_spr_ne_601(env);
4066 gen_spr_7xx(env);
4067 /* Time base */
4068 gen_tbl(env);
4069 /* Hardware implementation registers */
4070 /* XXX : not implemented */
4071 spr_register(env, SPR_HID0, "HID0",
4072 SPR_NOACCESS, SPR_NOACCESS,
06403421 4073 &spr_read_generic, &spr_write_clear,
d63001d1 4074 0x60000000);
a750fc0b
JM		 4075 /* XXX : not implemented */
4076 spr_register(env, SPR_HID1, "HID1",
4077 SPR_NOACCESS, SPR_NOACCESS,
4078 &spr_read_generic, &spr_write_generic,
4079 0x00000000);
4080 /* XXX : not implemented */
4081 spr_register(env, SPR_750_HID2, "HID2",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_generic,
4084 0x00000000);
d63001d1
JM		 4085 /* XXX : not implemented */
4086 spr_register(env, SPR_970_HID5, "HID5",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
e57448f1
JM		 4089#if defined(CONFIG_USER_ONLY)
4090 0x00000080
4091#else
4092 0x00000000
4093#endif
4094 );
a750fc0b
JM		 4095 /* Memory management */
4096 /* XXX: not correct */
4097 gen_low_BATs(env);
12de9a39
JM		 4098 /* XXX : not implemented */
4099 spr_register(env, SPR_MMUCFG, "MMUCFG",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, SPR_NOACCESS,
4102 0x00000000); /* TOFIX */
4103 /* XXX : not implemented */
4104 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000); /* TOFIX */
4108 spr_register(env, SPR_HIOR, "SPR_HIOR",
4109 SPR_NOACCESS, SPR_NOACCESS,
4110 &spr_read_generic, &spr_write_generic,
4111 0xFFF00000); /* XXX: This is a hack */
4112#if !defined(CONFIG_USER_ONLY)
4113 env->excp_prefix = 0xFFF00000;
a750fc0b 4114#endif
12de9a39 4115 env->slb_nr = 32;
e1833e1f 4116 init_excp_970(env);
d63001d1
JM		 4117 env->dcache_line_size = 128;
4118 env->icache_line_size = 128;
a750fc0b
JM		 4119 /* Allocate hardware IRQ controller */
4120 ppc970_irq_init(env);
4121}
a750fc0b
JM		 4122
4123/* PowerPC 970 GX */
d63001d1 4124#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4125 PPC_64B | PPC_ALTIVEC | \
12de9a39 4126 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4127#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 4128#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 4129#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4130#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 4131#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
d26bfc9a 4132#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE)
a750fc0b
JM		 4133
4134static void init_proc_970GX (CPUPPCState *env)
4135{
4136 gen_spr_ne_601(env);
4137 gen_spr_7xx(env);
4138 /* Time base */
4139 gen_tbl(env);
4140 /* Hardware implementation registers */
4141 /* XXX : not implemented */
4142 spr_register(env, SPR_HID0, "HID0",
4143 SPR_NOACCESS, SPR_NOACCESS,
06403421 4144 &spr_read_generic, &spr_write_clear,
d63001d1 4145 0x60000000);
a750fc0b
JM		 4146 /* XXX : not implemented */
4147 spr_register(env, SPR_HID1, "HID1",
4148 SPR_NOACCESS, SPR_NOACCESS,
4149 &spr_read_generic, &spr_write_generic,
4150 0x00000000);
4151 /* XXX : not implemented */
4152 spr_register(env, SPR_750_HID2, "HID2",
4153 SPR_NOACCESS, SPR_NOACCESS,
4154 &spr_read_generic, &spr_write_generic,
4155 0x00000000);
d63001d1
JM		 4156 /* XXX : not implemented */
4157 spr_register(env, SPR_970_HID5, "HID5",
4158 SPR_NOACCESS, SPR_NOACCESS,
4159 &spr_read_generic, &spr_write_generic,
e57448f1
JM		 4160#if defined(CONFIG_USER_ONLY)
4161 0x00000080
4162#else
4163 0x00000000
4164#endif
4165 );
a750fc0b
JM		 4166 /* Memory management */
4167 /* XXX: not correct */
4168 gen_low_BATs(env);
12de9a39
JM		 4169 /* XXX : not implemented */
4170 spr_register(env, SPR_MMUCFG, "MMUCFG",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, SPR_NOACCESS,
4173 0x00000000); /* TOFIX */
4174 /* XXX : not implemented */
4175 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4176 SPR_NOACCESS, SPR_NOACCESS,
4177 &spr_read_generic, &spr_write_generic,
4178 0x00000000); /* TOFIX */
4179 spr_register(env, SPR_HIOR, "SPR_HIOR",
4180 SPR_NOACCESS, SPR_NOACCESS,
4181 &spr_read_generic, &spr_write_generic,
4182 0xFFF00000); /* XXX: This is a hack */
4183#if !defined(CONFIG_USER_ONLY)
4184 env->excp_prefix = 0xFFF00000;
a750fc0b 4185#endif
12de9a39 4186 env->slb_nr = 32;
e1833e1f 4187 init_excp_970(env);
d63001d1
JM		 4188 env->dcache_line_size = 128;
4189 env->icache_line_size = 128;
a750fc0b
JM		 4190 /* Allocate hardware IRQ controller */
4191 ppc970_irq_init(env);
4192}
a750fc0b
JM		 4193
4194/* PowerPC 620 */
a750fc0b
JM		 4195#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4196 PPC_64B | PPC_SLBI)
4197#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4198#define POWERPC_MMU_620 (POWERPC_MMU_64B)
4199#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4200#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
237c0af0 4201#define POWERPC_BFDM_620 (bfd_mach_ppc64)
d26bfc9a 4202#define POWERPC_FLAG_620 (POWERPC_FLAG_NONE)
a750fc0b 4203
578bb252 4204__attribute__ (( unused ))
a750fc0b
JM		 4205static void init_proc_620 (CPUPPCState *env)
4206{
4207 gen_spr_ne_601(env);
4208 gen_spr_620(env);
4209 /* Time base */
4210 gen_tbl(env);
4211 /* Hardware implementation registers */
4212 /* XXX : not implemented */
4213 spr_register(env, SPR_HID0, "HID0",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 /* Memory management */
4218 gen_low_BATs(env);
4219 gen_high_BATs(env);
e1833e1f 4220 init_excp_620(env);
d63001d1
JM		 4221 env->dcache_line_size = 64;
4222 env->icache_line_size = 64;
a750fc0b
JM		 4223 /* XXX: TODO: initialize internal interrupt controller */
4224}
a750fc0b
JM		 4225#endif /* defined (TARGET_PPC64) */
4226
4227/* Default 32 bits PowerPC target will be 604 */
4228#define CPU_POWERPC_PPC32 CPU_POWERPC_604
4229#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4230#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4231#define POWERPC_MMU_PPC32 POWERPC_MMU_604
4232#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4233#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4234#define init_proc_PPC32 init_proc_604
237c0af0 4235#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 4236#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
a750fc0b
JM		 4237
4238/* Default 64 bits PowerPC target will be 970 FX */
4239#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4240#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4241#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4242#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4243#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4244#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4245#define init_proc_PPC64 init_proc_970FX
237c0af0 4246#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 4247#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
a750fc0b
JM		 4248
4249/* Default PowerPC target will be PowerPC 32 */
4250#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 4251#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4252#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4253#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4254#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4255#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4256#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4257#define init_proc_DEFAULT init_proc_PPC64
237c0af0 4258#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 4259#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
a750fc0b 4260#else
d12f4c38
JM		 4261#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4262#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4263#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4264#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4265#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4266#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4267#define init_proc_DEFAULT init_proc_PPC32
237c0af0 4268#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 4269#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
a750fc0b
JM		 4270#endif
4271
4272/*****************************************************************************/
4273/* PVR definitions for most known PowerPC */
4274enum {
4275 /* PowerPC 401 family */
4276 /* Generic PowerPC 401 */
4277#define CPU_POWERPC_401 CPU_POWERPC_401G2
4278 /* PowerPC 401 cores */
4279 CPU_POWERPC_401A1 = 0x00210000,
4280 CPU_POWERPC_401B2 = 0x00220000,
4281#if 0
4282 CPU_POWERPC_401B3 = xxx,
4283#endif
4284 CPU_POWERPC_401C2 = 0x00230000,
4285 CPU_POWERPC_401D2 = 0x00240000,
4286 CPU_POWERPC_401E2 = 0x00250000,
4287 CPU_POWERPC_401F2 = 0x00260000,
4288 CPU_POWERPC_401G2 = 0x00270000,
4289 /* PowerPC 401 microcontrolers */
4290#if 0
4291 CPU_POWERPC_401GF = xxx,
4292#endif
4293#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4294 /* IBM Processor for Network Resources */
4295 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4296#if 0
4297 CPU_POWERPC_XIPCHIP = xxx,
4298#endif
4299 /* PowerPC 403 family */
4300 /* Generic PowerPC 403 */
4301#define CPU_POWERPC_403 CPU_POWERPC_403GC
4302 /* PowerPC 403 microcontrollers */
4303 CPU_POWERPC_403GA = 0x00200011,
4304 CPU_POWERPC_403GB = 0x00200100,
4305 CPU_POWERPC_403GC = 0x00200200,
4306 CPU_POWERPC_403GCX = 0x00201400,
4307#if 0
4308 CPU_POWERPC_403GP = xxx,
4309#endif
4310 /* PowerPC 405 family */
4311 /* Generic PowerPC 405 */
4312#define CPU_POWERPC_405 CPU_POWERPC_405D4
4313 /* PowerPC 405 cores */
4314#if 0
4315 CPU_POWERPC_405A3 = xxx,
4316#endif
4317#if 0
4318 CPU_POWERPC_405A4 = xxx,
4319#endif
4320#if 0
4321 CPU_POWERPC_405B3 = xxx,
4322#endif
4323#if 0
4324 CPU_POWERPC_405B4 = xxx,
4325#endif
4326#if 0
4327 CPU_POWERPC_405C3 = xxx,
4328#endif
4329#if 0
4330 CPU_POWERPC_405C4 = xxx,
4331#endif
4332 CPU_POWERPC_405D2 = 0x20010000,
4333#if 0
4334 CPU_POWERPC_405D3 = xxx,
4335#endif
4336 CPU_POWERPC_405D4 = 0x41810000,
4337#if 0
4338 CPU_POWERPC_405D5 = xxx,
4339#endif
4340#if 0
4341 CPU_POWERPC_405E4 = xxx,
4342#endif
4343#if 0
4344 CPU_POWERPC_405F4 = xxx,
4345#endif
4346#if 0
4347 CPU_POWERPC_405F5 = xxx,
4348#endif
4349#if 0
4350 CPU_POWERPC_405F6 = xxx,
4351#endif
4352 /* PowerPC 405 microcontrolers */
4353 /* XXX: missing 0x200108a0 */
4354#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4355 CPU_POWERPC_405CRa = 0x40110041,
4356 CPU_POWERPC_405CRb = 0x401100C5,
4357 CPU_POWERPC_405CRc = 0x40110145,
4358 CPU_POWERPC_405EP = 0x51210950,
4359#if 0
4360 CPU_POWERPC_405EXr = xxx,
4361#endif
4362 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4363#if 0
4364 CPU_POWERPC_405FX = xxx,
4365#endif
4366#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4367 CPU_POWERPC_405GPa = 0x40110000,
4368 CPU_POWERPC_405GPb = 0x40110040,
4369 CPU_POWERPC_405GPc = 0x40110082,
4370 CPU_POWERPC_405GPd = 0x401100C4,
4371#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4372 CPU_POWERPC_405GPR = 0x50910951,
4373#if 0
4374 CPU_POWERPC_405H = xxx,
4375#endif
4376#if 0
4377 CPU_POWERPC_405L = xxx,
4378#endif
4379 CPU_POWERPC_405LP = 0x41F10000,
4380#if 0
4381 CPU_POWERPC_405PM = xxx,
4382#endif
4383#if 0
4384 CPU_POWERPC_405PS = xxx,
4385#endif
4386#if 0
4387 CPU_POWERPC_405S = xxx,
4388#endif
4389 /* IBM network processors */
4390 CPU_POWERPC_NPE405H = 0x414100C0,
4391 CPU_POWERPC_NPE405H2 = 0x41410140,
4392 CPU_POWERPC_NPE405L = 0x416100C0,
4393 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4394#if 0
4395 CPU_POWERPC_NPCxx1 = xxx,
4396#endif
4397#if 0
4398 CPU_POWERPC_NPR161 = xxx,
4399#endif
4400#if 0
4401 CPU_POWERPC_LC77700 = xxx,
4402#endif
4403 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4404#if 0
4405 CPU_POWERPC_STB01000 = xxx,
4406#endif
4407#if 0
4408 CPU_POWERPC_STB01010 = xxx,
4409#endif
4410#if 0
4411 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4412#endif
4413 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4414#if 0
4415 CPU_POWERPC_STB043 = xxx,
4416#endif
4417#if 0
4418 CPU_POWERPC_STB045 = xxx,
4419#endif
4420 CPU_POWERPC_STB04 = 0x41810000,
4421 CPU_POWERPC_STB25 = 0x51510950,
4422#if 0
4423 CPU_POWERPC_STB130 = xxx,
4424#endif
4425 /* Xilinx cores */
4426 CPU_POWERPC_X2VP4 = 0x20010820,
4427#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4428 CPU_POWERPC_X2VP20 = 0x20010860,
4429#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4430#if 0
4431 CPU_POWERPC_ZL10310 = xxx,
4432#endif
4433#if 0
4434 CPU_POWERPC_ZL10311 = xxx,
4435#endif
4436#if 0
4437 CPU_POWERPC_ZL10320 = xxx,
4438#endif
4439#if 0
4440 CPU_POWERPC_ZL10321 = xxx,
4441#endif
4442 /* PowerPC 440 family */
4443 /* Generic PowerPC 440 */
4444#define CPU_POWERPC_440 CPU_POWERPC_440GXf
4445 /* PowerPC 440 cores */
4446#if 0
4447 CPU_POWERPC_440A4 = xxx,
4448#endif
4449#if 0
4450 CPU_POWERPC_440A5 = xxx,
4451#endif
4452#if 0
4453 CPU_POWERPC_440B4 = xxx,
4454#endif
4455#if 0
4456 CPU_POWERPC_440F5 = xxx,
4457#endif
4458#if 0
4459 CPU_POWERPC_440G5 = xxx,
4460#endif
4461#if 0
4462 CPU_POWERPC_440H4 = xxx,
4463#endif
4464#if 0
4465 CPU_POWERPC_440H6 = xxx,
4466#endif
4467 /* PowerPC 440 microcontrolers */
4468#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4469 CPU_POWERPC_440EPa = 0x42221850,
4470 CPU_POWERPC_440EPb = 0x422218D3,
4471#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4472 CPU_POWERPC_440GPb = 0x40120440,
4473 CPU_POWERPC_440GPc = 0x40120481,
4474#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4475#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4476 CPU_POWERPC_440GRX = 0x200008D0,
4477#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4478#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4479 CPU_POWERPC_440GXa = 0x51B21850,
4480 CPU_POWERPC_440GXb = 0x51B21851,
4481 CPU_POWERPC_440GXc = 0x51B21892,
4482 CPU_POWERPC_440GXf = 0x51B21894,
4483#if 0
4484 CPU_POWERPC_440S = xxx,
4485#endif
4486 CPU_POWERPC_440SP = 0x53221850,
4487 CPU_POWERPC_440SP2 = 0x53221891,
4488 CPU_POWERPC_440SPE = 0x53421890,
4489 /* PowerPC 460 family */
4490#if 0
4491 /* Generic PowerPC 464 */
4492#define CPU_POWERPC_464 CPU_POWERPC_464H90
4493#endif
4494 /* PowerPC 464 microcontrolers */
4495#if 0
4496 CPU_POWERPC_464H90 = xxx,
4497#endif
4498#if 0
4499 CPU_POWERPC_464H90FP = xxx,
4500#endif
4501 /* Freescale embedded PowerPC cores */
4502 /* e200 family */
4503#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4504#if 0
4505 CPU_POWERPC_e200z0 = xxx,
4506#endif
4507#if 0
4508 CPU_POWERPC_e200z3 = xxx,
4509#endif
4510 CPU_POWERPC_e200z5 = 0x81000000,
4511 CPU_POWERPC_e200z6 = 0x81120000,
4512 /* e300 family */
4513#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4514 CPU_POWERPC_e300c1 = 0x00830000,
4515 CPU_POWERPC_e300c2 = 0x00840000,
4516 CPU_POWERPC_e300c3 = 0x00850000,
4517 /* e500 family */
4518#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4519 CPU_POWERPC_e500_v11 = 0x80200010,
4520 CPU_POWERPC_e500_v12 = 0x80200020,
4521 CPU_POWERPC_e500_v21 = 0x80210010,
4522 CPU_POWERPC_e500_v22 = 0x80210020,
4523#if 0
4524 CPU_POWERPC_e500mc = xxx,
4525#endif
4526 /* e600 family */
4527 CPU_POWERPC_e600 = 0x80040010,
4528 /* PowerPC MPC 5xx cores */
4529 CPU_POWERPC_5xx = 0x00020020,
4530 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4531 CPU_POWERPC_8xx = 0x00500000,
4532 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4533 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4534 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4535 CPU_POWERPC_827x = 0x80822013,
4536 /* PowerPC 6xx cores */
4537 CPU_POWERPC_601 = 0x00010001,
4538 CPU_POWERPC_601a = 0x00010002,
4539 CPU_POWERPC_602 = 0x00050100,
4540 CPU_POWERPC_603 = 0x00030100,
4541#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4542 CPU_POWERPC_603E_v11 = 0x00060101,
4543 CPU_POWERPC_603E_v12 = 0x00060102,
4544 CPU_POWERPC_603E_v13 = 0x00060103,
4545 CPU_POWERPC_603E_v14 = 0x00060104,
4546 CPU_POWERPC_603E_v22 = 0x00060202,
4547 CPU_POWERPC_603E_v3 = 0x00060300,
4548 CPU_POWERPC_603E_v4 = 0x00060400,
4549 CPU_POWERPC_603E_v41 = 0x00060401,
4550 CPU_POWERPC_603E7t = 0x00071201,
4551 CPU_POWERPC_603E7v = 0x00070100,
4552 CPU_POWERPC_603E7v1 = 0x00070101,
4553 CPU_POWERPC_603E7v2 = 0x00070201,
4554 CPU_POWERPC_603E7 = 0x00070200,
4555 CPU_POWERPC_603P = 0x00070000,
4556#define CPU_POWERPC_603R CPU_POWERPC_603E7t
4557 CPU_POWERPC_G2 = 0x00810011,
4558#if 0 // Linux pretends the MSB is zero...
4559 CPU_POWERPC_G2H4 = 0x80811010,
4560 CPU_POWERPC_G2gp = 0x80821010,
4561 CPU_POWERPC_G2ls = 0x90810010,
4562 CPU_POWERPC_G2LE = 0x80820010,
4563 CPU_POWERPC_G2LEgp = 0x80822010,
4564 CPU_POWERPC_G2LEls = 0xA0822010,
4565#else
4566 CPU_POWERPC_G2H4 = 0x00811010,
4567 CPU_POWERPC_G2gp = 0x00821010,
4568 CPU_POWERPC_G2ls = 0x10810010,
4569 CPU_POWERPC_G2LE = 0x00820010,
4570 CPU_POWERPC_G2LEgp = 0x00822010,
4571 CPU_POWERPC_G2LEls = 0x20822010,
4572#endif
4573 CPU_POWERPC_604 = 0x00040103,
4574#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4575 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4576 CPU_POWERPC_604E_v22 = 0x00090202,
4577 CPU_POWERPC_604E_v24 = 0x00090204,
4578 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4579#if 0
4580 CPU_POWERPC_604EV = xxx,
4581#endif
4582 /* PowerPC 740/750 cores (aka G3) */
4583 /* XXX: missing 0x00084202 */
4584#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4585 CPU_POWERPC_7x0_v20 = 0x00080200,
4586 CPU_POWERPC_7x0_v21 = 0x00080201,
4587 CPU_POWERPC_7x0_v22 = 0x00080202,
4588 CPU_POWERPC_7x0_v30 = 0x00080300,
4589 CPU_POWERPC_7x0_v31 = 0x00080301,
4590 CPU_POWERPC_740E = 0x00080100,
4591 CPU_POWERPC_7x0P = 0x10080000,
4592 /* XXX: missing 0x00087010 (CL ?) */
4593 CPU_POWERPC_750CL = 0x00087200,
4594#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4595 CPU_POWERPC_750CX_v21 = 0x00082201,
4596 CPU_POWERPC_750CX_v22 = 0x00082202,
4597#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4598 CPU_POWERPC_750CXE_v21 = 0x00082211,
4599 CPU_POWERPC_750CXE_v22 = 0x00082212,
4600 CPU_POWERPC_750CXE_v23 = 0x00082213,
4601 CPU_POWERPC_750CXE_v24 = 0x00082214,
4602 CPU_POWERPC_750CXE_v24b = 0x00083214,
4603 CPU_POWERPC_750CXE_v31 = 0x00083211,
4604 CPU_POWERPC_750CXE_v31b = 0x00083311,
4605 CPU_POWERPC_750CXR = 0x00083410,
4606 CPU_POWERPC_750E = 0x00080200,
4607 CPU_POWERPC_750FL = 0x700A0203,
4608#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4609 CPU_POWERPC_750FX_v10 = 0x70000100,
4610 CPU_POWERPC_750FX_v20 = 0x70000200,
4611 CPU_POWERPC_750FX_v21 = 0x70000201,
4612 CPU_POWERPC_750FX_v22 = 0x70000202,
4613 CPU_POWERPC_750FX_v23 = 0x70000203,
4614 CPU_POWERPC_750GL = 0x70020102,
4615#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4616 CPU_POWERPC_750GX_v10 = 0x70020100,
4617 CPU_POWERPC_750GX_v11 = 0x70020101,
4618 CPU_POWERPC_750GX_v12 = 0x70020102,
4619#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4620 CPU_POWERPC_750L_v22 = 0x00088202,
4621 CPU_POWERPC_750L_v30 = 0x00088300,
4622 CPU_POWERPC_750L_v32 = 0x00088302,
4623 /* PowerPC 745/755 cores */
4624#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4625 CPU_POWERPC_7x5_v10 = 0x00083100,
4626 CPU_POWERPC_7x5_v11 = 0x00083101,
4627 CPU_POWERPC_7x5_v20 = 0x00083200,
4628 CPU_POWERPC_7x5_v21 = 0x00083201,
4629 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4630 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4631 CPU_POWERPC_7x5_v24 = 0x00083204,
4632 CPU_POWERPC_7x5_v25 = 0x00083205,
4633 CPU_POWERPC_7x5_v26 = 0x00083206,
4634 CPU_POWERPC_7x5_v27 = 0x00083207,
4635 CPU_POWERPC_7x5_v28 = 0x00083208,
4636#if 0
4637 CPU_POWERPC_7x5P = xxx,
4638#endif
4639 /* PowerPC 74xx cores (aka G4) */
4640 /* XXX: missing 0x000C1101 */
4641#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4642 CPU_POWERPC_7400_v10 = 0x000C0100,
4643 CPU_POWERPC_7400_v11 = 0x000C0101,
4644 CPU_POWERPC_7400_v20 = 0x000C0200,
4645 CPU_POWERPC_7400_v22 = 0x000C0202,
4646 CPU_POWERPC_7400_v26 = 0x000C0206,
4647 CPU_POWERPC_7400_v27 = 0x000C0207,
4648 CPU_POWERPC_7400_v28 = 0x000C0208,
4649 CPU_POWERPC_7400_v29 = 0x000C0209,
4650#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4651 CPU_POWERPC_7410_v10 = 0x800C1100,
4652 CPU_POWERPC_7410_v11 = 0x800C1101,
4653 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4654 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4655 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4656#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4657 CPU_POWERPC_7448_v10 = 0x80040100,
4658 CPU_POWERPC_7448_v11 = 0x80040101,
4659 CPU_POWERPC_7448_v20 = 0x80040200,
4660 CPU_POWERPC_7448_v21 = 0x80040201,
4661#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4662 CPU_POWERPC_7450_v10 = 0x80000100,
4663 CPU_POWERPC_7450_v11 = 0x80000101,
4664 CPU_POWERPC_7450_v12 = 0x80000102,
4665 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4666 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4667 CPU_POWERPC_74x1 = 0x80000203,
4668 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4669 /* XXX: missing 0x80010200 */
4670#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4671 CPU_POWERPC_74x5_v10 = 0x80010100,
4672 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4673 CPU_POWERPC_74x5_v32 = 0x80010302,
4674 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4675 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4676#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4677 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4678 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4679 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4680 /* 64 bits PowerPC */
00af685f 4681#if defined(TARGET_PPC64)
a750fc0b
JM		 4682 CPU_POWERPC_620 = 0x00140000,
4683 CPU_POWERPC_630 = 0x00400000,
4684 CPU_POWERPC_631 = 0x00410104,
4685 CPU_POWERPC_POWER4 = 0x00350000,
4686 CPU_POWERPC_POWER4P = 0x00380000,
4687 CPU_POWERPC_POWER5 = 0x003A0203,
4688#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4689 CPU_POWERPC_POWER5P = 0x003B0000,
4690#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4691 CPU_POWERPC_POWER6 = 0x003E0000,
4692 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4693 CPU_POWERPC_POWER6A = 0x0F000002,
4694 CPU_POWERPC_970 = 0x00390202,
4695#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4696 CPU_POWERPC_970FX_v10 = 0x00391100,
4697 CPU_POWERPC_970FX_v20 = 0x003C0200,
4698 CPU_POWERPC_970FX_v21 = 0x003C0201,
4699 CPU_POWERPC_970FX_v30 = 0x003C0300,
4700 CPU_POWERPC_970FX_v31 = 0x003C0301,
4701 CPU_POWERPC_970GX = 0x00450000,
4702#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4703 CPU_POWERPC_970MP_v10 = 0x00440100,
4704 CPU_POWERPC_970MP_v11 = 0x00440101,
4705#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4706 CPU_POWERPC_CELL_v10 = 0x00700100,
4707 CPU_POWERPC_CELL_v20 = 0x00700400,
4708 CPU_POWERPC_CELL_v30 = 0x00700500,
4709 CPU_POWERPC_CELL_v31 = 0x00700501,
4710#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4711 CPU_POWERPC_RS64 = 0x00330000,
4712 CPU_POWERPC_RS64II = 0x00340000,
4713 CPU_POWERPC_RS64III = 0x00360000,
4714 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 4715#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 4716 /* Original POWER */
4717 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4718 * POWER2 (RIOS2) & RSC2 (P2SC) here
4719 */
4720#if 0
4721 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4722#endif
4723#if 0
4724 CPU_POWER2 = xxx, /* 0x40000 ? */
4725#endif
4726 /* PA Semi core */
4727 CPU_POWERPC_PA6T = 0x00900000,
4728};
4729
4730/* System version register (used on MPC 8xxx) */
4731enum {
4732 PPC_SVR_8540 = 0x80300000,
4733 PPC_SVR_8541E = 0x807A0010,
4734 PPC_SVR_8543v10 = 0x80320010,
4735 PPC_SVR_8543v11 = 0x80320011,
4736 PPC_SVR_8543v20 = 0x80320020,
4737 PPC_SVR_8543Ev10 = 0x803A0010,
4738 PPC_SVR_8543Ev11 = 0x803A0011,
4739 PPC_SVR_8543Ev20 = 0x803A0020,
4740 PPC_SVR_8545 = 0x80310220,
4741 PPC_SVR_8545E = 0x80390220,
4742 PPC_SVR_8547E = 0x80390120,
4743 PPC_SCR_8548v10 = 0x80310010,
4744 PPC_SCR_8548v11 = 0x80310011,
4745 PPC_SCR_8548v20 = 0x80310020,
4746 PPC_SVR_8548Ev10 = 0x80390010,
4747 PPC_SVR_8548Ev11 = 0x80390011,
4748 PPC_SVR_8548Ev20 = 0x80390020,
4749 PPC_SVR_8555E = 0x80790010,
4750 PPC_SVR_8560v10 = 0x80700010,
4751 PPC_SVR_8560v20 = 0x80700020,
4752};
4753
3fc6c082 4754/*****************************************************************************/
a750fc0b
JM		 4755/* PowerPC CPU definitions */
4756#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4757 { \
4758 .name = _name, \
4759 .pvr = _pvr, \
4760 .pvr_mask = _pvr_mask, \
4761 .insns_flags = glue(POWERPC_INSNS_,_type), \
4762 .msr_mask = glue(POWERPC_MSRM_,_type), \
4763 .mmu_model = glue(POWERPC_MMU_,_type), \
4764 .excp_model = glue(POWERPC_EXCP_,_type), \
4765 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 4766 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 4767 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b
JM		 4768 .init_proc = &glue(init_proc_,_type), \
4769 }
4770
3a607854 4771static ppc_def_t ppc_defs[] = {
a750fc0b
JM		 4772 /* Embedded PowerPC */
4773 /* PowerPC 401 family */
2662a059 4774 /* Generic PowerPC 401 */
a750fc0b
JM		 4775 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4776 /* PowerPC 401 cores */
2662a059 4777 /* PowerPC 401A1 */
a750fc0b
JM		 4778 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4779 /* PowerPC 401B2 */
4780 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
2662a059 4781#if defined (TODO)
a750fc0b
JM		 4782 /* PowerPC 401B3 */
4783 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4784#endif
4785 /* PowerPC 401C2 */
4786 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4787 /* PowerPC 401D2 */
4788 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4789 /* PowerPC 401E2 */
4790 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4791 /* PowerPC 401F2 */
4792 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4793 /* PowerPC 401G2 */
4794 /* XXX: to be checked */
4795 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4796 /* PowerPC 401 microcontrolers */
2662a059 4797#if defined (TODO)
a750fc0b
JM		 4798 /* PowerPC 401GF */
4799 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
3fc6c082 4800#endif
a750fc0b
JM		 4801 /* IOP480 (401 microcontroler) */
4802 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4803 /* IBM Processor for Network Resources */
4804 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
3fc6c082 4805#if defined (TODO)
a750fc0b 4806 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
3fc6c082 4807#endif
a750fc0b
JM		 4808 /* PowerPC 403 family */
4809 /* Generic PowerPC 403 */
4810 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4811 /* PowerPC 403 microcontrolers */
4812 /* PowerPC 403 GA */
4813 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4814 /* PowerPC 403 GB */
4815 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4816 /* PowerPC 403 GC */
4817 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4818 /* PowerPC 403 GCX */
4819 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
3fc6c082 4820#if defined (TODO)
a750fc0b
JM		 4821 /* PowerPC 403 GP */
4822 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
3fc6c082 4823#endif
a750fc0b
JM		 4824 /* PowerPC 405 family */
4825 /* Generic PowerPC 405 */
4826 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4827 /* PowerPC 405 cores */
2662a059 4828#if defined (TODO)
a750fc0b
JM		 4829 /* PowerPC 405 A3 */
4830 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
3a607854 4831#endif
3a607854 4832#if defined (TODO)
a750fc0b
JM		 4833 /* PowerPC 405 A4 */
4834 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
3a607854 4835#endif
3a607854 4836#if defined (TODO)
a750fc0b
JM		 4837 /* PowerPC 405 B3 */
4838 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
3fc6c082
FB		 4839#endif
4840#if defined (TODO)
a750fc0b
JM		 4841 /* PowerPC 405 B4 */
4842 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4843#endif
4844#if defined (TODO)
4845 /* PowerPC 405 C3 */
4846 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4847#endif
4848#if defined (TODO)
4849 /* PowerPC 405 C4 */
4850 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4851#endif
4852 /* PowerPC 405 D2 */
4853 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4854#if defined (TODO)
4855 /* PowerPC 405 D3 */
4856 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4857#endif
4858 /* PowerPC 405 D4 */
4859 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4860#if defined (TODO)
4861 /* PowerPC 405 D5 */
4862 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4863#endif
4864#if defined (TODO)
4865 /* PowerPC 405 E4 */
4866 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4867#endif
4868#if defined (TODO)
4869 /* PowerPC 405 F4 */
4870 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4871#endif
4872#if defined (TODO)
4873 /* PowerPC 405 F5 */
4874 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4875#endif
4876#if defined (TODO)
4877 /* PowerPC 405 F6 */
4878 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4879#endif
4880 /* PowerPC 405 microcontrolers */
4881 /* PowerPC 405 CR */
4882 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4883 /* PowerPC 405 CRa */
4884 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4885 /* PowerPC 405 CRb */
4886 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4887 /* PowerPC 405 CRc */
4888 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4889 /* PowerPC 405 EP */
4890 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4891#if defined(TODO)
4892 /* PowerPC 405 EXr */
4893 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4894#endif
4895 /* PowerPC 405 EZ */
4896 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4897#if defined(TODO)
4898 /* PowerPC 405 FX */
4899 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4900#endif
4901 /* PowerPC 405 GP */
4902 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4903 /* PowerPC 405 GPa */
4904 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4905 /* PowerPC 405 GPb */
4906 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4907 /* PowerPC 405 GPc */
4908 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4909 /* PowerPC 405 GPd */
4910 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4911 /* PowerPC 405 GPe */
4912 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4913 /* PowerPC 405 GPR */
4914 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4915#if defined(TODO)
4916 /* PowerPC 405 H */
4917 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
4918#endif
4919#if defined(TODO)
4920 /* PowerPC 405 L */
4921 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
4922#endif
4923 /* PowerPC 405 LP */
4924 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
4925#if defined(TODO)
4926 /* PowerPC 405 PM */
4927 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
4928#endif
4929#if defined(TODO)
4930 /* PowerPC 405 PS */
4931 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
4932#endif
4933#if defined(TODO)
4934 /* PowerPC 405 S */
4935 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
4936#endif
4937 /* Npe405 H */
4938 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
4939 /* Npe405 H2 */
4940 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
4941 /* Npe405 L */
4942 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
4943 /* Npe4GS3 */
4944 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
4945#if defined (TODO)
4946 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
4947#endif
4948#if defined (TODO)
4949 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
4950#endif
4951#if defined (TODO)
4952 /* PowerPC LC77700 (Sanyo) */
4953 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
4954#endif
4955 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4956#if defined (TODO)
4957 /* STB010000 */
4958 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
4959#endif
4960#if defined (TODO)
4961 /* STB01010 */
4962 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
4963#endif
4964#if defined (TODO)
4965 /* STB0210 */
4966 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
4967#endif
4968 /* STB03xx */
4969 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
4970#if defined (TODO)
4971 /* STB043x */
4972 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
4973#endif
4974#if defined (TODO)
4975 /* STB045x */
4976 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
4977#endif
4978 /* STB04xx */
4979 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
4980 /* STB25xx */
4981 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
4982#if defined (TODO)
4983 /* STB130 */
4984 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
4985#endif
4986 /* Xilinx PowerPC 405 cores */
4987 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
4988 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
4989 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
4990 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
4991#if defined (TODO)
4992 /* Zarlink ZL10310 */
4993 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
4994#endif
4995#if defined (TODO)
4996 /* Zarlink ZL10311 */
4997 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
4998#endif
4999#if defined (TODO)
5000 /* Zarlink ZL10320 */
5001 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
5002#endif
5003#if defined (TODO)
5004 /* Zarlink ZL10321 */
5005 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
5006#endif
5007 /* PowerPC 440 family */
5008 /* Generic PowerPC 440 */
5009 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
5010 /* PowerPC 440 cores */
5011#if defined (TODO)
5012 /* PowerPC 440 A4 */
5013 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
5014#endif
5015#if defined (TODO)
5016 /* PowerPC 440 A5 */
5017 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
5018#endif
5019#if defined (TODO)
5020 /* PowerPC 440 B4 */
5021 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
5022#endif
5023#if defined (TODO)
5024 /* PowerPC 440 G4 */
5025 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
5026#endif
5027#if defined (TODO)
5028 /* PowerPC 440 F5 */
5029 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
5030#endif
5031#if defined (TODO)
5032 /* PowerPC 440 G5 */
5033 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
5034#endif
5035#if defined (TODO)
5036 /* PowerPC 440H4 */
5037 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
5038#endif
5039#if defined (TODO)
5040 /* PowerPC 440H6 */
5041 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5042#endif
5043 /* PowerPC 440 microcontrolers */
5044 /* PowerPC 440 EP */
5045 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5046 /* PowerPC 440 EPa */
5047 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5048 /* PowerPC 440 EPb */
5049 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5050 /* PowerPC 440 EPX */
5051 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5052 /* PowerPC 440 GP */
5053 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5054 /* PowerPC 440 GPb */
5055 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5056 /* PowerPC 440 GPc */
5057 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5058 /* PowerPC 440 GR */
5059 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5060 /* PowerPC 440 GRa */
5061 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5062 /* PowerPC 440 GRX */
5063 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5064 /* PowerPC 440 GX */
5065 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5066 /* PowerPC 440 GXa */
5067 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5068 /* PowerPC 440 GXb */
5069 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5070 /* PowerPC 440 GXc */
5071 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5072 /* PowerPC 440 GXf */
5073 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5074#if defined(TODO)
5075 /* PowerPC 440 S */
5076 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5077#endif
5078 /* PowerPC 440 SP */
5079 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5080 /* PowerPC 440 SP2 */
5081 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5082 /* PowerPC 440 SPE */
5083 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5084 /* PowerPC 460 family */
5085#if defined (TODO)
5086 /* Generic PowerPC 464 */
5087 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5088#endif
5089 /* PowerPC 464 microcontrolers */
5090#if defined (TODO)
5091 /* PowerPC 464H90 */
5092 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5093#endif
5094#if defined (TODO)
5095 /* PowerPC 464H90F */
5096 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5097#endif
5098 /* Freescale embedded PowerPC cores */
5099 /* e200 family */
5100#if defined (TODO)
5101 /* Generic PowerPC e200 core */
5102 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5103#endif
5104#if defined (TODO)
5105 /* PowerPC e200z5 core */
5106 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5107#endif
5108#if defined (TODO)
5109 /* PowerPC e200z6 core */
5110 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5111#endif
5112 /* e300 family */
5113#if defined (TODO)
5114 /* Generic PowerPC e300 core */
5115 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5116#endif
5117#if defined (TODO)
5118 /* PowerPC e300c1 core */
5119 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5120#endif
5121#if defined (TODO)
5122 /* PowerPC e300c2 core */
5123 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5124#endif
5125#if defined (TODO)
5126 /* PowerPC e300c3 core */
5127 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5128#endif
5129 /* e500 family */
5130#if defined (TODO)
5131 /* PowerPC e500 core */
5132 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5133#endif
5134#if defined (TODO)
5135 /* PowerPC e500 v1.1 core */
5136 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5137#endif
5138#if defined (TODO)
5139 /* PowerPC e500 v1.2 core */
5140 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5141#endif
5142#if defined (TODO)
5143 /* PowerPC e500 v2.1 core */
5144 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5145#endif
5146#if defined (TODO)
5147 /* PowerPC e500 v2.2 core */
5148 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5149#endif
5150 /* e600 family */
5151#if defined (TODO)
5152 /* PowerPC e600 core */
5153 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5154#endif
5155 /* PowerPC MPC 5xx cores */
5156#if defined (TODO)
5157 /* PowerPC MPC 5xx */
5158 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5159#endif
5160 /* PowerPC MPC 8xx cores */
5161#if defined (TODO)
5162 /* PowerPC MPC 8xx */
5163 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5164#endif
5165 /* PowerPC MPC 8xxx cores */
5166#if defined (TODO)
5167 /* PowerPC MPC 82xx HIP3 */
5168 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5169#endif
5170#if defined (TODO)
5171 /* PowerPC MPC 82xx HIP4 */
5172 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5173#endif
5174#if defined (TODO)
5175 /* PowerPC MPC 827x */
5176 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5177#endif
5178
5179 /* 32 bits "classic" PowerPC */
5180 /* PowerPC 6xx family */
5181 /* PowerPC 601 */
5182 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5183 /* PowerPC 601v2 */
5184 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5185 /* PowerPC 602 */
5186 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5187 /* PowerPC 603 */
5188 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5189 /* Code name for PowerPC 603 */
5190 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5191 /* PowerPC 603e */
5192 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5193 /* Code name for PowerPC 603e */
5194 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5195 /* PowerPC 603e v1.1 */
5196 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5197 /* PowerPC 603e v1.2 */
5198 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5199 /* PowerPC 603e v1.3 */
5200 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5201 /* PowerPC 603e v1.4 */
5202 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5203 /* PowerPC 603e v2.2 */
5204 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5205 /* PowerPC 603e v3 */
5206 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5207 /* PowerPC 603e v4 */
5208 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5209 /* PowerPC 603e v4.1 */
5210 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5211 /* PowerPC 603e */
5212 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5213 /* PowerPC 603e7t */
5214 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5215 /* PowerPC 603e7v */
5216 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5217 /* Code name for PowerPC 603ev */
5218 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5219 /* PowerPC 603e7v1 */
5220 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5221 /* PowerPC 603e7v2 */
5222 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5223 /* PowerPC 603p */
5224 /* to be checked */
5225 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5226 /* PowerPC 603r */
5227 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5228 /* Code name for PowerPC 603r */
5229 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5230 /* PowerPC G2 core */
5231 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5232 /* PowerPC G2 H4 */
5233 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5234 /* PowerPC G2 GP */
5235 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5236 /* PowerPC G2 LS */
5237 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5238 /* PowerPC G2LE */
5239 /* Same as G2, with little-endian mode support */
5240 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5241 /* PowerPC G2LE GP */
5242 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5243 /* PowerPC G2LE LS */
5244 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5245 /* PowerPC 604 */
5246 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5247 /* PowerPC 604e */
5248 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5249 /* PowerPC 604e v1.0 */
5250 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5251 /* PowerPC 604e v2.2 */
5252 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5253 /* PowerPC 604e v2.4 */
5254 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5255 /* PowerPC 604r */
5256 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5257#if defined(TODO)
5258 /* PowerPC 604ev */
5259 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5260#endif
5261 /* PowerPC 7xx family */
5262 /* Generic PowerPC 740 (G3) */
5263 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5264 /* Generic PowerPC 750 (G3) */
5265 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5266 /* Code name for generic PowerPC 740/750 (G3) */
5267 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5268 /* PowerPC 740/750 is also known as G3 */
5269 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5270 /* PowerPC 740 v2.0 (G3) */
5271 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5272 /* PowerPC 750 v2.0 (G3) */
5273 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5274 /* PowerPC 740 v2.1 (G3) */
5275 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5276 /* PowerPC 750 v2.1 (G3) */
5277 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5278 /* PowerPC 740 v2.2 (G3) */
5279 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5280 /* PowerPC 750 v2.2 (G3) */
5281 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5282 /* PowerPC 740 v3.0 (G3) */
5283 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5284 /* PowerPC 750 v3.0 (G3) */
5285 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5286 /* PowerPC 740 v3.1 (G3) */
5287 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5288 /* PowerPC 750 v3.1 (G3) */
5289 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5290 /* PowerPC 740E (G3) */
5291 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5292 /* PowerPC 740P (G3) */
5293 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5294 /* PowerPC 750P (G3) */
5295 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5296 /* Code name for PowerPC 740P/750P (G3) */
5297 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5298 /* PowerPC 750CL (G3 embedded) */
5299 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5300 /* PowerPC 750CX (G3 embedded) */
5301 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5302 /* PowerPC 750CX v2.1 (G3 embedded) */
5303 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5304 /* PowerPC 750CX v2.2 (G3 embedded) */
5305 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5306 /* PowerPC 750CXe (G3 embedded) */
5307 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5308 /* PowerPC 750CXe v2.1 (G3 embedded) */
5309 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5310 /* PowerPC 750CXe v2.2 (G3 embedded) */
5311 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5312 /* PowerPC 750CXe v2.3 (G3 embedded) */
5313 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5314 /* PowerPC 750CXe v2.4 (G3 embedded) */
5315 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5316 /* PowerPC 750CXe v2.4b (G3 embedded) */
5317 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5318 /* PowerPC 750CXe v3.1 (G3 embedded) */
5319 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5320 /* PowerPC 750CXe v3.1b (G3 embedded) */
5321 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5322 /* PowerPC 750CXr (G3 embedded) */
5323 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5324 /* PowerPC 750E (G3) */
5325 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5326 /* PowerPC 750FL (G3 embedded) */
d12f4c38 5327 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5328 /* PowerPC 750FX (G3 embedded) */
5329 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5330 /* PowerPC 750FX v1.0 (G3 embedded) */
5331 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5332 /* PowerPC 750FX v2.0 (G3 embedded) */
5333 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5334 /* PowerPC 750FX v2.1 (G3 embedded) */
5335 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5336 /* PowerPC 750FX v2.2 (G3 embedded) */
5337 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5338 /* PowerPC 750FX v2.3 (G3 embedded) */
5339 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5340 /* PowerPC 750GL (G3 embedded) */
d12f4c38 5341 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5342 /* PowerPC 750GX (G3 embedded) */
5343 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5344 /* PowerPC 750GX v1.0 (G3 embedded) */
5345 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5346 /* PowerPC 750GX v1.1 (G3 embedded) */
5347 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5348 /* PowerPC 750GX v1.2 (G3 embedded) */
5349 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5350 /* PowerPC 750L (G3 embedded) */
5351 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5352 /* Code name for PowerPC 750L (G3 embedded) */
5353 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5354 /* PowerPC 750L v2.2 (G3 embedded) */
5355 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5356 /* PowerPC 750L v3.0 (G3 embedded) */
5357 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5358 /* PowerPC 750L v3.2 (G3 embedded) */
5359 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5360 /* Generic PowerPC 745 */
5361 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5362 /* Generic PowerPC 755 */
5363 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5364 /* Code name for PowerPC 745/755 */
5365 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5366 /* PowerPC 745 v1.0 */
5367 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5368 /* PowerPC 755 v1.0 */
5369 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5370 /* PowerPC 745 v1.1 */
5371 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5372 /* PowerPC 755 v1.1 */
5373 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5374 /* PowerPC 745 v2.0 */
5375 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5376 /* PowerPC 755 v2.0 */
5377 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5378 /* PowerPC 745 v2.1 */
5379 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5380 /* PowerPC 755 v2.1 */
5381 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5382 /* PowerPC 745 v2.2 */
5383 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5384 /* PowerPC 755 v2.2 */
5385 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5386 /* PowerPC 745 v2.3 */
5387 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5388 /* PowerPC 755 v2.3 */
5389 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5390 /* PowerPC 745 v2.4 */
5391 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5392 /* PowerPC 755 v2.4 */
5393 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5394 /* PowerPC 745 v2.5 */
5395 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5396 /* PowerPC 755 v2.5 */
5397 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5398 /* PowerPC 745 v2.6 */
5399 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5400 /* PowerPC 755 v2.6 */
5401 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5402 /* PowerPC 745 v2.7 */
5403 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5404 /* PowerPC 755 v2.7 */
5405 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5406 /* PowerPC 745 v2.8 */
5407 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5408 /* PowerPC 755 v2.8 */
5409 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5410#if defined (TODO)
5411 /* PowerPC 745P (G3) */
5412 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5413 /* PowerPC 755P (G3) */
5414 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5415#endif
5416 /* PowerPC 74xx family */
5417 /* PowerPC 7400 (G4) */
5418 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5419 /* Code name for PowerPC 7400 */
5420 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5421 /* PowerPC 74xx is also well known as G4 */
5422 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5423 /* PowerPC 7400 v1.0 (G4) */
5424 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5425 /* PowerPC 7400 v1.1 (G4) */
5426 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5427 /* PowerPC 7400 v2.0 (G4) */
5428 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5429 /* PowerPC 7400 v2.2 (G4) */
5430 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5431 /* PowerPC 7400 v2.6 (G4) */
5432 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5433 /* PowerPC 7400 v2.7 (G4) */
5434 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5435 /* PowerPC 7400 v2.8 (G4) */
5436 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5437 /* PowerPC 7400 v2.9 (G4) */
5438 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5439 /* PowerPC 7410 (G4) */
5440 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5441 /* Code name for PowerPC 7410 */
5442 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5443 /* PowerPC 7410 v1.0 (G4) */
5444 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5445 /* PowerPC 7410 v1.1 (G4) */
5446 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5447 /* PowerPC 7410 v1.2 (G4) */
5448 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5449 /* PowerPC 7410 v1.3 (G4) */
5450 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5451 /* PowerPC 7410 v1.4 (G4) */
5452 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5453 /* PowerPC 7448 (G4) */
5454 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5455 /* PowerPC 7448 v1.0 (G4) */
5456 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5457 /* PowerPC 7448 v1.1 (G4) */
5458 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5459 /* PowerPC 7448 v2.0 (G4) */
5460 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5461 /* PowerPC 7448 v2.1 (G4) */
5462 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5463#if defined (TODO)
5464 /* PowerPC 7450 (G4) */
5465 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5466 /* Code name for PowerPC 7450 */
5467 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5468#endif
5469#if defined (TODO)
5470 /* PowerPC 7450 v1.0 (G4) */
5471 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5472#endif
5473#if defined (TODO)
5474 /* PowerPC 7450 v1.1 (G4) */
5475 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5476#endif
5477#if defined (TODO)
5478 /* PowerPC 7450 v1.2 (G4) */
5479 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5480#endif
5481#if defined (TODO)
5482 /* PowerPC 7450 v2.0 (G4) */
5483 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5484#endif
5485#if defined (TODO)
5486 /* PowerPC 7450 v2.1 (G4) */
5487 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5488#endif
5489#if defined (TODO)
5490 /* PowerPC 7441 (G4) */
5491 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5492 /* PowerPC 7451 (G4) */
5493 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5494#endif
3fc6c082 5495#if defined (TODO)
a750fc0b
JM		 5496 /* PowerPC 7441g (G4) */
5497 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5498 /* PowerPC 7451g (G4) */
5499 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
2662a059
JM		 5500#endif
5501#if defined (TODO)
a750fc0b
JM		 5502 /* PowerPC 7445 (G4) */
5503 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5504 /* PowerPC 7455 (G4) */
5505 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5506 /* Code name for PowerPC 7445/7455 */
5507 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
2662a059
JM		 5508#endif
5509#if defined (TODO)
a750fc0b
JM		 5510 /* PowerPC 7445 v1.0 (G4) */
5511 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5512 /* PowerPC 7455 v1.0 (G4) */
5513 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5514#endif
2662a059 5515#if defined (TODO)
a750fc0b
JM		 5516 /* PowerPC 7445 v2.1 (G4) */
5517 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5518 /* PowerPC 7455 v2.1 (G4) */
5519 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
2662a059
JM		 5520#endif
5521#if defined (TODO)
a750fc0b
JM		 5522 /* PowerPC 7445 v3.2 (G4) */
5523 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5524 /* PowerPC 7455 v3.2 (G4) */
5525 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
2662a059
JM		 5526#endif
5527#if defined (TODO)
a750fc0b
JM		 5528 /* PowerPC 7445 v3.3 (G4) */
5529 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5530 /* PowerPC 7455 v3.3 (G4) */
5531 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
3fc6c082
FB		 5532#endif
5533#if defined (TODO)
a750fc0b
JM		 5534 /* PowerPC 7445 v3.4 (G4) */
5535 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5536 /* PowerPC 7455 v3.4 (G4) */
5537 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
3a607854 5538#endif
04f20795 5539#if defined (TODO)
a750fc0b
JM		 5540 /* PowerPC 7447 (G4) */
5541 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5542 /* PowerPC 7457 (G4) */
5543 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5544 /* Code name for PowerPC 7447/7457 */
5545 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
3fc6c082
FB		 5546#endif
5547#if defined (TODO)
a750fc0b
JM		 5548 /* PowerPC 7447 v1.0 (G4) */
5549 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5550 /* PowerPC 7457 v1.0 (G4) */
5551 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5552 /* Code name for PowerPC 7447A/7457A */
5553 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
3a607854
JM		 5554#endif
5555#if defined (TODO)
a750fc0b
JM		 5556 /* PowerPC 7447 v1.1 (G4) */
5557 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5558 /* PowerPC 7457 v1.1 (G4) */
5559 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
3a607854
JM		 5560#endif
5561#if defined (TODO)
a750fc0b
JM		 5562 /* PowerPC 7447 v1.2 (G4) */
5563 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5564 /* PowerPC 7457 v1.2 (G4) */
5565 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5566#endif
5567 /* 64 bits PowerPC */
5568#if defined (TARGET_PPC64)
3fc6c082 5569#if defined (TODO)
a750fc0b
JM		 5570 /* PowerPC 620 */
5571 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5572#endif
3fc6c082 5573#if defined (TODO)
a750fc0b
JM		 5574 /* PowerPC 630 (POWER3) */
5575 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5576 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5577#endif
3a607854 5578#if defined (TODO)
a750fc0b
JM		 5579 /* PowerPC 631 (Power 3+) */
5580 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5581 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
3a607854
JM		 5582#endif
5583#if defined (TODO)
a750fc0b
JM		 5584 /* POWER4 */
5585 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5586#endif
3a607854 5587#if defined (TODO)
a750fc0b
JM		 5588 /* POWER4p */
5589 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5590#endif
2662a059 5591#if defined (TODO)
a750fc0b
JM		 5592 /* POWER5 */
5593 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5594 /* POWER5GR */
5595 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
2662a059 5596#endif
3a607854 5597#if defined (TODO)
a750fc0b
JM		 5598 /* POWER5+ */
5599 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5600 /* POWER5GS */
5601 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5602#endif
2662a059 5603#if defined (TODO)
a750fc0b
JM		 5604 /* POWER6 */
5605 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5606 /* POWER6 running in POWER5 mode */
5607 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5608 /* POWER6A */
5609 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
2662a059 5610#endif
a750fc0b
JM		 5611 /* PowerPC 970 */
5612 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
a750fc0b
JM		 5613 /* PowerPC 970FX (G5) */
5614 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5615 /* PowerPC 970FX v1.0 (G5) */
5616 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5617 /* PowerPC 970FX v2.0 (G5) */
5618 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5619 /* PowerPC 970FX v2.1 (G5) */
5620 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5621 /* PowerPC 970FX v3.0 (G5) */
5622 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5623 /* PowerPC 970FX v3.1 (G5) */
5624 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5625 /* PowerPC 970GX (G5) */
5626 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
a750fc0b
JM		 5627 /* PowerPC 970MP */
5628 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
a750fc0b
JM		 5629 /* PowerPC 970MP v1.0 */
5630 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
a750fc0b
JM		 5631 /* PowerPC 970MP v1.1 */
5632 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
3a607854 5633#if defined (TODO)
a750fc0b
JM		 5634 /* PowerPC Cell */
5635 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
2662a059
JM		 5636#endif
5637#if defined (TODO)
a750fc0b
JM		 5638 /* PowerPC Cell v1.0 */
5639 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
2662a059
JM		 5640#endif
5641#if defined (TODO)
a750fc0b
JM		 5642 /* PowerPC Cell v2.0 */
5643 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
2662a059
JM		 5644#endif
5645#if defined (TODO)
a750fc0b
JM		 5646 /* PowerPC Cell v3.0 */
5647 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
3a607854 5648#endif
3a607854 5649#if defined (TODO)
a750fc0b
JM		 5650 /* PowerPC Cell v3.1 */
5651 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
2662a059
JM		 5652#endif
5653#if defined (TODO)
a750fc0b
JM		 5654 /* PowerPC Cell v3.2 */
5655 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
2662a059
JM		 5656#endif
5657#if defined (TODO)
a750fc0b
JM		 5658 /* RS64 (Apache/A35) */
5659 /* This one seems to support the whole POWER2 instruction set
5660 * and the PowerPC 64 one.
5661 */
5662 /* What about A10 & A30 ? */
5663 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5664 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5665 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
3a607854
JM		 5666#endif
5667#if defined (TODO)
a750fc0b
JM		 5668 /* RS64-II (NorthStar/A50) */
5669 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5670 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5671 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
3a607854
JM		 5672#endif
5673#if defined (TODO)
a750fc0b
JM		 5674 /* RS64-III (Pulsar) */
5675 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5676 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
2662a059
JM		 5677#endif
5678#if defined (TODO)
a750fc0b
JM		 5679 /* RS64-IV (IceStar/IStar/SStar) */
5680 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5681 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5682 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5683 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
3a607854 5684#endif
a750fc0b
JM		 5685#endif /* defined (TARGET_PPC64) */
5686 /* POWER */
3fc6c082 5687#if defined (TODO)
a750fc0b
JM		 5688 /* Original POWER */
5689 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5690 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5691 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5692 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5693 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
76a66253
JM		 5694#endif
5695#if defined (TODO)
a750fc0b
JM		 5696 /* POWER2 */
5697 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5698 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5699 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5700#endif
5701 /* PA semi cores */
5702#if defined (TODO)
5703 /* PA PA6T */
5704 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5705#endif
5706 /* Generic PowerPCs */
5707#if defined (TARGET_PPC64)
5708#if defined (TODO)
5709 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5710#endif
5711#endif
5712 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
d12f4c38 5713 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b 5714 /* Fallback */
d12f4c38 5715 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b
JM		 5716};
5717
5718/*****************************************************************************/
5719/* Generic CPU instanciation routine */
5720static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5721{
5722#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 5723 int i;
5724
a750fc0b 5725 env->irq_inputs = NULL;
e1833e1f
JM		 5726 /* Set all exception vectors to an invalid address */
5727 for (i = 0; i < POWERPC_EXCP_NB; i++)
5728 env->excp_vectors[i] = (target_ulong)(-1ULL);
5729 env->excp_prefix = 0x00000000;
5730 env->ivor_mask = 0x00000000;
5731 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 5732#endif
5733 /* Default MMU definitions */
5734 env->nb_BATs = 0;
5735 env->nb_tlb = 0;
5736 env->nb_ways = 0;
5737 /* Register SPR common to all PowerPC implementations */
5738 gen_spr_generic(env);
5739 spr_register(env, SPR_PVR, "PVR",
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 &spr_read_generic, SPR_NOACCESS,
5742 def->pvr);
5743 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5744 (*def->init_proc)(env);
5745 /* Allocate TLBs buffer when needed */
5746 if (env->nb_tlb != 0) {
5747 int nb_tlb = env->nb_tlb;
5748 if (env->id_tlbs != 0)
5749 nb_tlb *= 2;
5750 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5751 /* Pre-compute some useful values */
5752 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5753 }
5754#if !defined(CONFIG_USER_ONLY)
5755 if (env->irq_inputs == NULL) {
5756 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5757 " Attempt Qemu to crash very soon !\n");
5758 }
5759#endif
5760}
5761
5762#if defined(PPC_DUMP_CPU)
5763static void dump_ppc_sprs (CPUPPCState *env)
5764{
5765 ppc_spr_t *spr;
5766#if !defined(CONFIG_USER_ONLY)
5767 uint32_t sr, sw;
5768#endif
5769 uint32_t ur, uw;
5770 int i, j, n;
5771
5772 printf("Special purpose registers:\n");
5773 for (i = 0; i < 32; i++) {
5774 for (j = 0; j < 32; j++) {
5775 n = (i << 5) | j;
5776 spr = &env->spr_cb[n];
5777 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5778 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5779#if !defined(CONFIG_USER_ONLY)
5780 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5781 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5782 if (sw || sr || uw || ur) {
5783 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5784 (i << 5) | j, (i << 5) | j, spr->name,
5785 sw ? 'w' : '-', sr ? 'r' : '-',
5786 uw ? 'w' : '-', ur ? 'r' : '-');
5787 }
5788#else
5789 if (uw || ur) {
5790 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5791 (i << 5) | j, (i << 5) | j, spr->name,
5792 uw ? 'w' : '-', ur ? 'r' : '-');
5793 }
5794#endif
5795 }
5796 }
5797 fflush(stdout);
5798 fflush(stderr);
5799}
5800#endif
5801
5802/*****************************************************************************/
5803#include <stdlib.h>
5804#include <string.h>
5805
5806int fflush (FILE *stream);
5807
5808/* Opcode types */
5809enum {
5810 PPC_DIRECT = 0, /* Opcode routine */
5811 PPC_INDIRECT = 1, /* Indirect opcode table */
5812};
5813
5814static inline int is_indirect_opcode (void *handler)
5815{
5816 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5817}
5818
5819static inline opc_handler_t **ind_table(void *handler)
5820{
5821 return (opc_handler_t **)((unsigned long)handler & ~3);
5822}
5823
5824/* Instruction table creation */
5825/* Opcodes tables creation */
5826static void fill_new_table (opc_handler_t **table, int len)
5827{
5828 int i;
5829
5830 for (i = 0; i < len; i++)
5831 table[i] = &invalid_handler;
5832}
5833
5834static int create_new_table (opc_handler_t **table, unsigned char idx)
5835{
5836 opc_handler_t **tmp;
5837
5838 tmp = malloc(0x20 * sizeof(opc_handler_t));
5839 if (tmp == NULL)
5840 return -1;
5841 fill_new_table(tmp, 0x20);
5842 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
5843
5844 return 0;
5845}
5846
5847static int insert_in_table (opc_handler_t **table, unsigned char idx,
5848 opc_handler_t *handler)
5849{
5850 if (table[idx] != &invalid_handler)
5851 return -1;
5852 table[idx] = handler;
5853
5854 return 0;
5855}
5856
5857static int register_direct_insn (opc_handler_t **ppc_opcodes,
5858 unsigned char idx, opc_handler_t *handler)
5859{
5860 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
5861 printf("*** ERROR: opcode %02x already assigned in main "
5862 "opcode table\n", idx);
5863 return -1;
5864 }
5865
5866 return 0;
5867}
5868
5869static int register_ind_in_table (opc_handler_t **table,
5870 unsigned char idx1, unsigned char idx2,
5871 opc_handler_t *handler)
5872{
5873 if (table[idx1] == &invalid_handler) {
5874 if (create_new_table(table, idx1) < 0) {
5875 printf("*** ERROR: unable to create indirect table "
5876 "idx=%02x\n", idx1);
5877 return -1;
5878 }
5879 } else {
5880 if (!is_indirect_opcode(table[idx1])) {
5881 printf("*** ERROR: idx %02x already assigned to a direct "
5882 "opcode\n", idx1);
5883 return -1;
5884 }
3a607854 5885 }
a750fc0b
JM		 5886 if (handler != NULL &&
5887 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
5888 printf("*** ERROR: opcode %02x already assigned in "
5889 "opcode table %02x\n", idx2, idx1);
5890 return -1;
3a607854 5891 }
a750fc0b
JM		 5892
5893 return 0;
5894}
5895
5896static int register_ind_insn (opc_handler_t **ppc_opcodes,
5897 unsigned char idx1, unsigned char idx2,
5898 opc_handler_t *handler)
5899{
5900 int ret;
5901
5902 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
5903
5904 return ret;
5905}
5906
5907static int register_dblind_insn (opc_handler_t **ppc_opcodes,
5908 unsigned char idx1, unsigned char idx2,
5909 unsigned char idx3, opc_handler_t *handler)
5910{
5911 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
5912 printf("*** ERROR: unable to join indirect table idx "
5913 "[%02x-%02x]\n", idx1, idx2);
5914 return -1;
5915 }
5916 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
5917 handler) < 0) {
5918 printf("*** ERROR: unable to insert opcode "
5919 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
5920 return -1;
5921 }
5922
5923 return 0;
5924}
5925
5926static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
5927{
5928 if (insn->opc2 != 0xFF) {
5929 if (insn->opc3 != 0xFF) {
5930 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
5931 insn->opc3, &insn->handler) < 0)
5932 return -1;
5933 } else {
5934 if (register_ind_insn(ppc_opcodes, insn->opc1,
5935 insn->opc2, &insn->handler) < 0)
5936 return -1;
5937 }
5938 } else {
5939 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
5940 return -1;
5941 }
5942
5943 return 0;
5944}
5945
5946static int test_opcode_table (opc_handler_t **table, int len)
5947{
5948 int i, count, tmp;
5949
5950 for (i = 0, count = 0; i < len; i++) {
5951 /* Consistency fixup */
5952 if (table[i] == NULL)
5953 table[i] = &invalid_handler;
5954 if (table[i] != &invalid_handler) {
5955 if (is_indirect_opcode(table[i])) {
5956 tmp = test_opcode_table(ind_table(table[i]), 0x20);
5957 if (tmp == 0) {
5958 free(table[i]);
5959 table[i] = &invalid_handler;
5960 } else {
5961 count++;
5962 }
5963 } else {
5964 count++;
5965 }
5966 }
5967 }
5968
5969 return count;
5970}
5971
5972static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
5973{
5974 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
5975 printf("*** WARNING: no opcode defined !\n");
5976}
5977
5978/*****************************************************************************/
5979static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
5980{
5981 opcode_t *opc, *start, *end;
5982
5983 fill_new_table(env->opcodes, 0x40);
5984 if (&opc_start < &opc_end) {
5985 start = &opc_start;
5986 end = &opc_end;
5987 } else {
5988 start = &opc_end;
5989 end = &opc_start;
5990 }
5991 for (opc = start + 1; opc != end; opc++) {
5992 if ((opc->handler.type & def->insns_flags) != 0) {
5993 if (register_insn(env->opcodes, opc) < 0) {
5994 printf("*** ERROR initializing PowerPC instruction "
5995 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
5996 opc->opc3);
5997 return -1;
5998 }
5999 }
6000 }
6001 fix_opcode_tables(env->opcodes);
6002 fflush(stdout);
6003 fflush(stderr);
6004
6005 return 0;
6006}
6007
6008#if defined(PPC_DUMP_CPU)
6009static int dump_ppc_insns (CPUPPCState *env)
6010{
6011 opc_handler_t **table, *handler;
6012 uint8_t opc1, opc2, opc3;
6013
6014 printf("Instructions set:\n");
6015 /* opc1 is 6 bits long */
6016 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6017 table = env->opcodes;
6018 handler = table[opc1];
6019 if (is_indirect_opcode(handler)) {
6020 /* opc2 is 5 bits long */
6021 for (opc2 = 0; opc2 < 0x20; opc2++) {
6022 table = env->opcodes;
6023 handler = env->opcodes[opc1];
6024 table = ind_table(handler);
6025 handler = table[opc2];
6026 if (is_indirect_opcode(handler)) {
6027 table = ind_table(handler);
6028 /* opc3 is 5 bits long */
6029 for (opc3 = 0; opc3 < 0x20; opc3++) {
6030 handler = table[opc3];
6031 if (handler->handler != &gen_invalid) {
6032 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6033 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6034 handler->oname);
6035 }
6036 }
6037 } else {
6038 if (handler->handler != &gen_invalid) {
6039 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6040 opc1, opc2, opc1, opc2, handler->oname);
6041 }
6042 }
6043 }
6044 } else {
6045 if (handler->handler != &gen_invalid) {
6046 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6047 opc1, opc1, handler->oname);
6048 }
6049 }
6050 }
6051}
3a607854 6052#endif
a750fc0b
JM		 6053
6054int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6055{
6056 env->msr_mask = def->msr_mask;
6057 env->mmu_model = def->mmu_model;
6058 env->excp_model = def->excp_model;
6059 env->bus_model = def->bus_model;
d26bfc9a 6060 env->flags = def->flags;
237c0af0 6061 env->bfd_mach = def->bfd_mach;
a750fc0b
JM		 6062 if (create_ppc_opcodes(env, def) < 0)
6063 return -1;
6064 init_ppc_proc(env, def);
6065#if defined(PPC_DUMP_CPU)
3a607854 6066 {
a750fc0b
JM		 6067 const unsigned char *mmu_model, *excp_model, *bus_model;
6068 switch (env->mmu_model) {
6069 case POWERPC_MMU_32B:
6070 mmu_model = "PowerPC 32";
6071 break;
a750fc0b
JM		 6072 case POWERPC_MMU_601:
6073 mmu_model = "PowerPC 601";
6074 break;
6075 case POWERPC_MMU_SOFT_6xx:
6076 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6077 break;
6078 case POWERPC_MMU_SOFT_74xx:
6079 mmu_model = "PowerPC 74xx with software driven TLBs";
6080 break;
6081 case POWERPC_MMU_SOFT_4xx:
6082 mmu_model = "PowerPC 4xx with software driven TLBs";
6083 break;
6084 case POWERPC_MMU_SOFT_4xx_Z:
6085 mmu_model = "PowerPC 4xx with software driven TLBs "
6086 "and zones protections";
6087 break;
6088 case POWERPC_MMU_REAL_4xx:
6089 mmu_model = "PowerPC 4xx real mode only";
6090 break;
6091 case POWERPC_MMU_BOOKE:
6092 mmu_model = "PowerPC BookE";
6093 break;
6094 case POWERPC_MMU_BOOKE_FSL:
6095 mmu_model = "PowerPC BookE FSL";
6096 break;
00af685f
JM		 6097#if defined (TARGET_PPC64)
6098 case POWERPC_MMU_64B:
6099 mmu_model = "PowerPC 64";
6100 break;
00af685f 6101#endif
a750fc0b
JM		 6102 default:
6103 mmu_model = "Unknown or invalid";
6104 break;
6105 }
6106 switch (env->excp_model) {
6107 case POWERPC_EXCP_STD:
6108 excp_model = "PowerPC";
6109 break;
6110 case POWERPC_EXCP_40x:
6111 excp_model = "PowerPC 40x";
6112 break;
6113 case POWERPC_EXCP_601:
6114 excp_model = "PowerPC 601";
6115 break;
6116 case POWERPC_EXCP_602:
6117 excp_model = "PowerPC 602";
6118 break;
6119 case POWERPC_EXCP_603:
6120 excp_model = "PowerPC 603";
6121 break;
6122 case POWERPC_EXCP_603E:
6123 excp_model = "PowerPC 603e";
6124 break;
6125 case POWERPC_EXCP_604:
6126 excp_model = "PowerPC 604";
6127 break;
6128 case POWERPC_EXCP_7x0:
6129 excp_model = "PowerPC 740/750";
6130 break;
6131 case POWERPC_EXCP_7x5:
6132 excp_model = "PowerPC 745/755";
6133 break;
6134 case POWERPC_EXCP_74xx:
6135 excp_model = "PowerPC 74xx";
6136 break;
a750fc0b
JM		 6137 case POWERPC_EXCP_BOOKE:
6138 excp_model = "PowerPC BookE";
6139 break;
00af685f
JM		 6140#if defined (TARGET_PPC64)
6141 case POWERPC_EXCP_970:
6142 excp_model = "PowerPC 970";
6143 break;
6144#endif
a750fc0b
JM		 6145 default:
6146 excp_model = "Unknown or invalid";
6147 break;
6148 }
6149 switch (env->bus_model) {
6150 case PPC_FLAGS_INPUT_6xx:
6151 bus_model = "PowerPC 6xx";
6152 break;
6153 case PPC_FLAGS_INPUT_BookE:
6154 bus_model = "PowerPC BookE";
6155 break;
6156 case PPC_FLAGS_INPUT_405:
6157 bus_model = "PowerPC 405";
6158 break;
a750fc0b
JM		 6159 case PPC_FLAGS_INPUT_401:
6160 bus_model = "PowerPC 401/403";
6161 break;
00af685f
JM		 6162#if defined (TARGET_PPC64)
6163 case PPC_FLAGS_INPUT_970:
6164 bus_model = "PowerPC 970";
6165 break;
6166#endif
a750fc0b
JM		 6167 default:
6168 bus_model = "Unknown or invalid";
6169 break;
6170 }
6171 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6172 " MMU model : %s\n",
6173 def->name, def->pvr, def->msr_mask, mmu_model);
6174 if (env->tlb != NULL) {
6175 printf(" %d %s TLB in %d ways\n",
6176 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6177 env->nb_ways);
6178 }
6179 printf(" Exceptions model : %s\n"
6180 " Bus model : %s\n",
6181 excp_model, bus_model);
6182 }
6183 dump_ppc_insns(env);
6184 dump_ppc_sprs(env);
6185 fflush(stdout);
3a607854 6186#endif
a750fc0b
JM		 6187
6188 return 0;
6189}
3fc6c082
FB		 6190
6191int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6192{
068abdc8 6193 int i, max, ret;
3fc6c082
FB		 6194
6195 ret = -1;
6196 *def = NULL;
068abdc8
JM		 6197 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6198 for (i = 0; i < max; i++) {
3fc6c082
FB		 6199 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6200 *def = &ppc_defs[i];
6201 ret = 0;
6202 break;
6203 }
6204 }
6205
6206 return ret;
6207}
6208
6209int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6210{
068abdc8 6211 int i, max, ret;
3fc6c082
FB		 6212
6213 ret = -1;
6214 *def = NULL;
068abdc8
JM		 6215 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6216 for (i = 0; i < max; i++) {
3fc6c082
FB		 6217 if ((pvr & ppc_defs[i].pvr_mask) ==
6218 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6219 *def = &ppc_defs[i];
6220 ret = 0;
6221 break;
6222 }
6223 }
6224
6225 return ret;
6226}
6227
6228void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6229{
068abdc8 6230 int i, max;
3fc6c082 6231
068abdc8
JM		 6232 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6233 for (i = 0; i < max; i++) {
a750fc0b
JM		 6234 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6235 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 6236 }
6237}
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