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Fix incorrect PowerPC instruction fetch exception dump.
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
237c0af0
JM		 26#include "dis-asm.h"
27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
a496775f 30//#define PPC_DEBUG_IRQ
3fc6c082
FB		 31
32struct ppc_def_t {
33 const unsigned char *name;
34 uint32_t pvr;
35 uint32_t pvr_mask;
0487d6a8 36 uint64_t insns_flags;
3fc6c082 37 uint64_t msr_mask;
a750fc0b
JM		 38 uint8_t mmu_model;
39 uint8_t excp_model;
40 uint8_t bus_model;
41 uint8_t pad;
d26bfc9a 42 uint32_t flags;
237c0af0 43 int bfd_mach;
a750fc0b 44 void (*init_proc)(CPUPPCState *env);
2f462816 45 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 46};
47
e9df014c
JM		 48/* For user-mode emulation, we don't emulate any IRQ controller */
49#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 50#define PPC_IRQ_INIT_FN(name) \
51static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
52{ \
e9df014c
JM		 53}
54#else
a750fc0b 55#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 56void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
57#endif
a750fc0b 58
4e290a0b 59PPC_IRQ_INIT_FN(40x);
e9df014c 60PPC_IRQ_INIT_FN(6xx);
d0dfae6e 61PPC_IRQ_INIT_FN(970);
e9df014c 62
3fc6c082
FB		 63/* Generic callbacks:
64 * do nothing but store/retrieve spr value
65 */
04f20795 66#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 67static void spr_read_generic (void *opaque, int sprn)
68{
04f20795 69 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 70}
71
72static void spr_write_generic (void *opaque, int sprn)
73{
04f20795 74 gen_op_store_dump_spr(sprn);
3fc6c082 75}
04f20795
JM		 76#else
77static void spr_read_generic (void *opaque, int sprn)
a496775f 78{
04f20795 79 gen_op_load_spr(sprn);
a496775f
JM		 80}
81
04f20795 82static void spr_write_generic (void *opaque, int sprn)
a496775f 83{
04f20795 84 gen_op_store_spr(sprn);
a496775f 85}
04f20795 86#endif
a496775f
JM		 87
88#if !defined(CONFIG_USER_ONLY)
89static void spr_write_clear (void *opaque, int sprn)
90{
91 gen_op_mask_spr(sprn);
92}
93#endif
94
76a66253 95/* SPR common to all PowerPC */
3fc6c082
FB		 96/* XER */
97static void spr_read_xer (void *opaque, int sprn)
98{
99 gen_op_load_xer();
100}
101
102static void spr_write_xer (void *opaque, int sprn)
103{
104 gen_op_store_xer();
105}
106
107/* LR */
108static void spr_read_lr (void *opaque, int sprn)
109{
110 gen_op_load_lr();
111}
112
113static void spr_write_lr (void *opaque, int sprn)
114{
115 gen_op_store_lr();
116}
117
118/* CTR */
119static void spr_read_ctr (void *opaque, int sprn)
120{
121 gen_op_load_ctr();
122}
123
124static void spr_write_ctr (void *opaque, int sprn)
125{
126 gen_op_store_ctr();
127}
128
129/* User read access to SPR */
130/* USPRx */
131/* UMMCRx */
132/* UPMCx */
133/* USIA */
134/* UDECR */
135static void spr_read_ureg (void *opaque, int sprn)
136{
137 gen_op_load_spr(sprn + 0x10);
138}
139
76a66253 140/* SPR common to all non-embedded PowerPC */
3fc6c082 141/* DECR */
76a66253 142#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 143static void spr_read_decr (void *opaque, int sprn)
144{
145 gen_op_load_decr();
146}
147
148static void spr_write_decr (void *opaque, int sprn)
149{
150 gen_op_store_decr();
151}
76a66253 152#endif
3fc6c082 153
76a66253 154/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 155/* Time base */
156static void spr_read_tbl (void *opaque, int sprn)
157{
158 gen_op_load_tbl();
159}
160
76a66253 161static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 162{
76a66253 163 gen_op_load_tbu();
3fc6c082
FB		 164}
165
a062e36c
JM		 166__attribute__ (( unused ))
167static void spr_read_atbl (void *opaque, int sprn)
168{
169 gen_op_load_atbl();
170}
171
172__attribute__ (( unused ))
173static void spr_read_atbu (void *opaque, int sprn)
174{
175 gen_op_load_atbu();
176}
177
76a66253
JM		 178#if !defined(CONFIG_USER_ONLY)
179static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 180{
76a66253 181 gen_op_store_tbl();
3fc6c082
FB		 182}
183
184static void spr_write_tbu (void *opaque, int sprn)
185{
186 gen_op_store_tbu();
187}
a062e36c
JM		 188
189__attribute__ (( unused ))
190static void spr_write_atbl (void *opaque, int sprn)
191{
192 gen_op_store_atbl();
193}
194
195__attribute__ (( unused ))
196static void spr_write_atbu (void *opaque, int sprn)
197{
198 gen_op_store_atbu();
199}
76a66253 200#endif
3fc6c082 201
76a66253 202#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 203/* IBAT0U...IBAT0U */
204/* IBAT0L...IBAT7L */
205static void spr_read_ibat (void *opaque, int sprn)
206{
207 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
208}
209
210static void spr_read_ibat_h (void *opaque, int sprn)
211{
212 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
213}
214
215static void spr_write_ibatu (void *opaque, int sprn)
216{
3fc6c082 217 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
3fc6c082
FB		 218}
219
220static void spr_write_ibatu_h (void *opaque, int sprn)
221{
3fc6c082 222 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
3fc6c082
FB		 223}
224
225static void spr_write_ibatl (void *opaque, int sprn)
226{
3fc6c082 227 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
3fc6c082
FB		 228}
229
230static void spr_write_ibatl_h (void *opaque, int sprn)
231{
3fc6c082 232 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
3fc6c082
FB		 233}
234
235/* DBAT0U...DBAT7U */
236/* DBAT0L...DBAT7L */
237static void spr_read_dbat (void *opaque, int sprn)
238{
239 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
240}
241
242static void spr_read_dbat_h (void *opaque, int sprn)
243{
244 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
245}
246
247static void spr_write_dbatu (void *opaque, int sprn)
248{
3fc6c082 249 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
3fc6c082
FB		 250}
251
252static void spr_write_dbatu_h (void *opaque, int sprn)
253{
3fc6c082 254 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
3fc6c082
FB		 255}
256
257static void spr_write_dbatl (void *opaque, int sprn)
258{
3fc6c082 259 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
3fc6c082
FB		 260}
261
262static void spr_write_dbatl_h (void *opaque, int sprn)
263{
3fc6c082 264 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
3fc6c082
FB		 265}
266
267/* SDR1 */
268static void spr_read_sdr1 (void *opaque, int sprn)
269{
270 gen_op_load_sdr1();
271}
272
273static void spr_write_sdr1 (void *opaque, int sprn)
274{
3fc6c082 275 gen_op_store_sdr1();
3fc6c082
FB		 276}
277
76a66253
JM		 278/* 64 bits PowerPC specific SPRs */
279/* ASR */
578bb252
JM		 280#if defined(TARGET_PPC64)
281__attribute__ (( unused ))
76a66253
JM		 282static void spr_read_asr (void *opaque, int sprn)
283{
284 gen_op_load_asr();
285}
286
578bb252 287__attribute__ (( unused ))
76a66253
JM		 288static void spr_write_asr (void *opaque, int sprn)
289{
76a66253 290 gen_op_store_asr();
76a66253
JM		 291}
292#endif
a750fc0b 293#endif
76a66253
JM		 294
295/* PowerPC 601 specific registers */
296/* RTC */
297static void spr_read_601_rtcl (void *opaque, int sprn)
298{
299 gen_op_load_601_rtcl();
300}
301
302static void spr_read_601_rtcu (void *opaque, int sprn)
303{
304 gen_op_load_601_rtcu();
305}
306
307#if !defined(CONFIG_USER_ONLY)
308static void spr_write_601_rtcu (void *opaque, int sprn)
309{
310 gen_op_store_601_rtcu();
311}
312
313static void spr_write_601_rtcl (void *opaque, int sprn)
314{
315 gen_op_store_601_rtcl();
316}
317#endif
318
319/* Unified bats */
320#if !defined(CONFIG_USER_ONLY)
321static void spr_read_601_ubat (void *opaque, int sprn)
322{
323 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
324}
325
326static void spr_write_601_ubatu (void *opaque, int sprn)
327{
76a66253 328 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
76a66253
JM		 329}
330
331static void spr_write_601_ubatl (void *opaque, int sprn)
332{
76a66253 333 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
76a66253
JM		 334}
335#endif
336
337/* PowerPC 40x specific registers */
338#if !defined(CONFIG_USER_ONLY)
339static void spr_read_40x_pit (void *opaque, int sprn)
340{
341 gen_op_load_40x_pit();
342}
343
344static void spr_write_40x_pit (void *opaque, int sprn)
345{
346 gen_op_store_40x_pit();
347}
348
8ecc7913
JM		 349static void spr_write_40x_dbcr0 (void *opaque, int sprn)
350{
351 DisasContext *ctx = opaque;
352
353 gen_op_store_40x_dbcr0();
354 /* We must stop translation as we may have rebooted */
e1833e1f 355 GEN_STOP(ctx);
8ecc7913
JM		 356}
357
c294fc58
JM		 358static void spr_write_40x_sler (void *opaque, int sprn)
359{
c294fc58 360 gen_op_store_40x_sler();
c294fc58
JM		 361}
362
76a66253
JM		 363static void spr_write_booke_tcr (void *opaque, int sprn)
364{
365 gen_op_store_booke_tcr();
366}
367
368static void spr_write_booke_tsr (void *opaque, int sprn)
369{
370 gen_op_store_booke_tsr();
371}
372#endif
373
374/* PowerPC 403 specific registers */
375/* PBL1 / PBU1 / PBL2 / PBU2 */
376#if !defined(CONFIG_USER_ONLY)
377static void spr_read_403_pbr (void *opaque, int sprn)
378{
379 gen_op_load_403_pb(sprn - SPR_403_PBL1);
380}
381
382static void spr_write_403_pbr (void *opaque, int sprn)
383{
76a66253 384 gen_op_store_403_pb(sprn - SPR_403_PBL1);
76a66253
JM		 385}
386
3fc6c082
FB		 387static void spr_write_pir (void *opaque, int sprn)
388{
389 gen_op_store_pir();
390}
76a66253 391#endif
3fc6c082 392
6f5d427d
JM		 393#if !defined(CONFIG_USER_ONLY)
394/* Callback used to write the exception vector base */
395static void spr_write_excp_prefix (void *opaque, int sprn)
396{
397 gen_op_store_excp_prefix();
398 gen_op_store_spr(sprn);
399}
400
401static void spr_write_excp_vector (void *opaque, int sprn)
402{
403 DisasContext *ctx = opaque;
404
405 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
406 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
407 gen_op_store_spr(sprn);
408 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
409 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
410 gen_op_store_spr(sprn);
411 } else {
412 printf("Trying to write an unknown exception vector %d %03x\n",
413 sprn, sprn);
414 GEN_EXCP_PRIVREG(ctx);
415 }
416}
417#endif
418
76a66253
JM		 419#if defined(CONFIG_USER_ONLY)
420#define spr_register(env, num, name, uea_read, uea_write, \
421 oea_read, oea_write, initial_value) \
422do { \
423 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
424} while (0)
425static inline void _spr_register (CPUPPCState *env, int num,
426 const unsigned char *name,
427 void (*uea_read)(void *opaque, int sprn),
428 void (*uea_write)(void *opaque, int sprn),
429 target_ulong initial_value)
430#else
3fc6c082
FB		 431static inline void spr_register (CPUPPCState *env, int num,
432 const unsigned char *name,
433 void (*uea_read)(void *opaque, int sprn),
434 void (*uea_write)(void *opaque, int sprn),
435 void (*oea_read)(void *opaque, int sprn),
436 void (*oea_write)(void *opaque, int sprn),
437 target_ulong initial_value)
76a66253 438#endif
3fc6c082
FB		 439{
440 ppc_spr_t *spr;
441
442 spr = &env->spr_cb[num];
443 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 444#if !defined(CONFIG_USER_ONLY)
445 spr->oea_read != NULL || spr->oea_write != NULL ||
446#endif
447 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 448 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
449 exit(1);
450 }
451#if defined(PPC_DEBUG_SPR)
1b9eb036 452 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 453 initial_value);
3fc6c082
FB		 454#endif
455 spr->name = name;
456 spr->uea_read = uea_read;
457 spr->uea_write = uea_write;
76a66253 458#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 459 spr->oea_read = oea_read;
460 spr->oea_write = oea_write;
76a66253 461#endif
3fc6c082
FB		 462 env->spr[num] = initial_value;
463}
464
465/* Generic PowerPC SPRs */
466static void gen_spr_generic (CPUPPCState *env)
467{
468 /* Integer processing */
469 spr_register(env, SPR_XER, "XER",
470 &spr_read_xer, &spr_write_xer,
471 &spr_read_xer, &spr_write_xer,
472 0x00000000);
473 /* Branch contol */
474 spr_register(env, SPR_LR, "LR",
475 &spr_read_lr, &spr_write_lr,
476 &spr_read_lr, &spr_write_lr,
477 0x00000000);
478 spr_register(env, SPR_CTR, "CTR",
479 &spr_read_ctr, &spr_write_ctr,
480 &spr_read_ctr, &spr_write_ctr,
481 0x00000000);
482 /* Interrupt processing */
483 spr_register(env, SPR_SRR0, "SRR0",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 spr_register(env, SPR_SRR1, "SRR1",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491 /* Processor control */
492 spr_register(env, SPR_SPRG0, "SPRG0",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 0x00000000);
496 spr_register(env, SPR_SPRG1, "SPRG1",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 0x00000000);
500 spr_register(env, SPR_SPRG2, "SPRG2",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 spr_register(env, SPR_SPRG3, "SPRG3",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508}
509
510/* SPR common to all non-embedded PowerPC, including 601 */
511static void gen_spr_ne_601 (CPUPPCState *env)
512{
513 /* Exception processing */
514 spr_register(env, SPR_DSISR, "DSISR",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518 spr_register(env, SPR_DAR, "DAR",
519 SPR_NOACCESS, SPR_NOACCESS,
520 &spr_read_generic, &spr_write_generic,
521 0x00000000);
522 /* Timer */
523 spr_register(env, SPR_DECR, "DECR",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_decr, &spr_write_decr,
526 0x00000000);
527 /* Memory management */
528 spr_register(env, SPR_SDR1, "SDR1",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_sdr1, &spr_write_sdr1,
531 0x00000000);
532}
533
534/* BATs 0-3 */
535static void gen_low_BATs (CPUPPCState *env)
536{
f2e63a42 537#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 538 spr_register(env, SPR_IBAT0U, "IBAT0U",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_ibat, &spr_write_ibatu,
541 0x00000000);
542 spr_register(env, SPR_IBAT0L, "IBAT0L",
543 SPR_NOACCESS, SPR_NOACCESS,
544 &spr_read_ibat, &spr_write_ibatl,
545 0x00000000);
546 spr_register(env, SPR_IBAT1U, "IBAT1U",
547 SPR_NOACCESS, SPR_NOACCESS,
548 &spr_read_ibat, &spr_write_ibatu,
549 0x00000000);
550 spr_register(env, SPR_IBAT1L, "IBAT1L",
551 SPR_NOACCESS, SPR_NOACCESS,
552 &spr_read_ibat, &spr_write_ibatl,
553 0x00000000);
554 spr_register(env, SPR_IBAT2U, "IBAT2U",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_ibat, &spr_write_ibatu,
557 0x00000000);
558 spr_register(env, SPR_IBAT2L, "IBAT2L",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_ibat, &spr_write_ibatl,
561 0x00000000);
562 spr_register(env, SPR_IBAT3U, "IBAT3U",
563 SPR_NOACCESS, SPR_NOACCESS,
564 &spr_read_ibat, &spr_write_ibatu,
565 0x00000000);
566 spr_register(env, SPR_IBAT3L, "IBAT3L",
567 SPR_NOACCESS, SPR_NOACCESS,
568 &spr_read_ibat, &spr_write_ibatl,
569 0x00000000);
570 spr_register(env, SPR_DBAT0U, "DBAT0U",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_dbat, &spr_write_dbatu,
573 0x00000000);
574 spr_register(env, SPR_DBAT0L, "DBAT0L",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_dbat, &spr_write_dbatl,
577 0x00000000);
578 spr_register(env, SPR_DBAT1U, "DBAT1U",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_dbat, &spr_write_dbatu,
581 0x00000000);
582 spr_register(env, SPR_DBAT1L, "DBAT1L",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_dbat, &spr_write_dbatl,
585 0x00000000);
586 spr_register(env, SPR_DBAT2U, "DBAT2U",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_dbat, &spr_write_dbatu,
589 0x00000000);
590 spr_register(env, SPR_DBAT2L, "DBAT2L",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_dbat, &spr_write_dbatl,
593 0x00000000);
594 spr_register(env, SPR_DBAT3U, "DBAT3U",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_dbat, &spr_write_dbatu,
597 0x00000000);
598 spr_register(env, SPR_DBAT3L, "DBAT3L",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_dbat, &spr_write_dbatl,
601 0x00000000);
a750fc0b 602 env->nb_BATs += 4;
f2e63a42 603#endif
3fc6c082
FB		 604}
605
606/* BATs 4-7 */
607static void gen_high_BATs (CPUPPCState *env)
608{
f2e63a42 609#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 610 spr_register(env, SPR_IBAT4U, "IBAT4U",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat_h, &spr_write_ibatu_h,
613 0x00000000);
614 spr_register(env, SPR_IBAT4L, "IBAT4L",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat_h, &spr_write_ibatl_h,
617 0x00000000);
618 spr_register(env, SPR_IBAT5U, "IBAT5U",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat_h, &spr_write_ibatu_h,
621 0x00000000);
622 spr_register(env, SPR_IBAT5L, "IBAT5L",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatl_h,
625 0x00000000);
626 spr_register(env, SPR_IBAT6U, "IBAT6U",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatu_h,
629 0x00000000);
630 spr_register(env, SPR_IBAT6L, "IBAT6L",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat_h, &spr_write_ibatl_h,
633 0x00000000);
634 spr_register(env, SPR_IBAT7U, "IBAT7U",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_ibat_h, &spr_write_ibatu_h,
637 0x00000000);
638 spr_register(env, SPR_IBAT7L, "IBAT7L",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_ibat_h, &spr_write_ibatl_h,
641 0x00000000);
642 spr_register(env, SPR_DBAT4U, "DBAT4U",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat_h, &spr_write_dbatu_h,
645 0x00000000);
646 spr_register(env, SPR_DBAT4L, "DBAT4L",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat_h, &spr_write_dbatl_h,
649 0x00000000);
650 spr_register(env, SPR_DBAT5U, "DBAT5U",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat_h, &spr_write_dbatu_h,
653 0x00000000);
654 spr_register(env, SPR_DBAT5L, "DBAT5L",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatl_h,
657 0x00000000);
658 spr_register(env, SPR_DBAT6U, "DBAT6U",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatu_h,
661 0x00000000);
662 spr_register(env, SPR_DBAT6L, "DBAT6L",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat_h, &spr_write_dbatl_h,
665 0x00000000);
666 spr_register(env, SPR_DBAT7U, "DBAT7U",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_dbat_h, &spr_write_dbatu_h,
669 0x00000000);
670 spr_register(env, SPR_DBAT7L, "DBAT7L",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_dbat_h, &spr_write_dbatl_h,
673 0x00000000);
a750fc0b 674 env->nb_BATs += 4;
f2e63a42 675#endif
3fc6c082
FB		 676}
677
678/* Generic PowerPC time base */
679static void gen_tbl (CPUPPCState *env)
680{
681 spr_register(env, SPR_VTBL, "TBL",
682 &spr_read_tbl, SPR_NOACCESS,
683 &spr_read_tbl, SPR_NOACCESS,
684 0x00000000);
685 spr_register(env, SPR_TBL, "TBL",
686 SPR_NOACCESS, SPR_NOACCESS,
687 SPR_NOACCESS, &spr_write_tbl,
688 0x00000000);
689 spr_register(env, SPR_VTBU, "TBU",
690 &spr_read_tbu, SPR_NOACCESS,
691 &spr_read_tbu, SPR_NOACCESS,
692 0x00000000);
693 spr_register(env, SPR_TBU, "TBU",
694 SPR_NOACCESS, SPR_NOACCESS,
695 SPR_NOACCESS, &spr_write_tbu,
696 0x00000000);
697}
698
76a66253
JM		 699/* Softare table search registers */
700static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
701{
f2e63a42 702#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 703 env->nb_tlb = nb_tlbs;
704 env->nb_ways = nb_ways;
705 env->id_tlbs = 1;
706 spr_register(env, SPR_DMISS, "DMISS",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, SPR_NOACCESS,
709 0x00000000);
710 spr_register(env, SPR_DCMP, "DCMP",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, SPR_NOACCESS,
713 0x00000000);
714 spr_register(env, SPR_HASH1, "HASH1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, SPR_NOACCESS,
717 0x00000000);
718 spr_register(env, SPR_HASH2, "HASH2",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, SPR_NOACCESS,
721 0x00000000);
722 spr_register(env, SPR_IMISS, "IMISS",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, SPR_NOACCESS,
725 0x00000000);
726 spr_register(env, SPR_ICMP, "ICMP",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, SPR_NOACCESS,
729 0x00000000);
730 spr_register(env, SPR_RPA, "RPA",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
f2e63a42 734#endif
76a66253
JM		 735}
736
737/* SPR common to MPC755 and G2 */
738static void gen_spr_G2_755 (CPUPPCState *env)
739{
740 /* SGPRs */
741 spr_register(env, SPR_SPRG4, "SPRG4",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 spr_register(env, SPR_SPRG5, "SPRG5",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_generic, &spr_write_generic,
748 0x00000000);
749 spr_register(env, SPR_SPRG6, "SPRG6",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_generic,
752 0x00000000);
753 spr_register(env, SPR_SPRG7, "SPRG7",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 /* External access control */
758 /* XXX : not implemented */
759 spr_register(env, SPR_EAR, "EAR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763}
764
3fc6c082
FB		 765/* SPR common to all 7xx PowerPC implementations */
766static void gen_spr_7xx (CPUPPCState *env)
767{
768 /* Breakpoints */
769 /* XXX : not implemented */
770 spr_register(env, SPR_DABR, "DABR",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
773 0x00000000);
774 /* XXX : not implemented */
775 spr_register(env, SPR_IABR, "IABR",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 0x00000000);
779 /* Cache management */
780 /* XXX : not implemented */
781 spr_register(env, SPR_ICTC, "ICTC",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_generic, &spr_write_generic,
784 0x00000000);
76a66253
JM		 785 /* XXX : not implemented */
786 spr_register(env, SPR_L2CR, "L2CR",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_generic,
789 0x00000000);
3fc6c082
FB		 790 /* Performance monitors */
791 /* XXX : not implemented */
792 spr_register(env, SPR_MMCR0, "MMCR0",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_generic, &spr_write_generic,
795 0x00000000);
796 /* XXX : not implemented */
797 spr_register(env, SPR_MMCR1, "MMCR1",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 /* XXX : not implemented */
802 spr_register(env, SPR_PMC1, "PMC1",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 /* XXX : not implemented */
807 spr_register(env, SPR_PMC2, "PMC2",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811 /* XXX : not implemented */
812 spr_register(env, SPR_PMC3, "PMC3",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 /* XXX : not implemented */
817 spr_register(env, SPR_PMC4, "PMC4",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
821 /* XXX : not implemented */
a750fc0b 822 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, SPR_NOACCESS,
825 0x00000000);
578bb252 826 /* XXX : not implemented */
3fc6c082
FB		 827 spr_register(env, SPR_UMMCR0, "UMMCR0",
828 &spr_read_ureg, SPR_NOACCESS,
829 &spr_read_ureg, SPR_NOACCESS,
830 0x00000000);
578bb252 831 /* XXX : not implemented */
3fc6c082
FB		 832 spr_register(env, SPR_UMMCR1, "UMMCR1",
833 &spr_read_ureg, SPR_NOACCESS,
834 &spr_read_ureg, SPR_NOACCESS,
835 0x00000000);
578bb252 836 /* XXX : not implemented */
3fc6c082
FB		 837 spr_register(env, SPR_UPMC1, "UPMC1",
838 &spr_read_ureg, SPR_NOACCESS,
839 &spr_read_ureg, SPR_NOACCESS,
840 0x00000000);
578bb252 841 /* XXX : not implemented */
3fc6c082
FB		 842 spr_register(env, SPR_UPMC2, "UPMC2",
843 &spr_read_ureg, SPR_NOACCESS,
844 &spr_read_ureg, SPR_NOACCESS,
845 0x00000000);
578bb252 846 /* XXX : not implemented */
3fc6c082
FB		 847 spr_register(env, SPR_UPMC3, "UPMC3",
848 &spr_read_ureg, SPR_NOACCESS,
849 &spr_read_ureg, SPR_NOACCESS,
850 0x00000000);
578bb252 851 /* XXX : not implemented */
3fc6c082
FB		 852 spr_register(env, SPR_UPMC4, "UPMC4",
853 &spr_read_ureg, SPR_NOACCESS,
854 &spr_read_ureg, SPR_NOACCESS,
855 0x00000000);
578bb252 856 /* XXX : not implemented */
a750fc0b 857 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 858 &spr_read_ureg, SPR_NOACCESS,
859 &spr_read_ureg, SPR_NOACCESS,
860 0x00000000);
a750fc0b 861 /* External access control */
3fc6c082 862 /* XXX : not implemented */
a750fc0b 863 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, &spr_write_generic,
866 0x00000000);
a750fc0b
JM		 867}
868
869static void gen_spr_thrm (CPUPPCState *env)
870{
871 /* Thermal management */
3fc6c082 872 /* XXX : not implemented */
a750fc0b 873 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
877 /* XXX : not implemented */
a750fc0b 878 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_generic,
881 0x00000000);
3fc6c082 882 /* XXX : not implemented */
a750fc0b 883 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887}
888
889/* SPR specific to PowerPC 604 implementation */
890static void gen_spr_604 (CPUPPCState *env)
891{
892 /* Processor identification */
893 spr_register(env, SPR_PIR, "PIR",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_pir,
896 0x00000000);
897 /* Breakpoints */
898 /* XXX : not implemented */
899 spr_register(env, SPR_IABR, "IABR",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 /* XXX : not implemented */
904 spr_register(env, SPR_DABR, "DABR",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, &spr_write_generic,
907 0x00000000);
908 /* Performance counters */
909 /* XXX : not implemented */
910 spr_register(env, SPR_MMCR0, "MMCR0",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* XXX : not implemented */
915 spr_register(env, SPR_MMCR1, "MMCR1",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 /* XXX : not implemented */
920 spr_register(env, SPR_PMC1, "PMC1",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 /* XXX : not implemented */
925 spr_register(env, SPR_PMC2, "PMC2",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_generic,
928 0x00000000);
929 /* XXX : not implemented */
930 spr_register(env, SPR_PMC3, "PMC3",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* XXX : not implemented */
935 spr_register(env, SPR_PMC4, "PMC4",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 /* XXX : not implemented */
a750fc0b 940 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, SPR_NOACCESS,
943 0x00000000);
944 /* XXX : not implemented */
945 spr_register(env, SPR_SDA, "SDA",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, SPR_NOACCESS,
948 0x00000000);
949 /* External access control */
950 /* XXX : not implemented */
951 spr_register(env, SPR_EAR, "EAR",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955}
956
76a66253
JM		 957/* SPR specific to PowerPC 603 implementation */
958static void gen_spr_603 (CPUPPCState *env)
3fc6c082 959{
76a66253
JM		 960 /* External access control */
961 /* XXX : not implemented */
962 spr_register(env, SPR_EAR, "EAR",
3fc6c082 963 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
3fc6c082
FB		 966}
967
76a66253
JM		 968/* SPR specific to PowerPC G2 implementation */
969static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 970{
76a66253
JM		 971 /* Memory base address */
972 /* MBAR */
578bb252 973 /* XXX : not implemented */
76a66253
JM		 974 spr_register(env, SPR_MBAR, "MBAR",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* System version register */
979 /* SVR */
578bb252 980 /* XXX : TODO: initialize it to an appropriate value */
76a66253
JM		 981 spr_register(env, SPR_SVR, "SVR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, SPR_NOACCESS,
984 0x00000000);
985 /* Exception processing */
363be49c 986 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
363be49c 990 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994 /* Breakpoints */
995 /* XXX : not implemented */
996 spr_register(env, SPR_DABR, "DABR",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_DABR2, "DABR2",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_IABR, "IABR",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_IABR2, "IABR2",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_IBCR, "IBCR",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_DBCR, "DBCR",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, &spr_write_generic,
1024 0x00000000);
1025}
1026
1027/* SPR specific to PowerPC 602 implementation */
1028static void gen_spr_602 (CPUPPCState *env)
1029{
1030 /* ESA registers */
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_SER, "SER",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, &spr_write_generic,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_SEBR, "SEBR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
a750fc0b 1042 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* Floating point status */
1047 /* XXX : not implemented */
1048 spr_register(env, SPR_SP, "SP",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* XXX : not implemented */
1053 spr_register(env, SPR_LT, "LT",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, &spr_write_generic,
1056 0x00000000);
1057 /* Watchdog timer */
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_TCR, "TCR",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 /* Interrupt base */
1064 spr_register(env, SPR_IBR, "IBR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
a750fc0b
JM		 1068 /* XXX : not implemented */
1069 spr_register(env, SPR_IABR, "IABR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
76a66253
JM		 1073}
1074
1075/* SPR specific to PowerPC 601 implementation */
1076static void gen_spr_601 (CPUPPCState *env)
1077{
1078 /* Multiplication/division register */
1079 /* MQ */
1080 spr_register(env, SPR_MQ, "MQ",
1081 &spr_read_generic, &spr_write_generic,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 /* RTC registers */
1085 spr_register(env, SPR_601_RTCU, "RTCU",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 SPR_NOACCESS, &spr_write_601_rtcu,
1088 0x00000000);
1089 spr_register(env, SPR_601_VRTCU, "RTCU",
1090 &spr_read_601_rtcu, SPR_NOACCESS,
1091 &spr_read_601_rtcu, SPR_NOACCESS,
1092 0x00000000);
1093 spr_register(env, SPR_601_RTCL, "RTCL",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 SPR_NOACCESS, &spr_write_601_rtcl,
1096 0x00000000);
1097 spr_register(env, SPR_601_VRTCL, "RTCL",
1098 &spr_read_601_rtcl, SPR_NOACCESS,
1099 &spr_read_601_rtcl, SPR_NOACCESS,
1100 0x00000000);
1101 /* Timer */
1102#if 0 /* ? */
1103 spr_register(env, SPR_601_UDECR, "UDECR",
1104 &spr_read_decr, SPR_NOACCESS,
1105 &spr_read_decr, SPR_NOACCESS,
1106 0x00000000);
1107#endif
1108 /* External access control */
1109 /* XXX : not implemented */
1110 spr_register(env, SPR_EAR, "EAR",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 /* Memory management */
f2e63a42 1115#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1116 spr_register(env, SPR_IBAT0U, "IBAT0U",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_601_ubat, &spr_write_601_ubatu,
1119 0x00000000);
1120 spr_register(env, SPR_IBAT0L, "IBAT0L",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_601_ubat, &spr_write_601_ubatl,
1123 0x00000000);
1124 spr_register(env, SPR_IBAT1U, "IBAT1U",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_601_ubat, &spr_write_601_ubatu,
1127 0x00000000);
1128 spr_register(env, SPR_IBAT1L, "IBAT1L",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_601_ubat, &spr_write_601_ubatl,
1131 0x00000000);
1132 spr_register(env, SPR_IBAT2U, "IBAT2U",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_601_ubat, &spr_write_601_ubatu,
1135 0x00000000);
1136 spr_register(env, SPR_IBAT2L, "IBAT2L",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_601_ubat, &spr_write_601_ubatl,
1139 0x00000000);
1140 spr_register(env, SPR_IBAT3U, "IBAT3U",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_601_ubat, &spr_write_601_ubatu,
1143 0x00000000);
1144 spr_register(env, SPR_IBAT3L, "IBAT3L",
1145 SPR_NOACCESS, SPR_NOACCESS,
1146 &spr_read_601_ubat, &spr_write_601_ubatl,
1147 0x00000000);
a750fc0b 1148 env->nb_BATs = 4;
f2e63a42 1149#endif
a750fc0b
JM		 1150}
1151
1152static void gen_spr_74xx (CPUPPCState *env)
1153{
1154 /* Processor identification */
1155 spr_register(env, SPR_PIR, "PIR",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_pir,
1158 0x00000000);
1159 /* XXX : not implemented */
1160 spr_register(env, SPR_MMCR2, "MMCR2",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
578bb252 1164 /* XXX : not implemented */
a750fc0b
JM		 1165 spr_register(env, SPR_UMMCR2, "UMMCR2",
1166 &spr_read_ureg, SPR_NOACCESS,
1167 &spr_read_ureg, SPR_NOACCESS,
1168 0x00000000);
1169 /* XXX: not implemented */
1170 spr_register(env, SPR_BAMR, "BAMR",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_generic,
1173 0x00000000);
578bb252 1174 /* XXX : not implemented */
a750fc0b
JM		 1175 spr_register(env, SPR_UBAMR, "UBAMR",
1176 &spr_read_ureg, SPR_NOACCESS,
1177 &spr_read_ureg, SPR_NOACCESS,
1178 0x00000000);
578bb252 1179 /* XXX : not implemented */
a750fc0b
JM		 1180 spr_register(env, SPR_MSSCR0, "MSSCR0",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 /* Hardware implementation registers */
1185 /* XXX : not implemented */
1186 spr_register(env, SPR_HID0, "HID0",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_HID1, "HID1",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* Altivec */
1196 spr_register(env, SPR_VRSAVE, "VRSAVE",
1197 &spr_read_generic, &spr_write_generic,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200}
1201
a750fc0b
JM		 1202static void gen_l3_ctrl (CPUPPCState *env)
1203{
1204 /* L3CR */
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_L3CR, "L3CR",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* L3ITCR0 */
578bb252 1211 /* XXX : not implemented */
a750fc0b
JM		 1212 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* L3ITCR1 */
578bb252 1217 /* XXX : not implemented */
a750fc0b
JM		 1218 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* L3ITCR2 */
578bb252 1223 /* XXX : not implemented */
a750fc0b
JM		 1224 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 /* L3ITCR3 */
578bb252 1229 /* XXX : not implemented */
a750fc0b
JM		 1230 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 /* L3OHCR */
578bb252 1235 /* XXX : not implemented */
a750fc0b
JM		 1236 spr_register(env, SPR_L3OHCR, "L3OHCR",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 /* L3PM */
578bb252 1241 /* XXX : not implemented */
a750fc0b
JM		 1242 spr_register(env, SPR_L3PM, "L3PM",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246}
a750fc0b 1247
578bb252 1248static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1249{
f2e63a42 1250#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1251 env->nb_tlb = nb_tlbs;
1252 env->nb_ways = nb_ways;
1253 env->id_tlbs = 1;
1254 /* XXX : not implemented */
a750fc0b
JM		 1255 spr_register(env, SPR_PTEHI, "PTEHI",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
578bb252 1259 /* XXX : not implemented */
a750fc0b
JM		 1260 spr_register(env, SPR_PTELO, "PTELO",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
578bb252 1264 /* XXX : not implemented */
a750fc0b
JM		 1265 spr_register(env, SPR_TLBMISS, "TLBMISS",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
f2e63a42 1269#endif
76a66253
JM		 1270}
1271
1272/* PowerPC BookE SPR */
1273static void gen_spr_BookE (CPUPPCState *env)
1274{
1275 /* Processor identification */
1276 spr_register(env, SPR_BOOKE_PIR, "PIR",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_pir,
1279 0x00000000);
1280 /* Interrupt processing */
363be49c 1281 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
363be49c
JM		 1285 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
2662a059 1289#if 0
363be49c
JM		 1290 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
2662a059 1298#endif
76a66253
JM		 1299 /* Debug */
1300 /* XXX : not implemented */
1301 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* XXX : not implemented */
1321 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 /* XXX : not implemented */
1331 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* XXX : not implemented */
1341 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1357 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1358 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1359 0x00000000);
1360 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 spr_register(env, SPR_BOOKE_ESR, "ESR",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
363be49c
JM		 1368 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1369 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1370 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1371 0x00000000);
1372 /* Exception vectors */
76a66253
JM		 1373 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1374 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1375 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1376 0x00000000);
1377 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1378 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1379 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1380 0x00000000);
1381 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1382 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1383 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1384 0x00000000);
1385 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1386 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1387 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1388 0x00000000);
1389 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1390 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1391 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1394 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1395 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1396 0x00000000);
1397 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1398 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1399 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1400 0x00000000);
1401 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1402 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1403 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1404 0x00000000);
1405 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1406 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1407 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1408 0x00000000);
1409 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1410 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1411 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1412 0x00000000);
1413 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1414 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1415 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1416 0x00000000);
1417 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1418 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1419 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1420 0x00000000);
1421 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1422 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1423 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1424 0x00000000);
1425 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1426 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1427 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1428 0x00000000);
1429 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1430 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1431 &spr_read_generic, &spr_write_excp_vector,
76a66253
JM		 1432 0x00000000);
1433 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1434 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1435 &spr_read_generic, &spr_write_excp_vector,
76a66253 1436 0x00000000);
2662a059 1437#if 0
363be49c
JM		 1438 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1439 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1440 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1441 0x00000000);
1442 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1443 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1444 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1445 0x00000000);
1446 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1447 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1448 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1449 0x00000000);
1450 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1451 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1452 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1453 0x00000000);
1454 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1455 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1456 &spr_read_generic, &spr_write_excp_vector,
363be49c
JM		 1457 0x00000000);
1458 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1459 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1460 &spr_read_generic, &spr_write_excp_vector,
363be49c 1461 0x00000000);
2662a059 1462#endif
76a66253
JM		 1463 spr_register(env, SPR_BOOKE_PID, "PID",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 spr_register(env, SPR_BOOKE_TCR, "TCR",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_booke_tcr,
1470 0x00000000);
1471 spr_register(env, SPR_BOOKE_TSR, "TSR",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_booke_tsr,
1474 0x00000000);
1475 /* Timer */
1476 spr_register(env, SPR_DECR, "DECR",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_decr, &spr_write_decr,
1479 0x00000000);
1480 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 SPR_NOACCESS, &spr_write_generic,
1483 0x00000000);
1484 /* SPRGs */
1485 spr_register(env, SPR_USPRG0, "USPRG0",
1486 &spr_read_generic, &spr_write_generic,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 spr_register(env, SPR_SPRG4, "SPRG4",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 spr_register(env, SPR_USPRG4, "USPRG4",
1494 &spr_read_ureg, SPR_NOACCESS,
1495 &spr_read_ureg, SPR_NOACCESS,
1496 0x00000000);
1497 spr_register(env, SPR_SPRG5, "SPRG5",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_USPRG5, "USPRG5",
1502 &spr_read_ureg, SPR_NOACCESS,
1503 &spr_read_ureg, SPR_NOACCESS,
1504 0x00000000);
1505 spr_register(env, SPR_SPRG6, "SPRG6",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 spr_register(env, SPR_USPRG6, "USPRG6",
1510 &spr_read_ureg, SPR_NOACCESS,
1511 &spr_read_ureg, SPR_NOACCESS,
1512 0x00000000);
1513 spr_register(env, SPR_SPRG7, "SPRG7",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517 spr_register(env, SPR_USPRG7, "USPRG7",
1518 &spr_read_ureg, SPR_NOACCESS,
1519 &spr_read_ureg, SPR_NOACCESS,
1520 0x00000000);
1521}
1522
363be49c
JM		 1523/* FSL storage control registers */
1524static void gen_spr_BookE_FSL (CPUPPCState *env)
1525{
f2e63a42 1526#if !defined(CONFIG_USER_ONLY)
363be49c 1527 /* TLB assist registers */
578bb252 1528 /* XXX : not implemented */
363be49c
JM		 1529 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
578bb252 1533 /* XXX : not implemented */
363be49c
JM		 1534 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
578bb252 1538 /* XXX : not implemented */
363be49c
JM		 1539 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, &spr_write_generic,
1542 0x00000000);
578bb252 1543 /* XXX : not implemented */
363be49c
JM		 1544 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
578bb252 1548 /* XXX : not implemented */
363be49c
JM		 1549 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
578bb252 1553 /* XXX : not implemented */
363be49c
JM		 1554 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
578bb252 1558 /* XXX : not implemented */
363be49c
JM		 1559 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 if (env->nb_pids > 1) {
578bb252 1564 /* XXX : not implemented */
363be49c
JM		 1565 spr_register(env, SPR_BOOKE_PID1, "PID1",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 }
1570 if (env->nb_pids > 2) {
578bb252 1571 /* XXX : not implemented */
363be49c
JM		 1572 spr_register(env, SPR_BOOKE_PID2, "PID2",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 }
578bb252 1577 /* XXX : not implemented */
65f9ee8d 1578 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, SPR_NOACCESS,
1581 0x00000000); /* TOFIX */
578bb252 1582 /* XXX : not implemented */
65f9ee8d 1583 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
363be49c
JM		 1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000); /* TOFIX */
1587 switch (env->nb_ways) {
1588 case 4:
578bb252 1589 /* XXX : not implemented */
363be49c
JM		 1590 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, SPR_NOACCESS,
1593 0x00000000); /* TOFIX */
1594 /* Fallthru */
1595 case 3:
578bb252 1596 /* XXX : not implemented */
363be49c
JM		 1597 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, SPR_NOACCESS,
1600 0x00000000); /* TOFIX */
1601 /* Fallthru */
1602 case 2:
578bb252 1603 /* XXX : not implemented */
363be49c
JM		 1604 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, SPR_NOACCESS,
1607 0x00000000); /* TOFIX */
1608 /* Fallthru */
1609 case 1:
578bb252 1610 /* XXX : not implemented */
363be49c
JM		 1611 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, SPR_NOACCESS,
1614 0x00000000); /* TOFIX */
1615 /* Fallthru */
1616 case 0:
1617 default:
1618 break;
1619 }
f2e63a42 1620#endif
363be49c
JM		 1621}
1622
76a66253
JM		 1623/* SPR specific to PowerPC 440 implementation */
1624static void gen_spr_440 (CPUPPCState *env)
1625{
1626 /* Cache control */
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_440_DNV0, "DNV0",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632 /* XXX : not implemented */
1633 spr_register(env, SPR_440_DNV1, "DNV1",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637 /* XXX : not implemented */
1638 spr_register(env, SPR_440_DNV2, "DNV2",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 /* XXX : not implemented */
1643 spr_register(env, SPR_440_DNV3, "DNV3",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 /* XXX : not implemented */
2662a059 1648 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 /* XXX : not implemented */
2662a059 1653 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, &spr_write_generic,
1656 0x00000000);
1657 /* XXX : not implemented */
2662a059 1658 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 /* XXX : not implemented */
2662a059 1663 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_440_DVLIM, "DVLIM",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_INV0, "INV0",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_440_INV1, "INV1",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_INV2, "INV2",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_INV3, "INV3",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
2662a059 1693 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
2662a059 1698 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
2662a059 1703 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
2662a059 1708 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_IVLIM, "IVLIM",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* Cache debug */
1718 /* XXX : not implemented */
2662a059 1719 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, SPR_NOACCESS,
1722 0x00000000);
1723 /* XXX : not implemented */
2662a059 1724 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, SPR_NOACCESS,
1727 0x00000000);
1728 /* XXX : not implemented */
2662a059 1729 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, SPR_NOACCESS,
1732 0x00000000);
1733 /* XXX : not implemented */
2662a059 1734 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, SPR_NOACCESS,
1737 0x00000000);
1738 /* XXX : not implemented */
2662a059 1739 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, SPR_NOACCESS,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_DBDR, "DBDR",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* Processor control */
1749 spr_register(env, SPR_4xx_CCR0, "CCR0",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, SPR_NOACCESS,
1756 0x00000000);
1757 /* Storage control */
1758 spr_register(env, SPR_440_MMUCR, "MMUCR",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762}
1763
1764/* SPR shared between PowerPC 40x implementations */
1765static void gen_spr_40x (CPUPPCState *env)
1766{
1767 /* Cache */
035feb88 1768 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1769 spr_register(env, SPR_40x_DCCR, "DCCR",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
035feb88 1773 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1774 spr_register(env, SPR_40x_ICCR, "ICCR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
578bb252 1778 /* not emulated, as Qemu do not emulate caches */
2662a059 1779 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, SPR_NOACCESS,
1782 0x00000000);
76a66253
JM		 1783 /* Exception */
1784 spr_register(env, SPR_40x_DEAR, "DEAR",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 spr_register(env, SPR_40x_ESR, "ESR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 spr_register(env, SPR_40x_EVPR, "EVPR",
1793 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1794 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1795 0x00000000);
1796 spr_register(env, SPR_40x_SRR2, "SRR2",
1797 &spr_read_generic, &spr_write_generic,
1798 &spr_read_generic, &spr_write_generic,
1799 0x00000000);
1800 spr_register(env, SPR_40x_SRR3, "SRR3",
1801 &spr_read_generic, &spr_write_generic,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Timers */
1805 spr_register(env, SPR_40x_PIT, "PIT",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_40x_pit, &spr_write_40x_pit,
1808 0x00000000);
1809 spr_register(env, SPR_40x_TCR, "TCR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_booke_tcr,
1812 0x00000000);
1813 spr_register(env, SPR_40x_TSR, "TSR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_booke_tsr,
1816 0x00000000);
2662a059
JM		 1817}
1818
1819/* SPR specific to PowerPC 405 implementation */
1820static void gen_spr_405 (CPUPPCState *env)
1821{
1822 /* MMU */
1823 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
2662a059 1827 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1830 0x00700000);
1831 /* Debug interface */
76a66253
JM		 1832 /* XXX : not implemented */
1833 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1834 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1835 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1836 0x00000000);
1837 /* XXX : not implemented */
2662a059
JM		 1838 spr_register(env, SPR_405_DBCR1, "DBCR1",
1839 SPR_NOACCESS, SPR_NOACCESS,
1840 &spr_read_generic, &spr_write_generic,
1841 0x00000000);
1842 /* XXX : not implemented */
76a66253
JM		 1843 spr_register(env, SPR_40x_DBSR, "DBSR",
1844 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1845 &spr_read_generic, &spr_write_clear,
1846 /* Last reset was system reset */
76a66253
JM		 1847 0x00000300);
1848 /* XXX : not implemented */
2662a059 1849 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
2662a059 1853 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
2662a059
JM		 1857 /* XXX : not implemented */
1858 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
2662a059 1861 0x00000000);
76a66253 1862 /* XXX : not implemented */
2662a059 1863 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867 /* XXX : not implemented */
2662a059 1868 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
2662a059 1872 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00000000);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_405_IAC3, "IAC3",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 /* XXX : not implemented */
1882 spr_register(env, SPR_405_IAC4, "IAC4",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886 /* Storage control */
035feb88 1887 /* XXX: TODO: not implemented */
76a66253
JM		 1888 spr_register(env, SPR_405_SLER, "SLER",
1889 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1890 &spr_read_generic, &spr_write_40x_sler,
76a66253 1891 0x00000000);
2662a059
JM		 1892 spr_register(env, SPR_40x_ZPR, "ZPR",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
76a66253
JM		 1896 /* XXX : not implemented */
1897 spr_register(env, SPR_405_SU0R, "SU0R",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, &spr_write_generic,
1900 0x00000000);
1901 /* SPRG */
1902 spr_register(env, SPR_USPRG0, "USPRG0",
1903 &spr_read_ureg, SPR_NOACCESS,
1904 &spr_read_ureg, SPR_NOACCESS,
1905 0x00000000);
1906 spr_register(env, SPR_SPRG4, "SPRG4",
1907 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1908 &spr_read_generic, &spr_write_generic,
76a66253
JM		 1909 0x00000000);
1910 spr_register(env, SPR_USPRG4, "USPRG4",
1911 &spr_read_ureg, SPR_NOACCESS,
1912 &spr_read_ureg, SPR_NOACCESS,
1913 0x00000000);
1914 spr_register(env, SPR_SPRG5, "SPRG5",
1915 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1916 spr_read_generic, &spr_write_generic,
76a66253
JM		 1917 0x00000000);
1918 spr_register(env, SPR_USPRG5, "USPRG5",
1919 &spr_read_ureg, SPR_NOACCESS,
1920 &spr_read_ureg, SPR_NOACCESS,
1921 0x00000000);
1922 spr_register(env, SPR_SPRG6, "SPRG6",
1923 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1924 spr_read_generic, &spr_write_generic,
76a66253
JM		 1925 0x00000000);
1926 spr_register(env, SPR_USPRG6, "USPRG6",
1927 &spr_read_ureg, SPR_NOACCESS,
1928 &spr_read_ureg, SPR_NOACCESS,
1929 0x00000000);
1930 spr_register(env, SPR_SPRG7, "SPRG7",
1931 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1932 spr_read_generic, &spr_write_generic,
76a66253
JM		 1933 0x00000000);
1934 spr_register(env, SPR_USPRG7, "USPRG7",
1935 &spr_read_ureg, SPR_NOACCESS,
1936 &spr_read_ureg, SPR_NOACCESS,
1937 0x00000000);
76a66253
JM		 1938}
1939
1940/* SPR shared between PowerPC 401 & 403 implementations */
1941static void gen_spr_401_403 (CPUPPCState *env)
1942{
1943 /* Time base */
1944 spr_register(env, SPR_403_VTBL, "TBL",
1945 &spr_read_tbl, SPR_NOACCESS,
1946 &spr_read_tbl, SPR_NOACCESS,
1947 0x00000000);
1948 spr_register(env, SPR_403_TBL, "TBL",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 SPR_NOACCESS, &spr_write_tbl,
1951 0x00000000);
1952 spr_register(env, SPR_403_VTBU, "TBU",
1953 &spr_read_tbu, SPR_NOACCESS,
1954 &spr_read_tbu, SPR_NOACCESS,
1955 0x00000000);
1956 spr_register(env, SPR_403_TBU, "TBU",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 SPR_NOACCESS, &spr_write_tbu,
1959 0x00000000);
1960 /* Debug */
578bb252 1961 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1962 spr_register(env, SPR_403_CDBCR, "CDBCR",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966}
1967
2662a059
JM		 1968/* SPR specific to PowerPC 401 implementation */
1969static void gen_spr_401 (CPUPPCState *env)
1970{
1971 /* Debug interface */
1972 /* XXX : not implemented */
1973 spr_register(env, SPR_40x_DBCR0, "DBCR",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_40x_dbcr0,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_40x_DBSR, "DBSR",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_clear,
1981 /* Last reset was system reset */
1982 0x00000300);
1983 /* XXX : not implemented */
1984 spr_register(env, SPR_40x_DAC1, "DAC",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0x00000000);
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_40x_IAC1, "IAC",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_generic,
1992 0x00000000);
1993 /* Storage control */
035feb88 1994 /* XXX: TODO: not implemented */
2662a059
JM		 1995 spr_register(env, SPR_405_SLER, "SLER",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_40x_sler,
1998 0x00000000);
035feb88
JM		 1999 /* not emulated, as Qemu never does speculative access */
2000 spr_register(env, SPR_40x_SGR, "SGR",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0xFFFFFFFF);
2004 /* not emulated, as Qemu do not emulate caches */
2005 spr_register(env, SPR_40x_DCWR, "DCWR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2662a059
JM		 2009}
2010
a750fc0b
JM		 2011static void gen_spr_401x2 (CPUPPCState *env)
2012{
2013 gen_spr_401(env);
2014 spr_register(env, SPR_40x_PID, "PID",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_40x_ZPR, "ZPR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022}
2023
76a66253
JM		 2024/* SPR specific to PowerPC 403 implementation */
2025static void gen_spr_403 (CPUPPCState *env)
2026{
2662a059
JM		 2027 /* Debug interface */
2028 /* XXX : not implemented */
2029 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_40x_dbcr0,
2032 0x00000000);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_40x_DBSR, "DBSR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_clear,
2037 /* Last reset was system reset */
2038 0x00000300);
2039 /* XXX : not implemented */
2040 spr_register(env, SPR_40x_DAC1, "DAC1",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
578bb252 2044 /* XXX : not implemented */
2662a059
JM		 2045 spr_register(env, SPR_40x_DAC2, "DAC2",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_40x_IAC1, "IAC1",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0x00000000);
578bb252 2054 /* XXX : not implemented */
2662a059
JM		 2055 spr_register(env, SPR_40x_IAC2, "IAC2",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
a750fc0b
JM		 2059}
2060
2061static void gen_spr_403_real (CPUPPCState *env)
2062{
76a66253
JM		 2063 spr_register(env, SPR_403_PBL1, "PBL1",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_403_pbr, &spr_write_403_pbr,
2066 0x00000000);
2067 spr_register(env, SPR_403_PBU1, "PBU1",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_403_pbr, &spr_write_403_pbr,
2070 0x00000000);
2071 spr_register(env, SPR_403_PBL2, "PBL2",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_403_pbr, &spr_write_403_pbr,
2074 0x00000000);
2075 spr_register(env, SPR_403_PBU2, "PBU2",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_403_pbr, &spr_write_403_pbr,
2078 0x00000000);
a750fc0b
JM		 2079}
2080
2081static void gen_spr_403_mmu (CPUPPCState *env)
2082{
2083 /* MMU */
2084 spr_register(env, SPR_40x_PID, "PID",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2662a059 2088 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092}
2093
2094/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2095static void gen_spr_compress (CPUPPCState *env)
2096{
578bb252 2097 /* XXX : not implemented */
76a66253
JM		 2098 spr_register(env, SPR_401_SKR, "SKR",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102}
a750fc0b
JM		 2103
2104#if defined (TARGET_PPC64)
a750fc0b
JM		 2105/* SPR specific to PowerPC 620 */
2106static void gen_spr_620 (CPUPPCState *env)
2107{
578bb252 2108 /* XXX : not implemented */
a750fc0b
JM		 2109 spr_register(env, SPR_620_PMR0, "PMR0",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_generic,
2112 0x00000000);
578bb252 2113 /* XXX : not implemented */
a750fc0b
JM		 2114 spr_register(env, SPR_620_PMR1, "PMR1",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
578bb252 2118 /* XXX : not implemented */
a750fc0b
JM		 2119 spr_register(env, SPR_620_PMR2, "PMR2",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
578bb252 2123 /* XXX : not implemented */
a750fc0b
JM		 2124 spr_register(env, SPR_620_PMR3, "PMR3",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
578bb252 2128 /* XXX : not implemented */
a750fc0b
JM		 2129 spr_register(env, SPR_620_PMR4, "PMR4",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
578bb252 2133 /* XXX : not implemented */
a750fc0b
JM		 2134 spr_register(env, SPR_620_PMR5, "PMR5",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
578bb252 2138 /* XXX : not implemented */
a750fc0b
JM		 2139 spr_register(env, SPR_620_PMR6, "PMR6",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
578bb252 2143 /* XXX : not implemented */
a750fc0b
JM		 2144 spr_register(env, SPR_620_PMR7, "PMR7",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_generic,
2147 0x00000000);
578bb252 2148 /* XXX : not implemented */
a750fc0b
JM		 2149 spr_register(env, SPR_620_PMR8, "PMR8",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_generic,
2152 0x00000000);
578bb252 2153 /* XXX : not implemented */
a750fc0b
JM		 2154 spr_register(env, SPR_620_PMR9, "PMR9",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
578bb252 2158 /* XXX : not implemented */
a750fc0b
JM		 2159 spr_register(env, SPR_620_PMRA, "PMR10",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
578bb252 2163 /* XXX : not implemented */
a750fc0b
JM		 2164 spr_register(env, SPR_620_PMRB, "PMR11",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
578bb252 2168 /* XXX : not implemented */
a750fc0b
JM		 2169 spr_register(env, SPR_620_PMRC, "PMR12",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
578bb252 2173 /* XXX : not implemented */
a750fc0b
JM		 2174 spr_register(env, SPR_620_PMRD, "PMR13",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
578bb252 2178 /* XXX : not implemented */
a750fc0b
JM		 2179 spr_register(env, SPR_620_PMRE, "PMR14",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
578bb252 2183 /* XXX : not implemented */
a750fc0b
JM		 2184 spr_register(env, SPR_620_PMRF, "PMR15",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
578bb252 2188 /* XXX : not implemented */
a750fc0b
JM		 2189 spr_register(env, SPR_620_HID8, "HID8",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
578bb252 2193 /* XXX : not implemented */
a750fc0b
JM		 2194 spr_register(env, SPR_620_HID9, "HID9",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198}
a750fc0b 2199#endif /* defined (TARGET_PPC64) */
76a66253 2200
2662a059 2201// XXX: TODO
76a66253 2202/*
2662a059
JM		 2203 * AMR => SPR 29 (Power 2.04)
2204 * CTRL => SPR 136 (Power 2.04)
2205 * CTRL => SPR 152 (Power 2.04)
2662a059
JM		 2206 * SCOMC => SPR 276 (64 bits ?)
2207 * SCOMD => SPR 277 (64 bits ?)
2662a059
JM		 2208 * TBU40 => SPR 286 (Power 2.04 hypv)
2209 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2210 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2211 * HDSISR => SPR 306 (Power 2.04 hypv)
2212 * HDAR => SPR 307 (Power 2.04 hypv)
2213 * PURR => SPR 309 (Power 2.04 hypv)
2214 * HDEC => SPR 310 (Power 2.04 hypv)
2215 * HIOR => SPR 311 (hypv)
2216 * RMOR => SPR 312 (970)
2217 * HRMOR => SPR 313 (Power 2.04 hypv)
2218 * HSRR0 => SPR 314 (Power 2.04 hypv)
2219 * HSRR1 => SPR 315 (Power 2.04 hypv)
2220 * LPCR => SPR 316 (970)
2221 * LPIDR => SPR 317 (970)
2222 * SPEFSCR => SPR 512 (Power 2.04 emb)
2662a059
JM		 2223 * EPR => SPR 702 (Power 2.04 emb)
2224 * perf => 768-783 (Power 2.04)
2225 * perf => 784-799 (Power 2.04)
2226 * PPR => SPR 896 (Power 2.04)
2227 * EPLC => SPR 947 (Power 2.04 emb)
2228 * EPSC => SPR 948 (Power 2.04 emb)
2229 * DABRX => 1015 (Power 2.04 hypv)
2230 * FPECR => SPR 1022 (?)
76a66253
JM		 2231 * ... and more (thermal management, performance counters, ...)
2232 */
2233
e1833e1f
JM		 2234/*****************************************************************************/
2235/* Exception vectors models */
2236static void init_excp_4xx_real (CPUPPCState *env)
2237{
2238#if !defined(CONFIG_USER_ONLY)
2239 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2240 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2241 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2242 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2243 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2244 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2245 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2246 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2247 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2248 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2249 env->excp_prefix = 0x00000000;
2250 env->ivor_mask = 0x0000FFF0;
2251 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2252 /* Hardware reset vector */
2253 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2254#endif
2255}
2256
2257static void init_excp_4xx_softmmu (CPUPPCState *env)
2258{
2259#if !defined(CONFIG_USER_ONLY)
2260 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2261 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2262 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2263 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2264 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2265 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2266 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2267 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2268 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2269 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2270 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2271 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2272 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2273 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
6f5d427d
JM		 2274 env->excp_prefix = 0x00000000;
2275 env->ivor_mask = 0x0000FFF0;
2276 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2277 /* Hardware reset vector */
2278 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2279#endif
2280}
2281
2282static void init_excp_BookE (CPUPPCState *env)
2283{
2284#if !defined(CONFIG_USER_ONLY)
2285 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2286 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2288 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2289 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2300 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2301 env->excp_prefix = 0x00000000;
2302 env->ivor_mask = 0x0000FFE0;
2303 env->ivpr_mask = 0xFFFF0000;
1c27f8fb
JM		 2304 /* Hardware reset vector */
2305 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2306#endif
2307}
2308
2309static void init_excp_601 (CPUPPCState *env)
2310{
2311#if !defined(CONFIG_USER_ONLY)
2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2321 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2322 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2323 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2324 env->excp_prefix = 0xFFF00000;
1c27f8fb 2325 /* Hardware reset vector */
4e80effc 2326 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2327#endif
2328}
2329
2330static void init_excp_602 (CPUPPCState *env)
2331{
2332#if !defined(CONFIG_USER_ONLY)
2333 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2334 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2335 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2336 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2337 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2338 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2339 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2340 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2341 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2342 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2343 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2344 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2345 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2346 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2347 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2348 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2349 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2350 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2351 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2352 env->excp_prefix = 0xFFF00000;
1c27f8fb
JM		 2353 /* Hardware reset vector */
2354 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2355#endif
2356}
2357
2358static void init_excp_603 (CPUPPCState *env)
2359{
2360#if !defined(CONFIG_USER_ONLY)
2361 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2362 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2363 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2364 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2365 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2366 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2367 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2368 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2369 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2370 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2371 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2372 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2373 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2374 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2375 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2376 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2377 /* Hardware reset vector */
2378 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2379#endif
2380}
2381
2382static void init_excp_G2 (CPUPPCState *env)
2383{
2384#if !defined(CONFIG_USER_ONLY)
2385 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2386 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2387 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2388 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2389 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2390 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2391 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2392 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2393 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2394 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2395 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2396 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2397 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2398 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2399 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2400 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2401 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2402 /* Hardware reset vector */
2403 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2404#endif
2405}
2406
2407static void init_excp_604 (CPUPPCState *env)
2408{
2409#if !defined(CONFIG_USER_ONLY)
2410 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2411 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2412 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2413 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2414 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2415 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2416 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2417 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2418 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2419 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2420 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2421 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2422 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2423 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2424 /* Hardware reset vector */
2425 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2426#endif
2427}
2428
578bb252 2429#if defined(TARGET_PPC64)
e1833e1f
JM		 2430static void init_excp_620 (CPUPPCState *env)
2431{
2432#if !defined(CONFIG_USER_ONLY)
2433 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2434 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2435 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2436 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2437 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2438 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2439 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2440 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2441 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2442 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2443 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2444 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2445 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2446 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2447 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb
JM		 2448 /* Hardware reset vector */
2449 env->hreset_vector = 0x0000000000000100ULL; /* ? */
e1833e1f
JM		 2450#endif
2451}
578bb252 2452#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2453
2454static void init_excp_7x0 (CPUPPCState *env)
2455{
2456#if !defined(CONFIG_USER_ONLY)
2457 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2458 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2459 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2460 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2461 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2462 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2463 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2464 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2465 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2466 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2467 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2468 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2469 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2470 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2471 /* Hardware reset vector */
2472 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2473#endif
2474}
2475
2476static void init_excp_750FX (CPUPPCState *env)
2477{
2478#if !defined(CONFIG_USER_ONLY)
2479 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2480 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2481 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2482 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2483 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2484 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2485 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2486 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2487 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2488 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2489 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2490 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2491 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2492 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2493 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2494 /* Hardware reset vector */
2495 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2496#endif
2497}
2498
7a3a6927
JM		 2499/* XXX: Check if this is correct */
2500static void init_excp_7x5 (CPUPPCState *env)
2501{
2502#if !defined(CONFIG_USER_ONLY)
2503 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2504 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2505 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2506 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2507 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2508 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2509 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2510 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2511 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2512 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2513 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2514 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2515 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2516 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2517 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2518 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2519 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2520 /* Hardware reset vector */
2521 env->hreset_vector = 0xFFFFFFFCUL;
2522#endif
2523}
2524
e1833e1f
JM		 2525static void init_excp_7400 (CPUPPCState *env)
2526{
2527#if !defined(CONFIG_USER_ONLY)
2528 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2529 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2530 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2531 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2532 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2533 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2534 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2535 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2536 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2537 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2538 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2539 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2540 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2541 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2542 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2543 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2544 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb
JM		 2545 /* Hardware reset vector */
2546 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2547#endif
2548}
2549
e1833e1f
JM		 2550static void init_excp_7450 (CPUPPCState *env)
2551{
2552#if !defined(CONFIG_USER_ONLY)
2553 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2554 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2555 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2556 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2557 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2558 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2559 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2560 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2561 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2562 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2563 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2564 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2565 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2566 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2567 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2568 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2569 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2570 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2571 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb
JM		 2572 /* Hardware reset vector */
2573 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2574#endif
2575}
e1833e1f
JM		 2576
2577#if defined (TARGET_PPC64)
2578static void init_excp_970 (CPUPPCState *env)
2579{
2580#if !defined(CONFIG_USER_ONLY)
2581 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2582 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2583 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2584 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2585 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2586 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2587 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2588 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2589 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2590 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2591 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2592#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2593 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2594#endif
2595 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2596 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2597 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2598 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2599 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2600 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2601 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2602 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 2603 /* Hardware reset vector */
2604 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2605#endif
2606}
2607#endif
2608
2f462816
JM		 2609/*****************************************************************************/
2610/* Power management enable checks */
2611static int check_pow_none (CPUPPCState *env)
2612{
2613 return 0;
2614}
2615
2616static int check_pow_nocheck (CPUPPCState *env)
2617{
2618 return 1;
2619}
2620
2621static int check_pow_hid0 (CPUPPCState *env)
2622{
2623 if (env->spr[SPR_HID0] & 0x00E00000)
2624 return 1;
2625
2626 return 0;
2627}
2628
a750fc0b
JM		 2629/*****************************************************************************/
2630/* PowerPC implementations definitions */
76a66253 2631
a750fc0b 2632/* PowerPC 40x instruction set */
d63001d1 2633#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
76a66253 2634
a750fc0b
JM		 2635/* PowerPC 401 */
2636#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2637 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2638 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2639#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2640#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2641#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2642#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 2643#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
25ba3a68 2644#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 2645#define check_pow_401 check_pow_nocheck
76a66253 2646
a750fc0b
JM		 2647static void init_proc_401 (CPUPPCState *env)
2648{
2649 gen_spr_40x(env);
2650 gen_spr_401_403(env);
2651 gen_spr_401(env);
e1833e1f 2652 init_excp_4xx_real(env);
d63001d1
JM		 2653 env->dcache_line_size = 32;
2654 env->icache_line_size = 32;
4e290a0b
JM		 2655 /* Allocate hardware IRQ controller */
2656 ppc40x_irq_init(env);
a750fc0b 2657}
76a66253 2658
a750fc0b
JM		 2659/* PowerPC 401x2 */
2660#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2661 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2662 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2663 PPC_CACHE_DCBA | PPC_MFTB | \
2664 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2665#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2666#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2667#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2668#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 2669#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
25ba3a68 2670#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 2671#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 2672
2673static void init_proc_401x2 (CPUPPCState *env)
2674{
2675 gen_spr_40x(env);
2676 gen_spr_401_403(env);
2677 gen_spr_401x2(env);
2678 gen_spr_compress(env);
a750fc0b 2679 /* Memory management */
f2e63a42 2680#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2681 env->nb_tlb = 64;
2682 env->nb_ways = 1;
2683 env->id_tlbs = 0;
f2e63a42 2684#endif
e1833e1f 2685 init_excp_4xx_softmmu(env);
d63001d1
JM		 2686 env->dcache_line_size = 32;
2687 env->icache_line_size = 32;
4e290a0b
JM		 2688 /* Allocate hardware IRQ controller */
2689 ppc40x_irq_init(env);
76a66253
JM		 2690}
2691
a750fc0b 2692/* PowerPC 401x3 */
a750fc0b
JM		 2693#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2694 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2695 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2696 PPC_CACHE_DCBA | PPC_MFTB | \
2697 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2698#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2699#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2700#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2701#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 2702#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
25ba3a68 2703#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 2704#define check_pow_401x3 check_pow_nocheck
a750fc0b 2705
578bb252 2706__attribute__ (( unused ))
e1833e1f 2707static void init_proc_401x3 (CPUPPCState *env)
76a66253 2708{
4e290a0b
JM		 2709 gen_spr_40x(env);
2710 gen_spr_401_403(env);
2711 gen_spr_401(env);
2712 gen_spr_401x2(env);
2713 gen_spr_compress(env);
e1833e1f 2714 init_excp_4xx_softmmu(env);
d63001d1
JM		 2715 env->dcache_line_size = 32;
2716 env->icache_line_size = 32;
4e290a0b
JM		 2717 /* Allocate hardware IRQ controller */
2718 ppc40x_irq_init(env);
3fc6c082 2719}
a750fc0b
JM		 2720
2721/* IOP480 */
2722#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2723 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2724 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2725 PPC_CACHE_DCBA | \
2726 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2727#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2728#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2729#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2730#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 2731#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
25ba3a68 2732#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2f462816 2733#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 2734
2735static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 2736{
a750fc0b
JM		 2737 gen_spr_40x(env);
2738 gen_spr_401_403(env);
2739 gen_spr_401x2(env);
2740 gen_spr_compress(env);
a750fc0b 2741 /* Memory management */
f2e63a42 2742#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2743 env->nb_tlb = 64;
2744 env->nb_ways = 1;
2745 env->id_tlbs = 0;
f2e63a42 2746#endif
e1833e1f 2747 init_excp_4xx_softmmu(env);
d63001d1
JM		 2748 env->dcache_line_size = 32;
2749 env->icache_line_size = 32;
4e290a0b
JM		 2750 /* Allocate hardware IRQ controller */
2751 ppc40x_irq_init(env);
3fc6c082
FB		 2752}
2753
a750fc0b
JM		 2754/* PowerPC 403 */
2755#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2756 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
a750fc0b
JM		 2757 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2758#define POWERPC_MSRM_403 (0x000000000007D00DULL)
2759#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2760#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2761#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 2762#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
25ba3a68 2763#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2f462816 2764#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 2765
2766static void init_proc_403 (CPUPPCState *env)
3fc6c082 2767{
a750fc0b
JM		 2768 gen_spr_40x(env);
2769 gen_spr_401_403(env);
2770 gen_spr_403(env);
2771 gen_spr_403_real(env);
e1833e1f 2772 init_excp_4xx_real(env);
d63001d1
JM		 2773 env->dcache_line_size = 32;
2774 env->icache_line_size = 32;
4e290a0b
JM		 2775 /* Allocate hardware IRQ controller */
2776 ppc40x_irq_init(env);
d63001d1
JM		 2777#if !defined(CONFIG_USER_ONLY)
2778 /* Hardware reset vector */
2779 env->hreset_vector = 0xFFFFFFFCUL;
2780#endif
3fc6c082
FB		 2781}
2782
a750fc0b
JM		 2783/* PowerPC 403 GCX */
2784#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2785 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2786 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2787 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2788#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2789#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2790#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2791#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 2792#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
25ba3a68 2793#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2f462816 2794#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 2795
2796static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 2797{
a750fc0b
JM		 2798 gen_spr_40x(env);
2799 gen_spr_401_403(env);
2800 gen_spr_403(env);
2801 gen_spr_403_real(env);
2802 gen_spr_403_mmu(env);
2803 /* Bus access control */
035feb88 2804 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2805 spr_register(env, SPR_40x_SGR, "SGR",
2806 SPR_NOACCESS, SPR_NOACCESS,
2807 &spr_read_generic, &spr_write_generic,
2808 0xFFFFFFFF);
035feb88 2809 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2810 spr_register(env, SPR_40x_DCWR, "DCWR",
2811 SPR_NOACCESS, SPR_NOACCESS,
2812 &spr_read_generic, &spr_write_generic,
2813 0x00000000);
2814 /* Memory management */
f2e63a42 2815#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2816 env->nb_tlb = 64;
2817 env->nb_ways = 1;
2818 env->id_tlbs = 0;
f2e63a42 2819#endif
e1833e1f 2820 init_excp_4xx_softmmu(env);
d63001d1
JM		 2821 env->dcache_line_size = 32;
2822 env->icache_line_size = 32;
4e290a0b
JM		 2823 /* Allocate hardware IRQ controller */
2824 ppc40x_irq_init(env);
3fc6c082
FB		 2825}
2826
a750fc0b
JM		 2827/* PowerPC 405 */
2828#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2829 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2830 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2831 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2832 PPC_405_MAC)
2833#define POWERPC_MSRM_405 (0x000000000006E630ULL)
2834#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2835#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2836#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
237c0af0 2837#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
25ba3a68
JM		 2838#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2839 POWERPC_FLAG_DE)
2f462816 2840#define check_pow_405 check_pow_nocheck
a750fc0b
JM		 2841
2842static void init_proc_405 (CPUPPCState *env)
3fc6c082 2843{
a750fc0b
JM		 2844 /* Time base */
2845 gen_tbl(env);
2846 gen_spr_40x(env);
2847 gen_spr_405(env);
2848 /* Bus access control */
035feb88 2849 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 2850 spr_register(env, SPR_40x_SGR, "SGR",
2851 SPR_NOACCESS, SPR_NOACCESS,
2852 &spr_read_generic, &spr_write_generic,
2853 0xFFFFFFFF);
035feb88 2854 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 2855 spr_register(env, SPR_40x_DCWR, "DCWR",
2856 SPR_NOACCESS, SPR_NOACCESS,
2857 &spr_read_generic, &spr_write_generic,
2858 0x00000000);
2859 /* Memory management */
f2e63a42 2860#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2861 env->nb_tlb = 64;
2862 env->nb_ways = 1;
2863 env->id_tlbs = 0;
f2e63a42 2864#endif
e1833e1f 2865 init_excp_4xx_softmmu(env);
d63001d1
JM		 2866 env->dcache_line_size = 32;
2867 env->icache_line_size = 32;
a750fc0b 2868 /* Allocate hardware IRQ controller */
4e290a0b 2869 ppc40x_irq_init(env);
3fc6c082
FB		 2870}
2871
a750fc0b
JM		 2872/* PowerPC 440 EP */
2873#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2874 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2875 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2876 PPC_440_SPEC | PPC_RFMCI)
2877#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2878#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2879#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2880#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
237c0af0 2881#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
25ba3a68
JM		 2882#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2883 POWERPC_FLAG_DE)
2f462816 2884#define check_pow_440EP check_pow_nocheck
a750fc0b
JM		 2885
2886static void init_proc_440EP (CPUPPCState *env)
3fc6c082 2887{
a750fc0b
JM		 2888 /* Time base */
2889 gen_tbl(env);
2890 gen_spr_BookE(env);
2891 gen_spr_440(env);
578bb252 2892 /* XXX : not implemented */
a750fc0b
JM		 2893 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2894 SPR_NOACCESS, SPR_NOACCESS,
2895 &spr_read_generic, &spr_write_generic,
2896 0x00000000);
2897 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2898 SPR_NOACCESS, SPR_NOACCESS,
2899 &spr_read_generic, &spr_write_generic,
2900 0x00000000);
2901 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2902 SPR_NOACCESS, SPR_NOACCESS,
2903 &spr_read_generic, &spr_write_generic,
2904 0x00000000);
578bb252 2905 /* XXX : not implemented */
a750fc0b
JM		 2906 spr_register(env, SPR_440_CCR1, "CCR1",
2907 SPR_NOACCESS, SPR_NOACCESS,
2908 &spr_read_generic, &spr_write_generic,
2909 0x00000000);
2910 /* Memory management */
f2e63a42 2911#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2912 env->nb_tlb = 64;
2913 env->nb_ways = 1;
2914 env->id_tlbs = 0;
f2e63a42 2915#endif
e1833e1f 2916 init_excp_BookE(env);
d63001d1
JM		 2917 env->dcache_line_size = 32;
2918 env->icache_line_size = 32;
a750fc0b 2919 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2920}
2921
a750fc0b
JM		 2922/* PowerPC 440 GP */
2923#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2924 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2925 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2926 PPC_405_MAC | PPC_440_SPEC)
2927#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2928#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2929#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2930#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
237c0af0 2931#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
25ba3a68
JM		 2932#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2933 POWERPC_FLAG_DE)
2f462816 2934#define check_pow_440GP check_pow_nocheck
a750fc0b
JM		 2935
2936static void init_proc_440GP (CPUPPCState *env)
3fc6c082 2937{
a750fc0b
JM		 2938 /* Time base */
2939 gen_tbl(env);
2940 gen_spr_BookE(env);
2941 gen_spr_440(env);
2942 /* Memory management */
f2e63a42 2943#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2944 env->nb_tlb = 64;
2945 env->nb_ways = 1;
2946 env->id_tlbs = 0;
f2e63a42 2947#endif
e1833e1f 2948 init_excp_BookE(env);
d63001d1
JM		 2949 env->dcache_line_size = 32;
2950 env->icache_line_size = 32;
a750fc0b 2951 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 2952}
2953
a750fc0b 2954/* PowerPC 440x4 */
a750fc0b
JM		 2955#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2956 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2957 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2958 PPC_440_SPEC)
2959#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2960#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2961#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2962#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
237c0af0 2963#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
25ba3a68
JM		 2964#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2965 POWERPC_FLAG_DE)
2f462816 2966#define check_pow_440x4 check_pow_nocheck
a750fc0b 2967
578bb252 2968__attribute__ (( unused ))
a750fc0b 2969static void init_proc_440x4 (CPUPPCState *env)
3fc6c082 2970{
a750fc0b
JM		 2971 /* Time base */
2972 gen_tbl(env);
2973 gen_spr_BookE(env);
2974 gen_spr_440(env);
2975 /* Memory management */
f2e63a42 2976#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2977 env->nb_tlb = 64;
2978 env->nb_ways = 1;
2979 env->id_tlbs = 0;
f2e63a42 2980#endif
e1833e1f 2981 init_excp_BookE(env);
d63001d1
JM		 2982 env->dcache_line_size = 32;
2983 env->icache_line_size = 32;
a750fc0b 2984 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2985}
a750fc0b
JM		 2986
2987/* PowerPC 440x5 */
2988#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2989 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2990 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2991 PPC_440_SPEC | PPC_RFMCI)
2992#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2993#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2994#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2995#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
237c0af0 2996#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
25ba3a68
JM		 2997#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2998 POWERPC_FLAG_DE)
2f462816 2999#define check_pow_440x5 check_pow_nocheck
a750fc0b
JM		 3000
3001static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3002{
a750fc0b
JM		 3003 /* Time base */
3004 gen_tbl(env);
3005 gen_spr_BookE(env);
3006 gen_spr_440(env);
578bb252 3007 /* XXX : not implemented */
a750fc0b
JM		 3008 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3009 SPR_NOACCESS, SPR_NOACCESS,
3010 &spr_read_generic, &spr_write_generic,
3011 0x00000000);
3012 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3013 SPR_NOACCESS, SPR_NOACCESS,
3014 &spr_read_generic, &spr_write_generic,
3015 0x00000000);
3016 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3017 SPR_NOACCESS, SPR_NOACCESS,
3018 &spr_read_generic, &spr_write_generic,
3019 0x00000000);
578bb252 3020 /* XXX : not implemented */
a750fc0b
JM		 3021 spr_register(env, SPR_440_CCR1, "CCR1",
3022 SPR_NOACCESS, SPR_NOACCESS,
3023 &spr_read_generic, &spr_write_generic,
3024 0x00000000);
3025 /* Memory management */
f2e63a42 3026#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3027 env->nb_tlb = 64;
3028 env->nb_ways = 1;
3029 env->id_tlbs = 0;
f2e63a42 3030#endif
e1833e1f 3031 init_excp_BookE(env);
d63001d1
JM		 3032 env->dcache_line_size = 32;
3033 env->icache_line_size = 32;
a750fc0b 3034 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3035}
3036
a750fc0b 3037/* PowerPC 460 (guessed) */
578bb252 3038#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
a750fc0b
JM		 3039 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3040 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3041 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3042#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3043#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3044#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3045#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
237c0af0 3046#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
25ba3a68
JM		 3047#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3048 POWERPC_FLAG_DE)
2f462816 3049#define check_pow_460 check_pow_nocheck
a750fc0b 3050
578bb252 3051__attribute__ (( unused ))
a750fc0b 3052static void init_proc_460 (CPUPPCState *env)
3fc6c082 3053{
e1833e1f
JM		 3054 /* Time base */
3055 gen_tbl(env);
3056 gen_spr_BookE(env);
3057 gen_spr_440(env);
578bb252 3058 /* XXX : not implemented */
e1833e1f
JM		 3059 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3060 SPR_NOACCESS, SPR_NOACCESS,
3061 &spr_read_generic, &spr_write_generic,
3062 0x00000000);
3063 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3064 SPR_NOACCESS, SPR_NOACCESS,
3065 &spr_read_generic, &spr_write_generic,
3066 0x00000000);
3067 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3068 SPR_NOACCESS, SPR_NOACCESS,
3069 &spr_read_generic, &spr_write_generic,
3070 0x00000000);
578bb252 3071 /* XXX : not implemented */
e1833e1f
JM		 3072 spr_register(env, SPR_440_CCR1, "CCR1",
3073 SPR_NOACCESS, SPR_NOACCESS,
3074 &spr_read_generic, &spr_write_generic,
3075 0x00000000);
578bb252 3076 /* XXX : not implemented */
e1833e1f
JM		 3077 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3078 &spr_read_generic, &spr_write_generic,
3079 &spr_read_generic, &spr_write_generic,
3080 0x00000000);
3081 /* Memory management */
f2e63a42 3082#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 3083 env->nb_tlb = 64;
3084 env->nb_ways = 1;
3085 env->id_tlbs = 0;
f2e63a42 3086#endif
e1833e1f 3087 init_excp_BookE(env);
d63001d1
JM		 3088 env->dcache_line_size = 32;
3089 env->icache_line_size = 32;
e1833e1f 3090 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3091}
a750fc0b
JM		 3092
3093/* PowerPC 460F (guessed) */
a750fc0b
JM		 3094#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3095 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3096 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3097 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3098 PPC_FLOAT_STFIWX | \
3099 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3100 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3101#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3102#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3103#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3104#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
237c0af0 3105#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
25ba3a68
JM		 3106#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3107 POWERPC_FLAG_DE)
2f462816 3108#define check_pow_460F check_pow_nocheck
a750fc0b 3109
578bb252 3110__attribute__ (( unused ))
e1833e1f 3111static void init_proc_460F (CPUPPCState *env)
3fc6c082 3112{
a750fc0b
JM		 3113 /* Time base */
3114 gen_tbl(env);
3115 gen_spr_BookE(env);
3116 gen_spr_440(env);
578bb252 3117 /* XXX : not implemented */
a750fc0b
JM		 3118 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3119 SPR_NOACCESS, SPR_NOACCESS,
3120 &spr_read_generic, &spr_write_generic,
3121 0x00000000);
3122 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3123 SPR_NOACCESS, SPR_NOACCESS,
3124 &spr_read_generic, &spr_write_generic,
3125 0x00000000);
3126 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3127 SPR_NOACCESS, SPR_NOACCESS,
3128 &spr_read_generic, &spr_write_generic,
3129 0x00000000);
578bb252 3130 /* XXX : not implemented */
a750fc0b
JM		 3131 spr_register(env, SPR_440_CCR1, "CCR1",
3132 SPR_NOACCESS, SPR_NOACCESS,
3133 &spr_read_generic, &spr_write_generic,
3134 0x00000000);
578bb252 3135 /* XXX : not implemented */
a750fc0b
JM		 3136 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3137 &spr_read_generic, &spr_write_generic,
3138 &spr_read_generic, &spr_write_generic,
3139 0x00000000);
3140 /* Memory management */
f2e63a42 3141#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3142 env->nb_tlb = 64;
3143 env->nb_ways = 1;
3144 env->id_tlbs = 0;
f2e63a42 3145#endif
e1833e1f 3146 init_excp_BookE(env);
d63001d1
JM		 3147 env->dcache_line_size = 32;
3148 env->icache_line_size = 32;
a750fc0b 3149 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3150}
a750fc0b
JM		 3151
3152/* Generic BookE PowerPC */
a750fc0b
JM		 3153#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3154 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3155 PPC_CACHE_DCBA | \
3156 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3157 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3158 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
3159 PPC_BOOKE)
3160#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3161#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3162#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3163#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
237c0af0 3164#define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
d26bfc9a 3165#define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
2f462816 3166#define check_pow_BookE check_pow_nocheck
a750fc0b 3167
578bb252 3168__attribute__ (( unused ))
a750fc0b 3169static void init_proc_BookE (CPUPPCState *env)
3fc6c082 3170{
e1833e1f 3171 init_excp_BookE(env);
d63001d1
JM		 3172 env->dcache_line_size = 32;
3173 env->icache_line_size = 32;
3fc6c082 3174}
a750fc0b
JM		 3175
3176/* e200 core */
a750fc0b
JM		 3177
3178/* e300 core */
a750fc0b
JM		 3179
3180/* e500 core */
a750fc0b
JM		 3181#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3182 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3183 PPC_CACHE_DCBA | \
3184 PPC_BOOKE | PPC_E500_VECTOR)
3185#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3186#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3187#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
237c0af0 3188#define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
d26bfc9a 3189#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
2f462816 3190#define check_pow_e500 check_pow_hid0
a750fc0b 3191
578bb252 3192__attribute__ (( unused ))
a750fc0b 3193static void init_proc_e500 (CPUPPCState *env)
3fc6c082 3194{
a750fc0b
JM		 3195 /* Time base */
3196 gen_tbl(env);
3197 gen_spr_BookE(env);
3198 /* Memory management */
3199 gen_spr_BookE_FSL(env);
f2e63a42 3200#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3201 env->nb_tlb = 64;
3202 env->nb_ways = 1;
3203 env->id_tlbs = 0;
f2e63a42 3204#endif
e1833e1f 3205 init_excp_BookE(env);
d63001d1
JM		 3206 env->dcache_line_size = 32;
3207 env->icache_line_size = 32;
a750fc0b 3208 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 3209}
a750fc0b
JM		 3210
3211/* e600 core */
a750fc0b
JM		 3212
3213/* Non-embedded PowerPC */
3214/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3215#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
12de9a39 3216 PPC_MEM_EIEIO | PPC_MEM_TLBIE)
a750fc0b
JM		 3217/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3218#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3219 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3220 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
12de9a39
JM		 3221 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3222 PPC_SEGMENT)
a750fc0b
JM		 3223
3224/* POWER : same as 601, without mfmsr, mfsr */
3225#if defined(TODO)
3226#define POWERPC_INSNS_POWER (XXX_TODO)
3227/* POWER RSC (from RAD6000) */
3228#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3229#endif /* TODO */
3230
3231/* PowerPC 601 */
d63001d1 3232#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
12de9a39 3233 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
25ba3a68 3234#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
a13d7523 3235#define POWERPC_MMU_601 (POWERPC_MMU_32B)
a750fc0b
JM		 3236//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3237#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 3238#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
25ba3a68 3239#define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
2f462816 3240#define check_pow_601 check_pow_none
a750fc0b
JM		 3241
3242static void init_proc_601 (CPUPPCState *env)
3fc6c082 3243{
a750fc0b
JM		 3244 gen_spr_ne_601(env);
3245 gen_spr_601(env);
3246 /* Hardware implementation registers */
3247 /* XXX : not implemented */
3248 spr_register(env, SPR_HID0, "HID0",
3249 SPR_NOACCESS, SPR_NOACCESS,
3250 &spr_read_generic, &spr_write_generic,
3251 0x00000000);
3252 /* XXX : not implemented */
3253 spr_register(env, SPR_HID1, "HID1",
3254 SPR_NOACCESS, SPR_NOACCESS,
3255 &spr_read_generic, &spr_write_generic,
3256 0x00000000);
3257 /* XXX : not implemented */
3258 spr_register(env, SPR_601_HID2, "HID2",
3259 SPR_NOACCESS, SPR_NOACCESS,
3260 &spr_read_generic, &spr_write_generic,
3261 0x00000000);
3262 /* XXX : not implemented */
3263 spr_register(env, SPR_601_HID5, "HID5",
3264 SPR_NOACCESS, SPR_NOACCESS,
3265 &spr_read_generic, &spr_write_generic,
3266 0x00000000);
3267 /* XXX : not implemented */
3268 spr_register(env, SPR_601_HID15, "HID15",
3269 SPR_NOACCESS, SPR_NOACCESS,
3270 &spr_read_generic, &spr_write_generic,
3271 0x00000000);
3272 /* Memory management */
f2e63a42 3273#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3274 env->nb_tlb = 64;
3275 env->nb_ways = 2;
3276 env->id_tlbs = 0;
f2e63a42 3277#endif
e1833e1f 3278 init_excp_601(env);
d63001d1
JM		 3279 env->dcache_line_size = 64;
3280 env->icache_line_size = 64;
a750fc0b 3281 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3282}
3283
a750fc0b
JM		 3284/* PowerPC 602 */
3285#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3286 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3287 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
d63001d1 3288 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
12de9a39 3289 PPC_SEGMENT | PPC_602_SPEC)
a750fc0b
JM		 3290#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3291#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3292//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3293#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 3294#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68
JM		 3295#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3296 POWERPC_FLAG_BE)
2f462816 3297#define check_pow_602 check_pow_hid0
a750fc0b
JM		 3298
3299static void init_proc_602 (CPUPPCState *env)
3fc6c082 3300{
a750fc0b
JM		 3301 gen_spr_ne_601(env);
3302 gen_spr_602(env);
3303 /* Time base */
3304 gen_tbl(env);
3305 /* hardware implementation registers */
3306 /* XXX : not implemented */
3307 spr_register(env, SPR_HID0, "HID0",
3308 SPR_NOACCESS, SPR_NOACCESS,
3309 &spr_read_generic, &spr_write_generic,
3310 0x00000000);
3311 /* XXX : not implemented */
3312 spr_register(env, SPR_HID1, "HID1",
3313 SPR_NOACCESS, SPR_NOACCESS,
3314 &spr_read_generic, &spr_write_generic,
3315 0x00000000);
3316 /* Memory management */
3317 gen_low_BATs(env);
3318 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3319 init_excp_602(env);
d63001d1
JM		 3320 env->dcache_line_size = 32;
3321 env->icache_line_size = 32;
a750fc0b
JM		 3322 /* Allocate hardware IRQ controller */
3323 ppc6xx_irq_init(env);
3324}
3fc6c082 3325
a750fc0b
JM		 3326/* PowerPC 603 */
3327#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
25ba3a68 3328#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 3329#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3330//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3331#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 3332#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68
JM		 3333#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3334 POWERPC_FLAG_BE)
2f462816 3335#define check_pow_603 check_pow_hid0
a750fc0b
JM		 3336
3337static void init_proc_603 (CPUPPCState *env)
3338{
3339 gen_spr_ne_601(env);
3340 gen_spr_603(env);
3341 /* Time base */
3342 gen_tbl(env);
3343 /* hardware implementation registers */
3344 /* XXX : not implemented */
3345 spr_register(env, SPR_HID0, "HID0",
3346 SPR_NOACCESS, SPR_NOACCESS,
3347 &spr_read_generic, &spr_write_generic,
3348 0x00000000);
3349 /* XXX : not implemented */
3350 spr_register(env, SPR_HID1, "HID1",
3351 SPR_NOACCESS, SPR_NOACCESS,
3352 &spr_read_generic, &spr_write_generic,
3353 0x00000000);
3354 /* Memory management */
3355 gen_low_BATs(env);
3356 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3357 init_excp_603(env);
d63001d1
JM		 3358 env->dcache_line_size = 32;
3359 env->icache_line_size = 32;
a750fc0b
JM		 3360 /* Allocate hardware IRQ controller */
3361 ppc6xx_irq_init(env);
3fc6c082
FB		 3362}
3363
a750fc0b
JM		 3364/* PowerPC 603e */
3365#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3366#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3367#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3368//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3369#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 3370#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68
JM		 3371#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3372 POWERPC_FLAG_BE)
2f462816 3373#define check_pow_603E check_pow_hid0
a750fc0b
JM		 3374
3375static void init_proc_603E (CPUPPCState *env)
3376{
3377 gen_spr_ne_601(env);
3378 gen_spr_603(env);
3379 /* Time base */
3380 gen_tbl(env);
3381 /* hardware implementation registers */
3382 /* XXX : not implemented */
3383 spr_register(env, SPR_HID0, "HID0",
3384 SPR_NOACCESS, SPR_NOACCESS,
3385 &spr_read_generic, &spr_write_generic,
3386 0x00000000);
3387 /* XXX : not implemented */
3388 spr_register(env, SPR_HID1, "HID1",
3389 SPR_NOACCESS, SPR_NOACCESS,
3390 &spr_read_generic, &spr_write_generic,
3391 0x00000000);
3392 /* XXX : not implemented */
3393 spr_register(env, SPR_IABR, "IABR",
3394 SPR_NOACCESS, SPR_NOACCESS,
3395 &spr_read_generic, &spr_write_generic,
3396 0x00000000);
3397 /* Memory management */
3398 gen_low_BATs(env);
3399 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3400 init_excp_603(env);
d63001d1
JM		 3401 env->dcache_line_size = 32;
3402 env->icache_line_size = 32;
a750fc0b
JM		 3403 /* Allocate hardware IRQ controller */
3404 ppc6xx_irq_init(env);
3405}
3406
3407/* PowerPC G2 */
3408#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3409#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3410#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3411//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3412#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
237c0af0 3413#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
25ba3a68
JM		 3414#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3415 POWERPC_FLAG_BE)
2f462816 3416#define check_pow_G2 check_pow_hid0
a750fc0b
JM		 3417
3418static void init_proc_G2 (CPUPPCState *env)
3419{
3420 gen_spr_ne_601(env);
3421 gen_spr_G2_755(env);
3422 gen_spr_G2(env);
3423 /* Time base */
3424 gen_tbl(env);
3425 /* Hardware implementation register */
3426 /* XXX : not implemented */
3427 spr_register(env, SPR_HID0, "HID0",
3428 SPR_NOACCESS, SPR_NOACCESS,
3429 &spr_read_generic, &spr_write_generic,
3430 0x00000000);
3431 /* XXX : not implemented */
3432 spr_register(env, SPR_HID1, "HID1",
3433 SPR_NOACCESS, SPR_NOACCESS,
3434 &spr_read_generic, &spr_write_generic,
3435 0x00000000);
3436 /* XXX : not implemented */
3437 spr_register(env, SPR_HID2, "HID2",
3438 SPR_NOACCESS, SPR_NOACCESS,
3439 &spr_read_generic, &spr_write_generic,
3440 0x00000000);
3441 /* Memory management */
3442 gen_low_BATs(env);
3443 gen_high_BATs(env);
3444 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3445 init_excp_G2(env);
d63001d1
JM		 3446 env->dcache_line_size = 32;
3447 env->icache_line_size = 32;
a750fc0b
JM		 3448 /* Allocate hardware IRQ controller */
3449 ppc6xx_irq_init(env);
3450}
3451
3452/* PowerPC G2LE */
3453#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3454#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3455#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3456#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3457#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
237c0af0 3458#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
25ba3a68
JM		 3459#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3460 POWERPC_FLAG_BE)
2f462816 3461#define check_pow_G2LE check_pow_hid0
a750fc0b
JM		 3462
3463static void init_proc_G2LE (CPUPPCState *env)
3464{
3465 gen_spr_ne_601(env);
3466 gen_spr_G2_755(env);
3467 gen_spr_G2(env);
3468 /* Time base */
3469 gen_tbl(env);
3470 /* Hardware implementation register */
3471 /* XXX : not implemented */
3472 spr_register(env, SPR_HID0, "HID0",
3473 SPR_NOACCESS, SPR_NOACCESS,
3474 &spr_read_generic, &spr_write_generic,
3475 0x00000000);
3476 /* XXX : not implemented */
3477 spr_register(env, SPR_HID1, "HID1",
3478 SPR_NOACCESS, SPR_NOACCESS,
3479 &spr_read_generic, &spr_write_generic,
3480 0x00000000);
3481 /* XXX : not implemented */
3482 spr_register(env, SPR_HID2, "HID2",
3483 SPR_NOACCESS, SPR_NOACCESS,
3484 &spr_read_generic, &spr_write_generic,
3485 0x00000000);
3486 /* Memory management */
3487 gen_low_BATs(env);
3488 gen_high_BATs(env);
3489 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3490 init_excp_G2(env);
d63001d1
JM		 3491 env->dcache_line_size = 32;
3492 env->icache_line_size = 32;
a750fc0b
JM		 3493 /* Allocate hardware IRQ controller */
3494 ppc6xx_irq_init(env);
3495}
3496
3497/* PowerPC 604 */
3498#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3499#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3500#define POWERPC_MMU_604 (POWERPC_MMU_32B)
3501//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3502#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 3503#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68
JM		 3504#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3505 POWERPC_FLAG_PMM)
2f462816 3506#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 3507
3508static void init_proc_604 (CPUPPCState *env)
3509{
3510 gen_spr_ne_601(env);
3511 gen_spr_604(env);
3512 /* Time base */
3513 gen_tbl(env);
3514 /* Hardware implementation registers */
3515 /* XXX : not implemented */
3516 spr_register(env, SPR_HID0, "HID0",
3517 SPR_NOACCESS, SPR_NOACCESS,
3518 &spr_read_generic, &spr_write_generic,
3519 0x00000000);
3520 /* XXX : not implemented */
3521 spr_register(env, SPR_HID1, "HID1",
3522 SPR_NOACCESS, SPR_NOACCESS,
3523 &spr_read_generic, &spr_write_generic,
3524 0x00000000);
3525 /* Memory management */
3526 gen_low_BATs(env);
e1833e1f 3527 init_excp_604(env);
d63001d1
JM		 3528 env->dcache_line_size = 32;
3529 env->icache_line_size = 32;
a750fc0b
JM		 3530 /* Allocate hardware IRQ controller */
3531 ppc6xx_irq_init(env);
3532}
3533
3534/* PowerPC 740/750 (aka G3) */
3535#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
25ba3a68 3536#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
a750fc0b
JM		 3537#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3538//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3539#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
237c0af0 3540#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
25ba3a68
JM		 3541#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3542 POWERPC_FLAG_PMM)
2f462816 3543#define check_pow_7x0 check_pow_hid0
a750fc0b
JM		 3544
3545static void init_proc_7x0 (CPUPPCState *env)
3546{
3547 gen_spr_ne_601(env);
3548 gen_spr_7xx(env);
3549 /* Time base */
3550 gen_tbl(env);
3551 /* Thermal management */
3552 gen_spr_thrm(env);
3553 /* Hardware implementation registers */
3554 /* XXX : not implemented */
3555 spr_register(env, SPR_HID0, "HID0",
3556 SPR_NOACCESS, SPR_NOACCESS,
3557 &spr_read_generic, &spr_write_generic,
3558 0x00000000);
3559 /* XXX : not implemented */
3560 spr_register(env, SPR_HID1, "HID1",
3561 SPR_NOACCESS, SPR_NOACCESS,
3562 &spr_read_generic, &spr_write_generic,
3563 0x00000000);
3564 /* Memory management */
3565 gen_low_BATs(env);
e1833e1f 3566 init_excp_7x0(env);
d63001d1
JM		 3567 env->dcache_line_size = 32;
3568 env->icache_line_size = 32;
a750fc0b
JM		 3569 /* Allocate hardware IRQ controller */
3570 ppc6xx_irq_init(env);
3571}
3572
3573/* PowerPC 750FX/GX */
3574#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
25ba3a68 3575#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 3576#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3577#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3578#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 3579#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68
JM		 3580#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3581 POWERPC_FLAG_PMM)
2f462816 3582#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 3583
3584static void init_proc_750fx (CPUPPCState *env)
3585{
3586 gen_spr_ne_601(env);
3587 gen_spr_7xx(env);
3588 /* Time base */
3589 gen_tbl(env);
3590 /* Thermal management */
3591 gen_spr_thrm(env);
3592 /* Hardware implementation registers */
3593 /* XXX : not implemented */
3594 spr_register(env, SPR_HID0, "HID0",
3595 SPR_NOACCESS, SPR_NOACCESS,
3596 &spr_read_generic, &spr_write_generic,
3597 0x00000000);
3598 /* XXX : not implemented */
3599 spr_register(env, SPR_HID1, "HID1",
3600 SPR_NOACCESS, SPR_NOACCESS,
3601 &spr_read_generic, &spr_write_generic,
3602 0x00000000);
3603 /* XXX : not implemented */
3604 spr_register(env, SPR_750_HID2, "HID2",
3605 SPR_NOACCESS, SPR_NOACCESS,
3606 &spr_read_generic, &spr_write_generic,
3607 0x00000000);
3608 /* Memory management */
3609 gen_low_BATs(env);
3610 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3611 gen_high_BATs(env);
e1833e1f 3612 init_excp_750FX(env);
d63001d1
JM		 3613 env->dcache_line_size = 32;
3614 env->icache_line_size = 32;
a750fc0b
JM		 3615 /* Allocate hardware IRQ controller */
3616 ppc6xx_irq_init(env);
3617}
3618
3619/* PowerPC 745/755 */
3620#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
25ba3a68 3621#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
a750fc0b
JM		 3622#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3623//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3624#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
237c0af0 3625#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
25ba3a68
JM		 3626#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3627 POWERPC_FLAG_PMM)
2f462816 3628#define check_pow_7x5 check_pow_hid0
a750fc0b
JM		 3629
3630static void init_proc_7x5 (CPUPPCState *env)
3631{
3632 gen_spr_ne_601(env);
3633 gen_spr_G2_755(env);
3634 /* Time base */
3635 gen_tbl(env);
3636 /* L2 cache control */
3637 /* XXX : not implemented */
3638 spr_register(env, SPR_ICTC, "ICTC",
3639 SPR_NOACCESS, SPR_NOACCESS,
3640 &spr_read_generic, &spr_write_generic,
3641 0x00000000);
3642 /* XXX : not implemented */
3643 spr_register(env, SPR_L2PMCR, "L2PMCR",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 /* Hardware implementation registers */
3648 /* XXX : not implemented */
3649 spr_register(env, SPR_HID0, "HID0",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653 /* XXX : not implemented */
3654 spr_register(env, SPR_HID1, "HID1",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 /* XXX : not implemented */
3659 spr_register(env, SPR_HID2, "HID2",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* Memory management */
3664 gen_low_BATs(env);
3665 gen_high_BATs(env);
3666 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 3667 init_excp_7x5(env);
d63001d1
JM		 3668 env->dcache_line_size = 32;
3669 env->icache_line_size = 32;
a750fc0b
JM		 3670 /* Allocate hardware IRQ controller */
3671 ppc6xx_irq_init(env);
d63001d1
JM		 3672#if !defined(CONFIG_USER_ONLY)
3673 /* Hardware reset vector */
3674 env->hreset_vector = 0xFFFFFFFCUL;
3675#endif
a750fc0b
JM		 3676}
3677
3678/* PowerPC 7400 (aka G4) */
3679#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3680 PPC_EXTERN | PPC_MEM_TLBIA | \
3681 PPC_ALTIVEC)
3682#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3683#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3684#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3685#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 3686#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68
JM		 3687#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3688 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 3689#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 3690
3691static void init_proc_7400 (CPUPPCState *env)
3692{
3693 gen_spr_ne_601(env);
3694 gen_spr_7xx(env);
3695 /* Time base */
3696 gen_tbl(env);
3697 /* 74xx specific SPR */
3698 gen_spr_74xx(env);
3699 /* Thermal management */
3700 gen_spr_thrm(env);
3701 /* Memory management */
3702 gen_low_BATs(env);
e1833e1f 3703 init_excp_7400(env);
d63001d1
JM		 3704 env->dcache_line_size = 32;
3705 env->icache_line_size = 32;
a750fc0b
JM		 3706 /* Allocate hardware IRQ controller */
3707 ppc6xx_irq_init(env);
3708}
3709
3710/* PowerPC 7410 (aka G4) */
3711#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3712 PPC_EXTERN | PPC_MEM_TLBIA | \
3713 PPC_ALTIVEC)
3714#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3715#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3716#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3717#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 3718#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68
JM		 3719#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3720 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 3721#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 3722
3723static void init_proc_7410 (CPUPPCState *env)
3724{
3725 gen_spr_ne_601(env);
3726 gen_spr_7xx(env);
3727 /* Time base */
3728 gen_tbl(env);
3729 /* 74xx specific SPR */
3730 gen_spr_74xx(env);
3731 /* Thermal management */
3732 gen_spr_thrm(env);
3733 /* L2PMCR */
3734 /* XXX : not implemented */
3735 spr_register(env, SPR_L2PMCR, "L2PMCR",
3736 SPR_NOACCESS, SPR_NOACCESS,
3737 &spr_read_generic, &spr_write_generic,
3738 0x00000000);
3739 /* LDSTDB */
3740 /* XXX : not implemented */
3741 spr_register(env, SPR_LDSTDB, "LDSTDB",
3742 SPR_NOACCESS, SPR_NOACCESS,
3743 &spr_read_generic, &spr_write_generic,
3744 0x00000000);
3745 /* Memory management */
3746 gen_low_BATs(env);
e1833e1f 3747 init_excp_7400(env);
d63001d1
JM		 3748 env->dcache_line_size = 32;
3749 env->icache_line_size = 32;
a750fc0b
JM		 3750 /* Allocate hardware IRQ controller */
3751 ppc6xx_irq_init(env);
3752}
3753
3754/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 3755#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3756 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3757 PPC_ALTIVEC)
3758#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3759#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3760#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3761#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 3762#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68
JM		 3763#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3764 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 3765#define check_pow_7440 check_pow_hid0
a750fc0b 3766
578bb252 3767__attribute__ (( unused ))
a750fc0b
JM		 3768static void init_proc_7440 (CPUPPCState *env)
3769{
3770 gen_spr_ne_601(env);
3771 gen_spr_7xx(env);
3772 /* Time base */
3773 gen_tbl(env);
3774 /* 74xx specific SPR */
3775 gen_spr_74xx(env);
3776 /* LDSTCR */
3777 /* XXX : not implemented */
3778 spr_register(env, SPR_LDSTCR, "LDSTCR",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 /* ICTRL */
3783 /* XXX : not implemented */
3784 spr_register(env, SPR_ICTRL, "ICTRL",
3785 SPR_NOACCESS, SPR_NOACCESS,
3786 &spr_read_generic, &spr_write_generic,
3787 0x00000000);
3788 /* MSSSR0 */
578bb252 3789 /* XXX : not implemented */
a750fc0b
JM		 3790 spr_register(env, SPR_MSSSR0, "MSSSR0",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_generic,
3793 0x00000000);
3794 /* PMC */
3795 /* XXX : not implemented */
3796 spr_register(env, SPR_PMC5, "PMC5",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
578bb252 3800 /* XXX : not implemented */
a750fc0b
JM		 3801 spr_register(env, SPR_UPMC5, "UPMC5",
3802 &spr_read_ureg, SPR_NOACCESS,
3803 &spr_read_ureg, SPR_NOACCESS,
3804 0x00000000);
578bb252 3805 /* XXX : not implemented */
a750fc0b
JM		 3806 spr_register(env, SPR_PMC6, "PMC6",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
578bb252 3810 /* XXX : not implemented */
a750fc0b
JM		 3811 spr_register(env, SPR_UPMC6, "UPMC6",
3812 &spr_read_ureg, SPR_NOACCESS,
3813 &spr_read_ureg, SPR_NOACCESS,
3814 0x00000000);
3815 /* Memory management */
3816 gen_low_BATs(env);
578bb252 3817 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 3818 init_excp_7450(env);
d63001d1
JM		 3819 env->dcache_line_size = 32;
3820 env->icache_line_size = 32;
a750fc0b
JM		 3821 /* Allocate hardware IRQ controller */
3822 ppc6xx_irq_init(env);
3823}
a750fc0b
JM		 3824
3825/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 3826#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3827 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3828 PPC_ALTIVEC)
3829#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3830#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3831#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3832#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 3833#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68
JM		 3834#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3835 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 3836#define check_pow_7450 check_pow_hid0
a750fc0b 3837
578bb252 3838__attribute__ (( unused ))
a750fc0b
JM		 3839static void init_proc_7450 (CPUPPCState *env)
3840{
3841 gen_spr_ne_601(env);
3842 gen_spr_7xx(env);
3843 /* Time base */
3844 gen_tbl(env);
3845 /* 74xx specific SPR */
3846 gen_spr_74xx(env);
3847 /* Level 3 cache control */
3848 gen_l3_ctrl(env);
3849 /* LDSTCR */
3850 /* XXX : not implemented */
3851 spr_register(env, SPR_LDSTCR, "LDSTCR",
3852 SPR_NOACCESS, SPR_NOACCESS,
3853 &spr_read_generic, &spr_write_generic,
3854 0x00000000);
3855 /* ICTRL */
3856 /* XXX : not implemented */
3857 spr_register(env, SPR_ICTRL, "ICTRL",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_generic,
3860 0x00000000);
3861 /* MSSSR0 */
578bb252 3862 /* XXX : not implemented */
a750fc0b
JM		 3863 spr_register(env, SPR_MSSSR0, "MSSSR0",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_generic,
3866 0x00000000);
3867 /* PMC */
3868 /* XXX : not implemented */
3869 spr_register(env, SPR_PMC5, "PMC5",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, &spr_write_generic,
3872 0x00000000);
578bb252 3873 /* XXX : not implemented */
a750fc0b
JM		 3874 spr_register(env, SPR_UPMC5, "UPMC5",
3875 &spr_read_ureg, SPR_NOACCESS,
3876 &spr_read_ureg, SPR_NOACCESS,
3877 0x00000000);
578bb252 3878 /* XXX : not implemented */
a750fc0b
JM		 3879 spr_register(env, SPR_PMC6, "PMC6",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
578bb252 3883 /* XXX : not implemented */
a750fc0b
JM		 3884 spr_register(env, SPR_UPMC6, "UPMC6",
3885 &spr_read_ureg, SPR_NOACCESS,
3886 &spr_read_ureg, SPR_NOACCESS,
3887 0x00000000);
3888 /* Memory management */
3889 gen_low_BATs(env);
578bb252 3890 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3891 init_excp_7450(env);
d63001d1
JM		 3892 env->dcache_line_size = 32;
3893 env->icache_line_size = 32;
a750fc0b
JM		 3894 /* Allocate hardware IRQ controller */
3895 ppc6xx_irq_init(env);
3896}
a750fc0b
JM		 3897
3898/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 3899#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3900 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3901 PPC_ALTIVEC)
3902#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3903#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3904#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3905#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 3906#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68
JM		 3907#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3908 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 3909#define check_pow_7445 check_pow_hid0
a750fc0b 3910
578bb252 3911__attribute__ (( unused ))
a750fc0b
JM		 3912static void init_proc_7445 (CPUPPCState *env)
3913{
3914 gen_spr_ne_601(env);
3915 gen_spr_7xx(env);
3916 /* Time base */
3917 gen_tbl(env);
3918 /* 74xx specific SPR */
3919 gen_spr_74xx(env);
3920 /* LDSTCR */
3921 /* XXX : not implemented */
3922 spr_register(env, SPR_LDSTCR, "LDSTCR",
3923 SPR_NOACCESS, SPR_NOACCESS,
3924 &spr_read_generic, &spr_write_generic,
3925 0x00000000);
3926 /* ICTRL */
3927 /* XXX : not implemented */
3928 spr_register(env, SPR_ICTRL, "ICTRL",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 /* MSSSR0 */
578bb252 3933 /* XXX : not implemented */
a750fc0b
JM		 3934 spr_register(env, SPR_MSSSR0, "MSSSR0",
3935 SPR_NOACCESS, SPR_NOACCESS,
3936 &spr_read_generic, &spr_write_generic,
3937 0x00000000);
3938 /* PMC */
3939 /* XXX : not implemented */
3940 spr_register(env, SPR_PMC5, "PMC5",
3941 SPR_NOACCESS, SPR_NOACCESS,
3942 &spr_read_generic, &spr_write_generic,
3943 0x00000000);
578bb252 3944 /* XXX : not implemented */
a750fc0b
JM		 3945 spr_register(env, SPR_UPMC5, "UPMC5",
3946 &spr_read_ureg, SPR_NOACCESS,
3947 &spr_read_ureg, SPR_NOACCESS,
3948 0x00000000);
578bb252 3949 /* XXX : not implemented */
a750fc0b
JM		 3950 spr_register(env, SPR_PMC6, "PMC6",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
578bb252 3954 /* XXX : not implemented */
a750fc0b
JM		 3955 spr_register(env, SPR_UPMC6, "UPMC6",
3956 &spr_read_ureg, SPR_NOACCESS,
3957 &spr_read_ureg, SPR_NOACCESS,
3958 0x00000000);
3959 /* SPRGs */
3960 spr_register(env, SPR_SPRG4, "SPRG4",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 spr_register(env, SPR_USPRG4, "USPRG4",
3965 &spr_read_ureg, SPR_NOACCESS,
3966 &spr_read_ureg, SPR_NOACCESS,
3967 0x00000000);
3968 spr_register(env, SPR_SPRG5, "SPRG5",
3969 SPR_NOACCESS, SPR_NOACCESS,
3970 &spr_read_generic, &spr_write_generic,
3971 0x00000000);
3972 spr_register(env, SPR_USPRG5, "USPRG5",
3973 &spr_read_ureg, SPR_NOACCESS,
3974 &spr_read_ureg, SPR_NOACCESS,
3975 0x00000000);
3976 spr_register(env, SPR_SPRG6, "SPRG6",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 spr_register(env, SPR_USPRG6, "USPRG6",
3981 &spr_read_ureg, SPR_NOACCESS,
3982 &spr_read_ureg, SPR_NOACCESS,
3983 0x00000000);
3984 spr_register(env, SPR_SPRG7, "SPRG7",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 spr_register(env, SPR_USPRG7, "USPRG7",
3989 &spr_read_ureg, SPR_NOACCESS,
3990 &spr_read_ureg, SPR_NOACCESS,
3991 0x00000000);
3992 /* Memory management */
3993 gen_low_BATs(env);
3994 gen_high_BATs(env);
578bb252 3995 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 3996 init_excp_7450(env);
d63001d1
JM		 3997 env->dcache_line_size = 32;
3998 env->icache_line_size = 32;
a750fc0b
JM		 3999 /* Allocate hardware IRQ controller */
4000 ppc6xx_irq_init(env);
4001}
a750fc0b
JM		 4002
4003/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 4004#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4005 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4006 PPC_ALTIVEC)
4007#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4008#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4009#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4010#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 4011#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68
JM		 4012#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4013 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
2f462816 4014#define check_pow_7455 check_pow_hid0
a750fc0b 4015
578bb252 4016__attribute__ (( unused ))
a750fc0b
JM		 4017static void init_proc_7455 (CPUPPCState *env)
4018{
4019 gen_spr_ne_601(env);
4020 gen_spr_7xx(env);
4021 /* Time base */
4022 gen_tbl(env);
4023 /* 74xx specific SPR */
4024 gen_spr_74xx(env);
4025 /* Level 3 cache control */
4026 gen_l3_ctrl(env);
4027 /* LDSTCR */
4028 /* XXX : not implemented */
4029 spr_register(env, SPR_LDSTCR, "LDSTCR",
4030 SPR_NOACCESS, SPR_NOACCESS,
4031 &spr_read_generic, &spr_write_generic,
4032 0x00000000);
4033 /* ICTRL */
4034 /* XXX : not implemented */
4035 spr_register(env, SPR_ICTRL, "ICTRL",
4036 SPR_NOACCESS, SPR_NOACCESS,
4037 &spr_read_generic, &spr_write_generic,
4038 0x00000000);
4039 /* MSSSR0 */
578bb252 4040 /* XXX : not implemented */
a750fc0b
JM		 4041 spr_register(env, SPR_MSSSR0, "MSSSR0",
4042 SPR_NOACCESS, SPR_NOACCESS,
4043 &spr_read_generic, &spr_write_generic,
4044 0x00000000);
4045 /* PMC */
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_PMC5, "PMC5",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
578bb252 4051 /* XXX : not implemented */
a750fc0b
JM		 4052 spr_register(env, SPR_UPMC5, "UPMC5",
4053 &spr_read_ureg, SPR_NOACCESS,
4054 &spr_read_ureg, SPR_NOACCESS,
4055 0x00000000);
578bb252 4056 /* XXX : not implemented */
a750fc0b
JM		 4057 spr_register(env, SPR_PMC6, "PMC6",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
578bb252 4061 /* XXX : not implemented */
a750fc0b
JM		 4062 spr_register(env, SPR_UPMC6, "UPMC6",
4063 &spr_read_ureg, SPR_NOACCESS,
4064 &spr_read_ureg, SPR_NOACCESS,
4065 0x00000000);
4066 /* SPRGs */
4067 spr_register(env, SPR_SPRG4, "SPRG4",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071 spr_register(env, SPR_USPRG4, "USPRG4",
4072 &spr_read_ureg, SPR_NOACCESS,
4073 &spr_read_ureg, SPR_NOACCESS,
4074 0x00000000);
4075 spr_register(env, SPR_SPRG5, "SPRG5",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 spr_register(env, SPR_USPRG5, "USPRG5",
4080 &spr_read_ureg, SPR_NOACCESS,
4081 &spr_read_ureg, SPR_NOACCESS,
4082 0x00000000);
4083 spr_register(env, SPR_SPRG6, "SPRG6",
4084 SPR_NOACCESS, SPR_NOACCESS,
4085 &spr_read_generic, &spr_write_generic,
4086 0x00000000);
4087 spr_register(env, SPR_USPRG6, "USPRG6",
4088 &spr_read_ureg, SPR_NOACCESS,
4089 &spr_read_ureg, SPR_NOACCESS,
4090 0x00000000);
4091 spr_register(env, SPR_SPRG7, "SPRG7",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 spr_register(env, SPR_USPRG7, "USPRG7",
4096 &spr_read_ureg, SPR_NOACCESS,
4097 &spr_read_ureg, SPR_NOACCESS,
4098 0x00000000);
4099 /* Memory management */
4100 gen_low_BATs(env);
4101 gen_high_BATs(env);
578bb252 4102 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 4103 init_excp_7450(env);
d63001d1
JM		 4104 env->dcache_line_size = 32;
4105 env->icache_line_size = 32;
a750fc0b
JM		 4106 /* Allocate hardware IRQ controller */
4107 ppc6xx_irq_init(env);
4108}
a750fc0b
JM		 4109
4110#if defined (TARGET_PPC64)
d63001d1 4111#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
12de9a39
JM		 4112 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4113 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4114 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
a750fc0b 4115/* PowerPC 970 */
d63001d1 4116#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4117 PPC_64B | PPC_ALTIVEC | \
12de9a39 4118 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4119#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 4120#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 4121//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4122#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 4123#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68
JM		 4124#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4125 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 4126
417bf010
JM		 4127#if defined(CONFIG_USER_ONLY)
4128#define POWERPC970_HID5_INIT 0x00000080
4129#else
4130#define POWERPC970_HID5_INIT 0x00000000
4131#endif
4132
2f462816
JM		 4133static int check_pow_970 (CPUPPCState *env)
4134{
4135 if (env->spr[SPR_HID0] & 0x00600000)
4136 return 1;
4137
4138 return 0;
4139}
4140
a750fc0b
JM		 4141static void init_proc_970 (CPUPPCState *env)
4142{
4143 gen_spr_ne_601(env);
4144 gen_spr_7xx(env);
4145 /* Time base */
4146 gen_tbl(env);
4147 /* Hardware implementation registers */
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_HID0, "HID0",
4150 SPR_NOACCESS, SPR_NOACCESS,
06403421 4151 &spr_read_generic, &spr_write_clear,
d63001d1 4152 0x60000000);
a750fc0b
JM		 4153 /* XXX : not implemented */
4154 spr_register(env, SPR_HID1, "HID1",
4155 SPR_NOACCESS, SPR_NOACCESS,
4156 &spr_read_generic, &spr_write_generic,
4157 0x00000000);
4158 /* XXX : not implemented */
4159 spr_register(env, SPR_750_HID2, "HID2",
4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
e57448f1
JM		 4163 /* XXX : not implemented */
4164 spr_register(env, SPR_970_HID5, "HID5",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
417bf010 4167 POWERPC970_HID5_INIT);
a750fc0b
JM		 4168 /* Memory management */
4169 /* XXX: not correct */
4170 gen_low_BATs(env);
12de9a39
JM		 4171 /* XXX : not implemented */
4172 spr_register(env, SPR_MMUCFG, "MMUCFG",
4173 SPR_NOACCESS, SPR_NOACCESS,
4174 &spr_read_generic, SPR_NOACCESS,
4175 0x00000000); /* TOFIX */
4176 /* XXX : not implemented */
4177 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4178 SPR_NOACCESS, SPR_NOACCESS,
4179 &spr_read_generic, &spr_write_generic,
4180 0x00000000); /* TOFIX */
4181 spr_register(env, SPR_HIOR, "SPR_HIOR",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_generic,
4184 0xFFF00000); /* XXX: This is a hack */
4185#if !defined(CONFIG_USER_ONLY)
4186 env->excp_prefix = 0xFFF00000;
a750fc0b 4187#endif
f2e63a42 4188#if !defined(CONFIG_USER_ONLY)
12de9a39 4189 env->slb_nr = 32;
f2e63a42 4190#endif
e1833e1f 4191 init_excp_970(env);
d63001d1
JM		 4192 env->dcache_line_size = 128;
4193 env->icache_line_size = 128;
a750fc0b
JM		 4194 /* Allocate hardware IRQ controller */
4195 ppc970_irq_init(env);
4196}
a750fc0b
JM		 4197
4198/* PowerPC 970FX (aka G5) */
d63001d1 4199#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4200 PPC_64B | PPC_ALTIVEC | \
12de9a39 4201 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4202#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 4203#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 4204#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4205#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 4206#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68
JM		 4207#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4208 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 4209
2f462816
JM		 4210static int check_pow_970FX (CPUPPCState *env)
4211{
4212 if (env->spr[SPR_HID0] & 0x00600000)
4213 return 1;
4214
4215 return 0;
4216}
4217
a750fc0b
JM		 4218static void init_proc_970FX (CPUPPCState *env)
4219{
4220 gen_spr_ne_601(env);
4221 gen_spr_7xx(env);
4222 /* Time base */
4223 gen_tbl(env);
4224 /* Hardware implementation registers */
4225 /* XXX : not implemented */
4226 spr_register(env, SPR_HID0, "HID0",
4227 SPR_NOACCESS, SPR_NOACCESS,
06403421 4228 &spr_read_generic, &spr_write_clear,
d63001d1 4229 0x60000000);
a750fc0b
JM		 4230 /* XXX : not implemented */
4231 spr_register(env, SPR_HID1, "HID1",
4232 SPR_NOACCESS, SPR_NOACCESS,
4233 &spr_read_generic, &spr_write_generic,
4234 0x00000000);
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_750_HID2, "HID2",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_generic,
4239 0x00000000);
d63001d1
JM		 4240 /* XXX : not implemented */
4241 spr_register(env, SPR_970_HID5, "HID5",
4242 SPR_NOACCESS, SPR_NOACCESS,
4243 &spr_read_generic, &spr_write_generic,
417bf010 4244 POWERPC970_HID5_INIT);
a750fc0b
JM		 4245 /* Memory management */
4246 /* XXX: not correct */
4247 gen_low_BATs(env);
12de9a39
JM		 4248 /* XXX : not implemented */
4249 spr_register(env, SPR_MMUCFG, "MMUCFG",
4250 SPR_NOACCESS, SPR_NOACCESS,
4251 &spr_read_generic, SPR_NOACCESS,
4252 0x00000000); /* TOFIX */
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000); /* TOFIX */
4258 spr_register(env, SPR_HIOR, "SPR_HIOR",
4259 SPR_NOACCESS, SPR_NOACCESS,
4260 &spr_read_generic, &spr_write_generic,
4261 0xFFF00000); /* XXX: This is a hack */
4262#if !defined(CONFIG_USER_ONLY)
4263 env->excp_prefix = 0xFFF00000;
a750fc0b 4264#endif
f2e63a42 4265#if !defined(CONFIG_USER_ONLY)
12de9a39 4266 env->slb_nr = 32;
f2e63a42 4267#endif
e1833e1f 4268 init_excp_970(env);
d63001d1
JM		 4269 env->dcache_line_size = 128;
4270 env->icache_line_size = 128;
a750fc0b
JM		 4271 /* Allocate hardware IRQ controller */
4272 ppc970_irq_init(env);
4273}
a750fc0b
JM		 4274
4275/* PowerPC 970 GX */
d63001d1 4276#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
a750fc0b 4277 PPC_64B | PPC_ALTIVEC | \
12de9a39 4278 PPC_SEGMENT_64B | PPC_SLBI)
a750fc0b 4279#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 4280#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 4281#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4282#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 4283#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68
JM		 4284#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4285 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
a750fc0b 4286
2f462816
JM		 4287static int check_pow_970GX (CPUPPCState *env)
4288{
4289 if (env->spr[SPR_HID0] & 0x00600000)
4290 return 1;
4291
4292 return 0;
4293}
4294
a750fc0b
JM		 4295static void init_proc_970GX (CPUPPCState *env)
4296{
4297 gen_spr_ne_601(env);
4298 gen_spr_7xx(env);
4299 /* Time base */
4300 gen_tbl(env);
4301 /* Hardware implementation registers */
4302 /* XXX : not implemented */
4303 spr_register(env, SPR_HID0, "HID0",
4304 SPR_NOACCESS, SPR_NOACCESS,
06403421 4305 &spr_read_generic, &spr_write_clear,
d63001d1 4306 0x60000000);
a750fc0b
JM		 4307 /* XXX : not implemented */
4308 spr_register(env, SPR_HID1, "HID1",
4309 SPR_NOACCESS, SPR_NOACCESS,
4310 &spr_read_generic, &spr_write_generic,
4311 0x00000000);
4312 /* XXX : not implemented */
4313 spr_register(env, SPR_750_HID2, "HID2",
4314 SPR_NOACCESS, SPR_NOACCESS,
4315 &spr_read_generic, &spr_write_generic,
4316 0x00000000);
d63001d1
JM		 4317 /* XXX : not implemented */
4318 spr_register(env, SPR_970_HID5, "HID5",
4319 SPR_NOACCESS, SPR_NOACCESS,
4320 &spr_read_generic, &spr_write_generic,
417bf010 4321 POWERPC970_HID5_INIT);
a750fc0b
JM		 4322 /* Memory management */
4323 /* XXX: not correct */
4324 gen_low_BATs(env);
12de9a39
JM		 4325 /* XXX : not implemented */
4326 spr_register(env, SPR_MMUCFG, "MMUCFG",
4327 SPR_NOACCESS, SPR_NOACCESS,
4328 &spr_read_generic, SPR_NOACCESS,
4329 0x00000000); /* TOFIX */
4330 /* XXX : not implemented */
4331 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4332 SPR_NOACCESS, SPR_NOACCESS,
4333 &spr_read_generic, &spr_write_generic,
4334 0x00000000); /* TOFIX */
4335 spr_register(env, SPR_HIOR, "SPR_HIOR",
4336 SPR_NOACCESS, SPR_NOACCESS,
4337 &spr_read_generic, &spr_write_generic,
4338 0xFFF00000); /* XXX: This is a hack */
4339#if !defined(CONFIG_USER_ONLY)
4340 env->excp_prefix = 0xFFF00000;
a750fc0b 4341#endif
f2e63a42 4342#if !defined(CONFIG_USER_ONLY)
12de9a39 4343 env->slb_nr = 32;
f2e63a42 4344#endif
e1833e1f 4345 init_excp_970(env);
d63001d1
JM		 4346 env->dcache_line_size = 128;
4347 env->icache_line_size = 128;
a750fc0b
JM		 4348 /* Allocate hardware IRQ controller */
4349 ppc970_irq_init(env);
4350}
a750fc0b 4351
2f462816
JM		 4352/* PowerPC 970 MP */
4353#define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4354 PPC_64B | PPC_ALTIVEC | \
4355 PPC_SEGMENT_64B | PPC_SLBI)
4356#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
4357#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
4358#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
4359#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
4360#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
4361#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4362 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4363
4364static int check_pow_970MP (CPUPPCState *env)
4365{
4366 if (env->spr[SPR_HID0] & 0x01C00000)
4367 return 1;
4368
4369 return 0;
4370}
4371
4372static void init_proc_970MP (CPUPPCState *env)
4373{
4374 gen_spr_ne_601(env);
4375 gen_spr_7xx(env);
4376 /* Time base */
4377 gen_tbl(env);
4378 /* Hardware implementation registers */
4379 /* XXX : not implemented */
4380 spr_register(env, SPR_HID0, "HID0",
4381 SPR_NOACCESS, SPR_NOACCESS,
4382 &spr_read_generic, &spr_write_clear,
4383 0x60000000);
4384 /* XXX : not implemented */
4385 spr_register(env, SPR_HID1, "HID1",
4386 SPR_NOACCESS, SPR_NOACCESS,
4387 &spr_read_generic, &spr_write_generic,
4388 0x00000000);
4389 /* XXX : not implemented */
4390 spr_register(env, SPR_750_HID2, "HID2",
4391 SPR_NOACCESS, SPR_NOACCESS,
4392 &spr_read_generic, &spr_write_generic,
4393 0x00000000);
4394 /* XXX : not implemented */
4395 spr_register(env, SPR_970_HID5, "HID5",
4396 SPR_NOACCESS, SPR_NOACCESS,
4397 &spr_read_generic, &spr_write_generic,
4398 POWERPC970_HID5_INIT);
4399 /* Memory management */
4400 /* XXX: not correct */
4401 gen_low_BATs(env);
4402 /* XXX : not implemented */
4403 spr_register(env, SPR_MMUCFG, "MMUCFG",
4404 SPR_NOACCESS, SPR_NOACCESS,
4405 &spr_read_generic, SPR_NOACCESS,
4406 0x00000000); /* TOFIX */
4407 /* XXX : not implemented */
4408 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4409 SPR_NOACCESS, SPR_NOACCESS,
4410 &spr_read_generic, &spr_write_generic,
4411 0x00000000); /* TOFIX */
4412 spr_register(env, SPR_HIOR, "SPR_HIOR",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0xFFF00000); /* XXX: This is a hack */
4416#if !defined(CONFIG_USER_ONLY)
4417 env->excp_prefix = 0xFFF00000;
4418#endif
4419#if !defined(CONFIG_USER_ONLY)
4420 env->slb_nr = 32;
4421#endif
4422 init_excp_970(env);
4423 env->dcache_line_size = 128;
4424 env->icache_line_size = 128;
4425 /* Allocate hardware IRQ controller */
4426 ppc970_irq_init(env);
4427}
4428
a750fc0b 4429/* PowerPC 620 */
a750fc0b
JM		 4430#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4431 PPC_64B | PPC_SLBI)
4432#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4433#define POWERPC_MMU_620 (POWERPC_MMU_64B)
4434#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4435#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
237c0af0 4436#define POWERPC_BFDM_620 (bfd_mach_ppc64)
25ba3a68 4437#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
2f462816 4438#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 4439
578bb252 4440__attribute__ (( unused ))
a750fc0b
JM		 4441static void init_proc_620 (CPUPPCState *env)
4442{
4443 gen_spr_ne_601(env);
4444 gen_spr_620(env);
4445 /* Time base */
4446 gen_tbl(env);
4447 /* Hardware implementation registers */
4448 /* XXX : not implemented */
4449 spr_register(env, SPR_HID0, "HID0",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* Memory management */
4454 gen_low_BATs(env);
4455 gen_high_BATs(env);
e1833e1f 4456 init_excp_620(env);
d63001d1
JM		 4457 env->dcache_line_size = 64;
4458 env->icache_line_size = 64;
a750fc0b
JM		 4459 /* XXX: TODO: initialize internal interrupt controller */
4460}
a750fc0b
JM		 4461#endif /* defined (TARGET_PPC64) */
4462
4463/* Default 32 bits PowerPC target will be 604 */
4464#define CPU_POWERPC_PPC32 CPU_POWERPC_604
4465#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4466#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4467#define POWERPC_MMU_PPC32 POWERPC_MMU_604
4468#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4469#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 4470#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 4471#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 4472#define check_pow_PPC32 check_pow_604
4473#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 4474
4475/* Default 64 bits PowerPC target will be 970 FX */
4476#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4477#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4478#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4479#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4480#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4481#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 4482#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 4483#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 4484#define check_pow_PPC64 check_pow_970FX
4485#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 4486
4487/* Default PowerPC target will be PowerPC 32 */
4488#if defined (TARGET_PPC64) && 0 // XXX: TODO
d12f4c38
JM		 4489#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4490#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4491#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4492#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4493#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4494#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
237c0af0 4495#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
d26bfc9a 4496#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
2f462816
JM		 4497#define check_pow_DEFAULT check_pow_PPC64
4498#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 4499#else
d12f4c38
JM		 4500#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4501#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4502#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4503#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4504#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4505#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
237c0af0 4506#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
d26bfc9a 4507#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
2f462816
JM		 4508#define check_pow_DEFAULT check_pow_PPC32
4509#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 4510#endif
4511
4512/*****************************************************************************/
4513/* PVR definitions for most known PowerPC */
4514enum {
4515 /* PowerPC 401 family */
4516 /* Generic PowerPC 401 */
4517#define CPU_POWERPC_401 CPU_POWERPC_401G2
4518 /* PowerPC 401 cores */
4519 CPU_POWERPC_401A1 = 0x00210000,
4520 CPU_POWERPC_401B2 = 0x00220000,
4521#if 0
4522 CPU_POWERPC_401B3 = xxx,
4523#endif
4524 CPU_POWERPC_401C2 = 0x00230000,
4525 CPU_POWERPC_401D2 = 0x00240000,
4526 CPU_POWERPC_401E2 = 0x00250000,
4527 CPU_POWERPC_401F2 = 0x00260000,
4528 CPU_POWERPC_401G2 = 0x00270000,
4529 /* PowerPC 401 microcontrolers */
4530#if 0
4531 CPU_POWERPC_401GF = xxx,
4532#endif
4533#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4534 /* IBM Processor for Network Resources */
4535 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4536#if 0
4537 CPU_POWERPC_XIPCHIP = xxx,
4538#endif
4539 /* PowerPC 403 family */
4540 /* Generic PowerPC 403 */
4541#define CPU_POWERPC_403 CPU_POWERPC_403GC
4542 /* PowerPC 403 microcontrollers */
4543 CPU_POWERPC_403GA = 0x00200011,
4544 CPU_POWERPC_403GB = 0x00200100,
4545 CPU_POWERPC_403GC = 0x00200200,
4546 CPU_POWERPC_403GCX = 0x00201400,
4547#if 0
4548 CPU_POWERPC_403GP = xxx,
4549#endif
4550 /* PowerPC 405 family */
4551 /* Generic PowerPC 405 */
4552#define CPU_POWERPC_405 CPU_POWERPC_405D4
4553 /* PowerPC 405 cores */
4554#if 0
4555 CPU_POWERPC_405A3 = xxx,
4556#endif
4557#if 0
4558 CPU_POWERPC_405A4 = xxx,
4559#endif
4560#if 0
4561 CPU_POWERPC_405B3 = xxx,
4562#endif
4563#if 0
4564 CPU_POWERPC_405B4 = xxx,
4565#endif
4566#if 0
4567 CPU_POWERPC_405C3 = xxx,
4568#endif
4569#if 0
4570 CPU_POWERPC_405C4 = xxx,
4571#endif
4572 CPU_POWERPC_405D2 = 0x20010000,
4573#if 0
4574 CPU_POWERPC_405D3 = xxx,
4575#endif
4576 CPU_POWERPC_405D4 = 0x41810000,
4577#if 0
4578 CPU_POWERPC_405D5 = xxx,
4579#endif
4580#if 0
4581 CPU_POWERPC_405E4 = xxx,
4582#endif
4583#if 0
4584 CPU_POWERPC_405F4 = xxx,
4585#endif
4586#if 0
4587 CPU_POWERPC_405F5 = xxx,
4588#endif
4589#if 0
4590 CPU_POWERPC_405F6 = xxx,
4591#endif
4592 /* PowerPC 405 microcontrolers */
4593 /* XXX: missing 0x200108a0 */
4594#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4595 CPU_POWERPC_405CRa = 0x40110041,
4596 CPU_POWERPC_405CRb = 0x401100C5,
4597 CPU_POWERPC_405CRc = 0x40110145,
4598 CPU_POWERPC_405EP = 0x51210950,
4599#if 0
4600 CPU_POWERPC_405EXr = xxx,
4601#endif
4602 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4603#if 0
4604 CPU_POWERPC_405FX = xxx,
4605#endif
4606#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4607 CPU_POWERPC_405GPa = 0x40110000,
4608 CPU_POWERPC_405GPb = 0x40110040,
4609 CPU_POWERPC_405GPc = 0x40110082,
4610 CPU_POWERPC_405GPd = 0x401100C4,
4611#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4612 CPU_POWERPC_405GPR = 0x50910951,
4613#if 0
4614 CPU_POWERPC_405H = xxx,
4615#endif
4616#if 0
4617 CPU_POWERPC_405L = xxx,
4618#endif
4619 CPU_POWERPC_405LP = 0x41F10000,
4620#if 0
4621 CPU_POWERPC_405PM = xxx,
4622#endif
4623#if 0
4624 CPU_POWERPC_405PS = xxx,
4625#endif
4626#if 0
4627 CPU_POWERPC_405S = xxx,
4628#endif
4629 /* IBM network processors */
4630 CPU_POWERPC_NPE405H = 0x414100C0,
4631 CPU_POWERPC_NPE405H2 = 0x41410140,
4632 CPU_POWERPC_NPE405L = 0x416100C0,
4633 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4634#if 0
4635 CPU_POWERPC_NPCxx1 = xxx,
4636#endif
4637#if 0
4638 CPU_POWERPC_NPR161 = xxx,
4639#endif
4640#if 0
4641 CPU_POWERPC_LC77700 = xxx,
4642#endif
4643 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4644#if 0
4645 CPU_POWERPC_STB01000 = xxx,
4646#endif
4647#if 0
4648 CPU_POWERPC_STB01010 = xxx,
4649#endif
4650#if 0
4651 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4652#endif
4653 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4654#if 0
4655 CPU_POWERPC_STB043 = xxx,
4656#endif
4657#if 0
4658 CPU_POWERPC_STB045 = xxx,
4659#endif
4660 CPU_POWERPC_STB04 = 0x41810000,
4661 CPU_POWERPC_STB25 = 0x51510950,
4662#if 0
4663 CPU_POWERPC_STB130 = xxx,
4664#endif
4665 /* Xilinx cores */
4666 CPU_POWERPC_X2VP4 = 0x20010820,
4667#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4668 CPU_POWERPC_X2VP20 = 0x20010860,
4669#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4670#if 0
4671 CPU_POWERPC_ZL10310 = xxx,
4672#endif
4673#if 0
4674 CPU_POWERPC_ZL10311 = xxx,
4675#endif
4676#if 0
4677 CPU_POWERPC_ZL10320 = xxx,
4678#endif
4679#if 0
4680 CPU_POWERPC_ZL10321 = xxx,
4681#endif
4682 /* PowerPC 440 family */
4683 /* Generic PowerPC 440 */
4684#define CPU_POWERPC_440 CPU_POWERPC_440GXf
4685 /* PowerPC 440 cores */
4686#if 0
4687 CPU_POWERPC_440A4 = xxx,
4688#endif
4689#if 0
4690 CPU_POWERPC_440A5 = xxx,
4691#endif
4692#if 0
4693 CPU_POWERPC_440B4 = xxx,
4694#endif
4695#if 0
4696 CPU_POWERPC_440F5 = xxx,
4697#endif
4698#if 0
4699 CPU_POWERPC_440G5 = xxx,
4700#endif
4701#if 0
4702 CPU_POWERPC_440H4 = xxx,
4703#endif
4704#if 0
4705 CPU_POWERPC_440H6 = xxx,
4706#endif
4707 /* PowerPC 440 microcontrolers */
4708#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4709 CPU_POWERPC_440EPa = 0x42221850,
4710 CPU_POWERPC_440EPb = 0x422218D3,
4711#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4712 CPU_POWERPC_440GPb = 0x40120440,
4713 CPU_POWERPC_440GPc = 0x40120481,
4714#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4715#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4716 CPU_POWERPC_440GRX = 0x200008D0,
4717#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4718#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4719 CPU_POWERPC_440GXa = 0x51B21850,
4720 CPU_POWERPC_440GXb = 0x51B21851,
4721 CPU_POWERPC_440GXc = 0x51B21892,
4722 CPU_POWERPC_440GXf = 0x51B21894,
4723#if 0
4724 CPU_POWERPC_440S = xxx,
4725#endif
4726 CPU_POWERPC_440SP = 0x53221850,
4727 CPU_POWERPC_440SP2 = 0x53221891,
4728 CPU_POWERPC_440SPE = 0x53421890,
4729 /* PowerPC 460 family */
4730#if 0
4731 /* Generic PowerPC 464 */
4732#define CPU_POWERPC_464 CPU_POWERPC_464H90
4733#endif
4734 /* PowerPC 464 microcontrolers */
4735#if 0
4736 CPU_POWERPC_464H90 = xxx,
4737#endif
4738#if 0
4739 CPU_POWERPC_464H90FP = xxx,
4740#endif
4741 /* Freescale embedded PowerPC cores */
4742 /* e200 family */
4743#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4744#if 0
4745 CPU_POWERPC_e200z0 = xxx,
4746#endif
4747#if 0
4748 CPU_POWERPC_e200z3 = xxx,
4749#endif
4750 CPU_POWERPC_e200z5 = 0x81000000,
4751 CPU_POWERPC_e200z6 = 0x81120000,
4752 /* e300 family */
4753#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4754 CPU_POWERPC_e300c1 = 0x00830000,
4755 CPU_POWERPC_e300c2 = 0x00840000,
4756 CPU_POWERPC_e300c3 = 0x00850000,
4757 /* e500 family */
4758#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4759 CPU_POWERPC_e500_v11 = 0x80200010,
4760 CPU_POWERPC_e500_v12 = 0x80200020,
4761 CPU_POWERPC_e500_v21 = 0x80210010,
4762 CPU_POWERPC_e500_v22 = 0x80210020,
4763#if 0
4764 CPU_POWERPC_e500mc = xxx,
4765#endif
4766 /* e600 family */
4767 CPU_POWERPC_e600 = 0x80040010,
4768 /* PowerPC MPC 5xx cores */
4769 CPU_POWERPC_5xx = 0x00020020,
4770 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4771 CPU_POWERPC_8xx = 0x00500000,
4772 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4773 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4774 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4775 CPU_POWERPC_827x = 0x80822013,
4776 /* PowerPC 6xx cores */
4777 CPU_POWERPC_601 = 0x00010001,
4778 CPU_POWERPC_601a = 0x00010002,
4779 CPU_POWERPC_602 = 0x00050100,
4780 CPU_POWERPC_603 = 0x00030100,
4781#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4782 CPU_POWERPC_603E_v11 = 0x00060101,
4783 CPU_POWERPC_603E_v12 = 0x00060102,
4784 CPU_POWERPC_603E_v13 = 0x00060103,
4785 CPU_POWERPC_603E_v14 = 0x00060104,
4786 CPU_POWERPC_603E_v22 = 0x00060202,
4787 CPU_POWERPC_603E_v3 = 0x00060300,
4788 CPU_POWERPC_603E_v4 = 0x00060400,
4789 CPU_POWERPC_603E_v41 = 0x00060401,
4790 CPU_POWERPC_603E7t = 0x00071201,
4791 CPU_POWERPC_603E7v = 0x00070100,
4792 CPU_POWERPC_603E7v1 = 0x00070101,
4793 CPU_POWERPC_603E7v2 = 0x00070201,
4794 CPU_POWERPC_603E7 = 0x00070200,
4795 CPU_POWERPC_603P = 0x00070000,
4796#define CPU_POWERPC_603R CPU_POWERPC_603E7t
4797 CPU_POWERPC_G2 = 0x00810011,
4798#if 0 // Linux pretends the MSB is zero...
4799 CPU_POWERPC_G2H4 = 0x80811010,
4800 CPU_POWERPC_G2gp = 0x80821010,
4801 CPU_POWERPC_G2ls = 0x90810010,
4802 CPU_POWERPC_G2LE = 0x80820010,
4803 CPU_POWERPC_G2LEgp = 0x80822010,
4804 CPU_POWERPC_G2LEls = 0xA0822010,
4805#else
4806 CPU_POWERPC_G2H4 = 0x00811010,
4807 CPU_POWERPC_G2gp = 0x00821010,
4808 CPU_POWERPC_G2ls = 0x10810010,
4809 CPU_POWERPC_G2LE = 0x00820010,
4810 CPU_POWERPC_G2LEgp = 0x00822010,
4811 CPU_POWERPC_G2LEls = 0x20822010,
4812#endif
4813 CPU_POWERPC_604 = 0x00040103,
4814#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4815 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4816 CPU_POWERPC_604E_v22 = 0x00090202,
4817 CPU_POWERPC_604E_v24 = 0x00090204,
4818 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4819#if 0
4820 CPU_POWERPC_604EV = xxx,
4821#endif
4822 /* PowerPC 740/750 cores (aka G3) */
4823 /* XXX: missing 0x00084202 */
4824#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4825 CPU_POWERPC_7x0_v20 = 0x00080200,
4826 CPU_POWERPC_7x0_v21 = 0x00080201,
4827 CPU_POWERPC_7x0_v22 = 0x00080202,
4828 CPU_POWERPC_7x0_v30 = 0x00080300,
4829 CPU_POWERPC_7x0_v31 = 0x00080301,
4830 CPU_POWERPC_740E = 0x00080100,
4831 CPU_POWERPC_7x0P = 0x10080000,
4832 /* XXX: missing 0x00087010 (CL ?) */
4833 CPU_POWERPC_750CL = 0x00087200,
4834#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4835 CPU_POWERPC_750CX_v21 = 0x00082201,
4836 CPU_POWERPC_750CX_v22 = 0x00082202,
4837#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4838 CPU_POWERPC_750CXE_v21 = 0x00082211,
4839 CPU_POWERPC_750CXE_v22 = 0x00082212,
4840 CPU_POWERPC_750CXE_v23 = 0x00082213,
4841 CPU_POWERPC_750CXE_v24 = 0x00082214,
4842 CPU_POWERPC_750CXE_v24b = 0x00083214,
4843 CPU_POWERPC_750CXE_v31 = 0x00083211,
4844 CPU_POWERPC_750CXE_v31b = 0x00083311,
4845 CPU_POWERPC_750CXR = 0x00083410,
4846 CPU_POWERPC_750E = 0x00080200,
4847 CPU_POWERPC_750FL = 0x700A0203,
4848#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4849 CPU_POWERPC_750FX_v10 = 0x70000100,
4850 CPU_POWERPC_750FX_v20 = 0x70000200,
4851 CPU_POWERPC_750FX_v21 = 0x70000201,
4852 CPU_POWERPC_750FX_v22 = 0x70000202,
4853 CPU_POWERPC_750FX_v23 = 0x70000203,
4854 CPU_POWERPC_750GL = 0x70020102,
4855#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4856 CPU_POWERPC_750GX_v10 = 0x70020100,
4857 CPU_POWERPC_750GX_v11 = 0x70020101,
4858 CPU_POWERPC_750GX_v12 = 0x70020102,
4859#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4860 CPU_POWERPC_750L_v22 = 0x00088202,
4861 CPU_POWERPC_750L_v30 = 0x00088300,
4862 CPU_POWERPC_750L_v32 = 0x00088302,
4863 /* PowerPC 745/755 cores */
4864#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4865 CPU_POWERPC_7x5_v10 = 0x00083100,
4866 CPU_POWERPC_7x5_v11 = 0x00083101,
4867 CPU_POWERPC_7x5_v20 = 0x00083200,
4868 CPU_POWERPC_7x5_v21 = 0x00083201,
4869 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4870 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4871 CPU_POWERPC_7x5_v24 = 0x00083204,
4872 CPU_POWERPC_7x5_v25 = 0x00083205,
4873 CPU_POWERPC_7x5_v26 = 0x00083206,
4874 CPU_POWERPC_7x5_v27 = 0x00083207,
4875 CPU_POWERPC_7x5_v28 = 0x00083208,
4876#if 0
4877 CPU_POWERPC_7x5P = xxx,
4878#endif
4879 /* PowerPC 74xx cores (aka G4) */
4880 /* XXX: missing 0x000C1101 */
4881#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4882 CPU_POWERPC_7400_v10 = 0x000C0100,
4883 CPU_POWERPC_7400_v11 = 0x000C0101,
4884 CPU_POWERPC_7400_v20 = 0x000C0200,
4885 CPU_POWERPC_7400_v22 = 0x000C0202,
4886 CPU_POWERPC_7400_v26 = 0x000C0206,
4887 CPU_POWERPC_7400_v27 = 0x000C0207,
4888 CPU_POWERPC_7400_v28 = 0x000C0208,
4889 CPU_POWERPC_7400_v29 = 0x000C0209,
4890#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4891 CPU_POWERPC_7410_v10 = 0x800C1100,
4892 CPU_POWERPC_7410_v11 = 0x800C1101,
4893 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4894 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4895 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4896#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4897 CPU_POWERPC_7448_v10 = 0x80040100,
4898 CPU_POWERPC_7448_v11 = 0x80040101,
4899 CPU_POWERPC_7448_v20 = 0x80040200,
4900 CPU_POWERPC_7448_v21 = 0x80040201,
4901#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4902 CPU_POWERPC_7450_v10 = 0x80000100,
4903 CPU_POWERPC_7450_v11 = 0x80000101,
4904 CPU_POWERPC_7450_v12 = 0x80000102,
4905 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4906 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4907 CPU_POWERPC_74x1 = 0x80000203,
4908 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4909 /* XXX: missing 0x80010200 */
4910#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4911 CPU_POWERPC_74x5_v10 = 0x80010100,
4912 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4913 CPU_POWERPC_74x5_v32 = 0x80010302,
4914 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4915 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4916#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4917 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4918 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4919 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4920 /* 64 bits PowerPC */
00af685f 4921#if defined(TARGET_PPC64)
a750fc0b
JM		 4922 CPU_POWERPC_620 = 0x00140000,
4923 CPU_POWERPC_630 = 0x00400000,
4924 CPU_POWERPC_631 = 0x00410104,
4925 CPU_POWERPC_POWER4 = 0x00350000,
4926 CPU_POWERPC_POWER4P = 0x00380000,
4927 CPU_POWERPC_POWER5 = 0x003A0203,
4928#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4929 CPU_POWERPC_POWER5P = 0x003B0000,
4930#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4931 CPU_POWERPC_POWER6 = 0x003E0000,
4932 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4933 CPU_POWERPC_POWER6A = 0x0F000002,
4934 CPU_POWERPC_970 = 0x00390202,
4935#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4936 CPU_POWERPC_970FX_v10 = 0x00391100,
4937 CPU_POWERPC_970FX_v20 = 0x003C0200,
4938 CPU_POWERPC_970FX_v21 = 0x003C0201,
4939 CPU_POWERPC_970FX_v30 = 0x003C0300,
4940 CPU_POWERPC_970FX_v31 = 0x003C0301,
4941 CPU_POWERPC_970GX = 0x00450000,
4942#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4943 CPU_POWERPC_970MP_v10 = 0x00440100,
4944 CPU_POWERPC_970MP_v11 = 0x00440101,
4945#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4946 CPU_POWERPC_CELL_v10 = 0x00700100,
4947 CPU_POWERPC_CELL_v20 = 0x00700400,
4948 CPU_POWERPC_CELL_v30 = 0x00700500,
4949 CPU_POWERPC_CELL_v31 = 0x00700501,
4950#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4951 CPU_POWERPC_RS64 = 0x00330000,
4952 CPU_POWERPC_RS64II = 0x00340000,
4953 CPU_POWERPC_RS64III = 0x00360000,
4954 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 4955#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 4956 /* Original POWER */
4957 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4958 * POWER2 (RIOS2) & RSC2 (P2SC) here
4959 */
4960#if 0
4961 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4962#endif
4963#if 0
4964 CPU_POWER2 = xxx, /* 0x40000 ? */
4965#endif
4966 /* PA Semi core */
4967 CPU_POWERPC_PA6T = 0x00900000,
4968};
4969
4970/* System version register (used on MPC 8xxx) */
4971enum {
4972 PPC_SVR_8540 = 0x80300000,
4973 PPC_SVR_8541E = 0x807A0010,
4974 PPC_SVR_8543v10 = 0x80320010,
4975 PPC_SVR_8543v11 = 0x80320011,
4976 PPC_SVR_8543v20 = 0x80320020,
4977 PPC_SVR_8543Ev10 = 0x803A0010,
4978 PPC_SVR_8543Ev11 = 0x803A0011,
4979 PPC_SVR_8543Ev20 = 0x803A0020,
4980 PPC_SVR_8545 = 0x80310220,
4981 PPC_SVR_8545E = 0x80390220,
4982 PPC_SVR_8547E = 0x80390120,
4983 PPC_SCR_8548v10 = 0x80310010,
4984 PPC_SCR_8548v11 = 0x80310011,
4985 PPC_SCR_8548v20 = 0x80310020,
4986 PPC_SVR_8548Ev10 = 0x80390010,
4987 PPC_SVR_8548Ev11 = 0x80390011,
4988 PPC_SVR_8548Ev20 = 0x80390020,
4989 PPC_SVR_8555E = 0x80790010,
4990 PPC_SVR_8560v10 = 0x80700010,
4991 PPC_SVR_8560v20 = 0x80700020,
4992};
4993
3fc6c082 4994/*****************************************************************************/
a750fc0b
JM		 4995/* PowerPC CPU definitions */
4996#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4997 { \
4998 .name = _name, \
4999 .pvr = _pvr, \
5000 .pvr_mask = _pvr_mask, \
5001 .insns_flags = glue(POWERPC_INSNS_,_type), \
5002 .msr_mask = glue(POWERPC_MSRM_,_type), \
5003 .mmu_model = glue(POWERPC_MMU_,_type), \
5004 .excp_model = glue(POWERPC_EXCP_,_type), \
5005 .bus_model = glue(POWERPC_INPUT_,_type), \
237c0af0 5006 .bfd_mach = glue(POWERPC_BFDM_,_type), \
d26bfc9a 5007 .flags = glue(POWERPC_FLAG_,_type), \
a750fc0b 5008 .init_proc = &glue(init_proc_,_type), \
2f462816 5009 .check_pow = &glue(check_pow_,_type), \
a750fc0b
JM		 5010 }
5011
3a607854 5012static ppc_def_t ppc_defs[] = {
a750fc0b
JM		 5013 /* Embedded PowerPC */
5014 /* PowerPC 401 family */
2662a059 5015 /* Generic PowerPC 401 */
a750fc0b
JM		 5016 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
5017 /* PowerPC 401 cores */
2662a059 5018 /* PowerPC 401A1 */
a750fc0b
JM		 5019 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
5020 /* PowerPC 401B2 */
5021 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
2662a059 5022#if defined (TODO)
a750fc0b
JM		 5023 /* PowerPC 401B3 */
5024 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
5025#endif
5026 /* PowerPC 401C2 */
5027 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
5028 /* PowerPC 401D2 */
5029 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
5030 /* PowerPC 401E2 */
5031 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
5032 /* PowerPC 401F2 */
5033 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
5034 /* PowerPC 401G2 */
5035 /* XXX: to be checked */
5036 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
5037 /* PowerPC 401 microcontrolers */
2662a059 5038#if defined (TODO)
a750fc0b
JM		 5039 /* PowerPC 401GF */
5040 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
3fc6c082 5041#endif
a750fc0b
JM		 5042 /* IOP480 (401 microcontroler) */
5043 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
5044 /* IBM Processor for Network Resources */
5045 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
3fc6c082 5046#if defined (TODO)
a750fc0b 5047 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
3fc6c082 5048#endif
a750fc0b
JM		 5049 /* PowerPC 403 family */
5050 /* Generic PowerPC 403 */
5051 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
5052 /* PowerPC 403 microcontrolers */
5053 /* PowerPC 403 GA */
5054 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
5055 /* PowerPC 403 GB */
5056 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
5057 /* PowerPC 403 GC */
5058 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
5059 /* PowerPC 403 GCX */
5060 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
3fc6c082 5061#if defined (TODO)
a750fc0b
JM		 5062 /* PowerPC 403 GP */
5063 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
3fc6c082 5064#endif
a750fc0b
JM		 5065 /* PowerPC 405 family */
5066 /* Generic PowerPC 405 */
5067 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
5068 /* PowerPC 405 cores */
2662a059 5069#if defined (TODO)
a750fc0b
JM		 5070 /* PowerPC 405 A3 */
5071 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
3a607854 5072#endif
3a607854 5073#if defined (TODO)
a750fc0b
JM		 5074 /* PowerPC 405 A4 */
5075 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
3a607854 5076#endif
3a607854 5077#if defined (TODO)
a750fc0b
JM		 5078 /* PowerPC 405 B3 */
5079 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
3fc6c082
FB		 5080#endif
5081#if defined (TODO)
a750fc0b
JM		 5082 /* PowerPC 405 B4 */
5083 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
5084#endif
5085#if defined (TODO)
5086 /* PowerPC 405 C3 */
5087 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
5088#endif
5089#if defined (TODO)
5090 /* PowerPC 405 C4 */
5091 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
5092#endif
5093 /* PowerPC 405 D2 */
5094 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
5095#if defined (TODO)
5096 /* PowerPC 405 D3 */
5097 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
5098#endif
5099 /* PowerPC 405 D4 */
5100 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
5101#if defined (TODO)
5102 /* PowerPC 405 D5 */
5103 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
5104#endif
5105#if defined (TODO)
5106 /* PowerPC 405 E4 */
5107 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
5108#endif
5109#if defined (TODO)
5110 /* PowerPC 405 F4 */
5111 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
5112#endif
5113#if defined (TODO)
5114 /* PowerPC 405 F5 */
5115 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
5116#endif
5117#if defined (TODO)
5118 /* PowerPC 405 F6 */
5119 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
5120#endif
5121 /* PowerPC 405 microcontrolers */
5122 /* PowerPC 405 CR */
5123 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
5124 /* PowerPC 405 CRa */
5125 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
5126 /* PowerPC 405 CRb */
5127 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
5128 /* PowerPC 405 CRc */
5129 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
5130 /* PowerPC 405 EP */
5131 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
5132#if defined(TODO)
5133 /* PowerPC 405 EXr */
5134 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
5135#endif
5136 /* PowerPC 405 EZ */
5137 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
5138#if defined(TODO)
5139 /* PowerPC 405 FX */
5140 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
5141#endif
5142 /* PowerPC 405 GP */
5143 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
5144 /* PowerPC 405 GPa */
5145 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
5146 /* PowerPC 405 GPb */
5147 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
5148 /* PowerPC 405 GPc */
5149 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
5150 /* PowerPC 405 GPd */
5151 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
5152 /* PowerPC 405 GPe */
5153 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
5154 /* PowerPC 405 GPR */
5155 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
5156#if defined(TODO)
5157 /* PowerPC 405 H */
5158 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
5159#endif
5160#if defined(TODO)
5161 /* PowerPC 405 L */
5162 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
5163#endif
5164 /* PowerPC 405 LP */
5165 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
5166#if defined(TODO)
5167 /* PowerPC 405 PM */
5168 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
5169#endif
5170#if defined(TODO)
5171 /* PowerPC 405 PS */
5172 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
5173#endif
5174#if defined(TODO)
5175 /* PowerPC 405 S */
5176 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
5177#endif
5178 /* Npe405 H */
5179 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
5180 /* Npe405 H2 */
5181 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
5182 /* Npe405 L */
5183 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
5184 /* Npe4GS3 */
5185 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
5186#if defined (TODO)
5187 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
5188#endif
5189#if defined (TODO)
5190 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
5191#endif
5192#if defined (TODO)
5193 /* PowerPC LC77700 (Sanyo) */
5194 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
5195#endif
5196 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5197#if defined (TODO)
5198 /* STB010000 */
5199 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
5200#endif
5201#if defined (TODO)
5202 /* STB01010 */
5203 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
5204#endif
5205#if defined (TODO)
5206 /* STB0210 */
5207 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
5208#endif
5209 /* STB03xx */
5210 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
5211#if defined (TODO)
5212 /* STB043x */
5213 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
5214#endif
5215#if defined (TODO)
5216 /* STB045x */
5217 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
5218#endif
5219 /* STB04xx */
5220 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
5221 /* STB25xx */
5222 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
5223#if defined (TODO)
5224 /* STB130 */
5225 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
5226#endif
5227 /* Xilinx PowerPC 405 cores */
5228 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
5229 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
5230 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
5231 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
5232#if defined (TODO)
5233 /* Zarlink ZL10310 */
5234 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
5235#endif
5236#if defined (TODO)
5237 /* Zarlink ZL10311 */
5238 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
5239#endif
5240#if defined (TODO)
5241 /* Zarlink ZL10320 */
5242 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
5243#endif
5244#if defined (TODO)
5245 /* Zarlink ZL10321 */
5246 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
5247#endif
5248 /* PowerPC 440 family */
5249 /* Generic PowerPC 440 */
5250 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
5251 /* PowerPC 440 cores */
5252#if defined (TODO)
5253 /* PowerPC 440 A4 */
5254 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
5255#endif
5256#if defined (TODO)
5257 /* PowerPC 440 A5 */
5258 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
5259#endif
5260#if defined (TODO)
5261 /* PowerPC 440 B4 */
5262 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
5263#endif
5264#if defined (TODO)
5265 /* PowerPC 440 G4 */
5266 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
5267#endif
5268#if defined (TODO)
5269 /* PowerPC 440 F5 */
5270 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
5271#endif
5272#if defined (TODO)
5273 /* PowerPC 440 G5 */
5274 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
5275#endif
5276#if defined (TODO)
5277 /* PowerPC 440H4 */
5278 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
5279#endif
5280#if defined (TODO)
5281 /* PowerPC 440H6 */
5282 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
5283#endif
5284 /* PowerPC 440 microcontrolers */
5285 /* PowerPC 440 EP */
5286 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
5287 /* PowerPC 440 EPa */
5288 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
5289 /* PowerPC 440 EPb */
5290 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
5291 /* PowerPC 440 EPX */
5292 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
5293 /* PowerPC 440 GP */
5294 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
5295 /* PowerPC 440 GPb */
5296 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
5297 /* PowerPC 440 GPc */
5298 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
5299 /* PowerPC 440 GR */
5300 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
5301 /* PowerPC 440 GRa */
5302 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
5303 /* PowerPC 440 GRX */
5304 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
5305 /* PowerPC 440 GX */
5306 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
5307 /* PowerPC 440 GXa */
5308 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
5309 /* PowerPC 440 GXb */
5310 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
5311 /* PowerPC 440 GXc */
5312 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
5313 /* PowerPC 440 GXf */
5314 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
5315#if defined(TODO)
5316 /* PowerPC 440 S */
5317 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
5318#endif
5319 /* PowerPC 440 SP */
5320 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
5321 /* PowerPC 440 SP2 */
5322 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
5323 /* PowerPC 440 SPE */
5324 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
5325 /* PowerPC 460 family */
5326#if defined (TODO)
5327 /* Generic PowerPC 464 */
5328 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
5329#endif
5330 /* PowerPC 464 microcontrolers */
5331#if defined (TODO)
5332 /* PowerPC 464H90 */
5333 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
5334#endif
5335#if defined (TODO)
5336 /* PowerPC 464H90F */
5337 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
5338#endif
5339 /* Freescale embedded PowerPC cores */
5340 /* e200 family */
5341#if defined (TODO)
5342 /* Generic PowerPC e200 core */
5343 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
5344#endif
5345#if defined (TODO)
5346 /* PowerPC e200z5 core */
5347 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
5348#endif
5349#if defined (TODO)
5350 /* PowerPC e200z6 core */
5351 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
5352#endif
5353 /* e300 family */
5354#if defined (TODO)
5355 /* Generic PowerPC e300 core */
5356 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
5357#endif
5358#if defined (TODO)
5359 /* PowerPC e300c1 core */
5360 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
5361#endif
5362#if defined (TODO)
5363 /* PowerPC e300c2 core */
5364 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
5365#endif
5366#if defined (TODO)
5367 /* PowerPC e300c3 core */
5368 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
5369#endif
5370 /* e500 family */
5371#if defined (TODO)
5372 /* PowerPC e500 core */
5373 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
5374#endif
5375#if defined (TODO)
5376 /* PowerPC e500 v1.1 core */
5377 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
5378#endif
5379#if defined (TODO)
5380 /* PowerPC e500 v1.2 core */
5381 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
5382#endif
5383#if defined (TODO)
5384 /* PowerPC e500 v2.1 core */
5385 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
5386#endif
5387#if defined (TODO)
5388 /* PowerPC e500 v2.2 core */
5389 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
5390#endif
5391 /* e600 family */
5392#if defined (TODO)
5393 /* PowerPC e600 core */
5394 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
5395#endif
5396 /* PowerPC MPC 5xx cores */
5397#if defined (TODO)
5398 /* PowerPC MPC 5xx */
5399 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
5400#endif
5401 /* PowerPC MPC 8xx cores */
5402#if defined (TODO)
5403 /* PowerPC MPC 8xx */
5404 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
5405#endif
5406 /* PowerPC MPC 8xxx cores */
5407#if defined (TODO)
5408 /* PowerPC MPC 82xx HIP3 */
5409 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
5410#endif
5411#if defined (TODO)
5412 /* PowerPC MPC 82xx HIP4 */
5413 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
5414#endif
5415#if defined (TODO)
5416 /* PowerPC MPC 827x */
5417 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
5418#endif
5419
5420 /* 32 bits "classic" PowerPC */
5421 /* PowerPC 6xx family */
5422 /* PowerPC 601 */
5423 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
5424 /* PowerPC 601v2 */
5425 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
5426 /* PowerPC 602 */
5427 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
5428 /* PowerPC 603 */
5429 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5430 /* Code name for PowerPC 603 */
5431 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
5432 /* PowerPC 603e */
5433 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5434 /* Code name for PowerPC 603e */
5435 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
5436 /* PowerPC 603e v1.1 */
5437 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
5438 /* PowerPC 603e v1.2 */
5439 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
5440 /* PowerPC 603e v1.3 */
5441 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
5442 /* PowerPC 603e v1.4 */
5443 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
5444 /* PowerPC 603e v2.2 */
5445 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
5446 /* PowerPC 603e v3 */
5447 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
5448 /* PowerPC 603e v4 */
5449 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
5450 /* PowerPC 603e v4.1 */
5451 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
5452 /* PowerPC 603e */
5453 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
5454 /* PowerPC 603e7t */
5455 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
5456 /* PowerPC 603e7v */
5457 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5458 /* Code name for PowerPC 603ev */
5459 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
5460 /* PowerPC 603e7v1 */
5461 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
5462 /* PowerPC 603e7v2 */
5463 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
5464 /* PowerPC 603p */
5465 /* to be checked */
5466 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
5467 /* PowerPC 603r */
5468 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5469 /* Code name for PowerPC 603r */
5470 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
5471 /* PowerPC G2 core */
5472 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
5473 /* PowerPC G2 H4 */
5474 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
5475 /* PowerPC G2 GP */
5476 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
5477 /* PowerPC G2 LS */
5478 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
5479 /* PowerPC G2LE */
5480 /* Same as G2, with little-endian mode support */
5481 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
5482 /* PowerPC G2LE GP */
5483 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
5484 /* PowerPC G2LE LS */
5485 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
5486 /* PowerPC 604 */
5487 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
5488 /* PowerPC 604e */
5489 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
5490 /* PowerPC 604e v1.0 */
5491 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
5492 /* PowerPC 604e v2.2 */
5493 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
5494 /* PowerPC 604e v2.4 */
5495 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
5496 /* PowerPC 604r */
5497 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
5498#if defined(TODO)
5499 /* PowerPC 604ev */
5500 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
5501#endif
5502 /* PowerPC 7xx family */
5503 /* Generic PowerPC 740 (G3) */
5504 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5505 /* Generic PowerPC 750 (G3) */
5506 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5507 /* Code name for generic PowerPC 740/750 (G3) */
5508 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5509 /* PowerPC 740/750 is also known as G3 */
5510 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
5511 /* PowerPC 740 v2.0 (G3) */
5512 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5513 /* PowerPC 750 v2.0 (G3) */
5514 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
5515 /* PowerPC 740 v2.1 (G3) */
5516 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5517 /* PowerPC 750 v2.1 (G3) */
5518 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
5519 /* PowerPC 740 v2.2 (G3) */
5520 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5521 /* PowerPC 750 v2.2 (G3) */
5522 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
5523 /* PowerPC 740 v3.0 (G3) */
5524 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5525 /* PowerPC 750 v3.0 (G3) */
5526 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
5527 /* PowerPC 740 v3.1 (G3) */
5528 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5529 /* PowerPC 750 v3.1 (G3) */
5530 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
5531 /* PowerPC 740E (G3) */
5532 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
5533 /* PowerPC 740P (G3) */
5534 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5535 /* PowerPC 750P (G3) */
5536 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5537 /* Code name for PowerPC 740P/750P (G3) */
5538 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
5539 /* PowerPC 750CL (G3 embedded) */
5540 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
5541 /* PowerPC 750CX (G3 embedded) */
5542 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
5543 /* PowerPC 750CX v2.1 (G3 embedded) */
5544 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
5545 /* PowerPC 750CX v2.2 (G3 embedded) */
5546 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
5547 /* PowerPC 750CXe (G3 embedded) */
5548 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
5549 /* PowerPC 750CXe v2.1 (G3 embedded) */
5550 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
5551 /* PowerPC 750CXe v2.2 (G3 embedded) */
5552 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
5553 /* PowerPC 750CXe v2.3 (G3 embedded) */
5554 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5555 /* PowerPC 750CXe v2.4 (G3 embedded) */
5556 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5557 /* PowerPC 750CXe v2.4b (G3 embedded) */
5558 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5559 /* PowerPC 750CXe v3.1 (G3 embedded) */
5560 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5561 /* PowerPC 750CXe v3.1b (G3 embedded) */
5562 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5563 /* PowerPC 750CXr (G3 embedded) */
5564 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5565 /* PowerPC 750E (G3) */
5566 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5567 /* PowerPC 750FL (G3 embedded) */
d12f4c38 5568 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5569 /* PowerPC 750FX (G3 embedded) */
5570 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5571 /* PowerPC 750FX v1.0 (G3 embedded) */
5572 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5573 /* PowerPC 750FX v2.0 (G3 embedded) */
5574 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5575 /* PowerPC 750FX v2.1 (G3 embedded) */
5576 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5577 /* PowerPC 750FX v2.2 (G3 embedded) */
5578 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5579 /* PowerPC 750FX v2.3 (G3 embedded) */
5580 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5581 /* PowerPC 750GL (G3 embedded) */
d12f4c38 5582 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
a750fc0b
JM		 5583 /* PowerPC 750GX (G3 embedded) */
5584 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5585 /* PowerPC 750GX v1.0 (G3 embedded) */
5586 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5587 /* PowerPC 750GX v1.1 (G3 embedded) */
5588 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5589 /* PowerPC 750GX v1.2 (G3 embedded) */
5590 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5591 /* PowerPC 750L (G3 embedded) */
5592 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5593 /* Code name for PowerPC 750L (G3 embedded) */
5594 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5595 /* PowerPC 750L v2.2 (G3 embedded) */
5596 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5597 /* PowerPC 750L v3.0 (G3 embedded) */
5598 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5599 /* PowerPC 750L v3.2 (G3 embedded) */
5600 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5601 /* Generic PowerPC 745 */
5602 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5603 /* Generic PowerPC 755 */
5604 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5605 /* Code name for PowerPC 745/755 */
5606 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5607 /* PowerPC 745 v1.0 */
5608 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5609 /* PowerPC 755 v1.0 */
5610 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5611 /* PowerPC 745 v1.1 */
5612 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5613 /* PowerPC 755 v1.1 */
5614 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5615 /* PowerPC 745 v2.0 */
5616 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5617 /* PowerPC 755 v2.0 */
5618 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5619 /* PowerPC 745 v2.1 */
5620 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5621 /* PowerPC 755 v2.1 */
5622 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5623 /* PowerPC 745 v2.2 */
5624 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5625 /* PowerPC 755 v2.2 */
5626 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5627 /* PowerPC 745 v2.3 */
5628 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5629 /* PowerPC 755 v2.3 */
5630 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5631 /* PowerPC 745 v2.4 */
5632 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5633 /* PowerPC 755 v2.4 */
5634 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5635 /* PowerPC 745 v2.5 */
5636 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5637 /* PowerPC 755 v2.5 */
5638 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5639 /* PowerPC 745 v2.6 */
5640 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5641 /* PowerPC 755 v2.6 */
5642 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5643 /* PowerPC 745 v2.7 */
5644 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5645 /* PowerPC 755 v2.7 */
5646 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5647 /* PowerPC 745 v2.8 */
5648 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5649 /* PowerPC 755 v2.8 */
5650 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5651#if defined (TODO)
5652 /* PowerPC 745P (G3) */
5653 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5654 /* PowerPC 755P (G3) */
5655 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5656#endif
5657 /* PowerPC 74xx family */
5658 /* PowerPC 7400 (G4) */
5659 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5660 /* Code name for PowerPC 7400 */
5661 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5662 /* PowerPC 74xx is also well known as G4 */
5663 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5664 /* PowerPC 7400 v1.0 (G4) */
5665 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5666 /* PowerPC 7400 v1.1 (G4) */
5667 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5668 /* PowerPC 7400 v2.0 (G4) */
5669 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5670 /* PowerPC 7400 v2.2 (G4) */
5671 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5672 /* PowerPC 7400 v2.6 (G4) */
5673 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5674 /* PowerPC 7400 v2.7 (G4) */
5675 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5676 /* PowerPC 7400 v2.8 (G4) */
5677 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5678 /* PowerPC 7400 v2.9 (G4) */
5679 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5680 /* PowerPC 7410 (G4) */
5681 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5682 /* Code name for PowerPC 7410 */
5683 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5684 /* PowerPC 7410 v1.0 (G4) */
5685 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5686 /* PowerPC 7410 v1.1 (G4) */
5687 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5688 /* PowerPC 7410 v1.2 (G4) */
5689 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5690 /* PowerPC 7410 v1.3 (G4) */
5691 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5692 /* PowerPC 7410 v1.4 (G4) */
5693 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5694 /* PowerPC 7448 (G4) */
5695 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5696 /* PowerPC 7448 v1.0 (G4) */
5697 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5698 /* PowerPC 7448 v1.1 (G4) */
5699 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5700 /* PowerPC 7448 v2.0 (G4) */
5701 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5702 /* PowerPC 7448 v2.1 (G4) */
5703 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
a750fc0b
JM		 5704 /* PowerPC 7450 (G4) */
5705 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5706 /* Code name for PowerPC 7450 */
5707 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5708 /* PowerPC 7450 v1.0 (G4) */
5709 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5710 /* PowerPC 7450 v1.1 (G4) */
5711 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5712 /* PowerPC 7450 v1.2 (G4) */
5713 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5714 /* PowerPC 7450 v2.0 (G4) */
5715 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5716 /* PowerPC 7450 v2.1 (G4) */
5717 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5718 /* PowerPC 7441 (G4) */
5719 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5720 /* PowerPC 7451 (G4) */
5721 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5722 /* PowerPC 7441g (G4) */
5723 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5724 /* PowerPC 7451g (G4) */
5725 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
a750fc0b
JM		 5726 /* PowerPC 7445 (G4) */
5727 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5728 /* PowerPC 7455 (G4) */
5729 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5730 /* Code name for PowerPC 7445/7455 */
5731 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5732 /* PowerPC 7445 v1.0 (G4) */
5733 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5734 /* PowerPC 7455 v1.0 (G4) */
5735 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5736 /* PowerPC 7445 v2.1 (G4) */
5737 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5738 /* PowerPC 7455 v2.1 (G4) */
5739 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5740 /* PowerPC 7445 v3.2 (G4) */
5741 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5742 /* PowerPC 7455 v3.2 (G4) */
5743 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5744 /* PowerPC 7445 v3.3 (G4) */
5745 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5746 /* PowerPC 7455 v3.3 (G4) */
5747 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5748 /* PowerPC 7445 v3.4 (G4) */
5749 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5750 /* PowerPC 7455 v3.4 (G4) */
5751 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5752 /* PowerPC 7447 (G4) */
5753 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5754 /* PowerPC 7457 (G4) */
5755 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5756 /* Code name for PowerPC 7447/7457 */
5757 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5758 /* PowerPC 7447 v1.0 (G4) */
5759 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5760 /* PowerPC 7457 v1.0 (G4) */
5761 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5762 /* Code name for PowerPC 7447A/7457A */
5763 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5764 /* PowerPC 7447 v1.1 (G4) */
5765 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5766 /* PowerPC 7457 v1.1 (G4) */
5767 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5768 /* PowerPC 7447 v1.2 (G4) */
5769 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5770 /* PowerPC 7457 v1.2 (G4) */
5771 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
a750fc0b
JM		 5772 /* 64 bits PowerPC */
5773#if defined (TARGET_PPC64)
3fc6c082 5774#if defined (TODO)
a750fc0b
JM		 5775 /* PowerPC 620 */
5776 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5777#endif
3fc6c082 5778#if defined (TODO)
a750fc0b
JM		 5779 /* PowerPC 630 (POWER3) */
5780 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5781 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5782#endif
3a607854 5783#if defined (TODO)
a750fc0b
JM		 5784 /* PowerPC 631 (Power 3+) */
5785 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5786 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
3a607854
JM		 5787#endif
5788#if defined (TODO)
a750fc0b
JM		 5789 /* POWER4 */
5790 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5791#endif
3a607854 5792#if defined (TODO)
a750fc0b
JM		 5793 /* POWER4p */
5794 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5795#endif
2662a059 5796#if defined (TODO)
a750fc0b
JM		 5797 /* POWER5 */
5798 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5799 /* POWER5GR */
5800 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
2662a059 5801#endif
3a607854 5802#if defined (TODO)
a750fc0b
JM		 5803 /* POWER5+ */
5804 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5805 /* POWER5GS */
5806 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5807#endif
2662a059 5808#if defined (TODO)
a750fc0b
JM		 5809 /* POWER6 */
5810 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5811 /* POWER6 running in POWER5 mode */
5812 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5813 /* POWER6A */
5814 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
2662a059 5815#endif
a750fc0b
JM		 5816 /* PowerPC 970 */
5817 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
a750fc0b
JM		 5818 /* PowerPC 970FX (G5) */
5819 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5820 /* PowerPC 970FX v1.0 (G5) */
5821 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5822 /* PowerPC 970FX v2.0 (G5) */
5823 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5824 /* PowerPC 970FX v2.1 (G5) */
5825 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5826 /* PowerPC 970FX v3.0 (G5) */
5827 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5828 /* PowerPC 970FX v3.1 (G5) */
5829 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
a750fc0b
JM		 5830 /* PowerPC 970GX (G5) */
5831 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
a750fc0b 5832 /* PowerPC 970MP */
2f462816 5833 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970MP),
a750fc0b 5834 /* PowerPC 970MP v1.0 */
2f462816 5835 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970MP),
a750fc0b 5836 /* PowerPC 970MP v1.1 */
2f462816 5837 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970MP),
3a607854 5838#if defined (TODO)
a750fc0b
JM		 5839 /* PowerPC Cell */
5840 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
2662a059
JM		 5841#endif
5842#if defined (TODO)
a750fc0b
JM		 5843 /* PowerPC Cell v1.0 */
5844 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
2662a059
JM		 5845#endif
5846#if defined (TODO)
a750fc0b
JM		 5847 /* PowerPC Cell v2.0 */
5848 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
2662a059
JM		 5849#endif
5850#if defined (TODO)
a750fc0b
JM		 5851 /* PowerPC Cell v3.0 */
5852 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
3a607854 5853#endif
3a607854 5854#if defined (TODO)
a750fc0b
JM		 5855 /* PowerPC Cell v3.1 */
5856 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
2662a059
JM		 5857#endif
5858#if defined (TODO)
a750fc0b
JM		 5859 /* PowerPC Cell v3.2 */
5860 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
2662a059
JM		 5861#endif
5862#if defined (TODO)
a750fc0b
JM		 5863 /* RS64 (Apache/A35) */
5864 /* This one seems to support the whole POWER2 instruction set
5865 * and the PowerPC 64 one.
5866 */
5867 /* What about A10 & A30 ? */
5868 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5869 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5870 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
3a607854
JM		 5871#endif
5872#if defined (TODO)
a750fc0b
JM		 5873 /* RS64-II (NorthStar/A50) */
5874 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5875 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5876 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
3a607854
JM		 5877#endif
5878#if defined (TODO)
a750fc0b
JM		 5879 /* RS64-III (Pulsar) */
5880 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5881 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
2662a059
JM		 5882#endif
5883#if defined (TODO)
a750fc0b
JM		 5884 /* RS64-IV (IceStar/IStar/SStar) */
5885 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5886 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5887 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5888 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
3a607854 5889#endif
a750fc0b
JM		 5890#endif /* defined (TARGET_PPC64) */
5891 /* POWER */
3fc6c082 5892#if defined (TODO)
a750fc0b
JM		 5893 /* Original POWER */
5894 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5895 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5896 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5897 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5898 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
76a66253
JM		 5899#endif
5900#if defined (TODO)
a750fc0b
JM		 5901 /* POWER2 */
5902 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5903 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5904 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5905#endif
5906 /* PA semi cores */
5907#if defined (TODO)
5908 /* PA PA6T */
5909 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5910#endif
5911 /* Generic PowerPCs */
5912#if defined (TARGET_PPC64)
5913#if defined (TODO)
5914 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5915#endif
5916#endif
5917 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
d12f4c38 5918 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b 5919 /* Fallback */
d12f4c38 5920 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
a750fc0b
JM		 5921};
5922
5923/*****************************************************************************/
5924/* Generic CPU instanciation routine */
5925static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5926{
5927#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 5928 int i;
5929
a750fc0b 5930 env->irq_inputs = NULL;
e1833e1f
JM		 5931 /* Set all exception vectors to an invalid address */
5932 for (i = 0; i < POWERPC_EXCP_NB; i++)
5933 env->excp_vectors[i] = (target_ulong)(-1ULL);
5934 env->excp_prefix = 0x00000000;
5935 env->ivor_mask = 0x00000000;
5936 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 5937 /* Default MMU definitions */
5938 env->nb_BATs = 0;
5939 env->nb_tlb = 0;
5940 env->nb_ways = 0;
f2e63a42 5941#endif
a750fc0b
JM		 5942 /* Register SPR common to all PowerPC implementations */
5943 gen_spr_generic(env);
5944 spr_register(env, SPR_PVR, "PVR",
5945 SPR_NOACCESS, SPR_NOACCESS,
5946 &spr_read_generic, SPR_NOACCESS,
5947 def->pvr);
5948 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5949 (*def->init_proc)(env);
25ba3a68
JM		 5950 /* MSR bits & flags consistency checks */
5951 if (env->msr_mask & (1 << 25)) {
5952 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
5953 case POWERPC_FLAG_SPE:
5954 case POWERPC_FLAG_VRE:
5955 break;
5956 default:
5957 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5958 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
5959 exit(1);
5960 }
5961 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
5962 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5963 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
5964 exit(1);
5965 }
5966 if (env->msr_mask & (1 << 17)) {
5967 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
5968 case POWERPC_FLAG_TGPR:
5969 case POWERPC_FLAG_CE:
5970 break;
5971 default:
5972 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5973 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
5974 exit(1);
5975 }
5976 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
5977 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5978 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
5979 exit(1);
5980 }
5981 if (env->msr_mask & (1 << 10)) {
5982 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
5983 POWERPC_FLAG_UBLE)) {
5984 case POWERPC_FLAG_SE:
5985 case POWERPC_FLAG_DWE:
5986 case POWERPC_FLAG_UBLE:
5987 break;
5988 default:
5989 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5990 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
5991 "POWERPC_FLAG_UBLE\n");
5992 exit(1);
5993 }
5994 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
5995 POWERPC_FLAG_UBLE)) {
5996 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
5997 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
5998 "POWERPC_FLAG_UBLE\n");
5999 exit(1);
6000 }
6001 if (env->msr_mask & (1 << 9)) {
6002 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6003 case POWERPC_FLAG_BE:
6004 case POWERPC_FLAG_DE:
6005 break;
6006 default:
6007 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6008 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6009 exit(1);
6010 }
6011 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6012 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6013 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6014 exit(1);
6015 }
6016 if (env->msr_mask & (1 << 2)) {
6017 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6018 case POWERPC_FLAG_PX:
6019 case POWERPC_FLAG_PMM:
6020 break;
6021 default:
6022 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6023 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6024 exit(1);
6025 }
6026 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6027 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6028 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6029 exit(1);
6030 }
a750fc0b 6031 /* Allocate TLBs buffer when needed */
f2e63a42 6032#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 6033 if (env->nb_tlb != 0) {
6034 int nb_tlb = env->nb_tlb;
6035 if (env->id_tlbs != 0)
6036 nb_tlb *= 2;
6037 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
6038 /* Pre-compute some useful values */
6039 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6040 }
a750fc0b
JM		 6041 if (env->irq_inputs == NULL) {
6042 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
6043 " Attempt Qemu to crash very soon !\n");
6044 }
6045#endif
2f462816
JM		 6046 if (env->check_pow == NULL) {
6047 fprintf(stderr, "WARNING: no power management check handler "
6048 "registered.\n"
6049 " Attempt Qemu to crash very soon !\n");
6050 }
a750fc0b
JM		 6051}
6052
6053#if defined(PPC_DUMP_CPU)
6054static void dump_ppc_sprs (CPUPPCState *env)
6055{
6056 ppc_spr_t *spr;
6057#if !defined(CONFIG_USER_ONLY)
6058 uint32_t sr, sw;
6059#endif
6060 uint32_t ur, uw;
6061 int i, j, n;
6062
6063 printf("Special purpose registers:\n");
6064 for (i = 0; i < 32; i++) {
6065 for (j = 0; j < 32; j++) {
6066 n = (i << 5) | j;
6067 spr = &env->spr_cb[n];
6068 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
6069 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
6070#if !defined(CONFIG_USER_ONLY)
6071 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
6072 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
6073 if (sw || sr || uw || ur) {
6074 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
6075 (i << 5) | j, (i << 5) | j, spr->name,
6076 sw ? 'w' : '-', sr ? 'r' : '-',
6077 uw ? 'w' : '-', ur ? 'r' : '-');
6078 }
6079#else
6080 if (uw || ur) {
6081 printf("SPR: %4d (%03x) %-8s u%c%c\n",
6082 (i << 5) | j, (i << 5) | j, spr->name,
6083 uw ? 'w' : '-', ur ? 'r' : '-');
6084 }
6085#endif
6086 }
6087 }
6088 fflush(stdout);
6089 fflush(stderr);
6090}
6091#endif
6092
6093/*****************************************************************************/
6094#include <stdlib.h>
6095#include <string.h>
6096
6097int fflush (FILE *stream);
6098
6099/* Opcode types */
6100enum {
6101 PPC_DIRECT = 0, /* Opcode routine */
6102 PPC_INDIRECT = 1, /* Indirect opcode table */
6103};
6104
6105static inline int is_indirect_opcode (void *handler)
6106{
6107 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
6108}
6109
6110static inline opc_handler_t **ind_table(void *handler)
6111{
6112 return (opc_handler_t **)((unsigned long)handler & ~3);
6113}
6114
6115/* Instruction table creation */
6116/* Opcodes tables creation */
6117static void fill_new_table (opc_handler_t **table, int len)
6118{
6119 int i;
6120
6121 for (i = 0; i < len; i++)
6122 table[i] = &invalid_handler;
6123}
6124
6125static int create_new_table (opc_handler_t **table, unsigned char idx)
6126{
6127 opc_handler_t **tmp;
6128
6129 tmp = malloc(0x20 * sizeof(opc_handler_t));
6130 if (tmp == NULL)
6131 return -1;
6132 fill_new_table(tmp, 0x20);
6133 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
6134
6135 return 0;
6136}
6137
6138static int insert_in_table (opc_handler_t **table, unsigned char idx,
6139 opc_handler_t *handler)
6140{
6141 if (table[idx] != &invalid_handler)
6142 return -1;
6143 table[idx] = handler;
6144
6145 return 0;
6146}
6147
6148static int register_direct_insn (opc_handler_t **ppc_opcodes,
6149 unsigned char idx, opc_handler_t *handler)
6150{
6151 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6152 printf("*** ERROR: opcode %02x already assigned in main "
6153 "opcode table\n", idx);
6154 return -1;
6155 }
6156
6157 return 0;
6158}
6159
6160static int register_ind_in_table (opc_handler_t **table,
6161 unsigned char idx1, unsigned char idx2,
6162 opc_handler_t *handler)
6163{
6164 if (table[idx1] == &invalid_handler) {
6165 if (create_new_table(table, idx1) < 0) {
6166 printf("*** ERROR: unable to create indirect table "
6167 "idx=%02x\n", idx1);
6168 return -1;
6169 }
6170 } else {
6171 if (!is_indirect_opcode(table[idx1])) {
6172 printf("*** ERROR: idx %02x already assigned to a direct "
6173 "opcode\n", idx1);
6174 return -1;
6175 }
3a607854 6176 }
a750fc0b
JM		 6177 if (handler != NULL &&
6178 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6179 printf("*** ERROR: opcode %02x already assigned in "
6180 "opcode table %02x\n", idx2, idx1);
6181 return -1;
3a607854 6182 }
a750fc0b
JM		 6183
6184 return 0;
6185}
6186
6187static int register_ind_insn (opc_handler_t **ppc_opcodes,
6188 unsigned char idx1, unsigned char idx2,
6189 opc_handler_t *handler)
6190{
6191 int ret;
6192
6193 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6194
6195 return ret;
6196}
6197
6198static int register_dblind_insn (opc_handler_t **ppc_opcodes,
6199 unsigned char idx1, unsigned char idx2,
6200 unsigned char idx3, opc_handler_t *handler)
6201{
6202 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6203 printf("*** ERROR: unable to join indirect table idx "
6204 "[%02x-%02x]\n", idx1, idx2);
6205 return -1;
6206 }
6207 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
6208 handler) < 0) {
6209 printf("*** ERROR: unable to insert opcode "
6210 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6211 return -1;
6212 }
6213
6214 return 0;
6215}
6216
6217static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
6218{
6219 if (insn->opc2 != 0xFF) {
6220 if (insn->opc3 != 0xFF) {
6221 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6222 insn->opc3, &insn->handler) < 0)
6223 return -1;
6224 } else {
6225 if (register_ind_insn(ppc_opcodes, insn->opc1,
6226 insn->opc2, &insn->handler) < 0)
6227 return -1;
6228 }
6229 } else {
6230 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
6231 return -1;
6232 }
6233
6234 return 0;
6235}
6236
6237static int test_opcode_table (opc_handler_t **table, int len)
6238{
6239 int i, count, tmp;
6240
6241 for (i = 0, count = 0; i < len; i++) {
6242 /* Consistency fixup */
6243 if (table[i] == NULL)
6244 table[i] = &invalid_handler;
6245 if (table[i] != &invalid_handler) {
6246 if (is_indirect_opcode(table[i])) {
6247 tmp = test_opcode_table(ind_table(table[i]), 0x20);
6248 if (tmp == 0) {
6249 free(table[i]);
6250 table[i] = &invalid_handler;
6251 } else {
6252 count++;
6253 }
6254 } else {
6255 count++;
6256 }
6257 }
6258 }
6259
6260 return count;
6261}
6262
6263static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6264{
6265 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6266 printf("*** WARNING: no opcode defined !\n");
6267}
6268
6269/*****************************************************************************/
6270static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
6271{
6272 opcode_t *opc, *start, *end;
6273
6274 fill_new_table(env->opcodes, 0x40);
6275 if (&opc_start < &opc_end) {
6276 start = &opc_start;
6277 end = &opc_end;
6278 } else {
6279 start = &opc_end;
6280 end = &opc_start;
6281 }
6282 for (opc = start + 1; opc != end; opc++) {
6283 if ((opc->handler.type & def->insns_flags) != 0) {
6284 if (register_insn(env->opcodes, opc) < 0) {
6285 printf("*** ERROR initializing PowerPC instruction "
6286 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6287 opc->opc3);
6288 return -1;
6289 }
6290 }
6291 }
6292 fix_opcode_tables(env->opcodes);
6293 fflush(stdout);
6294 fflush(stderr);
6295
6296 return 0;
6297}
6298
6299#if defined(PPC_DUMP_CPU)
25ba3a68 6300static void dump_ppc_insns (CPUPPCState *env)
a750fc0b
JM		 6301{
6302 opc_handler_t **table, *handler;
6303 uint8_t opc1, opc2, opc3;
6304
6305 printf("Instructions set:\n");
6306 /* opc1 is 6 bits long */
6307 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6308 table = env->opcodes;
6309 handler = table[opc1];
6310 if (is_indirect_opcode(handler)) {
6311 /* opc2 is 5 bits long */
6312 for (opc2 = 0; opc2 < 0x20; opc2++) {
6313 table = env->opcodes;
6314 handler = env->opcodes[opc1];
6315 table = ind_table(handler);
6316 handler = table[opc2];
6317 if (is_indirect_opcode(handler)) {
6318 table = ind_table(handler);
6319 /* opc3 is 5 bits long */
6320 for (opc3 = 0; opc3 < 0x20; opc3++) {
6321 handler = table[opc3];
6322 if (handler->handler != &gen_invalid) {
6323 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6324 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6325 handler->oname);
6326 }
6327 }
6328 } else {
6329 if (handler->handler != &gen_invalid) {
6330 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6331 opc1, opc2, opc1, opc2, handler->oname);
6332 }
6333 }
6334 }
6335 } else {
6336 if (handler->handler != &gen_invalid) {
6337 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6338 opc1, opc1, handler->oname);
6339 }
6340 }
6341 }
6342}
3a607854 6343#endif
a750fc0b
JM		 6344
6345int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6346{
6347 env->msr_mask = def->msr_mask;
6348 env->mmu_model = def->mmu_model;
6349 env->excp_model = def->excp_model;
6350 env->bus_model = def->bus_model;
d26bfc9a 6351 env->flags = def->flags;
237c0af0 6352 env->bfd_mach = def->bfd_mach;
2f462816 6353 env->check_pow = def->check_pow;
a750fc0b
JM		 6354 if (create_ppc_opcodes(env, def) < 0)
6355 return -1;
6356 init_ppc_proc(env, def);
6357#if defined(PPC_DUMP_CPU)
3a607854 6358 {
a750fc0b
JM		 6359 const unsigned char *mmu_model, *excp_model, *bus_model;
6360 switch (env->mmu_model) {
6361 case POWERPC_MMU_32B:
6362 mmu_model = "PowerPC 32";
6363 break;
a750fc0b
JM		 6364 case POWERPC_MMU_SOFT_6xx:
6365 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6366 break;
6367 case POWERPC_MMU_SOFT_74xx:
6368 mmu_model = "PowerPC 74xx with software driven TLBs";
6369 break;
6370 case POWERPC_MMU_SOFT_4xx:
6371 mmu_model = "PowerPC 4xx with software driven TLBs";
6372 break;
6373 case POWERPC_MMU_SOFT_4xx_Z:
6374 mmu_model = "PowerPC 4xx with software driven TLBs "
6375 "and zones protections";
6376 break;
6377 case POWERPC_MMU_REAL_4xx:
6378 mmu_model = "PowerPC 4xx real mode only";
6379 break;
6380 case POWERPC_MMU_BOOKE:
6381 mmu_model = "PowerPC BookE";
6382 break;
6383 case POWERPC_MMU_BOOKE_FSL:
6384 mmu_model = "PowerPC BookE FSL";
6385 break;
00af685f
JM		 6386#if defined (TARGET_PPC64)
6387 case POWERPC_MMU_64B:
6388 mmu_model = "PowerPC 64";
6389 break;
00af685f 6390#endif
a750fc0b
JM		 6391 default:
6392 mmu_model = "Unknown or invalid";
6393 break;
6394 }
6395 switch (env->excp_model) {
6396 case POWERPC_EXCP_STD:
6397 excp_model = "PowerPC";
6398 break;
6399 case POWERPC_EXCP_40x:
6400 excp_model = "PowerPC 40x";
6401 break;
6402 case POWERPC_EXCP_601:
6403 excp_model = "PowerPC 601";
6404 break;
6405 case POWERPC_EXCP_602:
6406 excp_model = "PowerPC 602";
6407 break;
6408 case POWERPC_EXCP_603:
6409 excp_model = "PowerPC 603";
6410 break;
6411 case POWERPC_EXCP_603E:
6412 excp_model = "PowerPC 603e";
6413 break;
6414 case POWERPC_EXCP_604:
6415 excp_model = "PowerPC 604";
6416 break;
6417 case POWERPC_EXCP_7x0:
6418 excp_model = "PowerPC 740/750";
6419 break;
6420 case POWERPC_EXCP_7x5:
6421 excp_model = "PowerPC 745/755";
6422 break;
6423 case POWERPC_EXCP_74xx:
6424 excp_model = "PowerPC 74xx";
6425 break;
a750fc0b
JM		 6426 case POWERPC_EXCP_BOOKE:
6427 excp_model = "PowerPC BookE";
6428 break;
00af685f
JM		 6429#if defined (TARGET_PPC64)
6430 case POWERPC_EXCP_970:
6431 excp_model = "PowerPC 970";
6432 break;
6433#endif
a750fc0b
JM		 6434 default:
6435 excp_model = "Unknown or invalid";
6436 break;
6437 }
6438 switch (env->bus_model) {
6439 case PPC_FLAGS_INPUT_6xx:
6440 bus_model = "PowerPC 6xx";
6441 break;
6442 case PPC_FLAGS_INPUT_BookE:
6443 bus_model = "PowerPC BookE";
6444 break;
6445 case PPC_FLAGS_INPUT_405:
6446 bus_model = "PowerPC 405";
6447 break;
a750fc0b
JM		 6448 case PPC_FLAGS_INPUT_401:
6449 bus_model = "PowerPC 401/403";
6450 break;
00af685f
JM		 6451#if defined (TARGET_PPC64)
6452 case PPC_FLAGS_INPUT_970:
6453 bus_model = "PowerPC 970";
6454 break;
6455#endif
a750fc0b
JM		 6456 default:
6457 bus_model = "Unknown or invalid";
6458 break;
6459 }
6460 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6461 " MMU model : %s\n",
6462 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 6463#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 6464 if (env->tlb != NULL) {
6465 printf(" %d %s TLB in %d ways\n",
6466 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6467 env->nb_ways);
6468 }
f2e63a42 6469#endif
a750fc0b
JM		 6470 printf(" Exceptions model : %s\n"
6471 " Bus model : %s\n",
6472 excp_model, bus_model);
25ba3a68
JM		 6473 printf(" MSR features :\n");
6474 if (env->flags & POWERPC_FLAG_SPE)
6475 printf(" signal processing engine enable"
6476 "\n");
6477 else if (env->flags & POWERPC_FLAG_VRE)
6478 printf(" vector processor enable\n");
6479 if (env->flags & POWERPC_FLAG_TGPR)
6480 printf(" temporary GPRs\n");
6481 else if (env->flags & POWERPC_FLAG_CE)
6482 printf(" critical input enable\n");
6483 if (env->flags & POWERPC_FLAG_SE)
6484 printf(" single-step trace mode\n");
6485 else if (env->flags & POWERPC_FLAG_DWE)
6486 printf(" debug wait enable\n");
6487 else if (env->flags & POWERPC_FLAG_UBLE)
6488 printf(" user BTB lock enable\n");
6489 if (env->flags & POWERPC_FLAG_BE)
6490 printf(" branch-step trace mode\n");
6491 else if (env->flags & POWERPC_FLAG_DE)
6492 printf(" debug interrupt enable\n");
6493 if (env->flags & POWERPC_FLAG_PX)
6494 printf(" inclusive protection\n");
6495 else if (env->flags & POWERPC_FLAG_PMM)
6496 printf(" performance monitor mark\n");
6497 if (env->flags == POWERPC_FLAG_NONE)
6498 printf(" none\n");
a750fc0b
JM		 6499 }
6500 dump_ppc_insns(env);
6501 dump_ppc_sprs(env);
6502 fflush(stdout);
3a607854 6503#endif
a750fc0b
JM		 6504
6505 return 0;
6506}
3fc6c082
FB		 6507
6508int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
6509{
068abdc8 6510 int i, max, ret;
3fc6c082
FB		 6511
6512 ret = -1;
6513 *def = NULL;
068abdc8
JM		 6514 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6515 for (i = 0; i < max; i++) {
3fc6c082
FB		 6516 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6517 *def = &ppc_defs[i];
6518 ret = 0;
6519 break;
6520 }
6521 }
6522
6523 return ret;
6524}
6525
6526int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
6527{
068abdc8 6528 int i, max, ret;
3fc6c082
FB		 6529
6530 ret = -1;
6531 *def = NULL;
068abdc8
JM		 6532 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6533 for (i = 0; i < max; i++) {
3fc6c082
FB		 6534 if ((pvr & ppc_defs[i].pvr_mask) ==
6535 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
6536 *def = &ppc_defs[i];
6537 ret = 0;
6538 break;
6539 }
6540 }
6541
6542 return ret;
6543}
6544
6545void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6546{
068abdc8 6547 int i, max;
3fc6c082 6548
068abdc8
JM		 6549 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6550 for (i = 0; i < max; i++) {
a750fc0b
JM		 6551 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6552 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 6553 }
6554}
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