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Commit | Line | Data |
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29e4bcb2 AF |
1 | /* |
2 | * QEMU S/390 CPU | |
3 | * | |
1ac1a749 AF |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright (c) 2011 Alexander Graf | |
29e4bcb2 | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
70bada03 | 7 | * Copyright (c) 2012 IBM Corp. |
29e4bcb2 AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
70bada03 JF |
22 | * Contributions after 2012-12-11 are licensed under the terms of the |
23 | * GNU GPL, version 2 or (at your option) any later version. | |
29e4bcb2 AF |
24 | */ |
25 | ||
564b863d | 26 | #include "cpu.h" |
29e4bcb2 | 27 | #include "qemu-common.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
eb24f7c6 | 29 | #include "qemu/error-report.h" |
70bada03 | 30 | #include "hw/hw.h" |
eb24f7c6 | 31 | #include "trace.h" |
c7396bbb | 32 | #ifndef CONFIG_USER_ONLY |
904e5fd5 VM |
33 | #include "sysemu/arch_init.h" |
34 | #endif | |
35 | ||
70bada03 JF |
36 | #define CR0_RESET 0xE0UL |
37 | #define CR14_RESET 0xC2000000UL; | |
38 | ||
904e5fd5 VM |
39 | /* generate CPU information for cpu -? */ |
40 | void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
41 | { | |
42 | #ifdef CONFIG_KVM | |
43 | (*cpu_fprintf)(f, "s390 %16s\n", "host"); | |
44 | #endif | |
45 | } | |
29e4bcb2 | 46 | |
904e5fd5 VM |
47 | #ifndef CONFIG_USER_ONLY |
48 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
49 | { | |
50 | CpuDefinitionInfoList *entry; | |
51 | CpuDefinitionInfo *info; | |
52 | ||
53 | info = g_malloc0(sizeof(*info)); | |
54 | info->name = g_strdup("host"); | |
55 | ||
56 | entry = g_malloc0(sizeof(*entry)); | |
57 | entry->value = info; | |
58 | ||
59 | return entry; | |
60 | } | |
61 | #endif | |
29e4bcb2 | 62 | |
f45748f1 AF |
63 | static void s390_cpu_set_pc(CPUState *cs, vaddr value) |
64 | { | |
65 | S390CPU *cpu = S390_CPU(cs); | |
66 | ||
67 | cpu->env.psw.addr = value; | |
68 | } | |
69 | ||
8c2e1b00 AF |
70 | static bool s390_cpu_has_work(CPUState *cs) |
71 | { | |
72 | S390CPU *cpu = S390_CPU(cs); | |
73 | CPUS390XState *env = &cpu->env; | |
74 | ||
75 | return (cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
76 | (env->psw.mask & PSW_MASK_EXT); | |
77 | } | |
78 | ||
29c6157c CB |
79 | #if !defined(CONFIG_USER_ONLY) |
80 | /* S390CPUClass::load_normal() */ | |
81 | static void s390_cpu_load_normal(CPUState *s) | |
82 | { | |
83 | S390CPU *cpu = S390_CPU(s); | |
fdfba1a2 | 84 | cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR; |
29c6157c | 85 | cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; |
eb24f7c6 | 86 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
29c6157c CB |
87 | } |
88 | #endif | |
89 | ||
f5ae2a4f | 90 | /* S390CPUClass::cpu_reset() */ |
29e4bcb2 AF |
91 | static void s390_cpu_reset(CPUState *s) |
92 | { | |
93 | S390CPU *cpu = S390_CPU(s); | |
94 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
95 | CPUS390XState *env = &cpu->env; | |
96 | ||
819bd309 | 97 | env->pfault_token = -1UL; |
f5ae2a4f | 98 | scc->parent_reset(s); |
18ff9494 | 99 | cpu->env.sigp_order = 0; |
eb24f7c6 | 100 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
00c8cb0a | 101 | tlb_flush(s, 1); |
f5ae2a4f CB |
102 | } |
103 | ||
104 | /* S390CPUClass::initial_reset() */ | |
105 | static void s390_cpu_initial_reset(CPUState *s) | |
106 | { | |
107 | S390CPU *cpu = S390_CPU(s); | |
108 | CPUS390XState *env = &cpu->env; | |
109 | ||
110 | s390_cpu_reset(s); | |
111 | /* initial reset does not touch regs,fregs and aregs */ | |
f0c3c505 | 112 | memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - |
f5ae2a4f CB |
113 | offsetof(CPUS390XState, fpc)); |
114 | ||
115 | /* architectured initial values for CR 0 and 14 */ | |
116 | env->cregs[0] = CR0_RESET; | |
117 | env->cregs[14] = CR14_RESET; | |
819bd309 DD |
118 | |
119 | env->pfault_token = -1UL; | |
7107e5a7 | 120 | env->ext_index = -1; |
49f5c9e9 | 121 | |
4a33565f AJ |
122 | /* tininess for underflow is detected before rounding */ |
123 | set_float_detect_tininess(float_tininess_before_rounding, | |
124 | &env->fpu_status); | |
125 | ||
49f5c9e9 TH |
126 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
127 | if (kvm_enabled()) { | |
99607144 | 128 | kvm_s390_reset_vcpu(cpu); |
49f5c9e9 | 129 | } |
f5ae2a4f CB |
130 | } |
131 | ||
132 | /* CPUClass:reset() */ | |
133 | static void s390_cpu_full_reset(CPUState *s) | |
134 | { | |
135 | S390CPU *cpu = S390_CPU(s); | |
136 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
137 | CPUS390XState *env = &cpu->env; | |
138 | ||
29e4bcb2 | 139 | scc->parent_reset(s); |
18ff9494 | 140 | cpu->env.sigp_order = 0; |
eb24f7c6 | 141 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
29e4bcb2 | 142 | |
f0c3c505 | 143 | memset(env, 0, offsetof(CPUS390XState, cpu_num)); |
70bada03 JF |
144 | |
145 | /* architectured initial values for CR 0 and 14 */ | |
146 | env->cregs[0] = CR0_RESET; | |
147 | env->cregs[14] = CR14_RESET; | |
819bd309 DD |
148 | |
149 | env->pfault_token = -1UL; | |
7107e5a7 | 150 | env->ext_index = -1; |
819bd309 | 151 | |
4a33565f AJ |
152 | /* tininess for underflow is detected before rounding */ |
153 | set_float_detect_tininess(float_tininess_before_rounding, | |
154 | &env->fpu_status); | |
155 | ||
99607144 | 156 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
50a2c6e5 PB |
157 | if (kvm_enabled()) { |
158 | kvm_s390_reset_vcpu(cpu); | |
159 | } | |
00c8cb0a | 160 | tlb_flush(s, 1); |
29e4bcb2 AF |
161 | } |
162 | ||
70bada03 JF |
163 | #if !defined(CONFIG_USER_ONLY) |
164 | static void s390_cpu_machine_reset_cb(void *opaque) | |
165 | { | |
166 | S390CPU *cpu = opaque; | |
167 | ||
1fad8b3b | 168 | run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, CPU(cpu)); |
70bada03 JF |
169 | } |
170 | #endif | |
171 | ||
1f136632 AF |
172 | static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
173 | { | |
14a10fc3 | 174 | CPUState *cs = CPU(dev); |
1f136632 AF |
175 | S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
176 | ||
73d510c9 | 177 | s390_cpu_gdb_init(cs); |
14a10fc3 | 178 | qemu_init_vcpu(cs); |
159855f0 DH |
179 | #if !defined(CONFIG_USER_ONLY) |
180 | run_on_cpu(cs, s390_do_cpu_full_reset, cs); | |
181 | #else | |
14a10fc3 | 182 | cpu_reset(cs); |
159855f0 | 183 | #endif |
1f136632 AF |
184 | |
185 | scc->parent_realize(dev, errp); | |
186 | } | |
187 | ||
8f22e0df AF |
188 | static void s390_cpu_initfn(Object *obj) |
189 | { | |
c05efcb1 | 190 | CPUState *cs = CPU(obj); |
8f22e0df AF |
191 | S390CPU *cpu = S390_CPU(obj); |
192 | CPUS390XState *env = &cpu->env; | |
2b7ac767 | 193 | static bool inited; |
8f22e0df AF |
194 | static int cpu_num = 0; |
195 | #if !defined(CONFIG_USER_ONLY) | |
196 | struct tm tm; | |
197 | #endif | |
198 | ||
c05efcb1 | 199 | cs->env_ptr = env; |
8f22e0df AF |
200 | cpu_exec_init(env); |
201 | #if !defined(CONFIG_USER_ONLY) | |
70bada03 | 202 | qemu_register_reset(s390_cpu_machine_reset_cb, cpu); |
8f22e0df AF |
203 | qemu_get_timedate(&tm, 0); |
204 | env->tod_offset = TOD_UNIX_EPOCH + | |
205 | (time2tod(mktimegm(&tm)) * 1000000000ULL); | |
206 | env->tod_basetime = 0; | |
bc72ad67 AB |
207 | env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); |
208 | env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); | |
eb24f7c6 | 209 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
8f22e0df AF |
210 | #endif |
211 | env->cpu_num = cpu_num++; | |
2b7ac767 AF |
212 | |
213 | if (tcg_enabled() && !inited) { | |
214 | inited = true; | |
215 | s390x_translate_init(); | |
216 | } | |
8f22e0df AF |
217 | } |
218 | ||
d5627ce8 AF |
219 | static void s390_cpu_finalize(Object *obj) |
220 | { | |
221 | #if !defined(CONFIG_USER_ONLY) | |
222 | S390CPU *cpu = S390_CPU(obj); | |
223 | ||
224 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | |
3cda44f7 | 225 | g_free(cpu->irqstate); |
d5627ce8 AF |
226 | #endif |
227 | } | |
228 | ||
75973bfe | 229 | #if !defined(CONFIG_USER_ONLY) |
eb24f7c6 DH |
230 | static bool disabled_wait(CPUState *cpu) |
231 | { | |
232 | return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & | |
233 | (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK)); | |
234 | } | |
235 | ||
75973bfe DH |
236 | static unsigned s390_count_running_cpus(void) |
237 | { | |
238 | CPUState *cpu; | |
239 | int nr_running = 0; | |
240 | ||
241 | CPU_FOREACH(cpu) { | |
242 | uint8_t state = S390_CPU(cpu)->env.cpu_state; | |
243 | if (state == CPU_STATE_OPERATING || | |
244 | state == CPU_STATE_LOAD) { | |
eb24f7c6 DH |
245 | if (!disabled_wait(cpu)) { |
246 | nr_running++; | |
247 | } | |
75973bfe DH |
248 | } |
249 | } | |
250 | ||
251 | return nr_running; | |
252 | } | |
253 | ||
eb24f7c6 | 254 | unsigned int s390_cpu_halt(S390CPU *cpu) |
75973bfe DH |
255 | { |
256 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 257 | trace_cpu_halt(cs->cpu_index); |
75973bfe | 258 | |
eb24f7c6 DH |
259 | if (!cs->halted) { |
260 | cs->halted = 1; | |
261 | cs->exception_index = EXCP_HLT; | |
75973bfe | 262 | } |
eb24f7c6 DH |
263 | |
264 | return s390_count_running_cpus(); | |
75973bfe DH |
265 | } |
266 | ||
eb24f7c6 | 267 | void s390_cpu_unhalt(S390CPU *cpu) |
75973bfe DH |
268 | { |
269 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 270 | trace_cpu_unhalt(cs->cpu_index); |
75973bfe | 271 | |
eb24f7c6 DH |
272 | if (cs->halted) { |
273 | cs->halted = 0; | |
274 | cs->exception_index = -1; | |
275 | } | |
276 | } | |
277 | ||
278 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) | |
279 | { | |
280 | trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state); | |
281 | ||
282 | switch (cpu_state) { | |
283 | case CPU_STATE_STOPPED: | |
284 | case CPU_STATE_CHECK_STOP: | |
285 | /* halt the cpu for common infrastructure */ | |
286 | s390_cpu_halt(cpu); | |
287 | break; | |
288 | case CPU_STATE_OPERATING: | |
289 | case CPU_STATE_LOAD: | |
290 | /* unhalt the cpu for common infrastructure */ | |
291 | s390_cpu_unhalt(cpu); | |
292 | break; | |
293 | default: | |
294 | error_report("Requested CPU state is not a valid S390 CPU state: %u", | |
295 | cpu_state); | |
296 | exit(1); | |
75973bfe | 297 | } |
c9e659c9 DH |
298 | if (kvm_enabled() && cpu->env.cpu_state != cpu_state) { |
299 | kvm_s390_set_cpu_state(cpu, cpu_state); | |
300 | } | |
eb24f7c6 | 301 | cpu->env.cpu_state = cpu_state; |
75973bfe DH |
302 | |
303 | return s390_count_running_cpus(); | |
304 | } | |
305 | #endif | |
306 | ||
29e4bcb2 AF |
307 | static void s390_cpu_class_init(ObjectClass *oc, void *data) |
308 | { | |
309 | S390CPUClass *scc = S390_CPU_CLASS(oc); | |
310 | CPUClass *cc = CPU_CLASS(scc); | |
c7396bbb | 311 | DeviceClass *dc = DEVICE_CLASS(oc); |
29e4bcb2 | 312 | |
1f136632 AF |
313 | scc->parent_realize = dc->realize; |
314 | dc->realize = s390_cpu_realizefn; | |
315 | ||
29e4bcb2 | 316 | scc->parent_reset = cc->reset; |
29c6157c CB |
317 | #if !defined(CONFIG_USER_ONLY) |
318 | scc->load_normal = s390_cpu_load_normal; | |
319 | #endif | |
f5ae2a4f CB |
320 | scc->cpu_reset = s390_cpu_reset; |
321 | scc->initial_cpu_reset = s390_cpu_initial_reset; | |
322 | cc->reset = s390_cpu_full_reset; | |
8c2e1b00 | 323 | cc->has_work = s390_cpu_has_work; |
97a8ea5a | 324 | cc->do_interrupt = s390_cpu_do_interrupt; |
878096ee | 325 | cc->dump_state = s390_cpu_dump_state; |
f45748f1 | 326 | cc->set_pc = s390_cpu_set_pc; |
5b50e790 AF |
327 | cc->gdb_read_register = s390_cpu_gdb_read_register; |
328 | cc->gdb_write_register = s390_cpu_gdb_write_register; | |
7510454e AF |
329 | #ifdef CONFIG_USER_ONLY |
330 | cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; | |
331 | #else | |
00b941e5 | 332 | cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; |
ef1df130 | 333 | cc->vmsd = &vmstate_s390_cpu; |
9b4f38e1 ET |
334 | cc->write_elf64_note = s390_cpu_write_elf64_note; |
335 | cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote; | |
02bb9bbf | 336 | cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; |
00b941e5 | 337 | #endif |
73d510c9 DH |
338 | cc->gdb_num_core_regs = S390_NUM_CORE_REGS; |
339 | cc->gdb_core_xml_file = "s390x-core64.xml"; | |
29e4bcb2 AF |
340 | } |
341 | ||
342 | static const TypeInfo s390_cpu_type_info = { | |
343 | .name = TYPE_S390_CPU, | |
344 | .parent = TYPE_CPU, | |
345 | .instance_size = sizeof(S390CPU), | |
8f22e0df | 346 | .instance_init = s390_cpu_initfn, |
d5627ce8 | 347 | .instance_finalize = s390_cpu_finalize, |
29e4bcb2 AF |
348 | .abstract = false, |
349 | .class_size = sizeof(S390CPUClass), | |
350 | .class_init = s390_cpu_class_init, | |
351 | }; | |
352 | ||
353 | static void s390_cpu_register_types(void) | |
354 | { | |
355 | type_register_static(&s390_cpu_type_info); | |
356 | } | |
357 | ||
358 | type_init(s390_cpu_register_types) |