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Commit | Line | Data |
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29e4bcb2 AF |
1 | /* |
2 | * QEMU S/390 CPU | |
3 | * | |
1ac1a749 AF |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright (c) 2011 Alexander Graf | |
29e4bcb2 | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
70bada03 | 7 | * Copyright (c) 2012 IBM Corp. |
29e4bcb2 AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
70bada03 JF |
22 | * Contributions after 2012-12-11 are licensed under the terms of the |
23 | * GNU GPL, version 2 or (at your option) any later version. | |
29e4bcb2 AF |
24 | */ |
25 | ||
564b863d | 26 | #include "cpu.h" |
29e4bcb2 | 27 | #include "qemu-common.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
eb24f7c6 | 29 | #include "qemu/error-report.h" |
70bada03 | 30 | #include "hw/hw.h" |
eb24f7c6 | 31 | #include "trace.h" |
c7396bbb | 32 | #ifndef CONFIG_USER_ONLY |
904e5fd5 VM |
33 | #include "sysemu/arch_init.h" |
34 | #endif | |
35 | ||
70bada03 JF |
36 | #define CR0_RESET 0xE0UL |
37 | #define CR14_RESET 0xC2000000UL; | |
38 | ||
904e5fd5 VM |
39 | /* generate CPU information for cpu -? */ |
40 | void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
41 | { | |
42 | #ifdef CONFIG_KVM | |
43 | (*cpu_fprintf)(f, "s390 %16s\n", "host"); | |
44 | #endif | |
45 | } | |
29e4bcb2 | 46 | |
904e5fd5 VM |
47 | #ifndef CONFIG_USER_ONLY |
48 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
49 | { | |
50 | CpuDefinitionInfoList *entry; | |
51 | CpuDefinitionInfo *info; | |
52 | ||
53 | info = g_malloc0(sizeof(*info)); | |
54 | info->name = g_strdup("host"); | |
55 | ||
56 | entry = g_malloc0(sizeof(*entry)); | |
57 | entry->value = info; | |
58 | ||
59 | return entry; | |
60 | } | |
61 | #endif | |
29e4bcb2 | 62 | |
f45748f1 AF |
63 | static void s390_cpu_set_pc(CPUState *cs, vaddr value) |
64 | { | |
65 | S390CPU *cpu = S390_CPU(cs); | |
66 | ||
67 | cpu->env.psw.addr = value; | |
68 | } | |
69 | ||
8c2e1b00 AF |
70 | static bool s390_cpu_has_work(CPUState *cs) |
71 | { | |
72 | S390CPU *cpu = S390_CPU(cs); | |
73 | CPUS390XState *env = &cpu->env; | |
74 | ||
75 | return (cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
76 | (env->psw.mask & PSW_MASK_EXT); | |
77 | } | |
78 | ||
29c6157c CB |
79 | #if !defined(CONFIG_USER_ONLY) |
80 | /* S390CPUClass::load_normal() */ | |
81 | static void s390_cpu_load_normal(CPUState *s) | |
82 | { | |
83 | S390CPU *cpu = S390_CPU(s); | |
fdfba1a2 | 84 | cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR; |
29c6157c | 85 | cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; |
eb24f7c6 | 86 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
29c6157c CB |
87 | } |
88 | #endif | |
89 | ||
f5ae2a4f | 90 | /* S390CPUClass::cpu_reset() */ |
29e4bcb2 AF |
91 | static void s390_cpu_reset(CPUState *s) |
92 | { | |
93 | S390CPU *cpu = S390_CPU(s); | |
94 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
95 | CPUS390XState *env = &cpu->env; | |
96 | ||
819bd309 | 97 | env->pfault_token = -1UL; |
f5ae2a4f | 98 | scc->parent_reset(s); |
18ff9494 | 99 | cpu->env.sigp_order = 0; |
eb24f7c6 | 100 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
00c8cb0a | 101 | tlb_flush(s, 1); |
f5ae2a4f CB |
102 | } |
103 | ||
104 | /* S390CPUClass::initial_reset() */ | |
105 | static void s390_cpu_initial_reset(CPUState *s) | |
106 | { | |
107 | S390CPU *cpu = S390_CPU(s); | |
108 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 109 | int i; |
f5ae2a4f CB |
110 | |
111 | s390_cpu_reset(s); | |
112 | /* initial reset does not touch regs,fregs and aregs */ | |
f0c3c505 | 113 | memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - |
f5ae2a4f CB |
114 | offsetof(CPUS390XState, fpc)); |
115 | ||
116 | /* architectured initial values for CR 0 and 14 */ | |
117 | env->cregs[0] = CR0_RESET; | |
118 | env->cregs[14] = CR14_RESET; | |
819bd309 DD |
119 | |
120 | env->pfault_token = -1UL; | |
7107e5a7 | 121 | env->ext_index = -1; |
cc0d079d AJ |
122 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
123 | env->io_index[i] = -1; | |
124 | } | |
49f5c9e9 | 125 | |
4a33565f AJ |
126 | /* tininess for underflow is detected before rounding */ |
127 | set_float_detect_tininess(float_tininess_before_rounding, | |
128 | &env->fpu_status); | |
129 | ||
49f5c9e9 TH |
130 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
131 | if (kvm_enabled()) { | |
99607144 | 132 | kvm_s390_reset_vcpu(cpu); |
49f5c9e9 | 133 | } |
f5ae2a4f CB |
134 | } |
135 | ||
136 | /* CPUClass:reset() */ | |
137 | static void s390_cpu_full_reset(CPUState *s) | |
138 | { | |
139 | S390CPU *cpu = S390_CPU(s); | |
140 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
141 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 142 | int i; |
f5ae2a4f | 143 | |
29e4bcb2 | 144 | scc->parent_reset(s); |
18ff9494 | 145 | cpu->env.sigp_order = 0; |
eb24f7c6 | 146 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
29e4bcb2 | 147 | |
f0c3c505 | 148 | memset(env, 0, offsetof(CPUS390XState, cpu_num)); |
70bada03 JF |
149 | |
150 | /* architectured initial values for CR 0 and 14 */ | |
151 | env->cregs[0] = CR0_RESET; | |
152 | env->cregs[14] = CR14_RESET; | |
819bd309 DD |
153 | |
154 | env->pfault_token = -1UL; | |
7107e5a7 | 155 | env->ext_index = -1; |
cc0d079d AJ |
156 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
157 | env->io_index[i] = -1; | |
158 | } | |
819bd309 | 159 | |
4a33565f AJ |
160 | /* tininess for underflow is detected before rounding */ |
161 | set_float_detect_tininess(float_tininess_before_rounding, | |
162 | &env->fpu_status); | |
163 | ||
99607144 | 164 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
50a2c6e5 PB |
165 | if (kvm_enabled()) { |
166 | kvm_s390_reset_vcpu(cpu); | |
167 | } | |
00c8cb0a | 168 | tlb_flush(s, 1); |
29e4bcb2 AF |
169 | } |
170 | ||
70bada03 JF |
171 | #if !defined(CONFIG_USER_ONLY) |
172 | static void s390_cpu_machine_reset_cb(void *opaque) | |
173 | { | |
174 | S390CPU *cpu = opaque; | |
175 | ||
1fad8b3b | 176 | run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, CPU(cpu)); |
70bada03 JF |
177 | } |
178 | #endif | |
179 | ||
1f136632 AF |
180 | static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
181 | { | |
14a10fc3 | 182 | CPUState *cs = CPU(dev); |
1f136632 AF |
183 | S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
184 | ||
73d510c9 | 185 | s390_cpu_gdb_init(cs); |
14a10fc3 | 186 | qemu_init_vcpu(cs); |
159855f0 DH |
187 | #if !defined(CONFIG_USER_ONLY) |
188 | run_on_cpu(cs, s390_do_cpu_full_reset, cs); | |
189 | #else | |
14a10fc3 | 190 | cpu_reset(cs); |
159855f0 | 191 | #endif |
1f136632 AF |
192 | |
193 | scc->parent_realize(dev, errp); | |
194 | } | |
195 | ||
8f22e0df AF |
196 | static void s390_cpu_initfn(Object *obj) |
197 | { | |
c05efcb1 | 198 | CPUState *cs = CPU(obj); |
8f22e0df AF |
199 | S390CPU *cpu = S390_CPU(obj); |
200 | CPUS390XState *env = &cpu->env; | |
2b7ac767 | 201 | static bool inited; |
8f22e0df AF |
202 | static int cpu_num = 0; |
203 | #if !defined(CONFIG_USER_ONLY) | |
204 | struct tm tm; | |
205 | #endif | |
206 | ||
c05efcb1 | 207 | cs->env_ptr = env; |
8f22e0df AF |
208 | cpu_exec_init(env); |
209 | #if !defined(CONFIG_USER_ONLY) | |
70bada03 | 210 | qemu_register_reset(s390_cpu_machine_reset_cb, cpu); |
8f22e0df AF |
211 | qemu_get_timedate(&tm, 0); |
212 | env->tod_offset = TOD_UNIX_EPOCH + | |
213 | (time2tod(mktimegm(&tm)) * 1000000000ULL); | |
214 | env->tod_basetime = 0; | |
bc72ad67 AB |
215 | env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); |
216 | env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); | |
eb24f7c6 | 217 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
8f22e0df AF |
218 | #endif |
219 | env->cpu_num = cpu_num++; | |
2b7ac767 AF |
220 | |
221 | if (tcg_enabled() && !inited) { | |
222 | inited = true; | |
223 | s390x_translate_init(); | |
224 | } | |
8f22e0df AF |
225 | } |
226 | ||
d5627ce8 AF |
227 | static void s390_cpu_finalize(Object *obj) |
228 | { | |
229 | #if !defined(CONFIG_USER_ONLY) | |
230 | S390CPU *cpu = S390_CPU(obj); | |
231 | ||
232 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | |
3cda44f7 | 233 | g_free(cpu->irqstate); |
d5627ce8 AF |
234 | #endif |
235 | } | |
236 | ||
75973bfe | 237 | #if !defined(CONFIG_USER_ONLY) |
eb24f7c6 DH |
238 | static bool disabled_wait(CPUState *cpu) |
239 | { | |
240 | return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & | |
241 | (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK)); | |
242 | } | |
243 | ||
75973bfe DH |
244 | static unsigned s390_count_running_cpus(void) |
245 | { | |
246 | CPUState *cpu; | |
247 | int nr_running = 0; | |
248 | ||
249 | CPU_FOREACH(cpu) { | |
250 | uint8_t state = S390_CPU(cpu)->env.cpu_state; | |
251 | if (state == CPU_STATE_OPERATING || | |
252 | state == CPU_STATE_LOAD) { | |
eb24f7c6 DH |
253 | if (!disabled_wait(cpu)) { |
254 | nr_running++; | |
255 | } | |
75973bfe DH |
256 | } |
257 | } | |
258 | ||
259 | return nr_running; | |
260 | } | |
261 | ||
eb24f7c6 | 262 | unsigned int s390_cpu_halt(S390CPU *cpu) |
75973bfe DH |
263 | { |
264 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 265 | trace_cpu_halt(cs->cpu_index); |
75973bfe | 266 | |
eb24f7c6 DH |
267 | if (!cs->halted) { |
268 | cs->halted = 1; | |
269 | cs->exception_index = EXCP_HLT; | |
75973bfe | 270 | } |
eb24f7c6 DH |
271 | |
272 | return s390_count_running_cpus(); | |
75973bfe DH |
273 | } |
274 | ||
eb24f7c6 | 275 | void s390_cpu_unhalt(S390CPU *cpu) |
75973bfe DH |
276 | { |
277 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 278 | trace_cpu_unhalt(cs->cpu_index); |
75973bfe | 279 | |
eb24f7c6 DH |
280 | if (cs->halted) { |
281 | cs->halted = 0; | |
282 | cs->exception_index = -1; | |
283 | } | |
284 | } | |
285 | ||
286 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) | |
287 | { | |
288 | trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state); | |
289 | ||
290 | switch (cpu_state) { | |
291 | case CPU_STATE_STOPPED: | |
292 | case CPU_STATE_CHECK_STOP: | |
293 | /* halt the cpu for common infrastructure */ | |
294 | s390_cpu_halt(cpu); | |
295 | break; | |
296 | case CPU_STATE_OPERATING: | |
297 | case CPU_STATE_LOAD: | |
298 | /* unhalt the cpu for common infrastructure */ | |
299 | s390_cpu_unhalt(cpu); | |
300 | break; | |
301 | default: | |
302 | error_report("Requested CPU state is not a valid S390 CPU state: %u", | |
303 | cpu_state); | |
304 | exit(1); | |
75973bfe | 305 | } |
c9e659c9 DH |
306 | if (kvm_enabled() && cpu->env.cpu_state != cpu_state) { |
307 | kvm_s390_set_cpu_state(cpu, cpu_state); | |
308 | } | |
eb24f7c6 | 309 | cpu->env.cpu_state = cpu_state; |
75973bfe DH |
310 | |
311 | return s390_count_running_cpus(); | |
312 | } | |
313 | #endif | |
314 | ||
29e4bcb2 AF |
315 | static void s390_cpu_class_init(ObjectClass *oc, void *data) |
316 | { | |
317 | S390CPUClass *scc = S390_CPU_CLASS(oc); | |
318 | CPUClass *cc = CPU_CLASS(scc); | |
c7396bbb | 319 | DeviceClass *dc = DEVICE_CLASS(oc); |
29e4bcb2 | 320 | |
1f136632 AF |
321 | scc->parent_realize = dc->realize; |
322 | dc->realize = s390_cpu_realizefn; | |
323 | ||
29e4bcb2 | 324 | scc->parent_reset = cc->reset; |
29c6157c CB |
325 | #if !defined(CONFIG_USER_ONLY) |
326 | scc->load_normal = s390_cpu_load_normal; | |
327 | #endif | |
f5ae2a4f CB |
328 | scc->cpu_reset = s390_cpu_reset; |
329 | scc->initial_cpu_reset = s390_cpu_initial_reset; | |
330 | cc->reset = s390_cpu_full_reset; | |
8c2e1b00 | 331 | cc->has_work = s390_cpu_has_work; |
97a8ea5a | 332 | cc->do_interrupt = s390_cpu_do_interrupt; |
878096ee | 333 | cc->dump_state = s390_cpu_dump_state; |
f45748f1 | 334 | cc->set_pc = s390_cpu_set_pc; |
5b50e790 AF |
335 | cc->gdb_read_register = s390_cpu_gdb_read_register; |
336 | cc->gdb_write_register = s390_cpu_gdb_write_register; | |
7510454e AF |
337 | #ifdef CONFIG_USER_ONLY |
338 | cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; | |
339 | #else | |
00b941e5 | 340 | cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; |
ef1df130 | 341 | cc->vmsd = &vmstate_s390_cpu; |
9b4f38e1 ET |
342 | cc->write_elf64_note = s390_cpu_write_elf64_note; |
343 | cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote; | |
02bb9bbf | 344 | cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; |
00b941e5 | 345 | #endif |
73d510c9 DH |
346 | cc->gdb_num_core_regs = S390_NUM_CORE_REGS; |
347 | cc->gdb_core_xml_file = "s390x-core64.xml"; | |
29e4bcb2 AF |
348 | } |
349 | ||
350 | static const TypeInfo s390_cpu_type_info = { | |
351 | .name = TYPE_S390_CPU, | |
352 | .parent = TYPE_CPU, | |
353 | .instance_size = sizeof(S390CPU), | |
8f22e0df | 354 | .instance_init = s390_cpu_initfn, |
d5627ce8 | 355 | .instance_finalize = s390_cpu_finalize, |
29e4bcb2 AF |
356 | .abstract = false, |
357 | .class_size = sizeof(S390CPUClass), | |
358 | .class_init = s390_cpu_class_init, | |
359 | }; | |
360 | ||
361 | static void s390_cpu_register_types(void) | |
362 | { | |
363 | type_register_static(&s390_cpu_type_info); | |
364 | } | |
365 | ||
366 | type_init(s390_cpu_register_types) |