projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 10ec5117 AG |
1 | /* |
| 2 | * S/390 virtual CPU header | |
| 3 | * | |
| 4 | * Copyright (c) 2009 Ulrich Hecht | |
| 5 | * | |
| 6 | * This library is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU Lesser General Public | |
| 8 | * License as published by the Free Software Foundation; either | |
| 9 | * version 2 of the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This library is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | * Lesser General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU Lesser General Public | |
| 70539e18 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 10ec5117 AG |
18 | */ |
| 19 | #ifndef CPU_S390X_H | |
| 20 | #define CPU_S390X_H | |
| 45133b74 SW |
21 | |
| 22 | #include "config.h" | |
| 23 | #include "qemu-common.h" | |
| 10ec5117 AG |
24 | |
| 25 | #define TARGET_LONG_BITS 64 | |
| 26 | ||
| 27 | #define ELF_MACHINE EM_S390 | |
| 28 | ||
| 29 | #define CPUState struct CPUS390XState | |
| 30 | ||
| 31 | #include "cpu-defs.h" | |
| bcec36ea AG |
32 | #define TARGET_PAGE_BITS 12 |
| 33 | ||
| 34 | #define TARGET_PHYS_ADDR_SPACE_BITS 64 | |
| 35 | #define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
| 36 | ||
| 37 | #include "cpu-all.h" | |
| 10ec5117 AG |
38 | |
| 39 | #include "softfloat.h" | |
| 40 | ||
| bcec36ea | 41 | #define NB_MMU_MODES 3 |
| 10ec5117 | 42 | |
| bcec36ea AG |
43 | #define MMU_MODE0_SUFFIX _primary |
| 44 | #define MMU_MODE1_SUFFIX _secondary | |
| 45 | #define MMU_MODE2_SUFFIX _home | |
| 46 | ||
| 47 | #define MMU_USER_IDX 1 | |
| 48 | ||
| 49 | #define MAX_EXT_QUEUE 16 | |
| 50 | ||
| 51 | typedef struct PSW { | |
| 52 | uint64_t mask; | |
| 53 | uint64_t addr; | |
| 54 | } PSW; | |
| 55 | ||
| 56 | typedef struct ExtQueue { | |
| 57 | uint32_t code; | |
| 58 | uint32_t param; | |
| 59 | uint32_t param64; | |
| 60 | } ExtQueue; | |
| 10ec5117 AG |
61 | |
| 62 | typedef struct CPUS390XState { | |
| 63 | uint64_t regs[16]; /* GP registers */ | |
| 64 | ||
| 65 | uint32_t aregs[16]; /* access registers */ | |
| 66 | ||
| 67 | uint32_t fpc; /* floating-point control register */ | |
| bcec36ea | 68 | CPU_DoubleU fregs[16]; /* FP registers */ |
| 10ec5117 AG |
69 | float_status fpu_status; /* passed to softfloat lib */ |
| 70 | ||
| bcec36ea | 71 | PSW psw; |
| 10ec5117 | 72 | |
| bcec36ea AG |
73 | uint32_t cc_op; |
| 74 | uint64_t cc_src; | |
| 75 | uint64_t cc_dst; | |
| 76 | uint64_t cc_vr; | |
| 10ec5117 AG |
77 | |
| 78 | uint64_t __excp_addr; | |
| bcec36ea AG |
79 | uint64_t psa; |
| 80 | ||
| 81 | uint32_t int_pgm_code; | |
| 82 | uint32_t int_pgm_ilc; | |
| 83 | ||
| 84 | uint32_t int_svc_code; | |
| 85 | uint32_t int_svc_ilc; | |
| 86 | ||
| 87 | uint64_t cregs[16]; /* control registers */ | |
| 88 | ||
| 89 | int pending_int; | |
| 90 | ExtQueue ext_queue[MAX_EXT_QUEUE]; | |
| 91 | ||
| 4e836781 AG |
92 | int ext_index; |
| 93 | ||
| 94 | CPU_COMMON | |
| 95 | ||
| bcec36ea AG |
96 | /* reset does memset(0) up to here */ |
| 97 | ||
| bcec36ea AG |
98 | int cpu_num; |
| 99 | uint8_t *storage_keys; | |
| 100 | ||
| 101 | uint64_t tod_offset; | |
| 102 | uint64_t tod_basetime; | |
| 103 | QEMUTimer *tod_timer; | |
| 104 | ||
| 105 | QEMUTimer *cpu_timer; | |
| 10ec5117 AG |
106 | } CPUS390XState; |
| 107 | ||
| 108 | #if defined(CONFIG_USER_ONLY) | |
| 109 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
| 110 | { | |
| bcec36ea | 111 | if (newsp) { |
| 10ec5117 | 112 | env->regs[15] = newsp; |
| bcec36ea | 113 | } |
| 10ec5117 AG |
114 | env->regs[0] = 0; |
| 115 | } | |
| 116 | #endif | |
| 117 | ||
| bcec36ea AG |
118 | /* Interrupt Codes */ |
| 119 | /* Program Interrupts */ | |
| 120 | #define PGM_OPERATION 0x0001 | |
| 121 | #define PGM_PRIVILEGED 0x0002 | |
| 122 | #define PGM_EXECUTE 0x0003 | |
| 123 | #define PGM_PROTECTION 0x0004 | |
| 124 | #define PGM_ADDRESSING 0x0005 | |
| 125 | #define PGM_SPECIFICATION 0x0006 | |
| 126 | #define PGM_DATA 0x0007 | |
| 127 | #define PGM_FIXPT_OVERFLOW 0x0008 | |
| 128 | #define PGM_FIXPT_DIVIDE 0x0009 | |
| 129 | #define PGM_DEC_OVERFLOW 0x000a | |
| 130 | #define PGM_DEC_DIVIDE 0x000b | |
| 131 | #define PGM_HFP_EXP_OVERFLOW 0x000c | |
| 132 | #define PGM_HFP_EXP_UNDERFLOW 0x000d | |
| 133 | #define PGM_HFP_SIGNIFICANCE 0x000e | |
| 134 | #define PGM_HFP_DIVIDE 0x000f | |
| 135 | #define PGM_SEGMENT_TRANS 0x0010 | |
| 136 | #define PGM_PAGE_TRANS 0x0011 | |
| 137 | #define PGM_TRANS_SPEC 0x0012 | |
| 138 | #define PGM_SPECIAL_OP 0x0013 | |
| 139 | #define PGM_OPERAND 0x0015 | |
| 140 | #define PGM_TRACE_TABLE 0x0016 | |
| 141 | #define PGM_SPACE_SWITCH 0x001c | |
| 142 | #define PGM_HFP_SQRT 0x001d | |
| 143 | #define PGM_PC_TRANS_SPEC 0x001f | |
| 144 | #define PGM_AFX_TRANS 0x0020 | |
| 145 | #define PGM_ASX_TRANS 0x0021 | |
| 146 | #define PGM_LX_TRANS 0x0022 | |
| 147 | #define PGM_EX_TRANS 0x0023 | |
| 148 | #define PGM_PRIM_AUTH 0x0024 | |
| 149 | #define PGM_SEC_AUTH 0x0025 | |
| 150 | #define PGM_ALET_SPEC 0x0028 | |
| 151 | #define PGM_ALEN_SPEC 0x0029 | |
| 152 | #define PGM_ALE_SEQ 0x002a | |
| 153 | #define PGM_ASTE_VALID 0x002b | |
| 154 | #define PGM_ASTE_SEQ 0x002c | |
| 155 | #define PGM_EXT_AUTH 0x002d | |
| 156 | #define PGM_STACK_FULL 0x0030 | |
| 157 | #define PGM_STACK_EMPTY 0x0031 | |
| 158 | #define PGM_STACK_SPEC 0x0032 | |
| 159 | #define PGM_STACK_TYPE 0x0033 | |
| 160 | #define PGM_STACK_OP 0x0034 | |
| 161 | #define PGM_ASCE_TYPE 0x0038 | |
| 162 | #define PGM_REG_FIRST_TRANS 0x0039 | |
| 163 | #define PGM_REG_SEC_TRANS 0x003a | |
| 164 | #define PGM_REG_THIRD_TRANS 0x003b | |
| 165 | #define PGM_MONITOR 0x0040 | |
| 166 | #define PGM_PER 0x0080 | |
| 167 | #define PGM_CRYPTO 0x0119 | |
| 168 | ||
| 169 | /* External Interrupts */ | |
| 170 | #define EXT_INTERRUPT_KEY 0x0040 | |
| 171 | #define EXT_CLOCK_COMP 0x1004 | |
| 172 | #define EXT_CPU_TIMER 0x1005 | |
| 173 | #define EXT_MALFUNCTION 0x1200 | |
| 174 | #define EXT_EMERGENCY 0x1201 | |
| 175 | #define EXT_EXTERNAL_CALL 0x1202 | |
| 176 | #define EXT_ETR 0x1406 | |
| 177 | #define EXT_SERVICE 0x2401 | |
| 178 | #define EXT_VIRTIO 0x2603 | |
| 179 | ||
| 180 | /* PSW defines */ | |
| 181 | #undef PSW_MASK_PER | |
| 182 | #undef PSW_MASK_DAT | |
| 183 | #undef PSW_MASK_IO | |
| 184 | #undef PSW_MASK_EXT | |
| 185 | #undef PSW_MASK_KEY | |
| 186 | #undef PSW_SHIFT_KEY | |
| 187 | #undef PSW_MASK_MCHECK | |
| 188 | #undef PSW_MASK_WAIT | |
| 189 | #undef PSW_MASK_PSTATE | |
| 190 | #undef PSW_MASK_ASC | |
| 191 | #undef PSW_MASK_CC | |
| 192 | #undef PSW_MASK_PM | |
| 193 | #undef PSW_MASK_64 | |
| 194 | ||
| 195 | #define PSW_MASK_PER 0x4000000000000000ULL | |
| 196 | #define PSW_MASK_DAT 0x0400000000000000ULL | |
| 197 | #define PSW_MASK_IO 0x0200000000000000ULL | |
| 198 | #define PSW_MASK_EXT 0x0100000000000000ULL | |
| 199 | #define PSW_MASK_KEY 0x00F0000000000000ULL | |
| 200 | #define PSW_SHIFT_KEY 56 | |
| 201 | #define PSW_MASK_MCHECK 0x0004000000000000ULL | |
| 202 | #define PSW_MASK_WAIT 0x0002000000000000ULL | |
| 203 | #define PSW_MASK_PSTATE 0x0001000000000000ULL | |
| 204 | #define PSW_MASK_ASC 0x0000C00000000000ULL | |
| 205 | #define PSW_MASK_CC 0x0000300000000000ULL | |
| 206 | #define PSW_MASK_PM 0x00000F0000000000ULL | |
| 207 | #define PSW_MASK_64 0x0000000100000000ULL | |
| 208 | #define PSW_MASK_32 0x0000000080000000ULL | |
| 209 | ||
| 210 | #undef PSW_ASC_PRIMARY | |
| 211 | #undef PSW_ASC_ACCREG | |
| 212 | #undef PSW_ASC_SECONDARY | |
| 213 | #undef PSW_ASC_HOME | |
| 214 | ||
| 215 | #define PSW_ASC_PRIMARY 0x0000000000000000ULL | |
| 216 | #define PSW_ASC_ACCREG 0x0000400000000000ULL | |
| 217 | #define PSW_ASC_SECONDARY 0x0000800000000000ULL | |
| 218 | #define PSW_ASC_HOME 0x0000C00000000000ULL | |
| 219 | ||
| 220 | /* tb flags */ | |
| 221 | ||
| 222 | #define FLAG_MASK_PER (PSW_MASK_PER >> 32) | |
| 223 | #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32) | |
| 224 | #define FLAG_MASK_IO (PSW_MASK_IO >> 32) | |
| 225 | #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32) | |
| 226 | #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32) | |
| 227 | #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32) | |
| 228 | #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32) | |
| 229 | #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32) | |
| 230 | #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32) | |
| 231 | #define FLAG_MASK_CC (PSW_MASK_CC >> 32) | |
| 232 | #define FLAG_MASK_PM (PSW_MASK_PM >> 32) | |
| 233 | #define FLAG_MASK_64 (PSW_MASK_64 >> 32) | |
| 234 | #define FLAG_MASK_32 0x00001000 | |
| 235 | ||
| 10c339a0 AG |
236 | static inline int cpu_mmu_index (CPUState *env) |
| 237 | { | |
| bcec36ea AG |
238 | if (env->psw.mask & PSW_MASK_PSTATE) { |
| 239 | return 1; | |
| 240 | } | |
| 241 | ||
| 10c339a0 AG |
242 | return 0; |
| 243 | } | |
| 244 | ||
| bcec36ea AG |
245 | static inline void cpu_get_tb_cpu_state(CPUState* env, target_ulong *pc, |
| 246 | target_ulong *cs_base, int *flags) | |
| 247 | { | |
| 248 | *pc = env->psw.addr; | |
| 249 | *cs_base = 0; | |
| 250 | *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) | | |
| 251 | ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0); | |
| 252 | } | |
| 253 | ||
| 254 | static inline int get_ilc(uint8_t opc) | |
| 255 | { | |
| 256 | switch (opc >> 6) { | |
| 257 | case 0: | |
| 258 | return 1; | |
| 259 | case 1: | |
| 260 | case 2: | |
| 261 | return 2; | |
| 262 | case 3: | |
| 263 | return 3; | |
| 264 | } | |
| 265 | ||
| 266 | return 0; | |
| 267 | } | |
| 268 | ||
| 269 | #define ILC_LATER 0x20 | |
| 270 | #define ILC_LATER_INC 0x21 | |
| 271 | #define ILC_LATER_INC_2 0x22 | |
| 272 | ||
| 273 | ||
| 10ec5117 | 274 | CPUS390XState *cpu_s390x_init(const char *cpu_model); |
| bcec36ea | 275 | void s390x_translate_init(void); |
| 10ec5117 AG |
276 | int cpu_s390x_exec(CPUS390XState *s); |
| 277 | void cpu_s390x_close(CPUS390XState *s); | |
| bcec36ea | 278 | void do_interrupt (CPUState *env); |
| 10ec5117 AG |
279 | |
| 280 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
| 281 | signal handlers to inform the virtual CPU of exceptions. non zero | |
| 282 | is returned if the signal was handled by the virtual CPU. */ | |
| 283 | int cpu_s390x_signal_handler(int host_signum, void *pinfo, | |
| 284 | void *puc); | |
| 285 | int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw, | |
| 97b348e7 | 286 | int mmu_idx); |
| 10ec5117 AG |
287 | #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault |
| 288 | ||
| 52705890 | 289 | |
| 10c339a0 | 290 | #ifndef CONFIG_USER_ONLY |
| bcec36ea AG |
291 | int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall); |
| 292 | ||
| 1f206266 | 293 | #ifdef CONFIG_KVM |
| bcec36ea | 294 | void kvm_s390_interrupt(CPUState *env, int type, uint32_t code); |
| 64b85a8f | 295 | void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token); |
| bcec36ea AG |
296 | void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm, |
| 297 | uint64_t parm64, int vm); | |
| 1f206266 AG |
298 | #else |
| 299 | static inline void kvm_s390_interrupt(CPUState *env, int type, uint32_t code) | |
| 300 | { | |
| 301 | } | |
| 302 | ||
| 303 | static inline void kvm_s390_virtio_irq(CPUState *env, int config_change, | |
| 304 | uint64_t token) | |
| 305 | { | |
| 306 | } | |
| 307 | ||
| 308 | static inline void kvm_s390_interrupt_internal(CPUState *env, int type, | |
| 309 | uint32_t parm, uint64_t parm64, | |
| 310 | int vm) | |
| 311 | { | |
| 312 | } | |
| 313 | #endif | |
| 64b85a8f | 314 | CPUState *s390_cpu_addr2state(uint16_t cpu_addr); |
| 854e42f3 CB |
315 | void s390_add_running_cpu(CPUState *env); |
| 316 | unsigned s390_del_running_cpu(CPUState *env); | |
| bcec36ea | 317 | |
| d1ff903c AG |
318 | /* from s390-virtio-bus */ |
| 319 | extern const target_phys_addr_t virtio_size; | |
| 320 | ||
| ef81522b AG |
321 | #else |
| 322 | static inline void s390_add_running_cpu(CPUState *env) | |
| 323 | { | |
| 324 | } | |
| 325 | ||
| 326 | static inline unsigned s390_del_running_cpu(CPUState *env) | |
| 327 | { | |
| 328 | return 0; | |
| 329 | } | |
| 10c339a0 | 330 | #endif |
| bcec36ea AG |
331 | void cpu_lock(void); |
| 332 | void cpu_unlock(void); | |
| 10c339a0 | 333 | |
| bcec36ea AG |
334 | static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls) |
| 335 | { | |
| 336 | env->aregs[0] = newtls >> 32; | |
| 337 | env->aregs[1] = newtls & 0xffffffffULL; | |
| 338 | } | |
| 10c339a0 | 339 | |
| 10ec5117 AG |
340 | #define cpu_init cpu_s390x_init |
| 341 | #define cpu_exec cpu_s390x_exec | |
| 342 | #define cpu_gen_code cpu_s390x_gen_code | |
| bcec36ea | 343 | #define cpu_signal_handler cpu_s390x_signal_handler |
| 10ec5117 | 344 | |
| bcec36ea AG |
345 | #include "exec-all.h" |
| 346 | ||
| 347 | #ifdef CONFIG_USER_ONLY | |
| 10ec5117 AG |
348 | |
| 349 | #define EXCP_OPEX 1 /* operation exception (sigill) */ | |
| 350 | #define EXCP_SVC 2 /* supervisor call (syscall) */ | |
| 351 | #define EXCP_ADDR 5 /* addressing exception */ | |
| bcec36ea | 352 | #define EXCP_SPEC 6 /* specification exception */ |
| 10ec5117 | 353 | |
| bcec36ea AG |
354 | #else |
| 355 | ||
| 356 | #define EXCP_EXT 1 /* external interrupt */ | |
| 357 | #define EXCP_SVC 2 /* supervisor call (syscall) */ | |
| 358 | #define EXCP_PGM 3 /* program interruption */ | |
| 359 | ||
| 360 | #endif /* CONFIG_USER_ONLY */ | |
| 361 | ||
| 362 | #define INTERRUPT_EXT (1 << 0) | |
| 363 | #define INTERRUPT_TOD (1 << 1) | |
| 364 | #define INTERRUPT_CPUTIMER (1 << 2) | |
| 10c339a0 AG |
365 | |
| 366 | /* Program Status Word. */ | |
| 367 | #define S390_PSWM_REGNUM 0 | |
| 368 | #define S390_PSWA_REGNUM 1 | |
| 369 | /* General Purpose Registers. */ | |
| 370 | #define S390_R0_REGNUM 2 | |
| 371 | #define S390_R1_REGNUM 3 | |
| 372 | #define S390_R2_REGNUM 4 | |
| 373 | #define S390_R3_REGNUM 5 | |
| 374 | #define S390_R4_REGNUM 6 | |
| 375 | #define S390_R5_REGNUM 7 | |
| 376 | #define S390_R6_REGNUM 8 | |
| 377 | #define S390_R7_REGNUM 9 | |
| 378 | #define S390_R8_REGNUM 10 | |
| 379 | #define S390_R9_REGNUM 11 | |
| 380 | #define S390_R10_REGNUM 12 | |
| 381 | #define S390_R11_REGNUM 13 | |
| 382 | #define S390_R12_REGNUM 14 | |
| 383 | #define S390_R13_REGNUM 15 | |
| 384 | #define S390_R14_REGNUM 16 | |
| 385 | #define S390_R15_REGNUM 17 | |
| 386 | /* Access Registers. */ | |
| 387 | #define S390_A0_REGNUM 18 | |
| 388 | #define S390_A1_REGNUM 19 | |
| 389 | #define S390_A2_REGNUM 20 | |
| 390 | #define S390_A3_REGNUM 21 | |
| 391 | #define S390_A4_REGNUM 22 | |
| 392 | #define S390_A5_REGNUM 23 | |
| 393 | #define S390_A6_REGNUM 24 | |
| 394 | #define S390_A7_REGNUM 25 | |
| 395 | #define S390_A8_REGNUM 26 | |
| 396 | #define S390_A9_REGNUM 27 | |
| 397 | #define S390_A10_REGNUM 28 | |
| 398 | #define S390_A11_REGNUM 29 | |
| 399 | #define S390_A12_REGNUM 30 | |
| 400 | #define S390_A13_REGNUM 31 | |
| 401 | #define S390_A14_REGNUM 32 | |
| 402 | #define S390_A15_REGNUM 33 | |
| 403 | /* Floating Point Control Word. */ | |
| 404 | #define S390_FPC_REGNUM 34 | |
| 405 | /* Floating Point Registers. */ | |
| 406 | #define S390_F0_REGNUM 35 | |
| 407 | #define S390_F1_REGNUM 36 | |
| 408 | #define S390_F2_REGNUM 37 | |
| 409 | #define S390_F3_REGNUM 38 | |
| 410 | #define S390_F4_REGNUM 39 | |
| 411 | #define S390_F5_REGNUM 40 | |
| 412 | #define S390_F6_REGNUM 41 | |
| 413 | #define S390_F7_REGNUM 42 | |
| 414 | #define S390_F8_REGNUM 43 | |
| 415 | #define S390_F9_REGNUM 44 | |
| 416 | #define S390_F10_REGNUM 45 | |
| 417 | #define S390_F11_REGNUM 46 | |
| 418 | #define S390_F12_REGNUM 47 | |
| 419 | #define S390_F13_REGNUM 48 | |
| 420 | #define S390_F14_REGNUM 49 | |
| 421 | #define S390_F15_REGNUM 50 | |
| 422 | /* Total. */ | |
| 423 | #define S390_NUM_REGS 51 | |
| 424 | ||
| 425 | /* Pseudo registers -- PC and condition code. */ | |
| 426 | #define S390_PC_REGNUM S390_NUM_REGS | |
| 427 | #define S390_CC_REGNUM (S390_NUM_REGS+1) | |
| 428 | #define S390_NUM_PSEUDO_REGS 2 | |
| 429 | #define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2) | |
| 430 | ||
| 431 | ||
| 432 | ||
| 433 | /* Program Status Word. */ | |
| 434 | #define S390_PSWM_REGNUM 0 | |
| 435 | #define S390_PSWA_REGNUM 1 | |
| 436 | /* General Purpose Registers. */ | |
| 437 | #define S390_R0_REGNUM 2 | |
| 438 | #define S390_R1_REGNUM 3 | |
| 439 | #define S390_R2_REGNUM 4 | |
| 440 | #define S390_R3_REGNUM 5 | |
| 441 | #define S390_R4_REGNUM 6 | |
| 442 | #define S390_R5_REGNUM 7 | |
| 443 | #define S390_R6_REGNUM 8 | |
| 444 | #define S390_R7_REGNUM 9 | |
| 445 | #define S390_R8_REGNUM 10 | |
| 446 | #define S390_R9_REGNUM 11 | |
| 447 | #define S390_R10_REGNUM 12 | |
| 448 | #define S390_R11_REGNUM 13 | |
| 449 | #define S390_R12_REGNUM 14 | |
| 450 | #define S390_R13_REGNUM 15 | |
| 451 | #define S390_R14_REGNUM 16 | |
| 452 | #define S390_R15_REGNUM 17 | |
| 453 | /* Access Registers. */ | |
| 454 | #define S390_A0_REGNUM 18 | |
| 455 | #define S390_A1_REGNUM 19 | |
| 456 | #define S390_A2_REGNUM 20 | |
| 457 | #define S390_A3_REGNUM 21 | |
| 458 | #define S390_A4_REGNUM 22 | |
| 459 | #define S390_A5_REGNUM 23 | |
| 460 | #define S390_A6_REGNUM 24 | |
| 461 | #define S390_A7_REGNUM 25 | |
| 462 | #define S390_A8_REGNUM 26 | |
| 463 | #define S390_A9_REGNUM 27 | |
| 464 | #define S390_A10_REGNUM 28 | |
| 465 | #define S390_A11_REGNUM 29 | |
| 466 | #define S390_A12_REGNUM 30 | |
| 467 | #define S390_A13_REGNUM 31 | |
| 468 | #define S390_A14_REGNUM 32 | |
| 469 | #define S390_A15_REGNUM 33 | |
| 470 | /* Floating Point Control Word. */ | |
| 471 | #define S390_FPC_REGNUM 34 | |
| 472 | /* Floating Point Registers. */ | |
| 473 | #define S390_F0_REGNUM 35 | |
| 474 | #define S390_F1_REGNUM 36 | |
| 475 | #define S390_F2_REGNUM 37 | |
| 476 | #define S390_F3_REGNUM 38 | |
| 477 | #define S390_F4_REGNUM 39 | |
| 478 | #define S390_F5_REGNUM 40 | |
| 479 | #define S390_F6_REGNUM 41 | |
| 480 | #define S390_F7_REGNUM 42 | |
| 481 | #define S390_F8_REGNUM 43 | |
| 482 | #define S390_F9_REGNUM 44 | |
| 483 | #define S390_F10_REGNUM 45 | |
| 484 | #define S390_F11_REGNUM 46 | |
| 485 | #define S390_F12_REGNUM 47 | |
| 486 | #define S390_F13_REGNUM 48 | |
| 487 | #define S390_F14_REGNUM 49 | |
| 488 | #define S390_F15_REGNUM 50 | |
| 489 | /* Total. */ | |
| 490 | #define S390_NUM_REGS 51 | |
| 491 | ||
| 492 | /* Pseudo registers -- PC and condition code. */ | |
| 493 | #define S390_PC_REGNUM S390_NUM_REGS | |
| 494 | #define S390_CC_REGNUM (S390_NUM_REGS+1) | |
| 495 | #define S390_NUM_PSEUDO_REGS 2 | |
| 496 | #define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2) | |
| 497 | ||
| bcec36ea AG |
498 | /* CC optimization */ |
| 499 | ||
| 500 | enum cc_op { | |
| 501 | CC_OP_CONST0 = 0, /* CC is 0 */ | |
| 502 | CC_OP_CONST1, /* CC is 1 */ | |
| 503 | CC_OP_CONST2, /* CC is 2 */ | |
| 504 | CC_OP_CONST3, /* CC is 3 */ | |
| 505 | ||
| 506 | CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */ | |
| 507 | CC_OP_STATIC, /* CC value is env->cc_op */ | |
| 508 | ||
| 509 | CC_OP_NZ, /* env->cc_dst != 0 */ | |
| 510 | CC_OP_LTGT_32, /* signed less/greater than (32bit) */ | |
| 511 | CC_OP_LTGT_64, /* signed less/greater than (64bit) */ | |
| 512 | CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */ | |
| 513 | CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */ | |
| 514 | CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */ | |
| 515 | CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */ | |
| 516 | ||
| 517 | CC_OP_ADD_64, /* overflow on add (64bit) */ | |
| 518 | CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */ | |
| e7d81004 SW |
519 | CC_OP_SUB_64, /* overflow on subtraction (64bit) */ |
| 520 | CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */ | |
| bcec36ea AG |
521 | CC_OP_ABS_64, /* sign eval on abs (64bit) */ |
| 522 | CC_OP_NABS_64, /* sign eval on nabs (64bit) */ | |
| 523 | ||
| 524 | CC_OP_ADD_32, /* overflow on add (32bit) */ | |
| 525 | CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */ | |
| e7d81004 SW |
526 | CC_OP_SUB_32, /* overflow on subtraction (32bit) */ |
| 527 | CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */ | |
| bcec36ea AG |
528 | CC_OP_ABS_32, /* sign eval on abs (64bit) */ |
| 529 | CC_OP_NABS_32, /* sign eval on nabs (64bit) */ | |
| 530 | ||
| 531 | CC_OP_COMP_32, /* complement */ | |
| 532 | CC_OP_COMP_64, /* complement */ | |
| 533 | ||
| 534 | CC_OP_TM_32, /* test under mask (32bit) */ | |
| 535 | CC_OP_TM_64, /* test under mask (64bit) */ | |
| 536 | ||
| 537 | CC_OP_LTGT_F32, /* FP compare (32bit) */ | |
| 538 | CC_OP_LTGT_F64, /* FP compare (64bit) */ | |
| 539 | ||
| 540 | CC_OP_NZ_F32, /* FP dst != 0 (32bit) */ | |
| 541 | CC_OP_NZ_F64, /* FP dst != 0 (64bit) */ | |
| 542 | ||
| 543 | CC_OP_ICM, /* insert characters under mask */ | |
| 544 | CC_OP_SLAG, /* Calculate shift left signed */ | |
| 545 | CC_OP_MAX | |
| 546 | }; | |
| 547 | ||
| 548 | static const char *cc_names[] = { | |
| 549 | [CC_OP_CONST0] = "CC_OP_CONST0", | |
| 550 | [CC_OP_CONST1] = "CC_OP_CONST1", | |
| 551 | [CC_OP_CONST2] = "CC_OP_CONST2", | |
| 552 | [CC_OP_CONST3] = "CC_OP_CONST3", | |
| 553 | [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC", | |
| 554 | [CC_OP_STATIC] = "CC_OP_STATIC", | |
| 555 | [CC_OP_NZ] = "CC_OP_NZ", | |
| 556 | [CC_OP_LTGT_32] = "CC_OP_LTGT_32", | |
| 557 | [CC_OP_LTGT_64] = "CC_OP_LTGT_64", | |
| 558 | [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32", | |
| 559 | [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64", | |
| 560 | [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32", | |
| 561 | [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64", | |
| 562 | [CC_OP_ADD_64] = "CC_OP_ADD_64", | |
| 563 | [CC_OP_ADDU_64] = "CC_OP_ADDU_64", | |
| 564 | [CC_OP_SUB_64] = "CC_OP_SUB_64", | |
| 565 | [CC_OP_SUBU_64] = "CC_OP_SUBU_64", | |
| 566 | [CC_OP_ABS_64] = "CC_OP_ABS_64", | |
| 567 | [CC_OP_NABS_64] = "CC_OP_NABS_64", | |
| 568 | [CC_OP_ADD_32] = "CC_OP_ADD_32", | |
| 569 | [CC_OP_ADDU_32] = "CC_OP_ADDU_32", | |
| 570 | [CC_OP_SUB_32] = "CC_OP_SUB_32", | |
| 571 | [CC_OP_SUBU_32] = "CC_OP_SUBU_32", | |
| 572 | [CC_OP_ABS_32] = "CC_OP_ABS_32", | |
| 573 | [CC_OP_NABS_32] = "CC_OP_NABS_32", | |
| 574 | [CC_OP_COMP_32] = "CC_OP_COMP_32", | |
| 575 | [CC_OP_COMP_64] = "CC_OP_COMP_64", | |
| 576 | [CC_OP_TM_32] = "CC_OP_TM_32", | |
| 577 | [CC_OP_TM_64] = "CC_OP_TM_64", | |
| 578 | [CC_OP_LTGT_F32] = "CC_OP_LTGT_F32", | |
| 579 | [CC_OP_LTGT_F64] = "CC_OP_LTGT_F64", | |
| 580 | [CC_OP_NZ_F32] = "CC_OP_NZ_F32", | |
| 581 | [CC_OP_NZ_F64] = "CC_OP_NZ_F64", | |
| 582 | [CC_OP_ICM] = "CC_OP_ICM", | |
| 583 | [CC_OP_SLAG] = "CC_OP_SLAG", | |
| 584 | }; | |
| 585 | ||
| 586 | static inline const char *cc_name(int cc_op) | |
| 587 | { | |
| 588 | return cc_names[cc_op]; | |
| 589 | } | |
| 590 | ||
| 591 | /* SCLP PV interface defines */ | |
| 592 | #define SCLP_CMDW_READ_SCP_INFO 0x00020001 | |
| 593 | #define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001 | |
| 594 | ||
| 595 | #define SCP_LENGTH 0x00 | |
| 596 | #define SCP_FUNCTION_CODE 0x02 | |
| 597 | #define SCP_CONTROL_MASK 0x03 | |
| 598 | #define SCP_RESPONSE_CODE 0x06 | |
| 599 | #define SCP_MEM_CODE 0x08 | |
| 600 | #define SCP_INCREMENT 0x0a | |
| 601 | ||
| 602 | typedef struct LowCore | |
| 603 | { | |
| 604 | /* prefix area: defined by architecture */ | |
| 605 | uint32_t ccw1[2]; /* 0x000 */ | |
| 606 | uint32_t ccw2[4]; /* 0x008 */ | |
| 607 | uint8_t pad1[0x80-0x18]; /* 0x018 */ | |
| 608 | uint32_t ext_params; /* 0x080 */ | |
| 609 | uint16_t cpu_addr; /* 0x084 */ | |
| 610 | uint16_t ext_int_code; /* 0x086 */ | |
| 611 | uint16_t svc_ilc; /* 0x088 */ | |
| 612 | uint16_t svc_code; /* 0x08a */ | |
| 613 | uint16_t pgm_ilc; /* 0x08c */ | |
| 614 | uint16_t pgm_code; /* 0x08e */ | |
| 615 | uint32_t data_exc_code; /* 0x090 */ | |
| 616 | uint16_t mon_class_num; /* 0x094 */ | |
| 617 | uint16_t per_perc_atmid; /* 0x096 */ | |
| 618 | uint64_t per_address; /* 0x098 */ | |
| 619 | uint8_t exc_access_id; /* 0x0a0 */ | |
| 620 | uint8_t per_access_id; /* 0x0a1 */ | |
| 621 | uint8_t op_access_id; /* 0x0a2 */ | |
| 622 | uint8_t ar_access_id; /* 0x0a3 */ | |
| 623 | uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */ | |
| 624 | uint64_t trans_exc_code; /* 0x0a8 */ | |
| 625 | uint64_t monitor_code; /* 0x0b0 */ | |
| 626 | uint16_t subchannel_id; /* 0x0b8 */ | |
| 627 | uint16_t subchannel_nr; /* 0x0ba */ | |
| 628 | uint32_t io_int_parm; /* 0x0bc */ | |
| 629 | uint32_t io_int_word; /* 0x0c0 */ | |
| 630 | uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */ | |
| 631 | uint32_t stfl_fac_list; /* 0x0c8 */ | |
| 632 | uint8_t pad4[0xe8-0xcc]; /* 0x0cc */ | |
| 633 | uint32_t mcck_interruption_code[2]; /* 0x0e8 */ | |
| 634 | uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */ | |
| 635 | uint32_t external_damage_code; /* 0x0f4 */ | |
| 636 | uint64_t failing_storage_address; /* 0x0f8 */ | |
| 637 | uint8_t pad6[0x120-0x100]; /* 0x100 */ | |
| 638 | PSW restart_old_psw; /* 0x120 */ | |
| 639 | PSW external_old_psw; /* 0x130 */ | |
| 640 | PSW svc_old_psw; /* 0x140 */ | |
| 641 | PSW program_old_psw; /* 0x150 */ | |
| 642 | PSW mcck_old_psw; /* 0x160 */ | |
| 643 | PSW io_old_psw; /* 0x170 */ | |
| 644 | uint8_t pad7[0x1a0-0x180]; /* 0x180 */ | |
| 645 | PSW restart_psw; /* 0x1a0 */ | |
| 646 | PSW external_new_psw; /* 0x1b0 */ | |
| 647 | PSW svc_new_psw; /* 0x1c0 */ | |
| 648 | PSW program_new_psw; /* 0x1d0 */ | |
| 649 | PSW mcck_new_psw; /* 0x1e0 */ | |
| 650 | PSW io_new_psw; /* 0x1f0 */ | |
| 651 | PSW return_psw; /* 0x200 */ | |
| 652 | uint8_t irb[64]; /* 0x210 */ | |
| 653 | uint64_t sync_enter_timer; /* 0x250 */ | |
| 654 | uint64_t async_enter_timer; /* 0x258 */ | |
| 655 | uint64_t exit_timer; /* 0x260 */ | |
| 656 | uint64_t last_update_timer; /* 0x268 */ | |
| 657 | uint64_t user_timer; /* 0x270 */ | |
| 658 | uint64_t system_timer; /* 0x278 */ | |
| 659 | uint64_t last_update_clock; /* 0x280 */ | |
| 660 | uint64_t steal_clock; /* 0x288 */ | |
| 661 | PSW return_mcck_psw; /* 0x290 */ | |
| 662 | uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */ | |
| 663 | /* System info area */ | |
| 664 | uint64_t save_area[16]; /* 0xc00 */ | |
| 665 | uint8_t pad9[0xd40-0xc80]; /* 0xc80 */ | |
| 666 | uint64_t kernel_stack; /* 0xd40 */ | |
| 667 | uint64_t thread_info; /* 0xd48 */ | |
| 668 | uint64_t async_stack; /* 0xd50 */ | |
| 669 | uint64_t kernel_asce; /* 0xd58 */ | |
| 670 | uint64_t user_asce; /* 0xd60 */ | |
| 671 | uint64_t panic_stack; /* 0xd68 */ | |
| 672 | uint64_t user_exec_asce; /* 0xd70 */ | |
| 673 | uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */ | |
| 674 | ||
| 675 | /* SMP info area: defined by DJB */ | |
| 676 | uint64_t clock_comparator; /* 0xdc0 */ | |
| 677 | uint64_t ext_call_fast; /* 0xdc8 */ | |
| 678 | uint64_t percpu_offset; /* 0xdd0 */ | |
| 679 | uint64_t current_task; /* 0xdd8 */ | |
| 680 | uint32_t softirq_pending; /* 0xde0 */ | |
| 681 | uint32_t pad_0x0de4; /* 0xde4 */ | |
| 682 | uint64_t int_clock; /* 0xde8 */ | |
| 683 | uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */ | |
| 684 | ||
| 685 | /* 0xe00 is used as indicator for dump tools */ | |
| 686 | /* whether the kernel died with panic() or not */ | |
| 687 | uint32_t panic_magic; /* 0xe00 */ | |
| 688 | ||
| 689 | uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */ | |
| 690 | ||
| 691 | /* 64 bit extparam used for pfault, diag 250 etc */ | |
| 692 | uint64_t ext_params2; /* 0x11B8 */ | |
| 693 | ||
| 694 | uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */ | |
| 695 | ||
| 696 | /* System info area */ | |
| 697 | ||
| 698 | uint64_t floating_pt_save_area[16]; /* 0x1200 */ | |
| 699 | uint64_t gpregs_save_area[16]; /* 0x1280 */ | |
| 700 | uint32_t st_status_fixed_logout[4]; /* 0x1300 */ | |
| 701 | uint8_t pad15[0x1318-0x1310]; /* 0x1310 */ | |
| 702 | uint32_t prefixreg_save_area; /* 0x1318 */ | |
| 703 | uint32_t fpt_creg_save_area; /* 0x131c */ | |
| 704 | uint8_t pad16[0x1324-0x1320]; /* 0x1320 */ | |
| 705 | uint32_t tod_progreg_save_area; /* 0x1324 */ | |
| 706 | uint32_t cpu_timer_save_area[2]; /* 0x1328 */ | |
| 707 | uint32_t clock_comp_save_area[2]; /* 0x1330 */ | |
| 708 | uint8_t pad17[0x1340-0x1338]; /* 0x1338 */ | |
| 709 | uint32_t access_regs_save_area[16]; /* 0x1340 */ | |
| 710 | uint64_t cregs_save_area[16]; /* 0x1380 */ | |
| 711 | ||
| 712 | /* align to the top of the prefix area */ | |
| 713 | ||
| 714 | uint8_t pad18[0x2000-0x1400]; /* 0x1400 */ | |
| 541dc0d4 | 715 | } QEMU_PACKED LowCore; |
| bcec36ea AG |
716 | |
| 717 | /* STSI */ | |
| 718 | #define STSI_LEVEL_MASK 0x00000000f0000000ULL | |
| 719 | #define STSI_LEVEL_CURRENT 0x0000000000000000ULL | |
| 720 | #define STSI_LEVEL_1 0x0000000010000000ULL | |
| 721 | #define STSI_LEVEL_2 0x0000000020000000ULL | |
| 722 | #define STSI_LEVEL_3 0x0000000030000000ULL | |
| 723 | #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL | |
| 724 | #define STSI_R0_SEL1_MASK 0x00000000000000ffULL | |
| 725 | #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL | |
| 726 | #define STSI_R1_SEL2_MASK 0x000000000000ffffULL | |
| 727 | ||
| 728 | /* Basic Machine Configuration */ | |
| 729 | struct sysib_111 { | |
| 730 | uint32_t res1[8]; | |
| 731 | uint8_t manuf[16]; | |
| 732 | uint8_t type[4]; | |
| 733 | uint8_t res2[12]; | |
| 734 | uint8_t model[16]; | |
| 735 | uint8_t sequence[16]; | |
| 736 | uint8_t plant[4]; | |
| 737 | uint8_t res3[156]; | |
| 738 | }; | |
| 739 | ||
| 740 | /* Basic Machine CPU */ | |
| 741 | struct sysib_121 { | |
| 742 | uint32_t res1[80]; | |
| 743 | uint8_t sequence[16]; | |
| 744 | uint8_t plant[4]; | |
| 745 | uint8_t res2[2]; | |
| 746 | uint16_t cpu_addr; | |
| 747 | uint8_t res3[152]; | |
| 748 | }; | |
| 749 | ||
| 750 | /* Basic Machine CPUs */ | |
| 751 | struct sysib_122 { | |
| 752 | uint8_t res1[32]; | |
| 753 | uint32_t capability; | |
| 754 | uint16_t total_cpus; | |
| 755 | uint16_t active_cpus; | |
| 756 | uint16_t standby_cpus; | |
| 757 | uint16_t reserved_cpus; | |
| 758 | uint16_t adjustments[2026]; | |
| 759 | }; | |
| 760 | ||
| 761 | /* LPAR CPU */ | |
| 762 | struct sysib_221 { | |
| 763 | uint32_t res1[80]; | |
| 764 | uint8_t sequence[16]; | |
| 765 | uint8_t plant[4]; | |
| 766 | uint16_t cpu_id; | |
| 767 | uint16_t cpu_addr; | |
| 768 | uint8_t res3[152]; | |
| 769 | }; | |
| 770 | ||
| 771 | /* LPAR CPUs */ | |
| 772 | struct sysib_222 { | |
| 773 | uint32_t res1[32]; | |
| 774 | uint16_t lpar_num; | |
| 775 | uint8_t res2; | |
| 776 | uint8_t lcpuc; | |
| 777 | uint16_t total_cpus; | |
| 778 | uint16_t conf_cpus; | |
| 779 | uint16_t standby_cpus; | |
| 780 | uint16_t reserved_cpus; | |
| 781 | uint8_t name[8]; | |
| 782 | uint32_t caf; | |
| 783 | uint8_t res3[16]; | |
| 784 | uint16_t dedicated_cpus; | |
| 785 | uint16_t shared_cpus; | |
| 786 | uint8_t res4[180]; | |
| 787 | }; | |
| 788 | ||
| 789 | /* VM CPUs */ | |
| 790 | struct sysib_322 { | |
| 791 | uint8_t res1[31]; | |
| 792 | uint8_t count; | |
| 793 | struct { | |
| 794 | uint8_t res2[4]; | |
| 795 | uint16_t total_cpus; | |
| 796 | uint16_t conf_cpus; | |
| 797 | uint16_t standby_cpus; | |
| 798 | uint16_t reserved_cpus; | |
| 799 | uint8_t name[8]; | |
| 800 | uint32_t caf; | |
| 801 | uint8_t cpi[16]; | |
| 802 | uint8_t res3[24]; | |
| 803 | } vm[8]; | |
| 804 | uint8_t res4[3552]; | |
| 805 | }; | |
| 806 | ||
| 807 | /* MMU defines */ | |
| 808 | #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ | |
| 809 | #define _ASCE_SUBSPACE 0x200 /* subspace group control */ | |
| 810 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
| 811 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
| 812 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
| 813 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
| 814 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
| 815 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
| 816 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
| 817 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
| 818 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
| 819 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
| 820 | ||
| 821 | #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ | |
| 822 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ | |
| 823 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
| 824 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
| 825 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
| 826 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
| 827 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
| 828 | ||
| 829 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ | |
| 830 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
| 831 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
| 832 | ||
| 833 | #define _PAGE_RO 0x200 /* HW read-only bit */ | |
| 834 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
| 835 | ||
| b9959138 AG |
836 | #define SK_C (0x1 << 1) |
| 837 | #define SK_R (0x1 << 2) | |
| 838 | #define SK_F (0x1 << 3) | |
| 839 | #define SK_ACC_MASK (0xf << 4) | |
| bcec36ea AG |
840 | |
| 841 | ||
| 842 | /* EBCDIC handling */ | |
| 843 | static const uint8_t ebcdic2ascii[] = { | |
| 844 | 0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F, | |
| 845 | 0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, | |
| 846 | 0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07, | |
| 847 | 0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
| 848 | 0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B, | |
| 849 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07, | |
| 850 | 0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04, | |
| 851 | 0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A, | |
| 852 | 0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86, | |
| 853 | 0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21, | |
| 854 | 0x26, 0x82, 0x88, 0x89, 0x8A, 0xA1, 0x8C, 0x07, | |
| 855 | 0x8D, 0xE1, 0x5D, 0x24, 0x2A, 0x29, 0x3B, 0x5E, | |
| 856 | 0x2D, 0x2F, 0x07, 0x8E, 0x07, 0x07, 0x07, 0x8F, | |
| 857 | 0x80, 0xA5, 0x07, 0x2C, 0x25, 0x5F, 0x3E, 0x3F, | |
| 858 | 0x07, 0x90, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
| 859 | 0x70, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22, | |
| 860 | 0x07, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, | |
| 861 | 0x68, 0x69, 0xAE, 0xAF, 0x07, 0x07, 0x07, 0xF1, | |
| 862 | 0xF8, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, | |
| 863 | 0x71, 0x72, 0xA6, 0xA7, 0x91, 0x07, 0x92, 0x07, | |
| 864 | 0xE6, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, | |
| 865 | 0x79, 0x7A, 0xAD, 0xAB, 0x07, 0x07, 0x07, 0x07, | |
| 866 | 0x9B, 0x9C, 0x9D, 0xFA, 0x07, 0x07, 0x07, 0xAC, | |
| 867 | 0xAB, 0x07, 0xAA, 0x7C, 0x07, 0x07, 0x07, 0x07, | |
| 868 | 0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, | |
| 869 | 0x48, 0x49, 0x07, 0x93, 0x94, 0x95, 0xA2, 0x07, | |
| 870 | 0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, | |
| 871 | 0x51, 0x52, 0x07, 0x96, 0x81, 0x97, 0xA3, 0x98, | |
| 872 | 0x5C, 0xF6, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, | |
| 873 | 0x59, 0x5A, 0xFD, 0x07, 0x99, 0x07, 0x07, 0x07, | |
| 874 | 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, | |
| 875 | 0x38, 0x39, 0x07, 0x07, 0x9A, 0x07, 0x07, 0x07, | |
| 876 | }; | |
| 877 | ||
| 878 | static const uint8_t ascii2ebcdic [] = { | |
| 879 | 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F, | |
| 880 | 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, | |
| 881 | 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26, | |
| 882 | 0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F, | |
| 883 | 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D, | |
| 884 | 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61, | |
| 885 | 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, | |
| 886 | 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F, | |
| 887 | 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, | |
| 888 | 0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, | |
| 889 | 0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, | |
| 890 | 0xE7, 0xE8, 0xE9, 0xBA, 0xE0, 0xBB, 0xB0, 0x6D, | |
| 891 | 0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, | |
| 892 | 0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, | |
| 893 | 0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, | |
| 894 | 0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07, | |
| 895 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 896 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 897 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 898 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 899 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 900 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 901 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 902 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 903 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 904 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 905 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 906 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 907 | 0x3F, 0x59, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 908 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 909 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, | |
| 910 | 0x90, 0x3F, 0x3F, 0x3F, 0x3F, 0xEA, 0x3F, 0xFF | |
| 911 | }; | |
| 912 | ||
| 913 | static inline void ebcdic_put(uint8_t *p, const char *ascii, int len) | |
| 914 | { | |
| 915 | int i; | |
| 916 | ||
| 917 | for (i = 0; i < len; i++) { | |
| 918 | p[i] = ascii2ebcdic[(int)ascii[i]]; | |
| 919 | } | |
| 920 | } | |
| 921 | ||
| 922 | #define SIGP_SENSE 0x01 | |
| 923 | #define SIGP_EXTERNAL_CALL 0x02 | |
| 924 | #define SIGP_EMERGENCY 0x03 | |
| 925 | #define SIGP_START 0x04 | |
| 926 | #define SIGP_STOP 0x05 | |
| 927 | #define SIGP_RESTART 0x06 | |
| 928 | #define SIGP_STOP_STORE_STATUS 0x09 | |
| 929 | #define SIGP_INITIAL_CPU_RESET 0x0b | |
| 930 | #define SIGP_CPU_RESET 0x0c | |
| 931 | #define SIGP_SET_PREFIX 0x0d | |
| 932 | #define SIGP_STORE_STATUS_ADDR 0x0e | |
| 933 | #define SIGP_SET_ARCH 0x12 | |
| 934 | ||
| 935 | /* cpu status bits */ | |
| 936 | #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL | |
| 937 | #define SIGP_STAT_INCORRECT_STATE 0x00000200UL | |
| 938 | #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL | |
| 939 | #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL | |
| 940 | #define SIGP_STAT_STOPPED 0x00000040UL | |
| 941 | #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL | |
| 942 | #define SIGP_STAT_CHECK_STOP 0x00000010UL | |
| 943 | #define SIGP_STAT_INOPERATIVE 0x00000004UL | |
| 944 | #define SIGP_STAT_INVALID_ORDER 0x00000002UL | |
| 945 | #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL | |
| 946 | ||
| 947 | void load_psw(CPUState *env, uint64_t mask, uint64_t addr); | |
| 948 | int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc, | |
| 949 | target_ulong *raddr, int *flags); | |
| 950 | int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code); | |
| 951 | uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst, | |
| 952 | uint64_t vr); | |
| 953 | ||
| 954 | #define TARGET_HAS_ICE 1 | |
| 955 | ||
| 956 | /* The value of the TOD clock for 1.1.1970. */ | |
| 957 | #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL | |
| 958 | ||
| 959 | /* Converts ns to s390's clock format */ | |
| 960 | static inline uint64_t time2tod(uint64_t ns) { | |
| 961 | return (ns << 9) / 125; | |
| 962 | } | |
| 963 | ||
| 964 | static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param, | |
| 965 | uint64_t param64) | |
| 966 | { | |
| 967 | if (env->ext_index == MAX_EXT_QUEUE - 1) { | |
| 968 | /* ugh - can't queue anymore. Let's drop. */ | |
| 969 | return; | |
| 970 | } | |
| 971 | ||
| 972 | env->ext_index++; | |
| 973 | assert(env->ext_index < MAX_EXT_QUEUE); | |
| 974 | ||
| 975 | env->ext_queue[env->ext_index].code = code; | |
| 976 | env->ext_queue[env->ext_index].param = param; | |
| 977 | env->ext_queue[env->ext_index].param64 = param64; | |
| 978 | ||
| 979 | env->pending_int |= INTERRUPT_EXT; | |
| 980 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
| 981 | } | |
| 10c339a0 | 982 | |
| f081c76c BS |
983 | static inline bool cpu_has_work(CPUState *env) |
| 984 | { | |
| 985 | return (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
| 986 | (env->psw.mask & PSW_MASK_EXT); | |
| 987 | } | |
| 988 | ||
| 989 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb) | |
| 990 | { | |
| 991 | env->psw.addr = tb->pc; | |
| 992 | } | |
| 993 | ||
| 10ec5117 | 994 | #endif |