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s390x/mmu: Check table length and offset fields
[mirror_qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
44b0c0bb
CB		 129 uint64_t gbea;
130 uint64_t pp;
131
4e836781
AG		 132 CPU_COMMON
133
bcec36ea
AG		 134 /* reset does memset(0) up to here */
135
7f745b31
RH		 136 uint32_t cpu_num;
137 uint32_t machine_type;
138
bcec36ea
AG		 139 uint8_t *storage_keys;
140
141 uint64_t tod_offset;
142 uint64_t tod_basetime;
143 QEMUTimer *tod_timer;
144
145 QEMUTimer *cpu_timer;
75973bfe
DH		 146
147 /*
148 * The cpu state represents the logical state of a cpu. In contrast to other
149 * architectures, there is a difference between a halt and a stop on s390.
150 * If all cpus are either stopped (including check stop) or in the disabled
151 * wait state, the vm can be shut down.
152 */
153#define CPU_STATE_UNINITIALIZED 0x00
154#define CPU_STATE_STOPPED 0x01
155#define CPU_STATE_CHECK_STOP 0x02
156#define CPU_STATE_OPERATING 0x03
157#define CPU_STATE_LOAD 0x04
158 uint8_t cpu_state;
159
10ec5117
AG		 160} CPUS390XState;
161
564b863d 162#include "cpu-qom.h"
3d0a615f 163#include <sysemu/kvm.h>
564b863d 164
7b18aad5
CH		 165/* distinguish between 24 bit and 31 bit addressing */
166#define HIGH_ORDER_BIT 0x80000000
167
bcec36ea
AG		 168/* Interrupt Codes */
169/* Program Interrupts */
170#define PGM_OPERATION 0x0001
171#define PGM_PRIVILEGED 0x0002
172#define PGM_EXECUTE 0x0003
173#define PGM_PROTECTION 0x0004
174#define PGM_ADDRESSING 0x0005
175#define PGM_SPECIFICATION 0x0006
176#define PGM_DATA 0x0007
177#define PGM_FIXPT_OVERFLOW 0x0008
178#define PGM_FIXPT_DIVIDE 0x0009
179#define PGM_DEC_OVERFLOW 0x000a
180#define PGM_DEC_DIVIDE 0x000b
181#define PGM_HFP_EXP_OVERFLOW 0x000c
182#define PGM_HFP_EXP_UNDERFLOW 0x000d
183#define PGM_HFP_SIGNIFICANCE 0x000e
184#define PGM_HFP_DIVIDE 0x000f
185#define PGM_SEGMENT_TRANS 0x0010
186#define PGM_PAGE_TRANS 0x0011
187#define PGM_TRANS_SPEC 0x0012
188#define PGM_SPECIAL_OP 0x0013
189#define PGM_OPERAND 0x0015
190#define PGM_TRACE_TABLE 0x0016
191#define PGM_SPACE_SWITCH 0x001c
192#define PGM_HFP_SQRT 0x001d
193#define PGM_PC_TRANS_SPEC 0x001f
194#define PGM_AFX_TRANS 0x0020
195#define PGM_ASX_TRANS 0x0021
196#define PGM_LX_TRANS 0x0022
197#define PGM_EX_TRANS 0x0023
198#define PGM_PRIM_AUTH 0x0024
199#define PGM_SEC_AUTH 0x0025
200#define PGM_ALET_SPEC 0x0028
201#define PGM_ALEN_SPEC 0x0029
202#define PGM_ALE_SEQ 0x002a
203#define PGM_ASTE_VALID 0x002b
204#define PGM_ASTE_SEQ 0x002c
205#define PGM_EXT_AUTH 0x002d
206#define PGM_STACK_FULL 0x0030
207#define PGM_STACK_EMPTY 0x0031
208#define PGM_STACK_SPEC 0x0032
209#define PGM_STACK_TYPE 0x0033
210#define PGM_STACK_OP 0x0034
211#define PGM_ASCE_TYPE 0x0038
212#define PGM_REG_FIRST_TRANS 0x0039
213#define PGM_REG_SEC_TRANS 0x003a
214#define PGM_REG_THIRD_TRANS 0x003b
215#define PGM_MONITOR 0x0040
216#define PGM_PER 0x0080
217#define PGM_CRYPTO 0x0119
218
219/* External Interrupts */
220#define EXT_INTERRUPT_KEY 0x0040
221#define EXT_CLOCK_COMP 0x1004
222#define EXT_CPU_TIMER 0x1005
223#define EXT_MALFUNCTION 0x1200
224#define EXT_EMERGENCY 0x1201
225#define EXT_EXTERNAL_CALL 0x1202
226#define EXT_ETR 0x1406
227#define EXT_SERVICE 0x2401
228#define EXT_VIRTIO 0x2603
229
230/* PSW defines */
231#undef PSW_MASK_PER
232#undef PSW_MASK_DAT
233#undef PSW_MASK_IO
234#undef PSW_MASK_EXT
235#undef PSW_MASK_KEY
236#undef PSW_SHIFT_KEY
237#undef PSW_MASK_MCHECK
238#undef PSW_MASK_WAIT
239#undef PSW_MASK_PSTATE
240#undef PSW_MASK_ASC
241#undef PSW_MASK_CC
242#undef PSW_MASK_PM
243#undef PSW_MASK_64
29c6157c
CB		 244#undef PSW_MASK_32
245#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 246
247#define PSW_MASK_PER 0x4000000000000000ULL
248#define PSW_MASK_DAT 0x0400000000000000ULL
249#define PSW_MASK_IO 0x0200000000000000ULL
250#define PSW_MASK_EXT 0x0100000000000000ULL
251#define PSW_MASK_KEY 0x00F0000000000000ULL
252#define PSW_SHIFT_KEY 56
253#define PSW_MASK_MCHECK 0x0004000000000000ULL
254#define PSW_MASK_WAIT 0x0002000000000000ULL
255#define PSW_MASK_PSTATE 0x0001000000000000ULL
256#define PSW_MASK_ASC 0x0000C00000000000ULL
257#define PSW_MASK_CC 0x0000300000000000ULL
258#define PSW_MASK_PM 0x00000F0000000000ULL
259#define PSW_MASK_64 0x0000000100000000ULL
260#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 261#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 262
263#undef PSW_ASC_PRIMARY
264#undef PSW_ASC_ACCREG
265#undef PSW_ASC_SECONDARY
266#undef PSW_ASC_HOME
267
268#define PSW_ASC_PRIMARY 0x0000000000000000ULL
269#define PSW_ASC_ACCREG 0x0000400000000000ULL
270#define PSW_ASC_SECONDARY 0x0000800000000000ULL
271#define PSW_ASC_HOME 0x0000C00000000000ULL
272
273/* tb flags */
274
275#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
276#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
277#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
278#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
279#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
280#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
281#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
282#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
283#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
284#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
285#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
286#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
287#define FLAG_MASK_32 0x00001000
288
c4400206
TH		 289/* Control register 0 bits */
290#define CR0_EDAT 0x0000000000800000ULL
291
a4e3ad19 292static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 293{
bcec36ea
AG		 294 if (env->psw.mask & PSW_MASK_PSTATE) {
295 return 1;
296 }
297
10c339a0
AG		 298 return 0;
299}
300
a4e3ad19 301static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 302 target_ulong *cs_base, int *flags)
303{
304 *pc = env->psw.addr;
305 *cs_base = 0;
306 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
307 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
308}
309
d5a103cd
RH		 310/* While the PoO talks about ILC (a number between 1-3) what is actually
311 stored in LowCore is shifted left one bit (an even between 2-6). As
312 this is the actual length of the insn and therefore more useful, that
313 is what we want to pass around and manipulate. To make sure that we
314 have applied this distinction universally, rename the "ILC" to "ILEN". */
315static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 316{
317 switch (opc >> 6) {
318 case 0:
d5a103cd 319 return 2;
bcec36ea
AG		 320 case 1:
321 case 2:
d5a103cd
RH		 322 return 4;
323 default:
324 return 6;
bcec36ea 325 }
bcec36ea
AG		 326}
327
d5a103cd
RH		 328#ifndef CONFIG_USER_ONLY
329/* In several cases of runtime exceptions, we havn't recorded the true
330 instruction length. Use these codes when raising exceptions in order
331 to re-compute the length by examining the insn in memory. */
332#define ILEN_LATER 0x20
333#define ILEN_LATER_INC 0x21
dfebd7a7 334void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
d5a103cd 335#endif
bcec36ea 336
564b863d 337S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 338void s390x_translate_init(void);
10ec5117 339int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 340
341/* you can call this signal handler from your SIGBUS and SIGSEGV
342 signal handlers to inform the virtual CPU of exceptions. non zero
343 is returned if the signal was handled by the virtual CPU. */
344int cpu_s390x_signal_handler(int host_signum, void *pinfo,
345 void *puc);
7510454e
AF		 346int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
347 int mmu_idx);
10ec5117 348
db1c8f53 349#include "ioinst.h"
52705890 350
10c339a0 351#ifndef CONFIG_USER_ONLY
38322ed6
CH		 352void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
353 int is_write);
354void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
355 int is_write);
7b18aad5
CH		 356static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
357{
358 hwaddr addr = 0;
359 uint8_t reg;
360
361 reg = ipb >> 28;
362 if (reg > 0) {
363 addr = env->regs[reg];
364 }
365 addr += (ipb >> 16) & 0xfff;
366
367 return addr;
368}
369
638129ff
CH		 370/* Base/displacement are at the same locations. */
371#define decode_basedisp_rs decode_basedisp_s
372
85ca3371
DH		 373/* helper functions for run_on_cpu() */
374static inline void s390_do_cpu_reset(void *arg)
375{
376 CPUState *cs = arg;
377 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
378
379 scc->cpu_reset(cs);
380}
381static inline void s390_do_cpu_full_reset(void *arg)
382{
383 CPUState *cs = arg;
384
385 cpu_reset(cs);
386}
387
8f22e0df
AF		 388void s390x_tod_timer(void *opaque);
389void s390x_cpu_timer(void *opaque);
390
28e942f8 391int s390_virtio_hypercall(CPUS390XState *env);
de13d216 392void s390_virtio_irq(int config_change, uint64_t token);
bcec36ea 393
1f206266 394#ifdef CONFIG_KVM
de13d216
CH		 395void kvm_s390_virtio_irq(int config_change, uint64_t token);
396void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH		 397void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
398void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 399int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
1f206266 400#else
de13d216 401static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
1f206266
AG		 402{
403}
de13d216 404static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH		 405{
406}
1f206266 407#endif
45fa769b 408S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH		 409unsigned int s390_cpu_halt(S390CPU *cpu);
410void s390_cpu_unhalt(S390CPU *cpu);
411unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
bcec36ea 412
000a1a38
CB		 413/* service interrupts are floating therefore we must not pass an cpustate */
414void s390_sclp_extint(uint32_t parm);
415
d1ff903c 416/* from s390-virtio-bus */
a8170e5e 417extern const hwaddr virtio_size;
d1ff903c 418
ef81522b 419#else
eb24f7c6
DH		 420static inline unsigned int s390_cpu_halt(S390CPU *cpu)
421{
422 return 0;
423}
424
425static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG		 426{
427}
428
eb24f7c6 429static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG		 430{
431 return 0;
432}
10c339a0 433#endif
bcec36ea
AG		 434void cpu_lock(void);
435void cpu_unlock(void);
10c339a0 436
7b18aad5
CH		 437typedef struct SubchDev SubchDev;
438
df1fe5bb 439#ifndef CONFIG_USER_ONLY
4e872a3f 440extern void io_subsystem_reset(void);
df1fe5bb
CH		 441SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
442 uint16_t schid);
443bool css_subch_visible(SubchDev *sch);
444void css_conditional_io_interrupt(SubchDev *sch);
445int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 446bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 447int css_do_msch(SubchDev *sch, SCHIB *schib);
448int css_do_xsch(SubchDev *sch);
449int css_do_csch(SubchDev *sch);
450int css_do_hsch(SubchDev *sch);
451int css_do_ssch(SubchDev *sch, ORB *orb);
452int css_do_tsch(SubchDev *sch, IRB *irb);
453int css_do_stcrw(CRW *crw);
50c8d9bf 454int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 455int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
456 int rfmt, void *buf);
457void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
458int css_enable_mcsse(void);
459int css_enable_mss(void);
460int css_do_rsch(SubchDev *sch);
461int css_do_rchp(uint8_t cssid, uint8_t chpid);
462bool css_present(uint8_t cssid);
df1fe5bb 463#endif
7b18aad5 464
564b863d 465#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 466#define cpu_exec cpu_s390x_exec
467#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 468#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 469
904e5fd5
VM		 470void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
471#define cpu_list s390_cpu_list
472
022c62cb 473#include "exec/exec-all.h"
bcec36ea 474
bcec36ea
AG		 475#define EXCP_EXT 1 /* external interrupt */
476#define EXCP_SVC 2 /* supervisor call (syscall) */
477#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 478#define EXCP_IO 7 /* I/O interrupt */
479#define EXCP_MCHK 8 /* machine check */
bcec36ea 480
bcec36ea
AG		 481#define INTERRUPT_EXT (1 << 0)
482#define INTERRUPT_TOD (1 << 1)
483#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 484#define INTERRUPT_IO (1 << 3)
485#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 486
487/* Program Status Word. */
488#define S390_PSWM_REGNUM 0
489#define S390_PSWA_REGNUM 1
490/* General Purpose Registers. */
491#define S390_R0_REGNUM 2
492#define S390_R1_REGNUM 3
493#define S390_R2_REGNUM 4
494#define S390_R3_REGNUM 5
495#define S390_R4_REGNUM 6
496#define S390_R5_REGNUM 7
497#define S390_R6_REGNUM 8
498#define S390_R7_REGNUM 9
499#define S390_R8_REGNUM 10
500#define S390_R9_REGNUM 11
501#define S390_R10_REGNUM 12
502#define S390_R11_REGNUM 13
503#define S390_R12_REGNUM 14
504#define S390_R13_REGNUM 15
505#define S390_R14_REGNUM 16
506#define S390_R15_REGNUM 17
73d510c9
DH		 507/* Total Core Registers. */
508#define S390_NUM_CORE_REGS 18
10c339a0 509
bcec36ea
AG		 510/* CC optimization */
511
512enum cc_op {
513 CC_OP_CONST0 = 0, /* CC is 0 */
514 CC_OP_CONST1, /* CC is 1 */
515 CC_OP_CONST2, /* CC is 2 */
516 CC_OP_CONST3, /* CC is 3 */
517
518 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
519 CC_OP_STATIC, /* CC value is env->cc_op */
520
521 CC_OP_NZ, /* env->cc_dst != 0 */
522 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
523 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
524 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
525 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
526 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
527 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
528
529 CC_OP_ADD_64, /* overflow on add (64bit) */
530 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 531 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 532 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
533 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 534 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 535 CC_OP_ABS_64, /* sign eval on abs (64bit) */
536 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
537
538 CC_OP_ADD_32, /* overflow on add (32bit) */
539 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 540 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 541 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
542 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 543 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 544 CC_OP_ABS_32, /* sign eval on abs (64bit) */
545 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
546
547 CC_OP_COMP_32, /* complement */
548 CC_OP_COMP_64, /* complement */
549
550 CC_OP_TM_32, /* test under mask (32bit) */
551 CC_OP_TM_64, /* test under mask (64bit) */
552
bcec36ea
AG		 553 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
554 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 555 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 556
557 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 558 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
559 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 560 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 561 CC_OP_MAX
562};
563
564static const char *cc_names[] = {
565 [CC_OP_CONST0] = "CC_OP_CONST0",
566 [CC_OP_CONST1] = "CC_OP_CONST1",
567 [CC_OP_CONST2] = "CC_OP_CONST2",
568 [CC_OP_CONST3] = "CC_OP_CONST3",
569 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
570 [CC_OP_STATIC] = "CC_OP_STATIC",
571 [CC_OP_NZ] = "CC_OP_NZ",
572 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
573 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
574 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
575 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
576 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
577 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
578 [CC_OP_ADD_64] = "CC_OP_ADD_64",
579 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 580 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 581 [CC_OP_SUB_64] = "CC_OP_SUB_64",
582 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 583 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 584 [CC_OP_ABS_64] = "CC_OP_ABS_64",
585 [CC_OP_NABS_64] = "CC_OP_NABS_64",
586 [CC_OP_ADD_32] = "CC_OP_ADD_32",
587 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 588 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 589 [CC_OP_SUB_32] = "CC_OP_SUB_32",
590 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 591 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 592 [CC_OP_ABS_32] = "CC_OP_ABS_32",
593 [CC_OP_NABS_32] = "CC_OP_NABS_32",
594 [CC_OP_COMP_32] = "CC_OP_COMP_32",
595 [CC_OP_COMP_64] = "CC_OP_COMP_64",
596 [CC_OP_TM_32] = "CC_OP_TM_32",
597 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 598 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
599 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 600 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 601 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 602 [CC_OP_SLA_32] = "CC_OP_SLA_32",
603 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 604 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 605};
606
607static inline const char *cc_name(int cc_op)
608{
609 return cc_names[cc_op];
610}
611
3d0a615f
TH		 612static inline void setcc(S390CPU *cpu, uint64_t cc)
613{
614 CPUS390XState *env = &cpu->env;
615
616 env->psw.mask &= ~(3ull << 44);
617 env->psw.mask |= (cc & 3) << 44;
618}
619
bcec36ea
AG		 620typedef struct LowCore
621{
622 /* prefix area: defined by architecture */
623 uint32_t ccw1[2]; /* 0x000 */
624 uint32_t ccw2[4]; /* 0x008 */
625 uint8_t pad1[0x80-0x18]; /* 0x018 */
626 uint32_t ext_params; /* 0x080 */
627 uint16_t cpu_addr; /* 0x084 */
628 uint16_t ext_int_code; /* 0x086 */
d5a103cd 629 uint16_t svc_ilen; /* 0x088 */
bcec36ea 630 uint16_t svc_code; /* 0x08a */
d5a103cd 631 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 632 uint16_t pgm_code; /* 0x08e */
633 uint32_t data_exc_code; /* 0x090 */
634 uint16_t mon_class_num; /* 0x094 */
635 uint16_t per_perc_atmid; /* 0x096 */
636 uint64_t per_address; /* 0x098 */
637 uint8_t exc_access_id; /* 0x0a0 */
638 uint8_t per_access_id; /* 0x0a1 */
639 uint8_t op_access_id; /* 0x0a2 */
640 uint8_t ar_access_id; /* 0x0a3 */
641 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
642 uint64_t trans_exc_code; /* 0x0a8 */
643 uint64_t monitor_code; /* 0x0b0 */
644 uint16_t subchannel_id; /* 0x0b8 */
645 uint16_t subchannel_nr; /* 0x0ba */
646 uint32_t io_int_parm; /* 0x0bc */
647 uint32_t io_int_word; /* 0x0c0 */
648 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
649 uint32_t stfl_fac_list; /* 0x0c8 */
650 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
651 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
652 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
653 uint32_t external_damage_code; /* 0x0f4 */
654 uint64_t failing_storage_address; /* 0x0f8 */
655 uint8_t pad6[0x120-0x100]; /* 0x100 */
656 PSW restart_old_psw; /* 0x120 */
657 PSW external_old_psw; /* 0x130 */
658 PSW svc_old_psw; /* 0x140 */
659 PSW program_old_psw; /* 0x150 */
660 PSW mcck_old_psw; /* 0x160 */
661 PSW io_old_psw; /* 0x170 */
662 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
663 PSW restart_psw; /* 0x1a0 */
664 PSW external_new_psw; /* 0x1b0 */
665 PSW svc_new_psw; /* 0x1c0 */
666 PSW program_new_psw; /* 0x1d0 */
667 PSW mcck_new_psw; /* 0x1e0 */
668 PSW io_new_psw; /* 0x1f0 */
669 PSW return_psw; /* 0x200 */
670 uint8_t irb[64]; /* 0x210 */
671 uint64_t sync_enter_timer; /* 0x250 */
672 uint64_t async_enter_timer; /* 0x258 */
673 uint64_t exit_timer; /* 0x260 */
674 uint64_t last_update_timer; /* 0x268 */
675 uint64_t user_timer; /* 0x270 */
676 uint64_t system_timer; /* 0x278 */
677 uint64_t last_update_clock; /* 0x280 */
678 uint64_t steal_clock; /* 0x288 */
679 PSW return_mcck_psw; /* 0x290 */
680 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
681 /* System info area */
682 uint64_t save_area[16]; /* 0xc00 */
683 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
684 uint64_t kernel_stack; /* 0xd40 */
685 uint64_t thread_info; /* 0xd48 */
686 uint64_t async_stack; /* 0xd50 */
687 uint64_t kernel_asce; /* 0xd58 */
688 uint64_t user_asce; /* 0xd60 */
689 uint64_t panic_stack; /* 0xd68 */
690 uint64_t user_exec_asce; /* 0xd70 */
691 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
692
693 /* SMP info area: defined by DJB */
694 uint64_t clock_comparator; /* 0xdc0 */
695 uint64_t ext_call_fast; /* 0xdc8 */
696 uint64_t percpu_offset; /* 0xdd0 */
697 uint64_t current_task; /* 0xdd8 */
698 uint32_t softirq_pending; /* 0xde0 */
699 uint32_t pad_0x0de4; /* 0xde4 */
700 uint64_t int_clock; /* 0xde8 */
701 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
702
703 /* 0xe00 is used as indicator for dump tools */
704 /* whether the kernel died with panic() or not */
705 uint32_t panic_magic; /* 0xe00 */
706
707 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
708
709 /* 64 bit extparam used for pfault, diag 250 etc */
710 uint64_t ext_params2; /* 0x11B8 */
711
712 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
713
714 /* System info area */
715
716 uint64_t floating_pt_save_area[16]; /* 0x1200 */
717 uint64_t gpregs_save_area[16]; /* 0x1280 */
718 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
719 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
720 uint32_t prefixreg_save_area; /* 0x1318 */
721 uint32_t fpt_creg_save_area; /* 0x131c */
722 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
723 uint32_t tod_progreg_save_area; /* 0x1324 */
724 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
725 uint32_t clock_comp_save_area[2]; /* 0x1330 */
726 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
727 uint32_t access_regs_save_area[16]; /* 0x1340 */
728 uint64_t cregs_save_area[16]; /* 0x1380 */
729
730 /* align to the top of the prefix area */
731
732 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 733} QEMU_PACKED LowCore;
bcec36ea
AG		 734
735/* STSI */
736#define STSI_LEVEL_MASK 0x00000000f0000000ULL
737#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
738#define STSI_LEVEL_1 0x0000000010000000ULL
739#define STSI_LEVEL_2 0x0000000020000000ULL
740#define STSI_LEVEL_3 0x0000000030000000ULL
741#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
742#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
743#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
744#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
745
746/* Basic Machine Configuration */
747struct sysib_111 {
748 uint32_t res1[8];
749 uint8_t manuf[16];
750 uint8_t type[4];
751 uint8_t res2[12];
752 uint8_t model[16];
753 uint8_t sequence[16];
754 uint8_t plant[4];
755 uint8_t res3[156];
756};
757
758/* Basic Machine CPU */
759struct sysib_121 {
760 uint32_t res1[80];
761 uint8_t sequence[16];
762 uint8_t plant[4];
763 uint8_t res2[2];
764 uint16_t cpu_addr;
765 uint8_t res3[152];
766};
767
768/* Basic Machine CPUs */
769struct sysib_122 {
770 uint8_t res1[32];
771 uint32_t capability;
772 uint16_t total_cpus;
773 uint16_t active_cpus;
774 uint16_t standby_cpus;
775 uint16_t reserved_cpus;
776 uint16_t adjustments[2026];
777};
778
779/* LPAR CPU */
780struct sysib_221 {
781 uint32_t res1[80];
782 uint8_t sequence[16];
783 uint8_t plant[4];
784 uint16_t cpu_id;
785 uint16_t cpu_addr;
786 uint8_t res3[152];
787};
788
789/* LPAR CPUs */
790struct sysib_222 {
791 uint32_t res1[32];
792 uint16_t lpar_num;
793 uint8_t res2;
794 uint8_t lcpuc;
795 uint16_t total_cpus;
796 uint16_t conf_cpus;
797 uint16_t standby_cpus;
798 uint16_t reserved_cpus;
799 uint8_t name[8];
800 uint32_t caf;
801 uint8_t res3[16];
802 uint16_t dedicated_cpus;
803 uint16_t shared_cpus;
804 uint8_t res4[180];
805};
806
807/* VM CPUs */
808struct sysib_322 {
809 uint8_t res1[31];
810 uint8_t count;
811 struct {
812 uint8_t res2[4];
813 uint16_t total_cpus;
814 uint16_t conf_cpus;
815 uint16_t standby_cpus;
816 uint16_t reserved_cpus;
817 uint8_t name[8];
818 uint32_t caf;
819 uint8_t cpi[16];
820 uint8_t res3[24];
821 } vm[8];
822 uint8_t res4[3552];
823};
824
825/* MMU defines */
826#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
827#define _ASCE_SUBSPACE 0x200 /* subspace group control */
828#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
829#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
830#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
831#define _ASCE_REAL_SPACE 0x20 /* real space control */
832#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
833#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
834#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
835#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
836#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
837#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
838
839#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
5d180439 840#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
bcec36ea
AG		 841#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
842#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
843#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
844#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
845#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
846#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
847
848#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 849#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG		 850#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
851#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
852
853#define _PAGE_RO 0x200 /* HW read-only bit */
854#define _PAGE_INVALID 0x400 /* HW invalid bit */
855
b9959138
AG		 856#define SK_C (0x1 << 1)
857#define SK_R (0x1 << 2)
858#define SK_F (0x1 << 3)
859#define SK_ACC_MASK (0xf << 4)
bcec36ea 860
bcec36ea
AG		 861#define SIGP_SENSE 0x01
862#define SIGP_EXTERNAL_CALL 0x02
863#define SIGP_EMERGENCY 0x03
864#define SIGP_START 0x04
865#define SIGP_STOP 0x05
866#define SIGP_RESTART 0x06
867#define SIGP_STOP_STORE_STATUS 0x09
868#define SIGP_INITIAL_CPU_RESET 0x0b
869#define SIGP_CPU_RESET 0x0c
870#define SIGP_SET_PREFIX 0x0d
871#define SIGP_STORE_STATUS_ADDR 0x0e
872#define SIGP_SET_ARCH 0x12
873
874/* cpu status bits */
875#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
876#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
877#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
878#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
879#define SIGP_STAT_STOPPED 0x00000040UL
880#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
881#define SIGP_STAT_CHECK_STOP 0x00000010UL
882#define SIGP_STAT_INOPERATIVE 0x00000004UL
883#define SIGP_STAT_INVALID_ORDER 0x00000002UL
884#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
885
a4e3ad19
AF		 886void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
887int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 888 target_ulong *raddr, int *flags);
6e252802 889int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 890uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 891 uint64_t vr);
892
bcec36ea
AG		 893/* The value of the TOD clock for 1.1.1970. */
894#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
895
896/* Converts ns to s390's clock format */
897static inline uint64_t time2tod(uint64_t ns) {
898 return (ns << 9) / 125;
899}
900
f9466733 901static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 902 uint64_t param64)
903{
f9466733
AF		 904 CPUS390XState *env = &cpu->env;
905
bcec36ea
AG		 906 if (env->ext_index == MAX_EXT_QUEUE - 1) {
907 /* ugh - can't queue anymore. Let's drop. */
908 return;
909 }
910
911 env->ext_index++;
912 assert(env->ext_index < MAX_EXT_QUEUE);
913
914 env->ext_queue[env->ext_index].code = code;
915 env->ext_queue[env->ext_index].param = param;
916 env->ext_queue[env->ext_index].param64 = param64;
917
918 env->pending_int |= INTERRUPT_EXT;
c3affe56 919 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 920}
10c339a0 921
f9466733 922static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 923 uint16_t subchannel_number,
924 uint32_t io_int_parm, uint32_t io_int_word)
925{
f9466733 926 CPUS390XState *env = &cpu->env;
91b0a8f3 927 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 928
929 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
930 /* ugh - can't queue anymore. Let's drop. */
931 return;
932 }
933
934 env->io_index[isc]++;
935 assert(env->io_index[isc] < MAX_IO_QUEUE);
936
937 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
938 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
939 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
940 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
941
942 env->pending_int |= INTERRUPT_IO;
c3affe56 943 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 944}
945
f9466733 946static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 947{
f9466733
AF		 948 CPUS390XState *env = &cpu->env;
949
5d69c547
CH		 950 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
951 /* ugh - can't queue anymore. Let's drop. */
952 return;
953 }
954
955 env->mchk_index++;
956 assert(env->mchk_index < MAX_MCHK_QUEUE);
957
958 env->mchk_queue[env->mchk_index].type = 1;
959
960 env->pending_int |= INTERRUPT_MCHK;
c3affe56 961 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 962}
963
b6fe0124
MR		 964/* from s390-virtio-ccw */
965#define MEM_SECTION_SIZE 0x10000000UL
1def6656 966#define MAX_AVAIL_SLOTS 32
b6fe0124 967
e72ca652 968/* fpu_helper.c */
e72ca652
BS		 969uint32_t set_cc_nz_f32(float32 v);
970uint32_t set_cc_nz_f64(float64 v);
587626f8 971uint32_t set_cc_nz_f128(float128 v);
e72ca652 972
aea1e885 973/* misc_helper.c */
268846ba
ED		 974#ifndef CONFIG_USER_ONLY
975void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
976#endif
d5a103cd 977void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 978void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
979 uintptr_t retaddr);
a78b0504 980
09b99878 981#ifdef CONFIG_KVM
de13d216 982void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH		 983 uint16_t subchannel_nr, uint32_t io_int_parm,
984 uint32_t io_int_word);
de13d216 985void kvm_s390_crw_mchk(void);
09b99878 986void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 987int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
988 int vq, bool assign);
7f7f9752 989int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 990int kvm_s390_get_memslot_count(KVMState *s);
4cb88c3c 991void kvm_s390_clear_cmma_callback(void *opaque);
c9e659c9 992int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
99607144 993void kvm_s390_reset_vcpu(S390CPU *cpu);
09b99878 994#else
de13d216 995static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH		 996 uint16_t subchannel_nr,
997 uint32_t io_int_parm,
998 uint32_t io_int_word)
999{
1000}
de13d216 1001static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH		 1002{
1003}
09b99878
CH		 1004static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1005{
1006}
cc3ac9c4
CH		 1007static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1008 uint32_t sch, int vq,
b4436a0b
CH		 1009 bool assign)
1010{
1011 return -ENOSYS;
1012}
7f7f9752
ED		 1013static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1014{
1015 return -ENOSYS;
1016}
4cb88c3c
DD		 1017static inline void kvm_s390_clear_cmma_callback(void *opaque)
1018{
1019}
1def6656
MR		 1020static inline int kvm_s390_get_memslot_count(KVMState *s)
1021{
1022 return MAX_AVAIL_SLOTS;
1023}
c9e659c9
DH		 1024static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1025{
1026 return -ENOSYS;
1027}
99607144
DH		 1028static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1029{
1030}
09b99878 1031#endif
df1fe5bb 1032
4cb88c3c
DD		 1033static inline void cmma_reset(S390CPU *cpu)
1034{
1035 if (kvm_enabled()) {
1036 CPUState *cs = CPU(cpu);
1037 kvm_s390_clear_cmma_callback(cs->kvm_state);
1038 }
1039}
1040
7f7f9752
ED		 1041static inline int s390_cpu_restart(S390CPU *cpu)
1042{
1043 if (kvm_enabled()) {
1044 return kvm_s390_cpu_restart(cpu);
1045 }
1046 return -ENOSYS;
1047}
1048
1def6656
MR		 1049static inline int s390_get_memslot_count(KVMState *s)
1050{
1051 if (kvm_enabled()) {
1052 return kvm_s390_get_memslot_count(s);
1053 } else {
1054 return MAX_AVAIL_SLOTS;
1055 }
1056}
1057
de13d216
CH		 1058void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1059 uint32_t io_int_parm, uint32_t io_int_word);
1060void s390_crw_mchk(void);
df1fe5bb 1061
cc3ac9c4
CH		 1062static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1063 uint32_t sch_id, int vq,
b4436a0b
CH		 1064 bool assign)
1065{
1066 if (kvm_enabled()) {
cc3ac9c4 1067 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1068 } else {
1069 return -ENOSYS;
1070 }
1071}
1072
10ec5117 1073#endif
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