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cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
[mirror_qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
4e836781
AG		 129 CPU_COMMON
130
bcec36ea
AG		 131 /* reset does memset(0) up to here */
132
bcec36ea
AG		 133 int cpu_num;
134 uint8_t *storage_keys;
135
136 uint64_t tod_offset;
137 uint64_t tod_basetime;
138 QEMUTimer *tod_timer;
139
140 QEMUTimer *cpu_timer;
10ec5117
AG		 141} CPUS390XState;
142
564b863d 143#include "cpu-qom.h"
3d0a615f 144#include <sysemu/kvm.h>
564b863d 145
7b18aad5
CH		 146/* distinguish between 24 bit and 31 bit addressing */
147#define HIGH_ORDER_BIT 0x80000000
148
bcec36ea
AG		 149/* Interrupt Codes */
150/* Program Interrupts */
151#define PGM_OPERATION 0x0001
152#define PGM_PRIVILEGED 0x0002
153#define PGM_EXECUTE 0x0003
154#define PGM_PROTECTION 0x0004
155#define PGM_ADDRESSING 0x0005
156#define PGM_SPECIFICATION 0x0006
157#define PGM_DATA 0x0007
158#define PGM_FIXPT_OVERFLOW 0x0008
159#define PGM_FIXPT_DIVIDE 0x0009
160#define PGM_DEC_OVERFLOW 0x000a
161#define PGM_DEC_DIVIDE 0x000b
162#define PGM_HFP_EXP_OVERFLOW 0x000c
163#define PGM_HFP_EXP_UNDERFLOW 0x000d
164#define PGM_HFP_SIGNIFICANCE 0x000e
165#define PGM_HFP_DIVIDE 0x000f
166#define PGM_SEGMENT_TRANS 0x0010
167#define PGM_PAGE_TRANS 0x0011
168#define PGM_TRANS_SPEC 0x0012
169#define PGM_SPECIAL_OP 0x0013
170#define PGM_OPERAND 0x0015
171#define PGM_TRACE_TABLE 0x0016
172#define PGM_SPACE_SWITCH 0x001c
173#define PGM_HFP_SQRT 0x001d
174#define PGM_PC_TRANS_SPEC 0x001f
175#define PGM_AFX_TRANS 0x0020
176#define PGM_ASX_TRANS 0x0021
177#define PGM_LX_TRANS 0x0022
178#define PGM_EX_TRANS 0x0023
179#define PGM_PRIM_AUTH 0x0024
180#define PGM_SEC_AUTH 0x0025
181#define PGM_ALET_SPEC 0x0028
182#define PGM_ALEN_SPEC 0x0029
183#define PGM_ALE_SEQ 0x002a
184#define PGM_ASTE_VALID 0x002b
185#define PGM_ASTE_SEQ 0x002c
186#define PGM_EXT_AUTH 0x002d
187#define PGM_STACK_FULL 0x0030
188#define PGM_STACK_EMPTY 0x0031
189#define PGM_STACK_SPEC 0x0032
190#define PGM_STACK_TYPE 0x0033
191#define PGM_STACK_OP 0x0034
192#define PGM_ASCE_TYPE 0x0038
193#define PGM_REG_FIRST_TRANS 0x0039
194#define PGM_REG_SEC_TRANS 0x003a
195#define PGM_REG_THIRD_TRANS 0x003b
196#define PGM_MONITOR 0x0040
197#define PGM_PER 0x0080
198#define PGM_CRYPTO 0x0119
199
200/* External Interrupts */
201#define EXT_INTERRUPT_KEY 0x0040
202#define EXT_CLOCK_COMP 0x1004
203#define EXT_CPU_TIMER 0x1005
204#define EXT_MALFUNCTION 0x1200
205#define EXT_EMERGENCY 0x1201
206#define EXT_EXTERNAL_CALL 0x1202
207#define EXT_ETR 0x1406
208#define EXT_SERVICE 0x2401
209#define EXT_VIRTIO 0x2603
210
211/* PSW defines */
212#undef PSW_MASK_PER
213#undef PSW_MASK_DAT
214#undef PSW_MASK_IO
215#undef PSW_MASK_EXT
216#undef PSW_MASK_KEY
217#undef PSW_SHIFT_KEY
218#undef PSW_MASK_MCHECK
219#undef PSW_MASK_WAIT
220#undef PSW_MASK_PSTATE
221#undef PSW_MASK_ASC
222#undef PSW_MASK_CC
223#undef PSW_MASK_PM
224#undef PSW_MASK_64
29c6157c
CB		 225#undef PSW_MASK_32
226#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 227
228#define PSW_MASK_PER 0x4000000000000000ULL
229#define PSW_MASK_DAT 0x0400000000000000ULL
230#define PSW_MASK_IO 0x0200000000000000ULL
231#define PSW_MASK_EXT 0x0100000000000000ULL
232#define PSW_MASK_KEY 0x00F0000000000000ULL
233#define PSW_SHIFT_KEY 56
234#define PSW_MASK_MCHECK 0x0004000000000000ULL
235#define PSW_MASK_WAIT 0x0002000000000000ULL
236#define PSW_MASK_PSTATE 0x0001000000000000ULL
237#define PSW_MASK_ASC 0x0000C00000000000ULL
238#define PSW_MASK_CC 0x0000300000000000ULL
239#define PSW_MASK_PM 0x00000F0000000000ULL
240#define PSW_MASK_64 0x0000000100000000ULL
241#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 242#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 243
244#undef PSW_ASC_PRIMARY
245#undef PSW_ASC_ACCREG
246#undef PSW_ASC_SECONDARY
247#undef PSW_ASC_HOME
248
249#define PSW_ASC_PRIMARY 0x0000000000000000ULL
250#define PSW_ASC_ACCREG 0x0000400000000000ULL
251#define PSW_ASC_SECONDARY 0x0000800000000000ULL
252#define PSW_ASC_HOME 0x0000C00000000000ULL
253
254/* tb flags */
255
256#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
257#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
258#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
259#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
260#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
261#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
262#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
263#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
264#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
265#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
266#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
267#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
268#define FLAG_MASK_32 0x00001000
269
a4e3ad19 270static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 271{
bcec36ea
AG		 272 if (env->psw.mask & PSW_MASK_PSTATE) {
273 return 1;
274 }
275
10c339a0
AG		 276 return 0;
277}
278
a4e3ad19 279static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 280 target_ulong *cs_base, int *flags)
281{
282 *pc = env->psw.addr;
283 *cs_base = 0;
284 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
285 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
286}
287
d5a103cd
RH		 288/* While the PoO talks about ILC (a number between 1-3) what is actually
289 stored in LowCore is shifted left one bit (an even between 2-6). As
290 this is the actual length of the insn and therefore more useful, that
291 is what we want to pass around and manipulate. To make sure that we
292 have applied this distinction universally, rename the "ILC" to "ILEN". */
293static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 294{
295 switch (opc >> 6) {
296 case 0:
d5a103cd 297 return 2;
bcec36ea
AG		 298 case 1:
299 case 2:
d5a103cd
RH		 300 return 4;
301 default:
302 return 6;
bcec36ea 303 }
bcec36ea
AG		 304}
305
d5a103cd
RH		 306#ifndef CONFIG_USER_ONLY
307/* In several cases of runtime exceptions, we havn't recorded the true
308 instruction length. Use these codes when raising exceptions in order
309 to re-compute the length by examining the insn in memory. */
310#define ILEN_LATER 0x20
311#define ILEN_LATER_INC 0x21
312#endif
bcec36ea 313
564b863d 314S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 315void s390x_translate_init(void);
10ec5117 316int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 317
318/* you can call this signal handler from your SIGBUS and SIGSEGV
319 signal handlers to inform the virtual CPU of exceptions. non zero
320 is returned if the signal was handled by the virtual CPU. */
321int cpu_s390x_signal_handler(int host_signum, void *pinfo,
322 void *puc);
7510454e
AF		 323int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
324 int mmu_idx);
10ec5117 325
db1c8f53 326#include "ioinst.h"
52705890 327
10c339a0 328#ifndef CONFIG_USER_ONLY
38322ed6
CH		 329void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
330 int is_write);
331void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
332 int is_write);
7b18aad5
CH		 333static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
334{
335 hwaddr addr = 0;
336 uint8_t reg;
337
338 reg = ipb >> 28;
339 if (reg > 0) {
340 addr = env->regs[reg];
341 }
342 addr += (ipb >> 16) & 0xfff;
343
344 return addr;
345}
346
638129ff
CH		 347/* Base/displacement are at the same locations. */
348#define decode_basedisp_rs decode_basedisp_s
349
8f22e0df
AF		 350void s390x_tod_timer(void *opaque);
351void s390x_cpu_timer(void *opaque);
352
28e942f8 353int s390_virtio_hypercall(CPUS390XState *env);
bcec36ea 354
1f206266 355#ifdef CONFIG_KVM
1bc22652
AF		 356void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
357void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
358void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
bcec36ea 359 uint64_t parm64, int vm);
1f206266 360#else
1bc22652 361static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
1f206266
AG		 362{
363}
364
1bc22652 365static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
1f206266
AG		 366 uint64_t token)
367{
368}
369
1bc22652 370static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
1f206266
AG		 371 uint32_t parm, uint64_t parm64,
372 int vm)
373{
374}
375#endif
45fa769b 376S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
49e15878
AF		 377void s390_add_running_cpu(S390CPU *cpu);
378unsigned s390_del_running_cpu(S390CPU *cpu);
bcec36ea 379
000a1a38
CB		 380/* service interrupts are floating therefore we must not pass an cpustate */
381void s390_sclp_extint(uint32_t parm);
382
d1ff903c 383/* from s390-virtio-bus */
a8170e5e 384extern const hwaddr virtio_size;
d1ff903c 385
ef81522b 386#else
49e15878 387static inline void s390_add_running_cpu(S390CPU *cpu)
ef81522b
AG		 388{
389}
390
49e15878 391static inline unsigned s390_del_running_cpu(S390CPU *cpu)
ef81522b
AG		 392{
393 return 0;
394}
10c339a0 395#endif
bcec36ea
AG		 396void cpu_lock(void);
397void cpu_unlock(void);
10c339a0 398
7b18aad5
CH		 399typedef struct SubchDev SubchDev;
400
df1fe5bb 401#ifndef CONFIG_USER_ONLY
4e872a3f 402extern void io_subsystem_reset(void);
df1fe5bb
CH		 403SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
404 uint16_t schid);
405bool css_subch_visible(SubchDev *sch);
406void css_conditional_io_interrupt(SubchDev *sch);
407int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 408bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 409int css_do_msch(SubchDev *sch, SCHIB *schib);
410int css_do_xsch(SubchDev *sch);
411int css_do_csch(SubchDev *sch);
412int css_do_hsch(SubchDev *sch);
413int css_do_ssch(SubchDev *sch, ORB *orb);
414int css_do_tsch(SubchDev *sch, IRB *irb);
415int css_do_stcrw(CRW *crw);
50c8d9bf 416int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 417int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
418 int rfmt, void *buf);
419void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
420int css_enable_mcsse(void);
421int css_enable_mss(void);
422int css_do_rsch(SubchDev *sch);
423int css_do_rchp(uint8_t cssid, uint8_t chpid);
424bool css_present(uint8_t cssid);
425#else
7b18aad5
CH		 426static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
427 uint16_t schid)
428{
429 return NULL;
430}
431static inline bool css_subch_visible(SubchDev *sch)
432{
433 return false;
434}
435static inline void css_conditional_io_interrupt(SubchDev *sch)
436{
437}
438static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
439{
440 return -ENODEV;
441}
442static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
443{
444 return true;
445}
446static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
447{
448 return -ENODEV;
449}
450static inline int css_do_xsch(SubchDev *sch)
451{
452 return -ENODEV;
453}
454static inline int css_do_csch(SubchDev *sch)
455{
456 return -ENODEV;
457}
458static inline int css_do_hsch(SubchDev *sch)
459{
460 return -ENODEV;
461}
462static inline int css_do_ssch(SubchDev *sch, ORB *orb)
463{
464 return -ENODEV;
465}
466static inline int css_do_tsch(SubchDev *sch, IRB *irb)
467{
468 return -ENODEV;
469}
470static inline int css_do_stcrw(CRW *crw)
471{
472 return 1;
473}
50c8d9bf 474static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
7b18aad5
CH		 475{
476 return 0;
477}
478static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
479 int rfmt, uint8_t l_chpid, void *buf)
480{
481 return 0;
482}
483static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
484{
485}
486static inline int css_enable_mss(void)
487{
488 return -EINVAL;
489}
490static inline int css_enable_mcsse(void)
491{
492 return -EINVAL;
493}
494static inline int css_do_rsch(SubchDev *sch)
495{
496 return -ENODEV;
497}
498static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
499{
500 return -ENODEV;
501}
502static inline bool css_present(uint8_t cssid)
503{
504 return false;
505}
df1fe5bb 506#endif
7b18aad5 507
564b863d 508#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 509#define cpu_exec cpu_s390x_exec
510#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 511#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 512
904e5fd5
VM		 513void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
514#define cpu_list s390_cpu_list
515
022c62cb 516#include "exec/exec-all.h"
bcec36ea 517
bcec36ea
AG		 518#define EXCP_EXT 1 /* external interrupt */
519#define EXCP_SVC 2 /* supervisor call (syscall) */
520#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 521#define EXCP_IO 7 /* I/O interrupt */
522#define EXCP_MCHK 8 /* machine check */
bcec36ea 523
bcec36ea
AG		 524#define INTERRUPT_EXT (1 << 0)
525#define INTERRUPT_TOD (1 << 1)
526#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 527#define INTERRUPT_IO (1 << 3)
528#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 529
530/* Program Status Word. */
531#define S390_PSWM_REGNUM 0
532#define S390_PSWA_REGNUM 1
533/* General Purpose Registers. */
534#define S390_R0_REGNUM 2
535#define S390_R1_REGNUM 3
536#define S390_R2_REGNUM 4
537#define S390_R3_REGNUM 5
538#define S390_R4_REGNUM 6
539#define S390_R5_REGNUM 7
540#define S390_R6_REGNUM 8
541#define S390_R7_REGNUM 9
542#define S390_R8_REGNUM 10
543#define S390_R9_REGNUM 11
544#define S390_R10_REGNUM 12
545#define S390_R11_REGNUM 13
546#define S390_R12_REGNUM 14
547#define S390_R13_REGNUM 15
548#define S390_R14_REGNUM 16
549#define S390_R15_REGNUM 17
550/* Access Registers. */
551#define S390_A0_REGNUM 18
552#define S390_A1_REGNUM 19
553#define S390_A2_REGNUM 20
554#define S390_A3_REGNUM 21
555#define S390_A4_REGNUM 22
556#define S390_A5_REGNUM 23
557#define S390_A6_REGNUM 24
558#define S390_A7_REGNUM 25
559#define S390_A8_REGNUM 26
560#define S390_A9_REGNUM 27
561#define S390_A10_REGNUM 28
562#define S390_A11_REGNUM 29
563#define S390_A12_REGNUM 30
564#define S390_A13_REGNUM 31
565#define S390_A14_REGNUM 32
566#define S390_A15_REGNUM 33
567/* Floating Point Control Word. */
568#define S390_FPC_REGNUM 34
569/* Floating Point Registers. */
570#define S390_F0_REGNUM 35
571#define S390_F1_REGNUM 36
572#define S390_F2_REGNUM 37
573#define S390_F3_REGNUM 38
574#define S390_F4_REGNUM 39
575#define S390_F5_REGNUM 40
576#define S390_F6_REGNUM 41
577#define S390_F7_REGNUM 42
578#define S390_F8_REGNUM 43
579#define S390_F9_REGNUM 44
580#define S390_F10_REGNUM 45
581#define S390_F11_REGNUM 46
582#define S390_F12_REGNUM 47
583#define S390_F13_REGNUM 48
584#define S390_F14_REGNUM 49
585#define S390_F15_REGNUM 50
586/* Total. */
587#define S390_NUM_REGS 51
588
bcec36ea
AG		 589/* CC optimization */
590
591enum cc_op {
592 CC_OP_CONST0 = 0, /* CC is 0 */
593 CC_OP_CONST1, /* CC is 1 */
594 CC_OP_CONST2, /* CC is 2 */
595 CC_OP_CONST3, /* CC is 3 */
596
597 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
598 CC_OP_STATIC, /* CC value is env->cc_op */
599
600 CC_OP_NZ, /* env->cc_dst != 0 */
601 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
602 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
603 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
604 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
605 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
606 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
607
608 CC_OP_ADD_64, /* overflow on add (64bit) */
609 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 610 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 611 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
612 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 613 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 614 CC_OP_ABS_64, /* sign eval on abs (64bit) */
615 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
616
617 CC_OP_ADD_32, /* overflow on add (32bit) */
618 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 619 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 620 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
621 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 622 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 623 CC_OP_ABS_32, /* sign eval on abs (64bit) */
624 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
625
626 CC_OP_COMP_32, /* complement */
627 CC_OP_COMP_64, /* complement */
628
629 CC_OP_TM_32, /* test under mask (32bit) */
630 CC_OP_TM_64, /* test under mask (64bit) */
631
bcec36ea
AG		 632 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
633 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 634 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 635
636 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 637 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
638 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 639 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 640 CC_OP_MAX
641};
642
643static const char *cc_names[] = {
644 [CC_OP_CONST0] = "CC_OP_CONST0",
645 [CC_OP_CONST1] = "CC_OP_CONST1",
646 [CC_OP_CONST2] = "CC_OP_CONST2",
647 [CC_OP_CONST3] = "CC_OP_CONST3",
648 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
649 [CC_OP_STATIC] = "CC_OP_STATIC",
650 [CC_OP_NZ] = "CC_OP_NZ",
651 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
652 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
653 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
654 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
655 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
656 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
657 [CC_OP_ADD_64] = "CC_OP_ADD_64",
658 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 659 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 660 [CC_OP_SUB_64] = "CC_OP_SUB_64",
661 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 662 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 663 [CC_OP_ABS_64] = "CC_OP_ABS_64",
664 [CC_OP_NABS_64] = "CC_OP_NABS_64",
665 [CC_OP_ADD_32] = "CC_OP_ADD_32",
666 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 667 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 668 [CC_OP_SUB_32] = "CC_OP_SUB_32",
669 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 670 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 671 [CC_OP_ABS_32] = "CC_OP_ABS_32",
672 [CC_OP_NABS_32] = "CC_OP_NABS_32",
673 [CC_OP_COMP_32] = "CC_OP_COMP_32",
674 [CC_OP_COMP_64] = "CC_OP_COMP_64",
675 [CC_OP_TM_32] = "CC_OP_TM_32",
676 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 677 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
678 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 679 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 680 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 681 [CC_OP_SLA_32] = "CC_OP_SLA_32",
682 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 683 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 684};
685
686static inline const char *cc_name(int cc_op)
687{
688 return cc_names[cc_op];
689}
690
3d0a615f
TH		 691static inline void setcc(S390CPU *cpu, uint64_t cc)
692{
693 CPUS390XState *env = &cpu->env;
694
695 env->psw.mask &= ~(3ull << 44);
696 env->psw.mask |= (cc & 3) << 44;
697}
698
bcec36ea
AG		 699typedef struct LowCore
700{
701 /* prefix area: defined by architecture */
702 uint32_t ccw1[2]; /* 0x000 */
703 uint32_t ccw2[4]; /* 0x008 */
704 uint8_t pad1[0x80-0x18]; /* 0x018 */
705 uint32_t ext_params; /* 0x080 */
706 uint16_t cpu_addr; /* 0x084 */
707 uint16_t ext_int_code; /* 0x086 */
d5a103cd 708 uint16_t svc_ilen; /* 0x088 */
bcec36ea 709 uint16_t svc_code; /* 0x08a */
d5a103cd 710 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 711 uint16_t pgm_code; /* 0x08e */
712 uint32_t data_exc_code; /* 0x090 */
713 uint16_t mon_class_num; /* 0x094 */
714 uint16_t per_perc_atmid; /* 0x096 */
715 uint64_t per_address; /* 0x098 */
716 uint8_t exc_access_id; /* 0x0a0 */
717 uint8_t per_access_id; /* 0x0a1 */
718 uint8_t op_access_id; /* 0x0a2 */
719 uint8_t ar_access_id; /* 0x0a3 */
720 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
721 uint64_t trans_exc_code; /* 0x0a8 */
722 uint64_t monitor_code; /* 0x0b0 */
723 uint16_t subchannel_id; /* 0x0b8 */
724 uint16_t subchannel_nr; /* 0x0ba */
725 uint32_t io_int_parm; /* 0x0bc */
726 uint32_t io_int_word; /* 0x0c0 */
727 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
728 uint32_t stfl_fac_list; /* 0x0c8 */
729 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
730 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
731 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
732 uint32_t external_damage_code; /* 0x0f4 */
733 uint64_t failing_storage_address; /* 0x0f8 */
734 uint8_t pad6[0x120-0x100]; /* 0x100 */
735 PSW restart_old_psw; /* 0x120 */
736 PSW external_old_psw; /* 0x130 */
737 PSW svc_old_psw; /* 0x140 */
738 PSW program_old_psw; /* 0x150 */
739 PSW mcck_old_psw; /* 0x160 */
740 PSW io_old_psw; /* 0x170 */
741 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
742 PSW restart_psw; /* 0x1a0 */
743 PSW external_new_psw; /* 0x1b0 */
744 PSW svc_new_psw; /* 0x1c0 */
745 PSW program_new_psw; /* 0x1d0 */
746 PSW mcck_new_psw; /* 0x1e0 */
747 PSW io_new_psw; /* 0x1f0 */
748 PSW return_psw; /* 0x200 */
749 uint8_t irb[64]; /* 0x210 */
750 uint64_t sync_enter_timer; /* 0x250 */
751 uint64_t async_enter_timer; /* 0x258 */
752 uint64_t exit_timer; /* 0x260 */
753 uint64_t last_update_timer; /* 0x268 */
754 uint64_t user_timer; /* 0x270 */
755 uint64_t system_timer; /* 0x278 */
756 uint64_t last_update_clock; /* 0x280 */
757 uint64_t steal_clock; /* 0x288 */
758 PSW return_mcck_psw; /* 0x290 */
759 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
760 /* System info area */
761 uint64_t save_area[16]; /* 0xc00 */
762 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
763 uint64_t kernel_stack; /* 0xd40 */
764 uint64_t thread_info; /* 0xd48 */
765 uint64_t async_stack; /* 0xd50 */
766 uint64_t kernel_asce; /* 0xd58 */
767 uint64_t user_asce; /* 0xd60 */
768 uint64_t panic_stack; /* 0xd68 */
769 uint64_t user_exec_asce; /* 0xd70 */
770 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
771
772 /* SMP info area: defined by DJB */
773 uint64_t clock_comparator; /* 0xdc0 */
774 uint64_t ext_call_fast; /* 0xdc8 */
775 uint64_t percpu_offset; /* 0xdd0 */
776 uint64_t current_task; /* 0xdd8 */
777 uint32_t softirq_pending; /* 0xde0 */
778 uint32_t pad_0x0de4; /* 0xde4 */
779 uint64_t int_clock; /* 0xde8 */
780 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
781
782 /* 0xe00 is used as indicator for dump tools */
783 /* whether the kernel died with panic() or not */
784 uint32_t panic_magic; /* 0xe00 */
785
786 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
787
788 /* 64 bit extparam used for pfault, diag 250 etc */
789 uint64_t ext_params2; /* 0x11B8 */
790
791 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
792
793 /* System info area */
794
795 uint64_t floating_pt_save_area[16]; /* 0x1200 */
796 uint64_t gpregs_save_area[16]; /* 0x1280 */
797 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
798 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
799 uint32_t prefixreg_save_area; /* 0x1318 */
800 uint32_t fpt_creg_save_area; /* 0x131c */
801 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
802 uint32_t tod_progreg_save_area; /* 0x1324 */
803 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
804 uint32_t clock_comp_save_area[2]; /* 0x1330 */
805 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
806 uint32_t access_regs_save_area[16]; /* 0x1340 */
807 uint64_t cregs_save_area[16]; /* 0x1380 */
808
809 /* align to the top of the prefix area */
810
811 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 812} QEMU_PACKED LowCore;
bcec36ea
AG		 813
814/* STSI */
815#define STSI_LEVEL_MASK 0x00000000f0000000ULL
816#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
817#define STSI_LEVEL_1 0x0000000010000000ULL
818#define STSI_LEVEL_2 0x0000000020000000ULL
819#define STSI_LEVEL_3 0x0000000030000000ULL
820#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
821#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
822#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
823#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
824
825/* Basic Machine Configuration */
826struct sysib_111 {
827 uint32_t res1[8];
828 uint8_t manuf[16];
829 uint8_t type[4];
830 uint8_t res2[12];
831 uint8_t model[16];
832 uint8_t sequence[16];
833 uint8_t plant[4];
834 uint8_t res3[156];
835};
836
837/* Basic Machine CPU */
838struct sysib_121 {
839 uint32_t res1[80];
840 uint8_t sequence[16];
841 uint8_t plant[4];
842 uint8_t res2[2];
843 uint16_t cpu_addr;
844 uint8_t res3[152];
845};
846
847/* Basic Machine CPUs */
848struct sysib_122 {
849 uint8_t res1[32];
850 uint32_t capability;
851 uint16_t total_cpus;
852 uint16_t active_cpus;
853 uint16_t standby_cpus;
854 uint16_t reserved_cpus;
855 uint16_t adjustments[2026];
856};
857
858/* LPAR CPU */
859struct sysib_221 {
860 uint32_t res1[80];
861 uint8_t sequence[16];
862 uint8_t plant[4];
863 uint16_t cpu_id;
864 uint16_t cpu_addr;
865 uint8_t res3[152];
866};
867
868/* LPAR CPUs */
869struct sysib_222 {
870 uint32_t res1[32];
871 uint16_t lpar_num;
872 uint8_t res2;
873 uint8_t lcpuc;
874 uint16_t total_cpus;
875 uint16_t conf_cpus;
876 uint16_t standby_cpus;
877 uint16_t reserved_cpus;
878 uint8_t name[8];
879 uint32_t caf;
880 uint8_t res3[16];
881 uint16_t dedicated_cpus;
882 uint16_t shared_cpus;
883 uint8_t res4[180];
884};
885
886/* VM CPUs */
887struct sysib_322 {
888 uint8_t res1[31];
889 uint8_t count;
890 struct {
891 uint8_t res2[4];
892 uint16_t total_cpus;
893 uint16_t conf_cpus;
894 uint16_t standby_cpus;
895 uint16_t reserved_cpus;
896 uint8_t name[8];
897 uint32_t caf;
898 uint8_t cpi[16];
899 uint8_t res3[24];
900 } vm[8];
901 uint8_t res4[3552];
902};
903
904/* MMU defines */
905#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
906#define _ASCE_SUBSPACE 0x200 /* subspace group control */
907#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
908#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
909#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
910#define _ASCE_REAL_SPACE 0x20 /* real space control */
911#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
912#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
913#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
914#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
915#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
916#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
917
918#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
919#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
920#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
921#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
922#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
923#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
924#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
925
926#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
927#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
928#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
929
930#define _PAGE_RO 0x200 /* HW read-only bit */
931#define _PAGE_INVALID 0x400 /* HW invalid bit */
932
b9959138
AG		 933#define SK_C (0x1 << 1)
934#define SK_R (0x1 << 2)
935#define SK_F (0x1 << 3)
936#define SK_ACC_MASK (0xf << 4)
bcec36ea 937
bcec36ea
AG		 938#define SIGP_SENSE 0x01
939#define SIGP_EXTERNAL_CALL 0x02
940#define SIGP_EMERGENCY 0x03
941#define SIGP_START 0x04
942#define SIGP_STOP 0x05
943#define SIGP_RESTART 0x06
944#define SIGP_STOP_STORE_STATUS 0x09
945#define SIGP_INITIAL_CPU_RESET 0x0b
946#define SIGP_CPU_RESET 0x0c
947#define SIGP_SET_PREFIX 0x0d
948#define SIGP_STORE_STATUS_ADDR 0x0e
949#define SIGP_SET_ARCH 0x12
950
951/* cpu status bits */
952#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
953#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
954#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
955#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
956#define SIGP_STAT_STOPPED 0x00000040UL
957#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
958#define SIGP_STAT_CHECK_STOP 0x00000010UL
959#define SIGP_STAT_INOPERATIVE 0x00000004UL
960#define SIGP_STAT_INVALID_ORDER 0x00000002UL
961#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
962
a4e3ad19
AF		 963void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
964int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 965 target_ulong *raddr, int *flags);
6e252802 966int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 967uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 968 uint64_t vr);
969
970#define TARGET_HAS_ICE 1
971
972/* The value of the TOD clock for 1.1.1970. */
973#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
974
975/* Converts ns to s390's clock format */
976static inline uint64_t time2tod(uint64_t ns) {
977 return (ns << 9) / 125;
978}
979
f9466733 980static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 981 uint64_t param64)
982{
f9466733
AF		 983 CPUS390XState *env = &cpu->env;
984
bcec36ea
AG		 985 if (env->ext_index == MAX_EXT_QUEUE - 1) {
986 /* ugh - can't queue anymore. Let's drop. */
987 return;
988 }
989
990 env->ext_index++;
991 assert(env->ext_index < MAX_EXT_QUEUE);
992
993 env->ext_queue[env->ext_index].code = code;
994 env->ext_queue[env->ext_index].param = param;
995 env->ext_queue[env->ext_index].param64 = param64;
996
997 env->pending_int |= INTERRUPT_EXT;
c3affe56 998 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 999}
10c339a0 1000
f9466733 1001static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 1002 uint16_t subchannel_number,
1003 uint32_t io_int_parm, uint32_t io_int_word)
1004{
f9466733 1005 CPUS390XState *env = &cpu->env;
91b0a8f3 1006 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1007
1008 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1009 /* ugh - can't queue anymore. Let's drop. */
1010 return;
1011 }
1012
1013 env->io_index[isc]++;
1014 assert(env->io_index[isc] < MAX_IO_QUEUE);
1015
1016 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1017 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1018 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1019 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1020
1021 env->pending_int |= INTERRUPT_IO;
c3affe56 1022 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1023}
1024
f9466733 1025static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1026{
f9466733
AF		 1027 CPUS390XState *env = &cpu->env;
1028
5d69c547
CH		 1029 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1030 /* ugh - can't queue anymore. Let's drop. */
1031 return;
1032 }
1033
1034 env->mchk_index++;
1035 assert(env->mchk_index < MAX_MCHK_QUEUE);
1036
1037 env->mchk_queue[env->mchk_index].type = 1;
1038
1039 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1040 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1041}
1042
e72ca652 1043/* fpu_helper.c */
e72ca652
BS		 1044uint32_t set_cc_nz_f32(float32 v);
1045uint32_t set_cc_nz_f64(float64 v);
587626f8 1046uint32_t set_cc_nz_f128(float128 v);
e72ca652 1047
aea1e885 1048/* misc_helper.c */
268846ba
ED		 1049#ifndef CONFIG_USER_ONLY
1050void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1051#endif
d5a103cd 1052void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1053void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1054 uintptr_t retaddr);
a78b0504 1055
09b99878
CH		 1056#ifdef CONFIG_KVM
1057void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1058 uint16_t subchannel_nr, uint32_t io_int_parm,
1059 uint32_t io_int_word);
1060void kvm_s390_crw_mchk(S390CPU *cpu);
1061void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1062int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1063 int vq, bool assign);
7f7f9752 1064int kvm_s390_cpu_restart(S390CPU *cpu);
09b99878 1065#else
df1fe5bb
CH		 1066static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1067 uint16_t subchannel_id,
1068 uint16_t subchannel_nr,
1069 uint32_t io_int_parm,
1070 uint32_t io_int_word)
1071{
1072}
1073static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1074{
1075}
09b99878
CH		 1076static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1077{
1078}
cc3ac9c4
CH		 1079static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1080 uint32_t sch, int vq,
b4436a0b
CH		 1081 bool assign)
1082{
1083 return -ENOSYS;
1084}
7f7f9752
ED		 1085static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1086{
1087 return -ENOSYS;
1088}
09b99878 1089#endif
df1fe5bb 1090
7f7f9752
ED		 1091static inline int s390_cpu_restart(S390CPU *cpu)
1092{
1093 if (kvm_enabled()) {
1094 return kvm_s390_cpu_restart(cpu);
1095 }
1096 return -ENOSYS;
1097}
1098
df1fe5bb
CH		 1099static inline void s390_io_interrupt(S390CPU *cpu,
1100 uint16_t subchannel_id,
1101 uint16_t subchannel_nr,
1102 uint32_t io_int_parm,
1103 uint32_t io_int_word)
1104{
1105 if (kvm_enabled()) {
1106 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1107 io_int_word);
1108 } else {
f9466733 1109 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
df1fe5bb
CH		 1110 io_int_word);
1111 }
1112}
1113
1114static inline void s390_crw_mchk(S390CPU *cpu)
1115{
1116 if (kvm_enabled()) {
1117 kvm_s390_crw_mchk(cpu);
1118 } else {
f9466733 1119 cpu_inject_crw_mchk(cpu);
df1fe5bb
CH		 1120 }
1121}
1122
cc3ac9c4
CH		 1123static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1124 uint32_t sch_id, int vq,
b4436a0b
CH		 1125 bool assign)
1126{
1127 if (kvm_enabled()) {
cc3ac9c4 1128 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1129 } else {
1130 return -ENOSYS;
1131 }
1132}
1133
10ec5117 1134#endif
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