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target-s390x: fix PSW value on dynamical exception from helpers
[mirror_qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f 83 uint64_t regs[16]; /* GP registers */
fcb79802
EF		 84 /*
85 * The floating point registers are part of the vector registers.
86 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
87 */
88 CPU_DoubleU vregs[32][2]; /* vector registers */
1ac5889f 89 uint32_t aregs[16]; /* access registers */
10ec5117 90
1ac5889f
RH		 91 uint32_t fpc; /* floating-point control register */
92 uint32_t cc_op;
10ec5117 93
10ec5117
AG		 94 float_status fpu_status; /* passed to softfloat lib */
95
1ac5889f
RH		 96 /* The low part of a 128-bit return, or remainder of a divide. */
97 uint64_t retxl;
98
bcec36ea 99 PSW psw;
10ec5117 100
bcec36ea
AG		 101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
10ec5117
AG		 104
105 uint64_t __excp_addr;
bcec36ea
AG		 106 uint64_t psa;
107
108 uint32_t int_pgm_code;
d5a103cd 109 uint32_t int_pgm_ilen;
bcec36ea
AG		 110
111 uint32_t int_svc_code;
d5a103cd 112 uint32_t int_svc_ilen;
bcec36ea
AG		 113
114 uint64_t cregs[16]; /* control registers */
115
bcec36ea 116 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 117 IOIntQueue io_queue[MAX_IO_QUEUE][8];
118 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 119
5d69c547 120 int pending_int;
4e836781 121 int ext_index;
5d69c547
CH		 122 int io_index[8];
123 int mchk_index;
124
125 uint64_t ckc;
126 uint64_t cputm;
127 uint32_t todpr;
4e836781 128
819bd309
DD		 129 uint64_t pfault_token;
130 uint64_t pfault_compare;
131 uint64_t pfault_select;
132
44b0c0bb
CB		 133 uint64_t gbea;
134 uint64_t pp;
135
4e836781
AG		 136 CPU_COMMON
137
bcec36ea
AG		 138 /* reset does memset(0) up to here */
139
7f745b31
RH		 140 uint32_t cpu_num;
141 uint32_t machine_type;
142
bcec36ea
AG		 143 uint8_t *storage_keys;
144
145 uint64_t tod_offset;
146 uint64_t tod_basetime;
147 QEMUTimer *tod_timer;
148
149 QEMUTimer *cpu_timer;
75973bfe
DH		 150
151 /*
152 * The cpu state represents the logical state of a cpu. In contrast to other
153 * architectures, there is a difference between a halt and a stop on s390.
154 * If all cpus are either stopped (including check stop) or in the disabled
155 * wait state, the vm can be shut down.
156 */
157#define CPU_STATE_UNINITIALIZED 0x00
158#define CPU_STATE_STOPPED 0x01
159#define CPU_STATE_CHECK_STOP 0x02
160#define CPU_STATE_OPERATING 0x03
161#define CPU_STATE_LOAD 0x04
162 uint8_t cpu_state;
163
18ff9494
DH		 164 /* currently processed sigp order */
165 uint8_t sigp_order;
166
10ec5117
AG		 167} CPUS390XState;
168
c498d8e3
EF		 169static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
170{
fcb79802 171 return &cs->vregs[nr][0];
c498d8e3
EF		 172}
173
564b863d 174#include "cpu-qom.h"
3d0a615f 175#include <sysemu/kvm.h>
564b863d 176
7b18aad5
CH		 177/* distinguish between 24 bit and 31 bit addressing */
178#define HIGH_ORDER_BIT 0x80000000
179
bcec36ea
AG		 180/* Interrupt Codes */
181/* Program Interrupts */
182#define PGM_OPERATION 0x0001
183#define PGM_PRIVILEGED 0x0002
184#define PGM_EXECUTE 0x0003
185#define PGM_PROTECTION 0x0004
186#define PGM_ADDRESSING 0x0005
187#define PGM_SPECIFICATION 0x0006
188#define PGM_DATA 0x0007
189#define PGM_FIXPT_OVERFLOW 0x0008
190#define PGM_FIXPT_DIVIDE 0x0009
191#define PGM_DEC_OVERFLOW 0x000a
192#define PGM_DEC_DIVIDE 0x000b
193#define PGM_HFP_EXP_OVERFLOW 0x000c
194#define PGM_HFP_EXP_UNDERFLOW 0x000d
195#define PGM_HFP_SIGNIFICANCE 0x000e
196#define PGM_HFP_DIVIDE 0x000f
197#define PGM_SEGMENT_TRANS 0x0010
198#define PGM_PAGE_TRANS 0x0011
199#define PGM_TRANS_SPEC 0x0012
200#define PGM_SPECIAL_OP 0x0013
201#define PGM_OPERAND 0x0015
202#define PGM_TRACE_TABLE 0x0016
203#define PGM_SPACE_SWITCH 0x001c
204#define PGM_HFP_SQRT 0x001d
205#define PGM_PC_TRANS_SPEC 0x001f
206#define PGM_AFX_TRANS 0x0020
207#define PGM_ASX_TRANS 0x0021
208#define PGM_LX_TRANS 0x0022
209#define PGM_EX_TRANS 0x0023
210#define PGM_PRIM_AUTH 0x0024
211#define PGM_SEC_AUTH 0x0025
212#define PGM_ALET_SPEC 0x0028
213#define PGM_ALEN_SPEC 0x0029
214#define PGM_ALE_SEQ 0x002a
215#define PGM_ASTE_VALID 0x002b
216#define PGM_ASTE_SEQ 0x002c
217#define PGM_EXT_AUTH 0x002d
218#define PGM_STACK_FULL 0x0030
219#define PGM_STACK_EMPTY 0x0031
220#define PGM_STACK_SPEC 0x0032
221#define PGM_STACK_TYPE 0x0033
222#define PGM_STACK_OP 0x0034
223#define PGM_ASCE_TYPE 0x0038
224#define PGM_REG_FIRST_TRANS 0x0039
225#define PGM_REG_SEC_TRANS 0x003a
226#define PGM_REG_THIRD_TRANS 0x003b
227#define PGM_MONITOR 0x0040
228#define PGM_PER 0x0080
229#define PGM_CRYPTO 0x0119
230
231/* External Interrupts */
232#define EXT_INTERRUPT_KEY 0x0040
233#define EXT_CLOCK_COMP 0x1004
234#define EXT_CPU_TIMER 0x1005
235#define EXT_MALFUNCTION 0x1200
236#define EXT_EMERGENCY 0x1201
237#define EXT_EXTERNAL_CALL 0x1202
238#define EXT_ETR 0x1406
239#define EXT_SERVICE 0x2401
240#define EXT_VIRTIO 0x2603
241
242/* PSW defines */
243#undef PSW_MASK_PER
244#undef PSW_MASK_DAT
245#undef PSW_MASK_IO
246#undef PSW_MASK_EXT
247#undef PSW_MASK_KEY
248#undef PSW_SHIFT_KEY
249#undef PSW_MASK_MCHECK
250#undef PSW_MASK_WAIT
251#undef PSW_MASK_PSTATE
252#undef PSW_MASK_ASC
253#undef PSW_MASK_CC
254#undef PSW_MASK_PM
255#undef PSW_MASK_64
29c6157c
CB		 256#undef PSW_MASK_32
257#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 258
259#define PSW_MASK_PER 0x4000000000000000ULL
260#define PSW_MASK_DAT 0x0400000000000000ULL
261#define PSW_MASK_IO 0x0200000000000000ULL
262#define PSW_MASK_EXT 0x0100000000000000ULL
263#define PSW_MASK_KEY 0x00F0000000000000ULL
264#define PSW_SHIFT_KEY 56
265#define PSW_MASK_MCHECK 0x0004000000000000ULL
266#define PSW_MASK_WAIT 0x0002000000000000ULL
267#define PSW_MASK_PSTATE 0x0001000000000000ULL
268#define PSW_MASK_ASC 0x0000C00000000000ULL
269#define PSW_MASK_CC 0x0000300000000000ULL
270#define PSW_MASK_PM 0x00000F0000000000ULL
271#define PSW_MASK_64 0x0000000100000000ULL
272#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 273#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 274
275#undef PSW_ASC_PRIMARY
276#undef PSW_ASC_ACCREG
277#undef PSW_ASC_SECONDARY
278#undef PSW_ASC_HOME
279
280#define PSW_ASC_PRIMARY 0x0000000000000000ULL
281#define PSW_ASC_ACCREG 0x0000400000000000ULL
282#define PSW_ASC_SECONDARY 0x0000800000000000ULL
283#define PSW_ASC_HOME 0x0000C00000000000ULL
284
285/* tb flags */
286
287#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
288#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
289#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
290#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
291#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
292#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
293#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
294#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
295#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
296#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
297#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
298#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
299#define FLAG_MASK_32 0x00001000
300
c4400206 301/* Control register 0 bits */
c3edd628 302#define CR0_LOWPROT 0x0000000010000000ULL
c4400206
TH		 303#define CR0_EDAT 0x0000000000800000ULL
304
a4e3ad19 305static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 306{
bcec36ea
AG		 307 if (env->psw.mask & PSW_MASK_PSTATE) {
308 return 1;
309 }
310
10c339a0
AG		 311 return 0;
312}
313
a4e3ad19 314static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 315 target_ulong *cs_base, int *flags)
316{
317 *pc = env->psw.addr;
318 *cs_base = 0;
319 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
320 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
321}
322
d5a103cd
RH		 323/* While the PoO talks about ILC (a number between 1-3) what is actually
324 stored in LowCore is shifted left one bit (an even between 2-6). As
325 this is the actual length of the insn and therefore more useful, that
326 is what we want to pass around and manipulate. To make sure that we
327 have applied this distinction universally, rename the "ILC" to "ILEN". */
328static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 329{
330 switch (opc >> 6) {
331 case 0:
d5a103cd 332 return 2;
bcec36ea
AG		 333 case 1:
334 case 2:
d5a103cd
RH		 335 return 4;
336 default:
337 return 6;
bcec36ea 338 }
bcec36ea
AG		 339}
340
d5a103cd
RH		 341#ifndef CONFIG_USER_ONLY
342/* In several cases of runtime exceptions, we havn't recorded the true
343 instruction length. Use these codes when raising exceptions in order
344 to re-compute the length by examining the insn in memory. */
345#define ILEN_LATER 0x20
346#define ILEN_LATER_INC 0x21
dfebd7a7 347void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
d5a103cd 348#endif
bcec36ea 349
564b863d 350S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 351void s390x_translate_init(void);
10ec5117 352int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 353
354/* you can call this signal handler from your SIGBUS and SIGSEGV
355 signal handlers to inform the virtual CPU of exceptions. non zero
356 is returned if the signal was handled by the virtual CPU. */
357int cpu_s390x_signal_handler(int host_signum, void *pinfo,
358 void *puc);
7510454e
AF		 359int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
360 int mmu_idx);
10ec5117 361
db1c8f53 362#include "ioinst.h"
52705890 363
3f10341f 364
10c339a0 365#ifndef CONFIG_USER_ONLY
3f10341f
DH		 366void do_restart_interrupt(CPUS390XState *env);
367
6cb1e49d
AY		 368static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
369 uint8_t *ar)
7b18aad5
CH		 370{
371 hwaddr addr = 0;
372 uint8_t reg;
373
374 reg = ipb >> 28;
375 if (reg > 0) {
376 addr = env->regs[reg];
377 }
378 addr += (ipb >> 16) & 0xfff;
6cb1e49d
AY		 379 if (ar) {
380 *ar = reg;
381 }
7b18aad5
CH		 382
383 return addr;
384}
385
638129ff
CH		 386/* Base/displacement are at the same locations. */
387#define decode_basedisp_rs decode_basedisp_s
388
85ca3371
DH		 389/* helper functions for run_on_cpu() */
390static inline void s390_do_cpu_reset(void *arg)
391{
392 CPUState *cs = arg;
393 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
394
395 scc->cpu_reset(cs);
396}
397static inline void s390_do_cpu_full_reset(void *arg)
398{
399 CPUState *cs = arg;
400
401 cpu_reset(cs);
402}
403
8f22e0df
AF		 404void s390x_tod_timer(void *opaque);
405void s390x_cpu_timer(void *opaque);
406
28e942f8 407int s390_virtio_hypercall(CPUS390XState *env);
de13d216 408void s390_virtio_irq(int config_change, uint64_t token);
bcec36ea 409
1f206266 410#ifdef CONFIG_KVM
de13d216
CH		 411void kvm_s390_virtio_irq(int config_change, uint64_t token);
412void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH		 413void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
414void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 415int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
801cdd35 416void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
6cb1e49d
AY		 417int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
418 int len, bool is_write);
3f9e59bb
JH		 419int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
420int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
1f206266 421#else
de13d216 422static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
1f206266
AG		 423{
424}
de13d216 425static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH		 426{
427}
3f9e59bb
JH		 428static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
429{
430 return -ENOSYS;
431}
432static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
433{
434 return -ENOSYS;
435}
6cb1e49d
AY		 436static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
437 void *hostbuf, int len, bool is_write)
a9bcd1b8
TH		 438{
439 return -ENOSYS;
440}
801cdd35
TH		 441static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
442 uint64_t te_code)
443{
444}
1f206266 445#endif
3f9e59bb
JH		 446
447static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
448{
449 if (kvm_enabled()) {
450 return kvm_s390_get_clock(tod_high, tod_low);
451 }
452 /* Fixme TCG */
453 *tod_high = 0;
454 *tod_low = 0;
455 return 0;
456}
457
458static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
459{
460 if (kvm_enabled()) {
461 return kvm_s390_set_clock(tod_high, tod_low);
462 }
463 /* Fixme TCG */
464 return 0;
465}
466
45fa769b 467S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH		 468unsigned int s390_cpu_halt(S390CPU *cpu);
469void s390_cpu_unhalt(S390CPU *cpu);
470unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
18ff9494
DH		 471static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
472{
473 return cpu->env.cpu_state;
474}
bcec36ea 475
3f9e59bb
JH		 476void gtod_save(QEMUFile *f, void *opaque);
477int gtod_load(QEMUFile *f, void *opaque, int version_id);
478
000a1a38
CB		 479/* service interrupts are floating therefore we must not pass an cpustate */
480void s390_sclp_extint(uint32_t parm);
481
d1ff903c 482/* from s390-virtio-bus */
a8170e5e 483extern const hwaddr virtio_size;
d1ff903c 484
ef81522b 485#else
eb24f7c6
DH		 486static inline unsigned int s390_cpu_halt(S390CPU *cpu)
487{
488 return 0;
489}
490
491static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG		 492{
493}
494
eb24f7c6 495static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG		 496{
497 return 0;
498}
10c339a0 499#endif
bcec36ea
AG		 500void cpu_lock(void);
501void cpu_unlock(void);
10c339a0 502
7b18aad5
CH		 503typedef struct SubchDev SubchDev;
504
df1fe5bb 505#ifndef CONFIG_USER_ONLY
4e872a3f 506extern void io_subsystem_reset(void);
df1fe5bb
CH		 507SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
508 uint16_t schid);
509bool css_subch_visible(SubchDev *sch);
510void css_conditional_io_interrupt(SubchDev *sch);
511int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 512bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
bffd09cd 513int css_do_msch(SubchDev *sch, const SCHIB *schib);
df1fe5bb
CH		 514int css_do_xsch(SubchDev *sch);
515int css_do_csch(SubchDev *sch);
516int css_do_hsch(SubchDev *sch);
517int css_do_ssch(SubchDev *sch, ORB *orb);
b7b6348a
TH		 518int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
519void css_do_tsch_update_subch(SubchDev *sch);
df1fe5bb 520int css_do_stcrw(CRW *crw);
7f74f0aa 521void css_undo_stcrw(CRW *crw);
50c8d9bf 522int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 523int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
524 int rfmt, void *buf);
525void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
526int css_enable_mcsse(void);
527int css_enable_mss(void);
528int css_do_rsch(SubchDev *sch);
529int css_do_rchp(uint8_t cssid, uint8_t chpid);
530bool css_present(uint8_t cssid);
df1fe5bb 531#endif
7b18aad5 532
2994fd96 533#define cpu_init(model) CPU(cpu_s390x_init(model))
10ec5117
AG		 534#define cpu_exec cpu_s390x_exec
535#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 536#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 537
904e5fd5
VM		 538void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
539#define cpu_list s390_cpu_list
540
022c62cb 541#include "exec/exec-all.h"
bcec36ea 542
bcec36ea
AG		 543#define EXCP_EXT 1 /* external interrupt */
544#define EXCP_SVC 2 /* supervisor call (syscall) */
545#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 546#define EXCP_IO 7 /* I/O interrupt */
547#define EXCP_MCHK 8 /* machine check */
bcec36ea 548
bcec36ea
AG		 549#define INTERRUPT_EXT (1 << 0)
550#define INTERRUPT_TOD (1 << 1)
551#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 552#define INTERRUPT_IO (1 << 3)
553#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 554
555/* Program Status Word. */
556#define S390_PSWM_REGNUM 0
557#define S390_PSWA_REGNUM 1
558/* General Purpose Registers. */
559#define S390_R0_REGNUM 2
560#define S390_R1_REGNUM 3
561#define S390_R2_REGNUM 4
562#define S390_R3_REGNUM 5
563#define S390_R4_REGNUM 6
564#define S390_R5_REGNUM 7
565#define S390_R6_REGNUM 8
566#define S390_R7_REGNUM 9
567#define S390_R8_REGNUM 10
568#define S390_R9_REGNUM 11
569#define S390_R10_REGNUM 12
570#define S390_R11_REGNUM 13
571#define S390_R12_REGNUM 14
572#define S390_R13_REGNUM 15
573#define S390_R14_REGNUM 16
574#define S390_R15_REGNUM 17
73d510c9
DH		 575/* Total Core Registers. */
576#define S390_NUM_CORE_REGS 18
10c339a0 577
bcec36ea
AG		 578/* CC optimization */
579
580enum cc_op {
581 CC_OP_CONST0 = 0, /* CC is 0 */
582 CC_OP_CONST1, /* CC is 1 */
583 CC_OP_CONST2, /* CC is 2 */
584 CC_OP_CONST3, /* CC is 3 */
585
586 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
587 CC_OP_STATIC, /* CC value is env->cc_op */
588
589 CC_OP_NZ, /* env->cc_dst != 0 */
590 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
591 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
592 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
593 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
594 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
595 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
596
597 CC_OP_ADD_64, /* overflow on add (64bit) */
598 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 599 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 600 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
601 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 602 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 603 CC_OP_ABS_64, /* sign eval on abs (64bit) */
604 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
605
606 CC_OP_ADD_32, /* overflow on add (32bit) */
607 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 608 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 609 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
610 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 611 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 612 CC_OP_ABS_32, /* sign eval on abs (64bit) */
613 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
614
615 CC_OP_COMP_32, /* complement */
616 CC_OP_COMP_64, /* complement */
617
618 CC_OP_TM_32, /* test under mask (32bit) */
619 CC_OP_TM_64, /* test under mask (64bit) */
620
bcec36ea
AG		 621 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
622 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 623 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 624
625 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 626 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
627 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 628 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 629 CC_OP_MAX
630};
631
632static const char *cc_names[] = {
633 [CC_OP_CONST0] = "CC_OP_CONST0",
634 [CC_OP_CONST1] = "CC_OP_CONST1",
635 [CC_OP_CONST2] = "CC_OP_CONST2",
636 [CC_OP_CONST3] = "CC_OP_CONST3",
637 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
638 [CC_OP_STATIC] = "CC_OP_STATIC",
639 [CC_OP_NZ] = "CC_OP_NZ",
640 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
641 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
642 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
643 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
644 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
645 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
646 [CC_OP_ADD_64] = "CC_OP_ADD_64",
647 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 648 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 649 [CC_OP_SUB_64] = "CC_OP_SUB_64",
650 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 651 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 652 [CC_OP_ABS_64] = "CC_OP_ABS_64",
653 [CC_OP_NABS_64] = "CC_OP_NABS_64",
654 [CC_OP_ADD_32] = "CC_OP_ADD_32",
655 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 656 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 657 [CC_OP_SUB_32] = "CC_OP_SUB_32",
658 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 659 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 660 [CC_OP_ABS_32] = "CC_OP_ABS_32",
661 [CC_OP_NABS_32] = "CC_OP_NABS_32",
662 [CC_OP_COMP_32] = "CC_OP_COMP_32",
663 [CC_OP_COMP_64] = "CC_OP_COMP_64",
664 [CC_OP_TM_32] = "CC_OP_TM_32",
665 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 666 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
667 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 668 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 669 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 670 [CC_OP_SLA_32] = "CC_OP_SLA_32",
671 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 672 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 673};
674
675static inline const char *cc_name(int cc_op)
676{
677 return cc_names[cc_op];
678}
679
3d0a615f
TH		 680static inline void setcc(S390CPU *cpu, uint64_t cc)
681{
682 CPUS390XState *env = &cpu->env;
683
684 env->psw.mask &= ~(3ull << 44);
685 env->psw.mask |= (cc & 3) << 44;
686}
687
bcec36ea
AG		 688typedef struct LowCore
689{
690 /* prefix area: defined by architecture */
691 uint32_t ccw1[2]; /* 0x000 */
692 uint32_t ccw2[4]; /* 0x008 */
693 uint8_t pad1[0x80-0x18]; /* 0x018 */
694 uint32_t ext_params; /* 0x080 */
695 uint16_t cpu_addr; /* 0x084 */
696 uint16_t ext_int_code; /* 0x086 */
d5a103cd 697 uint16_t svc_ilen; /* 0x088 */
bcec36ea 698 uint16_t svc_code; /* 0x08a */
d5a103cd 699 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 700 uint16_t pgm_code; /* 0x08e */
701 uint32_t data_exc_code; /* 0x090 */
702 uint16_t mon_class_num; /* 0x094 */
703 uint16_t per_perc_atmid; /* 0x096 */
704 uint64_t per_address; /* 0x098 */
705 uint8_t exc_access_id; /* 0x0a0 */
706 uint8_t per_access_id; /* 0x0a1 */
707 uint8_t op_access_id; /* 0x0a2 */
708 uint8_t ar_access_id; /* 0x0a3 */
709 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
710 uint64_t trans_exc_code; /* 0x0a8 */
711 uint64_t monitor_code; /* 0x0b0 */
712 uint16_t subchannel_id; /* 0x0b8 */
713 uint16_t subchannel_nr; /* 0x0ba */
714 uint32_t io_int_parm; /* 0x0bc */
715 uint32_t io_int_word; /* 0x0c0 */
716 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
717 uint32_t stfl_fac_list; /* 0x0c8 */
718 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
719 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
720 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
721 uint32_t external_damage_code; /* 0x0f4 */
722 uint64_t failing_storage_address; /* 0x0f8 */
723 uint8_t pad6[0x120-0x100]; /* 0x100 */
724 PSW restart_old_psw; /* 0x120 */
725 PSW external_old_psw; /* 0x130 */
726 PSW svc_old_psw; /* 0x140 */
727 PSW program_old_psw; /* 0x150 */
728 PSW mcck_old_psw; /* 0x160 */
729 PSW io_old_psw; /* 0x170 */
730 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
3f10341f 731 PSW restart_new_psw; /* 0x1a0 */
bcec36ea
AG		 732 PSW external_new_psw; /* 0x1b0 */
733 PSW svc_new_psw; /* 0x1c0 */
734 PSW program_new_psw; /* 0x1d0 */
735 PSW mcck_new_psw; /* 0x1e0 */
736 PSW io_new_psw; /* 0x1f0 */
737 PSW return_psw; /* 0x200 */
738 uint8_t irb[64]; /* 0x210 */
739 uint64_t sync_enter_timer; /* 0x250 */
740 uint64_t async_enter_timer; /* 0x258 */
741 uint64_t exit_timer; /* 0x260 */
742 uint64_t last_update_timer; /* 0x268 */
743 uint64_t user_timer; /* 0x270 */
744 uint64_t system_timer; /* 0x278 */
745 uint64_t last_update_clock; /* 0x280 */
746 uint64_t steal_clock; /* 0x288 */
747 PSW return_mcck_psw; /* 0x290 */
748 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
749 /* System info area */
750 uint64_t save_area[16]; /* 0xc00 */
751 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
752 uint64_t kernel_stack; /* 0xd40 */
753 uint64_t thread_info; /* 0xd48 */
754 uint64_t async_stack; /* 0xd50 */
755 uint64_t kernel_asce; /* 0xd58 */
756 uint64_t user_asce; /* 0xd60 */
757 uint64_t panic_stack; /* 0xd68 */
758 uint64_t user_exec_asce; /* 0xd70 */
759 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
760
761 /* SMP info area: defined by DJB */
762 uint64_t clock_comparator; /* 0xdc0 */
763 uint64_t ext_call_fast; /* 0xdc8 */
764 uint64_t percpu_offset; /* 0xdd0 */
765 uint64_t current_task; /* 0xdd8 */
766 uint32_t softirq_pending; /* 0xde0 */
767 uint32_t pad_0x0de4; /* 0xde4 */
768 uint64_t int_clock; /* 0xde8 */
769 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
770
771 /* 0xe00 is used as indicator for dump tools */
772 /* whether the kernel died with panic() or not */
773 uint32_t panic_magic; /* 0xe00 */
774
775 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
776
777 /* 64 bit extparam used for pfault, diag 250 etc */
778 uint64_t ext_params2; /* 0x11B8 */
779
780 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
781
782 /* System info area */
783
784 uint64_t floating_pt_save_area[16]; /* 0x1200 */
785 uint64_t gpregs_save_area[16]; /* 0x1280 */
786 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
787 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
788 uint32_t prefixreg_save_area; /* 0x1318 */
789 uint32_t fpt_creg_save_area; /* 0x131c */
790 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
791 uint32_t tod_progreg_save_area; /* 0x1324 */
792 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
793 uint32_t clock_comp_save_area[2]; /* 0x1330 */
794 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
795 uint32_t access_regs_save_area[16]; /* 0x1340 */
796 uint64_t cregs_save_area[16]; /* 0x1380 */
797
798 /* align to the top of the prefix area */
799
800 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 801} QEMU_PACKED LowCore;
bcec36ea
AG		 802
803/* STSI */
804#define STSI_LEVEL_MASK 0x00000000f0000000ULL
805#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
806#define STSI_LEVEL_1 0x0000000010000000ULL
807#define STSI_LEVEL_2 0x0000000020000000ULL
808#define STSI_LEVEL_3 0x0000000030000000ULL
809#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
810#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
811#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
812#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
813
814/* Basic Machine Configuration */
815struct sysib_111 {
816 uint32_t res1[8];
817 uint8_t manuf[16];
818 uint8_t type[4];
819 uint8_t res2[12];
820 uint8_t model[16];
821 uint8_t sequence[16];
822 uint8_t plant[4];
823 uint8_t res3[156];
824};
825
826/* Basic Machine CPU */
827struct sysib_121 {
828 uint32_t res1[80];
829 uint8_t sequence[16];
830 uint8_t plant[4];
831 uint8_t res2[2];
832 uint16_t cpu_addr;
833 uint8_t res3[152];
834};
835
836/* Basic Machine CPUs */
837struct sysib_122 {
838 uint8_t res1[32];
839 uint32_t capability;
840 uint16_t total_cpus;
841 uint16_t active_cpus;
842 uint16_t standby_cpus;
843 uint16_t reserved_cpus;
844 uint16_t adjustments[2026];
845};
846
847/* LPAR CPU */
848struct sysib_221 {
849 uint32_t res1[80];
850 uint8_t sequence[16];
851 uint8_t plant[4];
852 uint16_t cpu_id;
853 uint16_t cpu_addr;
854 uint8_t res3[152];
855};
856
857/* LPAR CPUs */
858struct sysib_222 {
859 uint32_t res1[32];
860 uint16_t lpar_num;
861 uint8_t res2;
862 uint8_t lcpuc;
863 uint16_t total_cpus;
864 uint16_t conf_cpus;
865 uint16_t standby_cpus;
866 uint16_t reserved_cpus;
867 uint8_t name[8];
868 uint32_t caf;
869 uint8_t res3[16];
870 uint16_t dedicated_cpus;
871 uint16_t shared_cpus;
872 uint8_t res4[180];
873};
874
875/* VM CPUs */
876struct sysib_322 {
877 uint8_t res1[31];
878 uint8_t count;
879 struct {
880 uint8_t res2[4];
881 uint16_t total_cpus;
882 uint16_t conf_cpus;
883 uint16_t standby_cpus;
884 uint16_t reserved_cpus;
885 uint8_t name[8];
886 uint32_t caf;
887 uint8_t cpi[16];
f07177a5
ET		 888 uint8_t res5[3];
889 uint8_t ext_name_encoding;
890 uint32_t res3;
891 uint8_t uuid[16];
bcec36ea 892 } vm[8];
f07177a5
ET		 893 uint8_t res4[1504];
894 uint8_t ext_names[8][256];
bcec36ea
AG		 895};
896
897/* MMU defines */
898#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
899#define _ASCE_SUBSPACE 0x200 /* subspace group control */
900#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
901#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
902#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
903#define _ASCE_REAL_SPACE 0x20 /* real space control */
904#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
905#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
906#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
907#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
908#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
909#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
910
911#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
43d49b01 912#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
5d180439 913#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
bcec36ea
AG		 914#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
915#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
916#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
917#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
918#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
919#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
920
921#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 922#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG		 923#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
924#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
925
926#define _PAGE_RO 0x200 /* HW read-only bit */
927#define _PAGE_INVALID 0x400 /* HW invalid bit */
b4ecbf80 928#define _PAGE_RES0 0x800 /* bit must be zero */
bcec36ea 929
b9959138
AG		 930#define SK_C (0x1 << 1)
931#define SK_R (0x1 << 2)
932#define SK_F (0x1 << 3)
933#define SK_ACC_MASK (0xf << 4)
bcec36ea 934
5172b780 935/* SIGP order codes */
bcec36ea
AG		 936#define SIGP_SENSE 0x01
937#define SIGP_EXTERNAL_CALL 0x02
938#define SIGP_EMERGENCY 0x03
939#define SIGP_START 0x04
940#define SIGP_STOP 0x05
941#define SIGP_RESTART 0x06
942#define SIGP_STOP_STORE_STATUS 0x09
943#define SIGP_INITIAL_CPU_RESET 0x0b
944#define SIGP_CPU_RESET 0x0c
945#define SIGP_SET_PREFIX 0x0d
946#define SIGP_STORE_STATUS_ADDR 0x0e
947#define SIGP_SET_ARCH 0x12
abec5356 948#define SIGP_STORE_ADTL_STATUS 0x17
bcec36ea 949
5172b780
DH		 950/* SIGP condition codes */
951#define SIGP_CC_ORDER_CODE_ACCEPTED 0
952#define SIGP_CC_STATUS_STORED 1
953#define SIGP_CC_BUSY 2
954#define SIGP_CC_NOT_OPERATIONAL 3
955
956/* SIGP status bits */
bcec36ea
AG		 957#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
958#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
959#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
960#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
961#define SIGP_STAT_STOPPED 0x00000040UL
962#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
963#define SIGP_STAT_CHECK_STOP 0x00000010UL
964#define SIGP_STAT_INOPERATIVE 0x00000004UL
965#define SIGP_STAT_INVALID_ORDER 0x00000002UL
966#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
967
18ff9494
DH		 968/* SIGP SET ARCHITECTURE modes */
969#define SIGP_MODE_ESA_S390 0
970#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
971#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
972
a4e3ad19
AF		 973void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
974int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
e3e09d87 975 target_ulong *raddr, int *flags, bool exc);
6e252802 976int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 977uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 978 uint64_t vr);
979
6cb1e49d
AY		 980int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
981 int len, bool is_write);
c3edd628 982
6cb1e49d
AY		 983#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
984 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
985#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
986 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
987#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
988 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
c3edd628 989
bcec36ea
AG		 990/* The value of the TOD clock for 1.1.1970. */
991#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
992
993/* Converts ns to s390's clock format */
994static inline uint64_t time2tod(uint64_t ns) {
995 return (ns << 9) / 125;
996}
997
9cb32c44
AJ		 998/* Converts s390's clock format to ns */
999static inline uint64_t tod2time(uint64_t t) {
1000 return (t * 125) >> 9;
1001}
1002
f9466733 1003static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 1004 uint64_t param64)
1005{
f9466733
AF		 1006 CPUS390XState *env = &cpu->env;
1007
bcec36ea
AG		 1008 if (env->ext_index == MAX_EXT_QUEUE - 1) {
1009 /* ugh - can't queue anymore. Let's drop. */
1010 return;
1011 }
1012
1013 env->ext_index++;
1014 assert(env->ext_index < MAX_EXT_QUEUE);
1015
1016 env->ext_queue[env->ext_index].code = code;
1017 env->ext_queue[env->ext_index].param = param;
1018 env->ext_queue[env->ext_index].param64 = param64;
1019
1020 env->pending_int |= INTERRUPT_EXT;
c3affe56 1021 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 1022}
10c339a0 1023
f9466733 1024static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 1025 uint16_t subchannel_number,
1026 uint32_t io_int_parm, uint32_t io_int_word)
1027{
f9466733 1028 CPUS390XState *env = &cpu->env;
91b0a8f3 1029 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1030
1031 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1032 /* ugh - can't queue anymore. Let's drop. */
1033 return;
1034 }
1035
1036 env->io_index[isc]++;
1037 assert(env->io_index[isc] < MAX_IO_QUEUE);
1038
1039 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1040 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1041 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1042 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1043
1044 env->pending_int |= INTERRUPT_IO;
c3affe56 1045 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1046}
1047
f9466733 1048static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1049{
f9466733
AF		 1050 CPUS390XState *env = &cpu->env;
1051
5d69c547
CH		 1052 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1053 /* ugh - can't queue anymore. Let's drop. */
1054 return;
1055 }
1056
1057 env->mchk_index++;
1058 assert(env->mchk_index < MAX_MCHK_QUEUE);
1059
1060 env->mchk_queue[env->mchk_index].type = 1;
1061
1062 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1063 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1064}
1065
b6fe0124
MR		 1066/* from s390-virtio-ccw */
1067#define MEM_SECTION_SIZE 0x10000000UL
1def6656 1068#define MAX_AVAIL_SLOTS 32
b6fe0124 1069
e72ca652 1070/* fpu_helper.c */
e72ca652
BS		 1071uint32_t set_cc_nz_f32(float32 v);
1072uint32_t set_cc_nz_f64(float64 v);
587626f8 1073uint32_t set_cc_nz_f128(float128 v);
e72ca652 1074
aea1e885 1075/* misc_helper.c */
268846ba
ED		 1076#ifndef CONFIG_USER_ONLY
1077void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1078#endif
d5a103cd 1079void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1080void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1081 uintptr_t retaddr);
a78b0504 1082
09b99878 1083#ifdef CONFIG_KVM
de13d216 1084void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH		 1085 uint16_t subchannel_nr, uint32_t io_int_parm,
1086 uint32_t io_int_word);
de13d216 1087void kvm_s390_crw_mchk(void);
09b99878 1088void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1089int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1090 int vq, bool assign);
7f7f9752 1091int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 1092int kvm_s390_get_memslot_count(KVMState *s);
4cb88c3c 1093void kvm_s390_clear_cmma_callback(void *opaque);
c9e659c9 1094int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
99607144 1095void kvm_s390_reset_vcpu(S390CPU *cpu);
a310b283 1096int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
3cda44f7
JF		 1097void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1098int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
09b99878 1099#else
de13d216 1100static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH		 1101 uint16_t subchannel_nr,
1102 uint32_t io_int_parm,
1103 uint32_t io_int_word)
1104{
1105}
de13d216 1106static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH		 1107{
1108}
09b99878
CH		 1109static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1110{
1111}
cc3ac9c4
CH		 1112static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1113 uint32_t sch, int vq,
b4436a0b
CH		 1114 bool assign)
1115{
1116 return -ENOSYS;
1117}
7f7f9752
ED		 1118static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1119{
1120 return -ENOSYS;
1121}
4cb88c3c
DD		 1122static inline void kvm_s390_clear_cmma_callback(void *opaque)
1123{
1124}
1def6656
MR		 1125static inline int kvm_s390_get_memslot_count(KVMState *s)
1126{
1127 return MAX_AVAIL_SLOTS;
1128}
c9e659c9
DH		 1129static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1130{
1131 return -ENOSYS;
1132}
99607144
DH		 1133static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1134{
1135}
a310b283
DD		 1136static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1137 uint64_t *hw_limit)
1138{
1139 return 0;
1140}
3cda44f7
JF		 1141static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1142{
1143}
1144static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1145{
1146 return 0;
1147}
09b99878 1148#endif
df1fe5bb 1149
a310b283
DD		 1150static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1151{
1152 if (kvm_enabled()) {
1153 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1154 }
1155 return 0;
1156}
1157
4cb88c3c
DD		 1158static inline void cmma_reset(S390CPU *cpu)
1159{
1160 if (kvm_enabled()) {
1161 CPUState *cs = CPU(cpu);
1162 kvm_s390_clear_cmma_callback(cs->kvm_state);
1163 }
1164}
1165
7f7f9752
ED		 1166static inline int s390_cpu_restart(S390CPU *cpu)
1167{
1168 if (kvm_enabled()) {
1169 return kvm_s390_cpu_restart(cpu);
1170 }
1171 return -ENOSYS;
1172}
1173
1def6656
MR		 1174static inline int s390_get_memslot_count(KVMState *s)
1175{
1176 if (kvm_enabled()) {
1177 return kvm_s390_get_memslot_count(s);
1178 } else {
1179 return MAX_AVAIL_SLOTS;
1180 }
1181}
1182
de13d216
CH		 1183void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1184 uint32_t io_int_parm, uint32_t io_int_word);
1185void s390_crw_mchk(void);
df1fe5bb 1186
cc3ac9c4
CH		 1187static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1188 uint32_t sch_id, int vq,
b4436a0b
CH		 1189 bool assign)
1190{
1191 if (kvm_enabled()) {
cc3ac9c4 1192 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1193 } else {
1194 return -ENOSYS;
1195 }
1196}
1197
b2ac0ff5
EF		 1198#ifdef CONFIG_KVM
1199static inline bool vregs_needed(void *opaque)
1200{
1201 if (kvm_enabled()) {
1202 return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1203 }
1204 return 0;
1205}
1206#else
1207static inline bool vregs_needed(void *opaque)
1208{
1209 return 0;
1210}
1211#endif
10ec5117 1212#endif
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