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s390x/ioinst: Rework memory access in TSCH instruction
[mirror_qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
44b0c0bb
CB		 129 uint64_t gbea;
130 uint64_t pp;
131
4e836781
AG		 132 CPU_COMMON
133
bcec36ea
AG		 134 /* reset does memset(0) up to here */
135
7f745b31
RH		 136 uint32_t cpu_num;
137 uint32_t machine_type;
138
bcec36ea
AG		 139 uint8_t *storage_keys;
140
141 uint64_t tod_offset;
142 uint64_t tod_basetime;
143 QEMUTimer *tod_timer;
144
145 QEMUTimer *cpu_timer;
75973bfe
DH		 146
147 /*
148 * The cpu state represents the logical state of a cpu. In contrast to other
149 * architectures, there is a difference between a halt and a stop on s390.
150 * If all cpus are either stopped (including check stop) or in the disabled
151 * wait state, the vm can be shut down.
152 */
153#define CPU_STATE_UNINITIALIZED 0x00
154#define CPU_STATE_STOPPED 0x01
155#define CPU_STATE_CHECK_STOP 0x02
156#define CPU_STATE_OPERATING 0x03
157#define CPU_STATE_LOAD 0x04
158 uint8_t cpu_state;
159
10ec5117
AG		 160} CPUS390XState;
161
564b863d 162#include "cpu-qom.h"
3d0a615f 163#include <sysemu/kvm.h>
564b863d 164
7b18aad5
CH		 165/* distinguish between 24 bit and 31 bit addressing */
166#define HIGH_ORDER_BIT 0x80000000
167
bcec36ea
AG		 168/* Interrupt Codes */
169/* Program Interrupts */
170#define PGM_OPERATION 0x0001
171#define PGM_PRIVILEGED 0x0002
172#define PGM_EXECUTE 0x0003
173#define PGM_PROTECTION 0x0004
174#define PGM_ADDRESSING 0x0005
175#define PGM_SPECIFICATION 0x0006
176#define PGM_DATA 0x0007
177#define PGM_FIXPT_OVERFLOW 0x0008
178#define PGM_FIXPT_DIVIDE 0x0009
179#define PGM_DEC_OVERFLOW 0x000a
180#define PGM_DEC_DIVIDE 0x000b
181#define PGM_HFP_EXP_OVERFLOW 0x000c
182#define PGM_HFP_EXP_UNDERFLOW 0x000d
183#define PGM_HFP_SIGNIFICANCE 0x000e
184#define PGM_HFP_DIVIDE 0x000f
185#define PGM_SEGMENT_TRANS 0x0010
186#define PGM_PAGE_TRANS 0x0011
187#define PGM_TRANS_SPEC 0x0012
188#define PGM_SPECIAL_OP 0x0013
189#define PGM_OPERAND 0x0015
190#define PGM_TRACE_TABLE 0x0016
191#define PGM_SPACE_SWITCH 0x001c
192#define PGM_HFP_SQRT 0x001d
193#define PGM_PC_TRANS_SPEC 0x001f
194#define PGM_AFX_TRANS 0x0020
195#define PGM_ASX_TRANS 0x0021
196#define PGM_LX_TRANS 0x0022
197#define PGM_EX_TRANS 0x0023
198#define PGM_PRIM_AUTH 0x0024
199#define PGM_SEC_AUTH 0x0025
200#define PGM_ALET_SPEC 0x0028
201#define PGM_ALEN_SPEC 0x0029
202#define PGM_ALE_SEQ 0x002a
203#define PGM_ASTE_VALID 0x002b
204#define PGM_ASTE_SEQ 0x002c
205#define PGM_EXT_AUTH 0x002d
206#define PGM_STACK_FULL 0x0030
207#define PGM_STACK_EMPTY 0x0031
208#define PGM_STACK_SPEC 0x0032
209#define PGM_STACK_TYPE 0x0033
210#define PGM_STACK_OP 0x0034
211#define PGM_ASCE_TYPE 0x0038
212#define PGM_REG_FIRST_TRANS 0x0039
213#define PGM_REG_SEC_TRANS 0x003a
214#define PGM_REG_THIRD_TRANS 0x003b
215#define PGM_MONITOR 0x0040
216#define PGM_PER 0x0080
217#define PGM_CRYPTO 0x0119
218
219/* External Interrupts */
220#define EXT_INTERRUPT_KEY 0x0040
221#define EXT_CLOCK_COMP 0x1004
222#define EXT_CPU_TIMER 0x1005
223#define EXT_MALFUNCTION 0x1200
224#define EXT_EMERGENCY 0x1201
225#define EXT_EXTERNAL_CALL 0x1202
226#define EXT_ETR 0x1406
227#define EXT_SERVICE 0x2401
228#define EXT_VIRTIO 0x2603
229
230/* PSW defines */
231#undef PSW_MASK_PER
232#undef PSW_MASK_DAT
233#undef PSW_MASK_IO
234#undef PSW_MASK_EXT
235#undef PSW_MASK_KEY
236#undef PSW_SHIFT_KEY
237#undef PSW_MASK_MCHECK
238#undef PSW_MASK_WAIT
239#undef PSW_MASK_PSTATE
240#undef PSW_MASK_ASC
241#undef PSW_MASK_CC
242#undef PSW_MASK_PM
243#undef PSW_MASK_64
29c6157c
CB		 244#undef PSW_MASK_32
245#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 246
247#define PSW_MASK_PER 0x4000000000000000ULL
248#define PSW_MASK_DAT 0x0400000000000000ULL
249#define PSW_MASK_IO 0x0200000000000000ULL
250#define PSW_MASK_EXT 0x0100000000000000ULL
251#define PSW_MASK_KEY 0x00F0000000000000ULL
252#define PSW_SHIFT_KEY 56
253#define PSW_MASK_MCHECK 0x0004000000000000ULL
254#define PSW_MASK_WAIT 0x0002000000000000ULL
255#define PSW_MASK_PSTATE 0x0001000000000000ULL
256#define PSW_MASK_ASC 0x0000C00000000000ULL
257#define PSW_MASK_CC 0x0000300000000000ULL
258#define PSW_MASK_PM 0x00000F0000000000ULL
259#define PSW_MASK_64 0x0000000100000000ULL
260#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 261#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 262
263#undef PSW_ASC_PRIMARY
264#undef PSW_ASC_ACCREG
265#undef PSW_ASC_SECONDARY
266#undef PSW_ASC_HOME
267
268#define PSW_ASC_PRIMARY 0x0000000000000000ULL
269#define PSW_ASC_ACCREG 0x0000400000000000ULL
270#define PSW_ASC_SECONDARY 0x0000800000000000ULL
271#define PSW_ASC_HOME 0x0000C00000000000ULL
272
273/* tb flags */
274
275#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
276#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
277#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
278#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
279#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
280#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
281#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
282#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
283#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
284#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
285#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
286#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
287#define FLAG_MASK_32 0x00001000
288
c4400206 289/* Control register 0 bits */
c3edd628 290#define CR0_LOWPROT 0x0000000010000000ULL
c4400206
TH		 291#define CR0_EDAT 0x0000000000800000ULL
292
a4e3ad19 293static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 294{
bcec36ea
AG		 295 if (env->psw.mask & PSW_MASK_PSTATE) {
296 return 1;
297 }
298
10c339a0
AG		 299 return 0;
300}
301
a4e3ad19 302static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 303 target_ulong *cs_base, int *flags)
304{
305 *pc = env->psw.addr;
306 *cs_base = 0;
307 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
308 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
309}
310
d5a103cd
RH		 311/* While the PoO talks about ILC (a number between 1-3) what is actually
312 stored in LowCore is shifted left one bit (an even between 2-6). As
313 this is the actual length of the insn and therefore more useful, that
314 is what we want to pass around and manipulate. To make sure that we
315 have applied this distinction universally, rename the "ILC" to "ILEN". */
316static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 317{
318 switch (opc >> 6) {
319 case 0:
d5a103cd 320 return 2;
bcec36ea
AG		 321 case 1:
322 case 2:
d5a103cd
RH		 323 return 4;
324 default:
325 return 6;
bcec36ea 326 }
bcec36ea
AG		 327}
328
d5a103cd
RH		 329#ifndef CONFIG_USER_ONLY
330/* In several cases of runtime exceptions, we havn't recorded the true
331 instruction length. Use these codes when raising exceptions in order
332 to re-compute the length by examining the insn in memory. */
333#define ILEN_LATER 0x20
334#define ILEN_LATER_INC 0x21
dfebd7a7 335void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
d5a103cd 336#endif
bcec36ea 337
564b863d 338S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 339void s390x_translate_init(void);
10ec5117 340int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 341
342/* you can call this signal handler from your SIGBUS and SIGSEGV
343 signal handlers to inform the virtual CPU of exceptions. non zero
344 is returned if the signal was handled by the virtual CPU. */
345int cpu_s390x_signal_handler(int host_signum, void *pinfo,
346 void *puc);
7510454e
AF		 347int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
348 int mmu_idx);
10ec5117 349
db1c8f53 350#include "ioinst.h"
52705890 351
10c339a0 352#ifndef CONFIG_USER_ONLY
38322ed6
CH		 353void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
354 int is_write);
355void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
356 int is_write);
7b18aad5
CH		 357static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
358{
359 hwaddr addr = 0;
360 uint8_t reg;
361
362 reg = ipb >> 28;
363 if (reg > 0) {
364 addr = env->regs[reg];
365 }
366 addr += (ipb >> 16) & 0xfff;
367
368 return addr;
369}
370
638129ff
CH		 371/* Base/displacement are at the same locations. */
372#define decode_basedisp_rs decode_basedisp_s
373
85ca3371
DH		 374/* helper functions for run_on_cpu() */
375static inline void s390_do_cpu_reset(void *arg)
376{
377 CPUState *cs = arg;
378 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
379
380 scc->cpu_reset(cs);
381}
382static inline void s390_do_cpu_full_reset(void *arg)
383{
384 CPUState *cs = arg;
385
386 cpu_reset(cs);
387}
388
8f22e0df
AF		 389void s390x_tod_timer(void *opaque);
390void s390x_cpu_timer(void *opaque);
391
28e942f8 392int s390_virtio_hypercall(CPUS390XState *env);
de13d216 393void s390_virtio_irq(int config_change, uint64_t token);
bcec36ea 394
1f206266 395#ifdef CONFIG_KVM
de13d216
CH		 396void kvm_s390_virtio_irq(int config_change, uint64_t token);
397void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH		 398void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
399void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 400int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
801cdd35 401void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
1f206266 402#else
de13d216 403static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
1f206266
AG		 404{
405}
de13d216 406static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH		 407{
408}
801cdd35
TH		 409static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
410 uint64_t te_code)
411{
412}
1f206266 413#endif
45fa769b 414S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH		 415unsigned int s390_cpu_halt(S390CPU *cpu);
416void s390_cpu_unhalt(S390CPU *cpu);
417unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
bcec36ea 418
000a1a38
CB		 419/* service interrupts are floating therefore we must not pass an cpustate */
420void s390_sclp_extint(uint32_t parm);
421
d1ff903c 422/* from s390-virtio-bus */
a8170e5e 423extern const hwaddr virtio_size;
d1ff903c 424
ef81522b 425#else
eb24f7c6
DH		 426static inline unsigned int s390_cpu_halt(S390CPU *cpu)
427{
428 return 0;
429}
430
431static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG		 432{
433}
434
eb24f7c6 435static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG		 436{
437 return 0;
438}
10c339a0 439#endif
bcec36ea
AG		 440void cpu_lock(void);
441void cpu_unlock(void);
10c339a0 442
7b18aad5
CH		 443typedef struct SubchDev SubchDev;
444
df1fe5bb 445#ifndef CONFIG_USER_ONLY
4e872a3f 446extern void io_subsystem_reset(void);
df1fe5bb
CH		 447SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
448 uint16_t schid);
449bool css_subch_visible(SubchDev *sch);
450void css_conditional_io_interrupt(SubchDev *sch);
451int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 452bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
bffd09cd 453int css_do_msch(SubchDev *sch, const SCHIB *schib);
df1fe5bb
CH		 454int css_do_xsch(SubchDev *sch);
455int css_do_csch(SubchDev *sch);
456int css_do_hsch(SubchDev *sch);
457int css_do_ssch(SubchDev *sch, ORB *orb);
b7b6348a
TH		 458int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
459void css_do_tsch_update_subch(SubchDev *sch);
df1fe5bb 460int css_do_stcrw(CRW *crw);
50c8d9bf 461int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 462int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
463 int rfmt, void *buf);
464void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
465int css_enable_mcsse(void);
466int css_enable_mss(void);
467int css_do_rsch(SubchDev *sch);
468int css_do_rchp(uint8_t cssid, uint8_t chpid);
469bool css_present(uint8_t cssid);
df1fe5bb 470#endif
7b18aad5 471
564b863d 472#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 473#define cpu_exec cpu_s390x_exec
474#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 475#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 476
904e5fd5
VM		 477void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
478#define cpu_list s390_cpu_list
479
022c62cb 480#include "exec/exec-all.h"
bcec36ea 481
bcec36ea
AG		 482#define EXCP_EXT 1 /* external interrupt */
483#define EXCP_SVC 2 /* supervisor call (syscall) */
484#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 485#define EXCP_IO 7 /* I/O interrupt */
486#define EXCP_MCHK 8 /* machine check */
bcec36ea 487
bcec36ea
AG		 488#define INTERRUPT_EXT (1 << 0)
489#define INTERRUPT_TOD (1 << 1)
490#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 491#define INTERRUPT_IO (1 << 3)
492#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 493
494/* Program Status Word. */
495#define S390_PSWM_REGNUM 0
496#define S390_PSWA_REGNUM 1
497/* General Purpose Registers. */
498#define S390_R0_REGNUM 2
499#define S390_R1_REGNUM 3
500#define S390_R2_REGNUM 4
501#define S390_R3_REGNUM 5
502#define S390_R4_REGNUM 6
503#define S390_R5_REGNUM 7
504#define S390_R6_REGNUM 8
505#define S390_R7_REGNUM 9
506#define S390_R8_REGNUM 10
507#define S390_R9_REGNUM 11
508#define S390_R10_REGNUM 12
509#define S390_R11_REGNUM 13
510#define S390_R12_REGNUM 14
511#define S390_R13_REGNUM 15
512#define S390_R14_REGNUM 16
513#define S390_R15_REGNUM 17
73d510c9
DH		 514/* Total Core Registers. */
515#define S390_NUM_CORE_REGS 18
10c339a0 516
bcec36ea
AG		 517/* CC optimization */
518
519enum cc_op {
520 CC_OP_CONST0 = 0, /* CC is 0 */
521 CC_OP_CONST1, /* CC is 1 */
522 CC_OP_CONST2, /* CC is 2 */
523 CC_OP_CONST3, /* CC is 3 */
524
525 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
526 CC_OP_STATIC, /* CC value is env->cc_op */
527
528 CC_OP_NZ, /* env->cc_dst != 0 */
529 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
530 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
531 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
532 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
533 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
534 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
535
536 CC_OP_ADD_64, /* overflow on add (64bit) */
537 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 538 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 539 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
540 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 541 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 542 CC_OP_ABS_64, /* sign eval on abs (64bit) */
543 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
544
545 CC_OP_ADD_32, /* overflow on add (32bit) */
546 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 547 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 548 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
549 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 550 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 551 CC_OP_ABS_32, /* sign eval on abs (64bit) */
552 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
553
554 CC_OP_COMP_32, /* complement */
555 CC_OP_COMP_64, /* complement */
556
557 CC_OP_TM_32, /* test under mask (32bit) */
558 CC_OP_TM_64, /* test under mask (64bit) */
559
bcec36ea
AG		 560 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
561 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 562 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 563
564 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 565 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
566 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 567 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 568 CC_OP_MAX
569};
570
571static const char *cc_names[] = {
572 [CC_OP_CONST0] = "CC_OP_CONST0",
573 [CC_OP_CONST1] = "CC_OP_CONST1",
574 [CC_OP_CONST2] = "CC_OP_CONST2",
575 [CC_OP_CONST3] = "CC_OP_CONST3",
576 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
577 [CC_OP_STATIC] = "CC_OP_STATIC",
578 [CC_OP_NZ] = "CC_OP_NZ",
579 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
580 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
581 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
582 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
583 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
584 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
585 [CC_OP_ADD_64] = "CC_OP_ADD_64",
586 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 587 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 588 [CC_OP_SUB_64] = "CC_OP_SUB_64",
589 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 590 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 591 [CC_OP_ABS_64] = "CC_OP_ABS_64",
592 [CC_OP_NABS_64] = "CC_OP_NABS_64",
593 [CC_OP_ADD_32] = "CC_OP_ADD_32",
594 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 595 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 596 [CC_OP_SUB_32] = "CC_OP_SUB_32",
597 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 598 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 599 [CC_OP_ABS_32] = "CC_OP_ABS_32",
600 [CC_OP_NABS_32] = "CC_OP_NABS_32",
601 [CC_OP_COMP_32] = "CC_OP_COMP_32",
602 [CC_OP_COMP_64] = "CC_OP_COMP_64",
603 [CC_OP_TM_32] = "CC_OP_TM_32",
604 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 605 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
606 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 607 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 608 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 609 [CC_OP_SLA_32] = "CC_OP_SLA_32",
610 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 611 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 612};
613
614static inline const char *cc_name(int cc_op)
615{
616 return cc_names[cc_op];
617}
618
3d0a615f
TH		 619static inline void setcc(S390CPU *cpu, uint64_t cc)
620{
621 CPUS390XState *env = &cpu->env;
622
623 env->psw.mask &= ~(3ull << 44);
624 env->psw.mask |= (cc & 3) << 44;
625}
626
bcec36ea
AG		 627typedef struct LowCore
628{
629 /* prefix area: defined by architecture */
630 uint32_t ccw1[2]; /* 0x000 */
631 uint32_t ccw2[4]; /* 0x008 */
632 uint8_t pad1[0x80-0x18]; /* 0x018 */
633 uint32_t ext_params; /* 0x080 */
634 uint16_t cpu_addr; /* 0x084 */
635 uint16_t ext_int_code; /* 0x086 */
d5a103cd 636 uint16_t svc_ilen; /* 0x088 */
bcec36ea 637 uint16_t svc_code; /* 0x08a */
d5a103cd 638 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 639 uint16_t pgm_code; /* 0x08e */
640 uint32_t data_exc_code; /* 0x090 */
641 uint16_t mon_class_num; /* 0x094 */
642 uint16_t per_perc_atmid; /* 0x096 */
643 uint64_t per_address; /* 0x098 */
644 uint8_t exc_access_id; /* 0x0a0 */
645 uint8_t per_access_id; /* 0x0a1 */
646 uint8_t op_access_id; /* 0x0a2 */
647 uint8_t ar_access_id; /* 0x0a3 */
648 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
649 uint64_t trans_exc_code; /* 0x0a8 */
650 uint64_t monitor_code; /* 0x0b0 */
651 uint16_t subchannel_id; /* 0x0b8 */
652 uint16_t subchannel_nr; /* 0x0ba */
653 uint32_t io_int_parm; /* 0x0bc */
654 uint32_t io_int_word; /* 0x0c0 */
655 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
656 uint32_t stfl_fac_list; /* 0x0c8 */
657 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
658 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
659 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
660 uint32_t external_damage_code; /* 0x0f4 */
661 uint64_t failing_storage_address; /* 0x0f8 */
662 uint8_t pad6[0x120-0x100]; /* 0x100 */
663 PSW restart_old_psw; /* 0x120 */
664 PSW external_old_psw; /* 0x130 */
665 PSW svc_old_psw; /* 0x140 */
666 PSW program_old_psw; /* 0x150 */
667 PSW mcck_old_psw; /* 0x160 */
668 PSW io_old_psw; /* 0x170 */
669 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
670 PSW restart_psw; /* 0x1a0 */
671 PSW external_new_psw; /* 0x1b0 */
672 PSW svc_new_psw; /* 0x1c0 */
673 PSW program_new_psw; /* 0x1d0 */
674 PSW mcck_new_psw; /* 0x1e0 */
675 PSW io_new_psw; /* 0x1f0 */
676 PSW return_psw; /* 0x200 */
677 uint8_t irb[64]; /* 0x210 */
678 uint64_t sync_enter_timer; /* 0x250 */
679 uint64_t async_enter_timer; /* 0x258 */
680 uint64_t exit_timer; /* 0x260 */
681 uint64_t last_update_timer; /* 0x268 */
682 uint64_t user_timer; /* 0x270 */
683 uint64_t system_timer; /* 0x278 */
684 uint64_t last_update_clock; /* 0x280 */
685 uint64_t steal_clock; /* 0x288 */
686 PSW return_mcck_psw; /* 0x290 */
687 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
688 /* System info area */
689 uint64_t save_area[16]; /* 0xc00 */
690 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
691 uint64_t kernel_stack; /* 0xd40 */
692 uint64_t thread_info; /* 0xd48 */
693 uint64_t async_stack; /* 0xd50 */
694 uint64_t kernel_asce; /* 0xd58 */
695 uint64_t user_asce; /* 0xd60 */
696 uint64_t panic_stack; /* 0xd68 */
697 uint64_t user_exec_asce; /* 0xd70 */
698 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
699
700 /* SMP info area: defined by DJB */
701 uint64_t clock_comparator; /* 0xdc0 */
702 uint64_t ext_call_fast; /* 0xdc8 */
703 uint64_t percpu_offset; /* 0xdd0 */
704 uint64_t current_task; /* 0xdd8 */
705 uint32_t softirq_pending; /* 0xde0 */
706 uint32_t pad_0x0de4; /* 0xde4 */
707 uint64_t int_clock; /* 0xde8 */
708 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
709
710 /* 0xe00 is used as indicator for dump tools */
711 /* whether the kernel died with panic() or not */
712 uint32_t panic_magic; /* 0xe00 */
713
714 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
715
716 /* 64 bit extparam used for pfault, diag 250 etc */
717 uint64_t ext_params2; /* 0x11B8 */
718
719 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
720
721 /* System info area */
722
723 uint64_t floating_pt_save_area[16]; /* 0x1200 */
724 uint64_t gpregs_save_area[16]; /* 0x1280 */
725 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
726 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
727 uint32_t prefixreg_save_area; /* 0x1318 */
728 uint32_t fpt_creg_save_area; /* 0x131c */
729 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
730 uint32_t tod_progreg_save_area; /* 0x1324 */
731 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
732 uint32_t clock_comp_save_area[2]; /* 0x1330 */
733 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
734 uint32_t access_regs_save_area[16]; /* 0x1340 */
735 uint64_t cregs_save_area[16]; /* 0x1380 */
736
737 /* align to the top of the prefix area */
738
739 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 740} QEMU_PACKED LowCore;
bcec36ea
AG		 741
742/* STSI */
743#define STSI_LEVEL_MASK 0x00000000f0000000ULL
744#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
745#define STSI_LEVEL_1 0x0000000010000000ULL
746#define STSI_LEVEL_2 0x0000000020000000ULL
747#define STSI_LEVEL_3 0x0000000030000000ULL
748#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
749#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
750#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
751#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
752
753/* Basic Machine Configuration */
754struct sysib_111 {
755 uint32_t res1[8];
756 uint8_t manuf[16];
757 uint8_t type[4];
758 uint8_t res2[12];
759 uint8_t model[16];
760 uint8_t sequence[16];
761 uint8_t plant[4];
762 uint8_t res3[156];
763};
764
765/* Basic Machine CPU */
766struct sysib_121 {
767 uint32_t res1[80];
768 uint8_t sequence[16];
769 uint8_t plant[4];
770 uint8_t res2[2];
771 uint16_t cpu_addr;
772 uint8_t res3[152];
773};
774
775/* Basic Machine CPUs */
776struct sysib_122 {
777 uint8_t res1[32];
778 uint32_t capability;
779 uint16_t total_cpus;
780 uint16_t active_cpus;
781 uint16_t standby_cpus;
782 uint16_t reserved_cpus;
783 uint16_t adjustments[2026];
784};
785
786/* LPAR CPU */
787struct sysib_221 {
788 uint32_t res1[80];
789 uint8_t sequence[16];
790 uint8_t plant[4];
791 uint16_t cpu_id;
792 uint16_t cpu_addr;
793 uint8_t res3[152];
794};
795
796/* LPAR CPUs */
797struct sysib_222 {
798 uint32_t res1[32];
799 uint16_t lpar_num;
800 uint8_t res2;
801 uint8_t lcpuc;
802 uint16_t total_cpus;
803 uint16_t conf_cpus;
804 uint16_t standby_cpus;
805 uint16_t reserved_cpus;
806 uint8_t name[8];
807 uint32_t caf;
808 uint8_t res3[16];
809 uint16_t dedicated_cpus;
810 uint16_t shared_cpus;
811 uint8_t res4[180];
812};
813
814/* VM CPUs */
815struct sysib_322 {
816 uint8_t res1[31];
817 uint8_t count;
818 struct {
819 uint8_t res2[4];
820 uint16_t total_cpus;
821 uint16_t conf_cpus;
822 uint16_t standby_cpus;
823 uint16_t reserved_cpus;
824 uint8_t name[8];
825 uint32_t caf;
826 uint8_t cpi[16];
827 uint8_t res3[24];
828 } vm[8];
829 uint8_t res4[3552];
830};
831
832/* MMU defines */
833#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
834#define _ASCE_SUBSPACE 0x200 /* subspace group control */
835#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
836#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
837#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
838#define _ASCE_REAL_SPACE 0x20 /* real space control */
839#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
840#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
841#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
842#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
843#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
844#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
845
846#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
43d49b01 847#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
5d180439 848#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
bcec36ea
AG		 849#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
850#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
851#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
852#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
853#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
854#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
855
856#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 857#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG		 858#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
859#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
860
861#define _PAGE_RO 0x200 /* HW read-only bit */
862#define _PAGE_INVALID 0x400 /* HW invalid bit */
b4ecbf80 863#define _PAGE_RES0 0x800 /* bit must be zero */
bcec36ea 864
b9959138
AG		 865#define SK_C (0x1 << 1)
866#define SK_R (0x1 << 2)
867#define SK_F (0x1 << 3)
868#define SK_ACC_MASK (0xf << 4)
bcec36ea 869
bcec36ea
AG		 870#define SIGP_SENSE 0x01
871#define SIGP_EXTERNAL_CALL 0x02
872#define SIGP_EMERGENCY 0x03
873#define SIGP_START 0x04
874#define SIGP_STOP 0x05
875#define SIGP_RESTART 0x06
876#define SIGP_STOP_STORE_STATUS 0x09
877#define SIGP_INITIAL_CPU_RESET 0x0b
878#define SIGP_CPU_RESET 0x0c
879#define SIGP_SET_PREFIX 0x0d
880#define SIGP_STORE_STATUS_ADDR 0x0e
881#define SIGP_SET_ARCH 0x12
882
883/* cpu status bits */
884#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
885#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
886#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
887#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
888#define SIGP_STAT_STOPPED 0x00000040UL
889#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
890#define SIGP_STAT_CHECK_STOP 0x00000010UL
891#define SIGP_STAT_INOPERATIVE 0x00000004UL
892#define SIGP_STAT_INVALID_ORDER 0x00000002UL
893#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
894
a4e3ad19
AF		 895void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
896int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
e3e09d87 897 target_ulong *raddr, int *flags, bool exc);
6e252802 898int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 899uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 900 uint64_t vr);
901
c3edd628
TH		 902int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, void *hostbuf, int len,
903 bool is_write);
904
905#define s390_cpu_virt_mem_read(cpu, laddr, dest, len) \
906 s390_cpu_virt_mem_rw(cpu, laddr, dest, len, false)
907#define s390_cpu_virt_mem_write(cpu, laddr, dest, len) \
908 s390_cpu_virt_mem_rw(cpu, laddr, dest, len, true)
909#define s390_cpu_virt_mem_check_write(cpu, laddr, len) \
910 s390_cpu_virt_mem_rw(cpu, laddr, NULL, len, true)
911
bcec36ea
AG		 912/* The value of the TOD clock for 1.1.1970. */
913#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
914
915/* Converts ns to s390's clock format */
916static inline uint64_t time2tod(uint64_t ns) {
917 return (ns << 9) / 125;
918}
919
f9466733 920static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 921 uint64_t param64)
922{
f9466733
AF		 923 CPUS390XState *env = &cpu->env;
924
bcec36ea
AG		 925 if (env->ext_index == MAX_EXT_QUEUE - 1) {
926 /* ugh - can't queue anymore. Let's drop. */
927 return;
928 }
929
930 env->ext_index++;
931 assert(env->ext_index < MAX_EXT_QUEUE);
932
933 env->ext_queue[env->ext_index].code = code;
934 env->ext_queue[env->ext_index].param = param;
935 env->ext_queue[env->ext_index].param64 = param64;
936
937 env->pending_int |= INTERRUPT_EXT;
c3affe56 938 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 939}
10c339a0 940
f9466733 941static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 942 uint16_t subchannel_number,
943 uint32_t io_int_parm, uint32_t io_int_word)
944{
f9466733 945 CPUS390XState *env = &cpu->env;
91b0a8f3 946 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 947
948 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
949 /* ugh - can't queue anymore. Let's drop. */
950 return;
951 }
952
953 env->io_index[isc]++;
954 assert(env->io_index[isc] < MAX_IO_QUEUE);
955
956 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
957 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
958 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
959 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
960
961 env->pending_int |= INTERRUPT_IO;
c3affe56 962 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 963}
964
f9466733 965static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 966{
f9466733
AF		 967 CPUS390XState *env = &cpu->env;
968
5d69c547
CH		 969 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
970 /* ugh - can't queue anymore. Let's drop. */
971 return;
972 }
973
974 env->mchk_index++;
975 assert(env->mchk_index < MAX_MCHK_QUEUE);
976
977 env->mchk_queue[env->mchk_index].type = 1;
978
979 env->pending_int |= INTERRUPT_MCHK;
c3affe56 980 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 981}
982
b6fe0124
MR		 983/* from s390-virtio-ccw */
984#define MEM_SECTION_SIZE 0x10000000UL
1def6656 985#define MAX_AVAIL_SLOTS 32
b6fe0124 986
e72ca652 987/* fpu_helper.c */
e72ca652
BS		 988uint32_t set_cc_nz_f32(float32 v);
989uint32_t set_cc_nz_f64(float64 v);
587626f8 990uint32_t set_cc_nz_f128(float128 v);
e72ca652 991
aea1e885 992/* misc_helper.c */
268846ba
ED		 993#ifndef CONFIG_USER_ONLY
994void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
995#endif
d5a103cd 996void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 997void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
998 uintptr_t retaddr);
a78b0504 999
09b99878 1000#ifdef CONFIG_KVM
de13d216 1001void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH		 1002 uint16_t subchannel_nr, uint32_t io_int_parm,
1003 uint32_t io_int_word);
de13d216 1004void kvm_s390_crw_mchk(void);
09b99878 1005void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1006int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1007 int vq, bool assign);
7f7f9752 1008int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 1009int kvm_s390_get_memslot_count(KVMState *s);
4cb88c3c 1010void kvm_s390_clear_cmma_callback(void *opaque);
c9e659c9 1011int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
99607144 1012void kvm_s390_reset_vcpu(S390CPU *cpu);
09b99878 1013#else
de13d216 1014static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH		 1015 uint16_t subchannel_nr,
1016 uint32_t io_int_parm,
1017 uint32_t io_int_word)
1018{
1019}
de13d216 1020static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH		 1021{
1022}
09b99878
CH		 1023static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1024{
1025}
cc3ac9c4
CH		 1026static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1027 uint32_t sch, int vq,
b4436a0b
CH		 1028 bool assign)
1029{
1030 return -ENOSYS;
1031}
7f7f9752
ED		 1032static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1033{
1034 return -ENOSYS;
1035}
4cb88c3c
DD		 1036static inline void kvm_s390_clear_cmma_callback(void *opaque)
1037{
1038}
1def6656
MR		 1039static inline int kvm_s390_get_memslot_count(KVMState *s)
1040{
1041 return MAX_AVAIL_SLOTS;
1042}
c9e659c9
DH		 1043static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1044{
1045 return -ENOSYS;
1046}
99607144
DH		 1047static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1048{
1049}
09b99878 1050#endif
df1fe5bb 1051
4cb88c3c
DD		 1052static inline void cmma_reset(S390CPU *cpu)
1053{
1054 if (kvm_enabled()) {
1055 CPUState *cs = CPU(cpu);
1056 kvm_s390_clear_cmma_callback(cs->kvm_state);
1057 }
1058}
1059
7f7f9752
ED		 1060static inline int s390_cpu_restart(S390CPU *cpu)
1061{
1062 if (kvm_enabled()) {
1063 return kvm_s390_cpu_restart(cpu);
1064 }
1065 return -ENOSYS;
1066}
1067
1def6656
MR		 1068static inline int s390_get_memslot_count(KVMState *s)
1069{
1070 if (kvm_enabled()) {
1071 return kvm_s390_get_memslot_count(s);
1072 } else {
1073 return MAX_AVAIL_SLOTS;
1074 }
1075}
1076
de13d216
CH		 1077void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1078 uint32_t io_int_parm, uint32_t io_int_word);
1079void s390_crw_mchk(void);
df1fe5bb 1080
cc3ac9c4
CH		 1081static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1082 uint32_t sch_id, int vq,
b4436a0b
CH		 1083 bool assign)
1084{
1085 if (kvm_enabled()) {
cc3ac9c4 1086 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1087 } else {
1088 return -ENOSYS;
1089 }
1090}
1091
10ec5117 1092#endif
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