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10ec5117 AG |
1 | /* |
2 | * S/390 virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2009 Ulrich Hecht | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
ccb084d3 CB |
16 | * Contributions after 2012-10-29 are licensed under the terms of the |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
18 | * | |
19 | * You should have received a copy of the GNU (Lesser) General Public | |
70539e18 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
10ec5117 AG |
21 | */ |
22 | #ifndef CPU_S390X_H | |
23 | #define CPU_S390X_H | |
45133b74 SW |
24 | |
25 | #include "config.h" | |
26 | #include "qemu-common.h" | |
10ec5117 AG |
27 | |
28 | #define TARGET_LONG_BITS 64 | |
29 | ||
30 | #define ELF_MACHINE EM_S390 | |
4ab23a91 | 31 | #define ELF_MACHINE_UNAME "S390X" |
10ec5117 | 32 | |
9349b4f9 | 33 | #define CPUArchState struct CPUS390XState |
10ec5117 | 34 | |
022c62cb | 35 | #include "exec/cpu-defs.h" |
bcec36ea AG |
36 | #define TARGET_PAGE_BITS 12 |
37 | ||
5b23fd03 | 38 | #define TARGET_PHYS_ADDR_SPACE_BITS 64 |
bcec36ea AG |
39 | #define TARGET_VIRT_ADDR_SPACE_BITS 64 |
40 | ||
022c62cb | 41 | #include "exec/cpu-all.h" |
10ec5117 | 42 | |
6b4c305c | 43 | #include "fpu/softfloat.h" |
10ec5117 | 44 | |
bcec36ea | 45 | #define NB_MMU_MODES 3 |
10ec5117 | 46 | |
bcec36ea AG |
47 | #define MMU_MODE0_SUFFIX _primary |
48 | #define MMU_MODE1_SUFFIX _secondary | |
49 | #define MMU_MODE2_SUFFIX _home | |
50 | ||
1f65958d | 51 | #define MMU_USER_IDX 0 |
bcec36ea AG |
52 | |
53 | #define MAX_EXT_QUEUE 16 | |
5d69c547 CH |
54 | #define MAX_IO_QUEUE 16 |
55 | #define MAX_MCHK_QUEUE 16 | |
56 | ||
57 | #define PSW_MCHK_MASK 0x0004000000000000 | |
58 | #define PSW_IO_MASK 0x0200000000000000 | |
bcec36ea AG |
59 | |
60 | typedef struct PSW { | |
61 | uint64_t mask; | |
62 | uint64_t addr; | |
63 | } PSW; | |
64 | ||
65 | typedef struct ExtQueue { | |
66 | uint32_t code; | |
67 | uint32_t param; | |
68 | uint32_t param64; | |
69 | } ExtQueue; | |
10ec5117 | 70 | |
5d69c547 CH |
71 | typedef struct IOIntQueue { |
72 | uint16_t id; | |
73 | uint16_t nr; | |
74 | uint32_t parm; | |
75 | uint32_t word; | |
76 | } IOIntQueue; | |
77 | ||
78 | typedef struct MchkQueue { | |
79 | uint16_t type; | |
80 | } MchkQueue; | |
81 | ||
10ec5117 | 82 | typedef struct CPUS390XState { |
1ac5889f | 83 | uint64_t regs[16]; /* GP registers */ |
fcb79802 EF |
84 | /* |
85 | * The floating point registers are part of the vector registers. | |
86 | * vregs[0][0] -> vregs[15][0] are 16 floating point registers | |
87 | */ | |
88 | CPU_DoubleU vregs[32][2]; /* vector registers */ | |
1ac5889f | 89 | uint32_t aregs[16]; /* access registers */ |
10ec5117 | 90 | |
1ac5889f RH |
91 | uint32_t fpc; /* floating-point control register */ |
92 | uint32_t cc_op; | |
10ec5117 | 93 | |
10ec5117 AG |
94 | float_status fpu_status; /* passed to softfloat lib */ |
95 | ||
1ac5889f RH |
96 | /* The low part of a 128-bit return, or remainder of a divide. */ |
97 | uint64_t retxl; | |
98 | ||
bcec36ea | 99 | PSW psw; |
10ec5117 | 100 | |
bcec36ea AG |
101 | uint64_t cc_src; |
102 | uint64_t cc_dst; | |
103 | uint64_t cc_vr; | |
10ec5117 AG |
104 | |
105 | uint64_t __excp_addr; | |
bcec36ea AG |
106 | uint64_t psa; |
107 | ||
108 | uint32_t int_pgm_code; | |
d5a103cd | 109 | uint32_t int_pgm_ilen; |
bcec36ea AG |
110 | |
111 | uint32_t int_svc_code; | |
d5a103cd | 112 | uint32_t int_svc_ilen; |
bcec36ea AG |
113 | |
114 | uint64_t cregs[16]; /* control registers */ | |
115 | ||
bcec36ea | 116 | ExtQueue ext_queue[MAX_EXT_QUEUE]; |
5d69c547 CH |
117 | IOIntQueue io_queue[MAX_IO_QUEUE][8]; |
118 | MchkQueue mchk_queue[MAX_MCHK_QUEUE]; | |
bcec36ea | 119 | |
5d69c547 | 120 | int pending_int; |
4e836781 | 121 | int ext_index; |
5d69c547 CH |
122 | int io_index[8]; |
123 | int mchk_index; | |
124 | ||
125 | uint64_t ckc; | |
126 | uint64_t cputm; | |
127 | uint32_t todpr; | |
4e836781 | 128 | |
819bd309 DD |
129 | uint64_t pfault_token; |
130 | uint64_t pfault_compare; | |
131 | uint64_t pfault_select; | |
132 | ||
44b0c0bb CB |
133 | uint64_t gbea; |
134 | uint64_t pp; | |
135 | ||
4e836781 AG |
136 | CPU_COMMON |
137 | ||
bcec36ea AG |
138 | /* reset does memset(0) up to here */ |
139 | ||
7f745b31 RH |
140 | uint32_t cpu_num; |
141 | uint32_t machine_type; | |
142 | ||
bcec36ea AG |
143 | uint8_t *storage_keys; |
144 | ||
145 | uint64_t tod_offset; | |
146 | uint64_t tod_basetime; | |
147 | QEMUTimer *tod_timer; | |
148 | ||
149 | QEMUTimer *cpu_timer; | |
75973bfe DH |
150 | |
151 | /* | |
152 | * The cpu state represents the logical state of a cpu. In contrast to other | |
153 | * architectures, there is a difference between a halt and a stop on s390. | |
154 | * If all cpus are either stopped (including check stop) or in the disabled | |
155 | * wait state, the vm can be shut down. | |
156 | */ | |
157 | #define CPU_STATE_UNINITIALIZED 0x00 | |
158 | #define CPU_STATE_STOPPED 0x01 | |
159 | #define CPU_STATE_CHECK_STOP 0x02 | |
160 | #define CPU_STATE_OPERATING 0x03 | |
161 | #define CPU_STATE_LOAD 0x04 | |
162 | uint8_t cpu_state; | |
163 | ||
18ff9494 DH |
164 | /* currently processed sigp order */ |
165 | uint8_t sigp_order; | |
166 | ||
10ec5117 AG |
167 | } CPUS390XState; |
168 | ||
c498d8e3 EF |
169 | static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr) |
170 | { | |
fcb79802 | 171 | return &cs->vregs[nr][0]; |
c498d8e3 EF |
172 | } |
173 | ||
564b863d | 174 | #include "cpu-qom.h" |
3d0a615f | 175 | #include <sysemu/kvm.h> |
564b863d | 176 | |
7b18aad5 CH |
177 | /* distinguish between 24 bit and 31 bit addressing */ |
178 | #define HIGH_ORDER_BIT 0x80000000 | |
179 | ||
bcec36ea AG |
180 | /* Interrupt Codes */ |
181 | /* Program Interrupts */ | |
182 | #define PGM_OPERATION 0x0001 | |
183 | #define PGM_PRIVILEGED 0x0002 | |
184 | #define PGM_EXECUTE 0x0003 | |
185 | #define PGM_PROTECTION 0x0004 | |
186 | #define PGM_ADDRESSING 0x0005 | |
187 | #define PGM_SPECIFICATION 0x0006 | |
188 | #define PGM_DATA 0x0007 | |
189 | #define PGM_FIXPT_OVERFLOW 0x0008 | |
190 | #define PGM_FIXPT_DIVIDE 0x0009 | |
191 | #define PGM_DEC_OVERFLOW 0x000a | |
192 | #define PGM_DEC_DIVIDE 0x000b | |
193 | #define PGM_HFP_EXP_OVERFLOW 0x000c | |
194 | #define PGM_HFP_EXP_UNDERFLOW 0x000d | |
195 | #define PGM_HFP_SIGNIFICANCE 0x000e | |
196 | #define PGM_HFP_DIVIDE 0x000f | |
197 | #define PGM_SEGMENT_TRANS 0x0010 | |
198 | #define PGM_PAGE_TRANS 0x0011 | |
199 | #define PGM_TRANS_SPEC 0x0012 | |
200 | #define PGM_SPECIAL_OP 0x0013 | |
201 | #define PGM_OPERAND 0x0015 | |
202 | #define PGM_TRACE_TABLE 0x0016 | |
203 | #define PGM_SPACE_SWITCH 0x001c | |
204 | #define PGM_HFP_SQRT 0x001d | |
205 | #define PGM_PC_TRANS_SPEC 0x001f | |
206 | #define PGM_AFX_TRANS 0x0020 | |
207 | #define PGM_ASX_TRANS 0x0021 | |
208 | #define PGM_LX_TRANS 0x0022 | |
209 | #define PGM_EX_TRANS 0x0023 | |
210 | #define PGM_PRIM_AUTH 0x0024 | |
211 | #define PGM_SEC_AUTH 0x0025 | |
212 | #define PGM_ALET_SPEC 0x0028 | |
213 | #define PGM_ALEN_SPEC 0x0029 | |
214 | #define PGM_ALE_SEQ 0x002a | |
215 | #define PGM_ASTE_VALID 0x002b | |
216 | #define PGM_ASTE_SEQ 0x002c | |
217 | #define PGM_EXT_AUTH 0x002d | |
218 | #define PGM_STACK_FULL 0x0030 | |
219 | #define PGM_STACK_EMPTY 0x0031 | |
220 | #define PGM_STACK_SPEC 0x0032 | |
221 | #define PGM_STACK_TYPE 0x0033 | |
222 | #define PGM_STACK_OP 0x0034 | |
223 | #define PGM_ASCE_TYPE 0x0038 | |
224 | #define PGM_REG_FIRST_TRANS 0x0039 | |
225 | #define PGM_REG_SEC_TRANS 0x003a | |
226 | #define PGM_REG_THIRD_TRANS 0x003b | |
227 | #define PGM_MONITOR 0x0040 | |
228 | #define PGM_PER 0x0080 | |
229 | #define PGM_CRYPTO 0x0119 | |
230 | ||
231 | /* External Interrupts */ | |
232 | #define EXT_INTERRUPT_KEY 0x0040 | |
233 | #define EXT_CLOCK_COMP 0x1004 | |
234 | #define EXT_CPU_TIMER 0x1005 | |
235 | #define EXT_MALFUNCTION 0x1200 | |
236 | #define EXT_EMERGENCY 0x1201 | |
237 | #define EXT_EXTERNAL_CALL 0x1202 | |
238 | #define EXT_ETR 0x1406 | |
239 | #define EXT_SERVICE 0x2401 | |
240 | #define EXT_VIRTIO 0x2603 | |
241 | ||
242 | /* PSW defines */ | |
243 | #undef PSW_MASK_PER | |
244 | #undef PSW_MASK_DAT | |
245 | #undef PSW_MASK_IO | |
246 | #undef PSW_MASK_EXT | |
247 | #undef PSW_MASK_KEY | |
248 | #undef PSW_SHIFT_KEY | |
249 | #undef PSW_MASK_MCHECK | |
250 | #undef PSW_MASK_WAIT | |
251 | #undef PSW_MASK_PSTATE | |
252 | #undef PSW_MASK_ASC | |
253 | #undef PSW_MASK_CC | |
254 | #undef PSW_MASK_PM | |
255 | #undef PSW_MASK_64 | |
29c6157c CB |
256 | #undef PSW_MASK_32 |
257 | #undef PSW_MASK_ESA_ADDR | |
bcec36ea AG |
258 | |
259 | #define PSW_MASK_PER 0x4000000000000000ULL | |
260 | #define PSW_MASK_DAT 0x0400000000000000ULL | |
261 | #define PSW_MASK_IO 0x0200000000000000ULL | |
262 | #define PSW_MASK_EXT 0x0100000000000000ULL | |
263 | #define PSW_MASK_KEY 0x00F0000000000000ULL | |
264 | #define PSW_SHIFT_KEY 56 | |
265 | #define PSW_MASK_MCHECK 0x0004000000000000ULL | |
266 | #define PSW_MASK_WAIT 0x0002000000000000ULL | |
267 | #define PSW_MASK_PSTATE 0x0001000000000000ULL | |
268 | #define PSW_MASK_ASC 0x0000C00000000000ULL | |
269 | #define PSW_MASK_CC 0x0000300000000000ULL | |
270 | #define PSW_MASK_PM 0x00000F0000000000ULL | |
271 | #define PSW_MASK_64 0x0000000100000000ULL | |
272 | #define PSW_MASK_32 0x0000000080000000ULL | |
29c6157c | 273 | #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL |
bcec36ea AG |
274 | |
275 | #undef PSW_ASC_PRIMARY | |
276 | #undef PSW_ASC_ACCREG | |
277 | #undef PSW_ASC_SECONDARY | |
278 | #undef PSW_ASC_HOME | |
279 | ||
280 | #define PSW_ASC_PRIMARY 0x0000000000000000ULL | |
281 | #define PSW_ASC_ACCREG 0x0000400000000000ULL | |
282 | #define PSW_ASC_SECONDARY 0x0000800000000000ULL | |
283 | #define PSW_ASC_HOME 0x0000C00000000000ULL | |
284 | ||
285 | /* tb flags */ | |
286 | ||
287 | #define FLAG_MASK_PER (PSW_MASK_PER >> 32) | |
288 | #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32) | |
289 | #define FLAG_MASK_IO (PSW_MASK_IO >> 32) | |
290 | #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32) | |
291 | #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32) | |
292 | #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32) | |
293 | #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32) | |
294 | #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32) | |
295 | #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32) | |
296 | #define FLAG_MASK_CC (PSW_MASK_CC >> 32) | |
297 | #define FLAG_MASK_PM (PSW_MASK_PM >> 32) | |
298 | #define FLAG_MASK_64 (PSW_MASK_64 >> 32) | |
299 | #define FLAG_MASK_32 0x00001000 | |
300 | ||
c4400206 | 301 | /* Control register 0 bits */ |
c3edd628 | 302 | #define CR0_LOWPROT 0x0000000010000000ULL |
c4400206 TH |
303 | #define CR0_EDAT 0x0000000000800000ULL |
304 | ||
4decd76d AJ |
305 | /* MMU */ |
306 | #define MMU_PRIMARY_IDX 0 | |
307 | #define MMU_SECONDARY_IDX 1 | |
308 | #define MMU_HOME_IDX 2 | |
309 | ||
a4e3ad19 | 310 | static inline int cpu_mmu_index (CPUS390XState *env) |
10c339a0 | 311 | { |
1f65958d AJ |
312 | switch (env->psw.mask & PSW_MASK_ASC) { |
313 | case PSW_ASC_PRIMARY: | |
4decd76d | 314 | return MMU_PRIMARY_IDX; |
1f65958d | 315 | case PSW_ASC_SECONDARY: |
4decd76d | 316 | return MMU_SECONDARY_IDX; |
1f65958d | 317 | case PSW_ASC_HOME: |
4decd76d | 318 | return MMU_HOME_IDX; |
1f65958d AJ |
319 | case PSW_ASC_ACCREG: |
320 | /* Fallthrough: access register mode is not yet supported */ | |
321 | default: | |
322 | abort(); | |
bcec36ea | 323 | } |
10c339a0 AG |
324 | } |
325 | ||
4decd76d AJ |
326 | static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) |
327 | { | |
328 | switch (mmu_idx) { | |
329 | case MMU_PRIMARY_IDX: | |
330 | return PSW_ASC_PRIMARY; | |
331 | case MMU_SECONDARY_IDX: | |
332 | return PSW_ASC_SECONDARY; | |
333 | case MMU_HOME_IDX: | |
334 | return PSW_ASC_HOME; | |
335 | default: | |
336 | abort(); | |
337 | } | |
338 | } | |
339 | ||
a4e3ad19 | 340 | static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, |
bcec36ea AG |
341 | target_ulong *cs_base, int *flags) |
342 | { | |
343 | *pc = env->psw.addr; | |
344 | *cs_base = 0; | |
345 | *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) | | |
346 | ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0); | |
347 | } | |
348 | ||
d5a103cd RH |
349 | /* While the PoO talks about ILC (a number between 1-3) what is actually |
350 | stored in LowCore is shifted left one bit (an even between 2-6). As | |
351 | this is the actual length of the insn and therefore more useful, that | |
352 | is what we want to pass around and manipulate. To make sure that we | |
353 | have applied this distinction universally, rename the "ILC" to "ILEN". */ | |
354 | static inline int get_ilen(uint8_t opc) | |
bcec36ea AG |
355 | { |
356 | switch (opc >> 6) { | |
357 | case 0: | |
d5a103cd | 358 | return 2; |
bcec36ea AG |
359 | case 1: |
360 | case 2: | |
d5a103cd RH |
361 | return 4; |
362 | default: | |
363 | return 6; | |
bcec36ea | 364 | } |
bcec36ea AG |
365 | } |
366 | ||
fb01bf4c AJ |
367 | /* PER bits from control register 9 */ |
368 | #define PER_CR9_EVENT_BRANCH 0x80000000 | |
369 | #define PER_CR9_EVENT_IFETCH 0x40000000 | |
370 | #define PER_CR9_EVENT_STORE 0x20000000 | |
371 | #define PER_CR9_EVENT_STORE_REAL 0x08000000 | |
372 | #define PER_CR9_EVENT_NULLIFICATION 0x01000000 | |
373 | #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 | |
374 | #define PER_CR9_CONTROL_ALTERATION 0x00200000 | |
375 | ||
376 | /* PER bits from the PER CODE/ATMID/AI in lowcore */ | |
377 | #define PER_CODE_EVENT_BRANCH 0x8000 | |
378 | #define PER_CODE_EVENT_IFETCH 0x4000 | |
379 | #define PER_CODE_EVENT_STORE 0x2000 | |
380 | #define PER_CODE_EVENT_STORE_REAL 0x0800 | |
381 | #define PER_CODE_EVENT_NULLIFICATION 0x0100 | |
382 | ||
a8f931a9 AJ |
383 | /* Compute the ATMID field that is stored in the per_perc_atmid lowcore |
384 | entry when a PER exception is triggered. */ | |
385 | static inline uint8_t get_per_atmid(CPUS390XState *env) | |
386 | { | |
387 | return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) | | |
388 | ( (1 << 6) ) | | |
389 | ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) | | |
390 | ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) | | |
391 | ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) | | |
392 | ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0); | |
393 | } | |
394 | ||
d453d103 AJ |
395 | /* Check if an address is within the PER starting address and the PER |
396 | ending address. The address range might loop. */ | |
397 | static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr) | |
398 | { | |
399 | if (env->cregs[10] <= env->cregs[11]) { | |
400 | return env->cregs[10] <= addr && addr <= env->cregs[11]; | |
401 | } else { | |
402 | return env->cregs[10] <= addr || addr <= env->cregs[11]; | |
403 | } | |
404 | } | |
405 | ||
d5a103cd RH |
406 | #ifndef CONFIG_USER_ONLY |
407 | /* In several cases of runtime exceptions, we havn't recorded the true | |
408 | instruction length. Use these codes when raising exceptions in order | |
409 | to re-compute the length by examining the insn in memory. */ | |
410 | #define ILEN_LATER 0x20 | |
411 | #define ILEN_LATER_INC 0x21 | |
dfebd7a7 | 412 | void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen); |
d5a103cd | 413 | #endif |
bcec36ea | 414 | |
564b863d | 415 | S390CPU *cpu_s390x_init(const char *cpu_model); |
bcec36ea | 416 | void s390x_translate_init(void); |
10ec5117 | 417 | int cpu_s390x_exec(CPUS390XState *s); |
10ec5117 AG |
418 | |
419 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
420 | signal handlers to inform the virtual CPU of exceptions. non zero | |
421 | is returned if the signal was handled by the virtual CPU. */ | |
422 | int cpu_s390x_signal_handler(int host_signum, void *pinfo, | |
423 | void *puc); | |
7510454e AF |
424 | int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
425 | int mmu_idx); | |
10ec5117 | 426 | |
db1c8f53 | 427 | #include "ioinst.h" |
52705890 | 428 | |
3f10341f | 429 | |
10c339a0 | 430 | #ifndef CONFIG_USER_ONLY |
3f10341f DH |
431 | void do_restart_interrupt(CPUS390XState *env); |
432 | ||
6cb1e49d AY |
433 | static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb, |
434 | uint8_t *ar) | |
7b18aad5 CH |
435 | { |
436 | hwaddr addr = 0; | |
437 | uint8_t reg; | |
438 | ||
439 | reg = ipb >> 28; | |
440 | if (reg > 0) { | |
441 | addr = env->regs[reg]; | |
442 | } | |
443 | addr += (ipb >> 16) & 0xfff; | |
6cb1e49d AY |
444 | if (ar) { |
445 | *ar = reg; | |
446 | } | |
7b18aad5 CH |
447 | |
448 | return addr; | |
449 | } | |
450 | ||
638129ff CH |
451 | /* Base/displacement are at the same locations. */ |
452 | #define decode_basedisp_rs decode_basedisp_s | |
453 | ||
85ca3371 DH |
454 | /* helper functions for run_on_cpu() */ |
455 | static inline void s390_do_cpu_reset(void *arg) | |
456 | { | |
457 | CPUState *cs = arg; | |
458 | S390CPUClass *scc = S390_CPU_GET_CLASS(cs); | |
459 | ||
460 | scc->cpu_reset(cs); | |
461 | } | |
462 | static inline void s390_do_cpu_full_reset(void *arg) | |
463 | { | |
464 | CPUState *cs = arg; | |
465 | ||
466 | cpu_reset(cs); | |
467 | } | |
468 | ||
8f22e0df AF |
469 | void s390x_tod_timer(void *opaque); |
470 | void s390x_cpu_timer(void *opaque); | |
471 | ||
28e942f8 | 472 | int s390_virtio_hypercall(CPUS390XState *env); |
de13d216 | 473 | void s390_virtio_irq(int config_change, uint64_t token); |
bcec36ea | 474 | |
1f206266 | 475 | #ifdef CONFIG_KVM |
de13d216 CH |
476 | void kvm_s390_virtio_irq(int config_change, uint64_t token); |
477 | void kvm_s390_service_interrupt(uint32_t parm); | |
66ad0893 CH |
478 | void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq); |
479 | void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq); | |
bbd8bb8e | 480 | int kvm_s390_inject_flic(struct kvm_s390_irq *irq); |
801cdd35 | 481 | void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code); |
6cb1e49d AY |
482 | int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf, |
483 | int len, bool is_write); | |
3f9e59bb JH |
484 | int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock); |
485 | int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock); | |
1f206266 | 486 | #else |
de13d216 | 487 | static inline void kvm_s390_virtio_irq(int config_change, uint64_t token) |
1f206266 AG |
488 | { |
489 | } | |
de13d216 | 490 | static inline void kvm_s390_service_interrupt(uint32_t parm) |
79afc36d CH |
491 | { |
492 | } | |
3f9e59bb JH |
493 | static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low) |
494 | { | |
495 | return -ENOSYS; | |
496 | } | |
497 | static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low) | |
498 | { | |
499 | return -ENOSYS; | |
500 | } | |
6cb1e49d AY |
501 | static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, |
502 | void *hostbuf, int len, bool is_write) | |
a9bcd1b8 TH |
503 | { |
504 | return -ENOSYS; | |
505 | } | |
801cdd35 TH |
506 | static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, |
507 | uint64_t te_code) | |
508 | { | |
509 | } | |
1f206266 | 510 | #endif |
3f9e59bb JH |
511 | |
512 | static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low) | |
513 | { | |
514 | if (kvm_enabled()) { | |
515 | return kvm_s390_get_clock(tod_high, tod_low); | |
516 | } | |
517 | /* Fixme TCG */ | |
518 | *tod_high = 0; | |
519 | *tod_low = 0; | |
520 | return 0; | |
521 | } | |
522 | ||
523 | static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low) | |
524 | { | |
525 | if (kvm_enabled()) { | |
526 | return kvm_s390_set_clock(tod_high, tod_low); | |
527 | } | |
528 | /* Fixme TCG */ | |
529 | return 0; | |
530 | } | |
531 | ||
45fa769b | 532 | S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); |
eb24f7c6 DH |
533 | unsigned int s390_cpu_halt(S390CPU *cpu); |
534 | void s390_cpu_unhalt(S390CPU *cpu); | |
535 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); | |
18ff9494 DH |
536 | static inline uint8_t s390_cpu_get_state(S390CPU *cpu) |
537 | { | |
538 | return cpu->env.cpu_state; | |
539 | } | |
bcec36ea | 540 | |
3f9e59bb JH |
541 | void gtod_save(QEMUFile *f, void *opaque); |
542 | int gtod_load(QEMUFile *f, void *opaque, int version_id); | |
543 | ||
000a1a38 CB |
544 | /* service interrupts are floating therefore we must not pass an cpustate */ |
545 | void s390_sclp_extint(uint32_t parm); | |
546 | ||
d1ff903c | 547 | /* from s390-virtio-bus */ |
a8170e5e | 548 | extern const hwaddr virtio_size; |
d1ff903c | 549 | |
ef81522b | 550 | #else |
eb24f7c6 DH |
551 | static inline unsigned int s390_cpu_halt(S390CPU *cpu) |
552 | { | |
553 | return 0; | |
554 | } | |
555 | ||
556 | static inline void s390_cpu_unhalt(S390CPU *cpu) | |
ef81522b AG |
557 | { |
558 | } | |
559 | ||
eb24f7c6 | 560 | static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) |
ef81522b AG |
561 | { |
562 | return 0; | |
563 | } | |
10c339a0 | 564 | #endif |
bcec36ea AG |
565 | void cpu_lock(void); |
566 | void cpu_unlock(void); | |
10c339a0 | 567 | |
7b18aad5 CH |
568 | typedef struct SubchDev SubchDev; |
569 | ||
df1fe5bb | 570 | #ifndef CONFIG_USER_ONLY |
4e872a3f | 571 | extern void io_subsystem_reset(void); |
df1fe5bb CH |
572 | SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, |
573 | uint16_t schid); | |
574 | bool css_subch_visible(SubchDev *sch); | |
575 | void css_conditional_io_interrupt(SubchDev *sch); | |
576 | int css_do_stsch(SubchDev *sch, SCHIB *schib); | |
38dd7cc7 | 577 | bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid); |
bffd09cd | 578 | int css_do_msch(SubchDev *sch, const SCHIB *schib); |
df1fe5bb CH |
579 | int css_do_xsch(SubchDev *sch); |
580 | int css_do_csch(SubchDev *sch); | |
581 | int css_do_hsch(SubchDev *sch); | |
582 | int css_do_ssch(SubchDev *sch, ORB *orb); | |
b7b6348a TH |
583 | int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len); |
584 | void css_do_tsch_update_subch(SubchDev *sch); | |
df1fe5bb | 585 | int css_do_stcrw(CRW *crw); |
7f74f0aa | 586 | void css_undo_stcrw(CRW *crw); |
50c8d9bf | 587 | int css_do_tpi(IOIntCode *int_code, int lowcore); |
df1fe5bb CH |
588 | int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, |
589 | int rfmt, void *buf); | |
590 | void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo); | |
591 | int css_enable_mcsse(void); | |
592 | int css_enable_mss(void); | |
593 | int css_do_rsch(SubchDev *sch); | |
594 | int css_do_rchp(uint8_t cssid, uint8_t chpid); | |
595 | bool css_present(uint8_t cssid); | |
df1fe5bb | 596 | #endif |
7b18aad5 | 597 | |
2994fd96 | 598 | #define cpu_init(model) CPU(cpu_s390x_init(model)) |
10ec5117 AG |
599 | #define cpu_exec cpu_s390x_exec |
600 | #define cpu_gen_code cpu_s390x_gen_code | |
bcec36ea | 601 | #define cpu_signal_handler cpu_s390x_signal_handler |
10ec5117 | 602 | |
904e5fd5 VM |
603 | void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
604 | #define cpu_list s390_cpu_list | |
605 | ||
022c62cb | 606 | #include "exec/exec-all.h" |
bcec36ea | 607 | |
bcec36ea AG |
608 | #define EXCP_EXT 1 /* external interrupt */ |
609 | #define EXCP_SVC 2 /* supervisor call (syscall) */ | |
610 | #define EXCP_PGM 3 /* program interruption */ | |
5d69c547 CH |
611 | #define EXCP_IO 7 /* I/O interrupt */ |
612 | #define EXCP_MCHK 8 /* machine check */ | |
bcec36ea | 613 | |
bcec36ea AG |
614 | #define INTERRUPT_EXT (1 << 0) |
615 | #define INTERRUPT_TOD (1 << 1) | |
616 | #define INTERRUPT_CPUTIMER (1 << 2) | |
5d69c547 CH |
617 | #define INTERRUPT_IO (1 << 3) |
618 | #define INTERRUPT_MCHK (1 << 4) | |
10c339a0 AG |
619 | |
620 | /* Program Status Word. */ | |
621 | #define S390_PSWM_REGNUM 0 | |
622 | #define S390_PSWA_REGNUM 1 | |
623 | /* General Purpose Registers. */ | |
624 | #define S390_R0_REGNUM 2 | |
625 | #define S390_R1_REGNUM 3 | |
626 | #define S390_R2_REGNUM 4 | |
627 | #define S390_R3_REGNUM 5 | |
628 | #define S390_R4_REGNUM 6 | |
629 | #define S390_R5_REGNUM 7 | |
630 | #define S390_R6_REGNUM 8 | |
631 | #define S390_R7_REGNUM 9 | |
632 | #define S390_R8_REGNUM 10 | |
633 | #define S390_R9_REGNUM 11 | |
634 | #define S390_R10_REGNUM 12 | |
635 | #define S390_R11_REGNUM 13 | |
636 | #define S390_R12_REGNUM 14 | |
637 | #define S390_R13_REGNUM 15 | |
638 | #define S390_R14_REGNUM 16 | |
639 | #define S390_R15_REGNUM 17 | |
73d510c9 DH |
640 | /* Total Core Registers. */ |
641 | #define S390_NUM_CORE_REGS 18 | |
10c339a0 | 642 | |
bcec36ea AG |
643 | /* CC optimization */ |
644 | ||
645 | enum cc_op { | |
646 | CC_OP_CONST0 = 0, /* CC is 0 */ | |
647 | CC_OP_CONST1, /* CC is 1 */ | |
648 | CC_OP_CONST2, /* CC is 2 */ | |
649 | CC_OP_CONST3, /* CC is 3 */ | |
650 | ||
651 | CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */ | |
652 | CC_OP_STATIC, /* CC value is env->cc_op */ | |
653 | ||
654 | CC_OP_NZ, /* env->cc_dst != 0 */ | |
655 | CC_OP_LTGT_32, /* signed less/greater than (32bit) */ | |
656 | CC_OP_LTGT_64, /* signed less/greater than (64bit) */ | |
657 | CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */ | |
658 | CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */ | |
659 | CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */ | |
660 | CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */ | |
661 | ||
662 | CC_OP_ADD_64, /* overflow on add (64bit) */ | |
663 | CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */ | |
4e4bb438 | 664 | CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */ |
e7d81004 SW |
665 | CC_OP_SUB_64, /* overflow on subtraction (64bit) */ |
666 | CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */ | |
4e4bb438 | 667 | CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */ |
bcec36ea AG |
668 | CC_OP_ABS_64, /* sign eval on abs (64bit) */ |
669 | CC_OP_NABS_64, /* sign eval on nabs (64bit) */ | |
670 | ||
671 | CC_OP_ADD_32, /* overflow on add (32bit) */ | |
672 | CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */ | |
4e4bb438 | 673 | CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */ |
e7d81004 SW |
674 | CC_OP_SUB_32, /* overflow on subtraction (32bit) */ |
675 | CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */ | |
4e4bb438 | 676 | CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */ |
bcec36ea AG |
677 | CC_OP_ABS_32, /* sign eval on abs (64bit) */ |
678 | CC_OP_NABS_32, /* sign eval on nabs (64bit) */ | |
679 | ||
680 | CC_OP_COMP_32, /* complement */ | |
681 | CC_OP_COMP_64, /* complement */ | |
682 | ||
683 | CC_OP_TM_32, /* test under mask (32bit) */ | |
684 | CC_OP_TM_64, /* test under mask (64bit) */ | |
685 | ||
bcec36ea AG |
686 | CC_OP_NZ_F32, /* FP dst != 0 (32bit) */ |
687 | CC_OP_NZ_F64, /* FP dst != 0 (64bit) */ | |
587626f8 | 688 | CC_OP_NZ_F128, /* FP dst != 0 (128bit) */ |
bcec36ea AG |
689 | |
690 | CC_OP_ICM, /* insert characters under mask */ | |
cbe24bfa RH |
691 | CC_OP_SLA_32, /* Calculate shift left signed (32bit) */ |
692 | CC_OP_SLA_64, /* Calculate shift left signed (64bit) */ | |
102bf2c6 | 693 | CC_OP_FLOGR, /* find leftmost one */ |
bcec36ea AG |
694 | CC_OP_MAX |
695 | }; | |
696 | ||
697 | static const char *cc_names[] = { | |
698 | [CC_OP_CONST0] = "CC_OP_CONST0", | |
699 | [CC_OP_CONST1] = "CC_OP_CONST1", | |
700 | [CC_OP_CONST2] = "CC_OP_CONST2", | |
701 | [CC_OP_CONST3] = "CC_OP_CONST3", | |
702 | [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC", | |
703 | [CC_OP_STATIC] = "CC_OP_STATIC", | |
704 | [CC_OP_NZ] = "CC_OP_NZ", | |
705 | [CC_OP_LTGT_32] = "CC_OP_LTGT_32", | |
706 | [CC_OP_LTGT_64] = "CC_OP_LTGT_64", | |
707 | [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32", | |
708 | [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64", | |
709 | [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32", | |
710 | [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64", | |
711 | [CC_OP_ADD_64] = "CC_OP_ADD_64", | |
712 | [CC_OP_ADDU_64] = "CC_OP_ADDU_64", | |
4e4bb438 | 713 | [CC_OP_ADDC_64] = "CC_OP_ADDC_64", |
bcec36ea AG |
714 | [CC_OP_SUB_64] = "CC_OP_SUB_64", |
715 | [CC_OP_SUBU_64] = "CC_OP_SUBU_64", | |
4e4bb438 | 716 | [CC_OP_SUBB_64] = "CC_OP_SUBB_64", |
bcec36ea AG |
717 | [CC_OP_ABS_64] = "CC_OP_ABS_64", |
718 | [CC_OP_NABS_64] = "CC_OP_NABS_64", | |
719 | [CC_OP_ADD_32] = "CC_OP_ADD_32", | |
720 | [CC_OP_ADDU_32] = "CC_OP_ADDU_32", | |
4e4bb438 | 721 | [CC_OP_ADDC_32] = "CC_OP_ADDC_32", |
bcec36ea AG |
722 | [CC_OP_SUB_32] = "CC_OP_SUB_32", |
723 | [CC_OP_SUBU_32] = "CC_OP_SUBU_32", | |
4e4bb438 | 724 | [CC_OP_SUBB_32] = "CC_OP_SUBB_32", |
bcec36ea AG |
725 | [CC_OP_ABS_32] = "CC_OP_ABS_32", |
726 | [CC_OP_NABS_32] = "CC_OP_NABS_32", | |
727 | [CC_OP_COMP_32] = "CC_OP_COMP_32", | |
728 | [CC_OP_COMP_64] = "CC_OP_COMP_64", | |
729 | [CC_OP_TM_32] = "CC_OP_TM_32", | |
730 | [CC_OP_TM_64] = "CC_OP_TM_64", | |
bcec36ea AG |
731 | [CC_OP_NZ_F32] = "CC_OP_NZ_F32", |
732 | [CC_OP_NZ_F64] = "CC_OP_NZ_F64", | |
587626f8 | 733 | [CC_OP_NZ_F128] = "CC_OP_NZ_F128", |
bcec36ea | 734 | [CC_OP_ICM] = "CC_OP_ICM", |
cbe24bfa RH |
735 | [CC_OP_SLA_32] = "CC_OP_SLA_32", |
736 | [CC_OP_SLA_64] = "CC_OP_SLA_64", | |
102bf2c6 | 737 | [CC_OP_FLOGR] = "CC_OP_FLOGR", |
bcec36ea AG |
738 | }; |
739 | ||
740 | static inline const char *cc_name(int cc_op) | |
741 | { | |
742 | return cc_names[cc_op]; | |
743 | } | |
744 | ||
3d0a615f TH |
745 | static inline void setcc(S390CPU *cpu, uint64_t cc) |
746 | { | |
747 | CPUS390XState *env = &cpu->env; | |
748 | ||
749 | env->psw.mask &= ~(3ull << 44); | |
750 | env->psw.mask |= (cc & 3) << 44; | |
06e3c077 | 751 | env->cc_op = cc; |
3d0a615f TH |
752 | } |
753 | ||
bcec36ea AG |
754 | typedef struct LowCore |
755 | { | |
756 | /* prefix area: defined by architecture */ | |
757 | uint32_t ccw1[2]; /* 0x000 */ | |
758 | uint32_t ccw2[4]; /* 0x008 */ | |
759 | uint8_t pad1[0x80-0x18]; /* 0x018 */ | |
760 | uint32_t ext_params; /* 0x080 */ | |
761 | uint16_t cpu_addr; /* 0x084 */ | |
762 | uint16_t ext_int_code; /* 0x086 */ | |
d5a103cd | 763 | uint16_t svc_ilen; /* 0x088 */ |
bcec36ea | 764 | uint16_t svc_code; /* 0x08a */ |
d5a103cd | 765 | uint16_t pgm_ilen; /* 0x08c */ |
bcec36ea AG |
766 | uint16_t pgm_code; /* 0x08e */ |
767 | uint32_t data_exc_code; /* 0x090 */ | |
768 | uint16_t mon_class_num; /* 0x094 */ | |
769 | uint16_t per_perc_atmid; /* 0x096 */ | |
770 | uint64_t per_address; /* 0x098 */ | |
771 | uint8_t exc_access_id; /* 0x0a0 */ | |
772 | uint8_t per_access_id; /* 0x0a1 */ | |
773 | uint8_t op_access_id; /* 0x0a2 */ | |
774 | uint8_t ar_access_id; /* 0x0a3 */ | |
775 | uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */ | |
776 | uint64_t trans_exc_code; /* 0x0a8 */ | |
777 | uint64_t monitor_code; /* 0x0b0 */ | |
778 | uint16_t subchannel_id; /* 0x0b8 */ | |
779 | uint16_t subchannel_nr; /* 0x0ba */ | |
780 | uint32_t io_int_parm; /* 0x0bc */ | |
781 | uint32_t io_int_word; /* 0x0c0 */ | |
782 | uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */ | |
783 | uint32_t stfl_fac_list; /* 0x0c8 */ | |
784 | uint8_t pad4[0xe8-0xcc]; /* 0x0cc */ | |
785 | uint32_t mcck_interruption_code[2]; /* 0x0e8 */ | |
786 | uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */ | |
787 | uint32_t external_damage_code; /* 0x0f4 */ | |
788 | uint64_t failing_storage_address; /* 0x0f8 */ | |
789 | uint8_t pad6[0x120-0x100]; /* 0x100 */ | |
790 | PSW restart_old_psw; /* 0x120 */ | |
791 | PSW external_old_psw; /* 0x130 */ | |
792 | PSW svc_old_psw; /* 0x140 */ | |
793 | PSW program_old_psw; /* 0x150 */ | |
794 | PSW mcck_old_psw; /* 0x160 */ | |
795 | PSW io_old_psw; /* 0x170 */ | |
796 | uint8_t pad7[0x1a0-0x180]; /* 0x180 */ | |
3f10341f | 797 | PSW restart_new_psw; /* 0x1a0 */ |
bcec36ea AG |
798 | PSW external_new_psw; /* 0x1b0 */ |
799 | PSW svc_new_psw; /* 0x1c0 */ | |
800 | PSW program_new_psw; /* 0x1d0 */ | |
801 | PSW mcck_new_psw; /* 0x1e0 */ | |
802 | PSW io_new_psw; /* 0x1f0 */ | |
803 | PSW return_psw; /* 0x200 */ | |
804 | uint8_t irb[64]; /* 0x210 */ | |
805 | uint64_t sync_enter_timer; /* 0x250 */ | |
806 | uint64_t async_enter_timer; /* 0x258 */ | |
807 | uint64_t exit_timer; /* 0x260 */ | |
808 | uint64_t last_update_timer; /* 0x268 */ | |
809 | uint64_t user_timer; /* 0x270 */ | |
810 | uint64_t system_timer; /* 0x278 */ | |
811 | uint64_t last_update_clock; /* 0x280 */ | |
812 | uint64_t steal_clock; /* 0x288 */ | |
813 | PSW return_mcck_psw; /* 0x290 */ | |
814 | uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */ | |
815 | /* System info area */ | |
816 | uint64_t save_area[16]; /* 0xc00 */ | |
817 | uint8_t pad9[0xd40-0xc80]; /* 0xc80 */ | |
818 | uint64_t kernel_stack; /* 0xd40 */ | |
819 | uint64_t thread_info; /* 0xd48 */ | |
820 | uint64_t async_stack; /* 0xd50 */ | |
821 | uint64_t kernel_asce; /* 0xd58 */ | |
822 | uint64_t user_asce; /* 0xd60 */ | |
823 | uint64_t panic_stack; /* 0xd68 */ | |
824 | uint64_t user_exec_asce; /* 0xd70 */ | |
825 | uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */ | |
826 | ||
827 | /* SMP info area: defined by DJB */ | |
828 | uint64_t clock_comparator; /* 0xdc0 */ | |
829 | uint64_t ext_call_fast; /* 0xdc8 */ | |
830 | uint64_t percpu_offset; /* 0xdd0 */ | |
831 | uint64_t current_task; /* 0xdd8 */ | |
832 | uint32_t softirq_pending; /* 0xde0 */ | |
833 | uint32_t pad_0x0de4; /* 0xde4 */ | |
834 | uint64_t int_clock; /* 0xde8 */ | |
835 | uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */ | |
836 | ||
837 | /* 0xe00 is used as indicator for dump tools */ | |
838 | /* whether the kernel died with panic() or not */ | |
839 | uint32_t panic_magic; /* 0xe00 */ | |
840 | ||
841 | uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */ | |
842 | ||
843 | /* 64 bit extparam used for pfault, diag 250 etc */ | |
844 | uint64_t ext_params2; /* 0x11B8 */ | |
845 | ||
846 | uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */ | |
847 | ||
848 | /* System info area */ | |
849 | ||
850 | uint64_t floating_pt_save_area[16]; /* 0x1200 */ | |
851 | uint64_t gpregs_save_area[16]; /* 0x1280 */ | |
852 | uint32_t st_status_fixed_logout[4]; /* 0x1300 */ | |
853 | uint8_t pad15[0x1318-0x1310]; /* 0x1310 */ | |
854 | uint32_t prefixreg_save_area; /* 0x1318 */ | |
855 | uint32_t fpt_creg_save_area; /* 0x131c */ | |
856 | uint8_t pad16[0x1324-0x1320]; /* 0x1320 */ | |
857 | uint32_t tod_progreg_save_area; /* 0x1324 */ | |
858 | uint32_t cpu_timer_save_area[2]; /* 0x1328 */ | |
859 | uint32_t clock_comp_save_area[2]; /* 0x1330 */ | |
860 | uint8_t pad17[0x1340-0x1338]; /* 0x1338 */ | |
861 | uint32_t access_regs_save_area[16]; /* 0x1340 */ | |
862 | uint64_t cregs_save_area[16]; /* 0x1380 */ | |
863 | ||
864 | /* align to the top of the prefix area */ | |
865 | ||
866 | uint8_t pad18[0x2000-0x1400]; /* 0x1400 */ | |
541dc0d4 | 867 | } QEMU_PACKED LowCore; |
bcec36ea AG |
868 | |
869 | /* STSI */ | |
870 | #define STSI_LEVEL_MASK 0x00000000f0000000ULL | |
871 | #define STSI_LEVEL_CURRENT 0x0000000000000000ULL | |
872 | #define STSI_LEVEL_1 0x0000000010000000ULL | |
873 | #define STSI_LEVEL_2 0x0000000020000000ULL | |
874 | #define STSI_LEVEL_3 0x0000000030000000ULL | |
875 | #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL | |
876 | #define STSI_R0_SEL1_MASK 0x00000000000000ffULL | |
877 | #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL | |
878 | #define STSI_R1_SEL2_MASK 0x000000000000ffffULL | |
879 | ||
880 | /* Basic Machine Configuration */ | |
881 | struct sysib_111 { | |
882 | uint32_t res1[8]; | |
883 | uint8_t manuf[16]; | |
884 | uint8_t type[4]; | |
885 | uint8_t res2[12]; | |
886 | uint8_t model[16]; | |
887 | uint8_t sequence[16]; | |
888 | uint8_t plant[4]; | |
889 | uint8_t res3[156]; | |
890 | }; | |
891 | ||
892 | /* Basic Machine CPU */ | |
893 | struct sysib_121 { | |
894 | uint32_t res1[80]; | |
895 | uint8_t sequence[16]; | |
896 | uint8_t plant[4]; | |
897 | uint8_t res2[2]; | |
898 | uint16_t cpu_addr; | |
899 | uint8_t res3[152]; | |
900 | }; | |
901 | ||
902 | /* Basic Machine CPUs */ | |
903 | struct sysib_122 { | |
904 | uint8_t res1[32]; | |
905 | uint32_t capability; | |
906 | uint16_t total_cpus; | |
907 | uint16_t active_cpus; | |
908 | uint16_t standby_cpus; | |
909 | uint16_t reserved_cpus; | |
910 | uint16_t adjustments[2026]; | |
911 | }; | |
912 | ||
913 | /* LPAR CPU */ | |
914 | struct sysib_221 { | |
915 | uint32_t res1[80]; | |
916 | uint8_t sequence[16]; | |
917 | uint8_t plant[4]; | |
918 | uint16_t cpu_id; | |
919 | uint16_t cpu_addr; | |
920 | uint8_t res3[152]; | |
921 | }; | |
922 | ||
923 | /* LPAR CPUs */ | |
924 | struct sysib_222 { | |
925 | uint32_t res1[32]; | |
926 | uint16_t lpar_num; | |
927 | uint8_t res2; | |
928 | uint8_t lcpuc; | |
929 | uint16_t total_cpus; | |
930 | uint16_t conf_cpus; | |
931 | uint16_t standby_cpus; | |
932 | uint16_t reserved_cpus; | |
933 | uint8_t name[8]; | |
934 | uint32_t caf; | |
935 | uint8_t res3[16]; | |
936 | uint16_t dedicated_cpus; | |
937 | uint16_t shared_cpus; | |
938 | uint8_t res4[180]; | |
939 | }; | |
940 | ||
941 | /* VM CPUs */ | |
942 | struct sysib_322 { | |
943 | uint8_t res1[31]; | |
944 | uint8_t count; | |
945 | struct { | |
946 | uint8_t res2[4]; | |
947 | uint16_t total_cpus; | |
948 | uint16_t conf_cpus; | |
949 | uint16_t standby_cpus; | |
950 | uint16_t reserved_cpus; | |
951 | uint8_t name[8]; | |
952 | uint32_t caf; | |
953 | uint8_t cpi[16]; | |
f07177a5 ET |
954 | uint8_t res5[3]; |
955 | uint8_t ext_name_encoding; | |
956 | uint32_t res3; | |
957 | uint8_t uuid[16]; | |
bcec36ea | 958 | } vm[8]; |
f07177a5 ET |
959 | uint8_t res4[1504]; |
960 | uint8_t ext_names[8][256]; | |
bcec36ea AG |
961 | }; |
962 | ||
963 | /* MMU defines */ | |
964 | #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ | |
965 | #define _ASCE_SUBSPACE 0x200 /* subspace group control */ | |
966 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
967 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
968 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
969 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
970 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
971 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
972 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
973 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
974 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
975 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
976 | ||
977 | #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ | |
43d49b01 | 978 | #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */ |
5d180439 | 979 | #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */ |
bcec36ea AG |
980 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ |
981 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
982 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
983 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
984 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
985 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
986 | ||
987 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ | |
c4400206 | 988 | #define _SEGMENT_ENTRY_FC 0x400 /* format control */ |
bcec36ea AG |
989 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ |
990 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
991 | ||
992 | #define _PAGE_RO 0x200 /* HW read-only bit */ | |
993 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
b4ecbf80 | 994 | #define _PAGE_RES0 0x800 /* bit must be zero */ |
bcec36ea | 995 | |
b9959138 AG |
996 | #define SK_C (0x1 << 1) |
997 | #define SK_R (0x1 << 2) | |
998 | #define SK_F (0x1 << 3) | |
999 | #define SK_ACC_MASK (0xf << 4) | |
bcec36ea | 1000 | |
5172b780 | 1001 | /* SIGP order codes */ |
bcec36ea AG |
1002 | #define SIGP_SENSE 0x01 |
1003 | #define SIGP_EXTERNAL_CALL 0x02 | |
1004 | #define SIGP_EMERGENCY 0x03 | |
1005 | #define SIGP_START 0x04 | |
1006 | #define SIGP_STOP 0x05 | |
1007 | #define SIGP_RESTART 0x06 | |
1008 | #define SIGP_STOP_STORE_STATUS 0x09 | |
1009 | #define SIGP_INITIAL_CPU_RESET 0x0b | |
1010 | #define SIGP_CPU_RESET 0x0c | |
1011 | #define SIGP_SET_PREFIX 0x0d | |
1012 | #define SIGP_STORE_STATUS_ADDR 0x0e | |
1013 | #define SIGP_SET_ARCH 0x12 | |
abec5356 | 1014 | #define SIGP_STORE_ADTL_STATUS 0x17 |
bcec36ea | 1015 | |
5172b780 DH |
1016 | /* SIGP condition codes */ |
1017 | #define SIGP_CC_ORDER_CODE_ACCEPTED 0 | |
1018 | #define SIGP_CC_STATUS_STORED 1 | |
1019 | #define SIGP_CC_BUSY 2 | |
1020 | #define SIGP_CC_NOT_OPERATIONAL 3 | |
1021 | ||
1022 | /* SIGP status bits */ | |
bcec36ea AG |
1023 | #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL |
1024 | #define SIGP_STAT_INCORRECT_STATE 0x00000200UL | |
1025 | #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL | |
1026 | #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL | |
1027 | #define SIGP_STAT_STOPPED 0x00000040UL | |
1028 | #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL | |
1029 | #define SIGP_STAT_CHECK_STOP 0x00000010UL | |
1030 | #define SIGP_STAT_INOPERATIVE 0x00000004UL | |
1031 | #define SIGP_STAT_INVALID_ORDER 0x00000002UL | |
1032 | #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL | |
1033 | ||
18ff9494 DH |
1034 | /* SIGP SET ARCHITECTURE modes */ |
1035 | #define SIGP_MODE_ESA_S390 0 | |
1036 | #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 | |
1037 | #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 | |
1038 | ||
a4e3ad19 AF |
1039 | void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); |
1040 | int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, | |
e3e09d87 | 1041 | target_ulong *raddr, int *flags, bool exc); |
6e252802 | 1042 | int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code); |
a4e3ad19 | 1043 | uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, |
bcec36ea AG |
1044 | uint64_t vr); |
1045 | ||
6cb1e49d AY |
1046 | int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, |
1047 | int len, bool is_write); | |
c3edd628 | 1048 | |
6cb1e49d AY |
1049 | #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ |
1050 | s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) | |
1051 | #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ | |
1052 | s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) | |
1053 | #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ | |
1054 | s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) | |
c3edd628 | 1055 | |
bcec36ea AG |
1056 | /* The value of the TOD clock for 1.1.1970. */ |
1057 | #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL | |
1058 | ||
1059 | /* Converts ns to s390's clock format */ | |
1060 | static inline uint64_t time2tod(uint64_t ns) { | |
1061 | return (ns << 9) / 125; | |
1062 | } | |
1063 | ||
9cb32c44 AJ |
1064 | /* Converts s390's clock format to ns */ |
1065 | static inline uint64_t tod2time(uint64_t t) { | |
1066 | return (t * 125) >> 9; | |
1067 | } | |
1068 | ||
f9466733 | 1069 | static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param, |
bcec36ea AG |
1070 | uint64_t param64) |
1071 | { | |
f9466733 AF |
1072 | CPUS390XState *env = &cpu->env; |
1073 | ||
bcec36ea AG |
1074 | if (env->ext_index == MAX_EXT_QUEUE - 1) { |
1075 | /* ugh - can't queue anymore. Let's drop. */ | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | env->ext_index++; | |
1080 | assert(env->ext_index < MAX_EXT_QUEUE); | |
1081 | ||
1082 | env->ext_queue[env->ext_index].code = code; | |
1083 | env->ext_queue[env->ext_index].param = param; | |
1084 | env->ext_queue[env->ext_index].param64 = param64; | |
1085 | ||
1086 | env->pending_int |= INTERRUPT_EXT; | |
c3affe56 | 1087 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
bcec36ea | 1088 | } |
10c339a0 | 1089 | |
f9466733 | 1090 | static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id, |
5d69c547 CH |
1091 | uint16_t subchannel_number, |
1092 | uint32_t io_int_parm, uint32_t io_int_word) | |
1093 | { | |
f9466733 | 1094 | CPUS390XState *env = &cpu->env; |
91b0a8f3 | 1095 | int isc = IO_INT_WORD_ISC(io_int_word); |
5d69c547 CH |
1096 | |
1097 | if (env->io_index[isc] == MAX_IO_QUEUE - 1) { | |
1098 | /* ugh - can't queue anymore. Let's drop. */ | |
1099 | return; | |
1100 | } | |
1101 | ||
1102 | env->io_index[isc]++; | |
1103 | assert(env->io_index[isc] < MAX_IO_QUEUE); | |
1104 | ||
1105 | env->io_queue[env->io_index[isc]][isc].id = subchannel_id; | |
1106 | env->io_queue[env->io_index[isc]][isc].nr = subchannel_number; | |
1107 | env->io_queue[env->io_index[isc]][isc].parm = io_int_parm; | |
1108 | env->io_queue[env->io_index[isc]][isc].word = io_int_word; | |
1109 | ||
1110 | env->pending_int |= INTERRUPT_IO; | |
c3affe56 | 1111 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
5d69c547 CH |
1112 | } |
1113 | ||
f9466733 | 1114 | static inline void cpu_inject_crw_mchk(S390CPU *cpu) |
5d69c547 | 1115 | { |
f9466733 AF |
1116 | CPUS390XState *env = &cpu->env; |
1117 | ||
5d69c547 CH |
1118 | if (env->mchk_index == MAX_MCHK_QUEUE - 1) { |
1119 | /* ugh - can't queue anymore. Let's drop. */ | |
1120 | return; | |
1121 | } | |
1122 | ||
1123 | env->mchk_index++; | |
1124 | assert(env->mchk_index < MAX_MCHK_QUEUE); | |
1125 | ||
1126 | env->mchk_queue[env->mchk_index].type = 1; | |
1127 | ||
1128 | env->pending_int |= INTERRUPT_MCHK; | |
c3affe56 | 1129 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
5d69c547 CH |
1130 | } |
1131 | ||
b6fe0124 MR |
1132 | /* from s390-virtio-ccw */ |
1133 | #define MEM_SECTION_SIZE 0x10000000UL | |
1def6656 | 1134 | #define MAX_AVAIL_SLOTS 32 |
b6fe0124 | 1135 | |
e72ca652 | 1136 | /* fpu_helper.c */ |
e72ca652 BS |
1137 | uint32_t set_cc_nz_f32(float32 v); |
1138 | uint32_t set_cc_nz_f64(float64 v); | |
587626f8 | 1139 | uint32_t set_cc_nz_f128(float128 v); |
e72ca652 | 1140 | |
aea1e885 | 1141 | /* misc_helper.c */ |
268846ba | 1142 | #ifndef CONFIG_USER_ONLY |
8fc639af | 1143 | int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3); |
268846ba ED |
1144 | void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3); |
1145 | #endif | |
d5a103cd | 1146 | void program_interrupt(CPUS390XState *env, uint32_t code, int ilen); |
b4e2bd35 RH |
1147 | void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, |
1148 | uintptr_t retaddr); | |
a78b0504 | 1149 | |
09b99878 | 1150 | #ifdef CONFIG_KVM |
de13d216 | 1151 | void kvm_s390_io_interrupt(uint16_t subchannel_id, |
09b99878 CH |
1152 | uint16_t subchannel_nr, uint32_t io_int_parm, |
1153 | uint32_t io_int_word); | |
de13d216 | 1154 | void kvm_s390_crw_mchk(void); |
09b99878 | 1155 | void kvm_s390_enable_css_support(S390CPU *cpu); |
cc3ac9c4 CH |
1156 | int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch, |
1157 | int vq, bool assign); | |
7f7f9752 | 1158 | int kvm_s390_cpu_restart(S390CPU *cpu); |
1def6656 | 1159 | int kvm_s390_get_memslot_count(KVMState *s); |
4cb88c3c | 1160 | void kvm_s390_clear_cmma_callback(void *opaque); |
c9e659c9 | 1161 | int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state); |
99607144 | 1162 | void kvm_s390_reset_vcpu(S390CPU *cpu); |
a310b283 | 1163 | int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit); |
3cda44f7 JF |
1164 | void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu); |
1165 | int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu); | |
09b99878 | 1166 | #else |
de13d216 | 1167 | static inline void kvm_s390_io_interrupt(uint16_t subchannel_id, |
df1fe5bb CH |
1168 | uint16_t subchannel_nr, |
1169 | uint32_t io_int_parm, | |
1170 | uint32_t io_int_word) | |
1171 | { | |
1172 | } | |
de13d216 | 1173 | static inline void kvm_s390_crw_mchk(void) |
df1fe5bb CH |
1174 | { |
1175 | } | |
09b99878 CH |
1176 | static inline void kvm_s390_enable_css_support(S390CPU *cpu) |
1177 | { | |
1178 | } | |
cc3ac9c4 CH |
1179 | static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, |
1180 | uint32_t sch, int vq, | |
b4436a0b CH |
1181 | bool assign) |
1182 | { | |
1183 | return -ENOSYS; | |
1184 | } | |
7f7f9752 ED |
1185 | static inline int kvm_s390_cpu_restart(S390CPU *cpu) |
1186 | { | |
1187 | return -ENOSYS; | |
1188 | } | |
4cb88c3c DD |
1189 | static inline void kvm_s390_clear_cmma_callback(void *opaque) |
1190 | { | |
1191 | } | |
1def6656 MR |
1192 | static inline int kvm_s390_get_memslot_count(KVMState *s) |
1193 | { | |
1194 | return MAX_AVAIL_SLOTS; | |
1195 | } | |
c9e659c9 DH |
1196 | static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state) |
1197 | { | |
1198 | return -ENOSYS; | |
1199 | } | |
99607144 DH |
1200 | static inline void kvm_s390_reset_vcpu(S390CPU *cpu) |
1201 | { | |
1202 | } | |
a310b283 DD |
1203 | static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, |
1204 | uint64_t *hw_limit) | |
1205 | { | |
1206 | return 0; | |
1207 | } | |
3cda44f7 JF |
1208 | static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu) |
1209 | { | |
1210 | } | |
1211 | static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu) | |
1212 | { | |
1213 | return 0; | |
1214 | } | |
09b99878 | 1215 | #endif |
df1fe5bb | 1216 | |
a310b283 DD |
1217 | static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit) |
1218 | { | |
1219 | if (kvm_enabled()) { | |
1220 | return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit); | |
1221 | } | |
1222 | return 0; | |
1223 | } | |
1224 | ||
4cb88c3c DD |
1225 | static inline void cmma_reset(S390CPU *cpu) |
1226 | { | |
1227 | if (kvm_enabled()) { | |
1228 | CPUState *cs = CPU(cpu); | |
1229 | kvm_s390_clear_cmma_callback(cs->kvm_state); | |
1230 | } | |
1231 | } | |
1232 | ||
7f7f9752 ED |
1233 | static inline int s390_cpu_restart(S390CPU *cpu) |
1234 | { | |
1235 | if (kvm_enabled()) { | |
1236 | return kvm_s390_cpu_restart(cpu); | |
1237 | } | |
1238 | return -ENOSYS; | |
1239 | } | |
1240 | ||
1def6656 MR |
1241 | static inline int s390_get_memslot_count(KVMState *s) |
1242 | { | |
1243 | if (kvm_enabled()) { | |
1244 | return kvm_s390_get_memslot_count(s); | |
1245 | } else { | |
1246 | return MAX_AVAIL_SLOTS; | |
1247 | } | |
1248 | } | |
1249 | ||
de13d216 CH |
1250 | void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, |
1251 | uint32_t io_int_parm, uint32_t io_int_word); | |
1252 | void s390_crw_mchk(void); | |
df1fe5bb | 1253 | |
cc3ac9c4 CH |
1254 | static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier, |
1255 | uint32_t sch_id, int vq, | |
b4436a0b CH |
1256 | bool assign) |
1257 | { | |
a499973f | 1258 | return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign); |
b4436a0b CH |
1259 | } |
1260 | ||
b2ac0ff5 EF |
1261 | #ifdef CONFIG_KVM |
1262 | static inline bool vregs_needed(void *opaque) | |
1263 | { | |
1264 | if (kvm_enabled()) { | |
1265 | return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS); | |
1266 | } | |
1267 | return 0; | |
1268 | } | |
1269 | #else | |
1270 | static inline bool vregs_needed(void *opaque) | |
1271 | { | |
1272 | return 0; | |
1273 | } | |
1274 | #endif | |
10ec5117 | 1275 | #endif |