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s390x/kvm: Put vm name, extended name and UUID into STSI322 SYSIB
[mirror_qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
44b0c0bb
CB		 129 uint64_t gbea;
130 uint64_t pp;
131
4e836781
AG		 132 CPU_COMMON
133
bcec36ea
AG		 134 /* reset does memset(0) up to here */
135
7f745b31
RH		 136 uint32_t cpu_num;
137 uint32_t machine_type;
138
bcec36ea
AG		 139 uint8_t *storage_keys;
140
141 uint64_t tod_offset;
142 uint64_t tod_basetime;
143 QEMUTimer *tod_timer;
144
145 QEMUTimer *cpu_timer;
75973bfe
DH		 146
147 /*
148 * The cpu state represents the logical state of a cpu. In contrast to other
149 * architectures, there is a difference between a halt and a stop on s390.
150 * If all cpus are either stopped (including check stop) or in the disabled
151 * wait state, the vm can be shut down.
152 */
153#define CPU_STATE_UNINITIALIZED 0x00
154#define CPU_STATE_STOPPED 0x01
155#define CPU_STATE_CHECK_STOP 0x02
156#define CPU_STATE_OPERATING 0x03
157#define CPU_STATE_LOAD 0x04
158 uint8_t cpu_state;
159
18ff9494
DH		 160 /* currently processed sigp order */
161 uint8_t sigp_order;
162
10ec5117
AG		 163} CPUS390XState;
164
564b863d 165#include "cpu-qom.h"
3d0a615f 166#include <sysemu/kvm.h>
564b863d 167
7b18aad5
CH		 168/* distinguish between 24 bit and 31 bit addressing */
169#define HIGH_ORDER_BIT 0x80000000
170
bcec36ea
AG		 171/* Interrupt Codes */
172/* Program Interrupts */
173#define PGM_OPERATION 0x0001
174#define PGM_PRIVILEGED 0x0002
175#define PGM_EXECUTE 0x0003
176#define PGM_PROTECTION 0x0004
177#define PGM_ADDRESSING 0x0005
178#define PGM_SPECIFICATION 0x0006
179#define PGM_DATA 0x0007
180#define PGM_FIXPT_OVERFLOW 0x0008
181#define PGM_FIXPT_DIVIDE 0x0009
182#define PGM_DEC_OVERFLOW 0x000a
183#define PGM_DEC_DIVIDE 0x000b
184#define PGM_HFP_EXP_OVERFLOW 0x000c
185#define PGM_HFP_EXP_UNDERFLOW 0x000d
186#define PGM_HFP_SIGNIFICANCE 0x000e
187#define PGM_HFP_DIVIDE 0x000f
188#define PGM_SEGMENT_TRANS 0x0010
189#define PGM_PAGE_TRANS 0x0011
190#define PGM_TRANS_SPEC 0x0012
191#define PGM_SPECIAL_OP 0x0013
192#define PGM_OPERAND 0x0015
193#define PGM_TRACE_TABLE 0x0016
194#define PGM_SPACE_SWITCH 0x001c
195#define PGM_HFP_SQRT 0x001d
196#define PGM_PC_TRANS_SPEC 0x001f
197#define PGM_AFX_TRANS 0x0020
198#define PGM_ASX_TRANS 0x0021
199#define PGM_LX_TRANS 0x0022
200#define PGM_EX_TRANS 0x0023
201#define PGM_PRIM_AUTH 0x0024
202#define PGM_SEC_AUTH 0x0025
203#define PGM_ALET_SPEC 0x0028
204#define PGM_ALEN_SPEC 0x0029
205#define PGM_ALE_SEQ 0x002a
206#define PGM_ASTE_VALID 0x002b
207#define PGM_ASTE_SEQ 0x002c
208#define PGM_EXT_AUTH 0x002d
209#define PGM_STACK_FULL 0x0030
210#define PGM_STACK_EMPTY 0x0031
211#define PGM_STACK_SPEC 0x0032
212#define PGM_STACK_TYPE 0x0033
213#define PGM_STACK_OP 0x0034
214#define PGM_ASCE_TYPE 0x0038
215#define PGM_REG_FIRST_TRANS 0x0039
216#define PGM_REG_SEC_TRANS 0x003a
217#define PGM_REG_THIRD_TRANS 0x003b
218#define PGM_MONITOR 0x0040
219#define PGM_PER 0x0080
220#define PGM_CRYPTO 0x0119
221
222/* External Interrupts */
223#define EXT_INTERRUPT_KEY 0x0040
224#define EXT_CLOCK_COMP 0x1004
225#define EXT_CPU_TIMER 0x1005
226#define EXT_MALFUNCTION 0x1200
227#define EXT_EMERGENCY 0x1201
228#define EXT_EXTERNAL_CALL 0x1202
229#define EXT_ETR 0x1406
230#define EXT_SERVICE 0x2401
231#define EXT_VIRTIO 0x2603
232
233/* PSW defines */
234#undef PSW_MASK_PER
235#undef PSW_MASK_DAT
236#undef PSW_MASK_IO
237#undef PSW_MASK_EXT
238#undef PSW_MASK_KEY
239#undef PSW_SHIFT_KEY
240#undef PSW_MASK_MCHECK
241#undef PSW_MASK_WAIT
242#undef PSW_MASK_PSTATE
243#undef PSW_MASK_ASC
244#undef PSW_MASK_CC
245#undef PSW_MASK_PM
246#undef PSW_MASK_64
29c6157c
CB		 247#undef PSW_MASK_32
248#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 249
250#define PSW_MASK_PER 0x4000000000000000ULL
251#define PSW_MASK_DAT 0x0400000000000000ULL
252#define PSW_MASK_IO 0x0200000000000000ULL
253#define PSW_MASK_EXT 0x0100000000000000ULL
254#define PSW_MASK_KEY 0x00F0000000000000ULL
255#define PSW_SHIFT_KEY 56
256#define PSW_MASK_MCHECK 0x0004000000000000ULL
257#define PSW_MASK_WAIT 0x0002000000000000ULL
258#define PSW_MASK_PSTATE 0x0001000000000000ULL
259#define PSW_MASK_ASC 0x0000C00000000000ULL
260#define PSW_MASK_CC 0x0000300000000000ULL
261#define PSW_MASK_PM 0x00000F0000000000ULL
262#define PSW_MASK_64 0x0000000100000000ULL
263#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 264#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 265
266#undef PSW_ASC_PRIMARY
267#undef PSW_ASC_ACCREG
268#undef PSW_ASC_SECONDARY
269#undef PSW_ASC_HOME
270
271#define PSW_ASC_PRIMARY 0x0000000000000000ULL
272#define PSW_ASC_ACCREG 0x0000400000000000ULL
273#define PSW_ASC_SECONDARY 0x0000800000000000ULL
274#define PSW_ASC_HOME 0x0000C00000000000ULL
275
276/* tb flags */
277
278#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
279#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
280#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
281#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
282#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
283#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
284#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
285#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
286#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
287#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
288#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
289#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
290#define FLAG_MASK_32 0x00001000
291
c4400206 292/* Control register 0 bits */
c3edd628 293#define CR0_LOWPROT 0x0000000010000000ULL
c4400206
TH		 294#define CR0_EDAT 0x0000000000800000ULL
295
a4e3ad19 296static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 297{
bcec36ea
AG		 298 if (env->psw.mask & PSW_MASK_PSTATE) {
299 return 1;
300 }
301
10c339a0
AG		 302 return 0;
303}
304
a4e3ad19 305static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 306 target_ulong *cs_base, int *flags)
307{
308 *pc = env->psw.addr;
309 *cs_base = 0;
310 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
311 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
312}
313
d5a103cd
RH		 314/* While the PoO talks about ILC (a number between 1-3) what is actually
315 stored in LowCore is shifted left one bit (an even between 2-6). As
316 this is the actual length of the insn and therefore more useful, that
317 is what we want to pass around and manipulate. To make sure that we
318 have applied this distinction universally, rename the "ILC" to "ILEN". */
319static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 320{
321 switch (opc >> 6) {
322 case 0:
d5a103cd 323 return 2;
bcec36ea
AG		 324 case 1:
325 case 2:
d5a103cd
RH		 326 return 4;
327 default:
328 return 6;
bcec36ea 329 }
bcec36ea
AG		 330}
331
d5a103cd
RH		 332#ifndef CONFIG_USER_ONLY
333/* In several cases of runtime exceptions, we havn't recorded the true
334 instruction length. Use these codes when raising exceptions in order
335 to re-compute the length by examining the insn in memory. */
336#define ILEN_LATER 0x20
337#define ILEN_LATER_INC 0x21
dfebd7a7 338void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
d5a103cd 339#endif
bcec36ea 340
564b863d 341S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 342void s390x_translate_init(void);
10ec5117 343int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 344
345/* you can call this signal handler from your SIGBUS and SIGSEGV
346 signal handlers to inform the virtual CPU of exceptions. non zero
347 is returned if the signal was handled by the virtual CPU. */
348int cpu_s390x_signal_handler(int host_signum, void *pinfo,
349 void *puc);
7510454e
AF		 350int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
351 int mmu_idx);
10ec5117 352
db1c8f53 353#include "ioinst.h"
52705890 354
3f10341f 355
10c339a0 356#ifndef CONFIG_USER_ONLY
3f10341f
DH		 357void do_restart_interrupt(CPUS390XState *env);
358
7b18aad5
CH		 359static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
360{
361 hwaddr addr = 0;
362 uint8_t reg;
363
364 reg = ipb >> 28;
365 if (reg > 0) {
366 addr = env->regs[reg];
367 }
368 addr += (ipb >> 16) & 0xfff;
369
370 return addr;
371}
372
638129ff
CH		 373/* Base/displacement are at the same locations. */
374#define decode_basedisp_rs decode_basedisp_s
375
85ca3371
DH		 376/* helper functions for run_on_cpu() */
377static inline void s390_do_cpu_reset(void *arg)
378{
379 CPUState *cs = arg;
380 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
381
382 scc->cpu_reset(cs);
383}
384static inline void s390_do_cpu_full_reset(void *arg)
385{
386 CPUState *cs = arg;
387
388 cpu_reset(cs);
389}
390
8f22e0df
AF		 391void s390x_tod_timer(void *opaque);
392void s390x_cpu_timer(void *opaque);
393
28e942f8 394int s390_virtio_hypercall(CPUS390XState *env);
de13d216 395void s390_virtio_irq(int config_change, uint64_t token);
bcec36ea 396
1f206266 397#ifdef CONFIG_KVM
de13d216
CH		 398void kvm_s390_virtio_irq(int config_change, uint64_t token);
399void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH		 400void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
401void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 402int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
801cdd35 403void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
3f9e59bb
JH		 404int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
405int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
1f206266 406#else
de13d216 407static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
1f206266
AG		 408{
409}
de13d216 410static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH		 411{
412}
3f9e59bb
JH		 413static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
414{
415 return -ENOSYS;
416}
417static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
418{
419 return -ENOSYS;
420}
801cdd35
TH		 421static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
422 uint64_t te_code)
423{
424}
1f206266 425#endif
3f9e59bb
JH		 426
427static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
428{
429 if (kvm_enabled()) {
430 return kvm_s390_get_clock(tod_high, tod_low);
431 }
432 /* Fixme TCG */
433 *tod_high = 0;
434 *tod_low = 0;
435 return 0;
436}
437
438static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
439{
440 if (kvm_enabled()) {
441 return kvm_s390_set_clock(tod_high, tod_low);
442 }
443 /* Fixme TCG */
444 return 0;
445}
446
45fa769b 447S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH		 448unsigned int s390_cpu_halt(S390CPU *cpu);
449void s390_cpu_unhalt(S390CPU *cpu);
450unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
18ff9494
DH		 451static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
452{
453 return cpu->env.cpu_state;
454}
bcec36ea 455
3f9e59bb
JH		 456void gtod_save(QEMUFile *f, void *opaque);
457int gtod_load(QEMUFile *f, void *opaque, int version_id);
458
000a1a38
CB		 459/* service interrupts are floating therefore we must not pass an cpustate */
460void s390_sclp_extint(uint32_t parm);
461
d1ff903c 462/* from s390-virtio-bus */
a8170e5e 463extern const hwaddr virtio_size;
d1ff903c 464
ef81522b 465#else
eb24f7c6
DH		 466static inline unsigned int s390_cpu_halt(S390CPU *cpu)
467{
468 return 0;
469}
470
471static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG		 472{
473}
474
eb24f7c6 475static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG		 476{
477 return 0;
478}
10c339a0 479#endif
bcec36ea
AG		 480void cpu_lock(void);
481void cpu_unlock(void);
10c339a0 482
7b18aad5
CH		 483typedef struct SubchDev SubchDev;
484
df1fe5bb 485#ifndef CONFIG_USER_ONLY
4e872a3f 486extern void io_subsystem_reset(void);
df1fe5bb
CH		 487SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
488 uint16_t schid);
489bool css_subch_visible(SubchDev *sch);
490void css_conditional_io_interrupt(SubchDev *sch);
491int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 492bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
bffd09cd 493int css_do_msch(SubchDev *sch, const SCHIB *schib);
df1fe5bb
CH		 494int css_do_xsch(SubchDev *sch);
495int css_do_csch(SubchDev *sch);
496int css_do_hsch(SubchDev *sch);
497int css_do_ssch(SubchDev *sch, ORB *orb);
b7b6348a
TH		 498int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
499void css_do_tsch_update_subch(SubchDev *sch);
df1fe5bb 500int css_do_stcrw(CRW *crw);
7f74f0aa 501void css_undo_stcrw(CRW *crw);
50c8d9bf 502int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 503int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
504 int rfmt, void *buf);
505void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
506int css_enable_mcsse(void);
507int css_enable_mss(void);
508int css_do_rsch(SubchDev *sch);
509int css_do_rchp(uint8_t cssid, uint8_t chpid);
510bool css_present(uint8_t cssid);
df1fe5bb 511#endif
7b18aad5 512
2994fd96 513#define cpu_init(model) CPU(cpu_s390x_init(model))
10ec5117
AG		 514#define cpu_exec cpu_s390x_exec
515#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 516#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 517
904e5fd5
VM		 518void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
519#define cpu_list s390_cpu_list
520
022c62cb 521#include "exec/exec-all.h"
bcec36ea 522
bcec36ea
AG		 523#define EXCP_EXT 1 /* external interrupt */
524#define EXCP_SVC 2 /* supervisor call (syscall) */
525#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 526#define EXCP_IO 7 /* I/O interrupt */
527#define EXCP_MCHK 8 /* machine check */
bcec36ea 528
bcec36ea
AG		 529#define INTERRUPT_EXT (1 << 0)
530#define INTERRUPT_TOD (1 << 1)
531#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 532#define INTERRUPT_IO (1 << 3)
533#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 534
535/* Program Status Word. */
536#define S390_PSWM_REGNUM 0
537#define S390_PSWA_REGNUM 1
538/* General Purpose Registers. */
539#define S390_R0_REGNUM 2
540#define S390_R1_REGNUM 3
541#define S390_R2_REGNUM 4
542#define S390_R3_REGNUM 5
543#define S390_R4_REGNUM 6
544#define S390_R5_REGNUM 7
545#define S390_R6_REGNUM 8
546#define S390_R7_REGNUM 9
547#define S390_R8_REGNUM 10
548#define S390_R9_REGNUM 11
549#define S390_R10_REGNUM 12
550#define S390_R11_REGNUM 13
551#define S390_R12_REGNUM 14
552#define S390_R13_REGNUM 15
553#define S390_R14_REGNUM 16
554#define S390_R15_REGNUM 17
73d510c9
DH		 555/* Total Core Registers. */
556#define S390_NUM_CORE_REGS 18
10c339a0 557
bcec36ea
AG		 558/* CC optimization */
559
560enum cc_op {
561 CC_OP_CONST0 = 0, /* CC is 0 */
562 CC_OP_CONST1, /* CC is 1 */
563 CC_OP_CONST2, /* CC is 2 */
564 CC_OP_CONST3, /* CC is 3 */
565
566 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
567 CC_OP_STATIC, /* CC value is env->cc_op */
568
569 CC_OP_NZ, /* env->cc_dst != 0 */
570 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
571 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
572 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
573 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
574 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
575 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
576
577 CC_OP_ADD_64, /* overflow on add (64bit) */
578 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 579 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 580 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
581 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 582 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 583 CC_OP_ABS_64, /* sign eval on abs (64bit) */
584 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
585
586 CC_OP_ADD_32, /* overflow on add (32bit) */
587 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 588 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 589 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
590 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 591 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 592 CC_OP_ABS_32, /* sign eval on abs (64bit) */
593 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
594
595 CC_OP_COMP_32, /* complement */
596 CC_OP_COMP_64, /* complement */
597
598 CC_OP_TM_32, /* test under mask (32bit) */
599 CC_OP_TM_64, /* test under mask (64bit) */
600
bcec36ea
AG		 601 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
602 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 603 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 604
605 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 606 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
607 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 608 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 609 CC_OP_MAX
610};
611
612static const char *cc_names[] = {
613 [CC_OP_CONST0] = "CC_OP_CONST0",
614 [CC_OP_CONST1] = "CC_OP_CONST1",
615 [CC_OP_CONST2] = "CC_OP_CONST2",
616 [CC_OP_CONST3] = "CC_OP_CONST3",
617 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
618 [CC_OP_STATIC] = "CC_OP_STATIC",
619 [CC_OP_NZ] = "CC_OP_NZ",
620 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
621 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
622 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
623 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
624 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
625 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
626 [CC_OP_ADD_64] = "CC_OP_ADD_64",
627 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 628 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 629 [CC_OP_SUB_64] = "CC_OP_SUB_64",
630 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 631 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 632 [CC_OP_ABS_64] = "CC_OP_ABS_64",
633 [CC_OP_NABS_64] = "CC_OP_NABS_64",
634 [CC_OP_ADD_32] = "CC_OP_ADD_32",
635 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 636 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 637 [CC_OP_SUB_32] = "CC_OP_SUB_32",
638 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 639 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 640 [CC_OP_ABS_32] = "CC_OP_ABS_32",
641 [CC_OP_NABS_32] = "CC_OP_NABS_32",
642 [CC_OP_COMP_32] = "CC_OP_COMP_32",
643 [CC_OP_COMP_64] = "CC_OP_COMP_64",
644 [CC_OP_TM_32] = "CC_OP_TM_32",
645 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 646 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
647 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 648 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 649 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 650 [CC_OP_SLA_32] = "CC_OP_SLA_32",
651 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 652 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 653};
654
655static inline const char *cc_name(int cc_op)
656{
657 return cc_names[cc_op];
658}
659
3d0a615f
TH		 660static inline void setcc(S390CPU *cpu, uint64_t cc)
661{
662 CPUS390XState *env = &cpu->env;
663
664 env->psw.mask &= ~(3ull << 44);
665 env->psw.mask |= (cc & 3) << 44;
666}
667
bcec36ea
AG		 668typedef struct LowCore
669{
670 /* prefix area: defined by architecture */
671 uint32_t ccw1[2]; /* 0x000 */
672 uint32_t ccw2[4]; /* 0x008 */
673 uint8_t pad1[0x80-0x18]; /* 0x018 */
674 uint32_t ext_params; /* 0x080 */
675 uint16_t cpu_addr; /* 0x084 */
676 uint16_t ext_int_code; /* 0x086 */
d5a103cd 677 uint16_t svc_ilen; /* 0x088 */
bcec36ea 678 uint16_t svc_code; /* 0x08a */
d5a103cd 679 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 680 uint16_t pgm_code; /* 0x08e */
681 uint32_t data_exc_code; /* 0x090 */
682 uint16_t mon_class_num; /* 0x094 */
683 uint16_t per_perc_atmid; /* 0x096 */
684 uint64_t per_address; /* 0x098 */
685 uint8_t exc_access_id; /* 0x0a0 */
686 uint8_t per_access_id; /* 0x0a1 */
687 uint8_t op_access_id; /* 0x0a2 */
688 uint8_t ar_access_id; /* 0x0a3 */
689 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
690 uint64_t trans_exc_code; /* 0x0a8 */
691 uint64_t monitor_code; /* 0x0b0 */
692 uint16_t subchannel_id; /* 0x0b8 */
693 uint16_t subchannel_nr; /* 0x0ba */
694 uint32_t io_int_parm; /* 0x0bc */
695 uint32_t io_int_word; /* 0x0c0 */
696 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
697 uint32_t stfl_fac_list; /* 0x0c8 */
698 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
699 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
700 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
701 uint32_t external_damage_code; /* 0x0f4 */
702 uint64_t failing_storage_address; /* 0x0f8 */
703 uint8_t pad6[0x120-0x100]; /* 0x100 */
704 PSW restart_old_psw; /* 0x120 */
705 PSW external_old_psw; /* 0x130 */
706 PSW svc_old_psw; /* 0x140 */
707 PSW program_old_psw; /* 0x150 */
708 PSW mcck_old_psw; /* 0x160 */
709 PSW io_old_psw; /* 0x170 */
710 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
3f10341f 711 PSW restart_new_psw; /* 0x1a0 */
bcec36ea
AG		 712 PSW external_new_psw; /* 0x1b0 */
713 PSW svc_new_psw; /* 0x1c0 */
714 PSW program_new_psw; /* 0x1d0 */
715 PSW mcck_new_psw; /* 0x1e0 */
716 PSW io_new_psw; /* 0x1f0 */
717 PSW return_psw; /* 0x200 */
718 uint8_t irb[64]; /* 0x210 */
719 uint64_t sync_enter_timer; /* 0x250 */
720 uint64_t async_enter_timer; /* 0x258 */
721 uint64_t exit_timer; /* 0x260 */
722 uint64_t last_update_timer; /* 0x268 */
723 uint64_t user_timer; /* 0x270 */
724 uint64_t system_timer; /* 0x278 */
725 uint64_t last_update_clock; /* 0x280 */
726 uint64_t steal_clock; /* 0x288 */
727 PSW return_mcck_psw; /* 0x290 */
728 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
729 /* System info area */
730 uint64_t save_area[16]; /* 0xc00 */
731 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
732 uint64_t kernel_stack; /* 0xd40 */
733 uint64_t thread_info; /* 0xd48 */
734 uint64_t async_stack; /* 0xd50 */
735 uint64_t kernel_asce; /* 0xd58 */
736 uint64_t user_asce; /* 0xd60 */
737 uint64_t panic_stack; /* 0xd68 */
738 uint64_t user_exec_asce; /* 0xd70 */
739 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
740
741 /* SMP info area: defined by DJB */
742 uint64_t clock_comparator; /* 0xdc0 */
743 uint64_t ext_call_fast; /* 0xdc8 */
744 uint64_t percpu_offset; /* 0xdd0 */
745 uint64_t current_task; /* 0xdd8 */
746 uint32_t softirq_pending; /* 0xde0 */
747 uint32_t pad_0x0de4; /* 0xde4 */
748 uint64_t int_clock; /* 0xde8 */
749 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
750
751 /* 0xe00 is used as indicator for dump tools */
752 /* whether the kernel died with panic() or not */
753 uint32_t panic_magic; /* 0xe00 */
754
755 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
756
757 /* 64 bit extparam used for pfault, diag 250 etc */
758 uint64_t ext_params2; /* 0x11B8 */
759
760 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
761
762 /* System info area */
763
764 uint64_t floating_pt_save_area[16]; /* 0x1200 */
765 uint64_t gpregs_save_area[16]; /* 0x1280 */
766 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
767 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
768 uint32_t prefixreg_save_area; /* 0x1318 */
769 uint32_t fpt_creg_save_area; /* 0x131c */
770 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
771 uint32_t tod_progreg_save_area; /* 0x1324 */
772 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
773 uint32_t clock_comp_save_area[2]; /* 0x1330 */
774 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
775 uint32_t access_regs_save_area[16]; /* 0x1340 */
776 uint64_t cregs_save_area[16]; /* 0x1380 */
777
778 /* align to the top of the prefix area */
779
780 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 781} QEMU_PACKED LowCore;
bcec36ea
AG		 782
783/* STSI */
784#define STSI_LEVEL_MASK 0x00000000f0000000ULL
785#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
786#define STSI_LEVEL_1 0x0000000010000000ULL
787#define STSI_LEVEL_2 0x0000000020000000ULL
788#define STSI_LEVEL_3 0x0000000030000000ULL
789#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
790#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
791#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
792#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
793
794/* Basic Machine Configuration */
795struct sysib_111 {
796 uint32_t res1[8];
797 uint8_t manuf[16];
798 uint8_t type[4];
799 uint8_t res2[12];
800 uint8_t model[16];
801 uint8_t sequence[16];
802 uint8_t plant[4];
803 uint8_t res3[156];
804};
805
806/* Basic Machine CPU */
807struct sysib_121 {
808 uint32_t res1[80];
809 uint8_t sequence[16];
810 uint8_t plant[4];
811 uint8_t res2[2];
812 uint16_t cpu_addr;
813 uint8_t res3[152];
814};
815
816/* Basic Machine CPUs */
817struct sysib_122 {
818 uint8_t res1[32];
819 uint32_t capability;
820 uint16_t total_cpus;
821 uint16_t active_cpus;
822 uint16_t standby_cpus;
823 uint16_t reserved_cpus;
824 uint16_t adjustments[2026];
825};
826
827/* LPAR CPU */
828struct sysib_221 {
829 uint32_t res1[80];
830 uint8_t sequence[16];
831 uint8_t plant[4];
832 uint16_t cpu_id;
833 uint16_t cpu_addr;
834 uint8_t res3[152];
835};
836
837/* LPAR CPUs */
838struct sysib_222 {
839 uint32_t res1[32];
840 uint16_t lpar_num;
841 uint8_t res2;
842 uint8_t lcpuc;
843 uint16_t total_cpus;
844 uint16_t conf_cpus;
845 uint16_t standby_cpus;
846 uint16_t reserved_cpus;
847 uint8_t name[8];
848 uint32_t caf;
849 uint8_t res3[16];
850 uint16_t dedicated_cpus;
851 uint16_t shared_cpus;
852 uint8_t res4[180];
853};
854
855/* VM CPUs */
856struct sysib_322 {
857 uint8_t res1[31];
858 uint8_t count;
859 struct {
860 uint8_t res2[4];
861 uint16_t total_cpus;
862 uint16_t conf_cpus;
863 uint16_t standby_cpus;
864 uint16_t reserved_cpus;
865 uint8_t name[8];
866 uint32_t caf;
867 uint8_t cpi[16];
f07177a5
ET		 868 uint8_t res5[3];
869 uint8_t ext_name_encoding;
870 uint32_t res3;
871 uint8_t uuid[16];
bcec36ea 872 } vm[8];
f07177a5
ET		 873 uint8_t res4[1504];
874 uint8_t ext_names[8][256];
bcec36ea
AG		 875};
876
877/* MMU defines */
878#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
879#define _ASCE_SUBSPACE 0x200 /* subspace group control */
880#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
881#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
882#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
883#define _ASCE_REAL_SPACE 0x20 /* real space control */
884#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
885#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
886#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
887#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
888#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
889#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
890
891#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
43d49b01 892#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
5d180439 893#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
bcec36ea
AG		 894#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
895#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
896#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
897#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
898#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
899#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
900
901#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 902#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG		 903#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
904#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
905
906#define _PAGE_RO 0x200 /* HW read-only bit */
907#define _PAGE_INVALID 0x400 /* HW invalid bit */
b4ecbf80 908#define _PAGE_RES0 0x800 /* bit must be zero */
bcec36ea 909
b9959138
AG		 910#define SK_C (0x1 << 1)
911#define SK_R (0x1 << 2)
912#define SK_F (0x1 << 3)
913#define SK_ACC_MASK (0xf << 4)
bcec36ea 914
5172b780 915/* SIGP order codes */
bcec36ea
AG		 916#define SIGP_SENSE 0x01
917#define SIGP_EXTERNAL_CALL 0x02
918#define SIGP_EMERGENCY 0x03
919#define SIGP_START 0x04
920#define SIGP_STOP 0x05
921#define SIGP_RESTART 0x06
922#define SIGP_STOP_STORE_STATUS 0x09
923#define SIGP_INITIAL_CPU_RESET 0x0b
924#define SIGP_CPU_RESET 0x0c
925#define SIGP_SET_PREFIX 0x0d
926#define SIGP_STORE_STATUS_ADDR 0x0e
927#define SIGP_SET_ARCH 0x12
928
5172b780
DH		 929/* SIGP condition codes */
930#define SIGP_CC_ORDER_CODE_ACCEPTED 0
931#define SIGP_CC_STATUS_STORED 1
932#define SIGP_CC_BUSY 2
933#define SIGP_CC_NOT_OPERATIONAL 3
934
935/* SIGP status bits */
bcec36ea
AG		 936#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
937#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
938#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
939#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
940#define SIGP_STAT_STOPPED 0x00000040UL
941#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
942#define SIGP_STAT_CHECK_STOP 0x00000010UL
943#define SIGP_STAT_INOPERATIVE 0x00000004UL
944#define SIGP_STAT_INVALID_ORDER 0x00000002UL
945#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
946
18ff9494
DH		 947/* SIGP SET ARCHITECTURE modes */
948#define SIGP_MODE_ESA_S390 0
949#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
950#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
951
a4e3ad19
AF		 952void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
953int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
e3e09d87 954 target_ulong *raddr, int *flags, bool exc);
6e252802 955int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 956uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 957 uint64_t vr);
958
c3edd628
TH		 959int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, void *hostbuf, int len,
960 bool is_write);
961
962#define s390_cpu_virt_mem_read(cpu, laddr, dest, len) \
963 s390_cpu_virt_mem_rw(cpu, laddr, dest, len, false)
964#define s390_cpu_virt_mem_write(cpu, laddr, dest, len) \
965 s390_cpu_virt_mem_rw(cpu, laddr, dest, len, true)
966#define s390_cpu_virt_mem_check_write(cpu, laddr, len) \
967 s390_cpu_virt_mem_rw(cpu, laddr, NULL, len, true)
968
bcec36ea
AG		 969/* The value of the TOD clock for 1.1.1970. */
970#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
971
972/* Converts ns to s390's clock format */
973static inline uint64_t time2tod(uint64_t ns) {
974 return (ns << 9) / 125;
975}
976
f9466733 977static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 978 uint64_t param64)
979{
f9466733
AF		 980 CPUS390XState *env = &cpu->env;
981
bcec36ea
AG		 982 if (env->ext_index == MAX_EXT_QUEUE - 1) {
983 /* ugh - can't queue anymore. Let's drop. */
984 return;
985 }
986
987 env->ext_index++;
988 assert(env->ext_index < MAX_EXT_QUEUE);
989
990 env->ext_queue[env->ext_index].code = code;
991 env->ext_queue[env->ext_index].param = param;
992 env->ext_queue[env->ext_index].param64 = param64;
993
994 env->pending_int |= INTERRUPT_EXT;
c3affe56 995 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 996}
10c339a0 997
f9466733 998static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 999 uint16_t subchannel_number,
1000 uint32_t io_int_parm, uint32_t io_int_word)
1001{
f9466733 1002 CPUS390XState *env = &cpu->env;
91b0a8f3 1003 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1004
1005 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1006 /* ugh - can't queue anymore. Let's drop. */
1007 return;
1008 }
1009
1010 env->io_index[isc]++;
1011 assert(env->io_index[isc] < MAX_IO_QUEUE);
1012
1013 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1014 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1015 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1016 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1017
1018 env->pending_int |= INTERRUPT_IO;
c3affe56 1019 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1020}
1021
f9466733 1022static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1023{
f9466733
AF		 1024 CPUS390XState *env = &cpu->env;
1025
5d69c547
CH		 1026 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1027 /* ugh - can't queue anymore. Let's drop. */
1028 return;
1029 }
1030
1031 env->mchk_index++;
1032 assert(env->mchk_index < MAX_MCHK_QUEUE);
1033
1034 env->mchk_queue[env->mchk_index].type = 1;
1035
1036 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1037 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1038}
1039
b6fe0124
MR		 1040/* from s390-virtio-ccw */
1041#define MEM_SECTION_SIZE 0x10000000UL
1def6656 1042#define MAX_AVAIL_SLOTS 32
b6fe0124 1043
e72ca652 1044/* fpu_helper.c */
e72ca652
BS		 1045uint32_t set_cc_nz_f32(float32 v);
1046uint32_t set_cc_nz_f64(float64 v);
587626f8 1047uint32_t set_cc_nz_f128(float128 v);
e72ca652 1048
aea1e885 1049/* misc_helper.c */
268846ba
ED		 1050#ifndef CONFIG_USER_ONLY
1051void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1052#endif
d5a103cd 1053void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1054void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1055 uintptr_t retaddr);
a78b0504 1056
09b99878 1057#ifdef CONFIG_KVM
de13d216 1058void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH		 1059 uint16_t subchannel_nr, uint32_t io_int_parm,
1060 uint32_t io_int_word);
de13d216 1061void kvm_s390_crw_mchk(void);
09b99878 1062void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1063int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1064 int vq, bool assign);
7f7f9752 1065int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 1066int kvm_s390_get_memslot_count(KVMState *s);
4cb88c3c 1067void kvm_s390_clear_cmma_callback(void *opaque);
c9e659c9 1068int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
99607144 1069void kvm_s390_reset_vcpu(S390CPU *cpu);
a310b283 1070int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
09b99878 1071#else
de13d216 1072static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH		 1073 uint16_t subchannel_nr,
1074 uint32_t io_int_parm,
1075 uint32_t io_int_word)
1076{
1077}
de13d216 1078static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH		 1079{
1080}
09b99878
CH		 1081static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1082{
1083}
cc3ac9c4
CH		 1084static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1085 uint32_t sch, int vq,
b4436a0b
CH		 1086 bool assign)
1087{
1088 return -ENOSYS;
1089}
7f7f9752
ED		 1090static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1091{
1092 return -ENOSYS;
1093}
4cb88c3c
DD		 1094static inline void kvm_s390_clear_cmma_callback(void *opaque)
1095{
1096}
1def6656
MR		 1097static inline int kvm_s390_get_memslot_count(KVMState *s)
1098{
1099 return MAX_AVAIL_SLOTS;
1100}
c9e659c9
DH		 1101static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1102{
1103 return -ENOSYS;
1104}
99607144
DH		 1105static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1106{
1107}
a310b283
DD		 1108static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1109 uint64_t *hw_limit)
1110{
1111 return 0;
1112}
09b99878 1113#endif
df1fe5bb 1114
a310b283
DD		 1115static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1116{
1117 if (kvm_enabled()) {
1118 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1119 }
1120 return 0;
1121}
1122
4cb88c3c
DD		 1123static inline void cmma_reset(S390CPU *cpu)
1124{
1125 if (kvm_enabled()) {
1126 CPUState *cs = CPU(cpu);
1127 kvm_s390_clear_cmma_callback(cs->kvm_state);
1128 }
1129}
1130
7f7f9752
ED		 1131static inline int s390_cpu_restart(S390CPU *cpu)
1132{
1133 if (kvm_enabled()) {
1134 return kvm_s390_cpu_restart(cpu);
1135 }
1136 return -ENOSYS;
1137}
1138
1def6656
MR		 1139static inline int s390_get_memslot_count(KVMState *s)
1140{
1141 if (kvm_enabled()) {
1142 return kvm_s390_get_memslot_count(s);
1143 } else {
1144 return MAX_AVAIL_SLOTS;
1145 }
1146}
1147
de13d216
CH		 1148void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1149 uint32_t io_int_parm, uint32_t io_int_word);
1150void s390_crw_mchk(void);
df1fe5bb 1151
cc3ac9c4
CH		 1152static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1153 uint32_t sch_id, int vq,
b4436a0b
CH		 1154 bool assign)
1155{
1156 if (kvm_enabled()) {
cc3ac9c4 1157 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1158 } else {
1159 return -ENOSYS;
1160 }
1161}
1162
10ec5117 1163#endif
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