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CommitLineData
10ec5117
AG
1/*
2 * S/390 helpers
3 *
4 * Copyright (c) 2009 Ulrich Hecht
d5a43964 5 * Copyright (c) 2011 Alexander Graf
10ec5117
AG
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
70539e18 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG
19 */
20
10ec5117 21#include "cpu.h"
022c62cb 22#include "exec/gdbstub.h"
1de7afc9 23#include "qemu/timer.h"
f08b6170 24#include "exec/cpu_ldst.h"
ef81522b 25#ifndef CONFIG_USER_ONLY
9c17d615 26#include "sysemu/sysemu.h"
ef81522b 27#endif
10ec5117 28
d5a43964 29//#define DEBUG_S390
d5a43964
AG
30//#define DEBUG_S390_STDOUT
31
32#ifdef DEBUG_S390
33#ifdef DEBUG_S390_STDOUT
34#define DPRINTF(fmt, ...) \
35 do { fprintf(stderr, fmt, ## __VA_ARGS__); \
36 qemu_log(fmt, ##__VA_ARGS__); } while (0)
37#else
38#define DPRINTF(fmt, ...) \
39 do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
40#endif
41#else
42#define DPRINTF(fmt, ...) \
43 do { } while (0)
44#endif
45
d5a43964
AG
46
47#ifndef CONFIG_USER_ONLY
8f22e0df 48void s390x_tod_timer(void *opaque)
d5a43964 49{
b8ba6799
AF
50 S390CPU *cpu = opaque;
51 CPUS390XState *env = &cpu->env;
d5a43964
AG
52
53 env->pending_int |= INTERRUPT_TOD;
c3affe56 54 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
d5a43964
AG
55}
56
8f22e0df 57void s390x_cpu_timer(void *opaque)
d5a43964 58{
b8ba6799
AF
59 S390CPU *cpu = opaque;
60 CPUS390XState *env = &cpu->env;
d5a43964
AG
61
62 env->pending_int |= INTERRUPT_CPUTIMER;
c3affe56 63 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
d5a43964
AG
64}
65#endif
10c339a0 66
564b863d 67S390CPU *cpu_s390x_init(const char *cpu_model)
10ec5117 68{
29e4bcb2 69 S390CPU *cpu;
10ec5117 70
29e4bcb2 71 cpu = S390_CPU(object_new(TYPE_S390_CPU));
1f136632
AF
72
73 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
74
564b863d 75 return cpu;
10ec5117
AG
76}
77
d5a43964
AG
78#if defined(CONFIG_USER_ONLY)
79
97a8ea5a 80void s390_cpu_do_interrupt(CPUState *cs)
d5a43964 81{
27103424 82 cs->exception_index = -1;
d5a43964
AG
83}
84
7510454e
AF
85int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
86 int rw, int mmu_idx)
d5a43964 87{
7510454e
AF
88 S390CPU *cpu = S390_CPU(cs);
89
27103424 90 cs->exception_index = EXCP_PGM;
7510454e 91 cpu->env.int_pgm_code = PGM_ADDRESSING;
d5a103cd
RH
92 /* On real machines this value is dropped into LowMem. Since this
93 is userland, simply put this someplace that cpu_loop can find it. */
7510454e 94 cpu->env.__excp_addr = address;
d5a43964
AG
95 return 1;
96}
97
b7e516ce 98#else /* !CONFIG_USER_ONLY */
d5a43964
AG
99
100/* Ensure to exit the TB after this call! */
dfebd7a7 101void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen)
d5a43964 102{
27103424
AF
103 CPUState *cs = CPU(s390_env_get_cpu(env));
104
105 cs->exception_index = EXCP_PGM;
d5a43964 106 env->int_pgm_code = code;
d5a103cd 107 env->int_pgm_ilen = ilen;
d5a43964
AG
108}
109
7510454e
AF
110int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
111 int rw, int mmu_idx)
10c339a0 112{
7510454e
AF
113 S390CPU *cpu = S390_CPU(cs);
114 CPUS390XState *env = &cpu->env;
d5a43964
AG
115 uint64_t asc = env->psw.mask & PSW_MASK_ASC;
116 target_ulong vaddr, raddr;
10c339a0
AG
117 int prot;
118
7510454e 119 DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
07cc7d12 120 __func__, orig_vaddr, rw, mmu_idx);
d5a43964 121
71e47088
BS
122 orig_vaddr &= TARGET_PAGE_MASK;
123 vaddr = orig_vaddr;
d5a43964
AG
124
125 /* 31-Bit mode */
126 if (!(env->psw.mask & PSW_MASK_64)) {
127 vaddr &= 0x7fffffff;
128 }
129
e3e09d87 130 if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) {
d5a43964
AG
131 /* Translation ended in exception */
132 return 1;
133 }
10c339a0 134
d5a43964
AG
135 /* check out of RAM access */
136 if (raddr > (ram_size + virtio_size)) {
a6f921b0
AF
137 DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
138 (uint64_t)raddr, (uint64_t)ram_size);
d5a103cd 139 trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);
d5a43964
AG
140 return 1;
141 }
10c339a0 142
339aaf5b
AP
143 qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
144 __func__, (uint64_t)vaddr, (uint64_t)raddr, prot);
d5a43964 145
0c591eb0 146 tlb_set_page(cs, orig_vaddr, raddr, prot,
d4c430a8 147 mmu_idx, TARGET_PAGE_SIZE);
d5a43964 148
d4c430a8 149 return 0;
10c339a0 150}
d5a43964 151
00b941e5 152hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
d5a43964 153{
00b941e5
AF
154 S390CPU *cpu = S390_CPU(cs);
155 CPUS390XState *env = &cpu->env;
d5a43964 156 target_ulong raddr;
e3e09d87 157 int prot;
d5a43964
AG
158 uint64_t asc = env->psw.mask & PSW_MASK_ASC;
159
160 /* 31-Bit mode */
161 if (!(env->psw.mask & PSW_MASK_64)) {
162 vaddr &= 0x7fffffff;
163 }
164
e3e09d87 165 mmu_translate(env, vaddr, 2, asc, &raddr, &prot, false);
d5a43964
AG
166
167 return raddr;
168}
169
770a6379
DH
170hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
171{
172 hwaddr phys_addr;
173 target_ulong page;
174
175 page = vaddr & TARGET_PAGE_MASK;
176 phys_addr = cpu_get_phys_page_debug(cs, page);
177 phys_addr += (vaddr & ~TARGET_PAGE_MASK);
178
179 return phys_addr;
180}
181
a4e3ad19 182void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
d5a43964 183{
eb24f7c6
DH
184 env->psw.addr = addr;
185 env->psw.mask = mask;
186 env->cc_op = (mask >> 44) & 3;
187
d5a43964 188 if (mask & PSW_MASK_WAIT) {
49e15878 189 S390CPU *cpu = s390_env_get_cpu(env);
eb24f7c6 190 if (s390_cpu_halt(cpu) == 0) {
ef81522b 191#ifndef CONFIG_USER_ONLY
eb24f7c6 192 qemu_system_shutdown_request();
ef81522b 193#endif
d5a43964
AG
194 }
195 }
d5a43964
AG
196}
197
a4e3ad19 198static uint64_t get_psw_mask(CPUS390XState *env)
d5a43964 199{
51855ecf 200 uint64_t r;
d5a43964
AG
201
202 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
203
51855ecf
RH
204 r = env->psw.mask;
205 r &= ~PSW_MASK_CC;
d5a43964 206 assert(!(env->cc_op & ~3));
51855ecf 207 r |= (uint64_t)env->cc_op << 44;
d5a43964
AG
208
209 return r;
210}
211
4782a23b
CH
212static LowCore *cpu_map_lowcore(CPUS390XState *env)
213{
a47dddd7 214 S390CPU *cpu = s390_env_get_cpu(env);
4782a23b
CH
215 LowCore *lowcore;
216 hwaddr len = sizeof(LowCore);
217
218 lowcore = cpu_physical_memory_map(env->psa, &len, 1);
219
220 if (len < sizeof(LowCore)) {
a47dddd7 221 cpu_abort(CPU(cpu), "Could not map lowcore\n");
4782a23b
CH
222 }
223
224 return lowcore;
225}
226
227static void cpu_unmap_lowcore(LowCore *lowcore)
228{
229 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
230}
231
a4e3ad19 232static void do_svc_interrupt(CPUS390XState *env)
d5a43964
AG
233{
234 uint64_t mask, addr;
235 LowCore *lowcore;
d5a43964 236
4782a23b 237 lowcore = cpu_map_lowcore(env);
d5a43964
AG
238
239 lowcore->svc_code = cpu_to_be16(env->int_svc_code);
d5a103cd 240 lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
d5a43964 241 lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
d5a103cd 242 lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
d5a43964
AG
243 mask = be64_to_cpu(lowcore->svc_new_psw.mask);
244 addr = be64_to_cpu(lowcore->svc_new_psw.addr);
245
4782a23b 246 cpu_unmap_lowcore(lowcore);
d5a43964
AG
247
248 load_psw(env, mask, addr);
249}
250
a4e3ad19 251static void do_program_interrupt(CPUS390XState *env)
d5a43964
AG
252{
253 uint64_t mask, addr;
254 LowCore *lowcore;
d5a103cd 255 int ilen = env->int_pgm_ilen;
d5a43964 256
d5a103cd
RH
257 switch (ilen) {
258 case ILEN_LATER:
259 ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
d5a43964 260 break;
d5a103cd
RH
261 case ILEN_LATER_INC:
262 ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
263 env->psw.addr += ilen;
d5a43964 264 break;
d5a103cd
RH
265 default:
266 assert(ilen == 2 || ilen == 4 || ilen == 6);
d5a43964
AG
267 }
268
d5a103cd
RH
269 qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
270 __func__, env->int_pgm_code, ilen);
d5a43964 271
4782a23b 272 lowcore = cpu_map_lowcore(env);
d5a43964 273
d5a103cd 274 lowcore->pgm_ilen = cpu_to_be16(ilen);
d5a43964
AG
275 lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
276 lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
277 lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
278 mask = be64_to_cpu(lowcore->program_new_psw.mask);
279 addr = be64_to_cpu(lowcore->program_new_psw.addr);
280
4782a23b 281 cpu_unmap_lowcore(lowcore);
d5a43964 282
71e47088 283 DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
d5a103cd 284 env->int_pgm_code, ilen, env->psw.mask,
d5a43964
AG
285 env->psw.addr);
286
287 load_psw(env, mask, addr);
288}
289
290#define VIRTIO_SUBCODE_64 0x0D00
291
a4e3ad19 292static void do_ext_interrupt(CPUS390XState *env)
d5a43964 293{
a47dddd7 294 S390CPU *cpu = s390_env_get_cpu(env);
d5a43964
AG
295 uint64_t mask, addr;
296 LowCore *lowcore;
d5a43964
AG
297 ExtQueue *q;
298
299 if (!(env->psw.mask & PSW_MASK_EXT)) {
a47dddd7 300 cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
d5a43964
AG
301 }
302
1a719923 303 if (env->ext_index < 0 || env->ext_index >= MAX_EXT_QUEUE) {
a47dddd7 304 cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index);
d5a43964
AG
305 }
306
307 q = &env->ext_queue[env->ext_index];
4782a23b 308 lowcore = cpu_map_lowcore(env);
d5a43964
AG
309
310 lowcore->ext_int_code = cpu_to_be16(q->code);
311 lowcore->ext_params = cpu_to_be32(q->param);
312 lowcore->ext_params2 = cpu_to_be64(q->param64);
313 lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
314 lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
315 lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
316 mask = be64_to_cpu(lowcore->external_new_psw.mask);
317 addr = be64_to_cpu(lowcore->external_new_psw.addr);
318
4782a23b 319 cpu_unmap_lowcore(lowcore);
d5a43964
AG
320
321 env->ext_index--;
322 if (env->ext_index == -1) {
323 env->pending_int &= ~INTERRUPT_EXT;
324 }
325
71e47088 326 DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
d5a43964
AG
327 env->psw.mask, env->psw.addr);
328
329 load_psw(env, mask, addr);
330}
3110e292 331
5d69c547
CH
332static void do_io_interrupt(CPUS390XState *env)
333{
a47dddd7 334 S390CPU *cpu = s390_env_get_cpu(env);
5d69c547
CH
335 LowCore *lowcore;
336 IOIntQueue *q;
337 uint8_t isc;
338 int disable = 1;
339 int found = 0;
340
341 if (!(env->psw.mask & PSW_MASK_IO)) {
a47dddd7 342 cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
5d69c547
CH
343 }
344
345 for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
91b0a8f3
CH
346 uint64_t isc_bits;
347
5d69c547
CH
348 if (env->io_index[isc] < 0) {
349 continue;
350 }
1a719923 351 if (env->io_index[isc] >= MAX_IO_QUEUE) {
a47dddd7 352 cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
5d69c547
CH
353 isc, env->io_index[isc]);
354 }
355
356 q = &env->io_queue[env->io_index[isc]][isc];
91b0a8f3
CH
357 isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
358 if (!(env->cregs[6] & isc_bits)) {
5d69c547
CH
359 disable = 0;
360 continue;
361 }
bd9a8d85
CH
362 if (!found) {
363 uint64_t mask, addr;
5d69c547 364
bd9a8d85
CH
365 found = 1;
366 lowcore = cpu_map_lowcore(env);
5d69c547 367
bd9a8d85
CH
368 lowcore->subchannel_id = cpu_to_be16(q->id);
369 lowcore->subchannel_nr = cpu_to_be16(q->nr);
370 lowcore->io_int_parm = cpu_to_be32(q->parm);
371 lowcore->io_int_word = cpu_to_be32(q->word);
372 lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
373 lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
374 mask = be64_to_cpu(lowcore->io_new_psw.mask);
375 addr = be64_to_cpu(lowcore->io_new_psw.addr);
5d69c547 376
bd9a8d85
CH
377 cpu_unmap_lowcore(lowcore);
378
379 env->io_index[isc]--;
380
381 DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
382 env->psw.mask, env->psw.addr);
383 load_psw(env, mask, addr);
384 }
b22dd124 385 if (env->io_index[isc] >= 0) {
5d69c547
CH
386 disable = 0;
387 }
bd9a8d85 388 continue;
5d69c547
CH
389 }
390
391 if (disable) {
392 env->pending_int &= ~INTERRUPT_IO;
393 }
394
5d69c547
CH
395}
396
397static void do_mchk_interrupt(CPUS390XState *env)
398{
a47dddd7 399 S390CPU *cpu = s390_env_get_cpu(env);
5d69c547
CH
400 uint64_t mask, addr;
401 LowCore *lowcore;
402 MchkQueue *q;
403 int i;
404
405 if (!(env->psw.mask & PSW_MASK_MCHECK)) {
a47dddd7 406 cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
5d69c547
CH
407 }
408
1a719923 409 if (env->mchk_index < 0 || env->mchk_index >= MAX_MCHK_QUEUE) {
a47dddd7 410 cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
5d69c547
CH
411 }
412
413 q = &env->mchk_queue[env->mchk_index];
414
415 if (q->type != 1) {
416 /* Don't know how to handle this... */
a47dddd7 417 cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
5d69c547
CH
418 }
419 if (!(env->cregs[14] & (1 << 28))) {
420 /* CRW machine checks disabled */
421 return;
422 }
423
424 lowcore = cpu_map_lowcore(env);
425
426 for (i = 0; i < 16; i++) {
427 lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll);
428 lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
429 lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
430 lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
431 }
432 lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
433 lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
434 lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
435 lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
436 lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
437 lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
438 lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
439
440 lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
441 lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
442 lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
443 lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
444 mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
445 addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
446
447 cpu_unmap_lowcore(lowcore);
448
449 env->mchk_index--;
450 if (env->mchk_index == -1) {
451 env->pending_int &= ~INTERRUPT_MCHK;
452 }
453
454 DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
455 env->psw.mask, env->psw.addr);
456
457 load_psw(env, mask, addr);
458}
459
97a8ea5a 460void s390_cpu_do_interrupt(CPUState *cs)
3110e292 461{
97a8ea5a
AF
462 S390CPU *cpu = S390_CPU(cs);
463 CPUS390XState *env = &cpu->env;
f9466733 464
0d404541 465 qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
27103424 466 __func__, cs->exception_index, env->psw.addr);
d5a43964 467
eb24f7c6 468 s390_cpu_set_state(CPU_STATE_OPERATING, cpu);
5d69c547
CH
469 /* handle machine checks */
470 if ((env->psw.mask & PSW_MASK_MCHECK) &&
27103424 471 (cs->exception_index == -1)) {
5d69c547 472 if (env->pending_int & INTERRUPT_MCHK) {
27103424 473 cs->exception_index = EXCP_MCHK;
5d69c547
CH
474 }
475 }
d5a43964
AG
476 /* handle external interrupts */
477 if ((env->psw.mask & PSW_MASK_EXT) &&
27103424 478 cs->exception_index == -1) {
d5a43964
AG
479 if (env->pending_int & INTERRUPT_EXT) {
480 /* code is already in env */
27103424 481 cs->exception_index = EXCP_EXT;
d5a43964 482 } else if (env->pending_int & INTERRUPT_TOD) {
f9466733 483 cpu_inject_ext(cpu, 0x1004, 0, 0);
27103424 484 cs->exception_index = EXCP_EXT;
d5a43964
AG
485 env->pending_int &= ~INTERRUPT_EXT;
486 env->pending_int &= ~INTERRUPT_TOD;
487 } else if (env->pending_int & INTERRUPT_CPUTIMER) {
f9466733 488 cpu_inject_ext(cpu, 0x1005, 0, 0);
27103424 489 cs->exception_index = EXCP_EXT;
d5a43964
AG
490 env->pending_int &= ~INTERRUPT_EXT;
491 env->pending_int &= ~INTERRUPT_TOD;
492 }
493 }
5d69c547
CH
494 /* handle I/O interrupts */
495 if ((env->psw.mask & PSW_MASK_IO) &&
27103424 496 (cs->exception_index == -1)) {
5d69c547 497 if (env->pending_int & INTERRUPT_IO) {
27103424 498 cs->exception_index = EXCP_IO;
5d69c547
CH
499 }
500 }
d5a43964 501
27103424 502 switch (cs->exception_index) {
d5a43964
AG
503 case EXCP_PGM:
504 do_program_interrupt(env);
505 break;
506 case EXCP_SVC:
507 do_svc_interrupt(env);
508 break;
509 case EXCP_EXT:
510 do_ext_interrupt(env);
511 break;
5d69c547
CH
512 case EXCP_IO:
513 do_io_interrupt(env);
514 break;
515 case EXCP_MCHK:
516 do_mchk_interrupt(env);
517 break;
d5a43964 518 }
27103424 519 cs->exception_index = -1;
d5a43964
AG
520
521 if (!env->pending_int) {
259186a7 522 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
d5a43964 523 }
3110e292 524}
d5a43964 525
02bb9bbf
RH
526bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
527{
528 if (interrupt_request & CPU_INTERRUPT_HARD) {
529 S390CPU *cpu = S390_CPU(cs);
530 CPUS390XState *env = &cpu->env;
531
532 if (env->psw.mask & PSW_MASK_EXT) {
533 s390_cpu_do_interrupt(cs);
534 return true;
535 }
536 }
537 return false;
538}
d5a43964 539#endif /* CONFIG_USER_ONLY */