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10ec5117 AG |
1 | /* |
2 | * S/390 helpers | |
3 | * | |
4 | * Copyright (c) 2009 Ulrich Hecht | |
d5a43964 | 5 | * Copyright (c) 2011 Alexander Graf |
10ec5117 AG |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
70539e18 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
10ec5117 AG |
19 | */ |
20 | ||
10ec5117 | 21 | #include "cpu.h" |
022c62cb | 22 | #include "exec/gdbstub.h" |
1de7afc9 | 23 | #include "qemu/timer.h" |
f08b6170 | 24 | #include "exec/cpu_ldst.h" |
ef81522b | 25 | #ifndef CONFIG_USER_ONLY |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
ef81522b | 27 | #endif |
10ec5117 | 28 | |
d5a43964 | 29 | //#define DEBUG_S390 |
d5a43964 AG |
30 | //#define DEBUG_S390_STDOUT |
31 | ||
32 | #ifdef DEBUG_S390 | |
33 | #ifdef DEBUG_S390_STDOUT | |
34 | #define DPRINTF(fmt, ...) \ | |
35 | do { fprintf(stderr, fmt, ## __VA_ARGS__); \ | |
36 | qemu_log(fmt, ##__VA_ARGS__); } while (0) | |
37 | #else | |
38 | #define DPRINTF(fmt, ...) \ | |
39 | do { qemu_log(fmt, ## __VA_ARGS__); } while (0) | |
40 | #endif | |
41 | #else | |
42 | #define DPRINTF(fmt, ...) \ | |
43 | do { } while (0) | |
44 | #endif | |
45 | ||
d5a43964 AG |
46 | |
47 | #ifndef CONFIG_USER_ONLY | |
8f22e0df | 48 | void s390x_tod_timer(void *opaque) |
d5a43964 | 49 | { |
b8ba6799 AF |
50 | S390CPU *cpu = opaque; |
51 | CPUS390XState *env = &cpu->env; | |
d5a43964 AG |
52 | |
53 | env->pending_int |= INTERRUPT_TOD; | |
c3affe56 | 54 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
d5a43964 AG |
55 | } |
56 | ||
8f22e0df | 57 | void s390x_cpu_timer(void *opaque) |
d5a43964 | 58 | { |
b8ba6799 AF |
59 | S390CPU *cpu = opaque; |
60 | CPUS390XState *env = &cpu->env; | |
d5a43964 AG |
61 | |
62 | env->pending_int |= INTERRUPT_CPUTIMER; | |
c3affe56 | 63 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); |
d5a43964 AG |
64 | } |
65 | #endif | |
10c339a0 | 66 | |
564b863d | 67 | S390CPU *cpu_s390x_init(const char *cpu_model) |
10ec5117 | 68 | { |
29e4bcb2 | 69 | S390CPU *cpu; |
10ec5117 | 70 | |
29e4bcb2 | 71 | cpu = S390_CPU(object_new(TYPE_S390_CPU)); |
1f136632 AF |
72 | |
73 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
74 | ||
564b863d | 75 | return cpu; |
10ec5117 AG |
76 | } |
77 | ||
d5a43964 AG |
78 | #if defined(CONFIG_USER_ONLY) |
79 | ||
97a8ea5a | 80 | void s390_cpu_do_interrupt(CPUState *cs) |
d5a43964 | 81 | { |
27103424 | 82 | cs->exception_index = -1; |
d5a43964 AG |
83 | } |
84 | ||
7510454e AF |
85 | int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
86 | int rw, int mmu_idx) | |
d5a43964 | 87 | { |
7510454e AF |
88 | S390CPU *cpu = S390_CPU(cs); |
89 | ||
27103424 | 90 | cs->exception_index = EXCP_PGM; |
7510454e | 91 | cpu->env.int_pgm_code = PGM_ADDRESSING; |
d5a103cd RH |
92 | /* On real machines this value is dropped into LowMem. Since this |
93 | is userland, simply put this someplace that cpu_loop can find it. */ | |
7510454e | 94 | cpu->env.__excp_addr = address; |
d5a43964 AG |
95 | return 1; |
96 | } | |
97 | ||
b7e516ce | 98 | #else /* !CONFIG_USER_ONLY */ |
d5a43964 AG |
99 | |
100 | /* Ensure to exit the TB after this call! */ | |
dfebd7a7 | 101 | void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen) |
d5a43964 | 102 | { |
27103424 AF |
103 | CPUState *cs = CPU(s390_env_get_cpu(env)); |
104 | ||
105 | cs->exception_index = EXCP_PGM; | |
d5a43964 | 106 | env->int_pgm_code = code; |
d5a103cd | 107 | env->int_pgm_ilen = ilen; |
d5a43964 AG |
108 | } |
109 | ||
7510454e AF |
110 | int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, |
111 | int rw, int mmu_idx) | |
10c339a0 | 112 | { |
7510454e AF |
113 | S390CPU *cpu = S390_CPU(cs); |
114 | CPUS390XState *env = &cpu->env; | |
d5a43964 AG |
115 | uint64_t asc = env->psw.mask & PSW_MASK_ASC; |
116 | target_ulong vaddr, raddr; | |
10c339a0 AG |
117 | int prot; |
118 | ||
7510454e | 119 | DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", |
07cc7d12 | 120 | __func__, orig_vaddr, rw, mmu_idx); |
d5a43964 | 121 | |
71e47088 BS |
122 | orig_vaddr &= TARGET_PAGE_MASK; |
123 | vaddr = orig_vaddr; | |
d5a43964 AG |
124 | |
125 | /* 31-Bit mode */ | |
126 | if (!(env->psw.mask & PSW_MASK_64)) { | |
127 | vaddr &= 0x7fffffff; | |
128 | } | |
129 | ||
e3e09d87 | 130 | if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) { |
d5a43964 AG |
131 | /* Translation ended in exception */ |
132 | return 1; | |
133 | } | |
10c339a0 | 134 | |
d5a43964 AG |
135 | /* check out of RAM access */ |
136 | if (raddr > (ram_size + virtio_size)) { | |
a6f921b0 AF |
137 | DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, |
138 | (uint64_t)raddr, (uint64_t)ram_size); | |
d5a103cd | 139 | trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER); |
d5a43964 AG |
140 | return 1; |
141 | } | |
10c339a0 | 142 | |
339aaf5b AP |
143 | qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", |
144 | __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); | |
d5a43964 | 145 | |
0c591eb0 | 146 | tlb_set_page(cs, orig_vaddr, raddr, prot, |
d4c430a8 | 147 | mmu_idx, TARGET_PAGE_SIZE); |
d5a43964 | 148 | |
d4c430a8 | 149 | return 0; |
10c339a0 | 150 | } |
d5a43964 | 151 | |
00b941e5 | 152 | hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) |
d5a43964 | 153 | { |
00b941e5 AF |
154 | S390CPU *cpu = S390_CPU(cs); |
155 | CPUS390XState *env = &cpu->env; | |
d5a43964 | 156 | target_ulong raddr; |
e3e09d87 | 157 | int prot; |
d5a43964 AG |
158 | uint64_t asc = env->psw.mask & PSW_MASK_ASC; |
159 | ||
160 | /* 31-Bit mode */ | |
161 | if (!(env->psw.mask & PSW_MASK_64)) { | |
162 | vaddr &= 0x7fffffff; | |
163 | } | |
164 | ||
217a4acb | 165 | mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false); |
d5a43964 AG |
166 | |
167 | return raddr; | |
168 | } | |
169 | ||
770a6379 DH |
170 | hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr) |
171 | { | |
172 | hwaddr phys_addr; | |
173 | target_ulong page; | |
174 | ||
175 | page = vaddr & TARGET_PAGE_MASK; | |
176 | phys_addr = cpu_get_phys_page_debug(cs, page); | |
177 | phys_addr += (vaddr & ~TARGET_PAGE_MASK); | |
178 | ||
179 | return phys_addr; | |
180 | } | |
181 | ||
a4e3ad19 | 182 | void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) |
d5a43964 | 183 | { |
eb24f7c6 DH |
184 | env->psw.addr = addr; |
185 | env->psw.mask = mask; | |
3f10341f DH |
186 | if (tcg_enabled()) { |
187 | env->cc_op = (mask >> 44) & 3; | |
188 | } | |
eb24f7c6 | 189 | |
d5a43964 | 190 | if (mask & PSW_MASK_WAIT) { |
49e15878 | 191 | S390CPU *cpu = s390_env_get_cpu(env); |
eb24f7c6 | 192 | if (s390_cpu_halt(cpu) == 0) { |
ef81522b | 193 | #ifndef CONFIG_USER_ONLY |
eb24f7c6 | 194 | qemu_system_shutdown_request(); |
ef81522b | 195 | #endif |
d5a43964 AG |
196 | } |
197 | } | |
d5a43964 AG |
198 | } |
199 | ||
a4e3ad19 | 200 | static uint64_t get_psw_mask(CPUS390XState *env) |
d5a43964 | 201 | { |
3f10341f | 202 | uint64_t r = env->psw.mask; |
d5a43964 | 203 | |
3f10341f DH |
204 | if (tcg_enabled()) { |
205 | env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, | |
206 | env->cc_vr); | |
d5a43964 | 207 | |
3f10341f DH |
208 | r &= ~PSW_MASK_CC; |
209 | assert(!(env->cc_op & ~3)); | |
210 | r |= (uint64_t)env->cc_op << 44; | |
211 | } | |
d5a43964 AG |
212 | |
213 | return r; | |
214 | } | |
215 | ||
4782a23b CH |
216 | static LowCore *cpu_map_lowcore(CPUS390XState *env) |
217 | { | |
a47dddd7 | 218 | S390CPU *cpu = s390_env_get_cpu(env); |
4782a23b CH |
219 | LowCore *lowcore; |
220 | hwaddr len = sizeof(LowCore); | |
221 | ||
222 | lowcore = cpu_physical_memory_map(env->psa, &len, 1); | |
223 | ||
224 | if (len < sizeof(LowCore)) { | |
a47dddd7 | 225 | cpu_abort(CPU(cpu), "Could not map lowcore\n"); |
4782a23b CH |
226 | } |
227 | ||
228 | return lowcore; | |
229 | } | |
230 | ||
231 | static void cpu_unmap_lowcore(LowCore *lowcore) | |
232 | { | |
233 | cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore)); | |
234 | } | |
235 | ||
3f10341f DH |
236 | void do_restart_interrupt(CPUS390XState *env) |
237 | { | |
238 | uint64_t mask, addr; | |
239 | LowCore *lowcore; | |
240 | ||
241 | lowcore = cpu_map_lowcore(env); | |
242 | ||
243 | lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
244 | lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr); | |
245 | mask = be64_to_cpu(lowcore->restart_new_psw.mask); | |
246 | addr = be64_to_cpu(lowcore->restart_new_psw.addr); | |
247 | ||
248 | cpu_unmap_lowcore(lowcore); | |
249 | ||
250 | load_psw(env, mask, addr); | |
251 | } | |
252 | ||
a4e3ad19 | 253 | static void do_svc_interrupt(CPUS390XState *env) |
d5a43964 AG |
254 | { |
255 | uint64_t mask, addr; | |
256 | LowCore *lowcore; | |
d5a43964 | 257 | |
4782a23b | 258 | lowcore = cpu_map_lowcore(env); |
d5a43964 AG |
259 | |
260 | lowcore->svc_code = cpu_to_be16(env->int_svc_code); | |
d5a103cd | 261 | lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen); |
d5a43964 | 262 | lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env)); |
d5a103cd | 263 | lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen); |
d5a43964 AG |
264 | mask = be64_to_cpu(lowcore->svc_new_psw.mask); |
265 | addr = be64_to_cpu(lowcore->svc_new_psw.addr); | |
266 | ||
4782a23b | 267 | cpu_unmap_lowcore(lowcore); |
d5a43964 AG |
268 | |
269 | load_psw(env, mask, addr); | |
270 | } | |
271 | ||
a4e3ad19 | 272 | static void do_program_interrupt(CPUS390XState *env) |
d5a43964 AG |
273 | { |
274 | uint64_t mask, addr; | |
275 | LowCore *lowcore; | |
d5a103cd | 276 | int ilen = env->int_pgm_ilen; |
d5a43964 | 277 | |
d5a103cd RH |
278 | switch (ilen) { |
279 | case ILEN_LATER: | |
280 | ilen = get_ilen(cpu_ldub_code(env, env->psw.addr)); | |
d5a43964 | 281 | break; |
d5a103cd RH |
282 | case ILEN_LATER_INC: |
283 | ilen = get_ilen(cpu_ldub_code(env, env->psw.addr)); | |
284 | env->psw.addr += ilen; | |
d5a43964 | 285 | break; |
d5a103cd RH |
286 | default: |
287 | assert(ilen == 2 || ilen == 4 || ilen == 6); | |
d5a43964 AG |
288 | } |
289 | ||
d5a103cd RH |
290 | qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n", |
291 | __func__, env->int_pgm_code, ilen); | |
d5a43964 | 292 | |
4782a23b | 293 | lowcore = cpu_map_lowcore(env); |
d5a43964 | 294 | |
d5a103cd | 295 | lowcore->pgm_ilen = cpu_to_be16(ilen); |
d5a43964 AG |
296 | lowcore->pgm_code = cpu_to_be16(env->int_pgm_code); |
297 | lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
298 | lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr); | |
299 | mask = be64_to_cpu(lowcore->program_new_psw.mask); | |
300 | addr = be64_to_cpu(lowcore->program_new_psw.addr); | |
301 | ||
4782a23b | 302 | cpu_unmap_lowcore(lowcore); |
d5a43964 | 303 | |
71e47088 | 304 | DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__, |
d5a103cd | 305 | env->int_pgm_code, ilen, env->psw.mask, |
d5a43964 AG |
306 | env->psw.addr); |
307 | ||
308 | load_psw(env, mask, addr); | |
309 | } | |
310 | ||
311 | #define VIRTIO_SUBCODE_64 0x0D00 | |
312 | ||
a4e3ad19 | 313 | static void do_ext_interrupt(CPUS390XState *env) |
d5a43964 | 314 | { |
a47dddd7 | 315 | S390CPU *cpu = s390_env_get_cpu(env); |
d5a43964 AG |
316 | uint64_t mask, addr; |
317 | LowCore *lowcore; | |
d5a43964 AG |
318 | ExtQueue *q; |
319 | ||
320 | if (!(env->psw.mask & PSW_MASK_EXT)) { | |
a47dddd7 | 321 | cpu_abort(CPU(cpu), "Ext int w/o ext mask\n"); |
d5a43964 AG |
322 | } |
323 | ||
1a719923 | 324 | if (env->ext_index < 0 || env->ext_index >= MAX_EXT_QUEUE) { |
a47dddd7 | 325 | cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index); |
d5a43964 AG |
326 | } |
327 | ||
328 | q = &env->ext_queue[env->ext_index]; | |
4782a23b | 329 | lowcore = cpu_map_lowcore(env); |
d5a43964 AG |
330 | |
331 | lowcore->ext_int_code = cpu_to_be16(q->code); | |
332 | lowcore->ext_params = cpu_to_be32(q->param); | |
333 | lowcore->ext_params2 = cpu_to_be64(q->param64); | |
334 | lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
335 | lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr); | |
336 | lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64); | |
337 | mask = be64_to_cpu(lowcore->external_new_psw.mask); | |
338 | addr = be64_to_cpu(lowcore->external_new_psw.addr); | |
339 | ||
4782a23b | 340 | cpu_unmap_lowcore(lowcore); |
d5a43964 AG |
341 | |
342 | env->ext_index--; | |
343 | if (env->ext_index == -1) { | |
344 | env->pending_int &= ~INTERRUPT_EXT; | |
345 | } | |
346 | ||
71e47088 | 347 | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, |
d5a43964 AG |
348 | env->psw.mask, env->psw.addr); |
349 | ||
350 | load_psw(env, mask, addr); | |
351 | } | |
3110e292 | 352 | |
5d69c547 CH |
353 | static void do_io_interrupt(CPUS390XState *env) |
354 | { | |
a47dddd7 | 355 | S390CPU *cpu = s390_env_get_cpu(env); |
5d69c547 CH |
356 | LowCore *lowcore; |
357 | IOIntQueue *q; | |
358 | uint8_t isc; | |
359 | int disable = 1; | |
360 | int found = 0; | |
361 | ||
362 | if (!(env->psw.mask & PSW_MASK_IO)) { | |
a47dddd7 | 363 | cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n"); |
5d69c547 CH |
364 | } |
365 | ||
366 | for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) { | |
91b0a8f3 CH |
367 | uint64_t isc_bits; |
368 | ||
5d69c547 CH |
369 | if (env->io_index[isc] < 0) { |
370 | continue; | |
371 | } | |
1a719923 | 372 | if (env->io_index[isc] >= MAX_IO_QUEUE) { |
a47dddd7 | 373 | cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n", |
5d69c547 CH |
374 | isc, env->io_index[isc]); |
375 | } | |
376 | ||
377 | q = &env->io_queue[env->io_index[isc]][isc]; | |
91b0a8f3 CH |
378 | isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word)); |
379 | if (!(env->cregs[6] & isc_bits)) { | |
5d69c547 CH |
380 | disable = 0; |
381 | continue; | |
382 | } | |
bd9a8d85 CH |
383 | if (!found) { |
384 | uint64_t mask, addr; | |
5d69c547 | 385 | |
bd9a8d85 CH |
386 | found = 1; |
387 | lowcore = cpu_map_lowcore(env); | |
5d69c547 | 388 | |
bd9a8d85 CH |
389 | lowcore->subchannel_id = cpu_to_be16(q->id); |
390 | lowcore->subchannel_nr = cpu_to_be16(q->nr); | |
391 | lowcore->io_int_parm = cpu_to_be32(q->parm); | |
392 | lowcore->io_int_word = cpu_to_be32(q->word); | |
393 | lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
394 | lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr); | |
395 | mask = be64_to_cpu(lowcore->io_new_psw.mask); | |
396 | addr = be64_to_cpu(lowcore->io_new_psw.addr); | |
5d69c547 | 397 | |
bd9a8d85 CH |
398 | cpu_unmap_lowcore(lowcore); |
399 | ||
400 | env->io_index[isc]--; | |
401 | ||
402 | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, | |
403 | env->psw.mask, env->psw.addr); | |
404 | load_psw(env, mask, addr); | |
405 | } | |
b22dd124 | 406 | if (env->io_index[isc] >= 0) { |
5d69c547 CH |
407 | disable = 0; |
408 | } | |
bd9a8d85 | 409 | continue; |
5d69c547 CH |
410 | } |
411 | ||
412 | if (disable) { | |
413 | env->pending_int &= ~INTERRUPT_IO; | |
414 | } | |
415 | ||
5d69c547 CH |
416 | } |
417 | ||
418 | static void do_mchk_interrupt(CPUS390XState *env) | |
419 | { | |
a47dddd7 | 420 | S390CPU *cpu = s390_env_get_cpu(env); |
5d69c547 CH |
421 | uint64_t mask, addr; |
422 | LowCore *lowcore; | |
423 | MchkQueue *q; | |
424 | int i; | |
425 | ||
426 | if (!(env->psw.mask & PSW_MASK_MCHECK)) { | |
a47dddd7 | 427 | cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n"); |
5d69c547 CH |
428 | } |
429 | ||
1a719923 | 430 | if (env->mchk_index < 0 || env->mchk_index >= MAX_MCHK_QUEUE) { |
a47dddd7 | 431 | cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index); |
5d69c547 CH |
432 | } |
433 | ||
434 | q = &env->mchk_queue[env->mchk_index]; | |
435 | ||
436 | if (q->type != 1) { | |
437 | /* Don't know how to handle this... */ | |
a47dddd7 | 438 | cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type); |
5d69c547 CH |
439 | } |
440 | if (!(env->cregs[14] & (1 << 28))) { | |
441 | /* CRW machine checks disabled */ | |
442 | return; | |
443 | } | |
444 | ||
445 | lowcore = cpu_map_lowcore(env); | |
446 | ||
447 | for (i = 0; i < 16; i++) { | |
448 | lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll); | |
449 | lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]); | |
450 | lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]); | |
451 | lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]); | |
452 | } | |
453 | lowcore->prefixreg_save_area = cpu_to_be32(env->psa); | |
454 | lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc); | |
455 | lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr); | |
456 | lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32); | |
457 | lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm); | |
458 | lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32); | |
459 | lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc); | |
460 | ||
461 | lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d); | |
462 | lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000); | |
463 | lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env)); | |
464 | lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr); | |
465 | mask = be64_to_cpu(lowcore->mcck_new_psw.mask); | |
466 | addr = be64_to_cpu(lowcore->mcck_new_psw.addr); | |
467 | ||
468 | cpu_unmap_lowcore(lowcore); | |
469 | ||
470 | env->mchk_index--; | |
471 | if (env->mchk_index == -1) { | |
472 | env->pending_int &= ~INTERRUPT_MCHK; | |
473 | } | |
474 | ||
475 | DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__, | |
476 | env->psw.mask, env->psw.addr); | |
477 | ||
478 | load_psw(env, mask, addr); | |
479 | } | |
480 | ||
97a8ea5a | 481 | void s390_cpu_do_interrupt(CPUState *cs) |
3110e292 | 482 | { |
97a8ea5a AF |
483 | S390CPU *cpu = S390_CPU(cs); |
484 | CPUS390XState *env = &cpu->env; | |
f9466733 | 485 | |
0d404541 | 486 | qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n", |
27103424 | 487 | __func__, cs->exception_index, env->psw.addr); |
d5a43964 | 488 | |
eb24f7c6 | 489 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
5d69c547 CH |
490 | /* handle machine checks */ |
491 | if ((env->psw.mask & PSW_MASK_MCHECK) && | |
27103424 | 492 | (cs->exception_index == -1)) { |
5d69c547 | 493 | if (env->pending_int & INTERRUPT_MCHK) { |
27103424 | 494 | cs->exception_index = EXCP_MCHK; |
5d69c547 CH |
495 | } |
496 | } | |
d5a43964 AG |
497 | /* handle external interrupts */ |
498 | if ((env->psw.mask & PSW_MASK_EXT) && | |
27103424 | 499 | cs->exception_index == -1) { |
d5a43964 AG |
500 | if (env->pending_int & INTERRUPT_EXT) { |
501 | /* code is already in env */ | |
27103424 | 502 | cs->exception_index = EXCP_EXT; |
d5a43964 | 503 | } else if (env->pending_int & INTERRUPT_TOD) { |
f9466733 | 504 | cpu_inject_ext(cpu, 0x1004, 0, 0); |
27103424 | 505 | cs->exception_index = EXCP_EXT; |
d5a43964 AG |
506 | env->pending_int &= ~INTERRUPT_EXT; |
507 | env->pending_int &= ~INTERRUPT_TOD; | |
508 | } else if (env->pending_int & INTERRUPT_CPUTIMER) { | |
f9466733 | 509 | cpu_inject_ext(cpu, 0x1005, 0, 0); |
27103424 | 510 | cs->exception_index = EXCP_EXT; |
d5a43964 AG |
511 | env->pending_int &= ~INTERRUPT_EXT; |
512 | env->pending_int &= ~INTERRUPT_TOD; | |
513 | } | |
514 | } | |
5d69c547 CH |
515 | /* handle I/O interrupts */ |
516 | if ((env->psw.mask & PSW_MASK_IO) && | |
27103424 | 517 | (cs->exception_index == -1)) { |
5d69c547 | 518 | if (env->pending_int & INTERRUPT_IO) { |
27103424 | 519 | cs->exception_index = EXCP_IO; |
5d69c547 CH |
520 | } |
521 | } | |
d5a43964 | 522 | |
27103424 | 523 | switch (cs->exception_index) { |
d5a43964 AG |
524 | case EXCP_PGM: |
525 | do_program_interrupt(env); | |
526 | break; | |
527 | case EXCP_SVC: | |
528 | do_svc_interrupt(env); | |
529 | break; | |
530 | case EXCP_EXT: | |
531 | do_ext_interrupt(env); | |
532 | break; | |
5d69c547 CH |
533 | case EXCP_IO: |
534 | do_io_interrupt(env); | |
535 | break; | |
536 | case EXCP_MCHK: | |
537 | do_mchk_interrupt(env); | |
538 | break; | |
d5a43964 | 539 | } |
27103424 | 540 | cs->exception_index = -1; |
d5a43964 AG |
541 | |
542 | if (!env->pending_int) { | |
259186a7 | 543 | cs->interrupt_request &= ~CPU_INTERRUPT_HARD; |
d5a43964 | 544 | } |
3110e292 | 545 | } |
d5a43964 | 546 | |
02bb9bbf RH |
547 | bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
548 | { | |
549 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
550 | S390CPU *cpu = S390_CPU(cs); | |
551 | CPUS390XState *env = &cpu->env; | |
552 | ||
553 | if (env->psw.mask & PSW_MASK_EXT) { | |
554 | s390_cpu_do_interrupt(cs); | |
555 | return true; | |
556 | } | |
557 | } | |
558 | return false; | |
559 | } | |
d5a43964 | 560 | #endif /* CONFIG_USER_ONLY */ |