[mirror_qemu.git] / target-s390x / misc_helper.c

/*
 *  S/390 misc helper routines
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2009 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "memory.h"
#include "cputlb.h"
#include "dyngen-exec.h"
#include "host-utils.h"
#include "helper.h"
#include <string.h>
#include "kvm.h"
#include "qemu-timer.h"
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#endif

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#include "sysemu.h"
#endif

/* #define DEBUG_HELPER */
#ifdef DEBUG_HELPER
#define HELPER_LOG(x...) qemu_log(x)
#else
#define HELPER_LOG(x...)
#endif

/* raise an exception */
void HELPER(exception)(uint32_t excp)
{
    HELPER_LOG("%s: exception %d\n", __func__, excp);
    env->exception_index = excp;
    cpu_loop_exit(env);
}

#ifndef CONFIG_USER_ONLY
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
    qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);

    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
#endif
    } else {
        env->int_pgm_code = code;
        env->int_pgm_ilc = ilc;
        env->exception_index = EXCP_PGM;
        cpu_loop_exit(env);
    }
}

/*
 * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
 */
int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
{
    int r = 0;
    int shift = 0;

#ifdef DEBUG_HELPER
    printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
#endif

    /* basic checks */
    if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
        return -PGM_ADDRESSING;
    }
    if (sccb & ~0x7ffffff8ul) {
        return -PGM_SPECIFICATION;
    }

    switch (code) {
    case SCLP_CMDW_READ_SCP_INFO:
    case SCLP_CMDW_READ_SCP_INFO_FORCED:
        while ((ram_size >> (20 + shift)) > 65535) {
            shift++;
        }
        stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
        stb_phys(sccb + SCP_INCREMENT, 1 << shift);
        stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);

        s390_sclp_extint(sccb & ~3);
        break;
    default:
#ifdef DEBUG_HELPER
        printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
#endif
        r = 3;
        break;
    }

    return r;
}

/* SCLP service call */
uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
{
    int r;

    r = sclp_service_call(env, r1, r2);
    if (r < 0) {
        program_interrupt(env, -r, 4);
        return 0;
    }
    return r;
}

/* DIAG */
uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
{
    uint64_t r;

    switch (num) {
    case 0x500:
        /* KVM hypercall */
        r = s390_virtio_hypercall(env, mem, code);
        break;
    case 0x44:
        /* yield */
        r = 0;
        break;
    case 0x308:
        /* ipl */
        r = 0;
        break;
    default:
        r = -1;
        break;
    }

    if (r) {
        program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
    }

    return r;
}

/* Store CPU ID */
void HELPER(stidp)(uint64_t a1)
{
    stq(a1, env->cpu_num);
}

/* Set Prefix */
void HELPER(spx)(uint64_t a1)
{
    uint32_t prefix;

    prefix = ldl(a1);
    env->psa = prefix & 0xfffff000;
    qemu_log("prefix: %#x\n", prefix);
    tlb_flush_page(env, 0);
    tlb_flush_page(env, TARGET_PAGE_SIZE);
}

/* Set Clock */
uint32_t HELPER(sck)(uint64_t a1)
{
    /* XXX not implemented - is it necessary? */

    return 0;
}

static inline uint64_t clock_value(CPUS390XState *env)
{
    uint64_t time;

    time = env->tod_offset +
        time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);

    return time;
}

/* Store Clock */
uint32_t HELPER(stck)(uint64_t a1)
{
    stq(a1, clock_value(env));

    return 0;
}

/* Store Clock Extended */
uint32_t HELPER(stcke)(uint64_t a1)
{
    stb(a1, 0);
    /* basically the same value as stck */
    stq(a1 + 1, clock_value(env) | env->cpu_num);
    /* more fine grained than stck */
    stq(a1 + 9, 0);
    /* XXX programmable fields */
    stw(a1 + 17, 0);

    return 0;
}

/* Set Clock Comparator */
void HELPER(sckc)(uint64_t a1)
{
    uint64_t time = ldq(a1);

    if (time == -1ULL) {
        return;
    }

    /* difference between now and then */
    time -= clock_value(env);
    /* nanoseconds */
    time = (time * 125) >> 9;

    qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
}

/* Store Clock Comparator */
void HELPER(stckc)(uint64_t a1)
{
    /* XXX implement */
    stq(a1, 0);
}

/* Set CPU Timer */
void HELPER(spt)(uint64_t a1)
{
    uint64_t time = ldq(a1);

    if (time == -1ULL) {
        return;
    }

    /* nanoseconds */
    time = (time * 125) >> 9;

    qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
}

/* Store CPU Timer */
void HELPER(stpt)(uint64_t a1)
{
    /* XXX implement */
    stq(a1, 0);
}

/* Store System Information */
uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
{
    int cc = 0;
    int sel1, sel2;

    if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
        ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
        /* valid function code, invalid reserved bits */
        program_interrupt(env, PGM_SPECIFICATION, 2);
    }

    sel1 = r0 & STSI_R0_SEL1_MASK;
    sel2 = r1 & STSI_R1_SEL2_MASK;

    /* XXX: spec exception if sysib is not 4k-aligned */

    switch (r0 & STSI_LEVEL_MASK) {
    case STSI_LEVEL_1:
        if ((sel1 == 1) && (sel2 == 1)) {
            /* Basic Machine Configuration */
            struct sysib_111 sysib;

            memset(&sysib, 0, sizeof(sysib));
            ebcdic_put(sysib.manuf, "QEMU            ", 16);
            /* same as machine type number in STORE CPU ID */
            ebcdic_put(sysib.type, "QEMU", 4);
            /* same as model number in STORE CPU ID */
            ebcdic_put(sysib.model, "QEMU            ", 16);
            ebcdic_put(sysib.sequence, "QEMU            ", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 1)) {
            /* Basic Machine CPU */
            struct sysib_121 sysib;

            memset(&sysib, 0, sizeof(sysib));
            /* XXX make different for different CPUs? */
            ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            stw_p(&sysib.cpu_addr, env->cpu_num);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 2)) {
            /* Basic Machine CPUs */
            struct sysib_122 sysib;

            memset(&sysib, 0, sizeof(sysib));
            stl_p(&sysib.capability, 0x443afc29);
            /* XXX change when SMP comes */
            stw_p(&sysib.total_cpus, 1);
            stw_p(&sysib.active_cpus, 1);
            stw_p(&sysib.standby_cpus, 0);
            stw_p(&sysib.reserved_cpus, 0);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else {
            cc = 3;
        }
        break;
    case STSI_LEVEL_2:
        {
            if ((sel1 == 2) && (sel2 == 1)) {
                /* LPAR CPU */
                struct sysib_221 sysib;

                memset(&sysib, 0, sizeof(sysib));
                /* XXX make different for different CPUs? */
                ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
                ebcdic_put(sysib.plant, "QEMU", 4);
                stw_p(&sysib.cpu_addr, env->cpu_num);
                stw_p(&sysib.cpu_id, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else if ((sel1 == 2) && (sel2 == 2)) {
                /* LPAR CPUs */
                struct sysib_222 sysib;

                memset(&sysib, 0, sizeof(sysib));
                stw_p(&sysib.lpar_num, 0);
                sysib.lcpuc = 0;
                /* XXX change when SMP comes */
                stw_p(&sysib.total_cpus, 1);
                stw_p(&sysib.conf_cpus, 1);
                stw_p(&sysib.standby_cpus, 0);
                stw_p(&sysib.reserved_cpus, 0);
                ebcdic_put(sysib.name, "QEMU    ", 8);
                stl_p(&sysib.caf, 1000);
                stw_p(&sysib.dedicated_cpus, 0);
                stw_p(&sysib.shared_cpus, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_3:
        {
            if ((sel1 == 2) && (sel2 == 2)) {
                /* VM CPUs */
                struct sysib_322 sysib;

                memset(&sysib, 0, sizeof(sysib));
                sysib.count = 1;
                /* XXX change when SMP comes */
                stw_p(&sysib.vm[0].total_cpus, 1);
                stw_p(&sysib.vm[0].conf_cpus, 1);
                stw_p(&sysib.vm[0].standby_cpus, 0);
                stw_p(&sysib.vm[0].reserved_cpus, 0);
                ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
                stl_p(&sysib.vm[0].caf, 1000);
                ebcdic_put(sysib.vm[0].cpi, "KVM/Linux       ", 16);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_CURRENT:
        env->regs[0] = STSI_LEVEL_3;
        break;
    default:
        cc = 3;
        break;
    }

    return cc;
}

uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
{
    int cc = 0;

    HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
               __func__, order_code, r1, cpu_addr);

    /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
       as parameter (input). Status (output) is always R1. */

    switch (order_code) {
    case SIGP_SET_ARCH:
        /* switch arch */
        break;
    case SIGP_SENSE:
        /* enumerate CPU status */
        if (cpu_addr) {
            /* XXX implement when SMP comes */
            return 3;
        }
        env->regs[r1] &= 0xffffffff00000000ULL;
        cc = 1;
        break;
#if !defined(CONFIG_USER_ONLY)
    case SIGP_RESTART:
        qemu_system_reset_request();
        cpu_loop_exit(env);
        break;
    case SIGP_STOP:
        qemu_system_shutdown_request();
        cpu_loop_exit(env);
        break;
#endif
    default:
        /* unknown sigp */
        fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
        cc = 3;
    }

    return cc;
}
#endif
Commit	Line	Data
10ec5117	1	/*
aea1e885	2	* S/390 misc helper routines
10ec5117	3	*
defb0e31	4	* Copyright (c) 2009 Ulrich Hecht
10ec5117 AG	5	* Copyright (c) 2009 Alexander Graf
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
70539e18	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 AG	19	*/
10ec5117 AG	20
3e457172	21	#include "cpu.h"
9abf567d CB	22	#include "memory.h"
9abf567d CB	23	#include "cputlb.h"
3e457172	24	#include "dyngen-exec.h"
defb0e31	25	#include "host-utils.h"
3208afbe	26	#include "helper.h"
defb0e31 AG	27	#include <string.h>
	28	#include "kvm.h"
	29	#include "qemu-timer.h"
af2be207 JK	30	#ifdef CONFIG_KVM
	31	#include <linux/kvm.h>
	32	#endif
10ec5117	33
71e47088	34	#if !defined(CONFIG_USER_ONLY)
3e457172	35	#include "softmmu_exec.h"
8ef7f78e	36	#include "sysemu.h"
10ec5117	37	#endif
d5a43964	38
defb0e31 AG	39	/* #define DEBUG_HELPER */
	40	#ifdef DEBUG_HELPER
	41	#define HELPER_LOG(x...) qemu_log(x)
	42	#else
	43	#define HELPER_LOG(x...)
	44	#endif
	45
	46	/* raise an exception */
	47	void HELPER(exception)(uint32_t excp)
	48	{
71e47088	49	HELPER_LOG("%s: exception %d\n", __func__, excp);
defb0e31	50	env->exception_index = excp;
1162c041	51	cpu_loop_exit(env);
defb0e31 AG	52	}
defb0e31 AG	53
defb0e31	54	#ifndef CONFIG_USER_ONLY
a78b0504	55	void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
defb0e31 AG	56	{
	57	qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
	58
	59	if (kvm_enabled()) {
af2be207	60	#ifdef CONFIG_KVM
defb0e31	61	kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
af2be207	62	#endif
defb0e31 AG	63	} else {
	64	env->int_pgm_code = code;
	65	env->int_pgm_ilc = ilc;
	66	env->exception_index = EXCP_PGM;
1162c041	67	cpu_loop_exit(env);
defb0e31 AG	68	}
	69	}
	70
9abf567d	71	/*
71e47088	72	* ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
9abf567d	73	*/
a4e3ad19	74	int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
defb0e31 AG	75	{
defb0e31 AG	76	int r = 0;
22486aa0	77	int shift = 0;
defb0e31 AG	78
	79	#ifdef DEBUG_HELPER
	80	printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
	81	#endif
	82
9abf567d CB	83	/* basic checks */
	84	if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
	85	return -PGM_ADDRESSING;
	86	}
defb0e31	87	if (sccb & ~0x7ffffff8ul) {
9abf567d	88	return -PGM_SPECIFICATION;
defb0e31 AG	89	}
defb0e31 AG	90
71e47088 BS	91	switch (code) {
	92	case SCLP_CMDW_READ_SCP_INFO:
	93	case SCLP_CMDW_READ_SCP_INFO_FORCED:
	94	while ((ram_size >> (20 + shift)) > 65535) {
	95	shift++;
	96	}
	97	stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
	98	stb_phys(sccb + SCP_INCREMENT, 1 << shift);
	99	stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
defb0e31	100
71e47088 BS	101	s390_sclp_extint(sccb & ~3);
	102	break;
	103	default:
defb0e31	104	#ifdef DEBUG_HELPER
71e47088	105	printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
defb0e31	106	#endif
71e47088 BS	107	r = 3;
71e47088 BS	108	break;
defb0e31 AG	109	}
defb0e31 AG	110
defb0e31 AG	111	return r;
	112	}
	113
	114	/* SCLP service call */
	115	uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
	116	{
9abf567d	117	int r;
defb0e31	118
9abf567d CB	119	r = sclp_service_call(env, r1, r2);
	120	if (r < 0) {
	121	program_interrupt(env, -r, 4);
	122	return 0;
	123	}
	124	return r;
defb0e31 AG	125	}
	126
	127	/* DIAG */
	128	uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
	129	{
	130	uint64_t r;
	131
	132	switch (num) {
	133	case 0x500:
	134	/* KVM hypercall */
	135	r = s390_virtio_hypercall(env, mem, code);
	136	break;
	137	case 0x44:
	138	/* yield */
	139	r = 0;
	140	break;
	141	case 0x308:
	142	/* ipl */
	143	r = 0;
	144	break;
	145	default:
	146	r = -1;
	147	break;
	148	}
	149
	150	if (r) {
	151	program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
	152	}
	153
	154	return r;
	155	}
	156
	157	/* Store CPU ID */
	158	void HELPER(stidp)(uint64_t a1)
	159	{
	160	stq(a1, env->cpu_num);
	161	}
	162
	163	/* Set Prefix */
	164	void HELPER(spx)(uint64_t a1)
	165	{
	166	uint32_t prefix;
	167
	168	prefix = ldl(a1);
	169	env->psa = prefix & 0xfffff000;
	170	qemu_log("prefix: %#x\n", prefix);
	171	tlb_flush_page(env, 0);
	172	tlb_flush_page(env, TARGET_PAGE_SIZE);
	173	}
	174
	175	/* Set Clock */
	176	uint32_t HELPER(sck)(uint64_t a1)
	177	{
	178	/* XXX not implemented - is it necessary? */
	179
	180	return 0;
	181	}
	182
a4e3ad19	183	static inline uint64_t clock_value(CPUS390XState *env)
defb0e31 AG	184	{
	185	uint64_t time;
	186
	187	time = env->tod_offset +
71e47088	188	time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
defb0e31 AG	189
	190	return time;
	191	}
	192
	193	/* Store Clock */
	194	uint32_t HELPER(stck)(uint64_t a1)
	195	{
	196	stq(a1, clock_value(env));
	197
	198	return 0;
	199	}
	200
	201	/* Store Clock Extended */
	202	uint32_t HELPER(stcke)(uint64_t a1)
	203	{
	204	stb(a1, 0);
	205	/* basically the same value as stck */
	206	stq(a1 + 1, clock_value(env) \| env->cpu_num);
	207	/* more fine grained than stck */
	208	stq(a1 + 9, 0);
	209	/* XXX programmable fields */
	210	stw(a1 + 17, 0);
	211
defb0e31 AG	212	return 0;
	213	}
	214
	215	/* Set Clock Comparator */
	216	void HELPER(sckc)(uint64_t a1)
	217	{
	218	uint64_t time = ldq(a1);
	219
	220	if (time == -1ULL) {
	221	return;
	222	}
	223
	224	/* difference between now and then */
	225	time -= clock_value(env);
	226	/* nanoseconds */
	227	time = (time * 125) >> 9;
	228
	229	qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
	230	}
	231
	232	/* Store Clock Comparator */
	233	void HELPER(stckc)(uint64_t a1)
	234	{
	235	/* XXX implement */
	236	stq(a1, 0);
	237	}
	238
	239	/* Set CPU Timer */
	240	void HELPER(spt)(uint64_t a1)
	241	{
	242	uint64_t time = ldq(a1);
	243
	244	if (time == -1ULL) {
	245	return;
	246	}
	247
	248	/* nanoseconds */
	249	time = (time * 125) >> 9;
	250
	251	qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
	252	}
	253
	254	/* Store CPU Timer */
	255	void HELPER(stpt)(uint64_t a1)
	256	{
	257	/* XXX implement */
	258	stq(a1, 0);
	259	}
	260
	261	/* Store System Information */
	262	uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
	263	{
	264	int cc = 0;
	265	int sel1, sel2;
	266
	267	if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
	268	((r0 & STSI_R0_RESERVED_MASK) \|\| (r1 & STSI_R1_RESERVED_MASK))) {
	269	/* valid function code, invalid reserved bits */
	270	program_interrupt(env, PGM_SPECIFICATION, 2);
	271	}
	272
	273	sel1 = r0 & STSI_R0_SEL1_MASK;
	274	sel2 = r1 & STSI_R1_SEL2_MASK;
	275
276	/* XXX: spec exception if sysib is not 4k-aligned */
277
278	switch (r0 & STSI_LEVEL_MASK) {
279	case STSI_LEVEL_1:
280	if ((sel1 == 1) && (sel2 == 1)) {
281	/* Basic Machine Configuration */
282	struct sysib_111 sysib;
283
284	memset(&sysib, 0, sizeof(sysib));
285	ebcdic_put(sysib.manuf, "QEMU ", 16);
286	/* same as machine type number in STORE CPU ID */
287	ebcdic_put(sysib.type, "QEMU", 4);
288	/* same as model number in STORE CPU ID */
289	ebcdic_put(sysib.model, "QEMU ", 16);
290	ebcdic_put(sysib.sequence, "QEMU ", 16);
291	ebcdic_put(sysib.plant, "QEMU", 4);
71e47088	292	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	293	} else if ((sel1 == 2) && (sel2 == 1)) {
	294	/* Basic Machine CPU */
	295	struct sysib_121 sysib;
	296
	297	memset(&sysib, 0, sizeof(sysib));
	298	/* XXX make different for different CPUs? */
	299	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	300	ebcdic_put(sysib.plant, "QEMU", 4);
	301	stw_p(&sysib.cpu_addr, env->cpu_num);
71e47088	302	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	303	} else if ((sel1 == 2) && (sel2 == 2)) {
	304	/* Basic Machine CPUs */
	305	struct sysib_122 sysib;
	306
	307	memset(&sysib, 0, sizeof(sysib));
	308	stl_p(&sysib.capability, 0x443afc29);
	309	/* XXX change when SMP comes */
	310	stw_p(&sysib.total_cpus, 1);
	311	stw_p(&sysib.active_cpus, 1);
	312	stw_p(&sysib.standby_cpus, 0);
	313	stw_p(&sysib.reserved_cpus, 0);
71e47088	314	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	315	} else {
	316	cc = 3;
	317	}
	318	break;
	319	case STSI_LEVEL_2:
71e47088 BS	320	{
	321	if ((sel1 == 2) && (sel2 == 1)) {
	322	/* LPAR CPU */
	323	struct sysib_221 sysib;
	324
	325	memset(&sysib, 0, sizeof(sysib));
	326	/* XXX make different for different CPUs? */
	327	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	328	ebcdic_put(sysib.plant, "QEMU", 4);
	329	stw_p(&sysib.cpu_addr, env->cpu_num);
	330	stw_p(&sysib.cpu_id, 0);
	331	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	332	} else if ((sel1 == 2) && (sel2 == 2)) {
	333	/* LPAR CPUs */
	334	struct sysib_222 sysib;
	335
	336	memset(&sysib, 0, sizeof(sysib));
	337	stw_p(&sysib.lpar_num, 0);
	338	sysib.lcpuc = 0;
	339	/* XXX change when SMP comes */
	340	stw_p(&sysib.total_cpus, 1);
	341	stw_p(&sysib.conf_cpus, 1);
	342	stw_p(&sysib.standby_cpus, 0);
	343	stw_p(&sysib.reserved_cpus, 0);
	344	ebcdic_put(sysib.name, "QEMU ", 8);
	345	stl_p(&sysib.caf, 1000);
	346	stw_p(&sysib.dedicated_cpus, 0);
	347	stw_p(&sysib.shared_cpus, 0);
	348	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	349	} else {
	350	cc = 3;
	351	}
	352	break;
defb0e31	353	}
defb0e31	354	case STSI_LEVEL_3:
71e47088 BS	355	{
	356	if ((sel1 == 2) && (sel2 == 2)) {
	357	/* VM CPUs */
	358	struct sysib_322 sysib;
	359
	360	memset(&sysib, 0, sizeof(sysib));
	361	sysib.count = 1;
	362	/* XXX change when SMP comes */
	363	stw_p(&sysib.vm[0].total_cpus, 1);
	364	stw_p(&sysib.vm[0].conf_cpus, 1);
	365	stw_p(&sysib.vm[0].standby_cpus, 0);
	366	stw_p(&sysib.vm[0].reserved_cpus, 0);
	367	ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
	368	stl_p(&sysib.vm[0].caf, 1000);
	369	ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
	370	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	371	} else {
	372	cc = 3;
	373	}
	374	break;
defb0e31	375	}
defb0e31 AG	376	case STSI_LEVEL_CURRENT:
	377	env->regs[0] = STSI_LEVEL_3;
	378	break;
	379	default:
	380	cc = 3;
	381	break;
	382	}
	383
	384	return cc;
	385	}
	386
defb0e31 AG	387	uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
	388	{
	389	int cc = 0;
	390
	391	HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
71e47088	392	__func__, order_code, r1, cpu_addr);
defb0e31	393
71e47088	394	/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
defb0e31 AG	395	as parameter (input). Status (output) is always R1. */
	396
	397	switch (order_code) {
	398	case SIGP_SET_ARCH:
	399	/* switch arch */
	400	break;
	401	case SIGP_SENSE:
	402	/* enumerate CPU status */
	403	if (cpu_addr) {
	404	/* XXX implement when SMP comes */
	405	return 3;
	406	}
	407	env->regs[r1] &= 0xffffffff00000000ULL;
	408	cc = 1;
	409	break;
71e47088	410	#if !defined(CONFIG_USER_ONLY)
1864b94a AG	411	case SIGP_RESTART:
	412	qemu_system_reset_request();
	413	cpu_loop_exit(env);
	414	break;
	415	case SIGP_STOP:
	416	qemu_system_shutdown_request();
	417	cpu_loop_exit(env);
	418	break;
	419	#endif
defb0e31 AG	420	default:
	421	/* unknown sigp */
	422	fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
	423	cc = 3;
	424	}
	425
	426	return cc;
	427	}
defb0e31	428	#endif