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Commit | Line | Data |
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10ec5117 | 1 | /* |
aea1e885 | 2 | * S/390 misc helper routines |
10ec5117 | 3 | * |
defb0e31 | 4 | * Copyright (c) 2009 Ulrich Hecht |
10ec5117 AG |
5 | * Copyright (c) 2009 Alexander Graf |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
70539e18 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
10ec5117 AG |
19 | */ |
20 | ||
3e457172 | 21 | #include "cpu.h" |
022c62cb | 22 | #include "exec/memory.h" |
1de7afc9 | 23 | #include "qemu/host-utils.h" |
2ef6175a | 24 | #include "exec/helper-proto.h" |
defb0e31 | 25 | #include <string.h> |
9c17d615 | 26 | #include "sysemu/kvm.h" |
1de7afc9 | 27 | #include "qemu/timer.h" |
df75a4e2 | 28 | #include "exec/address-spaces.h" |
af2be207 JK |
29 | #ifdef CONFIG_KVM |
30 | #include <linux/kvm.h> | |
31 | #endif | |
f08b6170 | 32 | #include "exec/cpu_ldst.h" |
10ec5117 | 33 | |
71e47088 | 34 | #if !defined(CONFIG_USER_ONLY) |
f0778475 | 35 | #include "sysemu/cpus.h" |
9c17d615 | 36 | #include "sysemu/sysemu.h" |
40fa5264 | 37 | #include "hw/s390x/ebcdic.h" |
df75a4e2 | 38 | #include "hw/s390x/ipl.h" |
10ec5117 | 39 | #endif |
d5a43964 | 40 | |
defb0e31 AG |
41 | /* #define DEBUG_HELPER */ |
42 | #ifdef DEBUG_HELPER | |
43 | #define HELPER_LOG(x...) qemu_log(x) | |
44 | #else | |
45 | #define HELPER_LOG(x...) | |
46 | #endif | |
47 | ||
b4e2bd35 RH |
48 | /* Raise an exception dynamically from a helper function. */ |
49 | void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, | |
50 | uintptr_t retaddr) | |
51 | { | |
27103424 | 52 | CPUState *cs = CPU(s390_env_get_cpu(env)); |
b4e2bd35 RH |
53 | int t; |
54 | ||
27103424 | 55 | cs->exception_index = EXCP_PGM; |
b4e2bd35 RH |
56 | env->int_pgm_code = excp; |
57 | ||
58 | /* Use the (ultimate) callers address to find the insn that trapped. */ | |
3f38f309 | 59 | cpu_restore_state(cs, retaddr); |
b4e2bd35 RH |
60 | |
61 | /* Advance past the insn. */ | |
62 | t = cpu_ldub_code(env, env->psw.addr); | |
63 | env->int_pgm_ilen = t = get_ilen(t); | |
64 | env->psw.addr += 2 * t; | |
65 | ||
5638d180 | 66 | cpu_loop_exit(cs); |
b4e2bd35 RH |
67 | } |
68 | ||
d5a103cd | 69 | /* Raise an exception statically from a TB. */ |
089f5c06 | 70 | void HELPER(exception)(CPUS390XState *env, uint32_t excp) |
defb0e31 | 71 | { |
27103424 AF |
72 | CPUState *cs = CPU(s390_env_get_cpu(env)); |
73 | ||
71e47088 | 74 | HELPER_LOG("%s: exception %d\n", __func__, excp); |
27103424 | 75 | cs->exception_index = excp; |
5638d180 | 76 | cpu_loop_exit(cs); |
defb0e31 AG |
77 | } |
78 | ||
defb0e31 | 79 | #ifndef CONFIG_USER_ONLY |
a158986d | 80 | |
d5a103cd | 81 | void program_interrupt(CPUS390XState *env, uint32_t code, int ilen) |
defb0e31 | 82 | { |
27103424 AF |
83 | S390CPU *cpu = s390_env_get_cpu(env); |
84 | ||
0d404541 RH |
85 | qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", |
86 | env->psw.addr); | |
defb0e31 AG |
87 | |
88 | if (kvm_enabled()) { | |
af2be207 | 89 | #ifdef CONFIG_KVM |
de13d216 CH |
90 | struct kvm_s390_irq irq = { |
91 | .type = KVM_S390_PROGRAM_INT, | |
92 | .u.pgm.code = code, | |
93 | }; | |
94 | ||
95 | kvm_s390_vcpu_interrupt(cpu, &irq); | |
af2be207 | 96 | #endif |
defb0e31 | 97 | } else { |
27103424 AF |
98 | CPUState *cs = CPU(cpu); |
99 | ||
defb0e31 | 100 | env->int_pgm_code = code; |
d5a103cd | 101 | env->int_pgm_ilen = ilen; |
27103424 | 102 | cs->exception_index = EXCP_PGM; |
5638d180 | 103 | cpu_loop_exit(cs); |
defb0e31 AG |
104 | } |
105 | } | |
106 | ||
defb0e31 | 107 | /* SCLP service call */ |
dc458df9 | 108 | uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2) |
defb0e31 | 109 | { |
6e252802 | 110 | int r = sclp_service_call(env, r1, r2); |
9abf567d CB |
111 | if (r < 0) { |
112 | program_interrupt(env, -r, 4); | |
113 | return 0; | |
114 | } | |
115 | return r; | |
defb0e31 AG |
116 | } |
117 | ||
268846ba | 118 | #ifndef CONFIG_USER_ONLY |
d8b30c83 CB |
119 | static int modified_clear_reset(S390CPU *cpu) |
120 | { | |
121 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
85ca3371 | 122 | CPUState *t; |
d8b30c83 CB |
123 | |
124 | pause_all_vcpus(); | |
125 | cpu_synchronize_all_states(); | |
85ca3371 DH |
126 | CPU_FOREACH(t) { |
127 | run_on_cpu(t, s390_do_cpu_full_reset, t); | |
128 | } | |
4cb88c3c | 129 | cmma_reset(cpu); |
d8b30c83 CB |
130 | io_subsystem_reset(); |
131 | scc->load_normal(CPU(cpu)); | |
132 | cpu_synchronize_all_post_reset(); | |
133 | resume_all_vcpus(); | |
134 | return 0; | |
135 | } | |
136 | ||
f0778475 CB |
137 | static int load_normal_reset(S390CPU *cpu) |
138 | { | |
139 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
85ca3371 | 140 | CPUState *t; |
f0778475 CB |
141 | |
142 | pause_all_vcpus(); | |
143 | cpu_synchronize_all_states(); | |
85ca3371 DH |
144 | CPU_FOREACH(t) { |
145 | run_on_cpu(t, s390_do_cpu_reset, t); | |
146 | } | |
4cb88c3c | 147 | cmma_reset(cpu); |
f0778475 CB |
148 | io_subsystem_reset(); |
149 | scc->initial_cpu_reset(CPU(cpu)); | |
150 | scc->load_normal(CPU(cpu)); | |
151 | cpu_synchronize_all_post_reset(); | |
152 | resume_all_vcpus(); | |
153 | return 0; | |
154 | } | |
155 | ||
df75a4e2 | 156 | #define DIAG_308_RC_OK 0x0001 |
268846ba ED |
157 | #define DIAG_308_RC_NO_CONF 0x0102 |
158 | #define DIAG_308_RC_INVALID 0x0402 | |
df75a4e2 | 159 | |
268846ba ED |
160 | void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3) |
161 | { | |
162 | uint64_t addr = env->regs[r1]; | |
163 | uint64_t subcode = env->regs[r3]; | |
df75a4e2 | 164 | IplParameterBlock *iplb; |
268846ba ED |
165 | |
166 | if (env->psw.mask & PSW_MASK_PSTATE) { | |
167 | program_interrupt(env, PGM_PRIVILEGED, ILEN_LATER_INC); | |
168 | return; | |
169 | } | |
170 | ||
171 | if ((subcode & ~0x0ffffULL) || (subcode > 6)) { | |
172 | program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); | |
173 | return; | |
174 | } | |
175 | ||
176 | switch (subcode) { | |
d8b30c83 CB |
177 | case 0: |
178 | modified_clear_reset(s390_env_get_cpu(env)); | |
179 | break; | |
f0778475 CB |
180 | case 1: |
181 | load_normal_reset(s390_env_get_cpu(env)); | |
182 | break; | |
268846ba ED |
183 | case 5: |
184 | if ((r1 & 1) || (addr & 0x0fffULL)) { | |
185 | program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); | |
186 | return; | |
187 | } | |
df75a4e2 FZ |
188 | if (!address_space_access_valid(&address_space_memory, addr, |
189 | sizeof(IplParameterBlock), false)) { | |
190 | program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC); | |
191 | return; | |
192 | } | |
193 | iplb = g_malloc0(sizeof(struct IplParameterBlock)); | |
194 | cpu_physical_memory_read(addr, iplb, sizeof(struct IplParameterBlock)); | |
195 | if (!s390_ipl_update_diag308(iplb)) { | |
196 | env->regs[r1 + 1] = DIAG_308_RC_OK; | |
197 | } else { | |
198 | env->regs[r1 + 1] = DIAG_308_RC_INVALID; | |
199 | } | |
200 | g_free(iplb); | |
268846ba ED |
201 | return; |
202 | case 6: | |
203 | if ((r1 & 1) || (addr & 0x0fffULL)) { | |
204 | program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); | |
205 | return; | |
206 | } | |
df75a4e2 FZ |
207 | if (!address_space_access_valid(&address_space_memory, addr, |
208 | sizeof(IplParameterBlock), true)) { | |
209 | program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC); | |
210 | return; | |
211 | } | |
212 | iplb = s390_ipl_get_iplb(); | |
213 | if (iplb) { | |
214 | cpu_physical_memory_write(addr, iplb, | |
215 | sizeof(struct IplParameterBlock)); | |
216 | env->regs[r1 + 1] = DIAG_308_RC_OK; | |
217 | } else { | |
218 | env->regs[r1 + 1] = DIAG_308_RC_NO_CONF; | |
219 | } | |
268846ba ED |
220 | return; |
221 | default: | |
222 | hw_error("Unhandled diag308 subcode %" PRIx64, subcode); | |
223 | break; | |
224 | } | |
225 | } | |
226 | #endif | |
227 | ||
defb0e31 | 228 | /* DIAG */ |
089f5c06 BS |
229 | uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem, |
230 | uint64_t code) | |
defb0e31 AG |
231 | { |
232 | uint64_t r; | |
233 | ||
234 | switch (num) { | |
235 | case 0x500: | |
236 | /* KVM hypercall */ | |
28e942f8 | 237 | r = s390_virtio_hypercall(env); |
defb0e31 AG |
238 | break; |
239 | case 0x44: | |
240 | /* yield */ | |
241 | r = 0; | |
242 | break; | |
243 | case 0x308: | |
244 | /* ipl */ | |
245 | r = 0; | |
246 | break; | |
247 | default: | |
248 | r = -1; | |
249 | break; | |
250 | } | |
251 | ||
252 | if (r) { | |
d5a103cd | 253 | program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC); |
defb0e31 AG |
254 | } |
255 | ||
256 | return r; | |
257 | } | |
258 | ||
defb0e31 | 259 | /* Set Prefix */ |
089f5c06 | 260 | void HELPER(spx)(CPUS390XState *env, uint64_t a1) |
defb0e31 | 261 | { |
31b030d4 | 262 | CPUState *cs = CPU(s390_env_get_cpu(env)); |
e805a0d3 | 263 | uint32_t prefix = a1 & 0x7fffe000; |
31b030d4 | 264 | |
e805a0d3 | 265 | env->psa = prefix; |
defb0e31 | 266 | qemu_log("prefix: %#x\n", prefix); |
31b030d4 AF |
267 | tlb_flush_page(cs, 0); |
268 | tlb_flush_page(cs, TARGET_PAGE_SIZE); | |
defb0e31 AG |
269 | } |
270 | ||
a4e3ad19 | 271 | static inline uint64_t clock_value(CPUS390XState *env) |
defb0e31 AG |
272 | { |
273 | uint64_t time; | |
274 | ||
275 | time = env->tod_offset + | |
bc72ad67 | 276 | time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - env->tod_basetime); |
defb0e31 AG |
277 | |
278 | return time; | |
279 | } | |
280 | ||
281 | /* Store Clock */ | |
434c91a5 | 282 | uint64_t HELPER(stck)(CPUS390XState *env) |
defb0e31 | 283 | { |
434c91a5 | 284 | return clock_value(env); |
defb0e31 AG |
285 | } |
286 | ||
defb0e31 | 287 | /* Set Clock Comparator */ |
dd3eb7b5 | 288 | void HELPER(sckc)(CPUS390XState *env, uint64_t time) |
defb0e31 | 289 | { |
defb0e31 AG |
290 | if (time == -1ULL) { |
291 | return; | |
292 | } | |
293 | ||
c941f074 AJ |
294 | /* difference between origins */ |
295 | time -= env->tod_offset; | |
296 | ||
defb0e31 | 297 | /* nanoseconds */ |
9cb32c44 | 298 | time = tod2time(time); |
defb0e31 | 299 | |
c941f074 | 300 | timer_mod(env->tod_timer, env->tod_basetime + time); |
defb0e31 AG |
301 | } |
302 | ||
303 | /* Store Clock Comparator */ | |
dd3eb7b5 | 304 | uint64_t HELPER(stckc)(CPUS390XState *env) |
defb0e31 AG |
305 | { |
306 | /* XXX implement */ | |
dd3eb7b5 | 307 | return 0; |
defb0e31 AG |
308 | } |
309 | ||
310 | /* Set CPU Timer */ | |
c4f0a863 | 311 | void HELPER(spt)(CPUS390XState *env, uint64_t time) |
defb0e31 | 312 | { |
defb0e31 AG |
313 | if (time == -1ULL) { |
314 | return; | |
315 | } | |
316 | ||
317 | /* nanoseconds */ | |
9cb32c44 | 318 | time = tod2time(time); |
defb0e31 | 319 | |
bc72ad67 | 320 | timer_mod(env->cpu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time); |
defb0e31 AG |
321 | } |
322 | ||
323 | /* Store CPU Timer */ | |
c4f0a863 | 324 | uint64_t HELPER(stpt)(CPUS390XState *env) |
defb0e31 AG |
325 | { |
326 | /* XXX implement */ | |
c4f0a863 | 327 | return 0; |
defb0e31 AG |
328 | } |
329 | ||
330 | /* Store System Information */ | |
d14b3e09 RH |
331 | uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, |
332 | uint64_t r0, uint64_t r1) | |
defb0e31 AG |
333 | { |
334 | int cc = 0; | |
335 | int sel1, sel2; | |
336 | ||
337 | if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 && | |
338 | ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) { | |
339 | /* valid function code, invalid reserved bits */ | |
340 | program_interrupt(env, PGM_SPECIFICATION, 2); | |
341 | } | |
342 | ||
343 | sel1 = r0 & STSI_R0_SEL1_MASK; | |
344 | sel2 = r1 & STSI_R1_SEL2_MASK; | |
345 | ||
346 | /* XXX: spec exception if sysib is not 4k-aligned */ | |
347 | ||
348 | switch (r0 & STSI_LEVEL_MASK) { | |
349 | case STSI_LEVEL_1: | |
350 | if ((sel1 == 1) && (sel2 == 1)) { | |
351 | /* Basic Machine Configuration */ | |
352 | struct sysib_111 sysib; | |
353 | ||
354 | memset(&sysib, 0, sizeof(sysib)); | |
355 | ebcdic_put(sysib.manuf, "QEMU ", 16); | |
356 | /* same as machine type number in STORE CPU ID */ | |
357 | ebcdic_put(sysib.type, "QEMU", 4); | |
358 | /* same as model number in STORE CPU ID */ | |
359 | ebcdic_put(sysib.model, "QEMU ", 16); | |
360 | ebcdic_put(sysib.sequence, "QEMU ", 16); | |
361 | ebcdic_put(sysib.plant, "QEMU", 4); | |
eb6282f2 | 362 | cpu_physical_memory_write(a0, &sysib, sizeof(sysib)); |
defb0e31 AG |
363 | } else if ((sel1 == 2) && (sel2 == 1)) { |
364 | /* Basic Machine CPU */ | |
365 | struct sysib_121 sysib; | |
366 | ||
367 | memset(&sysib, 0, sizeof(sysib)); | |
368 | /* XXX make different for different CPUs? */ | |
369 | ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16); | |
370 | ebcdic_put(sysib.plant, "QEMU", 4); | |
371 | stw_p(&sysib.cpu_addr, env->cpu_num); | |
eb6282f2 | 372 | cpu_physical_memory_write(a0, &sysib, sizeof(sysib)); |
defb0e31 AG |
373 | } else if ((sel1 == 2) && (sel2 == 2)) { |
374 | /* Basic Machine CPUs */ | |
375 | struct sysib_122 sysib; | |
376 | ||
377 | memset(&sysib, 0, sizeof(sysib)); | |
378 | stl_p(&sysib.capability, 0x443afc29); | |
379 | /* XXX change when SMP comes */ | |
380 | stw_p(&sysib.total_cpus, 1); | |
381 | stw_p(&sysib.active_cpus, 1); | |
382 | stw_p(&sysib.standby_cpus, 0); | |
383 | stw_p(&sysib.reserved_cpus, 0); | |
eb6282f2 | 384 | cpu_physical_memory_write(a0, &sysib, sizeof(sysib)); |
defb0e31 AG |
385 | } else { |
386 | cc = 3; | |
387 | } | |
388 | break; | |
389 | case STSI_LEVEL_2: | |
71e47088 BS |
390 | { |
391 | if ((sel1 == 2) && (sel2 == 1)) { | |
392 | /* LPAR CPU */ | |
393 | struct sysib_221 sysib; | |
394 | ||
395 | memset(&sysib, 0, sizeof(sysib)); | |
396 | /* XXX make different for different CPUs? */ | |
397 | ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16); | |
398 | ebcdic_put(sysib.plant, "QEMU", 4); | |
399 | stw_p(&sysib.cpu_addr, env->cpu_num); | |
400 | stw_p(&sysib.cpu_id, 0); | |
eb6282f2 | 401 | cpu_physical_memory_write(a0, &sysib, sizeof(sysib)); |
71e47088 BS |
402 | } else if ((sel1 == 2) && (sel2 == 2)) { |
403 | /* LPAR CPUs */ | |
404 | struct sysib_222 sysib; | |
405 | ||
406 | memset(&sysib, 0, sizeof(sysib)); | |
407 | stw_p(&sysib.lpar_num, 0); | |
408 | sysib.lcpuc = 0; | |
409 | /* XXX change when SMP comes */ | |
410 | stw_p(&sysib.total_cpus, 1); | |
411 | stw_p(&sysib.conf_cpus, 1); | |
412 | stw_p(&sysib.standby_cpus, 0); | |
413 | stw_p(&sysib.reserved_cpus, 0); | |
414 | ebcdic_put(sysib.name, "QEMU ", 8); | |
415 | stl_p(&sysib.caf, 1000); | |
416 | stw_p(&sysib.dedicated_cpus, 0); | |
417 | stw_p(&sysib.shared_cpus, 0); | |
eb6282f2 | 418 | cpu_physical_memory_write(a0, &sysib, sizeof(sysib)); |
71e47088 BS |
419 | } else { |
420 | cc = 3; | |
421 | } | |
422 | break; | |
defb0e31 | 423 | } |
defb0e31 | 424 | case STSI_LEVEL_3: |
71e47088 BS |
425 | { |
426 | if ((sel1 == 2) && (sel2 == 2)) { | |
427 | /* VM CPUs */ | |
428 | struct sysib_322 sysib; | |
429 | ||
430 | memset(&sysib, 0, sizeof(sysib)); | |
431 | sysib.count = 1; | |
432 | /* XXX change when SMP comes */ | |
433 | stw_p(&sysib.vm[0].total_cpus, 1); | |
434 | stw_p(&sysib.vm[0].conf_cpus, 1); | |
435 | stw_p(&sysib.vm[0].standby_cpus, 0); | |
436 | stw_p(&sysib.vm[0].reserved_cpus, 0); | |
437 | ebcdic_put(sysib.vm[0].name, "KVMguest", 8); | |
438 | stl_p(&sysib.vm[0].caf, 1000); | |
439 | ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16); | |
eb6282f2 | 440 | cpu_physical_memory_write(a0, &sysib, sizeof(sysib)); |
71e47088 BS |
441 | } else { |
442 | cc = 3; | |
443 | } | |
444 | break; | |
defb0e31 | 445 | } |
defb0e31 AG |
446 | case STSI_LEVEL_CURRENT: |
447 | env->regs[0] = STSI_LEVEL_3; | |
448 | break; | |
449 | default: | |
450 | cc = 3; | |
451 | break; | |
452 | } | |
453 | ||
454 | return cc; | |
455 | } | |
456 | ||
089f5c06 BS |
457 | uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, |
458 | uint64_t cpu_addr) | |
defb0e31 | 459 | { |
5172b780 | 460 | int cc = SIGP_CC_ORDER_CODE_ACCEPTED; |
defb0e31 AG |
461 | |
462 | HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n", | |
71e47088 | 463 | __func__, order_code, r1, cpu_addr); |
defb0e31 | 464 | |
71e47088 | 465 | /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register" |
defb0e31 AG |
466 | as parameter (input). Status (output) is always R1. */ |
467 | ||
468 | switch (order_code) { | |
469 | case SIGP_SET_ARCH: | |
470 | /* switch arch */ | |
471 | break; | |
472 | case SIGP_SENSE: | |
473 | /* enumerate CPU status */ | |
474 | if (cpu_addr) { | |
475 | /* XXX implement when SMP comes */ | |
476 | return 3; | |
477 | } | |
478 | env->regs[r1] &= 0xffffffff00000000ULL; | |
479 | cc = 1; | |
480 | break; | |
71e47088 | 481 | #if !defined(CONFIG_USER_ONLY) |
1864b94a AG |
482 | case SIGP_RESTART: |
483 | qemu_system_reset_request(); | |
5638d180 | 484 | cpu_loop_exit(CPU(s390_env_get_cpu(env))); |
1864b94a AG |
485 | break; |
486 | case SIGP_STOP: | |
487 | qemu_system_shutdown_request(); | |
5638d180 | 488 | cpu_loop_exit(CPU(s390_env_get_cpu(env))); |
1864b94a AG |
489 | break; |
490 | #endif | |
defb0e31 AG |
491 | default: |
492 | /* unknown sigp */ | |
493 | fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code); | |
5172b780 | 494 | cc = SIGP_CC_NOT_OPERATIONAL; |
defb0e31 AG |
495 | } |
496 | ||
497 | return cc; | |
498 | } | |
defb0e31 | 499 | #endif |