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target-s390x: Add missing tcg_temp_free_i64() in disas_b2()
[mirror_qemu.git] / target-s390x / translate.c
CommitLineData
10ec5117
AG		 1/*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
e023e832 5 * Copyright (c) 2010 Alexander Graf
10ec5117
AG		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
70539e18 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 19 */
e023e832
AG		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
26/* #define DEBUG_ILLEGAL_INSTRUCTIONS */
27/* #define DEBUG_INLINE_BRANCHES */
28#define S390X_DEBUG_DISAS
29/* #define S390X_DEBUG_DISAS_VERBOSE */
30
31#ifdef S390X_DEBUG_DISAS_VERBOSE
32# define LOG_DISAS(...) qemu_log(__VA_ARGS__)
33#else
34# define LOG_DISAS(...) do { } while (0)
35#endif
10ec5117
AG		 36
37#include "cpu.h"
38#include "exec-all.h"
39#include "disas.h"
40#include "tcg-op.h"
41#include "qemu-log.h"
42
e023e832
AG		 43/* global register indexes */
44static TCGv_ptr cpu_env;
45
46#include "gen-icount.h"
47#include "helpers.h"
48#define GEN_HELPER 1
49#include "helpers.h"
50
51typedef struct DisasContext DisasContext;
52struct DisasContext {
53 uint64_t pc;
54 int is_jmp;
55 enum cc_op cc_op;
56 struct TranslationBlock *tb;
57};
58
59#define DISAS_EXCP 4
60
61static void gen_op_calc_cc(DisasContext *s);
62
63#ifdef DEBUG_INLINE_BRANCHES
64static uint64_t inline_branch_hit[CC_OP_MAX];
65static uint64_t inline_branch_miss[CC_OP_MAX];
66#endif
67
68static inline void debug_insn(uint64_t insn)
69{
70 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
71}
72
73static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
74{
75 if (!(s->tb->flags & FLAG_MASK_64)) {
76 if (s->tb->flags & FLAG_MASK_32) {
77 return pc | 0x80000000;
78 }
79 }
80 return pc;
81}
82
9a78eead 83void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
10ec5117
AG		 84 int flags)
85{
86 int i;
e023e832 87
10ec5117 88 for (i = 0; i < 16; i++) {
e023e832 89 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
10ec5117
AG		 90 if ((i % 4) == 3) {
91 cpu_fprintf(f, "\n");
92 } else {
93 cpu_fprintf(f, " ");
94 }
95 }
e023e832 96
10ec5117 97 for (i = 0; i < 16; i++) {
bcec36ea 98 cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]);
10ec5117
AG		 99 if ((i % 4) == 3) {
100 cpu_fprintf(f, "\n");
101 } else {
102 cpu_fprintf(f, " ");
103 }
104 }
e023e832
AG		 105
106 cpu_fprintf(f, "\n");
107
108#ifndef CONFIG_USER_ONLY
109 for (i = 0; i < 16; i++) {
110 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
111 if ((i % 4) == 3) {
112 cpu_fprintf(f, "\n");
113 } else {
114 cpu_fprintf(f, " ");
115 }
116 }
117#endif
118
119 cpu_fprintf(f, "\n");
120
121 if (env->cc_op > 3) {
122 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
123 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
124 } else {
125 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
126 env->psw.mask, env->psw.addr, env->cc_op);
127 }
128
129#ifdef DEBUG_INLINE_BRANCHES
130 for (i = 0; i < CC_OP_MAX; i++) {
131 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
132 inline_branch_miss[i], inline_branch_hit[i]);
133 }
134#endif
10ec5117
AG		 135}
136
e023e832
AG		 137static TCGv_i64 psw_addr;
138static TCGv_i64 psw_mask;
139
140static TCGv_i32 cc_op;
141static TCGv_i64 cc_src;
142static TCGv_i64 cc_dst;
143static TCGv_i64 cc_vr;
144
145static char cpu_reg_names[10*3 + 6*4];
146static TCGv_i64 regs[16];
147
148static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
149
d5a43964
AG		 150void s390x_translate_init(void)
151{
e023e832
AG		 152 int i;
153 size_t cpu_reg_names_size = sizeof(cpu_reg_names);
154 char *p;
155
156 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
157 psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr),
158 "psw_addr");
159 psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask),
160 "psw_mask");
161
162 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
163 "cc_op");
164 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src),
165 "cc_src");
166 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst),
167 "cc_dst");
168 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr),
169 "cc_vr");
170
171 p = cpu_reg_names;
172 for (i = 0; i < 16; i++) {
173 snprintf(p, cpu_reg_names_size, "r%d", i);
174 regs[i] = tcg_global_mem_new(TCG_AREG0,
175 offsetof(CPUState, regs[i]), p);
176 p += (i < 10) ? 3 : 4;
177 cpu_reg_names_size -= (i < 10) ? 3 : 4;
178 }
d5a43964
AG		 179}
180
e023e832 181static inline TCGv_i64 load_reg(int reg)
10ec5117 182{
e023e832
AG		 183 TCGv_i64 r = tcg_temp_new_i64();
184 tcg_gen_mov_i64(r, regs[reg]);
185 return r;
10ec5117
AG		 186}
187
e023e832 188static inline TCGv_i64 load_freg(int reg)
10ec5117 189{
e023e832
AG		 190 TCGv_i64 r = tcg_temp_new_i64();
191 tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d));
192 return r;
10ec5117
AG		 193}
194
e023e832 195static inline TCGv_i32 load_freg32(int reg)
10ec5117 196{
e023e832
AG		 197 TCGv_i32 r = tcg_temp_new_i32();
198 tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
199 return r;
200}
201
202static inline TCGv_i32 load_reg32(int reg)
203{
204 TCGv_i32 r = tcg_temp_new_i32();
205 tcg_gen_trunc_i64_i32(r, regs[reg]);
206 return r;
207}
208
209static inline TCGv_i64 load_reg32_i64(int reg)
210{
211 TCGv_i64 r = tcg_temp_new_i64();
212 tcg_gen_ext32s_i64(r, regs[reg]);
213 return r;
214}
215
216static inline void store_reg(int reg, TCGv_i64 v)
217{
218 tcg_gen_mov_i64(regs[reg], v);
219}
220
221static inline void store_freg(int reg, TCGv_i64 v)
222{
223 tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d));
224}
225
226static inline void store_reg32(int reg, TCGv_i32 v)
227{
228#if HOST_LONG_BITS == 32
229 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
230#else
231 TCGv_i64 tmp = tcg_temp_new_i64();
232 tcg_gen_extu_i32_i64(tmp, v);
233 /* 32 bit register writes keep the upper half */
234 tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
235 tcg_temp_free_i64(tmp);
236#endif
237}
238
239static inline void store_reg32_i64(int reg, TCGv_i64 v)
240{
241 /* 32 bit register writes keep the upper half */
242#if HOST_LONG_BITS == 32
243 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v));
244#else
245 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
246#endif
247}
248
249static inline void store_reg16(int reg, TCGv_i32 v)
250{
251 TCGv_i64 tmp = tcg_temp_new_i64();
252 tcg_gen_extu_i32_i64(tmp, v);
253 /* 16 bit register writes keep the upper bytes */
254 tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16);
255 tcg_temp_free_i64(tmp);
256}
257
258static inline void store_reg8(int reg, TCGv_i64 v)
259{
260 /* 8 bit register writes keep the upper bytes */
261 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8);
262}
263
264static inline void store_freg32(int reg, TCGv_i32 v)
265{
266 tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
267}
268
269static inline void update_psw_addr(DisasContext *s)
270{
271 /* psw.addr */
272 tcg_gen_movi_i64(psw_addr, s->pc);
273}
274
275static inline void potential_page_fault(DisasContext *s)
276{
277#ifndef CONFIG_USER_ONLY
278 update_psw_addr(s);
279 gen_op_calc_cc(s);
280#endif
281}
282
283static inline uint64_t ld_code2(uint64_t pc)
284{
285 return (uint64_t)lduw_code(pc);
286}
287
288static inline uint64_t ld_code4(uint64_t pc)
289{
290 return (uint64_t)ldl_code(pc);
291}
292
293static inline uint64_t ld_code6(uint64_t pc)
294{
295 uint64_t opc;
296 opc = (uint64_t)lduw_code(pc) << 32;
297 opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
298 return opc;
299}
300
301static inline int get_mem_index(DisasContext *s)
302{
303 switch (s->tb->flags & FLAG_MASK_ASC) {
304 case PSW_ASC_PRIMARY >> 32:
305 return 0;
306 case PSW_ASC_SECONDARY >> 32:
307 return 1;
308 case PSW_ASC_HOME >> 32:
309 return 2;
310 default:
311 tcg_abort();
312 break;
313 }
314}
315
316static inline void gen_debug(DisasContext *s)
317{
318 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
319 update_psw_addr(s);
320 gen_op_calc_cc(s);
321 gen_helper_exception(tmp);
322 tcg_temp_free_i32(tmp);
323 s->is_jmp = DISAS_EXCP;
324}
325
326#ifdef CONFIG_USER_ONLY
327
328static void gen_illegal_opcode(DisasContext *s, int ilc)
329{
330 TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
331 update_psw_addr(s);
332 gen_op_calc_cc(s);
333 gen_helper_exception(tmp);
334 tcg_temp_free_i32(tmp);
335 s->is_jmp = DISAS_EXCP;
336}
337
338#else /* CONFIG_USER_ONLY */
339
340static void debug_print_inst(DisasContext *s, int ilc)
341{
342#ifdef DEBUG_ILLEGAL_INSTRUCTIONS
343 uint64_t inst = 0;
344
345 switch (ilc & 3) {
346 case 1:
347 inst = ld_code2(s->pc);
348 break;
349 case 2:
350 inst = ld_code4(s->pc);
351 break;
352 case 3:
353 inst = ld_code6(s->pc);
354 break;
355 }
356
357 fprintf(stderr, "Illegal instruction [%d at %016" PRIx64 "]: 0x%016"
358 PRIx64 "\n", ilc, s->pc, inst);
359#endif
360}
361
362static void gen_program_exception(DisasContext *s, int ilc, int code)
363{
364 TCGv_i32 tmp;
365
366 debug_print_inst(s, ilc);
367
368 /* remember what pgm exeption this was */
369 tmp = tcg_const_i32(code);
370 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code));
371 tcg_temp_free_i32(tmp);
372
373 tmp = tcg_const_i32(ilc);
374 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc));
375 tcg_temp_free_i32(tmp);
376
377 /* advance past instruction */
378 s->pc += (ilc * 2);
379 update_psw_addr(s);
380
381 /* save off cc */
382 gen_op_calc_cc(s);
383
384 /* trigger exception */
385 tmp = tcg_const_i32(EXCP_PGM);
386 gen_helper_exception(tmp);
387 tcg_temp_free_i32(tmp);
388
389 /* end TB here */
390 s->is_jmp = DISAS_EXCP;
391}
392
393
394static void gen_illegal_opcode(DisasContext *s, int ilc)
395{
396 gen_program_exception(s, ilc, PGM_SPECIFICATION);
397}
398
399static void gen_privileged_exception(DisasContext *s, int ilc)
400{
401 gen_program_exception(s, ilc, PGM_PRIVILEGED);
402}
403
404static void check_privileged(DisasContext *s, int ilc)
405{
406 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
407 gen_privileged_exception(s, ilc);
408 }
409}
410
411#endif /* CONFIG_USER_ONLY */
412
413static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
414{
415 TCGv_i64 tmp;
416
417 /* 31-bitify the immediate part; register contents are dealt with below */
418 if (!(s->tb->flags & FLAG_MASK_64)) {
419 d2 &= 0x7fffffffUL;
420 }
421
422 if (x2) {
423 if (d2) {
424 tmp = tcg_const_i64(d2);
425 tcg_gen_add_i64(tmp, tmp, regs[x2]);
426 } else {
427 tmp = load_reg(x2);
428 }
429 if (b2) {
430 tcg_gen_add_i64(tmp, tmp, regs[b2]);
431 }
432 } else if (b2) {
433 if (d2) {
434 tmp = tcg_const_i64(d2);
435 tcg_gen_add_i64(tmp, tmp, regs[b2]);
436 } else {
437 tmp = load_reg(b2);
438 }
439 } else {
440 tmp = tcg_const_i64(d2);
441 }
442
443 /* 31-bit mode mask if there are values loaded from registers */
444 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
445 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
446 }
447
448 return tmp;
449}
450
451static void gen_op_movi_cc(DisasContext *s, uint32_t val)
452{
453 s->cc_op = CC_OP_CONST0 + val;
454}
455
456static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
457{
458 tcg_gen_discard_i64(cc_src);
459 tcg_gen_mov_i64(cc_dst, dst);
460 tcg_gen_discard_i64(cc_vr);
461 s->cc_op = op;
462}
463
464static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
465{
466 tcg_gen_discard_i64(cc_src);
467 tcg_gen_extu_i32_i64(cc_dst, dst);
468 tcg_gen_discard_i64(cc_vr);
469 s->cc_op = op;
470}
471
472static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
473 TCGv_i64 dst)
474{
475 tcg_gen_mov_i64(cc_src, src);
476 tcg_gen_mov_i64(cc_dst, dst);
477 tcg_gen_discard_i64(cc_vr);
478 s->cc_op = op;
479}
480
481static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
482 TCGv_i32 dst)
483{
484 tcg_gen_extu_i32_i64(cc_src, src);
485 tcg_gen_extu_i32_i64(cc_dst, dst);
486 tcg_gen_discard_i64(cc_vr);
487 s->cc_op = op;
488}
489
490static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
491 TCGv_i64 dst, TCGv_i64 vr)
492{
493 tcg_gen_mov_i64(cc_src, src);
494 tcg_gen_mov_i64(cc_dst, dst);
495 tcg_gen_mov_i64(cc_vr, vr);
496 s->cc_op = op;
497}
498
499static void gen_op_update3_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
500 TCGv_i32 dst, TCGv_i32 vr)
501{
502 tcg_gen_extu_i32_i64(cc_src, src);
503 tcg_gen_extu_i32_i64(cc_dst, dst);
504 tcg_gen_extu_i32_i64(cc_vr, vr);
505 s->cc_op = op;
506}
507
508static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
509{
510 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
511}
512
513static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
514{
515 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
516}
517
518static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
519 enum cc_op cond)
520{
521 gen_op_update2_cc_i32(s, cond, v1, v2);
522}
523
524static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
525 enum cc_op cond)
526{
527 gen_op_update2_cc_i64(s, cond, v1, v2);
528}
529
530static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
531{
532 cmp_32(s, v1, v2, CC_OP_LTGT_32);
533}
534
535static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
536{
537 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
538}
539
540static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
541{
542 /* XXX optimize for the constant? put it in s? */
543 TCGv_i32 tmp = tcg_const_i32(v2);
544 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
545 tcg_temp_free_i32(tmp);
546}
547
548static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
549{
550 TCGv_i32 tmp = tcg_const_i32(v2);
551 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
552 tcg_temp_free_i32(tmp);
553}
554
555static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
556{
557 cmp_64(s, v1, v2, CC_OP_LTGT_64);
558}
559
560static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
561{
562 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
563}
564
565static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
566{
567 TCGv_i64 tmp = tcg_const_i64(v2);
568 cmp_s64(s, v1, tmp);
569 tcg_temp_free_i64(tmp);
570}
571
572static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
573{
574 TCGv_i64 tmp = tcg_const_i64(v2);
575 cmp_u64(s, v1, tmp);
576 tcg_temp_free_i64(tmp);
577}
578
579static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
580{
581 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
582}
583
584static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
585{
586 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
587}
588
589static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
590{
591 gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
592}
593
594static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
595 TCGv_i64 vr)
596{
597 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, v1, v2, vr);
598}
599
600static void set_cc_sub64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
601{
602 gen_op_update3_cc_i64(s, CC_OP_SUB_64, v1, v2, vr);
603}
604
605static void set_cc_subu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
606 TCGv_i64 vr)
607{
608 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, v1, v2, vr);
609}
610
611static void set_cc_abs64(DisasContext *s, TCGv_i64 v1)
612{
613 gen_op_update1_cc_i64(s, CC_OP_ABS_64, v1);
614}
615
616static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1)
617{
618 gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1);
619}
620
621static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
622{
623 gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr);
624}
625
626static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
627 TCGv_i32 vr)
628{
629 gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr);
630}
631
632static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
633{
634 gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr);
635}
636
637static void set_cc_subu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
638 TCGv_i32 vr)
639{
640 gen_op_update3_cc_i32(s, CC_OP_SUBU_32, v1, v2, vr);
641}
642
643static void set_cc_abs32(DisasContext *s, TCGv_i32 v1)
644{
645 gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1);
646}
647
648static void set_cc_nabs32(DisasContext *s, TCGv_i32 v1)
649{
650 gen_op_update1_cc_i32(s, CC_OP_NABS_32, v1);
651}
652
653static void set_cc_comp32(DisasContext *s, TCGv_i32 v1)
654{
655 gen_op_update1_cc_i32(s, CC_OP_COMP_32, v1);
656}
657
658static void set_cc_comp64(DisasContext *s, TCGv_i64 v1)
659{
660 gen_op_update1_cc_i64(s, CC_OP_COMP_64, v1);
661}
662
663static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
664{
665 gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2);
666}
667
668static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
669{
670 tcg_gen_extu_i32_i64(cc_src, v1);
671 tcg_gen_mov_i64(cc_dst, v2);
672 tcg_gen_discard_i64(cc_vr);
673 s->cc_op = CC_OP_LTGT_F32;
674}
675
676static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
677{
678 gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
679}
680
681static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
682{
683 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
684}
685
686/* CC value is in env->cc_op */
687static inline void set_cc_static(DisasContext *s)
688{
689 tcg_gen_discard_i64(cc_src);
690 tcg_gen_discard_i64(cc_dst);
691 tcg_gen_discard_i64(cc_vr);
692 s->cc_op = CC_OP_STATIC;
693}
694
695static inline void gen_op_set_cc_op(DisasContext *s)
696{
697 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
698 tcg_gen_movi_i32(cc_op, s->cc_op);
699 }
700}
701
702static inline void gen_update_cc_op(DisasContext *s)
703{
704 gen_op_set_cc_op(s);
705}
706
707/* calculates cc into cc_op */
708static void gen_op_calc_cc(DisasContext *s)
709{
710 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
711 TCGv_i64 dummy = tcg_const_i64(0);
712
713 switch (s->cc_op) {
714 case CC_OP_CONST0:
715 case CC_OP_CONST1:
716 case CC_OP_CONST2:
717 case CC_OP_CONST3:
718 /* s->cc_op is the cc value */
719 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
720 break;
721 case CC_OP_STATIC:
722 /* env->cc_op already is the cc value */
723 break;
724 case CC_OP_NZ:
725 case CC_OP_ABS_64:
726 case CC_OP_NABS_64:
727 case CC_OP_ABS_32:
728 case CC_OP_NABS_32:
729 case CC_OP_LTGT0_32:
730 case CC_OP_LTGT0_64:
731 case CC_OP_COMP_32:
732 case CC_OP_COMP_64:
733 case CC_OP_NZ_F32:
734 case CC_OP_NZ_F64:
735 /* 1 argument */
736 gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
737 break;
738 case CC_OP_ICM:
739 case CC_OP_LTGT_32:
740 case CC_OP_LTGT_64:
741 case CC_OP_LTUGTU_32:
742 case CC_OP_LTUGTU_64:
743 case CC_OP_TM_32:
744 case CC_OP_TM_64:
745 case CC_OP_LTGT_F32:
746 case CC_OP_LTGT_F64:
747 case CC_OP_SLAG:
748 /* 2 arguments */
749 gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
750 break;
751 case CC_OP_ADD_64:
752 case CC_OP_ADDU_64:
753 case CC_OP_SUB_64:
754 case CC_OP_SUBU_64:
755 case CC_OP_ADD_32:
756 case CC_OP_ADDU_32:
757 case CC_OP_SUB_32:
758 case CC_OP_SUBU_32:
759 /* 3 arguments */
760 gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
761 break;
762 case CC_OP_DYNAMIC:
763 /* unknown operation - assume 3 arguments and cc_op in env */
764 gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
765 break;
766 default:
767 tcg_abort();
768 }
769
770 tcg_temp_free_i32(local_cc_op);
771
772 /* We now have cc in cc_op as constant */
773 set_cc_static(s);
774}
775
776static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
777{
778 debug_insn(insn);
779
780 *r1 = (insn >> 4) & 0xf;
781 *r2 = insn & 0xf;
782}
783
784static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
785 int *x2, int *b2, int *d2)
786{
787 debug_insn(insn);
788
789 *r1 = (insn >> 20) & 0xf;
790 *x2 = (insn >> 16) & 0xf;
791 *b2 = (insn >> 12) & 0xf;
792 *d2 = insn & 0xfff;
793
794 return get_address(s, *x2, *b2, *d2);
795}
796
797static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
798 int *b2, int *d2)
799{
800 debug_insn(insn);
801
802 *r1 = (insn >> 20) & 0xf;
803 /* aka m3 */
804 *r3 = (insn >> 16) & 0xf;
805 *b2 = (insn >> 12) & 0xf;
806 *d2 = insn & 0xfff;
807}
808
809static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
810 int *b1, int *d1)
811{
812 debug_insn(insn);
813
814 *i2 = (insn >> 16) & 0xff;
815 *b1 = (insn >> 12) & 0xf;
816 *d1 = insn & 0xfff;
817
818 return get_address(s, 0, *b1, *d1);
819}
820
821static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
822{
823 TranslationBlock *tb;
824
825 gen_update_cc_op(s);
826
827 tb = s->tb;
828 /* NOTE: we handle the case where the TB spans two pages here */
829 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
830 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
831 /* jump to same page: we can use a direct jump */
832 tcg_gen_goto_tb(tb_num);
833 tcg_gen_movi_i64(psw_addr, pc);
834 tcg_gen_exit_tb((long)tb + tb_num);
835 } else {
836 /* jump to another page: currently not optimized */
837 tcg_gen_movi_i64(psw_addr, pc);
838 tcg_gen_exit_tb(0);
839 }
840}
841
842static inline void account_noninline_branch(DisasContext *s, int cc_op)
843{
844#ifdef DEBUG_INLINE_BRANCHES
845 inline_branch_miss[cc_op]++;
846#endif
847}
848
849static inline void account_inline_branch(DisasContext *s)
850{
851#ifdef DEBUG_INLINE_BRANCHES
852 inline_branch_hit[s->cc_op]++;
853#endif
854}
855
856static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
857{
858 TCGv_i32 tmp, tmp2, r;
859 TCGv_i64 tmp64;
860 int old_cc_op;
861
862 switch (s->cc_op) {
863 case CC_OP_LTGT0_32:
864 tmp = tcg_temp_new_i32();
865 tcg_gen_trunc_i64_i32(tmp, cc_dst);
866 switch (mask) {
867 case 0x8 | 0x4: /* dst <= 0 */
868 tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip);
869 break;
870 case 0x8 | 0x2: /* dst >= 0 */
871 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip);
872 break;
873 case 0x8: /* dst == 0 */
874 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
875 break;
876 case 0x7: /* dst != 0 */
877 case 0x6: /* dst != 0 */
878 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
879 break;
880 case 0x4: /* dst < 0 */
881 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip);
882 break;
883 case 0x2: /* dst > 0 */
884 tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip);
885 break;
886 default:
887 tcg_temp_free_i32(tmp);
888 goto do_dynamic;
889 }
890 account_inline_branch(s);
891 tcg_temp_free_i32(tmp);
892 break;
893 case CC_OP_LTGT0_64:
894 switch (mask) {
895 case 0x8 | 0x4: /* dst <= 0 */
896 tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip);
897 break;
898 case 0x8 | 0x2: /* dst >= 0 */
899 tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip);
900 break;
901 case 0x8: /* dst == 0 */
902 tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
903 break;
904 case 0x7: /* dst != 0 */
905 case 0x6: /* dst != 0 */
906 tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
907 break;
908 case 0x4: /* dst < 0 */
909 tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip);
910 break;
911 case 0x2: /* dst > 0 */
912 tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip);
913 break;
914 default:
915 goto do_dynamic;
916 }
917 account_inline_branch(s);
918 break;
919 case CC_OP_LTGT_32:
920 tmp = tcg_temp_new_i32();
921 tmp2 = tcg_temp_new_i32();
922 tcg_gen_trunc_i64_i32(tmp, cc_src);
923 tcg_gen_trunc_i64_i32(tmp2, cc_dst);
924 switch (mask) {
925 case 0x8 | 0x4: /* src <= dst */
926 tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip);
927 break;
928 case 0x8 | 0x2: /* src >= dst */
929 tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip);
930 break;
931 case 0x8: /* src == dst */
932 tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
933 break;
934 case 0x7: /* src != dst */
935 case 0x6: /* src != dst */
936 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
937 break;
938 case 0x4: /* src < dst */
939 tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip);
940 break;
941 case 0x2: /* src > dst */
942 tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip);
943 break;
944 default:
945 tcg_temp_free_i32(tmp);
946 tcg_temp_free_i32(tmp2);
947 goto do_dynamic;
948 }
949 account_inline_branch(s);
950 tcg_temp_free_i32(tmp);
951 tcg_temp_free_i32(tmp2);
952 break;
953 case CC_OP_LTGT_64:
954 switch (mask) {
955 case 0x8 | 0x4: /* src <= dst */
956 tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip);
957 break;
958 case 0x8 | 0x2: /* src >= dst */
959 tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip);
960 break;
961 case 0x8: /* src == dst */
962 tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
963 break;
964 case 0x7: /* src != dst */
965 case 0x6: /* src != dst */
966 tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
967 break;
968 case 0x4: /* src < dst */
969 tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip);
970 break;
971 case 0x2: /* src > dst */
972 tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip);
973 break;
974 default:
975 goto do_dynamic;
976 }
977 account_inline_branch(s);
978 break;
979 case CC_OP_LTUGTU_32:
980 tmp = tcg_temp_new_i32();
981 tmp2 = tcg_temp_new_i32();
982 tcg_gen_trunc_i64_i32(tmp, cc_src);
983 tcg_gen_trunc_i64_i32(tmp2, cc_dst);
984 switch (mask) {
985 case 0x8 | 0x4: /* src <= dst */
986 tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip);
987 break;
988 case 0x8 | 0x2: /* src >= dst */
989 tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip);
990 break;
991 case 0x8: /* src == dst */
992 tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
993 break;
994 case 0x7: /* src != dst */
995 case 0x6: /* src != dst */
996 tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
997 break;
998 case 0x4: /* src < dst */
999 tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip);
1000 break;
1001 case 0x2: /* src > dst */
1002 tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip);
1003 break;
1004 default:
1005 tcg_temp_free_i32(tmp);
1006 tcg_temp_free_i32(tmp2);
1007 goto do_dynamic;
1008 }
1009 account_inline_branch(s);
1010 tcg_temp_free_i32(tmp);
1011 tcg_temp_free_i32(tmp2);
1012 break;
1013 case CC_OP_LTUGTU_64:
1014 switch (mask) {
1015 case 0x8 | 0x4: /* src <= dst */
1016 tcg_gen_brcond_i64(TCG_COND_GTU, cc_src, cc_dst, skip);
1017 break;
1018 case 0x8 | 0x2: /* src >= dst */
1019 tcg_gen_brcond_i64(TCG_COND_LTU, cc_src, cc_dst, skip);
1020 break;
1021 case 0x8: /* src == dst */
1022 tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
1023 break;
1024 case 0x7: /* src != dst */
1025 case 0x6: /* src != dst */
1026 tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
1027 break;
1028 case 0x4: /* src < dst */
1029 tcg_gen_brcond_i64(TCG_COND_GEU, cc_src, cc_dst, skip);
1030 break;
1031 case 0x2: /* src > dst */
1032 tcg_gen_brcond_i64(TCG_COND_LEU, cc_src, cc_dst, skip);
1033 break;
1034 default:
1035 goto do_dynamic;
1036 }
1037 account_inline_branch(s);
1038 break;
1039 case CC_OP_NZ:
1040 switch (mask) {
1041 /* dst == 0 || dst != 0 */
1042 case 0x8 | 0x4:
1043 case 0x8 | 0x4 | 0x2:
1044 case 0x8 | 0x4 | 0x2 | 0x1:
1045 case 0x8 | 0x4 | 0x1:
1046 break;
1047 /* dst == 0 */
1048 case 0x8:
1049 case 0x8 | 0x2:
1050 case 0x8 | 0x2 | 0x1:
1051 case 0x8 | 0x1:
1052 tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
1053 break;
1054 /* dst != 0 */
1055 case 0x4:
1056 case 0x4 | 0x2:
1057 case 0x4 | 0x2 | 0x1:
1058 case 0x4 | 0x1:
1059 tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
1060 break;
1061 default:
1062 goto do_dynamic;
1063 }
1064 account_inline_branch(s);
1065 break;
1066 case CC_OP_TM_32:
1067 tmp = tcg_temp_new_i32();
1068 tmp2 = tcg_temp_new_i32();
1069
1070 tcg_gen_trunc_i64_i32(tmp, cc_src);
1071 tcg_gen_trunc_i64_i32(tmp2, cc_dst);
1072 tcg_gen_and_i32(tmp, tmp, tmp2);
1073 switch (mask) {
1074 case 0x8: /* val & mask == 0 */
1075 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
1076 break;
1077 case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
1079 break;
1080 default:
1081 goto do_dynamic;
1082 }
1083 tcg_temp_free_i32(tmp);
1084 account_inline_branch(s);
1085 break;
1086 case CC_OP_TM_64:
1087 tmp64 = tcg_temp_new_i64();
1088
1089 tcg_gen_and_i64(tmp64, cc_src, cc_dst);
1090 switch (mask) {
1091 case 0x8: /* val & mask == 0 */
1092 tcg_gen_brcondi_i64(TCG_COND_NE, tmp64, 0, skip);
1093 break;
1094 case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1095 tcg_gen_brcondi_i64(TCG_COND_EQ, tmp64, 0, skip);
1096 break;
1097 default:
a825aefb 1098 tcg_temp_free_i64(tmp64);
e023e832
AG		 1099 goto do_dynamic;
1100 }
1101 tcg_temp_free_i64(tmp64);
1102 account_inline_branch(s);
1103 break;
1104 case CC_OP_ICM:
1105 switch (mask) {
1106 case 0x8: /* val == 0 */
1107 tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
1108 break;
1109 case 0x4 | 0x2 | 0x1: /* val != 0 */
1110 case 0x4 | 0x2: /* val != 0 */
1111 tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
1112 break;
1113 default:
1114 goto do_dynamic;
1115 }
1116 account_inline_branch(s);
1117 break;
1118 case CC_OP_STATIC:
1119 old_cc_op = s->cc_op;
1120 goto do_dynamic_nocccalc;
1121 case CC_OP_DYNAMIC:
1122 default:
1123do_dynamic:
1124 old_cc_op = s->cc_op;
1125 /* calculate cc value */
1126 gen_op_calc_cc(s);
1127
1128do_dynamic_nocccalc:
1129 /* jump based on cc */
1130 account_noninline_branch(s, old_cc_op);
1131
1132 switch (mask) {
1133 case 0x8 | 0x4 | 0x2 | 0x1:
1134 /* always true */
1135 break;
1136 case 0x8 | 0x4 | 0x2: /* cc != 3 */
1137 tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 3, skip);
1138 break;
1139 case 0x8 | 0x4 | 0x1: /* cc != 2 */
1140 tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 2, skip);
1141 break;
1142 case 0x8 | 0x2 | 0x1: /* cc != 1 */
1143 tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 1, skip);
1144 break;
1145 case 0x8 | 0x2: /* cc == 0 || cc == 2 */
1146 tmp = tcg_temp_new_i32();
1147 tcg_gen_andi_i32(tmp, cc_op, 1);
1148 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
1149 tcg_temp_free_i32(tmp);
1150 break;
1151 case 0x8 | 0x4: /* cc < 2 */
1152 tcg_gen_brcondi_i32(TCG_COND_GEU, cc_op, 2, skip);
1153 break;
1154 case 0x8: /* cc == 0 */
1155 tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 0, skip);
1156 break;
1157 case 0x4 | 0x2 | 0x1: /* cc != 0 */
1158 tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 0, skip);
1159 break;
1160 case 0x4 | 0x1: /* cc == 1 || cc == 3 */
1161 tmp = tcg_temp_new_i32();
1162 tcg_gen_andi_i32(tmp, cc_op, 1);
1163 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
1164 tcg_temp_free_i32(tmp);
1165 break;
1166 case 0x4: /* cc == 1 */
1167 tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 1, skip);
1168 break;
1169 case 0x2 | 0x1: /* cc > 1 */
1170 tcg_gen_brcondi_i32(TCG_COND_LEU, cc_op, 1, skip);
1171 break;
1172 case 0x2: /* cc == 2 */
1173 tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 2, skip);
1174 break;
1175 case 0x1: /* cc == 3 */
1176 tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 3, skip);
1177 break;
1178 default: /* cc is masked by something else */
1179 tmp = tcg_const_i32(3);
1180 /* 3 - cc */
1181 tcg_gen_sub_i32(tmp, tmp, cc_op);
1182 tmp2 = tcg_const_i32(1);
1183 /* 1 << (3 - cc) */
1184 tcg_gen_shl_i32(tmp2, tmp2, tmp);
1185 r = tcg_const_i32(mask);
1186 /* mask & (1 << (3 - cc)) */
1187 tcg_gen_and_i32(r, r, tmp2);
1188 tcg_temp_free_i32(tmp);
1189 tcg_temp_free_i32(tmp2);
1190
1191 tcg_gen_brcondi_i32(TCG_COND_EQ, r, 0, skip);
1192 tcg_temp_free_i32(r);
1193 break;
1194 }
1195 break;
1196 }
1197}
1198
1199static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target,
1200 uint64_t offset)
1201{
1202 int skip;
1203
1204 if (mask == 0xf) {
1205 /* unconditional */
1206 tcg_gen_mov_i64(psw_addr, target);
1207 tcg_gen_exit_tb(0);
1208 } else if (mask == 0) {
1209 /* ignore cc and never match */
1210 gen_goto_tb(s, 0, offset + 2);
1211 } else {
1212 TCGv_i64 new_addr = tcg_temp_local_new_i64();
1213
1214 tcg_gen_mov_i64(new_addr, target);
1215 skip = gen_new_label();
1216 gen_jcc(s, mask, skip);
1217 tcg_gen_mov_i64(psw_addr, new_addr);
1218 tcg_temp_free_i64(new_addr);
1219 tcg_gen_exit_tb(0);
1220 gen_set_label(skip);
1221 tcg_temp_free_i64(new_addr);
1222 gen_goto_tb(s, 1, offset + 2);
1223 }
1224}
1225
1226static void gen_brc(uint32_t mask, DisasContext *s, int32_t offset)
1227{
1228 int skip;
1229
1230 if (mask == 0xf) {
1231 /* unconditional */
1232 gen_goto_tb(s, 0, s->pc + offset);
1233 } else if (mask == 0) {
1234 /* ignore cc and never match */
1235 gen_goto_tb(s, 0, s->pc + 4);
1236 } else {
1237 skip = gen_new_label();
1238 gen_jcc(s, mask, skip);
1239 gen_goto_tb(s, 0, s->pc + offset);
1240 gen_set_label(skip);
1241 gen_goto_tb(s, 1, s->pc + 4);
1242 }
1243 s->is_jmp = DISAS_TB_JUMP;
1244}
1245
1246static void gen_op_mvc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
1247{
1248 TCGv_i64 tmp, tmp2;
1249 int i;
1250 int l_memset = gen_new_label();
1251 int l_out = gen_new_label();
1252 TCGv_i64 dest = tcg_temp_local_new_i64();
1253 TCGv_i64 src = tcg_temp_local_new_i64();
1254 TCGv_i32 vl;
1255
1256 /* Find out if we should use the inline version of mvc */
1257 switch (l) {
1258 case 0:
1259 case 1:
1260 case 2:
1261 case 3:
1262 case 4:
1263 case 5:
1264 case 6:
1265 case 7:
1266 case 11:
1267 case 15:
1268 /* use inline */
1269 break;
1270 default:
1271 /* Fall back to helper */
1272 vl = tcg_const_i32(l);
1273 potential_page_fault(s);
1274 gen_helper_mvc(vl, s1, s2);
1275 tcg_temp_free_i32(vl);
1276 return;
1277 }
1278
1279 tcg_gen_mov_i64(dest, s1);
1280 tcg_gen_mov_i64(src, s2);
1281
1282 if (!(s->tb->flags & FLAG_MASK_64)) {
1283 /* XXX what if we overflow while moving? */
1284 tcg_gen_andi_i64(dest, dest, 0x7fffffffUL);
1285 tcg_gen_andi_i64(src, src, 0x7fffffffUL);
1286 }
1287
1288 tmp = tcg_temp_new_i64();
1289 tcg_gen_addi_i64(tmp, src, 1);
1290 tcg_gen_brcond_i64(TCG_COND_EQ, dest, tmp, l_memset);
1291 tcg_temp_free_i64(tmp);
1292
1293 switch (l) {
1294 case 0:
1295 tmp = tcg_temp_new_i64();
1296
1297 tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1298 tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1299
1300 tcg_temp_free_i64(tmp);
1301 break;
1302 case 1:
1303 tmp = tcg_temp_new_i64();
1304
1305 tcg_gen_qemu_ld16u(tmp, src, get_mem_index(s));
1306 tcg_gen_qemu_st16(tmp, dest, get_mem_index(s));
1307
1308 tcg_temp_free_i64(tmp);
1309 break;
1310 case 3:
1311 tmp = tcg_temp_new_i64();
1312
1313 tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
1314 tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
1315
1316 tcg_temp_free_i64(tmp);
1317 break;
1318 case 4:
1319 tmp = tcg_temp_new_i64();
1320 tmp2 = tcg_temp_new_i64();
1321
1322 tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
1323 tcg_gen_addi_i64(src, src, 4);
1324 tcg_gen_qemu_ld8u(tmp2, src, get_mem_index(s));
1325 tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
1326 tcg_gen_addi_i64(dest, dest, 4);
1327 tcg_gen_qemu_st8(tmp2, dest, get_mem_index(s));
1328
1329 tcg_temp_free_i64(tmp);
1330 tcg_temp_free_i64(tmp2);
1331 break;
1332 case 7:
1333 tmp = tcg_temp_new_i64();
1334
1335 tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
1336 tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1337
1338 tcg_temp_free_i64(tmp);
1339 break;
1340 default:
1341 /* The inline version can become too big for too uneven numbers, only
1342 use it on known good lengths */
1343 tmp = tcg_temp_new_i64();
1344 tmp2 = tcg_const_i64(8);
1345 for (i = 0; (i + 7) <= l; i += 8) {
1346 tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
1347 tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1348
1349 tcg_gen_add_i64(src, src, tmp2);
1350 tcg_gen_add_i64(dest, dest, tmp2);
1351 }
1352
1353 tcg_temp_free_i64(tmp2);
1354 tmp2 = tcg_const_i64(1);
1355
1356 for (; i <= l; i++) {
1357 tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1358 tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1359
1360 tcg_gen_add_i64(src, src, tmp2);
1361 tcg_gen_add_i64(dest, dest, tmp2);
1362 }
1363
1364 tcg_temp_free_i64(tmp2);
1365 tcg_temp_free_i64(tmp);
1366 break;
1367 }
1368
1369 tcg_gen_br(l_out);
1370
1371 gen_set_label(l_memset);
1372 /* memset case (dest == (src + 1)) */
1373
1374 tmp = tcg_temp_new_i64();
1375 tmp2 = tcg_temp_new_i64();
1376 /* fill tmp with the byte */
1377 tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1378 tcg_gen_shli_i64(tmp2, tmp, 8);
1379 tcg_gen_or_i64(tmp, tmp, tmp2);
1380 tcg_gen_shli_i64(tmp2, tmp, 16);
1381 tcg_gen_or_i64(tmp, tmp, tmp2);
1382 tcg_gen_shli_i64(tmp2, tmp, 32);
1383 tcg_gen_or_i64(tmp, tmp, tmp2);
1384 tcg_temp_free_i64(tmp2);
1385
1386 tmp2 = tcg_const_i64(8);
1387
1388 for (i = 0; (i + 7) <= l; i += 8) {
1389 tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1390 tcg_gen_addi_i64(dest, dest, 8);
1391 }
1392
1393 tcg_temp_free_i64(tmp2);
1394 tmp2 = tcg_const_i64(1);
1395
1396 for (; i <= l; i++) {
1397 tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1398 tcg_gen_addi_i64(dest, dest, 1);
1399 }
1400
1401 tcg_temp_free_i64(tmp2);
1402 tcg_temp_free_i64(tmp);
1403
1404 gen_set_label(l_out);
1405
1406 tcg_temp_free(dest);
1407 tcg_temp_free(src);
1408}
1409
1410static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
1411{
1412 TCGv_i64 tmp;
1413 TCGv_i64 tmp2;
1414 TCGv_i32 vl;
1415
1416 /* check for simple 32bit or 64bit match */
1417 switch (l) {
1418 case 0:
1419 tmp = tcg_temp_new_i64();
1420 tmp2 = tcg_temp_new_i64();
1421
1422 tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s));
1423 tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s));
1424 cmp_u64(s, tmp, tmp2);
1425
1426 tcg_temp_free_i64(tmp);
1427 tcg_temp_free_i64(tmp2);
1428 return;
1429 case 1:
1430 tmp = tcg_temp_new_i64();
1431 tmp2 = tcg_temp_new_i64();
1432
1433 tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s));
1434 tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s));
1435 cmp_u64(s, tmp, tmp2);
1436
1437 tcg_temp_free_i64(tmp);
1438 tcg_temp_free_i64(tmp2);
1439 return;
1440 case 3:
1441 tmp = tcg_temp_new_i64();
1442 tmp2 = tcg_temp_new_i64();
1443
1444 tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s));
1445 tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s));
1446 cmp_u64(s, tmp, tmp2);
1447
1448 tcg_temp_free_i64(tmp);
1449 tcg_temp_free_i64(tmp2);
1450 return;
1451 case 7:
1452 tmp = tcg_temp_new_i64();
1453 tmp2 = tcg_temp_new_i64();
1454
1455 tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s));
1456 tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s));
1457 cmp_u64(s, tmp, tmp2);
1458
1459 tcg_temp_free_i64(tmp);
1460 tcg_temp_free_i64(tmp2);
1461 return;
1462 }
1463
1464 potential_page_fault(s);
1465 vl = tcg_const_i32(l);
1466 gen_helper_clc(cc_op, vl, s1, s2);
1467 tcg_temp_free_i32(vl);
1468 set_cc_static(s);
1469}
1470
1471static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
1472{
1473 TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;
1474 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1475
1476 LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1477 op, r1, x2, b2, d2);
1478 addr = get_address(s, x2, b2, d2);
1479 switch (op) {
1480 case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
1481 case 0x4: /* lg r1,d2(x2,b2) */
1482 tcg_gen_qemu_ld64(regs[r1], addr, get_mem_index(s));
1483 if (op == 0x2) {
1484 set_cc_s64(s, regs[r1]);
1485 }
1486 break;
1487 case 0x12: /* LT R1,D2(X2,B2) [RXY] */
1488 tmp2 = tcg_temp_new_i64();
1489 tmp32_1 = tcg_temp_new_i32();
1490 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1491 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1492 store_reg32(r1, tmp32_1);
1493 set_cc_s32(s, tmp32_1);
1494 tcg_temp_free_i64(tmp2);
1495 tcg_temp_free_i32(tmp32_1);
1496 break;
1497 case 0xc: /* MSG R1,D2(X2,B2) [RXY] */
1498 case 0x1c: /* MSGF R1,D2(X2,B2) [RXY] */
1499 tmp2 = tcg_temp_new_i64();
1500 if (op == 0xc) {
1501 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1502 } else {
1503 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1504 }
1505 tcg_gen_mul_i64(regs[r1], regs[r1], tmp2);
1506 tcg_temp_free_i64(tmp2);
1507 break;
1508 case 0xd: /* DSG R1,D2(X2,B2) [RXY] */
1509 case 0x1d: /* DSGF R1,D2(X2,B2) [RXY] */
1510 tmp2 = tcg_temp_new_i64();
1511 if (op == 0x1d) {
1512 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1513 } else {
1514 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1515 }
1516 tmp4 = load_reg(r1 + 1);
1517 tmp3 = tcg_temp_new_i64();
1518 tcg_gen_div_i64(tmp3, tmp4, tmp2);
1519 store_reg(r1 + 1, tmp3);
1520 tcg_gen_rem_i64(tmp3, tmp4, tmp2);
1521 store_reg(r1, tmp3);
1522 tcg_temp_free_i64(tmp2);
1523 tcg_temp_free_i64(tmp3);
1524 tcg_temp_free_i64(tmp4);
1525 break;
1526 case 0x8: /* AG R1,D2(X2,B2) [RXY] */
1527 case 0xa: /* ALG R1,D2(X2,B2) [RXY] */
1528 case 0x18: /* AGF R1,D2(X2,B2) [RXY] */
1529 case 0x1a: /* ALGF R1,D2(X2,B2) [RXY] */
1530 if (op == 0x1a) {
1531 tmp2 = tcg_temp_new_i64();
1532 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1533 } else if (op == 0x18) {
1534 tmp2 = tcg_temp_new_i64();
1535 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1536 } else {
1537 tmp2 = tcg_temp_new_i64();
1538 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1539 }
1540 tmp4 = load_reg(r1);
1541 tmp3 = tcg_temp_new_i64();
1542 tcg_gen_add_i64(tmp3, tmp4, tmp2);
1543 store_reg(r1, tmp3);
1544 switch (op) {
1545 case 0x8:
1546 case 0x18:
1547 set_cc_add64(s, tmp4, tmp2, tmp3);
1548 break;
1549 case 0xa:
1550 case 0x1a:
1551 set_cc_addu64(s, tmp4, tmp2, tmp3);
1552 break;
1553 default:
1554 tcg_abort();
1555 }
1556 tcg_temp_free_i64(tmp2);
1557 tcg_temp_free_i64(tmp3);
1558 tcg_temp_free_i64(tmp4);
1559 break;
1560 case 0x9: /* SG R1,D2(X2,B2) [RXY] */
1561 case 0xb: /* SLG R1,D2(X2,B2) [RXY] */
1562 case 0x19: /* SGF R1,D2(X2,B2) [RXY] */
1563 case 0x1b: /* SLGF R1,D2(X2,B2) [RXY] */
1564 tmp2 = tcg_temp_new_i64();
1565 if (op == 0x19) {
1566 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1567 } else if (op == 0x1b) {
1568 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1569 } else {
1570 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1571 }
1572 tmp4 = load_reg(r1);
1573 tmp3 = tcg_temp_new_i64();
1574 tcg_gen_sub_i64(tmp3, tmp4, tmp2);
1575 store_reg(r1, tmp3);
1576 switch (op) {
1577 case 0x9:
1578 case 0x19:
1579 set_cc_sub64(s, tmp4, tmp2, tmp3);
1580 break;
1581 case 0xb:
1582 case 0x1b:
1583 set_cc_subu64(s, tmp4, tmp2, tmp3);
1584 break;
1585 default:
1586 tcg_abort();
1587 }
1588 tcg_temp_free_i64(tmp2);
1589 tcg_temp_free_i64(tmp3);
1590 tcg_temp_free_i64(tmp4);
1591 break;
1592 case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
1593 tmp2 = tcg_temp_new_i64();
1594 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1595 tcg_gen_bswap64_i64(tmp2, tmp2);
1596 store_reg(r1, tmp2);
1597 tcg_temp_free_i64(tmp2);
1598 break;
1599 case 0x14: /* LGF R1,D2(X2,B2) [RXY] */
1600 case 0x16: /* LLGF R1,D2(X2,B2) [RXY] */
1601 tmp2 = tcg_temp_new_i64();
1602 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1603 if (op == 0x14) {
1604 tcg_gen_ext32s_i64(tmp2, tmp2);
1605 }
1606 store_reg(r1, tmp2);
1607 tcg_temp_free_i64(tmp2);
1608 break;
1609 case 0x15: /* LGH R1,D2(X2,B2) [RXY] */
1610 tmp2 = tcg_temp_new_i64();
1611 tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
1612 store_reg(r1, tmp2);
1613 tcg_temp_free_i64(tmp2);
1614 break;
1615 case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
1616 tmp2 = tcg_temp_new_i64();
1617 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1618 tcg_gen_andi_i64(tmp2, tmp2, 0x7fffffffULL);
1619 store_reg(r1, tmp2);
1620 tcg_temp_free_i64(tmp2);
1621 break;
1622 case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1623 tmp2 = tcg_temp_new_i64();
1624 tmp32_1 = tcg_temp_new_i32();
1625 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1626 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1627 tcg_temp_free_i64(tmp2);
1628 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1629 store_reg32(r1, tmp32_1);
1630 tcg_temp_free_i32(tmp32_1);
1631 break;
1632 case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1633 tmp2 = tcg_temp_new_i64();
1634 tmp32_1 = tcg_temp_new_i32();
1635 tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
1636 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1637 tcg_temp_free_i64(tmp2);
1638 tcg_gen_bswap16_i32(tmp32_1, tmp32_1);
1639 store_reg16(r1, tmp32_1);
1640 tcg_temp_free_i32(tmp32_1);
1641 break;
1642 case 0x20: /* CG R1,D2(X2,B2) [RXY] */
1643 case 0x21: /* CLG R1,D2(X2,B2) */
1644 case 0x30: /* CGF R1,D2(X2,B2) [RXY] */
1645 case 0x31: /* CLGF R1,D2(X2,B2) [RXY] */
1646 tmp2 = tcg_temp_new_i64();
1647 switch (op) {
1648 case 0x20:
1649 case 0x21:
1650 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1651 break;
1652 case 0x30:
1653 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1654 break;
1655 case 0x31:
1656 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1657 break;
1658 default:
1659 tcg_abort();
1660 }
1661 switch (op) {
1662 case 0x20:
1663 case 0x30:
1664 cmp_s64(s, regs[r1], tmp2);
1665 break;
1666 case 0x21:
1667 case 0x31:
1668 cmp_u64(s, regs[r1], tmp2);
1669 break;
1670 default:
1671 tcg_abort();
1672 }
1673 tcg_temp_free_i64(tmp2);
1674 break;
1675 case 0x24: /* stg r1, d2(x2,b2) */
1676 tcg_gen_qemu_st64(regs[r1], addr, get_mem_index(s));
1677 break;
1678 case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1679 tmp32_1 = load_reg32(r1);
1680 tmp2 = tcg_temp_new_i64();
1681 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1682 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1683 tcg_temp_free_i32(tmp32_1);
1684 tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
1685 tcg_temp_free_i64(tmp2);
1686 break;
1687 case 0x50: /* STY R1,D2(X2,B2) [RXY] */
1688 tmp32_1 = load_reg32(r1);
1689 tmp2 = tcg_temp_new_i64();
1690 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1691 tcg_temp_free_i32(tmp32_1);
1692 tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
1693 tcg_temp_free_i64(tmp2);
1694 break;
1695 case 0x57: /* XY R1,D2(X2,B2) [RXY] */
1696 tmp32_1 = load_reg32(r1);
1697 tmp32_2 = tcg_temp_new_i32();
1698 tmp2 = tcg_temp_new_i64();
1699 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1700 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1701 tcg_temp_free_i64(tmp2);
1702 tcg_gen_xor_i32(tmp32_2, tmp32_1, tmp32_2);
1703 store_reg32(r1, tmp32_2);
1704 set_cc_nz_u32(s, tmp32_2);
1705 tcg_temp_free_i32(tmp32_1);
1706 tcg_temp_free_i32(tmp32_2);
1707 break;
1708 case 0x58: /* LY R1,D2(X2,B2) [RXY] */
1709 tmp3 = tcg_temp_new_i64();
1710 tcg_gen_qemu_ld32u(tmp3, addr, get_mem_index(s));
1711 store_reg32_i64(r1, tmp3);
1712 tcg_temp_free_i64(tmp3);
1713 break;
1714 case 0x5a: /* AY R1,D2(X2,B2) [RXY] */
1715 case 0x5b: /* SY R1,D2(X2,B2) [RXY] */
1716 tmp32_1 = load_reg32(r1);
1717 tmp32_2 = tcg_temp_new_i32();
1718 tmp32_3 = tcg_temp_new_i32();
1719 tmp2 = tcg_temp_new_i64();
1720 tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1721 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1722 tcg_temp_free_i64(tmp2);
1723 switch (op) {
1724 case 0x5a:
1725 tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
1726 break;
1727 case 0x5b:
1728 tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
1729 break;
1730 default:
1731 tcg_abort();
1732 }
1733 store_reg32(r1, tmp32_3);
1734 switch (op) {
1735 case 0x5a:
1736 set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
1737 break;
1738 case 0x5b:
1739 set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
1740 break;
1741 default:
1742 tcg_abort();
1743 }
1744 tcg_temp_free_i32(tmp32_1);
1745 tcg_temp_free_i32(tmp32_2);
1746 tcg_temp_free_i32(tmp32_3);
1747 break;
1748 case 0x71: /* LAY R1,D2(X2,B2) [RXY] */
1749 store_reg(r1, addr);
1750 break;
1751 case 0x72: /* STCY R1,D2(X2,B2) [RXY] */
1752 tmp32_1 = load_reg32(r1);
1753 tmp2 = tcg_temp_new_i64();
1754 tcg_gen_ext_i32_i64(tmp2, tmp32_1);
1755 tcg_gen_qemu_st8(tmp2, addr, get_mem_index(s));
1756 tcg_temp_free_i32(tmp32_1);
1757 tcg_temp_free_i64(tmp2);
1758 break;
1759 case 0x73: /* ICY R1,D2(X2,B2) [RXY] */
1760 tmp3 = tcg_temp_new_i64();
1761 tcg_gen_qemu_ld8u(tmp3, addr, get_mem_index(s));
1762 store_reg8(r1, tmp3);
1763 tcg_temp_free_i64(tmp3);
1764 break;
1765 case 0x76: /* LB R1,D2(X2,B2) [RXY] */
1766 case 0x77: /* LGB R1,D2(X2,B2) [RXY] */
1767 tmp2 = tcg_temp_new_i64();
1768 tcg_gen_qemu_ld8s(tmp2, addr, get_mem_index(s));
1769 switch (op) {
1770 case 0x76:
1771 tcg_gen_ext8s_i64(tmp2, tmp2);
1772 store_reg32_i64(r1, tmp2);
1773 break;
1774 case 0x77:
1775 tcg_gen_ext8s_i64(tmp2, tmp2);
1776 store_reg(r1, tmp2);
1777 break;
1778 default:
1779 tcg_abort();
1780 }
1781 tcg_temp_free_i64(tmp2);
1782 break;
1783 case 0x78: /* LHY R1,D2(X2,B2) [RXY] */
1784 tmp2 = tcg_temp_new_i64();
1785 tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
1786 store_reg32_i64(r1, tmp2);
1787 tcg_temp_free_i64(tmp2);
1788 break;
1789 case 0x80: /* NG R1,D2(X2,B2) [RXY] */
1790 case 0x81: /* OG R1,D2(X2,B2) [RXY] */
1791 case 0x82: /* XG R1,D2(X2,B2) [RXY] */
1792 tmp3 = tcg_temp_new_i64();
1793 tcg_gen_qemu_ld64(tmp3, addr, get_mem_index(s));
1794 switch (op) {
1795 case 0x80:
1796 tcg_gen_and_i64(regs[r1], regs[r1], tmp3);
1797 break;
1798 case 0x81:
1799 tcg_gen_or_i64(regs[r1], regs[r1], tmp3);
1800 break;
1801 case 0x82:
1802 tcg_gen_xor_i64(regs[r1], regs[r1], tmp3);
1803 break;
1804 default:
1805 tcg_abort();
1806 }
1807 set_cc_nz_u64(s, regs[r1]);
1808 tcg_temp_free_i64(tmp3);
1809 break;
1810 case 0x86: /* MLG R1,D2(X2,B2) [RXY] */
1811 tmp2 = tcg_temp_new_i64();
1812 tmp32_1 = tcg_const_i32(r1);
1813 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1814 gen_helper_mlg(tmp32_1, tmp2);
1815 tcg_temp_free_i64(tmp2);
1816 tcg_temp_free_i32(tmp32_1);
1817 break;
1818 case 0x87: /* DLG R1,D2(X2,B2) [RXY] */
1819 tmp2 = tcg_temp_new_i64();
1820 tmp32_1 = tcg_const_i32(r1);
1821 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1822 gen_helper_dlg(tmp32_1, tmp2);
1823 tcg_temp_free_i64(tmp2);
1824 tcg_temp_free_i32(tmp32_1);
1825 break;
1826 case 0x88: /* ALCG R1,D2(X2,B2) [RXY] */
1827 tmp2 = tcg_temp_new_i64();
1828 tmp3 = tcg_temp_new_i64();
1829 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1830 /* XXX possible optimization point */
1831 gen_op_calc_cc(s);
1832 tcg_gen_extu_i32_i64(tmp3, cc_op);
1833 tcg_gen_shri_i64(tmp3, tmp3, 1);
1834 tcg_gen_andi_i64(tmp3, tmp3, 1);
1835 tcg_gen_add_i64(tmp3, tmp2, tmp3);
1836 tcg_gen_add_i64(tmp3, regs[r1], tmp3);
1837 store_reg(r1, tmp3);
1838 set_cc_addu64(s, regs[r1], tmp2, tmp3);
1839 tcg_temp_free_i64(tmp2);
1840 tcg_temp_free_i64(tmp3);
1841 break;
1842 case 0x89: /* SLBG R1,D2(X2,B2) [RXY] */
1843 tmp2 = tcg_temp_new_i64();
1844 tmp32_1 = tcg_const_i32(r1);
1845 tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1846 /* XXX possible optimization point */
1847 gen_op_calc_cc(s);
1848 gen_helper_slbg(cc_op, cc_op, tmp32_1, regs[r1], tmp2);
1849 set_cc_static(s);
1850 tcg_temp_free_i64(tmp2);
1851 tcg_temp_free_i32(tmp32_1);
1852 break;
1853 case 0x90: /* LLGC R1,D2(X2,B2) [RXY] */
1854 tcg_gen_qemu_ld8u(regs[r1], addr, get_mem_index(s));
1855 break;
1856 case 0x91: /* LLGH R1,D2(X2,B2) [RXY] */
1857 tcg_gen_qemu_ld16u(regs[r1], addr, get_mem_index(s));
1858 break;
1859 case 0x94: /* LLC R1,D2(X2,B2) [RXY] */
1860 tmp2 = tcg_temp_new_i64();
1861 tcg_gen_qemu_ld8u(tmp2, addr, get_mem_index(s));
1862 store_reg32_i64(r1, tmp2);
1863 tcg_temp_free_i64(tmp2);
1864 break;
1865 case 0x95: /* LLH R1,D2(X2,B2) [RXY] */
1866 tmp2 = tcg_temp_new_i64();
1867 tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
1868 store_reg32_i64(r1, tmp2);
1869 tcg_temp_free_i64(tmp2);
1870 break;
1871 case 0x96: /* ML R1,D2(X2,B2) [RXY] */
1872 tmp2 = tcg_temp_new_i64();
1873 tmp3 = load_reg((r1 + 1) & 15);
1874 tcg_gen_ext32u_i64(tmp3, tmp3);
1875 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1876 tcg_gen_mul_i64(tmp2, tmp2, tmp3);
1877 store_reg32_i64((r1 + 1) & 15, tmp2);
1878 tcg_gen_shri_i64(tmp2, tmp2, 32);
1879 store_reg32_i64(r1, tmp2);
1880 tcg_temp_free_i64(tmp2);
1881 tcg_temp_free_i64(tmp3);
1882 break;
1883 case 0x97: /* DL R1,D2(X2,B2) [RXY] */
1884 /* reg(r1) = reg(r1, r1+1) % ld32(addr) */
1885 /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
1886 tmp = load_reg(r1);
1887 tmp2 = tcg_temp_new_i64();
1888 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1889 tmp3 = load_reg((r1 + 1) & 15);
1890 tcg_gen_ext32u_i64(tmp2, tmp2);
1891 tcg_gen_ext32u_i64(tmp3, tmp3);
1892 tcg_gen_shli_i64(tmp, tmp, 32);
1893 tcg_gen_or_i64(tmp, tmp, tmp3);
1894
1895 tcg_gen_rem_i64(tmp3, tmp, tmp2);
1896 tcg_gen_div_i64(tmp, tmp, tmp2);
1897 store_reg32_i64((r1 + 1) & 15, tmp);
1898 store_reg32_i64(r1, tmp3);
1899 tcg_temp_free_i64(tmp);
1900 tcg_temp_free_i64(tmp2);
1901 tcg_temp_free_i64(tmp3);
1902 break;
1903 case 0x98: /* ALC R1,D2(X2,B2) [RXY] */
1904 tmp2 = tcg_temp_new_i64();
1905 tmp32_1 = load_reg32(r1);
1906 tmp32_2 = tcg_temp_new_i32();
1907 tmp32_3 = tcg_temp_new_i32();
1908 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1909 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1910 /* XXX possible optimization point */
1911 gen_op_calc_cc(s);
1912 gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2);
1913 set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
1914 store_reg32(r1, tmp32_3);
1915 tcg_temp_free_i64(tmp2);
1916 tcg_temp_free_i32(tmp32_1);
1917 tcg_temp_free_i32(tmp32_2);
1918 tcg_temp_free_i32(tmp32_3);
1919 break;
1920 case 0x99: /* SLB R1,D2(X2,B2) [RXY] */
1921 tmp2 = tcg_temp_new_i64();
1922 tmp32_1 = tcg_const_i32(r1);
1923 tmp32_2 = tcg_temp_new_i32();
1924 tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1925 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1926 /* XXX possible optimization point */
1927 gen_op_calc_cc(s);
1928 gen_helper_slb(cc_op, cc_op, tmp32_1, tmp32_2);
1929 set_cc_static(s);
1930 tcg_temp_free_i64(tmp2);
1931 tcg_temp_free_i32(tmp32_1);
1932 tcg_temp_free_i32(tmp32_2);
1933 break;
1934 default:
1935 LOG_DISAS("illegal e3 operation 0x%x\n", op);
1936 gen_illegal_opcode(s, 3);
1937 break;
1938 }
1939 tcg_temp_free_i64(addr);
1940}
1941
1942#ifndef CONFIG_USER_ONLY
1943static void disas_e5(DisasContext* s, uint64_t insn)
1944{
1945 TCGv_i64 tmp, tmp2;
1946 int op = (insn >> 32) & 0xff;
1947
1948 tmp = get_address(s, 0, (insn >> 28) & 0xf, (insn >> 16) & 0xfff);
1949 tmp2 = get_address(s, 0, (insn >> 12) & 0xf, insn & 0xfff);
1950
1951 LOG_DISAS("disas_e5: insn %" PRIx64 "\n", insn);
1952 switch (op) {
1953 case 0x01: /* TPROT D1(B1),D2(B2) [SSE] */
1954 /* Test Protection */
1955 potential_page_fault(s);
1956 gen_helper_tprot(cc_op, tmp, tmp2);
1957 set_cc_static(s);
1958 break;
1959 default:
1960 LOG_DISAS("illegal e5 operation 0x%x\n", op);
1961 gen_illegal_opcode(s, 3);
1962 break;
1963 }
1964
1965 tcg_temp_free_i64(tmp);
1966 tcg_temp_free_i64(tmp2);
1967}
1968#endif
1969
1970static void disas_eb(DisasContext *s, int op, int r1, int r3, int b2, int d2)
1971{
1972 TCGv_i64 tmp, tmp2, tmp3, tmp4;
1973 TCGv_i32 tmp32_1, tmp32_2;
1974 int i, stm_len;
1975 int ilc = 3;
1976
1977 LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1978 op, r1, r3, b2, d2);
1979 switch (op) {
1980 case 0xc: /* SRLG R1,R3,D2(B2) [RSY] */
1981 case 0xd: /* SLLG R1,R3,D2(B2) [RSY] */
1982 case 0xa: /* SRAG R1,R3,D2(B2) [RSY] */
1983 case 0xb: /* SLAG R1,R3,D2(B2) [RSY] */
1984 case 0x1c: /* RLLG R1,R3,D2(B2) [RSY] */
1985 if (b2) {
1986 tmp = get_address(s, 0, b2, d2);
1987 tcg_gen_andi_i64(tmp, tmp, 0x3f);
1988 } else {
1989 tmp = tcg_const_i64(d2 & 0x3f);
1990 }
1991 switch (op) {
1992 case 0xc:
1993 tcg_gen_shr_i64(regs[r1], regs[r3], tmp);
1994 break;
1995 case 0xd:
1996 tcg_gen_shl_i64(regs[r1], regs[r3], tmp);
1997 break;
1998 case 0xa:
1999 tcg_gen_sar_i64(regs[r1], regs[r3], tmp);
2000 break;
2001 case 0xb:
2002 tmp2 = tcg_temp_new_i64();
2003 tmp3 = tcg_temp_new_i64();
2004 gen_op_update2_cc_i64(s, CC_OP_SLAG, regs[r3], tmp);
2005 tcg_gen_shl_i64(tmp2, regs[r3], tmp);
2006 /* override sign bit with source sign */
2007 tcg_gen_andi_i64(tmp2, tmp2, ~0x8000000000000000ULL);
2008 tcg_gen_andi_i64(tmp3, regs[r3], 0x8000000000000000ULL);
2009 tcg_gen_or_i64(regs[r1], tmp2, tmp3);
2010 tcg_temp_free_i64(tmp2);
2011 tcg_temp_free_i64(tmp3);
2012 break;
2013 case 0x1c:
2014 tcg_gen_rotl_i64(regs[r1], regs[r3], tmp);
2015 break;
2016 default:
2017 tcg_abort();
2018 break;
2019 }
2020 if (op == 0xa) {
2021 set_cc_s64(s, regs[r1]);
2022 }
2023 tcg_temp_free_i64(tmp);
2024 break;
2025 case 0x1d: /* RLL R1,R3,D2(B2) [RSY] */
2026 if (b2) {
2027 tmp = get_address(s, 0, b2, d2);
2028 tcg_gen_andi_i64(tmp, tmp, 0x3f);
2029 } else {
2030 tmp = tcg_const_i64(d2 & 0x3f);
2031 }
2032 tmp32_1 = tcg_temp_new_i32();
2033 tmp32_2 = load_reg32(r3);
2034 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
2035 switch (op) {
2036 case 0x1d:
2037 tcg_gen_rotl_i32(tmp32_1, tmp32_2, tmp32_1);
2038 break;
2039 default:
2040 tcg_abort();
2041 break;
2042 }
2043 store_reg32(r1, tmp32_1);
2044 tcg_temp_free_i64(tmp);
2045 tcg_temp_free_i32(tmp32_1);
2046 tcg_temp_free_i32(tmp32_2);
2047 break;
2048 case 0x4: /* LMG R1,R3,D2(B2) [RSE] */
2049 case 0x24: /* STMG R1,R3,D2(B2) [RSE] */
2050 stm_len = 8;
2051 goto do_mh;
2052 case 0x26: /* STMH R1,R3,D2(B2) [RSE] */
2053 case 0x96: /* LMH R1,R3,D2(B2) [RSE] */
2054 stm_len = 4;
2055do_mh:
2056 /* Apparently, unrolling lmg/stmg of any size gains performance -
2057 even for very long ones... */
2058 tmp = get_address(s, 0, b2, d2);
2059 tmp3 = tcg_const_i64(stm_len);
be82ee2a 2060 tmp4 = tcg_const_i64(op == 0x26 ? 32 : 4);
e023e832
AG		 2061 for (i = r1;; i = (i + 1) % 16) {
2062 switch (op) {
2063 case 0x4:
2064 tcg_gen_qemu_ld64(regs[i], tmp, get_mem_index(s));
2065 break;
2066 case 0x96:
2067 tmp2 = tcg_temp_new_i64();
2068#if HOST_LONG_BITS == 32
2069 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
2070 tcg_gen_trunc_i64_i32(TCGV_HIGH(regs[i]), tmp2);
2071#else
e023e832 2072 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
be82ee2a 2073 tcg_gen_shl_i64(tmp2, tmp2, tmp4);
e023e832
AG		 2074 tcg_gen_ext32u_i64(regs[i], regs[i]);
2075 tcg_gen_or_i64(regs[i], regs[i], tmp2);
2076#endif
2077 tcg_temp_free_i64(tmp2);
2078 break;
2079 case 0x24:
2080 tcg_gen_qemu_st64(regs[i], tmp, get_mem_index(s));
2081 break;
2082 case 0x26:
2083 tmp2 = tcg_temp_new_i64();
2084 tcg_gen_shr_i64(tmp2, regs[i], tmp4);
2085 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2086 tcg_temp_free_i64(tmp2);
2087 break;
2088 default:
2089 tcg_abort();
2090 }
2091 if (i == r3) {
2092 break;
2093 }
2094 tcg_gen_add_i64(tmp, tmp, tmp3);
2095 }
2096 tcg_temp_free_i64(tmp);
21de37a7 2097 tcg_temp_free_i64(tmp3);
e023e832
AG		 2098 tcg_temp_free_i64(tmp4);
2099 break;
2100 case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
2101 tmp = get_address(s, 0, b2, d2);
2102 tmp32_1 = tcg_const_i32(r1);
2103 tmp32_2 = tcg_const_i32(r3);
2104 potential_page_fault(s);
2105 gen_helper_stcmh(tmp32_1, tmp, tmp32_2);
2106 tcg_temp_free_i64(tmp);
2107 tcg_temp_free_i32(tmp32_1);
2108 tcg_temp_free_i32(tmp32_2);
2109 break;
2110#ifndef CONFIG_USER_ONLY
2111 case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
2112 /* Load Control */
2113 check_privileged(s, ilc);
2114 tmp = get_address(s, 0, b2, d2);
2115 tmp32_1 = tcg_const_i32(r1);
2116 tmp32_2 = tcg_const_i32(r3);
2117 potential_page_fault(s);
2118 gen_helper_lctlg(tmp32_1, tmp, tmp32_2);
2119 tcg_temp_free_i64(tmp);
2120 tcg_temp_free_i32(tmp32_1);
2121 tcg_temp_free_i32(tmp32_2);
2122 break;
2123 case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
2124 /* Store Control */
2125 check_privileged(s, ilc);
2126 tmp = get_address(s, 0, b2, d2);
2127 tmp32_1 = tcg_const_i32(r1);
2128 tmp32_2 = tcg_const_i32(r3);
2129 potential_page_fault(s);
2130 gen_helper_stctg(tmp32_1, tmp, tmp32_2);
2131 tcg_temp_free_i64(tmp);
2132 tcg_temp_free_i32(tmp32_1);
2133 tcg_temp_free_i32(tmp32_2);
2134 break;
2135#endif
2136 case 0x30: /* CSG R1,R3,D2(B2) [RSY] */
2137 tmp = get_address(s, 0, b2, d2);
2138 tmp32_1 = tcg_const_i32(r1);
2139 tmp32_2 = tcg_const_i32(r3);
2140 potential_page_fault(s);
2141 /* XXX rewrite in tcg */
2142 gen_helper_csg(cc_op, tmp32_1, tmp, tmp32_2);
2143 set_cc_static(s);
2144 tcg_temp_free_i64(tmp);
2145 tcg_temp_free_i32(tmp32_1);
2146 tcg_temp_free_i32(tmp32_2);
2147 break;
2148 case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
2149 tmp = get_address(s, 0, b2, d2);
2150 tmp32_1 = tcg_const_i32(r1);
2151 tmp32_2 = tcg_const_i32(r3);
2152 potential_page_fault(s);
2153 /* XXX rewrite in tcg */
2154 gen_helper_cdsg(cc_op, tmp32_1, tmp, tmp32_2);
2155 set_cc_static(s);
2156 tcg_temp_free_i64(tmp);
2157 tcg_temp_free_i32(tmp32_1);
2158 tcg_temp_free_i32(tmp32_2);
2159 break;
2160 case 0x51: /* TMY D1(B1),I2 [SIY] */
2161 tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */
2162 tmp2 = tcg_const_i64((r1 << 4) | r3);
2163 tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s));
2164 /* yes, this is a 32 bit operation with 64 bit tcg registers, because
2165 that incurs less conversions */
2166 cmp_64(s, tmp, tmp2, CC_OP_TM_32);
2167 tcg_temp_free_i64(tmp);
2168 tcg_temp_free_i64(tmp2);
2169 break;
2170 case 0x52: /* MVIY D1(B1),I2 [SIY] */
2171 tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */
2172 tmp2 = tcg_const_i64((r1 << 4) | r3);
2173 tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
2174 tcg_temp_free_i64(tmp);
2175 tcg_temp_free_i64(tmp2);
2176 break;
2177 case 0x55: /* CLIY D1(B1),I2 [SIY] */
2178 tmp3 = get_address(s, 0, b2, d2); /* SIY -> this is the 1st operand */
2179 tmp = tcg_temp_new_i64();
2180 tmp32_1 = tcg_temp_new_i32();
2181 tcg_gen_qemu_ld8u(tmp, tmp3, get_mem_index(s));
2182 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
2183 cmp_u32c(s, tmp32_1, (r1 << 4) | r3);
2184 tcg_temp_free_i64(tmp);
2185 tcg_temp_free_i64(tmp3);
2186 tcg_temp_free_i32(tmp32_1);
2187 break;
2188 case 0x80: /* ICMH R1,M3,D2(B2) [RSY] */
2189 tmp = get_address(s, 0, b2, d2);
2190 tmp32_1 = tcg_const_i32(r1);
2191 tmp32_2 = tcg_const_i32(r3);
2192 potential_page_fault(s);
2193 /* XXX split CC calculation out */
2194 gen_helper_icmh(cc_op, tmp32_1, tmp, tmp32_2);
2195 set_cc_static(s);
2196 tcg_temp_free_i64(tmp);
2197 tcg_temp_free_i32(tmp32_1);
2198 tcg_temp_free_i32(tmp32_2);
2199 break;
2200 default:
2201 LOG_DISAS("illegal eb operation 0x%x\n", op);
2202 gen_illegal_opcode(s, ilc);
2203 break;
2204 }
2205}
2206
2207static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
2208 int r1b)
2209{
2210 TCGv_i32 tmp_r1, tmp32;
2211 TCGv_i64 addr, tmp;
2212 addr = get_address(s, x2, b2, d2);
2213 tmp_r1 = tcg_const_i32(r1);
2214 switch (op) {
2215 case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
2216 potential_page_fault(s);
2217 gen_helper_lxdb(tmp_r1, addr);
2218 break;
2219 case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
2220 tmp = tcg_temp_new_i64();
2221 tmp32 = load_freg32(r1);
2222 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2223 set_cc_cmp_f32_i64(s, tmp32, tmp);
2224 tcg_temp_free_i64(tmp);
2225 tcg_temp_free_i32(tmp32);
2226 break;
2227 case 0xa: /* AEB R1,D2(X2,B2) [RXE] */
2228 tmp = tcg_temp_new_i64();
2229 tmp32 = tcg_temp_new_i32();
2230 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2231 tcg_gen_trunc_i64_i32(tmp32, tmp);
2232 gen_helper_aeb(tmp_r1, tmp32);
2233 tcg_temp_free_i64(tmp);
2234 tcg_temp_free_i32(tmp32);
2235
2236 tmp32 = load_freg32(r1);
2237 set_cc_nz_f32(s, tmp32);
2238 tcg_temp_free_i32(tmp32);
2239 break;
2240 case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
2241 tmp = tcg_temp_new_i64();
2242 tmp32 = tcg_temp_new_i32();
2243 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2244 tcg_gen_trunc_i64_i32(tmp32, tmp);
2245 gen_helper_seb(tmp_r1, tmp32);
2246 tcg_temp_free_i64(tmp);
2247 tcg_temp_free_i32(tmp32);
2248
2249 tmp32 = load_freg32(r1);
2250 set_cc_nz_f32(s, tmp32);
2251 tcg_temp_free_i32(tmp32);
2252 break;
2253 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
2254 tmp = tcg_temp_new_i64();
2255 tmp32 = tcg_temp_new_i32();
2256 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2257 tcg_gen_trunc_i64_i32(tmp32, tmp);
2258 gen_helper_deb(tmp_r1, tmp32);
2259 tcg_temp_free_i64(tmp);
2260 tcg_temp_free_i32(tmp32);
2261 break;
2262 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
2263 potential_page_fault(s);
2264 gen_helper_tceb(cc_op, tmp_r1, addr);
2265 set_cc_static(s);
2266 break;
2267 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
2268 potential_page_fault(s);
2269 gen_helper_tcdb(cc_op, tmp_r1, addr);
2270 set_cc_static(s);
2271 break;
2272 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
2273 potential_page_fault(s);
2274 gen_helper_tcxb(cc_op, tmp_r1, addr);
2275 set_cc_static(s);
2276 break;
2277 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
2278 tmp = tcg_temp_new_i64();
2279 tmp32 = tcg_temp_new_i32();
2280 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2281 tcg_gen_trunc_i64_i32(tmp32, tmp);
2282 gen_helper_meeb(tmp_r1, tmp32);
2283 tcg_temp_free_i64(tmp);
2284 tcg_temp_free_i32(tmp32);
2285 break;
2286 case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
2287 potential_page_fault(s);
2288 gen_helper_cdb(cc_op, tmp_r1, addr);
2289 set_cc_static(s);
2290 break;
2291 case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
2292 potential_page_fault(s);
2293 gen_helper_adb(cc_op, tmp_r1, addr);
2294 set_cc_static(s);
2295 break;
2296 case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
2297 potential_page_fault(s);
2298 gen_helper_sdb(cc_op, tmp_r1, addr);
2299 set_cc_static(s);
2300 break;
2301 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
2302 potential_page_fault(s);
2303 gen_helper_mdb(tmp_r1, addr);
2304 break;
2305 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
2306 potential_page_fault(s);
2307 gen_helper_ddb(tmp_r1, addr);
2308 break;
2309 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
2310 /* for RXF insns, r1 is R3 and r1b is R1 */
2311 tmp32 = tcg_const_i32(r1b);
2312 potential_page_fault(s);
2313 gen_helper_madb(tmp32, addr, tmp_r1);
2314 tcg_temp_free_i32(tmp32);
2315 break;
2316 default:
2317 LOG_DISAS("illegal ed operation 0x%x\n", op);
2318 gen_illegal_opcode(s, 3);
2319 return;
2320 }
2321 tcg_temp_free_i32(tmp_r1);
2322 tcg_temp_free_i64(addr);
2323}
2324
2325static void disas_a5(DisasContext *s, int op, int r1, int i2)
2326{
2327 TCGv_i64 tmp, tmp2;
2328 TCGv_i32 tmp32;
2329 LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
2330 switch (op) {
2331 case 0x0: /* IIHH R1,I2 [RI] */
2332 tmp = tcg_const_i64(i2);
2333 tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16);
2334 break;
2335 case 0x1: /* IIHL R1,I2 [RI] */
2336 tmp = tcg_const_i64(i2);
2337 tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16);
2338 break;
2339 case 0x2: /* IILH R1,I2 [RI] */
2340 tmp = tcg_const_i64(i2);
2341 tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 16, 16);
2342 break;
2343 case 0x3: /* IILL R1,I2 [RI] */
2344 tmp = tcg_const_i64(i2);
2345 tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 0, 16);
2346 break;
2347 case 0x4: /* NIHH R1,I2 [RI] */
2348 case 0x8: /* OIHH R1,I2 [RI] */
2349 tmp = load_reg(r1);
2350 tmp32 = tcg_temp_new_i32();
2351 switch (op) {
2352 case 0x4:
2353 tmp2 = tcg_const_i64((((uint64_t)i2) << 48)
2354 | 0x0000ffffffffffffULL);
2355 tcg_gen_and_i64(tmp, tmp, tmp2);
2356 break;
2357 case 0x8:
2358 tmp2 = tcg_const_i64(((uint64_t)i2) << 48);
2359 tcg_gen_or_i64(tmp, tmp, tmp2);
2360 break;
2361 default:
2362 tcg_abort();
2363 }
2364 store_reg(r1, tmp);
2365 tcg_gen_shri_i64(tmp2, tmp, 48);
2366 tcg_gen_trunc_i64_i32(tmp32, tmp2);
2367 set_cc_nz_u32(s, tmp32);
2368 tcg_temp_free_i64(tmp2);
2369 tcg_temp_free_i32(tmp32);
2370 break;
2371 case 0x5: /* NIHL R1,I2 [RI] */
2372 case 0x9: /* OIHL R1,I2 [RI] */
2373 tmp = load_reg(r1);
2374 tmp32 = tcg_temp_new_i32();
2375 switch (op) {
2376 case 0x5:
2377 tmp2 = tcg_const_i64((((uint64_t)i2) << 32)
2378 | 0xffff0000ffffffffULL);
2379 tcg_gen_and_i64(tmp, tmp, tmp2);
2380 break;
2381 case 0x9:
2382 tmp2 = tcg_const_i64(((uint64_t)i2) << 32);
2383 tcg_gen_or_i64(tmp, tmp, tmp2);
2384 break;
2385 default:
2386 tcg_abort();
2387 }
2388 store_reg(r1, tmp);
2389 tcg_gen_shri_i64(tmp2, tmp, 32);
2390 tcg_gen_trunc_i64_i32(tmp32, tmp2);
2391 tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
2392 set_cc_nz_u32(s, tmp32);
2393 tcg_temp_free_i64(tmp2);
2394 tcg_temp_free_i32(tmp32);
2395 break;
2396 case 0x6: /* NILH R1,I2 [RI] */
2397 case 0xa: /* OILH R1,I2 [RI] */
2398 tmp = load_reg(r1);
2399 tmp32 = tcg_temp_new_i32();
2400 switch (op) {
2401 case 0x6:
2402 tmp2 = tcg_const_i64((((uint64_t)i2) << 16)
2403 | 0xffffffff0000ffffULL);
2404 tcg_gen_and_i64(tmp, tmp, tmp2);
2405 break;
2406 case 0xa:
2407 tmp2 = tcg_const_i64(((uint64_t)i2) << 16);
2408 tcg_gen_or_i64(tmp, tmp, tmp2);
2409 break;
2410 default:
2411 tcg_abort();
2412 }
2413 store_reg(r1, tmp);
2414 tcg_gen_shri_i64(tmp, tmp, 16);
2415 tcg_gen_trunc_i64_i32(tmp32, tmp);
2416 tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
2417 set_cc_nz_u32(s, tmp32);
2418 tcg_temp_free_i64(tmp2);
2419 tcg_temp_free_i32(tmp32);
2420 break;
2421 case 0x7: /* NILL R1,I2 [RI] */
2422 case 0xb: /* OILL R1,I2 [RI] */
2423 tmp = load_reg(r1);
2424 tmp32 = tcg_temp_new_i32();
2425 switch (op) {
2426 case 0x7:
2427 tmp2 = tcg_const_i64(i2 | 0xffffffffffff0000ULL);
2428 tcg_gen_and_i64(tmp, tmp, tmp2);
2429 break;
2430 case 0xb:
2431 tmp2 = tcg_const_i64(i2);
2432 tcg_gen_or_i64(tmp, tmp, tmp2);
2433 break;
2434 default:
2435 tcg_abort();
2436 }
2437 store_reg(r1, tmp);
2438 tcg_gen_trunc_i64_i32(tmp32, tmp);
2439 tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
2440 set_cc_nz_u32(s, tmp32); /* signedness should not matter here */
2441 tcg_temp_free_i64(tmp2);
2442 tcg_temp_free_i32(tmp32);
2443 break;
2444 case 0xc: /* LLIHH R1,I2 [RI] */
2445 tmp = tcg_const_i64( ((uint64_t)i2) << 48 );
2446 store_reg(r1, tmp);
2447 break;
2448 case 0xd: /* LLIHL R1,I2 [RI] */
2449 tmp = tcg_const_i64( ((uint64_t)i2) << 32 );
2450 store_reg(r1, tmp);
2451 break;
2452 case 0xe: /* LLILH R1,I2 [RI] */
2453 tmp = tcg_const_i64( ((uint64_t)i2) << 16 );
2454 store_reg(r1, tmp);
2455 break;
2456 case 0xf: /* LLILL R1,I2 [RI] */
2457 tmp = tcg_const_i64(i2);
2458 store_reg(r1, tmp);
2459 break;
2460 default:
2461 LOG_DISAS("illegal a5 operation 0x%x\n", op);
2462 gen_illegal_opcode(s, 2);
2463 return;
2464 }
2465 tcg_temp_free_i64(tmp);
2466}
2467
2468static void disas_a7(DisasContext *s, int op, int r1, int i2)
2469{
2470 TCGv_i64 tmp, tmp2;
2471 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2472 int l1;
2473
2474 LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
2475 switch (op) {
2476 case 0x0: /* TMLH or TMH R1,I2 [RI] */
2477 case 0x1: /* TMLL or TML R1,I2 [RI] */
2478 case 0x2: /* TMHH R1,I2 [RI] */
2479 case 0x3: /* TMHL R1,I2 [RI] */
2480 tmp = load_reg(r1);
2481 tmp2 = tcg_const_i64((uint16_t)i2);
2482 switch (op) {
2483 case 0x0:
2484 tcg_gen_shri_i64(tmp, tmp, 16);
2485 break;
2486 case 0x1:
2487 break;
2488 case 0x2:
2489 tcg_gen_shri_i64(tmp, tmp, 48);
2490 break;
2491 case 0x3:
2492 tcg_gen_shri_i64(tmp, tmp, 32);
2493 break;
2494 }
2495 tcg_gen_andi_i64(tmp, tmp, 0xffff);
2496 cmp_64(s, tmp, tmp2, CC_OP_TM_64);
2497 tcg_temp_free_i64(tmp);
2498 tcg_temp_free_i64(tmp2);
2499 break;
2500 case 0x4: /* brc m1, i2 */
2501 gen_brc(r1, s, i2 * 2LL);
2502 return;
2503 case 0x5: /* BRAS R1,I2 [RI] */
2504 tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 4));
2505 store_reg(r1, tmp);
2506 tcg_temp_free_i64(tmp);
2507 gen_goto_tb(s, 0, s->pc + i2 * 2LL);
2508 s->is_jmp = DISAS_TB_JUMP;
2509 break;
2510 case 0x6: /* BRCT R1,I2 [RI] */
2511 tmp32_1 = load_reg32(r1);
2512 tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
2513 store_reg32(r1, tmp32_1);
2514 gen_update_cc_op(s);
2515 l1 = gen_new_label();
2516 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1);
2517 gen_goto_tb(s, 0, s->pc + (i2 * 2LL));
2518 gen_set_label(l1);
2519 gen_goto_tb(s, 1, s->pc + 4);
2520 s->is_jmp = DISAS_TB_JUMP;
2521 tcg_temp_free_i32(tmp32_1);
2522 break;
2523 case 0x7: /* BRCTG R1,I2 [RI] */
2524 tmp = load_reg(r1);
2525 tcg_gen_subi_i64(tmp, tmp, 1);
2526 store_reg(r1, tmp);
2527 gen_update_cc_op(s);
2528 l1 = gen_new_label();
2529 tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
2530 gen_goto_tb(s, 0, s->pc + (i2 * 2LL));
2531 gen_set_label(l1);
2532 gen_goto_tb(s, 1, s->pc + 4);
2533 s->is_jmp = DISAS_TB_JUMP;
2534 tcg_temp_free_i64(tmp);
2535 break;
2536 case 0x8: /* lhi r1, i2 */
2537 tmp32_1 = tcg_const_i32(i2);
2538 store_reg32(r1, tmp32_1);
2539 tcg_temp_free_i32(tmp32_1);
2540 break;
2541 case 0x9: /* lghi r1, i2 */
2542 tmp = tcg_const_i64(i2);
2543 store_reg(r1, tmp);
2544 tcg_temp_free_i64(tmp);
2545 break;
2546 case 0xa: /* AHI R1,I2 [RI] */
2547 tmp32_1 = load_reg32(r1);
2548 tmp32_2 = tcg_temp_new_i32();
2549 tmp32_3 = tcg_const_i32(i2);
2550
2551 if (i2 < 0) {
2552 tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2);
2553 } else {
2554 tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3);
2555 }
2556
2557 store_reg32(r1, tmp32_2);
2558 set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2);
2559 tcg_temp_free_i32(tmp32_1);
2560 tcg_temp_free_i32(tmp32_2);
2561 tcg_temp_free_i32(tmp32_3);
2562 break;
2563 case 0xb: /* aghi r1, i2 */
2564 tmp = load_reg(r1);
2565 tmp2 = tcg_const_i64(i2);
2566
2567 if (i2 < 0) {
2568 tcg_gen_subi_i64(regs[r1], tmp, -i2);
2569 } else {
2570 tcg_gen_add_i64(regs[r1], tmp, tmp2);
2571 }
2572 set_cc_add64(s, tmp, tmp2, regs[r1]);
2573 tcg_temp_free_i64(tmp);
2574 tcg_temp_free_i64(tmp2);
2575 break;
2576 case 0xc: /* MHI R1,I2 [RI] */
2577 tmp32_1 = load_reg32(r1);
2578 tcg_gen_muli_i32(tmp32_1, tmp32_1, i2);
2579 store_reg32(r1, tmp32_1);
2580 tcg_temp_free_i32(tmp32_1);
2581 break;
2582 case 0xd: /* MGHI R1,I2 [RI] */
2583 tmp = load_reg(r1);
2584 tcg_gen_muli_i64(tmp, tmp, i2);
2585 store_reg(r1, tmp);
2586 tcg_temp_free_i64(tmp);
2587 break;
2588 case 0xe: /* CHI R1,I2 [RI] */
2589 tmp32_1 = load_reg32(r1);
2590 cmp_s32c(s, tmp32_1, i2);
2591 tcg_temp_free_i32(tmp32_1);
2592 break;
2593 case 0xf: /* CGHI R1,I2 [RI] */
2594 tmp = load_reg(r1);
2595 cmp_s64c(s, tmp, i2);
2596 tcg_temp_free_i64(tmp);
2597 break;
2598 default:
2599 LOG_DISAS("illegal a7 operation 0x%x\n", op);
2600 gen_illegal_opcode(s, 2);
2601 return;
2602 }
2603}
2604
2605static void disas_b2(DisasContext *s, int op, uint32_t insn)
2606{
2607 TCGv_i64 tmp, tmp2, tmp3;
2608 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2609 int r1, r2;
2610 int ilc = 2;
2611#ifndef CONFIG_USER_ONLY
2612 int r3, d2, b2;
2613#endif
2614
2615 r1 = (insn >> 4) & 0xf;
2616 r2 = insn & 0xf;
2617
2618 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
2619
2620 switch (op) {
2621 case 0x22: /* IPM R1 [RRE] */
2622 tmp32_1 = tcg_const_i32(r1);
2623 gen_op_calc_cc(s);
2624 gen_helper_ipm(cc_op, tmp32_1);
2625 tcg_temp_free_i32(tmp32_1);
2626 break;
2627 case 0x41: /* CKSM R1,R2 [RRE] */
2628 tmp32_1 = tcg_const_i32(r1);
2629 tmp32_2 = tcg_const_i32(r2);
2630 potential_page_fault(s);
2631 gen_helper_cksm(tmp32_1, tmp32_2);
2632 tcg_temp_free_i32(tmp32_1);
2633 tcg_temp_free_i32(tmp32_2);
2634 gen_op_movi_cc(s, 0);
2635 break;
2636 case 0x4e: /* SAR R1,R2 [RRE] */
2637 tmp32_1 = load_reg32(r2);
2638 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r1]));
2639 tcg_temp_free_i32(tmp32_1);
2640 break;
2641 case 0x4f: /* EAR R1,R2 [RRE] */
2642 tmp32_1 = tcg_temp_new_i32();
2643 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r2]));
2644 store_reg32(r1, tmp32_1);
2645 tcg_temp_free_i32(tmp32_1);
2646 break;
2647 case 0x52: /* MSR R1,R2 [RRE] */
2648 tmp32_1 = load_reg32(r1);
2649 tmp32_2 = load_reg32(r2);
2650 tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
2651 store_reg32(r1, tmp32_1);
2652 tcg_temp_free_i32(tmp32_1);
2653 tcg_temp_free_i32(tmp32_2);
2654 break;
2655 case 0x54: /* MVPG R1,R2 [RRE] */
2656 tmp = load_reg(0);
2657 tmp2 = load_reg(r1);
2658 tmp3 = load_reg(r2);
2659 potential_page_fault(s);
2660 gen_helper_mvpg(tmp, tmp2, tmp3);
2661 tcg_temp_free_i64(tmp);
2662 tcg_temp_free_i64(tmp2);
2663 tcg_temp_free_i64(tmp3);
2664 /* XXX check CCO bit and set CC accordingly */
2665 gen_op_movi_cc(s, 0);
2666 break;
2667 case 0x55: /* MVST R1,R2 [RRE] */
2668 tmp32_1 = load_reg32(0);
2669 tmp32_2 = tcg_const_i32(r1);
2670 tmp32_3 = tcg_const_i32(r2);
2671 potential_page_fault(s);
2672 gen_helper_mvst(tmp32_1, tmp32_2, tmp32_3);
2673 tcg_temp_free_i32(tmp32_1);
2674 tcg_temp_free_i32(tmp32_2);
2675 tcg_temp_free_i32(tmp32_3);
2676 gen_op_movi_cc(s, 1);
2677 break;
2678 case 0x5d: /* CLST R1,R2 [RRE] */
2679 tmp32_1 = load_reg32(0);
2680 tmp32_2 = tcg_const_i32(r1);
2681 tmp32_3 = tcg_const_i32(r2);
2682 potential_page_fault(s);
2683 gen_helper_clst(cc_op, tmp32_1, tmp32_2, tmp32_3);
2684 set_cc_static(s);
2685 tcg_temp_free_i32(tmp32_1);
2686 tcg_temp_free_i32(tmp32_2);
2687 tcg_temp_free_i32(tmp32_3);
2688 break;
2689 case 0x5e: /* SRST R1,R2 [RRE] */
2690 tmp32_1 = load_reg32(0);
2691 tmp32_2 = tcg_const_i32(r1);
2692 tmp32_3 = tcg_const_i32(r2);
2693 potential_page_fault(s);
2694 gen_helper_srst(cc_op, tmp32_1, tmp32_2, tmp32_3);
2695 set_cc_static(s);
2696 tcg_temp_free_i32(tmp32_1);
2697 tcg_temp_free_i32(tmp32_2);
2698 tcg_temp_free_i32(tmp32_3);
2699 break;
2700
2701#ifndef CONFIG_USER_ONLY
2702 case 0x02: /* STIDP D2(B2) [S] */
2703 /* Store CPU ID */
2704 check_privileged(s, ilc);
2705 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2706 tmp = get_address(s, 0, b2, d2);
2707 potential_page_fault(s);
2708 gen_helper_stidp(tmp);
2709 tcg_temp_free_i64(tmp);
2710 break;
2711 case 0x04: /* SCK D2(B2) [S] */
2712 /* Set Clock */
2713 check_privileged(s, ilc);
2714 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2715 tmp = get_address(s, 0, b2, d2);
2716 potential_page_fault(s);
2717 gen_helper_sck(cc_op, tmp);
2718 set_cc_static(s);
2719 tcg_temp_free_i64(tmp);
2720 break;
2721 case 0x05: /* STCK D2(B2) [S] */
2722 /* Store Clock */
2723 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2724 tmp = get_address(s, 0, b2, d2);
2725 potential_page_fault(s);
2726 gen_helper_stck(cc_op, tmp);
2727 set_cc_static(s);
2728 tcg_temp_free_i64(tmp);
2729 break;
2730 case 0x06: /* SCKC D2(B2) [S] */
2731 /* Set Clock Comparator */
2732 check_privileged(s, ilc);
2733 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2734 tmp = get_address(s, 0, b2, d2);
2735 potential_page_fault(s);
2736 gen_helper_sckc(tmp);
2737 tcg_temp_free_i64(tmp);
2738 break;
2739 case 0x07: /* STCKC D2(B2) [S] */
2740 /* Store Clock Comparator */
2741 check_privileged(s, ilc);
2742 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2743 tmp = get_address(s, 0, b2, d2);
2744 potential_page_fault(s);
2745 gen_helper_stckc(tmp);
2746 tcg_temp_free_i64(tmp);
2747 break;
2748 case 0x08: /* SPT D2(B2) [S] */
2749 /* Set CPU Timer */
2750 check_privileged(s, ilc);
2751 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2752 tmp = get_address(s, 0, b2, d2);
2753 potential_page_fault(s);
2754 gen_helper_spt(tmp);
2755 tcg_temp_free_i64(tmp);
2756 break;
2757 case 0x09: /* STPT D2(B2) [S] */
2758 /* Store CPU Timer */
2759 check_privileged(s, ilc);
2760 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2761 tmp = get_address(s, 0, b2, d2);
2762 potential_page_fault(s);
2763 gen_helper_stpt(tmp);
2764 tcg_temp_free_i64(tmp);
2765 break;
2766 case 0x0a: /* SPKA D2(B2) [S] */
2767 /* Set PSW Key from Address */
2768 check_privileged(s, ilc);
2769 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2770 tmp = get_address(s, 0, b2, d2);
2771 tmp2 = tcg_temp_new_i64();
2772 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
2773 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
2774 tcg_gen_or_i64(psw_mask, tmp2, tmp);
2775 tcg_temp_free_i64(tmp2);
2776 tcg_temp_free_i64(tmp);
2777 break;
2778 case 0x0d: /* PTLB [S] */
2779 /* Purge TLB */
2780 check_privileged(s, ilc);
2781 gen_helper_ptlb();
2782 break;
2783 case 0x10: /* SPX D2(B2) [S] */
2784 /* Set Prefix Register */
2785 check_privileged(s, ilc);
2786 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2787 tmp = get_address(s, 0, b2, d2);
2788 potential_page_fault(s);
2789 gen_helper_spx(tmp);
2790 tcg_temp_free_i64(tmp);
2791 break;
2792 case 0x11: /* STPX D2(B2) [S] */
2793 /* Store Prefix */
2794 check_privileged(s, ilc);
2795 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2796 tmp = get_address(s, 0, b2, d2);
2797 tmp2 = tcg_temp_new_i64();
2798 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUState, psa));
2799 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2800 tcg_temp_free_i64(tmp);
2801 tcg_temp_free_i64(tmp2);
2802 break;
2803 case 0x12: /* STAP D2(B2) [S] */
2804 /* Store CPU Address */
2805 check_privileged(s, ilc);
2806 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2807 tmp = get_address(s, 0, b2, d2);
2808 tmp2 = tcg_temp_new_i64();
2809 tmp32_1 = tcg_temp_new_i32();
2810 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, cpu_num));
2811 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
2812 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2813 tcg_temp_free_i64(tmp);
2814 tcg_temp_free_i64(tmp2);
2815 tcg_temp_free_i32(tmp32_1);
2816 break;
2817 case 0x21: /* IPTE R1,R2 [RRE] */
2818 /* Invalidate PTE */
2819 check_privileged(s, ilc);
2820 r1 = (insn >> 4) & 0xf;
2821 r2 = insn & 0xf;
2822 tmp = load_reg(r1);
2823 tmp2 = load_reg(r2);
2824 gen_helper_ipte(tmp, tmp2);
2825 tcg_temp_free_i64(tmp);
2826 tcg_temp_free_i64(tmp2);
2827 break;
2828 case 0x29: /* ISKE R1,R2 [RRE] */
2829 /* Insert Storage Key Extended */
2830 check_privileged(s, ilc);
2831 r1 = (insn >> 4) & 0xf;
2832 r2 = insn & 0xf;
2833 tmp = load_reg(r2);
2834 tmp2 = tcg_temp_new_i64();
2835 gen_helper_iske(tmp2, tmp);
2836 store_reg(r1, tmp2);
2837 tcg_temp_free_i64(tmp);
2838 tcg_temp_free_i64(tmp2);
2839 break;
2840 case 0x2a: /* RRBE R1,R2 [RRE] */
2841 /* Set Storage Key Extended */
2842 check_privileged(s, ilc);
2843 r1 = (insn >> 4) & 0xf;
2844 r2 = insn & 0xf;
2845 tmp32_1 = load_reg32(r1);
2846 tmp = load_reg(r2);
2847 gen_helper_rrbe(cc_op, tmp32_1, tmp);
2848 set_cc_static(s);
2849 tcg_temp_free_i32(tmp32_1);
2850 tcg_temp_free_i64(tmp);
2851 break;
2852 case 0x2b: /* SSKE R1,R2 [RRE] */
2853 /* Set Storage Key Extended */
2854 check_privileged(s, ilc);
2855 r1 = (insn >> 4) & 0xf;
2856 r2 = insn & 0xf;
2857 tmp32_1 = load_reg32(r1);
2858 tmp = load_reg(r2);
2859 gen_helper_sske(tmp32_1, tmp);
2860 tcg_temp_free_i32(tmp32_1);
2861 tcg_temp_free_i64(tmp);
2862 break;
2863 case 0x34: /* STCH ? */
2864 /* Store Subchannel */
2865 check_privileged(s, ilc);
2866 gen_op_movi_cc(s, 3);
2867 break;
2868 case 0x46: /* STURA R1,R2 [RRE] */
2869 /* Store Using Real Address */
2870 check_privileged(s, ilc);
2871 r1 = (insn >> 4) & 0xf;
2872 r2 = insn & 0xf;
2873 tmp32_1 = load_reg32(r1);
2874 tmp = load_reg(r2);
2875 potential_page_fault(s);
2876 gen_helper_stura(tmp, tmp32_1);
2877 tcg_temp_free_i32(tmp32_1);
2878 tcg_temp_free_i64(tmp);
2879 break;
2880 case 0x50: /* CSP R1,R2 [RRE] */
2881 /* Compare And Swap And Purge */
2882 check_privileged(s, ilc);
2883 r1 = (insn >> 4) & 0xf;
2884 r2 = insn & 0xf;
2885 tmp32_1 = tcg_const_i32(r1);
2886 tmp32_2 = tcg_const_i32(r2);
2887 gen_helper_csp(cc_op, tmp32_1, tmp32_2);
2888 set_cc_static(s);
2889 tcg_temp_free_i32(tmp32_1);
2890 tcg_temp_free_i32(tmp32_2);
2891 break;
2892 case 0x5f: /* CHSC ? */
2893 /* Channel Subsystem Call */
2894 check_privileged(s, ilc);
2895 gen_op_movi_cc(s, 3);
2896 break;
2897 case 0x78: /* STCKE D2(B2) [S] */
2898 /* Store Clock Extended */
2899 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2900 tmp = get_address(s, 0, b2, d2);
2901 potential_page_fault(s);
2902 gen_helper_stcke(cc_op, tmp);
2903 set_cc_static(s);
2904 tcg_temp_free_i64(tmp);
2905 break;
2906 case 0x79: /* SACF D2(B2) [S] */
2907 /* Store Clock Extended */
2908 check_privileged(s, ilc);
2909 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2910 tmp = get_address(s, 0, b2, d2);
2911 potential_page_fault(s);
2912 gen_helper_sacf(tmp);
2913 tcg_temp_free_i64(tmp);
2914 /* addressing mode has changed, so end the block */
2915 s->pc += ilc * 2;
2916 update_psw_addr(s);
2917 s->is_jmp = DISAS_EXCP;
2918 break;
2919 case 0x7d: /* STSI D2,(B2) [S] */
2920 check_privileged(s, ilc);
2921 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2922 tmp = get_address(s, 0, b2, d2);
2923 tmp32_1 = load_reg32(0);
2924 tmp32_2 = load_reg32(1);
2925 potential_page_fault(s);
2926 gen_helper_stsi(cc_op, tmp, tmp32_1, tmp32_2);
2927 set_cc_static(s);
2928 tcg_temp_free_i64(tmp);
2929 tcg_temp_free_i32(tmp32_1);
2930 tcg_temp_free_i32(tmp32_2);
2931 break;
2932 case 0x9d: /* LFPC D2(B2) [S] */
2933 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2934 tmp = get_address(s, 0, b2, d2);
2935 tmp2 = tcg_temp_new_i64();
2936 tmp32_1 = tcg_temp_new_i32();
2937 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
2938 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
2939 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
2940 tcg_temp_free_i64(tmp);
2941 tcg_temp_free_i64(tmp2);
2942 tcg_temp_free_i32(tmp32_1);
2943 break;
2944 case 0xb1: /* STFL D2(B2) [S] */
2945 /* Store Facility List (CPU features) at 200 */
2946 check_privileged(s, ilc);
2947 tmp2 = tcg_const_i64(0xc0000000);
2948 tmp = tcg_const_i64(200);
2949 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2950 tcg_temp_free_i64(tmp2);
2951 tcg_temp_free_i64(tmp);
2952 break;
2953 case 0xb2: /* LPSWE D2(B2) [S] */
2954 /* Load PSW Extended */
2955 check_privileged(s, ilc);
2956 decode_rs(s, insn, &r1, &r3, &b2, &d2);
2957 tmp = get_address(s, 0, b2, d2);
2958 tmp2 = tcg_temp_new_i64();
2959 tmp3 = tcg_temp_new_i64();
2960 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
2961 tcg_gen_addi_i64(tmp, tmp, 8);
2962 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
2963 gen_helper_load_psw(tmp2, tmp3);
2964 /* we need to keep cc_op intact */
2965 s->is_jmp = DISAS_JUMP;
2966 tcg_temp_free_i64(tmp);
e32a1832
SW		 2967 tcg_temp_free_i64(tmp2);
2968 tcg_temp_free_i64(tmp3);
e023e832
AG		 2969 break;
2970 case 0x20: /* SERVC R1,R2 [RRE] */
2971 /* SCLP Service call (PV hypercall) */
2972 check_privileged(s, ilc);
2973 potential_page_fault(s);
2974 tmp32_1 = load_reg32(r2);
2975 tmp = load_reg(r1);
2976 gen_helper_servc(cc_op, tmp32_1, tmp);
2977 set_cc_static(s);
2978 tcg_temp_free_i32(tmp32_1);
2979 tcg_temp_free_i64(tmp);
2980 break;
2981#endif
2982 default:
2983 LOG_DISAS("illegal b2 operation 0x%x\n", op);
2984 gen_illegal_opcode(s, ilc);
2985 break;
2986 }
2987}
2988
2989static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
2990{
2991 TCGv_i64 tmp;
2992 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2993 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op, m3, r1, r2);
2994#define FP_HELPER(i) \
2995 tmp32_1 = tcg_const_i32(r1); \
2996 tmp32_2 = tcg_const_i32(r2); \
2997 gen_helper_ ## i (tmp32_1, tmp32_2); \
2998 tcg_temp_free_i32(tmp32_1); \
2999 tcg_temp_free_i32(tmp32_2);
3000
3001#define FP_HELPER_CC(i) \
3002 tmp32_1 = tcg_const_i32(r1); \
3003 tmp32_2 = tcg_const_i32(r2); \
3004 gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \
3005 set_cc_static(s); \
3006 tcg_temp_free_i32(tmp32_1); \
3007 tcg_temp_free_i32(tmp32_2);
3008
3009 switch (op) {
3010 case 0x0: /* LPEBR R1,R2 [RRE] */
3011 FP_HELPER_CC(lpebr);
3012 break;
3013 case 0x2: /* LTEBR R1,R2 [RRE] */
3014 FP_HELPER_CC(ltebr);
3015 break;
3016 case 0x3: /* LCEBR R1,R2 [RRE] */
3017 FP_HELPER_CC(lcebr);
3018 break;
3019 case 0x4: /* LDEBR R1,R2 [RRE] */
3020 FP_HELPER(ldebr);
3021 break;
3022 case 0x5: /* LXDBR R1,R2 [RRE] */
3023 FP_HELPER(lxdbr);
3024 break;
3025 case 0x9: /* CEBR R1,R2 [RRE] */
3026 FP_HELPER_CC(cebr);
3027 break;
3028 case 0xa: /* AEBR R1,R2 [RRE] */
3029 FP_HELPER_CC(aebr);
3030 break;
3031 case 0xb: /* SEBR R1,R2 [RRE] */
3032 FP_HELPER_CC(sebr);
3033 break;
3034 case 0xd: /* DEBR R1,R2 [RRE] */
3035 FP_HELPER(debr);
3036 break;
3037 case 0x10: /* LPDBR R1,R2 [RRE] */
3038 FP_HELPER_CC(lpdbr);
3039 break;
3040 case 0x12: /* LTDBR R1,R2 [RRE] */
3041 FP_HELPER_CC(ltdbr);
3042 break;
3043 case 0x13: /* LCDBR R1,R2 [RRE] */
3044 FP_HELPER_CC(lcdbr);
3045 break;
3046 case 0x15: /* SQBDR R1,R2 [RRE] */
3047 FP_HELPER(sqdbr);
3048 break;
3049 case 0x17: /* MEEBR R1,R2 [RRE] */
3050 FP_HELPER(meebr);
3051 break;
3052 case 0x19: /* CDBR R1,R2 [RRE] */
3053 FP_HELPER_CC(cdbr);
3054 break;
3055 case 0x1a: /* ADBR R1,R2 [RRE] */
3056 FP_HELPER_CC(adbr);
3057 break;
3058 case 0x1b: /* SDBR R1,R2 [RRE] */
3059 FP_HELPER_CC(sdbr);
3060 break;
3061 case 0x1c: /* MDBR R1,R2 [RRE] */
3062 FP_HELPER(mdbr);
3063 break;
3064 case 0x1d: /* DDBR R1,R2 [RRE] */
3065 FP_HELPER(ddbr);
3066 break;
3067 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
3068 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
3069 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
3070 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
3071 tmp32_1 = tcg_const_i32(m3);
3072 tmp32_2 = tcg_const_i32(r2);
3073 tmp32_3 = tcg_const_i32(r1);
3074 switch (op) {
3075 case 0xe:
3076 gen_helper_maebr(tmp32_1, tmp32_3, tmp32_2);
3077 break;
3078 case 0x1e:
3079 gen_helper_madbr(tmp32_1, tmp32_3, tmp32_2);
3080 break;
3081 case 0x1f:
3082 gen_helper_msdbr(tmp32_1, tmp32_3, tmp32_2);
3083 break;
3084 default:
3085 tcg_abort();
3086 }
3087 tcg_temp_free_i32(tmp32_1);
3088 tcg_temp_free_i32(tmp32_2);
3089 tcg_temp_free_i32(tmp32_3);
3090 break;
3091 case 0x40: /* LPXBR R1,R2 [RRE] */
3092 FP_HELPER_CC(lpxbr);
3093 break;
3094 case 0x42: /* LTXBR R1,R2 [RRE] */
3095 FP_HELPER_CC(ltxbr);
3096 break;
3097 case 0x43: /* LCXBR R1,R2 [RRE] */
3098 FP_HELPER_CC(lcxbr);
3099 break;
3100 case 0x44: /* LEDBR R1,R2 [RRE] */
3101 FP_HELPER(ledbr);
3102 break;
3103 case 0x45: /* LDXBR R1,R2 [RRE] */
3104 FP_HELPER(ldxbr);
3105 break;
3106 case 0x46: /* LEXBR R1,R2 [RRE] */
3107 FP_HELPER(lexbr);
3108 break;
3109 case 0x49: /* CXBR R1,R2 [RRE] */
3110 FP_HELPER_CC(cxbr);
3111 break;
3112 case 0x4a: /* AXBR R1,R2 [RRE] */
3113 FP_HELPER_CC(axbr);
3114 break;
3115 case 0x4b: /* SXBR R1,R2 [RRE] */
3116 FP_HELPER_CC(sxbr);
3117 break;
3118 case 0x4c: /* MXBR R1,R2 [RRE] */
3119 FP_HELPER(mxbr);
3120 break;
3121 case 0x4d: /* DXBR R1,R2 [RRE] */
3122 FP_HELPER(dxbr);
3123 break;
3124 case 0x65: /* LXR R1,R2 [RRE] */
3125 tmp = load_freg(r2);
3126 store_freg(r1, tmp);
3127 tcg_temp_free_i64(tmp);
3128 tmp = load_freg(r2 + 2);
3129 store_freg(r1 + 2, tmp);
3130 tcg_temp_free_i64(tmp);
3131 break;
3132 case 0x74: /* LZER R1 [RRE] */
3133 tmp32_1 = tcg_const_i32(r1);
3134 gen_helper_lzer(tmp32_1);
3135 tcg_temp_free_i32(tmp32_1);
3136 break;
3137 case 0x75: /* LZDR R1 [RRE] */
3138 tmp32_1 = tcg_const_i32(r1);
3139 gen_helper_lzdr(tmp32_1);
3140 tcg_temp_free_i32(tmp32_1);
3141 break;
3142 case 0x76: /* LZXR R1 [RRE] */
3143 tmp32_1 = tcg_const_i32(r1);
3144 gen_helper_lzxr(tmp32_1);
3145 tcg_temp_free_i32(tmp32_1);
3146 break;
3147 case 0x84: /* SFPC R1 [RRE] */
3148 tmp32_1 = load_reg32(r1);
3149 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
3150 tcg_temp_free_i32(tmp32_1);
3151 break;
3152 case 0x8c: /* EFPC R1 [RRE] */
3153 tmp32_1 = tcg_temp_new_i32();
3154 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
3155 store_reg32(r1, tmp32_1);
3156 tcg_temp_free_i32(tmp32_1);
3157 break;
3158 case 0x94: /* CEFBR R1,R2 [RRE] */
3159 case 0x95: /* CDFBR R1,R2 [RRE] */
3160 case 0x96: /* CXFBR R1,R2 [RRE] */
3161 tmp32_1 = tcg_const_i32(r1);
3162 tmp32_2 = load_reg32(r2);
3163 switch (op) {
3164 case 0x94:
3165 gen_helper_cefbr(tmp32_1, tmp32_2);
3166 break;
3167 case 0x95:
3168 gen_helper_cdfbr(tmp32_1, tmp32_2);
3169 break;
3170 case 0x96:
3171 gen_helper_cxfbr(tmp32_1, tmp32_2);
3172 break;
3173 default:
3174 tcg_abort();
3175 }
3176 tcg_temp_free_i32(tmp32_1);
3177 tcg_temp_free_i32(tmp32_2);
3178 break;
3179 case 0x98: /* CFEBR R1,R2 [RRE] */
3180 case 0x99: /* CFDBR R1,R2 [RRE] */
3181 case 0x9a: /* CFXBR R1,R2 [RRE] */
3182 tmp32_1 = tcg_const_i32(r1);
3183 tmp32_2 = tcg_const_i32(r2);
3184 tmp32_3 = tcg_const_i32(m3);
3185 switch (op) {
3186 case 0x98:
3187 gen_helper_cfebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3188 break;
3189 case 0x99:
3190 gen_helper_cfdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3191 break;
3192 case 0x9a:
3193 gen_helper_cfxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3194 break;
3195 default:
3196 tcg_abort();
3197 }
3198 set_cc_static(s);
3199 tcg_temp_free_i32(tmp32_1);
3200 tcg_temp_free_i32(tmp32_2);
3201 tcg_temp_free_i32(tmp32_3);
3202 break;
3203 case 0xa4: /* CEGBR R1,R2 [RRE] */
3204 case 0xa5: /* CDGBR R1,R2 [RRE] */
3205 tmp32_1 = tcg_const_i32(r1);
3206 tmp = load_reg(r2);
3207 switch (op) {
3208 case 0xa4:
3209 gen_helper_cegbr(tmp32_1, tmp);
3210 break;
3211 case 0xa5:
3212 gen_helper_cdgbr(tmp32_1, tmp);
3213 break;
3214 default:
3215 tcg_abort();
3216 }
3217 tcg_temp_free_i32(tmp32_1);
3218 tcg_temp_free_i64(tmp);
3219 break;
3220 case 0xa6: /* CXGBR R1,R2 [RRE] */
3221 tmp32_1 = tcg_const_i32(r1);
3222 tmp = load_reg(r2);
3223 gen_helper_cxgbr(tmp32_1, tmp);
3224 tcg_temp_free_i32(tmp32_1);
3225 tcg_temp_free_i64(tmp);
3226 break;
3227 case 0xa8: /* CGEBR R1,R2 [RRE] */
3228 tmp32_1 = tcg_const_i32(r1);
3229 tmp32_2 = tcg_const_i32(r2);
3230 tmp32_3 = tcg_const_i32(m3);
3231 gen_helper_cgebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3232 set_cc_static(s);
3233 tcg_temp_free_i32(tmp32_1);
3234 tcg_temp_free_i32(tmp32_2);
3235 tcg_temp_free_i32(tmp32_3);
3236 break;
3237 case 0xa9: /* CGDBR R1,R2 [RRE] */
3238 tmp32_1 = tcg_const_i32(r1);
3239 tmp32_2 = tcg_const_i32(r2);
3240 tmp32_3 = tcg_const_i32(m3);
3241 gen_helper_cgdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3242 set_cc_static(s);
3243 tcg_temp_free_i32(tmp32_1);
3244 tcg_temp_free_i32(tmp32_2);
3245 tcg_temp_free_i32(tmp32_3);
3246 break;
3247 case 0xaa: /* CGXBR R1,R2 [RRE] */
3248 tmp32_1 = tcg_const_i32(r1);
3249 tmp32_2 = tcg_const_i32(r2);
3250 tmp32_3 = tcg_const_i32(m3);
3251 gen_helper_cgxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3252 set_cc_static(s);
3253 tcg_temp_free_i32(tmp32_1);
3254 tcg_temp_free_i32(tmp32_2);
3255 tcg_temp_free_i32(tmp32_3);
3256 break;
3257 default:
3258 LOG_DISAS("illegal b3 operation 0x%x\n", op);
3259 gen_illegal_opcode(s, 2);
3260 break;
3261 }
3262
3263#undef FP_HELPER_CC
3264#undef FP_HELPER
3265}
3266
3267static void disas_b9(DisasContext *s, int op, int r1, int r2)
3268{
3269 TCGv_i64 tmp, tmp2, tmp3;
3270 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
3271
3272 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op, r1, r2);
3273 switch (op) {
3274 case 0x0: /* LPGR R1,R2 [RRE] */
3275 case 0x1: /* LNGR R1,R2 [RRE] */
3276 case 0x2: /* LTGR R1,R2 [RRE] */
3277 case 0x3: /* LCGR R1,R2 [RRE] */
3278 case 0x10: /* LPGFR R1,R2 [RRE] */
3279 case 0x11: /* LNFGR R1,R2 [RRE] */
3280 case 0x12: /* LTGFR R1,R2 [RRE] */
3281 case 0x13: /* LCGFR R1,R2 [RRE] */
3282 if (op & 0x10) {
3283 tmp = load_reg32_i64(r2);
3284 } else {
3285 tmp = load_reg(r2);
3286 }
3287 switch (op & 0xf) {
3288 case 0x0: /* LP?GR */
3289 set_cc_abs64(s, tmp);
3290 gen_helper_abs_i64(tmp, tmp);
3291 store_reg(r1, tmp);
3292 break;
3293 case 0x1: /* LN?GR */
3294 set_cc_nabs64(s, tmp);
3295 gen_helper_nabs_i64(tmp, tmp);
3296 store_reg(r1, tmp);
3297 break;
3298 case 0x2: /* LT?GR */
3299 if (r1 != r2) {
3300 store_reg(r1, tmp);
3301 }
3302 set_cc_s64(s, tmp);
3303 break;
3304 case 0x3: /* LC?GR */
3305 tcg_gen_neg_i64(regs[r1], tmp);
3306 set_cc_comp64(s, regs[r1]);
3307 break;
3308 }
3309 tcg_temp_free_i64(tmp);
3310 break;
3311 case 0x4: /* LGR R1,R2 [RRE] */
3312 store_reg(r1, regs[r2]);
3313 break;
3314 case 0x6: /* LGBR R1,R2 [RRE] */
3315 tmp2 = load_reg(r2);
3316 tcg_gen_ext8s_i64(tmp2, tmp2);
3317 store_reg(r1, tmp2);
3318 tcg_temp_free_i64(tmp2);
3319 break;
3320 case 0x8: /* AGR R1,R2 [RRE] */
3321 case 0xa: /* ALGR R1,R2 [RRE] */
3322 tmp = load_reg(r1);
3323 tmp2 = load_reg(r2);
3324 tmp3 = tcg_temp_new_i64();
3325 tcg_gen_add_i64(tmp3, tmp, tmp2);
3326 store_reg(r1, tmp3);
3327 switch (op) {
3328 case 0x8:
3329 set_cc_add64(s, tmp, tmp2, tmp3);
3330 break;
3331 case 0xa:
3332 set_cc_addu64(s, tmp, tmp2, tmp3);
3333 break;
3334 default:
3335 tcg_abort();
3336 }
3337 tcg_temp_free_i64(tmp);
3338 tcg_temp_free_i64(tmp2);
3339 tcg_temp_free_i64(tmp3);
3340 break;
3341 case 0x9: /* SGR R1,R2 [RRE] */
3342 case 0xb: /* SLGR R1,R2 [RRE] */
3343 case 0x1b: /* SLGFR R1,R2 [RRE] */
3344 case 0x19: /* SGFR R1,R2 [RRE] */
3345 tmp = load_reg(r1);
3346 switch (op) {
3347 case 0x1b:
3348 tmp32_1 = load_reg32(r2);
3349 tmp2 = tcg_temp_new_i64();
3350 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
3351 tcg_temp_free_i32(tmp32_1);
3352 break;
3353 case 0x19:
3354 tmp32_1 = load_reg32(r2);
3355 tmp2 = tcg_temp_new_i64();
3356 tcg_gen_ext_i32_i64(tmp2, tmp32_1);
3357 tcg_temp_free_i32(tmp32_1);
3358 break;
3359 default:
3360 tmp2 = load_reg(r2);
3361 break;
3362 }
3363 tmp3 = tcg_temp_new_i64();
3364 tcg_gen_sub_i64(tmp3, tmp, tmp2);
3365 store_reg(r1, tmp3);
3366 switch (op) {
3367 case 0x9:
3368 case 0x19:
3369 set_cc_sub64(s, tmp, tmp2, tmp3);
3370 break;
3371 case 0xb:
3372 case 0x1b:
3373 set_cc_subu64(s, tmp, tmp2, tmp3);
3374 break;
3375 default:
3376 tcg_abort();
3377 }
3378 tcg_temp_free_i64(tmp);
3379 tcg_temp_free_i64(tmp2);
3380 tcg_temp_free_i64(tmp3);
3381 break;
3382 case 0xc: /* MSGR R1,R2 [RRE] */
3383 case 0x1c: /* MSGFR R1,R2 [RRE] */
3384 tmp = load_reg(r1);
3385 tmp2 = load_reg(r2);
3386 if (op == 0x1c) {
3387 tcg_gen_ext32s_i64(tmp2, tmp2);
3388 }
3389 tcg_gen_mul_i64(tmp, tmp, tmp2);
3390 store_reg(r1, tmp);
3391 tcg_temp_free_i64(tmp);
3392 tcg_temp_free_i64(tmp2);
3393 break;
3394 case 0xd: /* DSGR R1,R2 [RRE] */
3395 case 0x1d: /* DSGFR R1,R2 [RRE] */
3396 tmp = load_reg(r1 + 1);
3397 if (op == 0xd) {
3398 tmp2 = load_reg(r2);
3399 } else {
3400 tmp32_1 = load_reg32(r2);
3401 tmp2 = tcg_temp_new_i64();
3402 tcg_gen_ext_i32_i64(tmp2, tmp32_1);
3403 tcg_temp_free_i32(tmp32_1);
3404 }
3405 tmp3 = tcg_temp_new_i64();
3406 tcg_gen_div_i64(tmp3, tmp, tmp2);
3407 store_reg(r1 + 1, tmp3);
3408 tcg_gen_rem_i64(tmp3, tmp, tmp2);
3409 store_reg(r1, tmp3);
3410 tcg_temp_free_i64(tmp);
3411 tcg_temp_free_i64(tmp2);
3412 tcg_temp_free_i64(tmp3);
3413 break;
3414 case 0x14: /* LGFR R1,R2 [RRE] */
3415 tmp32_1 = load_reg32(r2);
3416 tmp = tcg_temp_new_i64();
3417 tcg_gen_ext_i32_i64(tmp, tmp32_1);
3418 store_reg(r1, tmp);
3419 tcg_temp_free_i32(tmp32_1);
3420 tcg_temp_free_i64(tmp);
3421 break;
3422 case 0x16: /* LLGFR R1,R2 [RRE] */
3423 tmp32_1 = load_reg32(r2);
3424 tmp = tcg_temp_new_i64();
3425 tcg_gen_extu_i32_i64(tmp, tmp32_1);
3426 store_reg(r1, tmp);
3427 tcg_temp_free_i32(tmp32_1);
3428 tcg_temp_free_i64(tmp);
3429 break;
3430 case 0x17: /* LLGTR R1,R2 [RRE] */
3431 tmp32_1 = load_reg32(r2);
3432 tmp = tcg_temp_new_i64();
3433 tcg_gen_andi_i32(tmp32_1, tmp32_1, 0x7fffffffUL);
3434 tcg_gen_extu_i32_i64(tmp, tmp32_1);
3435 store_reg(r1, tmp);
3436 tcg_temp_free_i32(tmp32_1);
3437 tcg_temp_free_i64(tmp);
3438 break;
3439 case 0x18: /* AGFR R1,R2 [RRE] */
3440 case 0x1a: /* ALGFR R1,R2 [RRE] */
3441 tmp32_1 = load_reg32(r2);
3442 tmp2 = tcg_temp_new_i64();
3443 if (op == 0x18) {
3444 tcg_gen_ext_i32_i64(tmp2, tmp32_1);
3445 } else {
3446 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
3447 }
3448 tcg_temp_free_i32(tmp32_1);
3449 tmp = load_reg(r1);
3450 tmp3 = tcg_temp_new_i64();
3451 tcg_gen_add_i64(tmp3, tmp, tmp2);
3452 store_reg(r1, tmp3);
3453 if (op == 0x18) {
3454 set_cc_add64(s, tmp, tmp2, tmp3);
3455 } else {
3456 set_cc_addu64(s, tmp, tmp2, tmp3);
3457 }
3458 tcg_temp_free_i64(tmp);
3459 tcg_temp_free_i64(tmp2);
3460 tcg_temp_free_i64(tmp3);
3461 break;
3462 case 0x1f: /* LRVR R1,R2 [RRE] */
3463 tmp32_1 = load_reg32(r2);
3464 tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
3465 store_reg32(r1, tmp32_1);
3466 tcg_temp_free_i32(tmp32_1);
3467 break;
3468 case 0x20: /* CGR R1,R2 [RRE] */
3469 case 0x30: /* CGFR R1,R2 [RRE] */
3470 tmp2 = load_reg(r2);
3471 if (op == 0x30) {
3472 tcg_gen_ext32s_i64(tmp2, tmp2);
3473 }
3474 tmp = load_reg(r1);
3475 cmp_s64(s, tmp, tmp2);
3476 tcg_temp_free_i64(tmp);
3477 tcg_temp_free_i64(tmp2);
3478 break;
3479 case 0x21: /* CLGR R1,R2 [RRE] */
3480 case 0x31: /* CLGFR R1,R2 [RRE] */
3481 tmp2 = load_reg(r2);
3482 if (op == 0x31) {
3483 tcg_gen_ext32u_i64(tmp2, tmp2);
3484 }
3485 tmp = load_reg(r1);
3486 cmp_u64(s, tmp, tmp2);
3487 tcg_temp_free_i64(tmp);
3488 tcg_temp_free_i64(tmp2);
3489 break;
3490 case 0x26: /* LBR R1,R2 [RRE] */
3491 tmp32_1 = load_reg32(r2);
3492 tcg_gen_ext8s_i32(tmp32_1, tmp32_1);
3493 store_reg32(r1, tmp32_1);
3494 tcg_temp_free_i32(tmp32_1);
3495 break;
3496 case 0x27: /* LHR R1,R2 [RRE] */
3497 tmp32_1 = load_reg32(r2);
3498 tcg_gen_ext16s_i32(tmp32_1, tmp32_1);
3499 store_reg32(r1, tmp32_1);
3500 tcg_temp_free_i32(tmp32_1);
3501 break;
3502 case 0x80: /* NGR R1,R2 [RRE] */
3503 case 0x81: /* OGR R1,R2 [RRE] */
3504 case 0x82: /* XGR R1,R2 [RRE] */
3505 tmp = load_reg(r1);
3506 tmp2 = load_reg(r2);
3507 switch (op) {
3508 case 0x80:
3509 tcg_gen_and_i64(tmp, tmp, tmp2);
3510 break;
3511 case 0x81:
3512 tcg_gen_or_i64(tmp, tmp, tmp2);
3513 break;
3514 case 0x82:
3515 tcg_gen_xor_i64(tmp, tmp, tmp2);
3516 break;
3517 default:
3518 tcg_abort();
3519 }
3520 store_reg(r1, tmp);
3521 set_cc_nz_u64(s, tmp);
3522 tcg_temp_free_i64(tmp);
3523 tcg_temp_free_i64(tmp2);
3524 break;
3525 case 0x83: /* FLOGR R1,R2 [RRE] */
3526 tmp = load_reg(r2);
3527 tmp32_1 = tcg_const_i32(r1);
3528 gen_helper_flogr(cc_op, tmp32_1, tmp);
3529 set_cc_static(s);
3530 tcg_temp_free_i64(tmp);
3531 tcg_temp_free_i32(tmp32_1);
3532 break;
3533 case 0x84: /* LLGCR R1,R2 [RRE] */
3534 tmp = load_reg(r2);
3535 tcg_gen_andi_i64(tmp, tmp, 0xff);
3536 store_reg(r1, tmp);
3537 tcg_temp_free_i64(tmp);
3538 break;
3539 case 0x85: /* LLGHR R1,R2 [RRE] */
3540 tmp = load_reg(r2);
3541 tcg_gen_andi_i64(tmp, tmp, 0xffff);
3542 store_reg(r1, tmp);
3543 tcg_temp_free_i64(tmp);
3544 break;
3545 case 0x87: /* DLGR R1,R2 [RRE] */
3546 tmp32_1 = tcg_const_i32(r1);
3547 tmp = load_reg(r2);
3548 gen_helper_dlg(tmp32_1, tmp);
3549 tcg_temp_free_i64(tmp);
3550 tcg_temp_free_i32(tmp32_1);
3551 break;
3552 case 0x88: /* ALCGR R1,R2 [RRE] */
3553 tmp = load_reg(r1);
3554 tmp2 = load_reg(r2);
3555 tmp3 = tcg_temp_new_i64();
3556 gen_op_calc_cc(s);
3557 tcg_gen_extu_i32_i64(tmp3, cc_op);
3558 tcg_gen_shri_i64(tmp3, tmp3, 1);
3559 tcg_gen_andi_i64(tmp3, tmp3, 1);
3560 tcg_gen_add_i64(tmp3, tmp2, tmp3);
3561 tcg_gen_add_i64(tmp3, tmp, tmp3);
3562 store_reg(r1, tmp3);
3563 set_cc_addu64(s, tmp, tmp2, tmp3);
3564 tcg_temp_free_i64(tmp);
3565 tcg_temp_free_i64(tmp2);
3566 tcg_temp_free_i64(tmp3);
3567 break;
3568 case 0x89: /* SLBGR R1,R2 [RRE] */
3569 tmp = load_reg(r1);
3570 tmp2 = load_reg(r2);
3571 tmp32_1 = tcg_const_i32(r1);
3572 gen_op_calc_cc(s);
3573 gen_helper_slbg(cc_op, cc_op, tmp32_1, tmp, tmp2);
3574 set_cc_static(s);
3575 tcg_temp_free_i64(tmp);
3576 tcg_temp_free_i64(tmp2);
3577 tcg_temp_free_i32(tmp32_1);
3578 break;
3579 case 0x94: /* LLCR R1,R2 [RRE] */
3580 tmp32_1 = load_reg32(r2);
3581 tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xff);
3582 store_reg32(r1, tmp32_1);
3583 tcg_temp_free_i32(tmp32_1);
3584 break;
3585 case 0x95: /* LLHR R1,R2 [RRE] */
3586 tmp32_1 = load_reg32(r2);
3587 tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xffff);
3588 store_reg32(r1, tmp32_1);
3589 tcg_temp_free_i32(tmp32_1);
3590 break;
3591 case 0x96: /* MLR R1,R2 [RRE] */
3592 /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
3593 tmp2 = load_reg(r2);
3594 tmp3 = load_reg((r1 + 1) & 15);
3595 tcg_gen_ext32u_i64(tmp2, tmp2);
3596 tcg_gen_ext32u_i64(tmp3, tmp3);
3597 tcg_gen_mul_i64(tmp2, tmp2, tmp3);
3598 store_reg32_i64((r1 + 1) & 15, tmp2);
3599 tcg_gen_shri_i64(tmp2, tmp2, 32);
3600 store_reg32_i64(r1, tmp2);
3601 tcg_temp_free_i64(tmp2);
3602 tcg_temp_free_i64(tmp3);
3603 break;
3604 case 0x97: /* DLR R1,R2 [RRE] */
3605 /* reg(r1) = reg(r1, r1+1) % reg(r2) */
3606 /* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
3607 tmp = load_reg(r1);
3608 tmp2 = load_reg(r2);
3609 tmp3 = load_reg((r1 + 1) & 15);
3610 tcg_gen_ext32u_i64(tmp2, tmp2);
3611 tcg_gen_ext32u_i64(tmp3, tmp3);
3612 tcg_gen_shli_i64(tmp, tmp, 32);
3613 tcg_gen_or_i64(tmp, tmp, tmp3);
3614
3615 tcg_gen_rem_i64(tmp3, tmp, tmp2);
3616 tcg_gen_div_i64(tmp, tmp, tmp2);
3617 store_reg32_i64((r1 + 1) & 15, tmp);
3618 store_reg32_i64(r1, tmp3);
3619 tcg_temp_free_i64(tmp);
3620 tcg_temp_free_i64(tmp2);
3621 tcg_temp_free_i64(tmp3);
3622 break;
3623 case 0x98: /* ALCR R1,R2 [RRE] */
3624 tmp32_1 = load_reg32(r1);
3625 tmp32_2 = load_reg32(r2);
3626 tmp32_3 = tcg_temp_new_i32();
3627 /* XXX possible optimization point */
3628 gen_op_calc_cc(s);
3629 gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2);
3630 set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
3631 store_reg32(r1, tmp32_3);
3632 tcg_temp_free_i32(tmp32_1);
3633 tcg_temp_free_i32(tmp32_2);
3634 tcg_temp_free_i32(tmp32_3);
3635 break;
3636 case 0x99: /* SLBR R1,R2 [RRE] */
3637 tmp32_1 = load_reg32(r2);
3638 tmp32_2 = tcg_const_i32(r1);
3639 gen_op_calc_cc(s);
3640 gen_helper_slb(cc_op, cc_op, tmp32_2, tmp32_1);
3641 set_cc_static(s);
3642 tcg_temp_free_i32(tmp32_1);
3643 tcg_temp_free_i32(tmp32_2);
3644 break;
3645 default:
3646 LOG_DISAS("illegal b9 operation 0x%x\n", op);
3647 gen_illegal_opcode(s, 2);
3648 break;
3649 }
3650}
3651
3652static void disas_c0(DisasContext *s, int op, int r1, int i2)
3653{
3654 TCGv_i64 tmp;
3655 TCGv_i32 tmp32_1, tmp32_2;
3656 uint64_t target = s->pc + i2 * 2LL;
3657 int l1;
3658
3659 LOG_DISAS("disas_c0: op 0x%x r1 %d i2 %d\n", op, r1, i2);
3660
3661 switch (op) {
3662 case 0: /* larl r1, i2 */
3663 tmp = tcg_const_i64(target);
3664 store_reg(r1, tmp);
3665 tcg_temp_free_i64(tmp);
3666 break;
3667 case 0x1: /* LGFI R1,I2 [RIL] */
3668 tmp = tcg_const_i64((int64_t)i2);
3669 store_reg(r1, tmp);
3670 tcg_temp_free_i64(tmp);
3671 break;
3672 case 0x4: /* BRCL M1,I2 [RIL] */
3673 /* m1 & (1 << (3 - cc)) */
3674 tmp32_1 = tcg_const_i32(3);
3675 tmp32_2 = tcg_const_i32(1);
3676 gen_op_calc_cc(s);
3677 tcg_gen_sub_i32(tmp32_1, tmp32_1, cc_op);
3678 tcg_gen_shl_i32(tmp32_2, tmp32_2, tmp32_1);
3679 tcg_temp_free_i32(tmp32_1);
3680 tmp32_1 = tcg_const_i32(r1); /* m1 == r1 */
3681 tcg_gen_and_i32(tmp32_1, tmp32_1, tmp32_2);
3682 l1 = gen_new_label();
3683 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1);
3684 gen_goto_tb(s, 0, target);
3685 gen_set_label(l1);
3686 gen_goto_tb(s, 1, s->pc + 6);
3687 s->is_jmp = DISAS_TB_JUMP;
3688 tcg_temp_free_i32(tmp32_1);
3689 tcg_temp_free_i32(tmp32_2);
3690 break;
3691 case 0x5: /* brasl r1, i2 */
3692 tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 6));
3693 store_reg(r1, tmp);
3694 tcg_temp_free_i64(tmp);
3695 gen_goto_tb(s, 0, target);
3696 s->is_jmp = DISAS_TB_JUMP;
3697 break;
3698 case 0x7: /* XILF R1,I2 [RIL] */
3699 case 0xb: /* NILF R1,I2 [RIL] */
3700 case 0xd: /* OILF R1,I2 [RIL] */
3701 tmp32_1 = load_reg32(r1);
3702 switch (op) {
3703 case 0x7:
3704 tcg_gen_xori_i32(tmp32_1, tmp32_1, (uint32_t)i2);
3705 break;
3706 case 0xb:
3707 tcg_gen_andi_i32(tmp32_1, tmp32_1, (uint32_t)i2);
3708 break;
3709 case 0xd:
3710 tcg_gen_ori_i32(tmp32_1, tmp32_1, (uint32_t)i2);
3711 break;
3712 default:
3713 tcg_abort();
3714 }
3715 store_reg32(r1, tmp32_1);
3716 set_cc_nz_u32(s, tmp32_1);
3717 tcg_temp_free_i32(tmp32_1);
3718 break;
3719 case 0x9: /* IILF R1,I2 [RIL] */
3720 tmp32_1 = tcg_const_i32((uint32_t)i2);
3721 store_reg32(r1, tmp32_1);
3722 tcg_temp_free_i32(tmp32_1);
3723 break;
3724 case 0xa: /* NIHF R1,I2 [RIL] */
3725 tmp = load_reg(r1);
3726 tmp32_1 = tcg_temp_new_i32();
3727 tcg_gen_andi_i64(tmp, tmp, (((uint64_t)((uint32_t)i2)) << 32)
3728 | 0xffffffffULL);
3729 store_reg(r1, tmp);
3730 tcg_gen_shri_i64(tmp, tmp, 32);
3731 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
3732 set_cc_nz_u32(s, tmp32_1);
3733 tcg_temp_free_i64(tmp);
3734 tcg_temp_free_i32(tmp32_1);
3735 break;
3736 case 0xe: /* LLIHF R1,I2 [RIL] */
3737 tmp = tcg_const_i64(((uint64_t)(uint32_t)i2) << 32);
3738 store_reg(r1, tmp);
3739 tcg_temp_free_i64(tmp);
3740 break;
3741 case 0xf: /* LLILF R1,I2 [RIL] */
3742 tmp = tcg_const_i64((uint32_t)i2);
3743 store_reg(r1, tmp);
3744 tcg_temp_free_i64(tmp);
3745 break;
3746 default:
3747 LOG_DISAS("illegal c0 operation 0x%x\n", op);
3748 gen_illegal_opcode(s, 3);
3749 break;
3750 }
3751}
3752
3753static void disas_c2(DisasContext *s, int op, int r1, int i2)
3754{
3755 TCGv_i64 tmp, tmp2, tmp3;
3756 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
3757
3758 switch (op) {
3759 case 0x4: /* SLGFI R1,I2 [RIL] */
3760 case 0xa: /* ALGFI R1,I2 [RIL] */
3761 tmp = load_reg(r1);
3762 tmp2 = tcg_const_i64((uint64_t)(uint32_t)i2);
3763 tmp3 = tcg_temp_new_i64();
3764 switch (op) {
3765 case 0x4:
3766 tcg_gen_sub_i64(tmp3, tmp, tmp2);
3767 set_cc_subu64(s, tmp, tmp2, tmp3);
3768 break;
3769 case 0xa:
3770 tcg_gen_add_i64(tmp3, tmp, tmp2);
3771 set_cc_addu64(s, tmp, tmp2, tmp3);
3772 break;
3773 default:
3774 tcg_abort();
3775 }
3776 store_reg(r1, tmp3);
3777 tcg_temp_free_i64(tmp);
3778 tcg_temp_free_i64(tmp2);
3779 tcg_temp_free_i64(tmp3);
3780 break;
3781 case 0x5: /* SLFI R1,I2 [RIL] */
3782 case 0xb: /* ALFI R1,I2 [RIL] */
3783 tmp32_1 = load_reg32(r1);
3784 tmp32_2 = tcg_const_i32(i2);
3785 tmp32_3 = tcg_temp_new_i32();
3786 switch (op) {
3787 case 0x5:
3788 tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
3789 set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3);
3790 break;
3791 case 0xb:
3792 tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
3793 set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
3794 break;
3795 default:
3796 tcg_abort();
3797 }
3798 store_reg32(r1, tmp32_3);
3799 tcg_temp_free_i32(tmp32_1);
3800 tcg_temp_free_i32(tmp32_2);
3801 tcg_temp_free_i32(tmp32_3);
3802 break;
3803 case 0xc: /* CGFI R1,I2 [RIL] */
3804 tmp = load_reg(r1);
3805 cmp_s64c(s, tmp, (int64_t)i2);
3806 tcg_temp_free_i64(tmp);
3807 break;
3808 case 0xe: /* CLGFI R1,I2 [RIL] */
3809 tmp = load_reg(r1);
3810 cmp_u64c(s, tmp, (uint64_t)(uint32_t)i2);
3811 tcg_temp_free_i64(tmp);
3812 break;
3813 case 0xd: /* CFI R1,I2 [RIL] */
3814 tmp32_1 = load_reg32(r1);
3815 cmp_s32c(s, tmp32_1, i2);
3816 tcg_temp_free_i32(tmp32_1);
3817 break;
3818 case 0xf: /* CLFI R1,I2 [RIL] */
3819 tmp32_1 = load_reg32(r1);
3820 cmp_u32c(s, tmp32_1, i2);
3821 tcg_temp_free_i32(tmp32_1);
3822 break;
3823 default:
3824 LOG_DISAS("illegal c2 operation 0x%x\n", op);
3825 gen_illegal_opcode(s, 3);
3826 break;
3827 }
3828}
3829
3830static void gen_and_or_xor_i32(int opc, TCGv_i32 tmp, TCGv_i32 tmp2)
3831{
3832 switch (opc & 0xf) {
3833 case 0x4:
3834 tcg_gen_and_i32(tmp, tmp, tmp2);
3835 break;
3836 case 0x6:
3837 tcg_gen_or_i32(tmp, tmp, tmp2);
3838 break;
3839 case 0x7:
3840 tcg_gen_xor_i32(tmp, tmp, tmp2);
3841 break;
3842 default:
3843 tcg_abort();
3844 }
3845}
3846
3847static void disas_s390_insn(DisasContext *s)
3848{
3849 TCGv_i64 tmp, tmp2, tmp3, tmp4;
3850 TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4;
3851 unsigned char opc;
3852 uint64_t insn;
3853 int op, r1, r2, r3, d1, d2, x2, b1, b2, i, i2, r1b;
3854 TCGv_i32 vl;
3855 int ilc;
3856 int l1;
3857
3858 opc = ldub_code(s->pc);
3859 LOG_DISAS("opc 0x%x\n", opc);
3860
3861 ilc = get_ilc(opc);
3862
3863 switch (opc) {
3864#ifndef CONFIG_USER_ONLY
3865 case 0x01: /* SAM */
3866 insn = ld_code2(s->pc);
3867 /* set addressing mode, but we only do 64bit anyways */
3868 break;
3869#endif
3870 case 0x6: /* BCTR R1,R2 [RR] */
3871 insn = ld_code2(s->pc);
3872 decode_rr(s, insn, &r1, &r2);
3873 tmp32_1 = load_reg32(r1);
3874 tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
3875 store_reg32(r1, tmp32_1);
3876
3877 if (r2) {
3878 gen_update_cc_op(s);
3879 l1 = gen_new_label();
3880 tcg_gen_brcondi_i32(TCG_COND_NE, tmp32_1, 0, l1);
3881
3882 /* not taking the branch, jump to after the instruction */
3883 gen_goto_tb(s, 0, s->pc + 2);
3884 gen_set_label(l1);
3885
3886 /* take the branch, move R2 into psw.addr */
3887 tmp32_1 = load_reg32(r2);
3888 tmp = tcg_temp_new_i64();
3889 tcg_gen_extu_i32_i64(tmp, tmp32_1);
3890 tcg_gen_mov_i64(psw_addr, tmp);
3891 s->is_jmp = DISAS_JUMP;
3892 tcg_temp_free_i32(tmp32_1);
3893 tcg_temp_free_i64(tmp);
3894 }
3895 break;
3896 case 0x7: /* BCR M1,R2 [RR] */
3897 insn = ld_code2(s->pc);
3898 decode_rr(s, insn, &r1, &r2);
3899 if (r2) {
3900 tmp = load_reg(r2);
3901 gen_bcr(s, r1, tmp, s->pc);
3902 tcg_temp_free_i64(tmp);
3903 s->is_jmp = DISAS_TB_JUMP;
3904 } else {
3905 /* XXX: "serialization and checkpoint-synchronization function"? */
3906 }
3907 break;
3908 case 0xa: /* SVC I [RR] */
3909 insn = ld_code2(s->pc);
3910 debug_insn(insn);
3911 i = insn & 0xff;
3912 update_psw_addr(s);
3913 gen_op_calc_cc(s);
3914 tmp32_1 = tcg_const_i32(i);
3915 tmp32_2 = tcg_const_i32(ilc * 2);
3916 tmp32_3 = tcg_const_i32(EXCP_SVC);
3917 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, int_svc_code));
3918 tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUState, int_svc_ilc));
3919 gen_helper_exception(tmp32_3);
3920 s->is_jmp = DISAS_EXCP;
3921 tcg_temp_free_i32(tmp32_1);
3922 tcg_temp_free_i32(tmp32_2);
3923 tcg_temp_free_i32(tmp32_3);
3924 break;
3925 case 0xd: /* BASR R1,R2 [RR] */
3926 insn = ld_code2(s->pc);
3927 decode_rr(s, insn, &r1, &r2);
3928 tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 2));
3929 store_reg(r1, tmp);
3930 if (r2) {
3931 tmp2 = load_reg(r2);
3932 tcg_gen_mov_i64(psw_addr, tmp2);
3933 tcg_temp_free_i64(tmp2);
3934 s->is_jmp = DISAS_JUMP;
3935 }
3936 tcg_temp_free_i64(tmp);
3937 break;
3938 case 0xe: /* MVCL R1,R2 [RR] */
3939 insn = ld_code2(s->pc);
3940 decode_rr(s, insn, &r1, &r2);
3941 tmp32_1 = tcg_const_i32(r1);
3942 tmp32_2 = tcg_const_i32(r2);
3943 potential_page_fault(s);
3944 gen_helper_mvcl(cc_op, tmp32_1, tmp32_2);
3945 set_cc_static(s);
3946 tcg_temp_free_i32(tmp32_1);
3947 tcg_temp_free_i32(tmp32_2);
3948 break;
3949 case 0x10: /* LPR R1,R2 [RR] */
3950 insn = ld_code2(s->pc);
3951 decode_rr(s, insn, &r1, &r2);
3952 tmp32_1 = load_reg32(r2);
3953 set_cc_abs32(s, tmp32_1);
3954 gen_helper_abs_i32(tmp32_1, tmp32_1);
3955 store_reg32(r1, tmp32_1);
3956 tcg_temp_free_i32(tmp32_1);
3957 break;
3958 case 0x11: /* LNR R1,R2 [RR] */
3959 insn = ld_code2(s->pc);
3960 decode_rr(s, insn, &r1, &r2);
3961 tmp32_1 = load_reg32(r2);
3962 set_cc_nabs32(s, tmp32_1);
3963 gen_helper_nabs_i32(tmp32_1, tmp32_1);
3964 store_reg32(r1, tmp32_1);
3965 tcg_temp_free_i32(tmp32_1);
3966 break;
3967 case 0x12: /* LTR R1,R2 [RR] */
3968 insn = ld_code2(s->pc);
3969 decode_rr(s, insn, &r1, &r2);
3970 tmp32_1 = load_reg32(r2);
3971 if (r1 != r2) {
3972 store_reg32(r1, tmp32_1);
3973 }
3974 set_cc_s32(s, tmp32_1);
3975 tcg_temp_free_i32(tmp32_1);
3976 break;
3977 case 0x13: /* LCR R1,R2 [RR] */
3978 insn = ld_code2(s->pc);
3979 decode_rr(s, insn, &r1, &r2);
3980 tmp32_1 = load_reg32(r2);
3981 tcg_gen_neg_i32(tmp32_1, tmp32_1);
3982 store_reg32(r1, tmp32_1);
3983 set_cc_comp32(s, tmp32_1);
3984 tcg_temp_free_i32(tmp32_1);
3985 break;
3986 case 0x14: /* NR R1,R2 [RR] */
3987 case 0x16: /* OR R1,R2 [RR] */
3988 case 0x17: /* XR R1,R2 [RR] */
3989 insn = ld_code2(s->pc);
3990 decode_rr(s, insn, &r1, &r2);
3991 tmp32_2 = load_reg32(r2);
3992 tmp32_1 = load_reg32(r1);
3993 gen_and_or_xor_i32(opc, tmp32_1, tmp32_2);
3994 store_reg32(r1, tmp32_1);
3995 set_cc_nz_u32(s, tmp32_1);
3996 tcg_temp_free_i32(tmp32_1);
3997 tcg_temp_free_i32(tmp32_2);
3998 break;
3999 case 0x18: /* LR R1,R2 [RR] */
4000 insn = ld_code2(s->pc);
4001 decode_rr(s, insn, &r1, &r2);
4002 tmp32_1 = load_reg32(r2);
4003 store_reg32(r1, tmp32_1);
4004 tcg_temp_free_i32(tmp32_1);
4005 break;
4006 case 0x15: /* CLR R1,R2 [RR] */
4007 case 0x19: /* CR R1,R2 [RR] */
4008 insn = ld_code2(s->pc);
4009 decode_rr(s, insn, &r1, &r2);
4010 tmp32_1 = load_reg32(r1);
4011 tmp32_2 = load_reg32(r2);
4012 if (opc == 0x15) {
4013 cmp_u32(s, tmp32_1, tmp32_2);
4014 } else {
4015 cmp_s32(s, tmp32_1, tmp32_2);
4016 }
4017 tcg_temp_free_i32(tmp32_1);
4018 tcg_temp_free_i32(tmp32_2);
4019 break;
4020 case 0x1a: /* AR R1,R2 [RR] */
4021 case 0x1e: /* ALR R1,R2 [RR] */
4022 insn = ld_code2(s->pc);
4023 decode_rr(s, insn, &r1, &r2);
4024 tmp32_1 = load_reg32(r1);
4025 tmp32_2 = load_reg32(r2);
4026 tmp32_3 = tcg_temp_new_i32();
4027 tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
4028 store_reg32(r1, tmp32_3);
4029 if (opc == 0x1a) {
4030 set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
4031 } else {
4032 set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
4033 }
4034 tcg_temp_free_i32(tmp32_1);
4035 tcg_temp_free_i32(tmp32_2);
4036 tcg_temp_free_i32(tmp32_3);
4037 break;
4038 case 0x1b: /* SR R1,R2 [RR] */
4039 case 0x1f: /* SLR R1,R2 [RR] */
4040 insn = ld_code2(s->pc);
4041 decode_rr(s, insn, &r1, &r2);
4042 tmp32_1 = load_reg32(r1);
4043 tmp32_2 = load_reg32(r2);
4044 tmp32_3 = tcg_temp_new_i32();
4045 tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
4046 store_reg32(r1, tmp32_3);
4047 if (opc == 0x1b) {
4048 set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
4049 } else {
4050 set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3);
4051 }
4052 tcg_temp_free_i32(tmp32_1);
4053 tcg_temp_free_i32(tmp32_2);
4054 tcg_temp_free_i32(tmp32_3);
4055 break;
4056 case 0x1c: /* MR R1,R2 [RR] */
4057 /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
4058 insn = ld_code2(s->pc);
4059 decode_rr(s, insn, &r1, &r2);
4060 tmp2 = load_reg(r2);
4061 tmp3 = load_reg((r1 + 1) & 15);
4062 tcg_gen_ext32s_i64(tmp2, tmp2);
4063 tcg_gen_ext32s_i64(tmp3, tmp3);
4064 tcg_gen_mul_i64(tmp2, tmp2, tmp3);
4065 store_reg32_i64((r1 + 1) & 15, tmp2);
4066 tcg_gen_shri_i64(tmp2, tmp2, 32);
4067 store_reg32_i64(r1, tmp2);
4068 tcg_temp_free_i64(tmp2);
4069 tcg_temp_free_i64(tmp3);
4070 break;
4071 case 0x1d: /* DR R1,R2 [RR] */
4072 insn = ld_code2(s->pc);
4073 decode_rr(s, insn, &r1, &r2);
4074 tmp32_1 = load_reg32(r1);
4075 tmp32_2 = load_reg32(r1 + 1);
4076 tmp32_3 = load_reg32(r2);
4077
4078 tmp = tcg_temp_new_i64(); /* dividend */
4079 tmp2 = tcg_temp_new_i64(); /* divisor */
4080 tmp3 = tcg_temp_new_i64();
4081
4082 /* dividend is r(r1 << 32) | r(r1 + 1) */
4083 tcg_gen_extu_i32_i64(tmp, tmp32_1);
4084 tcg_gen_extu_i32_i64(tmp2, tmp32_2);
4085 tcg_gen_shli_i64(tmp, tmp, 32);
4086 tcg_gen_or_i64(tmp, tmp, tmp2);
4087
4088 /* divisor is r(r2) */
4089 tcg_gen_ext_i32_i64(tmp2, tmp32_3);
4090
4091 tcg_gen_div_i64(tmp3, tmp, tmp2);
4092 tcg_gen_rem_i64(tmp, tmp, tmp2);
4093
4094 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4095 tcg_gen_trunc_i64_i32(tmp32_2, tmp3);
4096
4097 store_reg32(r1, tmp32_1); /* remainder */
4098 store_reg32(r1 + 1, tmp32_2); /* quotient */
4099 tcg_temp_free_i32(tmp32_1);
4100 tcg_temp_free_i32(tmp32_2);
4101 tcg_temp_free_i32(tmp32_3);
4102 tcg_temp_free_i64(tmp);
4103 tcg_temp_free_i64(tmp2);
4104 tcg_temp_free_i64(tmp3);
4105 break;
4106 case 0x28: /* LDR R1,R2 [RR] */
4107 insn = ld_code2(s->pc);
4108 decode_rr(s, insn, &r1, &r2);
4109 tmp = load_freg(r2);
4110 store_freg(r1, tmp);
4111 tcg_temp_free_i64(tmp);
4112 break;
4113 case 0x38: /* LER R1,R2 [RR] */
4114 insn = ld_code2(s->pc);
4115 decode_rr(s, insn, &r1, &r2);
4116 tmp32_1 = load_freg32(r2);
4117 store_freg32(r1, tmp32_1);
4118 tcg_temp_free_i32(tmp32_1);
4119 break;
4120 case 0x40: /* STH R1,D2(X2,B2) [RX] */
4121 insn = ld_code4(s->pc);
4122 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4123 tmp2 = load_reg(r1);
4124 tcg_gen_qemu_st16(tmp2, tmp, get_mem_index(s));
4125 tcg_temp_free_i64(tmp);
4126 tcg_temp_free_i64(tmp2);
4127 break;
4128 case 0x41: /* la */
4129 insn = ld_code4(s->pc);
4130 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4131 store_reg(r1, tmp); /* FIXME: 31/24-bit addressing */
4132 tcg_temp_free_i64(tmp);
4133 break;
4134 case 0x42: /* STC R1,D2(X2,B2) [RX] */
4135 insn = ld_code4(s->pc);
4136 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4137 tmp2 = load_reg(r1);
4138 tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4139 tcg_temp_free_i64(tmp);
4140 tcg_temp_free_i64(tmp2);
4141 break;
4142 case 0x43: /* IC R1,D2(X2,B2) [RX] */
4143 insn = ld_code4(s->pc);
4144 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4145 tmp2 = tcg_temp_new_i64();
4146 tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4147 store_reg8(r1, tmp2);
4148 tcg_temp_free_i64(tmp);
4149 tcg_temp_free_i64(tmp2);
4150 break;
4151 case 0x44: /* EX R1,D2(X2,B2) [RX] */
4152 insn = ld_code4(s->pc);
4153 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4154 tmp2 = load_reg(r1);
4155 tmp3 = tcg_const_i64(s->pc + 4);
4156 update_psw_addr(s);
4157 gen_op_calc_cc(s);
4158 gen_helper_ex(cc_op, cc_op, tmp2, tmp, tmp3);
4159 set_cc_static(s);
4160 tcg_temp_free_i64(tmp);
4161 tcg_temp_free_i64(tmp2);
4162 tcg_temp_free_i64(tmp3);
4163 break;
4164 case 0x46: /* BCT R1,D2(X2,B2) [RX] */
4165 insn = ld_code4(s->pc);
4166 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4167 tcg_temp_free_i64(tmp);
4168
4169 tmp32_1 = load_reg32(r1);
4170 tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
4171 store_reg32(r1, tmp32_1);
4172
4173 gen_update_cc_op(s);
4174 l1 = gen_new_label();
4175 tcg_gen_brcondi_i32(TCG_COND_NE, tmp32_1, 0, l1);
4176
4177 /* not taking the branch, jump to after the instruction */
4178 gen_goto_tb(s, 0, s->pc + 4);
4179 gen_set_label(l1);
4180
4181 /* take the branch, move R2 into psw.addr */
4182 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4183 tcg_gen_mov_i64(psw_addr, tmp);
4184 s->is_jmp = DISAS_JUMP;
4185 tcg_temp_free_i32(tmp32_1);
4186 tcg_temp_free_i64(tmp);
4187 break;
4188 case 0x47: /* BC M1,D2(X2,B2) [RX] */
4189 insn = ld_code4(s->pc);
4190 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4191 gen_bcr(s, r1, tmp, s->pc + 4);
4192 tcg_temp_free_i64(tmp);
4193 s->is_jmp = DISAS_TB_JUMP;
4194 break;
4195 case 0x48: /* LH R1,D2(X2,B2) [RX] */
4196 insn = ld_code4(s->pc);
4197 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4198 tmp2 = tcg_temp_new_i64();
4199 tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
4200 store_reg32_i64(r1, tmp2);
4201 tcg_temp_free_i64(tmp);
4202 tcg_temp_free_i64(tmp2);
4203 break;
4204 case 0x49: /* CH R1,D2(X2,B2) [RX] */
4205 insn = ld_code4(s->pc);
4206 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4207 tmp32_1 = load_reg32(r1);
4208 tmp32_2 = tcg_temp_new_i32();
4209 tmp2 = tcg_temp_new_i64();
4210 tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
4211 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4212 cmp_s32(s, tmp32_1, tmp32_2);
4213 tcg_temp_free_i32(tmp32_1);
4214 tcg_temp_free_i32(tmp32_2);
4215 tcg_temp_free_i64(tmp);
4216 tcg_temp_free_i64(tmp2);
4217 break;
4218 case 0x4a: /* AH R1,D2(X2,B2) [RX] */
4219 case 0x4b: /* SH R1,D2(X2,B2) [RX] */
4220 case 0x4c: /* MH R1,D2(X2,B2) [RX] */
4221 insn = ld_code4(s->pc);
4222 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4223 tmp2 = tcg_temp_new_i64();
4224 tmp32_1 = load_reg32(r1);
4225 tmp32_2 = tcg_temp_new_i32();
4226 tmp32_3 = tcg_temp_new_i32();
4227
4228 tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
4229 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4230 switch (opc) {
4231 case 0x4a:
4232 tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
4233 set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
4234 break;
4235 case 0x4b:
4236 tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
4237 set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
4238 break;
4239 case 0x4c:
4240 tcg_gen_mul_i32(tmp32_3, tmp32_1, tmp32_2);
4241 break;
4242 default:
4243 tcg_abort();
4244 }
4245 store_reg32(r1, tmp32_3);
4246
4247 tcg_temp_free_i32(tmp32_1);
4248 tcg_temp_free_i32(tmp32_2);
4249 tcg_temp_free_i32(tmp32_3);
4250 tcg_temp_free_i64(tmp);
4251 tcg_temp_free_i64(tmp2);
4252 break;
4253 case 0x4d: /* BAS R1,D2(X2,B2) [RX] */
4254 insn = ld_code4(s->pc);
4255 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4256 tmp2 = tcg_const_i64(pc_to_link_info(s, s->pc + 4));
4257 store_reg(r1, tmp2);
4258 tcg_gen_mov_i64(psw_addr, tmp);
4259 tcg_temp_free_i64(tmp);
4260 tcg_temp_free_i64(tmp2);
4261 s->is_jmp = DISAS_JUMP;
4262 break;
4263 case 0x4e: /* CVD R1,D2(X2,B2) [RX] */
4264 insn = ld_code4(s->pc);
4265 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4266 tmp2 = tcg_temp_new_i64();
4267 tmp32_1 = tcg_temp_new_i32();
4268 tcg_gen_trunc_i64_i32(tmp32_1, regs[r1]);
4269 gen_helper_cvd(tmp2, tmp32_1);
4270 tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s));
4271 tcg_temp_free_i64(tmp);
4272 tcg_temp_free_i64(tmp2);
4273 tcg_temp_free_i32(tmp32_1);
4274 break;
4275 case 0x50: /* st r1, d2(x2, b2) */
4276 insn = ld_code4(s->pc);
4277 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4278 tmp2 = load_reg(r1);
4279 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
4280 tcg_temp_free_i64(tmp);
4281 tcg_temp_free_i64(tmp2);
4282 break;
4283 case 0x55: /* CL R1,D2(X2,B2) [RX] */
4284 insn = ld_code4(s->pc);
4285 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4286 tmp2 = tcg_temp_new_i64();
4287 tmp32_1 = tcg_temp_new_i32();
4288 tmp32_2 = load_reg32(r1);
4289 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4290 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4291 cmp_u32(s, tmp32_2, tmp32_1);
4292 tcg_temp_free_i64(tmp);
4293 tcg_temp_free_i64(tmp2);
4294 tcg_temp_free_i32(tmp32_1);
4295 tcg_temp_free_i32(tmp32_2);
4296 break;
4297 case 0x54: /* N R1,D2(X2,B2) [RX] */
4298 case 0x56: /* O R1,D2(X2,B2) [RX] */
4299 case 0x57: /* X R1,D2(X2,B2) [RX] */
4300 insn = ld_code4(s->pc);
4301 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4302 tmp2 = tcg_temp_new_i64();
4303 tmp32_1 = load_reg32(r1);
4304 tmp32_2 = tcg_temp_new_i32();
4305 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4306 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4307 gen_and_or_xor_i32(opc, tmp32_1, tmp32_2);
4308 store_reg32(r1, tmp32_1);
4309 set_cc_nz_u32(s, tmp32_1);
4310 tcg_temp_free_i64(tmp);
4311 tcg_temp_free_i64(tmp2);
4312 tcg_temp_free_i32(tmp32_1);
4313 tcg_temp_free_i32(tmp32_2);
4314 break;
4315 case 0x58: /* l r1, d2(x2, b2) */
4316 insn = ld_code4(s->pc);
4317 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4318 tmp2 = tcg_temp_new_i64();
4319 tmp32_1 = tcg_temp_new_i32();
4320 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4321 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4322 store_reg32(r1, tmp32_1);
4323 tcg_temp_free_i64(tmp);
4324 tcg_temp_free_i64(tmp2);
4325 tcg_temp_free_i32(tmp32_1);
4326 break;
4327 case 0x59: /* C R1,D2(X2,B2) [RX] */
4328 insn = ld_code4(s->pc);
4329 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4330 tmp2 = tcg_temp_new_i64();
4331 tmp32_1 = tcg_temp_new_i32();
4332 tmp32_2 = load_reg32(r1);
4333 tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
4334 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4335 cmp_s32(s, tmp32_2, tmp32_1);
4336 tcg_temp_free_i64(tmp);
4337 tcg_temp_free_i64(tmp2);
4338 tcg_temp_free_i32(tmp32_1);
4339 tcg_temp_free_i32(tmp32_2);
4340 break;
4341 case 0x5a: /* A R1,D2(X2,B2) [RX] */
4342 case 0x5b: /* S R1,D2(X2,B2) [RX] */
4343 case 0x5e: /* AL R1,D2(X2,B2) [RX] */
4344 case 0x5f: /* SL R1,D2(X2,B2) [RX] */
4345 insn = ld_code4(s->pc);
4346 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4347 tmp32_1 = load_reg32(r1);
4348 tmp32_2 = tcg_temp_new_i32();
4349 tmp32_3 = tcg_temp_new_i32();
4350 tcg_gen_qemu_ld32s(tmp, tmp, get_mem_index(s));
4351 tcg_gen_trunc_i64_i32(tmp32_2, tmp);
4352 switch (opc) {
4353 case 0x5a:
4354 case 0x5e:
4355 tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
4356 break;
4357 case 0x5b:
4358 case 0x5f:
4359 tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
4360 break;
4361 default:
4362 tcg_abort();
4363 }
4364 store_reg32(r1, tmp32_3);
4365 switch (opc) {
4366 case 0x5a:
4367 set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
4368 break;
4369 case 0x5e:
4370 set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
4371 break;
4372 case 0x5b:
4373 set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
4374 break;
4375 case 0x5f:
4376 set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3);
4377 break;
4378 default:
4379 tcg_abort();
4380 }
4381 tcg_temp_free_i64(tmp);
4382 tcg_temp_free_i32(tmp32_1);
4383 tcg_temp_free_i32(tmp32_2);
4384 tcg_temp_free_i32(tmp32_3);
4385 break;
4386 case 0x5c: /* M R1,D2(X2,B2) [RX] */
4387 /* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
4388 insn = ld_code4(s->pc);
4389 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4390 tmp2 = tcg_temp_new_i64();
4391 tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
4392 tmp3 = load_reg((r1 + 1) & 15);
4393 tcg_gen_ext32s_i64(tmp2, tmp2);
4394 tcg_gen_ext32s_i64(tmp3, tmp3);
4395 tcg_gen_mul_i64(tmp2, tmp2, tmp3);
4396 store_reg32_i64((r1 + 1) & 15, tmp2);
4397 tcg_gen_shri_i64(tmp2, tmp2, 32);
4398 store_reg32_i64(r1, tmp2);
4399 tcg_temp_free_i64(tmp);
4400 tcg_temp_free_i64(tmp2);
4401 tcg_temp_free_i64(tmp3);
4402 break;
4403 case 0x5d: /* D R1,D2(X2,B2) [RX] */
4404 insn = ld_code4(s->pc);
4405 tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4406 tmp32_1 = load_reg32(r1);
4407 tmp32_2 = load_reg32(r1 + 1);
4408
4409 tmp = tcg_temp_new_i64();
4410 tmp2 = tcg_temp_new_i64();
4411
4412 /* dividend is r(r1 << 32) | r(r1 + 1) */
4413 tcg_gen_extu_i32_i64(tmp, tmp32_1);
4414 tcg_gen_extu_i32_i64(tmp2, tmp32_2);
4415 tcg_gen_shli_i64(tmp, tmp, 32);
4416 tcg_gen_or_i64(tmp, tmp, tmp2);
4417
4418 /* divisor is in memory */
4419 tcg_gen_qemu_ld32s(tmp2, tmp3, get_mem_index(s));
4420
4421 /* XXX divisor == 0 -> FixP divide exception */
4422
4423 tcg_gen_div_i64(tmp3, tmp, tmp2);
4424 tcg_gen_rem_i64(tmp, tmp, tmp2);
4425
4426 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4427 tcg_gen_trunc_i64_i32(tmp32_2, tmp3);
4428
4429 store_reg32(r1, tmp32_1); /* remainder */
4430 store_reg32(r1 + 1, tmp32_2); /* quotient */
4431 tcg_temp_free_i32(tmp32_1);
4432 tcg_temp_free_i32(tmp32_2);
4433 tcg_temp_free_i64(tmp);
4434 tcg_temp_free_i64(tmp2);
4435 tcg_temp_free_i64(tmp3);
4436 break;
4437 case 0x60: /* STD R1,D2(X2,B2) [RX] */
4438 insn = ld_code4(s->pc);
4439 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4440 tmp2 = load_freg(r1);
4441 tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s));
4442 tcg_temp_free_i64(tmp);
4443 tcg_temp_free_i64(tmp2);
4444 break;
4445 case 0x68: /* LD R1,D2(X2,B2) [RX] */
4446 insn = ld_code4(s->pc);
4447 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4448 tmp2 = tcg_temp_new_i64();
4449 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
4450 store_freg(r1, tmp2);
4451 tcg_temp_free_i64(tmp);
4452 tcg_temp_free_i64(tmp2);
4453 break;
4454 case 0x70: /* STE R1,D2(X2,B2) [RX] */
4455 insn = ld_code4(s->pc);
4456 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4457 tmp2 = tcg_temp_new_i64();
4458 tmp32_1 = load_freg32(r1);
4459 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
4460 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
4461 tcg_temp_free_i64(tmp);
4462 tcg_temp_free_i64(tmp2);
4463 tcg_temp_free_i32(tmp32_1);
4464 break;
4465 case 0x71: /* MS R1,D2(X2,B2) [RX] */
4466 insn = ld_code4(s->pc);
4467 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4468 tmp2 = tcg_temp_new_i64();
4469 tmp32_1 = load_reg32(r1);
4470 tmp32_2 = tcg_temp_new_i32();
4471 tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
4472 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4473 tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
4474 store_reg32(r1, tmp32_1);
4475 tcg_temp_free_i64(tmp);
4476 tcg_temp_free_i64(tmp2);
4477 tcg_temp_free_i32(tmp32_1);
4478 tcg_temp_free_i32(tmp32_2);
4479 break;
4480 case 0x78: /* LE R1,D2(X2,B2) [RX] */
4481 insn = ld_code4(s->pc);
4482 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4483 tmp2 = tcg_temp_new_i64();
4484 tmp32_1 = tcg_temp_new_i32();
4485 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4486 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4487 store_freg32(r1, tmp32_1);
4488 tcg_temp_free_i64(tmp);
4489 tcg_temp_free_i64(tmp2);
4490 tcg_temp_free_i32(tmp32_1);
4491 break;
4492#ifndef CONFIG_USER_ONLY
4493 case 0x80: /* SSM D2(B2) [S] */
4494 /* Set System Mask */
4495 check_privileged(s, ilc);
4496 insn = ld_code4(s->pc);
4497 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4498 tmp = get_address(s, 0, b2, d2);
4499 tmp2 = tcg_temp_new_i64();
4500 tmp3 = tcg_temp_new_i64();
4501 tcg_gen_andi_i64(tmp3, psw_mask, ~0xff00000000000000ULL);
4502 tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4503 tcg_gen_shli_i64(tmp2, tmp2, 56);
4504 tcg_gen_or_i64(psw_mask, tmp3, tmp2);
4505 tcg_temp_free_i64(tmp);
4506 tcg_temp_free_i64(tmp2);
4507 tcg_temp_free_i64(tmp3);
4508 break;
4509 case 0x82: /* LPSW D2(B2) [S] */
4510 /* Load PSW */
4511 check_privileged(s, ilc);
4512 insn = ld_code4(s->pc);
4513 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4514 tmp = get_address(s, 0, b2, d2);
4515 tmp2 = tcg_temp_new_i64();
4516 tmp3 = tcg_temp_new_i64();
4517 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4518 tcg_gen_addi_i64(tmp, tmp, 4);
4519 tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s));
4520 gen_helper_load_psw(tmp2, tmp3);
4521 tcg_temp_free_i64(tmp);
4522 tcg_temp_free_i64(tmp2);
4523 tcg_temp_free_i64(tmp3);
4524 /* we need to keep cc_op intact */
4525 s->is_jmp = DISAS_JUMP;
4526 break;
4527 case 0x83: /* DIAG R1,R3,D2 [RS] */
4528 /* Diagnose call (KVM hypercall) */
4529 check_privileged(s, ilc);
4530 potential_page_fault(s);
4531 insn = ld_code4(s->pc);
4532 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4533 tmp32_1 = tcg_const_i32(insn & 0xfff);
4534 tmp2 = load_reg(2);
4535 tmp3 = load_reg(1);
4536 gen_helper_diag(tmp2, tmp32_1, tmp2, tmp3);
4537 store_reg(2, tmp2);
4538 tcg_temp_free_i32(tmp32_1);
4539 tcg_temp_free_i64(tmp2);
4540 tcg_temp_free_i64(tmp3);
4541 break;
4542#endif
4543 case 0x88: /* SRL R1,D2(B2) [RS] */
4544 case 0x89: /* SLL R1,D2(B2) [RS] */
4545 case 0x8a: /* SRA R1,D2(B2) [RS] */
4546 insn = ld_code4(s->pc);
4547 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4548 tmp = get_address(s, 0, b2, d2);
4549 tmp32_1 = load_reg32(r1);
4550 tmp32_2 = tcg_temp_new_i32();
4551 tcg_gen_trunc_i64_i32(tmp32_2, tmp);
4552 tcg_gen_andi_i32(tmp32_2, tmp32_2, 0x3f);
4553 switch (opc) {
4554 case 0x88:
4555 tcg_gen_shr_i32(tmp32_1, tmp32_1, tmp32_2);
4556 break;
4557 case 0x89:
4558 tcg_gen_shl_i32(tmp32_1, tmp32_1, tmp32_2);
4559 break;
4560 case 0x8a:
4561 tcg_gen_sar_i32(tmp32_1, tmp32_1, tmp32_2);
4562 set_cc_s32(s, tmp32_1);
4563 break;
4564 default:
4565 tcg_abort();
4566 }
4567 store_reg32(r1, tmp32_1);
4568 tcg_temp_free_i64(tmp);
4569 tcg_temp_free_i32(tmp32_1);
4570 tcg_temp_free_i32(tmp32_2);
4571 break;
4572 case 0x8c: /* SRDL R1,D2(B2) [RS] */
4573 case 0x8d: /* SLDL R1,D2(B2) [RS] */
4574 case 0x8e: /* SRDA R1,D2(B2) [RS] */
4575 insn = ld_code4(s->pc);
4576 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4577 tmp = get_address(s, 0, b2, d2); /* shift */
4578 tmp2 = tcg_temp_new_i64();
4579 tmp32_1 = load_reg32(r1);
4580 tmp32_2 = load_reg32(r1 + 1);
4581 tcg_gen_concat_i32_i64(tmp2, tmp32_2, tmp32_1); /* operand */
4582 switch (opc) {
4583 case 0x8c:
4584 tcg_gen_shr_i64(tmp2, tmp2, tmp);
4585 break;
4586 case 0x8d:
4587 tcg_gen_shl_i64(tmp2, tmp2, tmp);
4588 break;
4589 case 0x8e:
4590 tcg_gen_sar_i64(tmp2, tmp2, tmp);
4591 set_cc_s64(s, tmp2);
4592 break;
4593 }
4594 tcg_gen_shri_i64(tmp, tmp2, 32);
4595 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4596 store_reg32(r1, tmp32_1);
4597 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4598 store_reg32(r1 + 1, tmp32_2);
4599 break;
4600 case 0x98: /* LM R1,R3,D2(B2) [RS] */
4601 case 0x90: /* STM R1,R3,D2(B2) [RS] */
4602 insn = ld_code4(s->pc);
4603 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4604
4605 tmp = get_address(s, 0, b2, d2);
4606 tmp2 = tcg_temp_new_i64();
4607 tmp3 = tcg_const_i64(4);
4608 tmp4 = tcg_const_i64(0xffffffff00000000ULL);
4609 for (i = r1;; i = (i + 1) % 16) {
4610 if (opc == 0x98) {
4611 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4612 tcg_gen_and_i64(regs[i], regs[i], tmp4);
4613 tcg_gen_or_i64(regs[i], regs[i], tmp2);
4614 } else {
4615 tcg_gen_qemu_st32(regs[i], tmp, get_mem_index(s));
4616 }
4617 if (i == r3) {
4618 break;
4619 }
4620 tcg_gen_add_i64(tmp, tmp, tmp3);
4621 }
4622 tcg_temp_free_i64(tmp2);
4623 tcg_temp_free_i64(tmp3);
4624 tcg_temp_free_i64(tmp4);
4625 break;
4626 case 0x91: /* TM D1(B1),I2 [SI] */
4627 insn = ld_code4(s->pc);
4628 tmp = decode_si(s, insn, &i2, &b1, &d1);
4629 tmp2 = tcg_const_i64(i2);
4630 tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s));
4631 cmp_64(s, tmp, tmp2, CC_OP_TM_32);
4632 tcg_temp_free_i64(tmp);
4633 tcg_temp_free_i64(tmp2);
4634 break;
4635 case 0x92: /* MVI D1(B1),I2 [SI] */
4636 insn = ld_code4(s->pc);
4637 tmp = decode_si(s, insn, &i2, &b1, &d1);
4638 tmp2 = tcg_const_i64(i2);
4639 tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4640 tcg_temp_free_i64(tmp);
4641 tcg_temp_free_i64(tmp2);
4642 break;
4643 case 0x94: /* NI D1(B1),I2 [SI] */
4644 case 0x96: /* OI D1(B1),I2 [SI] */
4645 case 0x97: /* XI D1(B1),I2 [SI] */
4646 insn = ld_code4(s->pc);
4647 tmp = decode_si(s, insn, &i2, &b1, &d1);
4648 tmp2 = tcg_temp_new_i64();
4649 tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4650 switch (opc) {
4651 case 0x94:
4652 tcg_gen_andi_i64(tmp2, tmp2, i2);
4653 break;
4654 case 0x96:
4655 tcg_gen_ori_i64(tmp2, tmp2, i2);
4656 break;
4657 case 0x97:
4658 tcg_gen_xori_i64(tmp2, tmp2, i2);
4659 break;
4660 default:
4661 tcg_abort();
4662 }
4663 tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4664 set_cc_nz_u64(s, tmp2);
4665 tcg_temp_free_i64(tmp);
4666 tcg_temp_free_i64(tmp2);
4667 break;
4668 case 0x95: /* CLI D1(B1),I2 [SI] */
4669 insn = ld_code4(s->pc);
4670 tmp = decode_si(s, insn, &i2, &b1, &d1);
4671 tmp2 = tcg_temp_new_i64();
4672 tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4673 cmp_u64c(s, tmp2, i2);
4674 tcg_temp_free_i64(tmp);
4675 tcg_temp_free_i64(tmp2);
4676 break;
4677 case 0x9a: /* LAM R1,R3,D2(B2) [RS] */
4678 insn = ld_code4(s->pc);
4679 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4680 tmp = get_address(s, 0, b2, d2);
4681 tmp32_1 = tcg_const_i32(r1);
4682 tmp32_2 = tcg_const_i32(r3);
4683 potential_page_fault(s);
4684 gen_helper_lam(tmp32_1, tmp, tmp32_2);
4685 tcg_temp_free_i64(tmp);
4686 tcg_temp_free_i32(tmp32_1);
4687 tcg_temp_free_i32(tmp32_2);
4688 break;
4689 case 0x9b: /* STAM R1,R3,D2(B2) [RS] */
4690 insn = ld_code4(s->pc);
4691 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4692 tmp = get_address(s, 0, b2, d2);
4693 tmp32_1 = tcg_const_i32(r1);
4694 tmp32_2 = tcg_const_i32(r3);
4695 potential_page_fault(s);
4696 gen_helper_stam(tmp32_1, tmp, tmp32_2);
4697 tcg_temp_free_i64(tmp);
4698 tcg_temp_free_i32(tmp32_1);
4699 tcg_temp_free_i32(tmp32_2);
4700 break;
4701 case 0xa5:
4702 insn = ld_code4(s->pc);
4703 r1 = (insn >> 20) & 0xf;
4704 op = (insn >> 16) & 0xf;
4705 i2 = insn & 0xffff;
4706 disas_a5(s, op, r1, i2);
4707 break;
4708 case 0xa7:
4709 insn = ld_code4(s->pc);
4710 r1 = (insn >> 20) & 0xf;
4711 op = (insn >> 16) & 0xf;
4712 i2 = (short)insn;
4713 disas_a7(s, op, r1, i2);
4714 break;
4715 case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */
4716 insn = ld_code4(s->pc);
4717 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4718 tmp = get_address(s, 0, b2, d2);
4719 tmp32_1 = tcg_const_i32(r1);
4720 tmp32_2 = tcg_const_i32(r3);
4721 potential_page_fault(s);
4722 gen_helper_mvcle(cc_op, tmp32_1, tmp, tmp32_2);
4723 set_cc_static(s);
4724 tcg_temp_free_i64(tmp);
4725 tcg_temp_free_i32(tmp32_1);
4726 tcg_temp_free_i32(tmp32_2);
4727 break;
4728 case 0xa9: /* CLCLE R1,R3,D2(B2) [RS] */
4729 insn = ld_code4(s->pc);
4730 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4731 tmp = get_address(s, 0, b2, d2);
4732 tmp32_1 = tcg_const_i32(r1);
4733 tmp32_2 = tcg_const_i32(r3);
4734 potential_page_fault(s);
4735 gen_helper_clcle(cc_op, tmp32_1, tmp, tmp32_2);
4736 set_cc_static(s);
4737 tcg_temp_free_i64(tmp);
4738 tcg_temp_free_i32(tmp32_1);
4739 tcg_temp_free_i32(tmp32_2);
4740 break;
4741#ifndef CONFIG_USER_ONLY
4742 case 0xac: /* STNSM D1(B1),I2 [SI] */
4743 case 0xad: /* STOSM D1(B1),I2 [SI] */
4744 check_privileged(s, ilc);
4745 insn = ld_code4(s->pc);
4746 tmp = decode_si(s, insn, &i2, &b1, &d1);
4747 tmp2 = tcg_temp_new_i64();
4748 tcg_gen_shri_i64(tmp2, psw_mask, 56);
4749 tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4750 if (opc == 0xac) {
4751 tcg_gen_andi_i64(psw_mask, psw_mask,
4752 ((uint64_t)i2 << 56) | 0x00ffffffffffffffULL);
4753 } else {
4754 tcg_gen_ori_i64(psw_mask, psw_mask, (uint64_t)i2 << 56);
4755 }
4756 tcg_temp_free_i64(tmp);
4757 tcg_temp_free_i64(tmp2);
4758 break;
4759 case 0xae: /* SIGP R1,R3,D2(B2) [RS] */
4760 check_privileged(s, ilc);
4761 insn = ld_code4(s->pc);
4762 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4763 tmp = get_address(s, 0, b2, d2);
4764 tmp2 = load_reg(r3);
4765 tmp32_1 = tcg_const_i32(r1);
4766 potential_page_fault(s);
4767 gen_helper_sigp(cc_op, tmp, tmp32_1, tmp2);
4768 set_cc_static(s);
4769 tcg_temp_free_i64(tmp);
4770 tcg_temp_free_i64(tmp2);
4771 tcg_temp_free_i32(tmp32_1);
4772 break;
4773 case 0xb1: /* LRA R1,D2(X2, B2) [RX] */
4774 check_privileged(s, ilc);
4775 insn = ld_code4(s->pc);
4776 tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4777 tmp32_1 = tcg_const_i32(r1);
4778 potential_page_fault(s);
4779 gen_helper_lra(cc_op, tmp, tmp32_1);
4780 set_cc_static(s);
4781 tcg_temp_free_i64(tmp);
4782 tcg_temp_free_i32(tmp32_1);
4783 break;
4784#endif
4785 case 0xb2:
4786 insn = ld_code4(s->pc);
4787 op = (insn >> 16) & 0xff;
4788 switch (op) {
4789 case 0x9c: /* STFPC D2(B2) [S] */
4790 d2 = insn & 0xfff;
4791 b2 = (insn >> 12) & 0xf;
4792 tmp32_1 = tcg_temp_new_i32();
4793 tmp = tcg_temp_new_i64();
4794 tmp2 = get_address(s, 0, b2, d2);
4795 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
4796 tcg_gen_extu_i32_i64(tmp, tmp32_1);
4797 tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s));
4798 tcg_temp_free_i32(tmp32_1);
4799 tcg_temp_free_i64(tmp);
4800 tcg_temp_free_i64(tmp2);
4801 break;
4802 default:
4803 disas_b2(s, op, insn);
4804 break;
4805 }
4806 break;
4807 case 0xb3:
4808 insn = ld_code4(s->pc);
4809 op = (insn >> 16) & 0xff;
4810 r3 = (insn >> 12) & 0xf; /* aka m3 */
4811 r1 = (insn >> 4) & 0xf;
4812 r2 = insn & 0xf;
4813 disas_b3(s, op, r3, r1, r2);
4814 break;
4815#ifndef CONFIG_USER_ONLY
4816 case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
4817 /* Store Control */
4818 check_privileged(s, ilc);
4819 insn = ld_code4(s->pc);
4820 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4821 tmp = get_address(s, 0, b2, d2);
4822 tmp32_1 = tcg_const_i32(r1);
4823 tmp32_2 = tcg_const_i32(r3);
4824 potential_page_fault(s);
4825 gen_helper_stctl(tmp32_1, tmp, tmp32_2);
4826 tcg_temp_free_i64(tmp);
4827 tcg_temp_free_i32(tmp32_1);
4828 tcg_temp_free_i32(tmp32_2);
4829 break;
4830 case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
4831 /* Load Control */
4832 check_privileged(s, ilc);
4833 insn = ld_code4(s->pc);
4834 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4835 tmp = get_address(s, 0, b2, d2);
4836 tmp32_1 = tcg_const_i32(r1);
4837 tmp32_2 = tcg_const_i32(r3);
4838 potential_page_fault(s);
4839 gen_helper_lctl(tmp32_1, tmp, tmp32_2);
4840 tcg_temp_free_i64(tmp);
4841 tcg_temp_free_i32(tmp32_1);
4842 tcg_temp_free_i32(tmp32_2);
4843 break;
4844#endif
4845 case 0xb9:
4846 insn = ld_code4(s->pc);
4847 r1 = (insn >> 4) & 0xf;
4848 r2 = insn & 0xf;
4849 op = (insn >> 16) & 0xff;
4850 disas_b9(s, op, r1, r2);
4851 break;
4852 case 0xba: /* CS R1,R3,D2(B2) [RS] */
4853 insn = ld_code4(s->pc);
4854 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4855 tmp = get_address(s, 0, b2, d2);
4856 tmp32_1 = tcg_const_i32(r1);
4857 tmp32_2 = tcg_const_i32(r3);
4858 potential_page_fault(s);
4859 gen_helper_cs(cc_op, tmp32_1, tmp, tmp32_2);
4860 set_cc_static(s);
4861 tcg_temp_free_i64(tmp);
4862 tcg_temp_free_i32(tmp32_1);
4863 tcg_temp_free_i32(tmp32_2);
4864 break;
4865 case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
4866 insn = ld_code4(s->pc);
4867 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4868 tmp = get_address(s, 0, b2, d2);
4869 tmp32_1 = load_reg32(r1);
4870 tmp32_2 = tcg_const_i32(r3);
4871 potential_page_fault(s);
4872 gen_helper_clm(cc_op, tmp32_1, tmp32_2, tmp);
4873 set_cc_static(s);
4874 tcg_temp_free_i64(tmp);
4875 tcg_temp_free_i32(tmp32_1);
4876 tcg_temp_free_i32(tmp32_2);
4877 break;
4878 case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
4879 insn = ld_code4(s->pc);
4880 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4881 tmp = get_address(s, 0, b2, d2);
4882 tmp32_1 = load_reg32(r1);
4883 tmp32_2 = tcg_const_i32(r3);
4884 potential_page_fault(s);
4885 gen_helper_stcm(tmp32_1, tmp32_2, tmp);
4886 tcg_temp_free_i64(tmp);
4887 tcg_temp_free_i32(tmp32_1);
4888 tcg_temp_free_i32(tmp32_2);
4889 break;
4890 case 0xbf: /* ICM R1,M3,D2(B2) [RS] */
4891 insn = ld_code4(s->pc);
4892 decode_rs(s, insn, &r1, &r3, &b2, &d2);
4893 if (r3 == 15) {
4894 /* effectively a 32-bit load */
4895 tmp = get_address(s, 0, b2, d2);
4896 tmp32_1 = tcg_temp_new_i32();
4897 tmp32_2 = tcg_const_i32(r3);
4898 tcg_gen_qemu_ld32u(tmp, tmp, get_mem_index(s));
4899 store_reg32_i64(r1, tmp);
4900 tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4901 set_cc_icm(s, tmp32_2, tmp32_1);
4902 tcg_temp_free_i64(tmp);
4903 tcg_temp_free_i32(tmp32_1);
4904 tcg_temp_free_i32(tmp32_2);
4905 } else if (r3) {
4906 uint32_t mask = 0x00ffffffUL;
4907 uint32_t shift = 24;
4908 int m3 = r3;
4909 tmp = get_address(s, 0, b2, d2);
4910 tmp2 = tcg_temp_new_i64();
4911 tmp32_1 = load_reg32(r1);
4912 tmp32_2 = tcg_temp_new_i32();
4913 tmp32_3 = tcg_const_i32(r3);
4914 tmp32_4 = tcg_const_i32(0);
4915 while (m3) {
4916 if (m3 & 8) {
4917 tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4918 tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4919 if (shift) {
4920 tcg_gen_shli_i32(tmp32_2, tmp32_2, shift);
4921 }
4922 tcg_gen_andi_i32(tmp32_1, tmp32_1, mask);
4923 tcg_gen_or_i32(tmp32_1, tmp32_1, tmp32_2);
4924 tcg_gen_or_i32(tmp32_4, tmp32_4, tmp32_2);
4925 tcg_gen_addi_i64(tmp, tmp, 1);
4926 }
4927 m3 = (m3 << 1) & 0xf;
4928 mask = (mask >> 8) | 0xff000000UL;
4929 shift -= 8;
4930 }
4931 store_reg32(r1, tmp32_1);
4932 set_cc_icm(s, tmp32_3, tmp32_4);
4933 tcg_temp_free_i64(tmp);
4934 tcg_temp_free_i64(tmp2);
4935 tcg_temp_free_i32(tmp32_1);
4936 tcg_temp_free_i32(tmp32_2);
4937 tcg_temp_free_i32(tmp32_3);
4938 tcg_temp_free_i32(tmp32_4);
4939 } else {
4940 /* i.e. env->cc = 0 */
4941 gen_op_movi_cc(s, 0);
4942 }
4943 break;
4944 case 0xc0:
4945 case 0xc2:
4946 insn = ld_code6(s->pc);
4947 r1 = (insn >> 36) & 0xf;
4948 op = (insn >> 32) & 0xf;
4949 i2 = (int)insn;
4950 switch (opc) {
4951 case 0xc0:
4952 disas_c0(s, op, r1, i2);
4953 break;
4954 case 0xc2:
4955 disas_c2(s, op, r1, i2);
4956 break;
4957 default:
4958 tcg_abort();
4959 }
4960 break;
4961 case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */
4962 case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */
4963 case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */
4964 case 0xd6: /* OC D1(L,B1),D2(B2) [SS] */
4965 case 0xd7: /* XC D1(L,B1),D2(B2) [SS] */
4966 case 0xdc: /* TR D1(L,B1),D2(B2) [SS] */
4967 case 0xf3: /* UNPK D1(L1,B1),D2(L2,B2) [SS] */
4968 insn = ld_code6(s->pc);
4969 vl = tcg_const_i32((insn >> 32) & 0xff);
4970 b1 = (insn >> 28) & 0xf;
4971 b2 = (insn >> 12) & 0xf;
4972 d1 = (insn >> 16) & 0xfff;
4973 d2 = insn & 0xfff;
4974 tmp = get_address(s, 0, b1, d1);
4975 tmp2 = get_address(s, 0, b2, d2);
4976 switch (opc) {
4977 case 0xd2:
4978 gen_op_mvc(s, (insn >> 32) & 0xff, tmp, tmp2);
4979 break;
4980 case 0xd4:
4981 potential_page_fault(s);
4982 gen_helper_nc(cc_op, vl, tmp, tmp2);
4983 set_cc_static(s);
4984 break;
4985 case 0xd5:
4986 gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2);
4987 break;
4988 case 0xd6:
4989 potential_page_fault(s);
4990 gen_helper_oc(cc_op, vl, tmp, tmp2);
4991 set_cc_static(s);
4992 break;
4993 case 0xd7:
4994 potential_page_fault(s);
4995 gen_helper_xc(cc_op, vl, tmp, tmp2);
4996 set_cc_static(s);
4997 break;
4998 case 0xdc:
4999 potential_page_fault(s);
5000 gen_helper_tr(vl, tmp, tmp2);
5001 set_cc_static(s);
5002 break;
5003 case 0xf3:
5004 potential_page_fault(s);
5005 gen_helper_unpk(vl, tmp, tmp2);
5006 break;
5007 default:
5008 tcg_abort();
5009 }
5010 tcg_temp_free_i64(tmp);
5011 tcg_temp_free_i64(tmp2);
5012 break;
5013#ifndef CONFIG_USER_ONLY
5014 case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */
5015 case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */
5016 check_privileged(s, ilc);
5017 potential_page_fault(s);
5018 insn = ld_code6(s->pc);
5019 r1 = (insn >> 36) & 0xf;
5020 r3 = (insn >> 32) & 0xf;
5021 b1 = (insn >> 28) & 0xf;
5022 d1 = (insn >> 16) & 0xfff;
5023 b2 = (insn >> 12) & 0xf;
5024 d2 = insn & 0xfff;
5025 tmp = load_reg(r1);
5026 /* XXX key in r3 */
5027 tmp2 = get_address(s, 0, b1, d1);
5028 tmp3 = get_address(s, 0, b2, d2);
5029 if (opc == 0xda) {
5030 gen_helper_mvcp(cc_op, tmp, tmp2, tmp3);
5031 } else {
5032 gen_helper_mvcs(cc_op, tmp, tmp2, tmp3);
5033 }
5034 set_cc_static(s);
5035 tcg_temp_free_i64(tmp);
5036 tcg_temp_free_i64(tmp2);
5037 tcg_temp_free_i64(tmp3);
5038 break;
5039#endif
5040 case 0xe3:
5041 insn = ld_code6(s->pc);
5042 debug_insn(insn);
5043 op = insn & 0xff;
5044 r1 = (insn >> 36) & 0xf;
5045 x2 = (insn >> 32) & 0xf;
5046 b2 = (insn >> 28) & 0xf;
5047 d2 = ((int)((((insn >> 16) & 0xfff)
5048 | ((insn << 4) & 0xff000)) << 12)) >> 12;
5049 disas_e3(s, op, r1, x2, b2, d2 );
5050 break;
5051#ifndef CONFIG_USER_ONLY
5052 case 0xe5:
5053 /* Test Protection */
5054 check_privileged(s, ilc);
5055 insn = ld_code6(s->pc);
5056 debug_insn(insn);
5057 disas_e5(s, insn);
5058 break;
5059#endif
5060 case 0xeb:
5061 insn = ld_code6(s->pc);
5062 debug_insn(insn);
5063 op = insn & 0xff;
5064 r1 = (insn >> 36) & 0xf;
5065 r3 = (insn >> 32) & 0xf;
5066 b2 = (insn >> 28) & 0xf;
5067 d2 = ((int)((((insn >> 16) & 0xfff)
5068 | ((insn << 4) & 0xff000)) << 12)) >> 12;
5069 disas_eb(s, op, r1, r3, b2, d2);
5070 break;
5071 case 0xed:
5072 insn = ld_code6(s->pc);
5073 debug_insn(insn);
5074 op = insn & 0xff;
5075 r1 = (insn >> 36) & 0xf;
5076 x2 = (insn >> 32) & 0xf;
5077 b2 = (insn >> 28) & 0xf;
5078 d2 = (short)((insn >> 16) & 0xfff);
5079 r1b = (insn >> 12) & 0xf;
5080 disas_ed(s, op, r1, x2, b2, d2, r1b);
5081 break;
5082 default:
5083 LOG_DISAS("unimplemented opcode 0x%x\n", opc);
5084 gen_illegal_opcode(s, ilc);
5085 break;
5086 }
5087
5088 /* Instruction length is encoded in the opcode */
5089 s->pc += (ilc * 2);
5090}
5091
5092static inline void gen_intermediate_code_internal(CPUState *env,
5093 TranslationBlock *tb,
5094 int search_pc)
5095{
5096 DisasContext dc;
5097 target_ulong pc_start;
5098 uint64_t next_page_start;
5099 uint16_t *gen_opc_end;
5100 int j, lj = -1;
5101 int num_insns, max_insns;
5102 CPUBreakpoint *bp;
5103
5104 pc_start = tb->pc;
5105
5106 /* 31-bit mode */
5107 if (!(tb->flags & FLAG_MASK_64)) {
5108 pc_start &= 0x7fffffff;
5109 }
5110
5111 dc.pc = pc_start;
5112 dc.is_jmp = DISAS_NEXT;
5113 dc.tb = tb;
5114 dc.cc_op = CC_OP_DYNAMIC;
5115
5116 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
5117
5118 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
5119
5120 num_insns = 0;
5121 max_insns = tb->cflags & CF_COUNT_MASK;
5122 if (max_insns == 0) {
5123 max_insns = CF_COUNT_MASK;
5124 }
5125
5126 gen_icount_start();
5127
5128 do {
5129 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
5130 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
5131 if (bp->pc == dc.pc) {
5132 gen_debug(&dc);
5133 break;
5134 }
5135 }
5136 }
5137 if (search_pc) {
5138 j = gen_opc_ptr - gen_opc_buf;
5139 if (lj < j) {
5140 lj++;
5141 while (lj < j) {
5142 gen_opc_instr_start[lj++] = 0;
5143 }
5144 }
5145 gen_opc_pc[lj] = dc.pc;
5146 gen_opc_cc_op[lj] = dc.cc_op;
5147 gen_opc_instr_start[lj] = 1;
5148 gen_opc_icount[lj] = num_insns;
5149 }
5150 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
5151 gen_io_start();
5152 }
5153#if defined(S390X_DEBUG_DISAS_VERBOSE)
5154 LOG_DISAS("pc " TARGET_FMT_lx "\n",
5155 dc.pc);
5156#endif
5157 disas_s390_insn(&dc);
5158
5159 num_insns++;
5160 if (env->singlestep_enabled) {
5161 gen_debug(&dc);
5162 }
5163 } while (!dc.is_jmp && gen_opc_ptr < gen_opc_end && dc.pc < next_page_start
5164 && num_insns < max_insns && !env->singlestep_enabled
5165 && !singlestep);
5166
5167 if (!dc.is_jmp) {
5168 update_psw_addr(&dc);
5169 }
5170
5171 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
5172 gen_op_calc_cc(&dc);
5173 } else {
5174 /* next TB starts off with CC_OP_DYNAMIC, so make sure the cc op type
5175 is in env */
5176 gen_op_set_cc_op(&dc);
5177 }
5178
5179 if (tb->cflags & CF_LAST_IO) {
5180 gen_io_end();
5181 }
5182 /* Generate the return instruction */
5183 if (dc.is_jmp != DISAS_TB_JUMP) {
5184 tcg_gen_exit_tb(0);
5185 }
5186 gen_icount_end(tb, num_insns);
5187 *gen_opc_ptr = INDEX_op_end;
5188 if (search_pc) {
5189 j = gen_opc_ptr - gen_opc_buf;
5190 lj++;
5191 while (lj <= j) {
5192 gen_opc_instr_start[lj++] = 0;
5193 }
5194 } else {
5195 tb->size = dc.pc - pc_start;
5196 tb->icount = num_insns;
5197 }
5198#if defined(S390X_DEBUG_DISAS)
5199 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
5200 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
5201 qemu_log("IN: %s\n", lookup_symbol(pc_start));
5202 log_target_disas(pc_start, dc.pc - pc_start, 1);
5203 qemu_log("\n");
5204 }
5205#endif
5206}
5207
5208void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
5209{
5210 gen_intermediate_code_internal(env, tb, 0);
5211}
5212
5213void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
5214{
5215 gen_intermediate_code_internal(env, tb, 1);
5216}
5217
5218void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
5219{
5220 int cc_op;
5221 env->psw.addr = gen_opc_pc[pc_pos];
5222 cc_op = gen_opc_cc_op[pc_pos];
5223 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
5224 env->cc_op = cc_op;
5225 }
10ec5117 5226}
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