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339894be AF |
1 | /* |
2 | * QEMU SuperH CPU | |
3 | * | |
c4bb0f99 | 4 | * Copyright (c) 2005 Samuel Tardieu |
339894be AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
22 | #include "cpu.h" | |
23 | #include "qemu-common.h" | |
1e45d31b | 24 | #include "migration/vmstate.h" |
339894be AF |
25 | |
26 | ||
f45748f1 AF |
27 | static void superh_cpu_set_pc(CPUState *cs, vaddr value) |
28 | { | |
29 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
30 | ||
31 | cpu->env.pc = value; | |
32 | } | |
33 | ||
bdf7ae5b AF |
34 | static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
35 | { | |
36 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
37 | ||
38 | cpu->env.pc = tb->pc; | |
39 | cpu->env.flags = tb->flags; | |
40 | } | |
41 | ||
339894be AF |
42 | /* CPUClass::reset() */ |
43 | static void superh_cpu_reset(CPUState *s) | |
44 | { | |
45 | SuperHCPU *cpu = SUPERH_CPU(s); | |
46 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); | |
47 | CPUSH4State *env = &cpu->env; | |
48 | ||
49 | scc->parent_reset(s); | |
50 | ||
c4bb0f99 AF |
51 | memset(env, 0, offsetof(CPUSH4State, breakpoints)); |
52 | tlb_flush(env, 1); | |
53 | ||
54 | env->pc = 0xA0000000; | |
55 | #if defined(CONFIG_USER_ONLY) | |
56 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
57 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ | |
58 | #else | |
59 | env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; | |
60 | env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ | |
61 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); | |
62 | set_flush_to_zero(1, &env->fp_status); | |
63 | #endif | |
64 | set_default_nan_mode(1, &env->fp_status); | |
339894be AF |
65 | } |
66 | ||
c1b382e7 AF |
67 | typedef struct SuperHCPUListState { |
68 | fprintf_function cpu_fprintf; | |
69 | FILE *file; | |
70 | } SuperHCPUListState; | |
71 | ||
72 | /* Sort alphabetically by type name. */ | |
73 | static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b) | |
74 | { | |
75 | ObjectClass *class_a = (ObjectClass *)a; | |
76 | ObjectClass *class_b = (ObjectClass *)b; | |
77 | const char *name_a, *name_b; | |
78 | ||
79 | name_a = object_class_get_name(class_a); | |
80 | name_b = object_class_get_name(class_b); | |
81 | return strcmp(name_a, name_b); | |
82 | } | |
83 | ||
84 | static void superh_cpu_list_entry(gpointer data, gpointer user_data) | |
85 | { | |
86 | ObjectClass *oc = data; | |
87 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
88 | SuperHCPUListState *s = user_data; | |
89 | ||
90 | (*s->cpu_fprintf)(s->file, "%s\n", | |
91 | scc->name); | |
92 | } | |
93 | ||
94 | void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
95 | { | |
96 | SuperHCPUListState s = { | |
97 | .cpu_fprintf = cpu_fprintf, | |
98 | .file = f, | |
99 | }; | |
100 | GSList *list; | |
101 | ||
102 | list = object_class_get_list(TYPE_SUPERH_CPU, false); | |
103 | list = g_slist_sort(list, superh_cpu_list_compare); | |
104 | g_slist_foreach(list, superh_cpu_list_entry, &s); | |
105 | g_slist_free(list); | |
106 | } | |
107 | ||
108 | static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b) | |
109 | { | |
110 | const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a); | |
111 | const char *name = b; | |
112 | ||
113 | return strcasecmp(scc->name, name); | |
114 | } | |
115 | ||
116 | static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) | |
117 | { | |
118 | ObjectClass *oc; | |
119 | GSList *list, *item; | |
120 | ||
121 | if (cpu_model == NULL) { | |
122 | return NULL; | |
123 | } | |
124 | if (strcasecmp(cpu_model, "any") == 0) { | |
125 | return object_class_by_name(TYPE_SH7750R_CPU); | |
126 | } | |
127 | ||
128 | oc = object_class_by_name(cpu_model); | |
129 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL | |
130 | && !object_class_is_abstract(oc)) { | |
131 | return oc; | |
132 | } | |
133 | ||
134 | oc = NULL; | |
135 | list = object_class_get_list(TYPE_SUPERH_CPU, false); | |
136 | item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare); | |
137 | if (item != NULL) { | |
138 | oc = item->data; | |
139 | } | |
140 | g_slist_free(list); | |
141 | return oc; | |
142 | } | |
143 | ||
144 | SuperHCPU *cpu_sh4_init(const char *cpu_model) | |
145 | { | |
146 | SuperHCPU *cpu; | |
c1b382e7 AF |
147 | ObjectClass *oc; |
148 | ||
149 | oc = superh_cpu_class_by_name(cpu_model); | |
150 | if (oc == NULL) { | |
151 | return NULL; | |
152 | } | |
153 | cpu = SUPERH_CPU(object_new(object_class_get_name(oc))); | |
c1b382e7 AF |
154 | |
155 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
156 | ||
157 | return cpu; | |
158 | } | |
159 | ||
160 | static void sh7750r_cpu_initfn(Object *obj) | |
161 | { | |
162 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
163 | CPUSH4State *env = &cpu->env; | |
164 | ||
165 | env->id = SH_CPU_SH7750R; | |
c1b382e7 AF |
166 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
167 | } | |
168 | ||
169 | static void sh7750r_class_init(ObjectClass *oc, void *data) | |
170 | { | |
171 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
172 | ||
173 | scc->name = "SH7750R"; | |
b350ab75 AF |
174 | scc->pvr = 0x00050000; |
175 | scc->prr = 0x00000100; | |
176 | scc->cvr = 0x00110000; | |
c1b382e7 AF |
177 | } |
178 | ||
179 | static const TypeInfo sh7750r_type_info = { | |
180 | .name = TYPE_SH7750R_CPU, | |
181 | .parent = TYPE_SUPERH_CPU, | |
182 | .class_init = sh7750r_class_init, | |
183 | .instance_init = sh7750r_cpu_initfn, | |
184 | }; | |
185 | ||
186 | static void sh7751r_cpu_initfn(Object *obj) | |
187 | { | |
188 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
189 | CPUSH4State *env = &cpu->env; | |
190 | ||
191 | env->id = SH_CPU_SH7751R; | |
c1b382e7 AF |
192 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
193 | } | |
194 | ||
195 | static void sh7751r_class_init(ObjectClass *oc, void *data) | |
196 | { | |
197 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
198 | ||
199 | scc->name = "SH7751R"; | |
b350ab75 AF |
200 | scc->pvr = 0x04050005; |
201 | scc->prr = 0x00000113; | |
202 | scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ | |
c1b382e7 AF |
203 | } |
204 | ||
205 | static const TypeInfo sh7751r_type_info = { | |
206 | .name = TYPE_SH7751R_CPU, | |
207 | .parent = TYPE_SUPERH_CPU, | |
208 | .class_init = sh7751r_class_init, | |
209 | .instance_init = sh7751r_cpu_initfn, | |
210 | }; | |
211 | ||
212 | static void sh7785_cpu_initfn(Object *obj) | |
213 | { | |
214 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
215 | CPUSH4State *env = &cpu->env; | |
216 | ||
217 | env->id = SH_CPU_SH7785; | |
c1b382e7 AF |
218 | env->features = SH_FEATURE_SH4A; |
219 | } | |
220 | ||
221 | static void sh7785_class_init(ObjectClass *oc, void *data) | |
222 | { | |
223 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
224 | ||
225 | scc->name = "SH7785"; | |
b350ab75 AF |
226 | scc->pvr = 0x10300700; |
227 | scc->prr = 0x00000200; | |
228 | scc->cvr = 0x71440211; | |
c1b382e7 AF |
229 | } |
230 | ||
231 | static const TypeInfo sh7785_type_info = { | |
232 | .name = TYPE_SH7785_CPU, | |
233 | .parent = TYPE_SUPERH_CPU, | |
234 | .class_init = sh7785_class_init, | |
235 | .instance_init = sh7785_cpu_initfn, | |
236 | }; | |
237 | ||
55acb588 AF |
238 | static void superh_cpu_realizefn(DeviceState *dev, Error **errp) |
239 | { | |
14a10fc3 | 240 | CPUState *cs = CPU(dev); |
55acb588 AF |
241 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); |
242 | ||
14a10fc3 AF |
243 | cpu_reset(cs); |
244 | qemu_init_vcpu(cs); | |
55acb588 AF |
245 | |
246 | scc->parent_realize(dev, errp); | |
247 | } | |
248 | ||
2b4b4906 AF |
249 | static void superh_cpu_initfn(Object *obj) |
250 | { | |
c05efcb1 | 251 | CPUState *cs = CPU(obj); |
2b4b4906 AF |
252 | SuperHCPU *cpu = SUPERH_CPU(obj); |
253 | CPUSH4State *env = &cpu->env; | |
254 | ||
c05efcb1 | 255 | cs->env_ptr = env; |
2b4b4906 AF |
256 | cpu_exec_init(env); |
257 | ||
258 | env->movcal_backup_tail = &(env->movcal_backup); | |
aa7408ec AF |
259 | |
260 | if (tcg_enabled()) { | |
261 | sh4_translate_init(); | |
262 | } | |
2b4b4906 AF |
263 | } |
264 | ||
1e45d31b AF |
265 | static const VMStateDescription vmstate_sh_cpu = { |
266 | .name = "cpu", | |
267 | .unmigratable = 1, | |
268 | }; | |
269 | ||
339894be AF |
270 | static void superh_cpu_class_init(ObjectClass *oc, void *data) |
271 | { | |
1e45d31b | 272 | DeviceClass *dc = DEVICE_CLASS(oc); |
339894be AF |
273 | CPUClass *cc = CPU_CLASS(oc); |
274 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
275 | ||
55acb588 AF |
276 | scc->parent_realize = dc->realize; |
277 | dc->realize = superh_cpu_realizefn; | |
278 | ||
339894be AF |
279 | scc->parent_reset = cc->reset; |
280 | cc->reset = superh_cpu_reset; | |
1e45d31b | 281 | |
c1b382e7 | 282 | cc->class_by_name = superh_cpu_class_by_name; |
97a8ea5a | 283 | cc->do_interrupt = superh_cpu_do_interrupt; |
878096ee | 284 | cc->dump_state = superh_cpu_dump_state; |
f45748f1 | 285 | cc->set_pc = superh_cpu_set_pc; |
bdf7ae5b | 286 | cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; |
5b50e790 AF |
287 | cc->gdb_read_register = superh_cpu_gdb_read_register; |
288 | cc->gdb_write_register = superh_cpu_gdb_write_register; | |
00b941e5 AF |
289 | #ifndef CONFIG_USER_ONLY |
290 | cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; | |
291 | #endif | |
1e45d31b | 292 | dc->vmsd = &vmstate_sh_cpu; |
a0e372f0 | 293 | cc->gdb_num_core_regs = 59; |
339894be AF |
294 | } |
295 | ||
296 | static const TypeInfo superh_cpu_type_info = { | |
297 | .name = TYPE_SUPERH_CPU, | |
298 | .parent = TYPE_CPU, | |
299 | .instance_size = sizeof(SuperHCPU), | |
2b4b4906 | 300 | .instance_init = superh_cpu_initfn, |
c1b382e7 | 301 | .abstract = true, |
339894be AF |
302 | .class_size = sizeof(SuperHCPUClass), |
303 | .class_init = superh_cpu_class_init, | |
304 | }; | |
305 | ||
306 | static void superh_cpu_register_types(void) | |
307 | { | |
308 | type_register_static(&superh_cpu_type_info); | |
c1b382e7 AF |
309 | type_register_static(&sh7750r_type_info); |
310 | type_register_static(&sh7751r_type_info); | |
311 | type_register_static(&sh7785_type_info); | |
339894be AF |
312 | } |
313 | ||
314 | type_init(superh_cpu_register_types) |