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339894be AF |
1 | /* |
2 | * QEMU SuperH CPU | |
3 | * | |
c4bb0f99 | 4 | * Copyright (c) 2005 Samuel Tardieu |
339894be AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
22 | #include "cpu.h" | |
23 | #include "qemu-common.h" | |
1e45d31b | 24 | #include "migration/vmstate.h" |
339894be AF |
25 | |
26 | ||
27 | /* CPUClass::reset() */ | |
28 | static void superh_cpu_reset(CPUState *s) | |
29 | { | |
30 | SuperHCPU *cpu = SUPERH_CPU(s); | |
31 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); | |
32 | CPUSH4State *env = &cpu->env; | |
33 | ||
34 | scc->parent_reset(s); | |
35 | ||
c4bb0f99 AF |
36 | memset(env, 0, offsetof(CPUSH4State, breakpoints)); |
37 | tlb_flush(env, 1); | |
38 | ||
39 | env->pc = 0xA0000000; | |
40 | #if defined(CONFIG_USER_ONLY) | |
41 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
42 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ | |
43 | #else | |
44 | env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; | |
45 | env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ | |
46 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); | |
47 | set_flush_to_zero(1, &env->fp_status); | |
48 | #endif | |
49 | set_default_nan_mode(1, &env->fp_status); | |
339894be AF |
50 | } |
51 | ||
c1b382e7 AF |
52 | typedef struct SuperHCPUListState { |
53 | fprintf_function cpu_fprintf; | |
54 | FILE *file; | |
55 | } SuperHCPUListState; | |
56 | ||
57 | /* Sort alphabetically by type name. */ | |
58 | static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b) | |
59 | { | |
60 | ObjectClass *class_a = (ObjectClass *)a; | |
61 | ObjectClass *class_b = (ObjectClass *)b; | |
62 | const char *name_a, *name_b; | |
63 | ||
64 | name_a = object_class_get_name(class_a); | |
65 | name_b = object_class_get_name(class_b); | |
66 | return strcmp(name_a, name_b); | |
67 | } | |
68 | ||
69 | static void superh_cpu_list_entry(gpointer data, gpointer user_data) | |
70 | { | |
71 | ObjectClass *oc = data; | |
72 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
73 | SuperHCPUListState *s = user_data; | |
74 | ||
75 | (*s->cpu_fprintf)(s->file, "%s\n", | |
76 | scc->name); | |
77 | } | |
78 | ||
79 | void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
80 | { | |
81 | SuperHCPUListState s = { | |
82 | .cpu_fprintf = cpu_fprintf, | |
83 | .file = f, | |
84 | }; | |
85 | GSList *list; | |
86 | ||
87 | list = object_class_get_list(TYPE_SUPERH_CPU, false); | |
88 | list = g_slist_sort(list, superh_cpu_list_compare); | |
89 | g_slist_foreach(list, superh_cpu_list_entry, &s); | |
90 | g_slist_free(list); | |
91 | } | |
92 | ||
93 | static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b) | |
94 | { | |
95 | const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a); | |
96 | const char *name = b; | |
97 | ||
98 | return strcasecmp(scc->name, name); | |
99 | } | |
100 | ||
101 | static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) | |
102 | { | |
103 | ObjectClass *oc; | |
104 | GSList *list, *item; | |
105 | ||
106 | if (cpu_model == NULL) { | |
107 | return NULL; | |
108 | } | |
109 | if (strcasecmp(cpu_model, "any") == 0) { | |
110 | return object_class_by_name(TYPE_SH7750R_CPU); | |
111 | } | |
112 | ||
113 | oc = object_class_by_name(cpu_model); | |
114 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL | |
115 | && !object_class_is_abstract(oc)) { | |
116 | return oc; | |
117 | } | |
118 | ||
119 | oc = NULL; | |
120 | list = object_class_get_list(TYPE_SUPERH_CPU, false); | |
121 | item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare); | |
122 | if (item != NULL) { | |
123 | oc = item->data; | |
124 | } | |
125 | g_slist_free(list); | |
126 | return oc; | |
127 | } | |
128 | ||
129 | SuperHCPU *cpu_sh4_init(const char *cpu_model) | |
130 | { | |
131 | SuperHCPU *cpu; | |
132 | CPUSH4State *env; | |
133 | ObjectClass *oc; | |
134 | ||
135 | oc = superh_cpu_class_by_name(cpu_model); | |
136 | if (oc == NULL) { | |
137 | return NULL; | |
138 | } | |
139 | cpu = SUPERH_CPU(object_new(object_class_get_name(oc))); | |
140 | env = &cpu->env; | |
141 | env->cpu_model_str = cpu_model; | |
142 | ||
143 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
144 | ||
145 | return cpu; | |
146 | } | |
147 | ||
148 | static void sh7750r_cpu_initfn(Object *obj) | |
149 | { | |
150 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
151 | CPUSH4State *env = &cpu->env; | |
152 | ||
153 | env->id = SH_CPU_SH7750R; | |
c1b382e7 AF |
154 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
155 | } | |
156 | ||
157 | static void sh7750r_class_init(ObjectClass *oc, void *data) | |
158 | { | |
159 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
160 | ||
161 | scc->name = "SH7750R"; | |
b350ab75 AF |
162 | scc->pvr = 0x00050000; |
163 | scc->prr = 0x00000100; | |
164 | scc->cvr = 0x00110000; | |
c1b382e7 AF |
165 | } |
166 | ||
167 | static const TypeInfo sh7750r_type_info = { | |
168 | .name = TYPE_SH7750R_CPU, | |
169 | .parent = TYPE_SUPERH_CPU, | |
170 | .class_init = sh7750r_class_init, | |
171 | .instance_init = sh7750r_cpu_initfn, | |
172 | }; | |
173 | ||
174 | static void sh7751r_cpu_initfn(Object *obj) | |
175 | { | |
176 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
177 | CPUSH4State *env = &cpu->env; | |
178 | ||
179 | env->id = SH_CPU_SH7751R; | |
c1b382e7 AF |
180 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
181 | } | |
182 | ||
183 | static void sh7751r_class_init(ObjectClass *oc, void *data) | |
184 | { | |
185 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
186 | ||
187 | scc->name = "SH7751R"; | |
b350ab75 AF |
188 | scc->pvr = 0x04050005; |
189 | scc->prr = 0x00000113; | |
190 | scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ | |
c1b382e7 AF |
191 | } |
192 | ||
193 | static const TypeInfo sh7751r_type_info = { | |
194 | .name = TYPE_SH7751R_CPU, | |
195 | .parent = TYPE_SUPERH_CPU, | |
196 | .class_init = sh7751r_class_init, | |
197 | .instance_init = sh7751r_cpu_initfn, | |
198 | }; | |
199 | ||
200 | static void sh7785_cpu_initfn(Object *obj) | |
201 | { | |
202 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
203 | CPUSH4State *env = &cpu->env; | |
204 | ||
205 | env->id = SH_CPU_SH7785; | |
c1b382e7 AF |
206 | env->features = SH_FEATURE_SH4A; |
207 | } | |
208 | ||
209 | static void sh7785_class_init(ObjectClass *oc, void *data) | |
210 | { | |
211 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
212 | ||
213 | scc->name = "SH7785"; | |
b350ab75 AF |
214 | scc->pvr = 0x10300700; |
215 | scc->prr = 0x00000200; | |
216 | scc->cvr = 0x71440211; | |
c1b382e7 AF |
217 | } |
218 | ||
219 | static const TypeInfo sh7785_type_info = { | |
220 | .name = TYPE_SH7785_CPU, | |
221 | .parent = TYPE_SUPERH_CPU, | |
222 | .class_init = sh7785_class_init, | |
223 | .instance_init = sh7785_cpu_initfn, | |
224 | }; | |
225 | ||
55acb588 AF |
226 | static void superh_cpu_realizefn(DeviceState *dev, Error **errp) |
227 | { | |
228 | SuperHCPU *cpu = SUPERH_CPU(dev); | |
229 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); | |
230 | ||
231 | cpu_reset(CPU(cpu)); | |
55acb588 AF |
232 | |
233 | scc->parent_realize(dev, errp); | |
234 | } | |
235 | ||
2b4b4906 AF |
236 | static void superh_cpu_initfn(Object *obj) |
237 | { | |
c05efcb1 | 238 | CPUState *cs = CPU(obj); |
2b4b4906 AF |
239 | SuperHCPU *cpu = SUPERH_CPU(obj); |
240 | CPUSH4State *env = &cpu->env; | |
241 | ||
c05efcb1 | 242 | cs->env_ptr = env; |
2b4b4906 AF |
243 | cpu_exec_init(env); |
244 | ||
245 | env->movcal_backup_tail = &(env->movcal_backup); | |
aa7408ec AF |
246 | |
247 | if (tcg_enabled()) { | |
248 | sh4_translate_init(); | |
249 | } | |
2b4b4906 AF |
250 | } |
251 | ||
1e45d31b AF |
252 | static const VMStateDescription vmstate_sh_cpu = { |
253 | .name = "cpu", | |
254 | .unmigratable = 1, | |
255 | }; | |
256 | ||
339894be AF |
257 | static void superh_cpu_class_init(ObjectClass *oc, void *data) |
258 | { | |
1e45d31b | 259 | DeviceClass *dc = DEVICE_CLASS(oc); |
339894be AF |
260 | CPUClass *cc = CPU_CLASS(oc); |
261 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
262 | ||
55acb588 AF |
263 | scc->parent_realize = dc->realize; |
264 | dc->realize = superh_cpu_realizefn; | |
265 | ||
339894be AF |
266 | scc->parent_reset = cc->reset; |
267 | cc->reset = superh_cpu_reset; | |
1e45d31b | 268 | |
c1b382e7 | 269 | cc->class_by_name = superh_cpu_class_by_name; |
97a8ea5a | 270 | cc->do_interrupt = superh_cpu_do_interrupt; |
878096ee | 271 | cc->dump_state = superh_cpu_dump_state; |
1e45d31b | 272 | dc->vmsd = &vmstate_sh_cpu; |
339894be AF |
273 | } |
274 | ||
275 | static const TypeInfo superh_cpu_type_info = { | |
276 | .name = TYPE_SUPERH_CPU, | |
277 | .parent = TYPE_CPU, | |
278 | .instance_size = sizeof(SuperHCPU), | |
2b4b4906 | 279 | .instance_init = superh_cpu_initfn, |
c1b382e7 | 280 | .abstract = true, |
339894be AF |
281 | .class_size = sizeof(SuperHCPUClass), |
282 | .class_init = superh_cpu_class_init, | |
283 | }; | |
284 | ||
285 | static void superh_cpu_register_types(void) | |
286 | { | |
287 | type_register_static(&superh_cpu_type_info); | |
c1b382e7 AF |
288 | type_register_static(&sh7750r_type_info); |
289 | type_register_static(&sh7751r_type_info); | |
290 | type_register_static(&sh7785_type_info); | |
339894be AF |
291 | } |
292 | ||
293 | type_init(superh_cpu_register_types) |