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CommitLineData
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1/*
2 * SH4 emulation
5fafdf24 3 *
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4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 */
19#ifndef _CPU_SH4_H
20#define _CPU_SH4_H
21
22#include "config.h"
9a78eead 23#include "qemu-common.h"
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24
25#define TARGET_LONG_BITS 32
fdf9b3e8 26
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27#define ELF_MACHINE EM_SH
28
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29/* CPU Subtypes */
30#define SH_CPU_SH7750 (1 << 0)
31#define SH_CPU_SH7750S (1 << 1)
32#define SH_CPU_SH7750R (1 << 2)
33#define SH_CPU_SH7751 (1 << 3)
34#define SH_CPU_SH7751R (1 << 4)
a9c43f8e 35#define SH_CPU_SH7785 (1 << 5)
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36#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
38
9349b4f9 39#define CPUArchState struct CPUSH4State
c2764719 40
022c62cb 41#include "exec/cpu-defs.h"
fdf9b3e8 42
6b4c305c 43#include "fpu/softfloat.h"
eda9b09b 44
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45#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
46
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47#define TARGET_PHYS_ADDR_SPACE_BITS 32
48#define TARGET_VIRT_ADDR_SPACE_BITS 32
49
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50#define SR_MD 30
51#define SR_RB 29
52#define SR_BL 28
53#define SR_FD 15
54#define SR_M 9
55#define SR_Q 8
56#define SR_I3 7
57#define SR_I2 6
58#define SR_I1 5
59#define SR_I0 4
60#define SR_S 1
61#define SR_T 0
fdf9b3e8 62
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63#define FPSCR_MASK (0x003fffff)
64#define FPSCR_FR (1 << 21)
65#define FPSCR_SZ (1 << 20)
66#define FPSCR_PR (1 << 19)
67#define FPSCR_DN (1 << 18)
68#define FPSCR_CAUSE_MASK (0x3f << 12)
69#define FPSCR_CAUSE_SHIFT (12)
70#define FPSCR_CAUSE_E (1 << 17)
71#define FPSCR_CAUSE_V (1 << 16)
72#define FPSCR_CAUSE_Z (1 << 15)
73#define FPSCR_CAUSE_O (1 << 14)
74#define FPSCR_CAUSE_U (1 << 13)
75#define FPSCR_CAUSE_I (1 << 12)
76#define FPSCR_ENABLE_MASK (0x1f << 7)
77#define FPSCR_ENABLE_SHIFT (7)
78#define FPSCR_ENABLE_V (1 << 11)
79#define FPSCR_ENABLE_Z (1 << 10)
80#define FPSCR_ENABLE_O (1 << 9)
81#define FPSCR_ENABLE_U (1 << 8)
82#define FPSCR_ENABLE_I (1 << 7)
83#define FPSCR_FLAG_MASK (0x1f << 2)
84#define FPSCR_FLAG_SHIFT (2)
85#define FPSCR_FLAG_V (1 << 6)
86#define FPSCR_FLAG_Z (1 << 5)
87#define FPSCR_FLAG_O (1 << 4)
88#define FPSCR_FLAG_U (1 << 3)
89#define FPSCR_FLAG_I (1 << 2)
90#define FPSCR_RM_MASK (0x03 << 0)
91#define FPSCR_RM_NEAREST (0 << 0)
92#define FPSCR_RM_ZERO (1 << 0)
93
823029f9 94#define DELAY_SLOT (1 << 0)
fdf9b3e8 95#define DELAY_SLOT_CONDITIONAL (1 << 1)
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96#define DELAY_SLOT_TRUE (1 << 2)
97#define DELAY_SLOT_CLEARME (1 << 3)
98/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
99 * after the delay slot should be taken or not. It is calculated from SR_T.
100 *
101 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
102 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
103 */
fdf9b3e8 104
fdf9b3e8 105typedef struct tlb_t {
fdf9b3e8 106 uint32_t vpn; /* virtual page number */
fdf9b3e8 107 uint32_t ppn; /* physical page number */
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108 uint32_t size; /* mapped page size in bytes */
109 uint8_t asid; /* address space identifier */
110 uint8_t v:1; /* validity */
111 uint8_t sz:2; /* page size */
112 uint8_t sh:1; /* share status */
113 uint8_t c:1; /* cacheability */
114 uint8_t pr:2; /* protection key */
115 uint8_t d:1; /* dirty */
116 uint8_t wt:1; /* write through */
117 uint8_t sa:3; /* space attribute (PCMCIA) */
118 uint8_t tc:1; /* timing control */
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119} tlb_t;
120
121#define UTLB_SIZE 64
122#define ITLB_SIZE 4
123
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124#define NB_MMU_MODES 2
125
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126enum sh_features {
127 SH_FEATURE_SH4A = 1,
c2432a42 128 SH_FEATURE_BCR3_AND_BCR4 = 2,
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129};
130
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131typedef struct memory_content {
132 uint32_t address;
133 uint32_t value;
134 struct memory_content *next;
135} memory_content;
136
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137typedef struct CPUSH4State {
138 uint32_t flags; /* general execution flags */
139 uint32_t gregs[24]; /* general registers */
e04ea3dc 140 float32 fregs[32]; /* floating point registers */
34086945 141 uint32_t sr; /* status register (with T split out) */
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142 uint32_t sr_m; /* M bit of status register */
143 uint32_t sr_q; /* Q bit of status register */
34086945 144 uint32_t sr_t; /* T bit of status register */
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145 uint32_t ssr; /* saved status register */
146 uint32_t spc; /* saved program counter */
147 uint32_t gbr; /* global base register */
148 uint32_t vbr; /* vector base register */
149 uint32_t sgr; /* saved global register 15 */
150 uint32_t dbr; /* debug base register */
151 uint32_t pc; /* program counter */
152 uint32_t delayed_pc; /* target of delayed jump */
153 uint32_t mach; /* multiply and accumulate high */
154 uint32_t macl; /* multiply and accumulate low */
155 uint32_t pr; /* procedure register */
156 uint32_t fpscr; /* floating point status/control register */
157 uint32_t fpul; /* floating point communication register */
158
17b086f7 159 /* float point status register */
ea6cf6be 160 float_status fp_status;
eda9b09b 161
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162 /* Those belong to the specific unit (SH7750) but are handled here */
163 uint32_t mmucr; /* MMU control register */
164 uint32_t pteh; /* page table entry high register */
165 uint32_t ptel; /* page table entry low register */
166 uint32_t ptea; /* page table entry assistance register */
167 uint32_t ttb; /* tranlation table base register */
168 uint32_t tea; /* TLB exception address register */
169 uint32_t tra; /* TRAPA exception register */
170 uint32_t expevt; /* exception event register */
171 uint32_t intevt; /* interrupt event register */
172
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173 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
174 tlb_t utlb[UTLB_SIZE]; /* unified translation table */
175
176 uint32_t ldst;
177
178 CPU_COMMON
179
f0c3c505 180 /* Fields from here on are preserved over CPU reset. */
4f6493ff 181 int id; /* CPU model */
0fd3ca30 182
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183 /* The features that we should emulate. See sh_features above. */
184 uint32_t features;
185
e96e2044 186 void *intc_handle;
efac4154 187 int in_sleep; /* SR_BL ignored during sleep */
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188 memory_content *movcal_backup;
189 memory_content **movcal_backup_tail;
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190} CPUSH4State;
191
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192#include "cpu-qom.h"
193
aa7408ec 194void sh4_translate_init(void);
445e9571 195SuperHCPU *cpu_sh4_init(const char *cpu_model);
fdf9b3e8 196int cpu_sh4_exec(CPUSH4State * s);
5fafdf24 197int cpu_sh4_signal_handler(int host_signum, void *pinfo,
5a7b542b 198 void *puc);
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199int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
200 int mmu_idx);
42083220 201
9a78eead 202void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
3c7b48b7 203#if !defined(CONFIG_USER_ONLY)
e0bcb9ca 204void cpu_sh4_invalidate_tlb(CPUSH4State *s);
bc656a29 205uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
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206 hwaddr addr);
207void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
9f97309a 208 uint32_t mem_value);
bc656a29 209uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
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210 hwaddr addr);
211void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
9f97309a 212 uint32_t mem_value);
bc656a29 213uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
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214 hwaddr addr);
215void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
9f97309a 216 uint32_t mem_value);
bc656a29 217uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
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218 hwaddr addr);
219void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
9f97309a 220 uint32_t mem_value);
3c7b48b7 221#endif
fdf9b3e8 222
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223int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
224
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225void cpu_load_tlb(CPUSH4State * env);
226
2994fd96 227#define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
445e9571 228
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229#define cpu_exec cpu_sh4_exec
230#define cpu_gen_code cpu_sh4_gen_code
231#define cpu_signal_handler cpu_sh4_signal_handler
0fd3ca30 232#define cpu_list sh4_cpu_list
9467d44c 233
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234/* MMU modes definitions */
235#define MMU_MODE0_SUFFIX _kernel
236#define MMU_MODE1_SUFFIX _user
237#define MMU_USER_IDX 1
73e5716c 238static inline int cpu_mmu_index (CPUSH4State *env)
6ebbf390 239{
5ed9a259 240 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
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241}
242
022c62cb 243#include "exec/cpu-all.h"
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244
245/* Memory access type */
246enum {
247 /* Privilege */
248 ACCESS_PRIV = 0x01,
249 /* Direction */
250 ACCESS_WRITE = 0x02,
251 /* Type of instruction */
252 ACCESS_CODE = 0x10,
253 ACCESS_INT = 0x20
254};
255
256/* MMU control register */
257#define MMUCR 0x1F000010
258#define MMUCR_AT (1<<0)
e0bcb9ca 259#define MMUCR_TI (1<<2)
fdf9b3e8 260#define MMUCR_SV (1<<8)
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261#define MMUCR_URC_BITS (6)
262#define MMUCR_URC_OFFSET (10)
263#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
264#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
265static inline int cpu_mmucr_urc (uint32_t mmucr)
266{
267 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
268}
269
270/* PTEH : Page Translation Entry High register */
271#define PTEH_ASID_BITS (8)
272#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
273#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
274#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
275#define PTEH_VPN_BITS (22)
276#define PTEH_VPN_OFFSET (10)
277#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
278#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
279static inline int cpu_pteh_vpn (uint32_t pteh)
280{
281 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
282}
283
284/* PTEL : Page Translation Entry Low register */
285#define PTEL_V (1 << 8)
286#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
287#define PTEL_C (1 << 3)
288#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
289#define PTEL_D (1 << 2)
290#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
291#define PTEL_SH (1 << 1)
292#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
293#define PTEL_WT (1 << 0)
294#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
295
296#define PTEL_SZ_HIGH_OFFSET (7)
297#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
298#define PTEL_SZ_LOW_OFFSET (4)
299#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
300static inline int cpu_ptel_sz (uint32_t ptel)
301{
302 int sz;
303 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
304 sz <<= 1;
305 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
306 return sz;
307}
308
309#define PTEL_PPN_BITS (19)
310#define PTEL_PPN_OFFSET (10)
311#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
312#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
313static inline int cpu_ptel_ppn (uint32_t ptel)
314{
315 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
316}
317
318#define PTEL_PR_BITS (2)
319#define PTEL_PR_OFFSET (5)
320#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
321#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
322static inline int cpu_ptel_pr (uint32_t ptel)
323{
324 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
325}
326
327/* PTEA : Page Translation Entry Assistance register */
328#define PTEA_SA_BITS (3)
329#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
330#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
331#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
332#define PTEA_TC (1 << 3)
333#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
fdf9b3e8 334
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335#define TB_FLAG_PENDING_MOVCA (1 << 4)
336
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337static inline target_ulong cpu_read_sr(CPUSH4State *env)
338{
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339 return env->sr | (env->sr_m << SR_M) |
340 (env->sr_q << SR_Q) |
341 (env->sr_t << SR_T);
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342}
343
344static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
345{
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346 env->sr_m = (sr >> SR_M) & 1;
347 env->sr_q = (sr >> SR_Q) & 1;
348 env->sr_t = (sr >> SR_T) & 1;
349 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
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350}
351
73e5716c 352static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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353 target_ulong *cs_base, int *flags)
354{
355 *pc = env->pc;
356 *cs_base = 0;
357 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
358 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
359 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
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360 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
361 | (env->sr & (1u << SR_FD)) /* Bit 15 */
852d481f 362 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
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363}
364
022c62cb 365#include "exec/exec-all.h"
f081c76c 366
fdf9b3e8 367#endif /* _CPU_SH4_H */