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ivshmem: Fix 64 bit memory bar configuration
[mirror_qemu.git] / target-sh4 / op_helper.c
CommitLineData
fdf9b3e8
FB
1/*
2 * SH4 emulation
5fafdf24 3 *
fdf9b3e8
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4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
fdf9b3e8 18 */
9d4c9946 19#include "qemu/osdep.h"
3e457172 20#include "cpu.h"
2ef6175a 21#include "exec/helper-proto.h"
63c91552 22#include "exec/exec-all.h"
f08b6170 23#include "exec/cpu_ldst.h"
fdf9b3e8 24
fdf9b3e8
FB
25#ifndef CONFIG_USER_ONLY
26
b35399bb
SS
27void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
28 int mmu_idx, uintptr_t retaddr)
fdf9b3e8 29{
fdf9b3e8
FB
30 int ret;
31
b35399bb 32 ret = superh_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
fdf9b3e8 33 if (ret) {
21829e9b 34 /* now we have a real cpu fault */
a8a826a3 35 if (retaddr) {
3f38f309 36 cpu_restore_state(cs, retaddr);
a8a826a3 37 }
5638d180 38 cpu_loop_exit(cs);
fdf9b3e8 39 }
fdf9b3e8
FB
40}
41
42#endif
43
485d0035 44void helper_ldtlb(CPUSH4State *env)
ea2b542a
AJ
45{
46#ifdef CONFIG_USER_ONLY
a47dddd7
AF
47 SuperHCPU *cpu = sh_env_get_cpu(env);
48
ea2b542a 49 /* XXXXX */
a47dddd7 50 cpu_abort(CPU(cpu), "Unhandled ldtlb");
ea2b542a
AJ
51#else
52 cpu_load_tlb(env);
53#endif
54}
55
10127400
AJ
56static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
57 uintptr_t retaddr)
e6afc2f4 58{
27103424
AF
59 CPUState *cs = CPU(sh_env_get_cpu(env));
60
61 cs->exception_index = index;
a8a826a3 62 if (retaddr) {
3f38f309 63 cpu_restore_state(cs, retaddr);
a8a826a3 64 }
5638d180 65 cpu_loop_exit(cs);
e6afc2f4
AJ
66}
67
485d0035 68void helper_raise_illegal_instruction(CPUSH4State *env)
fd4bab10 69{
10127400 70 raise_exception(env, 0x180, 0);
fd4bab10
AJ
71}
72
485d0035 73void helper_raise_slot_illegal_instruction(CPUSH4State *env)
e6afc2f4 74{
10127400 75 raise_exception(env, 0x1a0, 0);
e6afc2f4
AJ
76}
77
485d0035 78void helper_raise_fpu_disable(CPUSH4State *env)
d8299bcc 79{
10127400 80 raise_exception(env, 0x800, 0);
d8299bcc
AJ
81}
82
485d0035 83void helper_raise_slot_fpu_disable(CPUSH4State *env)
d8299bcc 84{
10127400 85 raise_exception(env, 0x820, 0);
d8299bcc
AJ
86}
87
485d0035 88void helper_debug(CPUSH4State *env)
e6afc2f4 89{
10127400 90 raise_exception(env, EXCP_DEBUG, 0);
e6afc2f4
AJ
91}
92
10127400 93void helper_sleep(CPUSH4State *env)
e6afc2f4 94{
259186a7
AF
95 CPUState *cs = CPU(sh_env_get_cpu(env));
96
97 cs->halted = 1;
efac4154 98 env->in_sleep = 1;
10127400 99 raise_exception(env, EXCP_HLT, 0);
e6afc2f4
AJ
100}
101
485d0035 102void helper_trapa(CPUSH4State *env, uint32_t tra)
e6afc2f4
AJ
103{
104 env->tra = tra << 2;
10127400 105 raise_exception(env, 0x160, 0);
e6afc2f4
AJ
106}
107
485d0035 108void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
852d481f
EI
109{
110 if (cpu_sh4_is_cached (env, address))
111 {
01a72012
PM
112 memory_content *r = g_new(memory_content, 1);
113
852d481f
EI
114 r->address = address;
115 r->value = value;
116 r->next = NULL;
117
118 *(env->movcal_backup_tail) = r;
119 env->movcal_backup_tail = &(r->next);
120 }
121}
122
485d0035 123void helper_discard_movcal_backup(CPUSH4State *env)
852d481f
EI
124{
125 memory_content *current = env->movcal_backup;
126
127 while(current)
128 {
129 memory_content *next = current->next;
01a72012 130 g_free(current);
852d481f 131 env->movcal_backup = current = next;
b9d38e95 132 if (current == NULL)
852d481f
EI
133 env->movcal_backup_tail = &(env->movcal_backup);
134 }
135}
136
485d0035 137void helper_ocbi(CPUSH4State *env, uint32_t address)
852d481f
EI
138{
139 memory_content **current = &(env->movcal_backup);
140 while (*current)
141 {
142 uint32_t a = (*current)->address;
143 if ((a & ~0x1F) == (address & ~0x1F))
144 {
145 memory_content *next = (*current)->next;
485d0035 146 cpu_stl_data(env, a, (*current)->value);
852d481f 147
b9d38e95 148 if (next == NULL)
852d481f
EI
149 {
150 env->movcal_backup_tail = current;
151 }
152
01a72012 153 g_free(*current);
852d481f
EI
154 *current = next;
155 break;
156 }
157 }
158}
159
485d0035 160void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8
FB
161{
162 int64_t res;
163
164 res = ((uint64_t) env->mach << 32) | env->macl;
6f06939b 165 res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
fdf9b3e8
FB
166 env->mach = (res >> 32) & 0xffffffff;
167 env->macl = res & 0xffffffff;
5ed9a259 168 if (env->sr & (1u << SR_S)) {
fdf9b3e8
FB
169 if (res < 0)
170 env->mach |= 0xffff0000;
171 else
172 env->mach &= 0x00007fff;
173 }
174}
175
485d0035 176void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
fdf9b3e8
FB
177{
178 int64_t res;
179
180 res = ((uint64_t) env->mach << 32) | env->macl;
6f06939b 181 res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
fdf9b3e8
FB
182 env->mach = (res >> 32) & 0xffffffff;
183 env->macl = res & 0xffffffff;
5ed9a259 184 if (env->sr & (1u << SR_S)) {
fdf9b3e8
FB
185 if (res < -0x80000000) {
186 env->mach = 1;
187 env->macl = 0x80000000;
188 } else if (res > 0x000000007fffffff) {
189 env->mach = 1;
190 env->macl = 0x7fffffff;
191 }
192 }
193}
194
485d0035 195void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
390af821 196{
26ac1ea5
AJ
197 env->fpscr = val & FPSCR_MASK;
198 if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
390af821 199 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
26ac1ea5 200 } else {
390af821 201 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
26ac1ea5 202 }
a0d4ac33 203 set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
390af821 204}
cc4ba6a9 205
485d0035 206static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
21829e9b
AJ
207{
208 int xcpt, cause, enable;
209
210 xcpt = get_float_exception_flags(&env->fp_status);
211
212 /* Clear the flag entries */
213 env->fpscr &= ~FPSCR_FLAG_MASK;
214
215 if (unlikely(xcpt)) {
216 if (xcpt & float_flag_invalid) {
217 env->fpscr |= FPSCR_FLAG_V;
218 }
219 if (xcpt & float_flag_divbyzero) {
220 env->fpscr |= FPSCR_FLAG_Z;
221 }
222 if (xcpt & float_flag_overflow) {
223 env->fpscr |= FPSCR_FLAG_O;
224 }
225 if (xcpt & float_flag_underflow) {
226 env->fpscr |= FPSCR_FLAG_U;
227 }
228 if (xcpt & float_flag_inexact) {
229 env->fpscr |= FPSCR_FLAG_I;
230 }
231
232 /* Accumulate in cause entries */
233 env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
234 << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
235
236 /* Generate an exception if enabled */
237 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
238 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
239 if (cause & enable) {
10127400 240 raise_exception(env, 0x120, retaddr);
21829e9b
AJ
241 }
242 }
243}
244
d6c424c5 245float32 helper_fabs_FT(float32 t0)
cc4ba6a9 246{
d6c424c5 247 return float32_abs(t0);
cc4ba6a9
AJ
248}
249
d6c424c5 250float64 helper_fabs_DT(float64 t0)
cc4ba6a9 251{
d6c424c5 252 return float64_abs(t0);
cc4ba6a9
AJ
253}
254
485d0035 255float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9 256{
21829e9b 257 set_float_exception_flags(0, &env->fp_status);
d6c424c5 258 t0 = float32_add(t0, t1, &env->fp_status);
485d0035 259 update_fpscr(env, GETPC());
d6c424c5 260 return t0;
cc4ba6a9
AJ
261}
262
485d0035 263float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9 264{
21829e9b 265 set_float_exception_flags(0, &env->fp_status);
d6c424c5 266 t0 = float64_add(t0, t1, &env->fp_status);
485d0035 267 update_fpscr(env, GETPC());
d6c424c5 268 return t0;
cc4ba6a9
AJ
269}
270
485d0035 271void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9 272{
21829e9b 273 int relation;
9850d1e8 274
21829e9b 275 set_float_exception_flags(0, &env->fp_status);
d6c424c5 276 relation = float32_compare(t0, t1, &env->fp_status);
21829e9b 277 if (unlikely(relation == float_relation_unordered)) {
485d0035 278 update_fpscr(env, GETPC());
21829e9b 279 } else {
34086945 280 env->sr_t = (relation == float_relation_equal);
21829e9b 281 }
cc4ba6a9
AJ
282}
283
485d0035 284void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9 285{
21829e9b 286 int relation;
9850d1e8 287
21829e9b 288 set_float_exception_flags(0, &env->fp_status);
d6c424c5 289 relation = float64_compare(t0, t1, &env->fp_status);
21829e9b 290 if (unlikely(relation == float_relation_unordered)) {
485d0035 291 update_fpscr(env, GETPC());
21829e9b 292 } else {
34086945 293 env->sr_t = (relation == float_relation_equal);
21829e9b 294 }
cc4ba6a9
AJ
295}
296
485d0035 297void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9 298{
21829e9b 299 int relation;
9850d1e8 300
21829e9b 301 set_float_exception_flags(0, &env->fp_status);
d6c424c5 302 relation = float32_compare(t0, t1, &env->fp_status);
21829e9b 303 if (unlikely(relation == float_relation_unordered)) {
485d0035 304 update_fpscr(env, GETPC());
21829e9b 305 } else {
34086945 306 env->sr_t = (relation == float_relation_greater);
21829e9b 307 }
cc4ba6a9
AJ
308}
309
485d0035 310void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9 311{
21829e9b 312 int relation;
9850d1e8 313
21829e9b 314 set_float_exception_flags(0, &env->fp_status);
d6c424c5 315 relation = float64_compare(t0, t1, &env->fp_status);
21829e9b 316 if (unlikely(relation == float_relation_unordered)) {
485d0035 317 update_fpscr(env, GETPC());
21829e9b 318 } else {
34086945 319 env->sr_t = (relation == float_relation_greater);
21829e9b 320 }
cc4ba6a9
AJ
321}
322
485d0035 323float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
cc4ba6a9 324{
d6c424c5 325 float64 ret;
21829e9b 326 set_float_exception_flags(0, &env->fp_status);
d6c424c5 327 ret = float32_to_float64(t0, &env->fp_status);
485d0035 328 update_fpscr(env, GETPC());
d6c424c5 329 return ret;
cc4ba6a9
AJ
330}
331
485d0035 332float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
cc4ba6a9 333{
d6c424c5 334 float32 ret;
21829e9b 335 set_float_exception_flags(0, &env->fp_status);
d6c424c5 336 ret = float64_to_float32(t0, &env->fp_status);
485d0035 337 update_fpscr(env, GETPC());
d6c424c5 338 return ret;
cc4ba6a9
AJ
339}
340
485d0035 341float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9 342{
21829e9b 343 set_float_exception_flags(0, &env->fp_status);
d6c424c5 344 t0 = float32_div(t0, t1, &env->fp_status);
485d0035 345 update_fpscr(env, GETPC());
d6c424c5 346 return t0;
cc4ba6a9
AJ
347}
348
485d0035 349float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9 350{
21829e9b 351 set_float_exception_flags(0, &env->fp_status);
d6c424c5 352 t0 = float64_div(t0, t1, &env->fp_status);
485d0035 353 update_fpscr(env, GETPC());
d6c424c5 354 return t0;
cc4ba6a9
AJ
355}
356
485d0035 357float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
cc4ba6a9 358{
d6c424c5 359 float32 ret;
21829e9b 360 set_float_exception_flags(0, &env->fp_status);
d6c424c5 361 ret = int32_to_float32(t0, &env->fp_status);
485d0035 362 update_fpscr(env, GETPC());
d6c424c5 363 return ret;
cc4ba6a9
AJ
364}
365
485d0035 366float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
cc4ba6a9 367{
d6c424c5 368 float64 ret;
21829e9b 369 set_float_exception_flags(0, &env->fp_status);
d6c424c5 370 ret = int32_to_float64(t0, &env->fp_status);
485d0035 371 update_fpscr(env, GETPC());
d6c424c5 372 return ret;
cc4ba6a9
AJ
373}
374
485d0035 375float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
5b7141a1 376{
21829e9b 377 set_float_exception_flags(0, &env->fp_status);
ff2086fe 378 t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
485d0035 379 update_fpscr(env, GETPC());
d6c424c5 380 return t0;
5b7141a1
AJ
381}
382
485d0035 383float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9 384{
21829e9b 385 set_float_exception_flags(0, &env->fp_status);
d6c424c5 386 t0 = float32_mul(t0, t1, &env->fp_status);
485d0035 387 update_fpscr(env, GETPC());
d6c424c5 388 return t0;
cc4ba6a9
AJ
389}
390
485d0035 391float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9 392{
21829e9b 393 set_float_exception_flags(0, &env->fp_status);
d6c424c5 394 t0 = float64_mul(t0, t1, &env->fp_status);
485d0035 395 update_fpscr(env, GETPC());
d6c424c5 396 return t0;
cc4ba6a9
AJ
397}
398
d6c424c5 399float32 helper_fneg_T(float32 t0)
7fdf924f 400{
d6c424c5 401 return float32_chs(t0);
7fdf924f
AJ
402}
403
485d0035 404float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
cc4ba6a9 405{
21829e9b 406 set_float_exception_flags(0, &env->fp_status);
d6c424c5 407 t0 = float32_sqrt(t0, &env->fp_status);
485d0035 408 update_fpscr(env, GETPC());
d6c424c5 409 return t0;
cc4ba6a9
AJ
410}
411
485d0035 412float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
cc4ba6a9 413{
21829e9b 414 set_float_exception_flags(0, &env->fp_status);
d6c424c5 415 t0 = float64_sqrt(t0, &env->fp_status);
485d0035 416 update_fpscr(env, GETPC());
d6c424c5 417 return t0;
cc4ba6a9
AJ
418}
419
485d0035 420float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
cc4ba6a9 421{
21829e9b 422 set_float_exception_flags(0, &env->fp_status);
d6c424c5 423 t0 = float32_sub(t0, t1, &env->fp_status);
485d0035 424 update_fpscr(env, GETPC());
d6c424c5 425 return t0;
cc4ba6a9
AJ
426}
427
485d0035 428float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
cc4ba6a9 429{
21829e9b 430 set_float_exception_flags(0, &env->fp_status);
d6c424c5 431 t0 = float64_sub(t0, t1, &env->fp_status);
485d0035 432 update_fpscr(env, GETPC());
d6c424c5 433 return t0;
cc4ba6a9
AJ
434}
435
485d0035 436uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
cc4ba6a9 437{
21829e9b 438 uint32_t ret;
21829e9b 439 set_float_exception_flags(0, &env->fp_status);
d6c424c5 440 ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
485d0035 441 update_fpscr(env, GETPC());
21829e9b 442 return ret;
cc4ba6a9
AJ
443}
444
485d0035 445uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
cc4ba6a9 446{
21829e9b 447 uint32_t ret;
21829e9b 448 set_float_exception_flags(0, &env->fp_status);
d6c424c5 449 ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
485d0035 450 update_fpscr(env, GETPC());
21829e9b 451 return ret;
cc4ba6a9 452}
af8c2bde 453
485d0035 454void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
af8c2bde
AJ
455{
456 int bank, i;
457 float32 r, p;
458
459 bank = (env->sr & FPSCR_FR) ? 16 : 0;
460 r = float32_zero;
461 set_float_exception_flags(0, &env->fp_status);
462
463 for (i = 0 ; i < 4 ; i++) {
464 p = float32_mul(env->fregs[bank + m + i],
465 env->fregs[bank + n + i],
466 &env->fp_status);
467 r = float32_add(r, p, &env->fp_status);
468 }
485d0035 469 update_fpscr(env, GETPC());
af8c2bde
AJ
470
471 env->fregs[bank + n + 3] = r;
472}
17075f10 473
485d0035 474void helper_ftrv(CPUSH4State *env, uint32_t n)
17075f10
AJ
475{
476 int bank_matrix, bank_vector;
477 int i, j;
478 float32 r[4];
479 float32 p;
480
481 bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
482 bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
483 set_float_exception_flags(0, &env->fp_status);
484 for (i = 0 ; i < 4 ; i++) {
485 r[i] = float32_zero;
486 for (j = 0 ; j < 4 ; j++) {
487 p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
488 env->fregs[bank_vector + j],
489 &env->fp_status);
490 r[i] = float32_add(r[i], p, &env->fp_status);
491 }
492 }
485d0035 493 update_fpscr(env, GETPC());
17075f10
AJ
494
495 for (i = 0 ; i < 4 ; i++) {
496 env->fregs[bank_vector + i] = r[i];
497 }
498}