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[mirror_qemu.git] / target-sparc / cpu.c
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ab3b491f
BS		 1/*
2 * Sparc CPU init helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
db5ebe5f 20#include "qemu/osdep.h"
da34e65c 21#include "qapi/error.h"
ab3b491f 22#include "cpu.h"
db5d39f7 23#include "qemu/error-report.h"
63c91552 24#include "exec/exec-all.h"
ab3b491f
BS		 25
26//#define DEBUG_FEATURES
27
28static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
29
ab7ab3d7
AF		 30/* CPUClass::reset() */
31static void sparc_cpu_reset(CPUState *s)
32{
33 SPARCCPU *cpu = SPARC_CPU(s);
34 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
35 CPUSPARCState *env = &cpu->env;
36
ab7ab3d7
AF		 37 scc->parent_reset(s);
38
f0c3c505 39 memset(env, 0, offsetof(CPUSPARCState, version));
00c8cb0a 40 tlb_flush(s, 1);
ab3b491f
BS		 41 env->cwp = 0;
42#ifndef TARGET_SPARC64
43 env->wim = 1;
44#endif
45 env->regwptr = env->regbase + (env->cwp * 16);
46 CC_OP = CC_OP_FLAGS;
47#if defined(CONFIG_USER_ONLY)
48#ifdef TARGET_SPARC64
49 env->cleanwin = env->nwindows - 2;
50 env->cansave = env->nwindows - 2;
51 env->pstate = PS_RMO | PS_PEF | PS_IE;
52 env->asi = 0x82; /* Primary no-fault */
53#endif
54#else
55#if !defined(TARGET_SPARC64)
56 env->psret = 0;
57 env->psrs = 1;
58 env->psrps = 1;
59#endif
60#ifdef TARGET_SPARC64
61 env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
62 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
63 env->tl = env->maxtl;
64 cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
65 env->lsu = 0;
66#else
67 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
68 env->mmuregs[0] |= env->def->mmu_bm;
69#endif
70 env->pc = 0;
71 env->npc = env->pc + 4;
72#endif
73 env->cache_control = 0;
74}
75
87afe467
RH		 76static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
77{
78 if (interrupt_request & CPU_INTERRUPT_HARD) {
79 SPARCCPU *cpu = SPARC_CPU(cs);
80 CPUSPARCState *env = &cpu->env;
81
82 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
83 int pil = env->interrupt_index & 0xf;
84 int type = env->interrupt_index & 0xf0;
85
86 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
87 cs->exception_index = env->interrupt_index;
88 sparc_cpu_do_interrupt(cs);
89 return true;
90 }
91 }
92 }
93 return false;
94}
95
df0900eb
PC		 96static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
97{
98 info->print_insn = print_insn_sparc;
99#ifdef TARGET_SPARC64
100 info->mach = bfd_mach_sparc_v9b;
101#endif
102}
103
fb02d56e
IM		 104static void sparc_cpu_parse_features(CPUState *cs, char *features,
105 Error **errp);
106
433ac7a9 107static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
ab3b491f 108{
433ac7a9
AF		 109 CPUSPARCState *env = &cpu->env;
110 char *s = g_strdup(cpu_model);
111 char *featurestr, *name = strtok(s, ",");
ab3b491f 112 sparc_def_t def1, *def = &def1;
433ac7a9 113 Error *err = NULL;
ab3b491f 114
433ac7a9
AF		 115 if (cpu_sparc_find_by_name(def, name) < 0) {
116 g_free(s);
ab3b491f
BS		 117 return -1;
118 }
119
d300854b 120 env->def = g_new0(sparc_def_t, 1);
ab3b491f 121 memcpy(env->def, def, sizeof(*def));
433ac7a9
AF		 122
123 featurestr = strtok(NULL, ",");
fb02d56e 124 sparc_cpu_parse_features(CPU(cpu), featurestr, &err);
433ac7a9
AF		 125 g_free(s);
126 if (err) {
565f65d2 127 error_report_err(err);
433ac7a9
AF		 128 return -1;
129 }
130
ab3b491f
BS		 131 env->version = def->iu_version;
132 env->fsr = def->fpu_version;
133 env->nwindows = def->nwindows;
134#if !defined(TARGET_SPARC64)
135 env->mmuregs[0] |= def->mmu_version;
136 cpu_sparc_set_id(env, 0);
137 env->mxccregs[7] |= def->mxcc_version;
138#else
139 env->mmu_version = def->mmu_version;
140 env->maxtl = def->maxtl;
141 env->version |= def->maxtl << 8;
142 env->version |= def->nwindows - 1;
143#endif
144 return 0;
145}
146
e59be77a 147SPARCCPU *cpu_sparc_init(const char *cpu_model)
ab3b491f 148{
ab7ab3d7 149 SPARCCPU *cpu;
ab3b491f 150
ab7ab3d7 151 cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU));
ab3b491f 152
433ac7a9 153 if (cpu_sparc_register(cpu, cpu_model) < 0) {
5c099537 154 object_unref(OBJECT(cpu));
ab3b491f
BS		 155 return NULL;
156 }
b6e91ebf
AF		 157
158 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
ab3b491f 159
e59be77a 160 return cpu;
ab3b491f
BS		 161}
162
163void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
164{
165#if !defined(TARGET_SPARC64)
166 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
167#endif
168}
169
170static const sparc_def_t sparc_defs[] = {
171#ifdef TARGET_SPARC64
172 {
173 .name = "Fujitsu Sparc64",
174 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
175 .fpu_version = 0x00000000,
176 .mmu_version = mmu_us_12,
177 .nwindows = 4,
178 .maxtl = 4,
179 .features = CPU_DEFAULT_FEATURES,
180 },
181 {
182 .name = "Fujitsu Sparc64 III",
183 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
184 .fpu_version = 0x00000000,
185 .mmu_version = mmu_us_12,
186 .nwindows = 5,
187 .maxtl = 4,
188 .features = CPU_DEFAULT_FEATURES,
189 },
190 {
191 .name = "Fujitsu Sparc64 IV",
192 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
193 .fpu_version = 0x00000000,
194 .mmu_version = mmu_us_12,
195 .nwindows = 8,
196 .maxtl = 5,
197 .features = CPU_DEFAULT_FEATURES,
198 },
199 {
200 .name = "Fujitsu Sparc64 V",
201 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
202 .fpu_version = 0x00000000,
203 .mmu_version = mmu_us_12,
204 .nwindows = 8,
205 .maxtl = 5,
206 .features = CPU_DEFAULT_FEATURES,
207 },
208 {
209 .name = "TI UltraSparc I",
210 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
211 .fpu_version = 0x00000000,
212 .mmu_version = mmu_us_12,
213 .nwindows = 8,
214 .maxtl = 5,
215 .features = CPU_DEFAULT_FEATURES,
216 },
217 {
218 .name = "TI UltraSparc II",
219 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
220 .fpu_version = 0x00000000,
221 .mmu_version = mmu_us_12,
222 .nwindows = 8,
223 .maxtl = 5,
224 .features = CPU_DEFAULT_FEATURES,
225 },
226 {
227 .name = "TI UltraSparc IIi",
228 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
229 .fpu_version = 0x00000000,
230 .mmu_version = mmu_us_12,
231 .nwindows = 8,
232 .maxtl = 5,
233 .features = CPU_DEFAULT_FEATURES,
234 },
235 {
236 .name = "TI UltraSparc IIe",
237 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
238 .fpu_version = 0x00000000,
239 .mmu_version = mmu_us_12,
240 .nwindows = 8,
241 .maxtl = 5,
242 .features = CPU_DEFAULT_FEATURES,
243 },
244 {
245 .name = "Sun UltraSparc III",
246 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
247 .fpu_version = 0x00000000,
248 .mmu_version = mmu_us_12,
249 .nwindows = 8,
250 .maxtl = 5,
251 .features = CPU_DEFAULT_FEATURES,
252 },
253 {
254 .name = "Sun UltraSparc III Cu",
255 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
256 .fpu_version = 0x00000000,
257 .mmu_version = mmu_us_3,
258 .nwindows = 8,
259 .maxtl = 5,
260 .features = CPU_DEFAULT_FEATURES,
261 },
262 {
263 .name = "Sun UltraSparc IIIi",
264 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
265 .fpu_version = 0x00000000,
266 .mmu_version = mmu_us_12,
267 .nwindows = 8,
268 .maxtl = 5,
269 .features = CPU_DEFAULT_FEATURES,
270 },
271 {
272 .name = "Sun UltraSparc IV",
273 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
274 .fpu_version = 0x00000000,
275 .mmu_version = mmu_us_4,
276 .nwindows = 8,
277 .maxtl = 5,
278 .features = CPU_DEFAULT_FEATURES,
279 },
280 {
281 .name = "Sun UltraSparc IV+",
282 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
283 .fpu_version = 0x00000000,
284 .mmu_version = mmu_us_12,
285 .nwindows = 8,
286 .maxtl = 5,
287 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
288 },
289 {
290 .name = "Sun UltraSparc IIIi+",
291 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
292 .fpu_version = 0x00000000,
293 .mmu_version = mmu_us_3,
294 .nwindows = 8,
295 .maxtl = 5,
296 .features = CPU_DEFAULT_FEATURES,
297 },
298 {
299 .name = "Sun UltraSparc T1",
300 /* defined in sparc_ifu_fdp.v and ctu.h */
301 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
302 .fpu_version = 0x00000000,
303 .mmu_version = mmu_sun4v,
304 .nwindows = 8,
305 .maxtl = 6,
306 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
307 | CPU_FEATURE_GL,
308 },
309 {
310 .name = "Sun UltraSparc T2",
311 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
312 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
313 .fpu_version = 0x00000000,
314 .mmu_version = mmu_sun4v,
315 .nwindows = 8,
316 .maxtl = 6,
317 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
318 | CPU_FEATURE_GL,
319 },
320 {
321 .name = "NEC UltraSparc I",
322 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
323 .fpu_version = 0x00000000,
324 .mmu_version = mmu_us_12,
325 .nwindows = 8,
326 .maxtl = 5,
327 .features = CPU_DEFAULT_FEATURES,
328 },
329#else
ab3b491f
BS		 330 {
331 .name = "Fujitsu MB86904",
332 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
333 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
334 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
335 .mmu_bm = 0x00004000,
336 .mmu_ctpr_mask = 0x00ffffc0,
337 .mmu_cxr_mask = 0x000000ff,
338 .mmu_sfsr_mask = 0x00016fff,
339 .mmu_trcr_mask = 0x00ffffff,
340 .nwindows = 8,
341 .features = CPU_DEFAULT_FEATURES,
342 },
343 {
344 .name = "Fujitsu MB86907",
345 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
346 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
347 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
348 .mmu_bm = 0x00004000,
349 .mmu_ctpr_mask = 0xffffffc0,
350 .mmu_cxr_mask = 0x000000ff,
351 .mmu_sfsr_mask = 0x00016fff,
352 .mmu_trcr_mask = 0xffffffff,
353 .nwindows = 8,
354 .features = CPU_DEFAULT_FEATURES,
355 },
ab3b491f
BS		 356 {
357 .name = "TI MicroSparc I",
358 .iu_version = 0x41000000,
359 .fpu_version = 4 << 17,
360 .mmu_version = 0x41000000,
361 .mmu_bm = 0x00004000,
362 .mmu_ctpr_mask = 0x007ffff0,
363 .mmu_cxr_mask = 0x0000003f,
364 .mmu_sfsr_mask = 0x00016fff,
365 .mmu_trcr_mask = 0x0000003f,
366 .nwindows = 7,
367 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
368 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
369 CPU_FEATURE_FMUL,
370 },
371 {
372 .name = "TI MicroSparc II",
373 .iu_version = 0x42000000,
374 .fpu_version = 4 << 17,
375 .mmu_version = 0x02000000,
376 .mmu_bm = 0x00004000,
377 .mmu_ctpr_mask = 0x00ffffc0,
378 .mmu_cxr_mask = 0x000000ff,
379 .mmu_sfsr_mask = 0x00016fff,
380 .mmu_trcr_mask = 0x00ffffff,
381 .nwindows = 8,
382 .features = CPU_DEFAULT_FEATURES,
383 },
384 {
385 .name = "TI MicroSparc IIep",
386 .iu_version = 0x42000000,
387 .fpu_version = 4 << 17,
388 .mmu_version = 0x04000000,
389 .mmu_bm = 0x00004000,
390 .mmu_ctpr_mask = 0x00ffffc0,
391 .mmu_cxr_mask = 0x000000ff,
392 .mmu_sfsr_mask = 0x00016bff,
393 .mmu_trcr_mask = 0x00ffffff,
394 .nwindows = 8,
395 .features = CPU_DEFAULT_FEATURES,
396 },
397 {
398 .name = "TI SuperSparc 40", /* STP1020NPGA */
399 .iu_version = 0x41000000, /* SuperSPARC 2.x */
400 .fpu_version = 0 << 17,
401 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
402 .mmu_bm = 0x00002000,
403 .mmu_ctpr_mask = 0xffffffc0,
404 .mmu_cxr_mask = 0x0000ffff,
405 .mmu_sfsr_mask = 0xffffffff,
406 .mmu_trcr_mask = 0xffffffff,
407 .nwindows = 8,
408 .features = CPU_DEFAULT_FEATURES,
409 },
410 {
411 .name = "TI SuperSparc 50", /* STP1020PGA */
412 .iu_version = 0x40000000, /* SuperSPARC 3.x */
413 .fpu_version = 0 << 17,
414 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
415 .mmu_bm = 0x00002000,
416 .mmu_ctpr_mask = 0xffffffc0,
417 .mmu_cxr_mask = 0x0000ffff,
418 .mmu_sfsr_mask = 0xffffffff,
419 .mmu_trcr_mask = 0xffffffff,
420 .nwindows = 8,
421 .features = CPU_DEFAULT_FEATURES,
422 },
423 {
424 .name = "TI SuperSparc 51",
425 .iu_version = 0x40000000, /* SuperSPARC 3.x */
426 .fpu_version = 0 << 17,
427 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
428 .mmu_bm = 0x00002000,
429 .mmu_ctpr_mask = 0xffffffc0,
430 .mmu_cxr_mask = 0x0000ffff,
431 .mmu_sfsr_mask = 0xffffffff,
432 .mmu_trcr_mask = 0xffffffff,
433 .mxcc_version = 0x00000104,
434 .nwindows = 8,
435 .features = CPU_DEFAULT_FEATURES,
436 },
437 {
438 .name = "TI SuperSparc 60", /* STP1020APGA */
439 .iu_version = 0x40000000, /* SuperSPARC 3.x */
440 .fpu_version = 0 << 17,
441 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
442 .mmu_bm = 0x00002000,
443 .mmu_ctpr_mask = 0xffffffc0,
444 .mmu_cxr_mask = 0x0000ffff,
445 .mmu_sfsr_mask = 0xffffffff,
446 .mmu_trcr_mask = 0xffffffff,
447 .nwindows = 8,
448 .features = CPU_DEFAULT_FEATURES,
449 },
450 {
451 .name = "TI SuperSparc 61",
452 .iu_version = 0x44000000, /* SuperSPARC 3.x */
453 .fpu_version = 0 << 17,
454 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
455 .mmu_bm = 0x00002000,
456 .mmu_ctpr_mask = 0xffffffc0,
457 .mmu_cxr_mask = 0x0000ffff,
458 .mmu_sfsr_mask = 0xffffffff,
459 .mmu_trcr_mask = 0xffffffff,
460 .mxcc_version = 0x00000104,
461 .nwindows = 8,
462 .features = CPU_DEFAULT_FEATURES,
463 },
464 {
465 .name = "TI SuperSparc II",
466 .iu_version = 0x40000000, /* SuperSPARC II 1.x */
467 .fpu_version = 0 << 17,
468 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
469 .mmu_bm = 0x00002000,
470 .mmu_ctpr_mask = 0xffffffc0,
471 .mmu_cxr_mask = 0x0000ffff,
472 .mmu_sfsr_mask = 0xffffffff,
473 .mmu_trcr_mask = 0xffffffff,
474 .mxcc_version = 0x00000104,
475 .nwindows = 8,
476 .features = CPU_DEFAULT_FEATURES,
477 },
ab3b491f
BS		 478 {
479 .name = "LEON2",
480 .iu_version = 0xf2000000,
481 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
482 .mmu_version = 0xf2000000,
483 .mmu_bm = 0x00004000,
484 .mmu_ctpr_mask = 0x007ffff0,
485 .mmu_cxr_mask = 0x0000003f,
486 .mmu_sfsr_mask = 0xffffffff,
487 .mmu_trcr_mask = 0xffffffff,
488 .nwindows = 8,
489 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
490 },
491 {
492 .name = "LEON3",
493 .iu_version = 0xf3000000,
494 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
495 .mmu_version = 0xf3000000,
496 .mmu_bm = 0x00000000,
7a0a9c2c
RH		 497 .mmu_ctpr_mask = 0xfffffffc,
498 .mmu_cxr_mask = 0x000000ff,
ab3b491f
BS		 499 .mmu_sfsr_mask = 0xffffffff,
500 .mmu_trcr_mask = 0xffffffff,
501 .nwindows = 8,
502 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
16c358e9
SH		 503 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
504 CPU_FEATURE_CASA,
ab3b491f
BS		 505 },
506#endif
507};
508
509static const char * const feature_name[] = {
510 "float",
511 "float128",
512 "swap",
513 "mul",
514 "div",
515 "flush",
516 "fsqrt",
517 "fmul",
518 "vis1",
519 "vis2",
520 "fsmuld",
521 "hypv",
522 "cmt",
523 "gl",
524};
525
526static void print_features(FILE *f, fprintf_function cpu_fprintf,
527 uint32_t features, const char *prefix)
528{
529 unsigned int i;
530
531 for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
532 if (feature_name[i] && (features & (1 << i))) {
533 if (prefix) {
534 (*cpu_fprintf)(f, "%s", prefix);
535 }
536 (*cpu_fprintf)(f, "%s ", feature_name[i]);
537 }
538 }
539}
540
541static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
542{
543 unsigned int i;
544
545 for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
546 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
547 *features |= 1 << i;
548 return;
549 }
550 }
db5d39f7 551 error_report("CPU feature %s not found", flagname);
ab3b491f
BS		 552}
553
433ac7a9 554static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *name)
ab3b491f
BS		 555{
556 unsigned int i;
557 const sparc_def_t *def = NULL;
ab3b491f
BS		 558
559 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
560 if (strcasecmp(name, sparc_defs[i].name) == 0) {
561 def = &sparc_defs[i];
562 }
563 }
564 if (!def) {
433ac7a9 565 return -1;
ab3b491f
BS		 566 }
567 memcpy(cpu_def, def, sizeof(*def));
433ac7a9
AF		 568 return 0;
569}
ab3b491f 570
433ac7a9
AF		 571static void sparc_cpu_parse_features(CPUState *cs, char *features,
572 Error **errp)
573{
574 SPARCCPU *cpu = SPARC_CPU(cs);
575 sparc_def_t *cpu_def = cpu->env.def;
576 char *featurestr;
577 uint32_t plus_features = 0;
578 uint32_t minus_features = 0;
579 uint64_t iu_version;
580 uint32_t fpu_version, mmu_version, nwindows;
581
582 featurestr = features ? strtok(features, ",") : NULL;
ab3b491f
BS		 583 while (featurestr) {
584 char *val;
585
586 if (featurestr[0] == '+') {
587 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
588 } else if (featurestr[0] == '-') {
589 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
590 } else if ((val = strchr(featurestr, '='))) {
591 *val = 0; val++;
592 if (!strcmp(featurestr, "iu_version")) {
593 char *err;
594
595 iu_version = strtoll(val, &err, 0);
596 if (!*val || *err) {
433ac7a9
AF		 597 error_setg(errp, "bad numerical value %s", val);
598 return;
ab3b491f
BS		 599 }
600 cpu_def->iu_version = iu_version;
601#ifdef DEBUG_FEATURES
602 fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
603#endif
604 } else if (!strcmp(featurestr, "fpu_version")) {
605 char *err;
606
607 fpu_version = strtol(val, &err, 0);
608 if (!*val || *err) {
433ac7a9
AF		 609 error_setg(errp, "bad numerical value %s", val);
610 return;
ab3b491f
BS		 611 }
612 cpu_def->fpu_version = fpu_version;
613#ifdef DEBUG_FEATURES
614 fprintf(stderr, "fpu_version %x\n", fpu_version);
615#endif
616 } else if (!strcmp(featurestr, "mmu_version")) {
617 char *err;
618
619 mmu_version = strtol(val, &err, 0);
620 if (!*val || *err) {
433ac7a9
AF		 621 error_setg(errp, "bad numerical value %s", val);
622 return;
ab3b491f
BS		 623 }
624 cpu_def->mmu_version = mmu_version;
625#ifdef DEBUG_FEATURES
626 fprintf(stderr, "mmu_version %x\n", mmu_version);
627#endif
628 } else if (!strcmp(featurestr, "nwindows")) {
629 char *err;
630
631 nwindows = strtol(val, &err, 0);
632 if (!*val || *err || nwindows > MAX_NWINDOWS ||
633 nwindows < MIN_NWINDOWS) {
433ac7a9
AF		 634 error_setg(errp, "bad numerical value %s", val);
635 return;
ab3b491f
BS		 636 }
637 cpu_def->nwindows = nwindows;
638#ifdef DEBUG_FEATURES
639 fprintf(stderr, "nwindows %d\n", nwindows);
640#endif
641 } else {
433ac7a9
AF		 642 error_setg(errp, "unrecognized feature %s", featurestr);
643 return;
ab3b491f
BS		 644 }
645 } else {
433ac7a9
AF		 646 error_setg(errp, "feature string `%s' not in format "
647 "(+feature|-feature|feature=xyz)", featurestr);
648 return;
ab3b491f
BS		 649 }
650 featurestr = strtok(NULL, ",");
651 }
652 cpu_def->features |= plus_features;
653 cpu_def->features &= ~minus_features;
654#ifdef DEBUG_FEATURES
655 print_features(stderr, fprintf, cpu_def->features, NULL);
656#endif
ab3b491f
BS		 657}
658
659void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
660{
661 unsigned int i;
662
663 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
664 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
665 " FPU %08x MMU %08x NWINS %d ",
666 sparc_defs[i].name,
667 sparc_defs[i].iu_version,
668 sparc_defs[i].fpu_version,
669 sparc_defs[i].mmu_version,
670 sparc_defs[i].nwindows);
671 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
672 ~sparc_defs[i].features, "-");
673 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
674 sparc_defs[i].features, "+");
675 (*cpu_fprintf)(f, "\n");
676 }
677 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
678 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
679 (*cpu_fprintf)(f, "\n");
680 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
681 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
682 (*cpu_fprintf)(f, "\n");
683 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
684 "fpu_version mmu_version nwindows\n");
685}
686
687static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
688 uint32_t cc)
689{
690 cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
691 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
692 cc & PSR_CARRY ? 'C' : '-');
693}
694
695#ifdef TARGET_SPARC64
696#define REGS_PER_LINE 4
697#else
698#define REGS_PER_LINE 8
699#endif
700
878096ee
AF		 701void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
702 int flags)
ab3b491f 703{
878096ee
AF		 704 SPARCCPU *cpu = SPARC_CPU(cs);
705 CPUSPARCState *env = &cpu->env;
ab3b491f
BS		 706 int i, x;
707
708 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
709 env->npc);
ab3b491f
BS		 710
711 for (i = 0; i < 8; i++) {
712 if (i % REGS_PER_LINE == 0) {
713 cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
714 }
715 cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
716 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
717 cpu_fprintf(f, "\n");
718 }
719 }
ab3b491f
BS		 720 for (x = 0; x < 3; x++) {
721 for (i = 0; i < 8; i++) {
722 if (i % REGS_PER_LINE == 0) {
723 cpu_fprintf(f, "%%%c%d-%d: ",
724 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
725 i, i + REGS_PER_LINE - 1);
726 }
727 cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
728 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
729 cpu_fprintf(f, "\n");
730 }
731 }
732 }
76a23ca0 733
30038fd8 734 for (i = 0; i < TARGET_DPREGS; i++) {
ab3b491f 735 if ((i & 3) == 0) {
76a23ca0 736 cpu_fprintf(f, "%%f%02d: ", i * 2);
ab3b491f 737 }
30038fd8 738 cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
ab3b491f
BS		 739 if ((i & 3) == 3) {
740 cpu_fprintf(f, "\n");
741 }
742 }
743#ifdef TARGET_SPARC64
744 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
745 (unsigned)cpu_get_ccr(env));
746 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
747 cpu_fprintf(f, " xcc: ");
748 cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
749 cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
750 env->psrpil);
751 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
752 "cleanwin: %d cwp: %d\n",
753 env->cansave, env->canrestore, env->otherwin, env->wstate,
754 env->cleanwin, env->nwindows - 1 - env->cwp);
755 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
756 TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
757#else
758 cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
759 cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
760 cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
761 env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
762 env->wim);
763 cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
764 env->fsr, env->y);
765#endif
76a23ca0 766 cpu_fprintf(f, "\n");
ab3b491f 767}
ab7ab3d7 768
f45748f1
AF		 769static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
770{
771 SPARCCPU *cpu = SPARC_CPU(cs);
772
773 cpu->env.pc = value;
774 cpu->env.npc = value + 4;
775}
776
bdf7ae5b
AF		 777static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
778{
779 SPARCCPU *cpu = SPARC_CPU(cs);
780
781 cpu->env.pc = tb->pc;
782 cpu->env.npc = tb->cs_base;
783}
784
8c2e1b00
AF		 785static bool sparc_cpu_has_work(CPUState *cs)
786{
787 SPARCCPU *cpu = SPARC_CPU(cs);
788 CPUSPARCState *env = &cpu->env;
789
790 return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
791 cpu_interrupts_enabled(env);
792}
793
b6e91ebf
AF		 794static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
795{
b6e91ebf 796 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
247bf011
AF		 797#if defined(CONFIG_USER_ONLY)
798 SPARCCPU *cpu = SPARC_CPU(dev);
799 CPUSPARCState *env = &cpu->env;
800
801 if ((env->def->features & CPU_FEATURE_FLOAT)) {
802 env->def->features |= CPU_FEATURE_FLOAT128;
803 }
804#endif
b6e91ebf 805
14a10fc3
AF		 806 qemu_init_vcpu(CPU(dev));
807
b6e91ebf
AF		 808 scc->parent_realize(dev, errp);
809}
810
ab7ab3d7
AF		 811static void sparc_cpu_initfn(Object *obj)
812{
c05efcb1 813 CPUState *cs = CPU(obj);
ab7ab3d7
AF		 814 SPARCCPU *cpu = SPARC_CPU(obj);
815 CPUSPARCState *env = &cpu->env;
816
c05efcb1 817 cs->env_ptr = env;
4bad9e39 818 cpu_exec_init(cs, &error_abort);
5266d20a
AF		 819
820 if (tcg_enabled()) {
821 gen_intermediate_code_init(env);
822 }
ab7ab3d7
AF		 823}
824
825static void sparc_cpu_uninitfn(Object *obj)
826{
827 SPARCCPU *cpu = SPARC_CPU(obj);
828 CPUSPARCState *env = &cpu->env;
829
830 g_free(env->def);
831}
832
833static void sparc_cpu_class_init(ObjectClass *oc, void *data)
834{
835 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
836 CPUClass *cc = CPU_CLASS(oc);
b6e91ebf
AF		 837 DeviceClass *dc = DEVICE_CLASS(oc);
838
839 scc->parent_realize = dc->realize;
840 dc->realize = sparc_cpu_realizefn;
ab7ab3d7
AF		 841
842 scc->parent_reset = cc->reset;
843 cc->reset = sparc_cpu_reset;
97a8ea5a 844
8c2e1b00 845 cc->has_work = sparc_cpu_has_work;
97a8ea5a 846 cc->do_interrupt = sparc_cpu_do_interrupt;
87afe467 847 cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
878096ee 848 cc->dump_state = sparc_cpu_dump_state;
f3659eee
AF		 849#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
850 cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
851#endif
f45748f1 852 cc->set_pc = sparc_cpu_set_pc;
bdf7ae5b 853 cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
5b50e790
AF		 854 cc->gdb_read_register = sparc_cpu_gdb_read_register;
855 cc->gdb_write_register = sparc_cpu_gdb_write_register;
7510454e
AF		 856#ifdef CONFIG_USER_ONLY
857 cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault;
858#else
00b941e5 859 cc->do_unassigned_access = sparc_cpu_unassigned_access;
93e22326 860 cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
00b941e5 861 cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
df32c8d4 862 cc->vmsd = &vmstate_sparc_cpu;
00b941e5 863#endif
df0900eb 864 cc->disas_set_info = cpu_sparc_disas_set_info;
a0e372f0
AF		 865
866#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
867 cc->gdb_num_core_regs = 86;
868#else
869 cc->gdb_num_core_regs = 72;
870#endif
4c315c27
MA		 871
872 /*
873 * Reason: sparc_cpu_initfn() calls cpu_exec_init(), which saves
874 * the object in cpus -> dangling pointer after final
875 * object_unref().
876 */
877 dc->cannot_destroy_with_object_finalize_yet = true;
ab7ab3d7
AF		 878}
879
880static const TypeInfo sparc_cpu_type_info = {
881 .name = TYPE_SPARC_CPU,
882 .parent = TYPE_CPU,
883 .instance_size = sizeof(SPARCCPU),
884 .instance_init = sparc_cpu_initfn,
885 .instance_finalize = sparc_cpu_uninitfn,
886 .abstract = false,
887 .class_size = sizeof(SPARCCPUClass),
888 .class_init = sparc_cpu_class_init,
889};
890
891static void sparc_cpu_register_types(void)
892{
893 type_register_static(&sparc_cpu_type_info);
894}
895
896type_init(sparc_cpu_register_types)
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