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Commit | Line | Data |
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07f5a258 MA |
1 | #ifndef SPARC_CPU_H |
2 | #define SPARC_CPU_H | |
7a3f1944 | 3 | |
047b39e4 | 4 | #include "qemu-common.h" |
1de7afc9 | 5 | #include "qemu/bswap.h" |
d61d1b20 | 6 | #include "cpu-qom.h" |
af7bf89b | 7 | |
d94f0a8e PB |
8 | #define ALIGNED_ONLY |
9 | ||
af7bf89b | 10 | #if !defined(TARGET_SPARC64) |
3cf1e035 | 11 | #define TARGET_LONG_BITS 32 |
30038fd8 | 12 | #define TARGET_DPREGS 16 |
83469015 | 13 | #define TARGET_PAGE_BITS 12 /* 4k */ |
058ed88c RH |
14 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
15 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
16 | #else | |
17 | #define TARGET_LONG_BITS 64 | |
30038fd8 | 18 | #define TARGET_DPREGS 32 |
058ed88c | 19 | #define TARGET_PAGE_BITS 13 /* 8k */ |
52705890 RH |
20 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 |
21 | # ifdef TARGET_ABI32 | |
22 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
23 | # else | |
24 | # define TARGET_VIRT_ADDR_SPACE_BITS 44 | |
25 | # endif | |
af7bf89b | 26 | #endif |
3cf1e035 | 27 | |
9349b4f9 | 28 | #define CPUArchState struct CPUSPARCState |
c2764719 | 29 | |
022c62cb | 30 | #include "exec/cpu-defs.h" |
7a3f1944 | 31 | |
6b4c305c | 32 | #include "fpu/softfloat.h" |
7a0e1f41 | 33 | |
7a3f1944 FB |
34 | /*#define EXCP_INTERRUPT 0x100*/ |
35 | ||
cf495bcf | 36 | /* trap definitions */ |
3475187d | 37 | #ifndef TARGET_SPARC64 |
878d3096 | 38 | #define TT_TFAULT 0x01 |
cf495bcf | 39 | #define TT_ILL_INSN 0x02 |
e8af50a3 | 40 | #define TT_PRIV_INSN 0x03 |
e80cfcfc | 41 | #define TT_NFPU_INSN 0x04 |
cf495bcf | 42 | #define TT_WIN_OVF 0x05 |
5fafdf24 | 43 | #define TT_WIN_UNF 0x06 |
d2889a3e | 44 | #define TT_UNALIGNED 0x07 |
e8af50a3 | 45 | #define TT_FP_EXCP 0x08 |
878d3096 | 46 | #define TT_DFAULT 0x09 |
e32f879d | 47 | #define TT_TOVF 0x0a |
878d3096 | 48 | #define TT_EXTINT 0x10 |
1b2e93c1 | 49 | #define TT_CODE_ACCESS 0x21 |
64a88d5d | 50 | #define TT_UNIMP_FLUSH 0x25 |
b4f0a316 | 51 | #define TT_DATA_ACCESS 0x29 |
cf495bcf | 52 | #define TT_DIV_ZERO 0x2a |
fcc72045 | 53 | #define TT_NCP_INSN 0x24 |
cf495bcf | 54 | #define TT_TRAP 0x80 |
3475187d | 55 | #else |
8194f35a | 56 | #define TT_POWER_ON_RESET 0x01 |
3475187d | 57 | #define TT_TFAULT 0x08 |
1b2e93c1 | 58 | #define TT_CODE_ACCESS 0x0a |
3475187d | 59 | #define TT_ILL_INSN 0x10 |
64a88d5d | 60 | #define TT_UNIMP_FLUSH TT_ILL_INSN |
3475187d FB |
61 | #define TT_PRIV_INSN 0x11 |
62 | #define TT_NFPU_INSN 0x20 | |
63 | #define TT_FP_EXCP 0x21 | |
e32f879d | 64 | #define TT_TOVF 0x23 |
3475187d FB |
65 | #define TT_CLRWIN 0x24 |
66 | #define TT_DIV_ZERO 0x28 | |
67 | #define TT_DFAULT 0x30 | |
b4f0a316 | 68 | #define TT_DATA_ACCESS 0x32 |
d2889a3e | 69 | #define TT_UNALIGNED 0x34 |
83469015 | 70 | #define TT_PRIV_ACT 0x37 |
3475187d | 71 | #define TT_EXTINT 0x40 |
74b9decc | 72 | #define TT_IVEC 0x60 |
e19e4efe BS |
73 | #define TT_TMISS 0x64 |
74 | #define TT_DMISS 0x68 | |
74b9decc | 75 | #define TT_DPROT 0x6c |
3475187d FB |
76 | #define TT_SPILL 0x80 |
77 | #define TT_FILL 0xc0 | |
88c8e03f | 78 | #define TT_WOTHER (1 << 5) |
3475187d FB |
79 | #define TT_TRAP 0x100 |
80 | #endif | |
7a3f1944 | 81 | |
4b8b8b76 BS |
82 | #define PSR_NEG_SHIFT 23 |
83 | #define PSR_NEG (1 << PSR_NEG_SHIFT) | |
84 | #define PSR_ZERO_SHIFT 22 | |
85 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) | |
86 | #define PSR_OVF_SHIFT 21 | |
87 | #define PSR_OVF (1 << PSR_OVF_SHIFT) | |
88 | #define PSR_CARRY_SHIFT 20 | |
89 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) | |
e8af50a3 | 90 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
2aae2b8e | 91 | #if !defined(TARGET_SPARC64) |
e80cfcfc FB |
92 | #define PSR_EF (1<<12) |
93 | #define PSR_PIL 0xf00 | |
e8af50a3 FB |
94 | #define PSR_S (1<<7) |
95 | #define PSR_PS (1<<6) | |
96 | #define PSR_ET (1<<5) | |
97 | #define PSR_CWP 0x1f | |
2aae2b8e | 98 | #endif |
e8af50a3 | 99 | |
8393617c BS |
100 | #define CC_SRC (env->cc_src) |
101 | #define CC_SRC2 (env->cc_src2) | |
102 | #define CC_DST (env->cc_dst) | |
103 | #define CC_OP (env->cc_op) | |
104 | ||
c3ce5a23 PB |
105 | /* Even though lazy evaluation of CPU condition codes tends to be less |
106 | * important on RISC systems where condition codes are only updated | |
107 | * when explicitly requested, SPARC uses it to update 32-bit and 64-bit | |
108 | * condition codes. | |
109 | */ | |
8393617c BS |
110 | enum { |
111 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
112 | CC_OP_FLAGS, /* all cc are back in status register */ | |
113 | CC_OP_DIV, /* modify N, Z and V, C = 0*/ | |
114 | CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
115 | CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
116 | CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
117 | CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ | |
118 | CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
119 | CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
120 | CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
121 | CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ | |
122 | CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */ | |
123 | CC_OP_NB, | |
124 | }; | |
125 | ||
e8af50a3 FB |
126 | /* Trap base register */ |
127 | #define TBR_BASE_MASK 0xfffff000 | |
128 | ||
3475187d | 129 | #if defined(TARGET_SPARC64) |
5210977a IK |
130 | #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ |
131 | #define PS_IG (1<<11) /* v9, zero on UA2007 */ | |
132 | #define PS_MG (1<<10) /* v9, zero on UA2007 */ | |
133 | #define PS_CLE (1<<9) /* UA2007 */ | |
134 | #define PS_TLE (1<<8) /* UA2007 */ | |
6ef905f6 | 135 | #define PS_RMO (1<<7) |
5210977a IK |
136 | #define PS_RED (1<<5) /* v9, zero on UA2007 */ |
137 | #define PS_PEF (1<<4) /* enable fpu */ | |
138 | #define PS_AM (1<<3) /* address mask */ | |
3475187d FB |
139 | #define PS_PRIV (1<<2) |
140 | #define PS_IE (1<<1) | |
5210977a | 141 | #define PS_AG (1<<0) /* v9, zero on UA2007 */ |
a80dde08 FB |
142 | |
143 | #define FPRS_FEF (1<<2) | |
6f27aba6 BS |
144 | |
145 | #define HS_PRIV (1<<2) | |
3475187d FB |
146 | #endif |
147 | ||
e8af50a3 | 148 | /* Fcc */ |
ba6a9d8c BS |
149 | #define FSR_RD1 (1ULL << 31) |
150 | #define FSR_RD0 (1ULL << 30) | |
e8af50a3 FB |
151 | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) |
152 | #define FSR_RD_NEAREST 0 | |
153 | #define FSR_RD_ZERO FSR_RD0 | |
154 | #define FSR_RD_POS FSR_RD1 | |
155 | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) | |
156 | ||
ba6a9d8c BS |
157 | #define FSR_NVM (1ULL << 27) |
158 | #define FSR_OFM (1ULL << 26) | |
159 | #define FSR_UFM (1ULL << 25) | |
160 | #define FSR_DZM (1ULL << 24) | |
161 | #define FSR_NXM (1ULL << 23) | |
e8af50a3 FB |
162 | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) |
163 | ||
ba6a9d8c BS |
164 | #define FSR_NVA (1ULL << 9) |
165 | #define FSR_OFA (1ULL << 8) | |
166 | #define FSR_UFA (1ULL << 7) | |
167 | #define FSR_DZA (1ULL << 6) | |
168 | #define FSR_NXA (1ULL << 5) | |
e8af50a3 FB |
169 | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) |
170 | ||
ba6a9d8c BS |
171 | #define FSR_NVC (1ULL << 4) |
172 | #define FSR_OFC (1ULL << 3) | |
173 | #define FSR_UFC (1ULL << 2) | |
174 | #define FSR_DZC (1ULL << 1) | |
175 | #define FSR_NXC (1ULL << 0) | |
e8af50a3 FB |
176 | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) |
177 | ||
ba6a9d8c BS |
178 | #define FSR_FTT2 (1ULL << 16) |
179 | #define FSR_FTT1 (1ULL << 15) | |
180 | #define FSR_FTT0 (1ULL << 14) | |
47ad35f1 BS |
181 | //gcc warns about constant overflow for ~FSR_FTT_MASK |
182 | //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) | |
183 | #ifdef TARGET_SPARC64 | |
184 | #define FSR_FTT_NMASK 0xfffffffffffe3fffULL | |
185 | #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL | |
3a3b925d BS |
186 | #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
187 | #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL | |
188 | #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL | |
47ad35f1 BS |
189 | #else |
190 | #define FSR_FTT_NMASK 0xfffe3fffULL | |
191 | #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL | |
3a3b925d | 192 | #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
47ad35f1 | 193 | #endif |
3a3b925d | 194 | #define FSR_LDFSR_MASK 0xcfc00fffULL |
ba6a9d8c BS |
195 | #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
196 | #define FSR_FTT_UNIMPFPOP (3ULL << 14) | |
197 | #define FSR_FTT_SEQ_ERROR (4ULL << 14) | |
198 | #define FSR_FTT_INVAL_FPR (6ULL << 14) | |
e8af50a3 | 199 | |
4b8b8b76 | 200 | #define FSR_FCC1_SHIFT 11 |
ba6a9d8c | 201 | #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
4b8b8b76 | 202 | #define FSR_FCC0_SHIFT 10 |
ba6a9d8c | 203 | #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
e8af50a3 FB |
204 | |
205 | /* MMU */ | |
0f8a249a BS |
206 | #define MMU_E (1<<0) |
207 | #define MMU_NF (1<<1) | |
e8af50a3 FB |
208 | |
209 | #define PTE_ENTRYTYPE_MASK 3 | |
210 | #define PTE_ACCESS_MASK 0x1c | |
211 | #define PTE_ACCESS_SHIFT 2 | |
8d5f07fa | 212 | #define PTE_PPN_SHIFT 7 |
e8af50a3 FB |
213 | #define PTE_ADDR_MASK 0xffffff00 |
214 | ||
0f8a249a BS |
215 | #define PG_ACCESSED_BIT 5 |
216 | #define PG_MODIFIED_BIT 6 | |
e8af50a3 FB |
217 | #define PG_CACHE_BIT 7 |
218 | ||
219 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
220 | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) | |
221 | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) | |
222 | ||
1a14026e BS |
223 | /* 3 <= NWINDOWS <= 32. */ |
224 | #define MIN_NWINDOWS 3 | |
225 | #define MAX_NWINDOWS 32 | |
cf495bcf | 226 | |
6f27aba6 | 227 | #if !defined(TARGET_SPARC64) |
6ebbf390 | 228 | #define NB_MMU_MODES 2 |
6f27aba6 | 229 | #else |
2065061e | 230 | #define NB_MMU_MODES 6 |
375ee38b BS |
231 | typedef struct trap_state { |
232 | uint64_t tpc; | |
233 | uint64_t tnpc; | |
234 | uint64_t tstate; | |
235 | uint32_t tt; | |
236 | } trap_state; | |
6f27aba6 | 237 | #endif |
a3d5ad76 | 238 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 239 | |
5578ceab BS |
240 | typedef struct sparc_def_t { |
241 | const char *name; | |
242 | target_ulong iu_version; | |
243 | uint32_t fpu_version; | |
244 | uint32_t mmu_version; | |
245 | uint32_t mmu_bm; | |
246 | uint32_t mmu_ctpr_mask; | |
247 | uint32_t mmu_cxr_mask; | |
248 | uint32_t mmu_sfsr_mask; | |
249 | uint32_t mmu_trcr_mask; | |
963262de | 250 | uint32_t mxcc_version; |
5578ceab BS |
251 | uint32_t features; |
252 | uint32_t nwindows; | |
253 | uint32_t maxtl; | |
254 | } sparc_def_t; | |
255 | ||
b04d9890 FC |
256 | #define CPU_FEATURE_FLOAT (1 << 0) |
257 | #define CPU_FEATURE_FLOAT128 (1 << 1) | |
258 | #define CPU_FEATURE_SWAP (1 << 2) | |
259 | #define CPU_FEATURE_MUL (1 << 3) | |
260 | #define CPU_FEATURE_DIV (1 << 4) | |
261 | #define CPU_FEATURE_FLUSH (1 << 5) | |
262 | #define CPU_FEATURE_FSQRT (1 << 6) | |
263 | #define CPU_FEATURE_FMUL (1 << 7) | |
264 | #define CPU_FEATURE_VIS1 (1 << 8) | |
265 | #define CPU_FEATURE_VIS2 (1 << 9) | |
266 | #define CPU_FEATURE_FSMULD (1 << 10) | |
267 | #define CPU_FEATURE_HYPV (1 << 11) | |
268 | #define CPU_FEATURE_CMT (1 << 12) | |
269 | #define CPU_FEATURE_GL (1 << 13) | |
270 | #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ | |
4a2ba232 | 271 | #define CPU_FEATURE_ASR17 (1 << 15) |
60f356e8 | 272 | #define CPU_FEATURE_CACHE_CTRL (1 << 16) |
d1c36ba7 | 273 | #define CPU_FEATURE_POWERDOWN (1 << 17) |
16c358e9 | 274 | #define CPU_FEATURE_CASA (1 << 18) |
60f356e8 | 275 | |
5578ceab BS |
276 | #ifndef TARGET_SPARC64 |
277 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ | |
278 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ | |
279 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ | |
280 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) | |
281 | #else | |
282 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ | |
283 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ | |
284 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ | |
285 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ | |
16c358e9 SH |
286 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ |
287 | CPU_FEATURE_CASA) | |
5578ceab BS |
288 | enum { |
289 | mmu_us_12, // Ultrasparc < III (64 entry TLB) | |
290 | mmu_us_3, // Ultrasparc III (512 entry TLB) | |
291 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) | |
292 | mmu_sun4v, // T1, T2 | |
293 | }; | |
294 | #endif | |
295 | ||
f707726e | 296 | #define TTE_VALID_BIT (1ULL << 63) |
d1afc48b | 297 | #define TTE_NFO_BIT (1ULL << 60) |
f707726e IK |
298 | #define TTE_USED_BIT (1ULL << 41) |
299 | #define TTE_LOCKED_BIT (1ULL << 6) | |
d1afc48b | 300 | #define TTE_SIDEEFFECT_BIT (1ULL << 3) |
06e12b65 TS |
301 | #define TTE_PRIV_BIT (1ULL << 2) |
302 | #define TTE_W_OK_BIT (1ULL << 1) | |
2a90358f | 303 | #define TTE_GLOBAL_BIT (1ULL << 0) |
f707726e IK |
304 | |
305 | #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) | |
d1afc48b | 306 | #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) |
f707726e IK |
307 | #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) |
308 | #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) | |
d1afc48b | 309 | #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) |
06e12b65 TS |
310 | #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) |
311 | #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) | |
2a90358f | 312 | #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) |
f707726e IK |
313 | |
314 | #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) | |
315 | #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) | |
316 | ||
06e12b65 TS |
317 | #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) |
318 | #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) | |
319 | ||
ccc76c24 TS |
320 | #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ |
321 | #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ | |
322 | #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ | |
323 | #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ | |
324 | #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ | |
325 | #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ | |
326 | #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ | |
327 | #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ | |
328 | #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ | |
329 | #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ | |
330 | #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ | |
331 | #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ | |
332 | #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ | |
333 | ||
334 | #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ | |
335 | #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) | |
336 | #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ | |
337 | #define SFSR_CT_SECONDARY (1ULL << 4) | |
338 | #define SFSR_CT_NUCLEUS (2ULL << 4) | |
339 | #define SFSR_CT_NOTRANS (3ULL << 4) | |
340 | #define SFSR_CT_MASK (3ULL << 4) | |
341 | ||
79227036 BS |
342 | /* Leon3 cache control */ |
343 | ||
344 | /* Cache control: emulate the behavior of cache control registers but without | |
345 | any effect on the emulated */ | |
346 | ||
347 | #define CACHE_STATE_MASK 0x3 | |
348 | #define CACHE_DISABLED 0x0 | |
349 | #define CACHE_FROZEN 0x1 | |
350 | #define CACHE_ENABLED 0x3 | |
351 | ||
352 | /* Cache Control register fields */ | |
353 | ||
354 | #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ | |
355 | #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ | |
356 | #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ | |
357 | #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ | |
358 | #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ | |
359 | #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ | |
360 | #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ | |
361 | #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ | |
362 | ||
6e8e7d4c IK |
363 | typedef struct SparcTLBEntry { |
364 | uint64_t tag; | |
365 | uint64_t tte; | |
366 | } SparcTLBEntry; | |
367 | ||
8f4efc55 IK |
368 | struct CPUTimer |
369 | { | |
370 | const char *name; | |
371 | uint32_t frequency; | |
372 | uint32_t disabled; | |
373 | uint64_t disabled_mask; | |
e913cac7 MCA |
374 | uint32_t npt; |
375 | uint64_t npt_mask; | |
8f4efc55 | 376 | int64_t clock_offset; |
1246b259 | 377 | QEMUTimer *qtimer; |
8f4efc55 IK |
378 | }; |
379 | ||
380 | typedef struct CPUTimer CPUTimer; | |
381 | ||
cb159821 AF |
382 | typedef struct CPUSPARCState CPUSPARCState; |
383 | ||
384 | struct CPUSPARCState { | |
af7bf89b FB |
385 | target_ulong gregs[8]; /* general registers */ |
386 | target_ulong *regwptr; /* pointer to current register window */ | |
af7bf89b FB |
387 | target_ulong pc; /* program counter */ |
388 | target_ulong npc; /* next program counter */ | |
389 | target_ulong y; /* multiply/divide register */ | |
dc99a3f2 BS |
390 | |
391 | /* emulator internal flags handling */ | |
d9bdab86 | 392 | target_ulong cc_src, cc_src2; |
dc99a3f2 | 393 | target_ulong cc_dst; |
8393617c | 394 | uint32_t cc_op; |
dc99a3f2 | 395 | |
7c60cc4b FB |
396 | target_ulong cond; /* conditional branch result (XXX: save it in a |
397 | temporary register when possible) */ | |
398 | ||
cf495bcf | 399 | uint32_t psr; /* processor state register */ |
3475187d | 400 | target_ulong fsr; /* FPU state register */ |
30038fd8 | 401 | CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ |
cf495bcf FB |
402 | uint32_t cwp; /* index of current register window (extracted |
403 | from PSR) */ | |
5210977a | 404 | #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) |
cf495bcf | 405 | uint32_t wim; /* window invalid mask */ |
5210977a | 406 | #endif |
3475187d | 407 | target_ulong tbr; /* trap base register */ |
2aae2b8e | 408 | #if !defined(TARGET_SPARC64) |
e8af50a3 FB |
409 | int psrs; /* supervisor mode (extracted from PSR) */ |
410 | int psrps; /* previous supervisor mode */ | |
411 | int psret; /* enable traps */ | |
5210977a | 412 | #endif |
327ac2e7 BS |
413 | uint32_t psrpil; /* interrupt blocking level */ |
414 | uint32_t pil_in; /* incoming interrupt level bitmap */ | |
2aae2b8e | 415 | #if !defined(TARGET_SPARC64) |
e80cfcfc | 416 | int psref; /* enable fpu */ |
2aae2b8e | 417 | #endif |
cf495bcf | 418 | int interrupt_index; |
cf495bcf | 419 | /* NOTE: we allow 8 more registers to handle wrapping */ |
1a14026e | 420 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
d720b93d | 421 | |
a316d335 FB |
422 | CPU_COMMON |
423 | ||
f0c3c505 | 424 | /* Fields from here on are preserved across CPU reset. */ |
89aaf60d BS |
425 | target_ulong version; |
426 | uint32_t nwindows; | |
427 | ||
e8af50a3 | 428 | /* MMU regs */ |
3475187d FB |
429 | #if defined(TARGET_SPARC64) |
430 | uint64_t lsu; | |
431 | #define DMMU_E 0x8 | |
432 | #define IMMU_E 0x4 | |
6e8e7d4c IK |
433 | //typedef struct SparcMMU |
434 | union { | |
435 | uint64_t immuregs[16]; | |
436 | struct { | |
437 | uint64_t tsb_tag_target; | |
438 | uint64_t unused_mmu_primary_context; // use DMMU | |
439 | uint64_t unused_mmu_secondary_context; // use DMMU | |
440 | uint64_t sfsr; | |
441 | uint64_t sfar; | |
442 | uint64_t tsb; | |
443 | uint64_t tag_access; | |
444 | } immu; | |
445 | }; | |
446 | union { | |
447 | uint64_t dmmuregs[16]; | |
448 | struct { | |
449 | uint64_t tsb_tag_target; | |
450 | uint64_t mmu_primary_context; | |
451 | uint64_t mmu_secondary_context; | |
452 | uint64_t sfsr; | |
453 | uint64_t sfar; | |
454 | uint64_t tsb; | |
455 | uint64_t tag_access; | |
456 | } dmmu; | |
457 | }; | |
458 | SparcTLBEntry itlb[64]; | |
459 | SparcTLBEntry dtlb[64]; | |
fb79ceb9 | 460 | uint32_t mmu_version; |
3475187d | 461 | #else |
3dd9a152 | 462 | uint32_t mmuregs[32]; |
952a328f BS |
463 | uint64_t mxccdata[4]; |
464 | uint64_t mxccregs[8]; | |
4d2c2b77 BS |
465 | uint32_t mmubpctrv, mmubpctrc, mmubpctrs; |
466 | uint64_t mmubpaction; | |
4017190e | 467 | uint64_t mmubpregs[4]; |
3ebf5aaf | 468 | uint64_t prom_addr; |
3475187d | 469 | #endif |
e8af50a3 | 470 | /* temporary float registers */ |
1f587329 | 471 | float128 qt0, qt1; |
7a0e1f41 | 472 | float_status fp_status; |
af7bf89b | 473 | #if defined(TARGET_SPARC64) |
c19148bd BS |
474 | #define MAXTL_MAX 8 |
475 | #define MAXTL_MASK (MAXTL_MAX - 1) | |
c19148bd | 476 | trap_state ts[MAXTL_MAX]; |
0f8a249a | 477 | uint32_t xcc; /* Extended integer condition codes */ |
3475187d FB |
478 | uint32_t asi; |
479 | uint32_t pstate; | |
480 | uint32_t tl; | |
c19148bd | 481 | uint32_t maxtl; |
3475187d | 482 | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
83469015 FB |
483 | uint64_t agregs[8]; /* alternate general registers */ |
484 | uint64_t bgregs[8]; /* backup for normal global registers */ | |
485 | uint64_t igregs[8]; /* interrupt general registers */ | |
486 | uint64_t mgregs[8]; /* mmu general registers */ | |
3475187d | 487 | uint64_t fprs; |
83469015 | 488 | uint64_t tick_cmpr, stick_cmpr; |
8f4efc55 | 489 | CPUTimer *tick, *stick; |
709f2c1b IK |
490 | #define TICK_NPT_MASK 0x8000000000000000ULL |
491 | #define TICK_INT_DIS 0x8000000000000000ULL | |
725cb90b | 492 | uint64_t gsr; |
e9ebed4d BS |
493 | uint32_t gl; // UA2005 |
494 | /* UA 2005 hyperprivileged registers */ | |
c19148bd | 495 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
8f4efc55 | 496 | CPUTimer *hstick; // UA 2005 |
361dea40 BS |
497 | /* Interrupt vector registers */ |
498 | uint64_t ivec_status; | |
499 | uint64_t ivec_data[3]; | |
9d926598 | 500 | uint32_t softint; |
8fa211e8 BS |
501 | #define SOFTINT_TIMER 1 |
502 | #define SOFTINT_STIMER (1 << 16) | |
709f2c1b IK |
503 | #define SOFTINT_INTRMASK (0xFFFE) |
504 | #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) | |
3475187d | 505 | #endif |
5578ceab | 506 | sparc_def_t *def; |
b04d9890 FC |
507 | |
508 | void *irq_manager; | |
c5f9864e | 509 | void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); |
b04d9890 FC |
510 | |
511 | /* Leon3 cache control */ | |
512 | uint32_t cache_control; | |
cb159821 | 513 | }; |
64a88d5d | 514 | |
d61d1b20 PB |
515 | /** |
516 | * SPARCCPU: | |
517 | * @env: #CPUSPARCState | |
518 | * | |
519 | * A SPARC CPU. | |
520 | */ | |
521 | struct SPARCCPU { | |
522 | /*< private >*/ | |
523 | CPUState parent_obj; | |
524 | /*< public >*/ | |
525 | ||
526 | CPUSPARCState env; | |
527 | }; | |
528 | ||
529 | static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) | |
530 | { | |
531 | return container_of(env, SPARCCPU, env); | |
532 | } | |
533 | ||
534 | #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) | |
535 | ||
536 | #define ENV_OFFSET offsetof(SPARCCPU, env) | |
537 | ||
538 | #ifndef CONFIG_USER_ONLY | |
539 | extern const struct VMStateDescription vmstate_sparc_cpu; | |
540 | #endif | |
541 | ||
542 | void sparc_cpu_do_interrupt(CPUState *cpu); | |
543 | void sparc_cpu_dump_state(CPUState *cpu, FILE *f, | |
544 | fprintf_function cpu_fprintf, int flags); | |
545 | hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
546 | int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
547 | int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
b35399bb SS |
548 | void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
549 | MMUAccessType access_type, | |
550 | int mmu_idx, | |
551 | uintptr_t retaddr); | |
2f9d35fc | 552 | void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; |
e59be77a | 553 | |
5a834bb4 | 554 | #ifndef NO_CPU_IO_DEFS |
ab3b491f | 555 | /* cpu_init.c */ |
e59be77a | 556 | SPARCCPU *cpu_sparc_init(const char *cpu_model); |
91736d37 | 557 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
047b39e4 | 558 | void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
163fa5ca | 559 | /* mmu_helper.c */ |
7510454e | 560 | int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
97b348e7 | 561 | int mmu_idx); |
48585ec5 | 562 | target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); |
c5f9864e | 563 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); |
91736d37 | 564 | |
44520db1 | 565 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) |
f3659eee AF |
566 | int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, |
567 | uint8_t *buf, int len, bool is_write); | |
44520db1 FC |
568 | #endif |
569 | ||
570 | ||
91736d37 BS |
571 | /* translate.c */ |
572 | void gen_intermediate_code_init(CPUSPARCState *env); | |
573 | ||
574 | /* cpu-exec.c */ | |
7a3f1944 | 575 | |
070af384 | 576 | /* win_helper.c */ |
c5f9864e AF |
577 | target_ulong cpu_get_psr(CPUSPARCState *env1); |
578 | void cpu_put_psr(CPUSPARCState *env1, target_ulong val); | |
4552a09d | 579 | void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); |
5a834bb4 | 580 | #ifdef TARGET_SPARC64 |
c5f9864e AF |
581 | target_ulong cpu_get_ccr(CPUSPARCState *env1); |
582 | void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); | |
583 | target_ulong cpu_get_cwp64(CPUSPARCState *env1); | |
584 | void cpu_put_cwp64(CPUSPARCState *env1, int cwp); | |
585 | void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); | |
4c6aa085 | 586 | #endif |
c5f9864e AF |
587 | int cpu_cwp_inc(CPUSPARCState *env1, int cwp); |
588 | int cpu_cwp_dec(CPUSPARCState *env1, int cwp); | |
589 | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); | |
070af384 | 590 | |
79227036 | 591 | /* int_helper.c */ |
c5f9864e | 592 | void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); |
b04d9890 | 593 | |
4c6aa085 BS |
594 | /* sun4m.c, sun4u.c */ |
595 | void cpu_check_irqs(CPUSPARCState *env); | |
1a14026e | 596 | |
60f356e8 FC |
597 | /* leon3.c */ |
598 | void leon3_irq_ack(void *irq_manager, int intno); | |
599 | ||
299b520c IK |
600 | #if defined (TARGET_SPARC64) |
601 | ||
602 | static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) | |
603 | { | |
604 | return (x & mask) == (y & mask); | |
605 | } | |
606 | ||
607 | #define MMU_CONTEXT_BITS 13 | |
608 | #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) | |
609 | ||
610 | static inline int tlb_compare_context(const SparcTLBEntry *tlb, | |
611 | uint64_t context) | |
612 | { | |
613 | return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); | |
614 | } | |
615 | ||
0bbd4a0d | 616 | #endif |
3475187d FB |
617 | #endif |
618 | ||
91736d37 | 619 | /* cpu-exec.c */ |
3c7b48b7 | 620 | #if !defined(CONFIG_USER_ONLY) |
c658b94f AF |
621 | void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
622 | bool is_write, bool is_exec, int is_asi, | |
623 | unsigned size); | |
b64b6436 | 624 | #if defined(TARGET_SPARC64) |
a8170e5e | 625 | hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, |
2065061e | 626 | int mmu_idx); |
fe8d8f0f | 627 | #endif |
3c7b48b7 | 628 | #endif |
f0d5e471 | 629 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
7a3f1944 | 630 | |
e59be77a | 631 | #ifndef NO_CPU_IO_DEFS |
2994fd96 | 632 | #define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model)) |
e59be77a AF |
633 | #endif |
634 | ||
9467d44c | 635 | #define cpu_signal_handler cpu_sparc_signal_handler |
c732abe2 | 636 | #define cpu_list sparc_cpu_list |
9467d44c | 637 | |
6ebbf390 | 638 | /* MMU modes definitions */ |
2aae2b8e IK |
639 | #if defined (TARGET_SPARC64) |
640 | #define MMU_USER_IDX 0 | |
6f27aba6 | 641 | #define MMU_MODE0_SUFFIX _user |
2aae2b8e IK |
642 | #define MMU_USER_SECONDARY_IDX 1 |
643 | #define MMU_MODE1_SUFFIX _user_secondary | |
644 | #define MMU_KERNEL_IDX 2 | |
645 | #define MMU_MODE2_SUFFIX _kernel | |
646 | #define MMU_KERNEL_SECONDARY_IDX 3 | |
647 | #define MMU_MODE3_SUFFIX _kernel_secondary | |
648 | #define MMU_NUCLEUS_IDX 4 | |
649 | #define MMU_MODE4_SUFFIX _nucleus | |
650 | #define MMU_HYPV_IDX 5 | |
651 | #define MMU_MODE5_SUFFIX _hypv | |
652 | #else | |
9e31b9e2 | 653 | #define MMU_USER_IDX 0 |
2aae2b8e | 654 | #define MMU_MODE0_SUFFIX _user |
9e31b9e2 | 655 | #define MMU_KERNEL_IDX 1 |
2aae2b8e IK |
656 | #define MMU_MODE1_SUFFIX _kernel |
657 | #endif | |
658 | ||
659 | #if defined (TARGET_SPARC64) | |
c5f9864e | 660 | static inline int cpu_has_hypervisor(CPUSPARCState *env1) |
2aae2b8e IK |
661 | { |
662 | return env1->def->features & CPU_FEATURE_HYPV; | |
663 | } | |
664 | ||
c5f9864e | 665 | static inline int cpu_hypervisor_mode(CPUSPARCState *env1) |
2aae2b8e IK |
666 | { |
667 | return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); | |
668 | } | |
669 | ||
c5f9864e | 670 | static inline int cpu_supervisor_mode(CPUSPARCState *env1) |
2aae2b8e IK |
671 | { |
672 | return env1->pstate & PS_PRIV; | |
673 | } | |
2065061e | 674 | #endif |
9e31b9e2 | 675 | |
97ed5ccd | 676 | static inline int cpu_mmu_index(CPUSPARCState *env1, bool ifetch) |
6ebbf390 | 677 | { |
6f27aba6 | 678 | #if defined(CONFIG_USER_ONLY) |
9e31b9e2 | 679 | return MMU_USER_IDX; |
6f27aba6 | 680 | #elif !defined(TARGET_SPARC64) |
22548760 | 681 | return env1->psrs; |
6f27aba6 | 682 | #else |
9fd1ae3a IK |
683 | if (env1->tl > 0) { |
684 | return MMU_NUCLEUS_IDX; | |
685 | } else if (cpu_hypervisor_mode(env1)) { | |
9e31b9e2 | 686 | return MMU_HYPV_IDX; |
2aae2b8e IK |
687 | } else if (cpu_supervisor_mode(env1)) { |
688 | return MMU_KERNEL_IDX; | |
689 | } else { | |
690 | return MMU_USER_IDX; | |
691 | } | |
6f27aba6 BS |
692 | #endif |
693 | } | |
694 | ||
c5f9864e | 695 | static inline int cpu_interrupts_enabled(CPUSPARCState *env1) |
2df6c2d0 IK |
696 | { |
697 | #if !defined (TARGET_SPARC64) | |
698 | if (env1->psret != 0) | |
699 | return 1; | |
700 | #else | |
701 | if (env1->pstate & PS_IE) | |
702 | return 1; | |
703 | #endif | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
c5f9864e | 708 | static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) |
d532b26c IK |
709 | { |
710 | #if !defined(TARGET_SPARC64) | |
711 | /* level 15 is non-maskable on sparc v8 */ | |
712 | return pil == 15 || pil > env1->psrpil; | |
713 | #else | |
714 | return pil > env1->psrpil; | |
715 | #endif | |
716 | } | |
717 | ||
022c62cb | 718 | #include "exec/cpu-all.h" |
7a3f1944 | 719 | |
f4b1a842 BS |
720 | #ifdef TARGET_SPARC64 |
721 | /* sun4u.c */ | |
8f4efc55 IK |
722 | void cpu_tick_set_count(CPUTimer *timer, uint64_t count); |
723 | uint64_t cpu_tick_get_count(CPUTimer *timer); | |
724 | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); | |
c5f9864e | 725 | trap_state* cpu_tsptr(CPUSPARCState* env); |
f4b1a842 BS |
726 | #endif |
727 | ||
99a23063 RH |
728 | #define TB_FLAG_MMU_MASK 7 |
729 | #define TB_FLAG_FPU_ENABLED (1 << 4) | |
730 | #define TB_FLAG_AM_ENABLED (1 << 5) | |
a6d567e5 | 731 | #define TB_FLAG_ASI_SHIFT 24 |
f838e2c5 | 732 | |
c5f9864e | 733 | static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, |
99a23063 | 734 | target_ulong *cs_base, uint32_t *pflags) |
6b917547 | 735 | { |
99a23063 | 736 | uint32_t flags; |
6b917547 AL |
737 | *pc = env->pc; |
738 | *cs_base = env->npc; | |
99a23063 | 739 | flags = cpu_mmu_index(env, false); |
6b917547 | 740 | #ifdef TARGET_SPARC64 |
f838e2c5 | 741 | if (env->pstate & PS_AM) { |
99a23063 | 742 | flags |= TB_FLAG_AM_ENABLED; |
f838e2c5 | 743 | } |
99a23063 RH |
744 | if ((env->def->features & CPU_FEATURE_FLOAT) |
745 | && (env->pstate & PS_PEF) | |
f838e2c5 | 746 | && (env->fprs & FPRS_FEF)) { |
99a23063 | 747 | flags |= TB_FLAG_FPU_ENABLED; |
f838e2c5 | 748 | } |
a6d567e5 | 749 | flags |= env->asi << TB_FLAG_ASI_SHIFT; |
6b917547 | 750 | #else |
f838e2c5 | 751 | if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) { |
99a23063 | 752 | flags |= TB_FLAG_FPU_ENABLED; |
f838e2c5 BS |
753 | } |
754 | #endif | |
99a23063 | 755 | *pflags = flags; |
f838e2c5 BS |
756 | } |
757 | ||
758 | static inline bool tb_fpu_enabled(int tb_flags) | |
759 | { | |
760 | #if defined(CONFIG_USER_ONLY) | |
761 | return true; | |
762 | #else | |
763 | return tb_flags & TB_FLAG_FPU_ENABLED; | |
764 | #endif | |
765 | } | |
766 | ||
767 | static inline bool tb_am_enabled(int tb_flags) | |
768 | { | |
769 | #ifndef TARGET_SPARC64 | |
770 | return false; | |
771 | #else | |
772 | return tb_flags & TB_FLAG_AM_ENABLED; | |
6b917547 AL |
773 | #endif |
774 | } | |
775 | ||
7a3f1944 | 776 | #endif |