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1 | #ifndef CPU_SPARC_H |
2 | #define CPU_SPARC_H | |
3 | ||
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4 | #define TARGET_LONG_BITS 32 |
5 | ||
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6 | #include "cpu-defs.h" |
7 | ||
8 | /*#define EXCP_INTERRUPT 0x100*/ | |
9 | ||
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10 | /* trap definitions */ |
11 | #define TT_ILL_INSN 0x02 | |
e8af50a3 | 12 | #define TT_PRIV_INSN 0x03 |
e80cfcfc | 13 | #define TT_NFPU_INSN 0x04 |
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14 | #define TT_WIN_OVF 0x05 |
15 | #define TT_WIN_UNF 0x06 | |
e8af50a3 | 16 | #define TT_FP_EXCP 0x08 |
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17 | #define TT_DIV_ZERO 0x2a |
18 | #define TT_TRAP 0x80 | |
e80cfcfc | 19 | #define TT_EXTINT 0x10 |
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20 | |
21 | #define PSR_NEG (1<<23) | |
22 | #define PSR_ZERO (1<<22) | |
23 | #define PSR_OVF (1<<21) | |
24 | #define PSR_CARRY (1<<20) | |
e8af50a3 | 25 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
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26 | #define PSR_EF (1<<12) |
27 | #define PSR_PIL 0xf00 | |
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28 | #define PSR_S (1<<7) |
29 | #define PSR_PS (1<<6) | |
30 | #define PSR_ET (1<<5) | |
31 | #define PSR_CWP 0x1f | |
32 | /* Fake impl 0, version 4 */ | |
e80cfcfc FB |
33 | #define GET_PSR(env) ((0 << 28) | (4 << 24) | env->psr | \ |
34 | (env->psref? PSR_EF : 0) | \ | |
35 | (env->psrpil << 8) | \ | |
36 | (env->psrs? PSR_S : 0) | \ | |
37 | (env->psrs? PSR_PS : 0) | \ | |
38 | (env->psret? PSR_ET : 0) | env->cwp) | |
39 | ||
40 | #define PUT_PSR(env, val) do { int _tmp = val; \ | |
41 | env->psr = _tmp & ~PSR_ICC; \ | |
42 | env->psref = (_tmp & PSR_EF)? 1 : 0; \ | |
43 | env->psrpil = (_tmp & PSR_PIL) >> 8; \ | |
44 | env->psrs = (_tmp & PSR_S)? 1 : 0; \ | |
45 | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ | |
46 | env->psret = (_tmp & PSR_ET)? 1 : 0; \ | |
47 | set_cwp(_tmp & PSR_CWP & (NWINDOWS - 1)); \ | |
48 | } while (0) | |
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49 | |
50 | /* Trap base register */ | |
51 | #define TBR_BASE_MASK 0xfffff000 | |
52 | ||
53 | /* Fcc */ | |
54 | #define FSR_RD1 (1<<31) | |
55 | #define FSR_RD0 (1<<30) | |
56 | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) | |
57 | #define FSR_RD_NEAREST 0 | |
58 | #define FSR_RD_ZERO FSR_RD0 | |
59 | #define FSR_RD_POS FSR_RD1 | |
60 | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) | |
61 | ||
62 | #define FSR_NVM (1<<27) | |
63 | #define FSR_OFM (1<<26) | |
64 | #define FSR_UFM (1<<25) | |
65 | #define FSR_DZM (1<<24) | |
66 | #define FSR_NXM (1<<23) | |
67 | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) | |
68 | ||
69 | #define FSR_NVA (1<<9) | |
70 | #define FSR_OFA (1<<8) | |
71 | #define FSR_UFA (1<<7) | |
72 | #define FSR_DZA (1<<6) | |
73 | #define FSR_NXA (1<<5) | |
74 | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) | |
75 | ||
76 | #define FSR_NVC (1<<4) | |
77 | #define FSR_OFC (1<<3) | |
78 | #define FSR_UFC (1<<2) | |
79 | #define FSR_DZC (1<<1) | |
80 | #define FSR_NXC (1<<0) | |
81 | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) | |
82 | ||
83 | #define FSR_FTT2 (1<<16) | |
84 | #define FSR_FTT1 (1<<15) | |
85 | #define FSR_FTT0 (1<<14) | |
86 | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) | |
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87 | #define FSR_FTT_IEEE_EXCP (1 << 14) |
88 | #define FSR_FTT_UNIMPFPOP (3 << 14) | |
89 | #define FSR_FTT_INVAL_FPR (6 << 14) | |
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90 | |
91 | #define FSR_FCC1 (1<<11) | |
92 | #define FSR_FCC0 (1<<10) | |
93 | ||
94 | /* MMU */ | |
95 | #define MMU_E (1<<0) | |
96 | #define MMU_NF (1<<1) | |
97 | ||
98 | #define PTE_ENTRYTYPE_MASK 3 | |
99 | #define PTE_ACCESS_MASK 0x1c | |
100 | #define PTE_ACCESS_SHIFT 2 | |
8d5f07fa | 101 | #define PTE_PPN_SHIFT 7 |
e8af50a3 FB |
102 | #define PTE_ADDR_MASK 0xffffff00 |
103 | ||
104 | #define PG_ACCESSED_BIT 5 | |
105 | #define PG_MODIFIED_BIT 6 | |
106 | #define PG_CACHE_BIT 7 | |
107 | ||
108 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
109 | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) | |
110 | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) | |
111 | ||
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112 | #define NWINDOWS 32 |
113 | ||
7a3f1944 | 114 | typedef struct CPUSPARCState { |
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115 | uint32_t gregs[8]; /* general registers */ |
116 | uint32_t *regwptr; /* pointer to current register window */ | |
e8af50a3 | 117 | float fpr[32]; /* floating point registers */ |
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118 | uint32_t pc; /* program counter */ |
119 | uint32_t npc; /* next program counter */ | |
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120 | uint32_t y; /* multiply/divide register */ |
121 | uint32_t psr; /* processor state register */ | |
e8af50a3 | 122 | uint32_t fsr; /* FPU state register */ |
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123 | uint32_t T2; |
124 | uint32_t cwp; /* index of current register window (extracted | |
125 | from PSR) */ | |
126 | uint32_t wim; /* window invalid mask */ | |
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127 | uint32_t tbr; /* trap base register */ |
128 | int psrs; /* supervisor mode (extracted from PSR) */ | |
129 | int psrps; /* previous supervisor mode */ | |
130 | int psret; /* enable traps */ | |
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131 | int psrpil; /* interrupt level */ |
132 | int psref; /* enable fpu */ | |
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133 | jmp_buf jmp_env; |
134 | int user_mode_only; | |
135 | int exception_index; | |
136 | int interrupt_index; | |
137 | int interrupt_request; | |
e8af50a3 | 138 | uint32_t exception_next_pc; |
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139 | struct TranslationBlock *current_tb; |
140 | void *opaque; | |
141 | /* NOTE: we allow 8 more registers to handle wrapping */ | |
142 | uint32_t regbase[NWINDOWS * 16 + 8]; | |
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143 | |
144 | /* in order to avoid passing too many arguments to the memory | |
145 | write helpers, we store some rarely used information in the CPU | |
146 | context) */ | |
147 | unsigned long mem_write_pc; /* host pc at which the memory was | |
148 | written */ | |
149 | unsigned long mem_write_vaddr; /* target virtual addr at which the | |
150 | memory was written */ | |
e8af50a3 FB |
151 | /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ |
152 | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; | |
153 | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; | |
154 | int error_code; | |
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155 | /* MMU regs */ |
156 | uint32_t mmuregs[16]; | |
157 | /* temporary float registers */ | |
158 | float ft0, ft1, ft2; | |
159 | double dt0, dt1, dt2; | |
160 | ||
161 | /* ice debug support */ | |
162 | uint32_t breakpoints[MAX_BREAKPOINTS]; | |
163 | int nb_breakpoints; | |
164 | int singlestep_enabled; /* XXX: should use CPU single step mode instead */ | |
165 | ||
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166 | } CPUSPARCState; |
167 | ||
168 | CPUSPARCState *cpu_sparc_init(void); | |
169 | int cpu_sparc_exec(CPUSPARCState *s); | |
170 | int cpu_sparc_close(CPUSPARCState *s); | |
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171 | void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f); |
172 | double cpu_put_fp64(uint64_t mant, uint16_t exp); | |
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173 | |
174 | struct siginfo; | |
175 | int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); | |
7a3f1944 | 176 | |
e8af50a3 | 177 | #define TARGET_PAGE_BITS 12 /* 4k */ |
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178 | #include "cpu-all.h" |
179 | ||
180 | #endif |