[mirror_qemu.git] / target-sparc / fop_helper.c

/*
 * FPU op helpers
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"

#define QT0 (env->qt0)
#define QT1 (env->qt1)

#define F_HELPER(name, p) void helper_f##name##p(CPUState *env)

#define F_BINOP(name)                                           \
    float32 helper_f ## name ## s (CPUState * env, float32 src1,\
                                   float32 src2)                \
    {                                                           \
        return float32_ ## name (src1, src2, &env->fp_status);  \
    }                                                           \
    float64 helper_f ## name ## d (CPUState * env, float64 src1,\
                                   float64 src2)                \
    {                                                           \
        return float64_ ## name (src1, src2, &env->fp_status);  \
    }                                                           \
    F_HELPER(name, q)                                           \
    {                                                           \
        QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \
    }

F_BINOP(add);
F_BINOP(sub);
F_BINOP(mul);
F_BINOP(div);
#undef F_BINOP

float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2)
{
    return float64_mul(float32_to_float64(src1, &env->fp_status),
                       float32_to_float64(src2, &env->fp_status),
                       &env->fp_status);
}

void helper_fdmulq(CPUState *env, float64 src1, float64 src2)
{
    QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
                       float64_to_float128(src2, &env->fp_status),
                       &env->fp_status);
}

float32 helper_fnegs(float32 src)
{
    return float32_chs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fnegd(float64 src)
{
    return float64_chs(src);
}

F_HELPER(neg, q)
{
    QT0 = float128_chs(QT1);
}
#endif

/* Integer to float conversion.  */
float32 helper_fitos(CPUState *env, int32_t src)
{
    return int32_to_float32(src, &env->fp_status);
}

float64 helper_fitod(CPUState *env, int32_t src)
{
    return int32_to_float64(src, &env->fp_status);
}

void helper_fitoq(CPUState *env, int32_t src)
{
    QT0 = int32_to_float128(src, &env->fp_status);
}

#ifdef TARGET_SPARC64
float32 helper_fxtos(CPUState *env, int64_t src)
{
    return int64_to_float32(src, &env->fp_status);
}

float64 helper_fxtod(CPUState *env, int64_t src)
{
    return int64_to_float64(src, &env->fp_status);
}

void helper_fxtoq(CPUState *env, int64_t src)
{
    QT0 = int64_to_float128(src, &env->fp_status);
}
#endif
#undef F_HELPER

/* floating point conversion */
float32 helper_fdtos(CPUState *env, float64 src)
{
    return float64_to_float32(src, &env->fp_status);
}

float64 helper_fstod(CPUState *env, float32 src)
{
    return float32_to_float64(src, &env->fp_status);
}

float32 helper_fqtos(CPUState *env)
{
    return float128_to_float32(QT1, &env->fp_status);
}

void helper_fstoq(CPUState *env, float32 src)
{
    QT0 = float32_to_float128(src, &env->fp_status);
}

float64 helper_fqtod(CPUState *env)
{
    return float128_to_float64(QT1, &env->fp_status);
}

void helper_fdtoq(CPUState *env, float64 src)
{
    QT0 = float64_to_float128(src, &env->fp_status);
}

/* Float to integer conversion.  */
int32_t helper_fstoi(CPUState *env, float32 src)
{
    return float32_to_int32_round_to_zero(src, &env->fp_status);
}

int32_t helper_fdtoi(CPUState *env, float64 src)
{
    return float64_to_int32_round_to_zero(src, &env->fp_status);
}

int32_t helper_fqtoi(CPUState *env)
{
    return float128_to_int32_round_to_zero(QT1, &env->fp_status);
}

#ifdef TARGET_SPARC64
int64_t helper_fstox(CPUState *env, float32 src)
{
    return float32_to_int64_round_to_zero(src, &env->fp_status);
}

int64_t helper_fdtox(CPUState *env, float64 src)
{
    return float64_to_int64_round_to_zero(src, &env->fp_status);
}

int64_t helper_fqtox(CPUState *env)
{
    return float128_to_int64_round_to_zero(QT1, &env->fp_status);
}
#endif

float32 helper_fabss(float32 src)
{
    return float32_abs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fabsd(float64 src)
{
    return float64_abs(src);
}

void helper_fabsq(CPUState *env)
{
    QT0 = float128_abs(QT1);
}
#endif

float32 helper_fsqrts(CPUState *env, float32 src)
{
    return float32_sqrt(src, &env->fp_status);
}

float64 helper_fsqrtd(CPUState *env, float64 src)
{
    return float64_sqrt(src, &env->fp_status);
}

void helper_fsqrtq(CPUState *env)
{
    QT0 = float128_sqrt(QT1, &env->fp_status);
}

#define GEN_FCMP(name, size, reg1, reg2, FS, E)                         \
    void glue(helper_, name) (CPUState *env)                            \
    {                                                                   \
        env->fsr &= FSR_FTT_NMASK;                                      \
        if (E && (glue(size, _is_any_nan)(reg1) ||                      \
                  glue(size, _is_any_nan)(reg2)) &&                     \
            (env->fsr & FSR_NVM)) {                                     \
            env->fsr |= FSR_NVC;                                        \
            env->fsr |= FSR_FTT_IEEE_EXCP;                              \
            helper_raise_exception(env, TT_FP_EXCP);                    \
        }                                                               \
        switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
        case float_relation_unordered:                                  \
            if ((env->fsr & FSR_NVM)) {                                 \
                env->fsr |= FSR_NVC;                                    \
                env->fsr |= FSR_FTT_IEEE_EXCP;                          \
                helper_raise_exception(env, TT_FP_EXCP);                \
            } else {                                                    \
                env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);             \
                env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                \
                env->fsr |= FSR_NVA;                                    \
            }                                                           \
            break;                                                      \
        case float_relation_less:                                       \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC0 << FS;                                 \
            break;                                                      \
        case float_relation_greater:                                    \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC1 << FS;                                 \
            break;                                                      \
        default:                                                        \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            break;                                                      \
        }                                                               \
    }
#define GEN_FCMP_T(name, size, FS, E)                                   \
    void glue(helper_, name)(CPUState *env, size src1, size src2)       \
    {                                                                   \
        env->fsr &= FSR_FTT_NMASK;                                      \
        if (E && (glue(size, _is_any_nan)(src1) ||                      \
                  glue(size, _is_any_nan)(src2)) &&                     \
            (env->fsr & FSR_NVM)) {                                     \
            env->fsr |= FSR_NVC;                                        \
            env->fsr |= FSR_FTT_IEEE_EXCP;                              \
            helper_raise_exception(env, TT_FP_EXCP);                    \
        }                                                               \
        switch (glue(size, _compare) (src1, src2, &env->fp_status)) {   \
        case float_relation_unordered:                                  \
            if ((env->fsr & FSR_NVM)) {                                 \
                env->fsr |= FSR_NVC;                                    \
                env->fsr |= FSR_FTT_IEEE_EXCP;                          \
                helper_raise_exception(env, TT_FP_EXCP);                \
            } else {                                                    \
                env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);             \
                env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                \
                env->fsr |= FSR_NVA;                                    \
            }                                                           \
            break;                                                      \
        case float_relation_less:                                       \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC0 << FS;                                 \
            break;                                                      \
        case float_relation_greater:                                    \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC1 << FS;                                 \
            break;                                                      \
        default:                                                        \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            break;                                                      \
        }                                                               \
    }

GEN_FCMP_T(fcmps, float32, 0, 0);
GEN_FCMP_T(fcmpd, float64, 0, 0);

GEN_FCMP_T(fcmpes, float32, 0, 1);
GEN_FCMP_T(fcmped, float64, 0, 1);

GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);

#ifdef TARGET_SPARC64
GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);

GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);

GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);

GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);

GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);

GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#endif
#undef GEN_FCMP_T
#undef GEN_FCMP

void helper_check_ieee_exceptions(CPUState *env)
{
    target_ulong status;

    status = get_float_exception_flags(&env->fp_status);
    if (status) {
        /* Copy IEEE 754 flags into FSR */
        if (status & float_flag_invalid) {
            env->fsr |= FSR_NVC;
        }
        if (status & float_flag_overflow) {
            env->fsr |= FSR_OFC;
        }
        if (status & float_flag_underflow) {
            env->fsr |= FSR_UFC;
        }
        if (status & float_flag_divbyzero) {
            env->fsr |= FSR_DZC;
        }
        if (status & float_flag_inexact) {
            env->fsr |= FSR_NXC;
        }

        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
            /* Unmasked exception, generate a trap */
            env->fsr |= FSR_FTT_IEEE_EXCP;
            helper_raise_exception(env, TT_FP_EXCP);
        } else {
            /* Accumulate exceptions */
            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
        }
    }
}

void helper_clear_float_exceptions(CPUState *env)
{
    set_float_exception_flags(0, &env->fp_status);
}

static inline void set_fsr(CPUState *env)
{
    int rnd_mode;

    switch (env->fsr & FSR_RD_MASK) {
    case FSR_RD_NEAREST:
        rnd_mode = float_round_nearest_even;
        break;
    default:
    case FSR_RD_ZERO:
        rnd_mode = float_round_to_zero;
        break;
    case FSR_RD_POS:
        rnd_mode = float_round_up;
        break;
    case FSR_RD_NEG:
        rnd_mode = float_round_down;
        break;
    }
    set_float_rounding_mode(rnd_mode, &env->fp_status);
}

void helper_ldfsr(CPUState *env, uint32_t new_fsr)
{
    env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
    set_fsr(env);
}

#ifdef TARGET_SPARC64
void helper_ldxfsr(CPUState *env, uint64_t new_fsr)
{
    env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
    set_fsr(env);
}
#endif
Commit	Line	Data
1bccec25 BS	1	/*
	2	* FPU op helpers
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
1bccec25 BS	21	#include "helper.h"
1bccec25 BS	22
1bccec25 BS	23	#define QT0 (env->qt0)
	24	#define QT1 (env->qt1)
	25
2e2f4ade	26	#define F_HELPER(name, p) void helper_f##name##p(CPUState *env)
1bccec25 BS	27
1bccec25 BS	28	#define F_BINOP(name) \
2e2f4ade BS	29	float32 helper_f ## name ## s (CPUState * env, float32 src1,\
2e2f4ade BS	30	float32 src2) \
1bccec25 BS	31	{ \
	32	return float32_ ## name (src1, src2, &env->fp_status); \
	33	} \
03fb8cfc RH	34	float64 helper_f ## name ## d (CPUState * env, float64 src1,\
03fb8cfc RH	35	float64 src2) \
1bccec25	36	{ \
03fb8cfc	37	return float64_ ## name (src1, src2, &env->fp_status); \
1bccec25 BS	38	} \
	39	F_HELPER(name, q) \
	40	{ \
	41	QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
	42	}
	43
	44	F_BINOP(add);
	45	F_BINOP(sub);
	46	F_BINOP(mul);
	47	F_BINOP(div);
	48	#undef F_BINOP
	49
03fb8cfc	50	float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2)
1bccec25	51	{
03fb8cfc RH	52	return float64_mul(float32_to_float64(src1, &env->fp_status),
	53	float32_to_float64(src2, &env->fp_status),
	54	&env->fp_status);
1bccec25 BS	55	}
1bccec25 BS	56
03fb8cfc	57	void helper_fdmulq(CPUState *env, float64 src1, float64 src2)
1bccec25	58	{
03fb8cfc RH	59	QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
03fb8cfc RH	60	float64_to_float128(src2, &env->fp_status),
1bccec25 BS	61	&env->fp_status);
	62	}
	63
	64	float32 helper_fnegs(float32 src)
	65	{
	66	return float32_chs(src);
	67	}
	68
	69	#ifdef TARGET_SPARC64
03fb8cfc	70	float64 helper_fnegd(float64 src)
1bccec25	71	{
03fb8cfc	72	return float64_chs(src);
1bccec25 BS	73	}
	74
	75	F_HELPER(neg, q)
	76	{
	77	QT0 = float128_chs(QT1);
	78	}
	79	#endif
	80
	81	/* Integer to float conversion. */
2e2f4ade	82	float32 helper_fitos(CPUState *env, int32_t src)
1bccec25 BS	83	{
	84	return int32_to_float32(src, &env->fp_status);
	85	}
	86
03fb8cfc	87	float64 helper_fitod(CPUState *env, int32_t src)
1bccec25	88	{
03fb8cfc	89	return int32_to_float64(src, &env->fp_status);
1bccec25 BS	90	}
1bccec25 BS	91
2e2f4ade	92	void helper_fitoq(CPUState *env, int32_t src)
1bccec25 BS	93	{
	94	QT0 = int32_to_float128(src, &env->fp_status);
	95	}
	96
	97	#ifdef TARGET_SPARC64
03fb8cfc	98	float32 helper_fxtos(CPUState *env, int64_t src)
1bccec25	99	{
03fb8cfc	100	return int64_to_float32(src, &env->fp_status);
1bccec25 BS	101	}
1bccec25 BS	102
03fb8cfc	103	float64 helper_fxtod(CPUState *env, int64_t src)
1bccec25	104	{
03fb8cfc	105	return int64_to_float64(src, &env->fp_status);
1bccec25 BS	106	}
1bccec25 BS	107
03fb8cfc	108	void helper_fxtoq(CPUState *env, int64_t src)
1bccec25	109	{
03fb8cfc	110	QT0 = int64_to_float128(src, &env->fp_status);
1bccec25 BS	111	}
	112	#endif
	113	#undef F_HELPER
	114
	115	/* floating point conversion */
03fb8cfc	116	float32 helper_fdtos(CPUState *env, float64 src)
1bccec25	117	{
03fb8cfc	118	return float64_to_float32(src, &env->fp_status);
1bccec25 BS	119	}
1bccec25 BS	120
03fb8cfc	121	float64 helper_fstod(CPUState *env, float32 src)
1bccec25	122	{
03fb8cfc	123	return float32_to_float64(src, &env->fp_status);
1bccec25 BS	124	}
1bccec25 BS	125
2e2f4ade	126	float32 helper_fqtos(CPUState *env)
1bccec25 BS	127	{
	128	return float128_to_float32(QT1, &env->fp_status);
	129	}
	130
2e2f4ade	131	void helper_fstoq(CPUState *env, float32 src)
1bccec25 BS	132	{
	133	QT0 = float32_to_float128(src, &env->fp_status);
	134	}
	135
03fb8cfc	136	float64 helper_fqtod(CPUState *env)
1bccec25	137	{
03fb8cfc	138	return float128_to_float64(QT1, &env->fp_status);
1bccec25 BS	139	}
1bccec25 BS	140
03fb8cfc	141	void helper_fdtoq(CPUState *env, float64 src)
1bccec25	142	{
03fb8cfc	143	QT0 = float64_to_float128(src, &env->fp_status);
1bccec25 BS	144	}
	145
	146	/* Float to integer conversion. */
2e2f4ade	147	int32_t helper_fstoi(CPUState *env, float32 src)
1bccec25 BS	148	{
	149	return float32_to_int32_round_to_zero(src, &env->fp_status);
	150	}
	151
03fb8cfc	152	int32_t helper_fdtoi(CPUState *env, float64 src)
1bccec25	153	{
03fb8cfc	154	return float64_to_int32_round_to_zero(src, &env->fp_status);
1bccec25 BS	155	}
1bccec25 BS	156
2e2f4ade	157	int32_t helper_fqtoi(CPUState *env)
1bccec25 BS	158	{
	159	return float128_to_int32_round_to_zero(QT1, &env->fp_status);
	160	}
	161
	162	#ifdef TARGET_SPARC64
03fb8cfc	163	int64_t helper_fstox(CPUState *env, float32 src)
1bccec25	164	{
03fb8cfc	165	return float32_to_int64_round_to_zero(src, &env->fp_status);
1bccec25 BS	166	}
1bccec25 BS	167
03fb8cfc	168	int64_t helper_fdtox(CPUState *env, float64 src)
1bccec25	169	{
03fb8cfc	170	return float64_to_int64_round_to_zero(src, &env->fp_status);
1bccec25 BS	171	}
1bccec25 BS	172
03fb8cfc	173	int64_t helper_fqtox(CPUState *env)
1bccec25	174	{
03fb8cfc	175	return float128_to_int64_round_to_zero(QT1, &env->fp_status);
1bccec25 BS	176	}
	177	#endif
	178
	179	float32 helper_fabss(float32 src)
	180	{
	181	return float32_abs(src);
	182	}
	183
	184	#ifdef TARGET_SPARC64
f027c3b1	185	float64 helper_fabsd(float64 src)
1bccec25	186	{
03fb8cfc	187	return float64_abs(src);
1bccec25 BS	188	}
1bccec25 BS	189
2e2f4ade	190	void helper_fabsq(CPUState *env)
1bccec25 BS	191	{
	192	QT0 = float128_abs(QT1);
	193	}
	194	#endif
	195
2e2f4ade	196	float32 helper_fsqrts(CPUState *env, float32 src)
1bccec25 BS	197	{
	198	return float32_sqrt(src, &env->fp_status);
	199	}
	200
03fb8cfc	201	float64 helper_fsqrtd(CPUState *env, float64 src)
1bccec25	202	{
03fb8cfc	203	return float64_sqrt(src, &env->fp_status);
1bccec25 BS	204	}
1bccec25 BS	205
2e2f4ade	206	void helper_fsqrtq(CPUState *env)
1bccec25 BS	207	{
	208	QT0 = float128_sqrt(QT1, &env->fp_status);
	209	}
	210
	211	#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
2e2f4ade	212	void glue(helper_, name) (CPUState *env) \
1bccec25 BS	213	{ \
	214	env->fsr &= FSR_FTT_NMASK; \
	215	if (E && (glue(size, _is_any_nan)(reg1) \|\| \
	216	glue(size, _is_any_nan)(reg2)) && \
	217	(env->fsr & FSR_NVM)) { \
	218	env->fsr \|= FSR_NVC; \
	219	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	220	helper_raise_exception(env, TT_FP_EXCP); \
	221	} \
	222	switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
	223	case float_relation_unordered: \
	224	if ((env->fsr & FSR_NVM)) { \
	225	env->fsr \|= FSR_NVC; \
	226	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	227	helper_raise_exception(env, TT_FP_EXCP); \
	228	} else { \
	229	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	230	env->fsr \|= (FSR_FCC1 \| FSR_FCC0) << FS; \
	231	env->fsr \|= FSR_NVA; \
	232	} \
	233	break; \
	234	case float_relation_less: \
	235	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	236	env->fsr \|= FSR_FCC0 << FS; \
	237	break; \
	238	case float_relation_greater: \
	239	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	240	env->fsr \|= FSR_FCC1 << FS; \
	241	break; \
	242	default: \
	243	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	244	break; \
	245	} \
	246	}
03fb8cfc RH	247	#define GEN_FCMP_T(name, size, FS, E) \
03fb8cfc RH	248	void glue(helper_, name)(CPUState *env, size src1, size src2) \
1bccec25 BS	249	{ \
	250	env->fsr &= FSR_FTT_NMASK; \
	251	if (E && (glue(size, _is_any_nan)(src1) \|\| \
	252	glue(size, _is_any_nan)(src2)) && \
	253	(env->fsr & FSR_NVM)) { \
	254	env->fsr \|= FSR_NVC; \
	255	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	256	helper_raise_exception(env, TT_FP_EXCP); \
	257	} \
	258	switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
	259	case float_relation_unordered: \
	260	if ((env->fsr & FSR_NVM)) { \
	261	env->fsr \|= FSR_NVC; \
	262	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	263	helper_raise_exception(env, TT_FP_EXCP); \
	264	} else { \
	265	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	266	env->fsr \|= (FSR_FCC1 \| FSR_FCC0) << FS; \
	267	env->fsr \|= FSR_NVA; \
	268	} \
	269	break; \
	270	case float_relation_less: \
	271	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	272	env->fsr \|= FSR_FCC0 << FS; \
	273	break; \
	274	case float_relation_greater: \
	275	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	276	env->fsr \|= FSR_FCC1 << FS; \
	277	break; \
	278	default: \
	279	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	280	break; \
	281	} \
	282	}
	283
03fb8cfc RH	284	GEN_FCMP_T(fcmps, float32, 0, 0);
03fb8cfc RH	285	GEN_FCMP_T(fcmpd, float64, 0, 0);
1bccec25	286
03fb8cfc RH	287	GEN_FCMP_T(fcmpes, float32, 0, 1);
03fb8cfc RH	288	GEN_FCMP_T(fcmped, float64, 0, 1);
1bccec25 BS	289
	290	GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
	291	GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
	292
	293	#ifdef TARGET_SPARC64
03fb8cfc RH	294	GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
03fb8cfc RH	295	GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
1bccec25 BS	296	GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1bccec25 BS	297
03fb8cfc RH	298	GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
03fb8cfc RH	299	GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
1bccec25 BS	300	GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1bccec25 BS	301
03fb8cfc RH	302	GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
03fb8cfc RH	303	GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
1bccec25 BS	304	GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1bccec25 BS	305
03fb8cfc RH	306	GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
03fb8cfc RH	307	GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
1bccec25 BS	308	GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1bccec25 BS	309
03fb8cfc RH	310	GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
03fb8cfc RH	311	GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
1bccec25 BS	312	GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1bccec25 BS	313
03fb8cfc RH	314	GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
03fb8cfc RH	315	GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
1bccec25 BS	316	GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1bccec25 BS	317	#endif
03fb8cfc RH	318	#undef GEN_FCMP_T
03fb8cfc RH	319	#undef GEN_FCMP
1bccec25	320
2e2f4ade	321	void helper_check_ieee_exceptions(CPUState *env)
1bccec25 BS	322	{
	323	target_ulong status;
	324
	325	status = get_float_exception_flags(&env->fp_status);
	326	if (status) {
	327	/* Copy IEEE 754 flags into FSR */
	328	if (status & float_flag_invalid) {
	329	env->fsr \|= FSR_NVC;
	330	}
	331	if (status & float_flag_overflow) {
	332	env->fsr \|= FSR_OFC;
	333	}
	334	if (status & float_flag_underflow) {
	335	env->fsr \|= FSR_UFC;
	336	}
	337	if (status & float_flag_divbyzero) {
	338	env->fsr \|= FSR_DZC;
	339	}
	340	if (status & float_flag_inexact) {
	341	env->fsr \|= FSR_NXC;
	342	}
	343
	344	if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
	345	/* Unmasked exception, generate a trap */
	346	env->fsr \|= FSR_FTT_IEEE_EXCP;
	347	helper_raise_exception(env, TT_FP_EXCP);
	348	} else {
	349	/* Accumulate exceptions */
	350	env->fsr \|= (env->fsr & FSR_CEXC_MASK) << 5;
	351	}
	352	}
	353	}
	354
2e2f4ade	355	void helper_clear_float_exceptions(CPUState *env)
1bccec25 BS	356	{
	357	set_float_exception_flags(0, &env->fp_status);
	358	}
	359
2e2f4ade	360	static inline void set_fsr(CPUState *env)
1bccec25 BS	361	{
	362	int rnd_mode;
	363
	364	switch (env->fsr & FSR_RD_MASK) {
	365	case FSR_RD_NEAREST:
	366	rnd_mode = float_round_nearest_even;
	367	break;
	368	default:
	369	case FSR_RD_ZERO:
	370	rnd_mode = float_round_to_zero;
	371	break;
	372	case FSR_RD_POS:
	373	rnd_mode = float_round_up;
	374	break;
	375	case FSR_RD_NEG:
	376	rnd_mode = float_round_down;
	377	break;
	378	}
	379	set_float_rounding_mode(rnd_mode, &env->fp_status);
	380	}
	381
2e2f4ade	382	void helper_ldfsr(CPUState *env, uint32_t new_fsr)
1bccec25 BS	383	{
1bccec25 BS	384	env->fsr = (new_fsr & FSR_LDFSR_MASK) \| (env->fsr & FSR_LDFSR_OLDMASK);
2e2f4ade	385	set_fsr(env);
1bccec25 BS	386	}
	387
	388	#ifdef TARGET_SPARC64
2e2f4ade	389	void helper_ldxfsr(CPUState *env, uint64_t new_fsr)
1bccec25 BS	390	{
1bccec25 BS	391	env->fsr = (new_fsr & FSR_LDXFSR_MASK) \| (env->fsr & FSR_LDXFSR_OLDMASK);
2e2f4ade	392	set_fsr(env);
1bccec25 BS	393	}
1bccec25 BS	394	#endif