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Commit | Line | Data |
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e8af50a3 | 1 | /* |
163fa5ca | 2 | * Misc Sparc helpers |
5fafdf24 | 3 | * |
83469015 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
e8af50a3 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e8af50a3 | 18 | */ |
ee5bbe38 | 19 | |
db5ebe5f | 20 | #include "qemu/osdep.h" |
ee5bbe38 | 21 | #include "cpu.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
1de7afc9 | 23 | #include "qemu/host-utils.h" |
2ef6175a | 24 | #include "exec/helper-proto.h" |
9c17d615 | 25 | #include "sysemu/sysemu.h" |
e8af50a3 | 26 | |
c5f9864e | 27 | void helper_raise_exception(CPUSPARCState *env, int tt) |
bc265319 | 28 | { |
27103424 AF |
29 | CPUState *cs = CPU(sparc_env_get_cpu(env)); |
30 | ||
31 | cs->exception_index = tt; | |
5638d180 | 32 | cpu_loop_exit(cs); |
bc265319 BS |
33 | } |
34 | ||
c5f9864e | 35 | void helper_debug(CPUSPARCState *env) |
bc265319 | 36 | { |
27103424 AF |
37 | CPUState *cs = CPU(sparc_env_get_cpu(env)); |
38 | ||
39 | cs->exception_index = EXCP_DEBUG; | |
5638d180 | 40 | cpu_loop_exit(cs); |
bc265319 BS |
41 | } |
42 | ||
2336c1f1 BS |
43 | #ifdef TARGET_SPARC64 |
44 | target_ulong helper_popc(target_ulong val) | |
45 | { | |
46 | return ctpop64(val); | |
47 | } | |
48 | ||
49 | void helper_tick_set_count(void *opaque, uint64_t count) | |
50 | { | |
51 | #if !defined(CONFIG_USER_ONLY) | |
52 | cpu_tick_set_count(opaque, count); | |
53 | #endif | |
54 | } | |
55 | ||
c9a46442 | 56 | uint64_t helper_tick_get_count(CPUSPARCState *env, void *opaque, int mem_idx) |
2336c1f1 BS |
57 | { |
58 | #if !defined(CONFIG_USER_ONLY) | |
c9a46442 MCA |
59 | CPUTimer *timer = opaque; |
60 | ||
61 | if (timer->npt && mem_idx < MMU_KERNEL_IDX) { | |
62 | helper_raise_exception(env, TT_PRIV_INSN); | |
63 | } | |
64 | ||
65 | return cpu_tick_get_count(timer); | |
2336c1f1 BS |
66 | #else |
67 | return 0; | |
68 | #endif | |
69 | } | |
70 | ||
71 | void helper_tick_set_limit(void *opaque, uint64_t limit) | |
72 | { | |
73 | #if !defined(CONFIG_USER_ONLY) | |
74 | cpu_tick_set_limit(opaque, limit); | |
75 | #endif | |
76 | } | |
77 | #endif | |
7a5e4488 | 78 | |
c5f9864e | 79 | static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, |
7a5e4488 BS |
80 | target_ulong b, int cc) |
81 | { | |
3f38f309 | 82 | SPARCCPU *cpu = sparc_env_get_cpu(env); |
7a5e4488 BS |
83 | int overflow = 0; |
84 | uint64_t x0; | |
85 | uint32_t x1; | |
86 | ||
87 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); | |
88 | x1 = (b & 0xffffffff); | |
89 | ||
90 | if (x1 == 0) { | |
3f38f309 | 91 | cpu_restore_state(CPU(cpu), GETPC()); |
7a5e4488 BS |
92 | helper_raise_exception(env, TT_DIV_ZERO); |
93 | } | |
94 | ||
95 | x0 = x0 / x1; | |
6a5b69a9 OD |
96 | if (x0 > UINT32_MAX) { |
97 | x0 = UINT32_MAX; | |
7a5e4488 BS |
98 | overflow = 1; |
99 | } | |
100 | ||
101 | if (cc) { | |
102 | env->cc_dst = x0; | |
103 | env->cc_src2 = overflow; | |
104 | env->cc_op = CC_OP_DIV; | |
105 | } | |
106 | return x0; | |
107 | } | |
108 | ||
c5f9864e | 109 | target_ulong helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong b) |
7a5e4488 BS |
110 | { |
111 | return helper_udiv_common(env, a, b, 0); | |
112 | } | |
113 | ||
c5f9864e | 114 | target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b) |
7a5e4488 BS |
115 | { |
116 | return helper_udiv_common(env, a, b, 1); | |
117 | } | |
118 | ||
c5f9864e | 119 | static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, |
7a5e4488 BS |
120 | target_ulong b, int cc) |
121 | { | |
3f38f309 | 122 | SPARCCPU *cpu = sparc_env_get_cpu(env); |
7a5e4488 BS |
123 | int overflow = 0; |
124 | int64_t x0; | |
125 | int32_t x1; | |
126 | ||
127 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); | |
128 | x1 = (b & 0xffffffff); | |
129 | ||
130 | if (x1 == 0) { | |
3f38f309 | 131 | cpu_restore_state(CPU(cpu), GETPC()); |
7a5e4488 | 132 | helper_raise_exception(env, TT_DIV_ZERO); |
6a5b69a9 OD |
133 | } else if (x1 == -1 && x0 == INT64_MIN) { |
134 | x0 = INT32_MAX; | |
7a5e4488 | 135 | overflow = 1; |
6a5b69a9 OD |
136 | } else { |
137 | x0 = x0 / x1; | |
138 | if ((int32_t) x0 != x0) { | |
139 | x0 = x0 < 0 ? INT32_MIN : INT32_MAX; | |
140 | overflow = 1; | |
141 | } | |
7a5e4488 BS |
142 | } |
143 | ||
144 | if (cc) { | |
145 | env->cc_dst = x0; | |
146 | env->cc_src2 = overflow; | |
147 | env->cc_op = CC_OP_DIV; | |
148 | } | |
149 | return x0; | |
150 | } | |
151 | ||
c5f9864e | 152 | target_ulong helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong b) |
7a5e4488 BS |
153 | { |
154 | return helper_sdiv_common(env, a, b, 0); | |
155 | } | |
156 | ||
c5f9864e | 157 | target_ulong helper_sdiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b) |
7a5e4488 BS |
158 | { |
159 | return helper_sdiv_common(env, a, b, 1); | |
160 | } | |
c28ae41e RH |
161 | |
162 | #ifdef TARGET_SPARC64 | |
163 | int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b) | |
164 | { | |
165 | if (b == 0) { | |
166 | /* Raise divide by zero trap. */ | |
3f38f309 AF |
167 | SPARCCPU *cpu = sparc_env_get_cpu(env); |
168 | ||
169 | cpu_restore_state(CPU(cpu), GETPC()); | |
c28ae41e RH |
170 | helper_raise_exception(env, TT_DIV_ZERO); |
171 | } else if (b == -1) { | |
172 | /* Avoid overflow trap with i386 divide insn. */ | |
173 | return -a; | |
174 | } else { | |
175 | return a / b; | |
176 | } | |
177 | } | |
178 | ||
179 | uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) | |
180 | { | |
181 | if (b == 0) { | |
182 | /* Raise divide by zero trap. */ | |
3f38f309 AF |
183 | SPARCCPU *cpu = sparc_env_get_cpu(env); |
184 | ||
185 | cpu_restore_state(CPU(cpu), GETPC()); | |
c28ae41e RH |
186 | helper_raise_exception(env, TT_DIV_ZERO); |
187 | } | |
188 | return a / b; | |
189 | } | |
190 | #endif | |
a2ea4aa9 RH |
191 | |
192 | target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1, | |
193 | target_ulong src2) | |
194 | { | |
3f38f309 | 195 | SPARCCPU *cpu = sparc_env_get_cpu(env); |
a2ea4aa9 RH |
196 | target_ulong dst; |
197 | ||
198 | /* Tag overflow occurs if either input has bits 0 or 1 set. */ | |
199 | if ((src1 | src2) & 3) { | |
200 | goto tag_overflow; | |
201 | } | |
202 | ||
203 | dst = src1 + src2; | |
204 | ||
205 | /* Tag overflow occurs if the addition overflows. */ | |
206 | if (~(src1 ^ src2) & (src1 ^ dst) & (1u << 31)) { | |
207 | goto tag_overflow; | |
208 | } | |
209 | ||
210 | /* Only modify the CC after any exceptions have been generated. */ | |
211 | env->cc_op = CC_OP_TADDTV; | |
212 | env->cc_src = src1; | |
213 | env->cc_src2 = src2; | |
214 | env->cc_dst = dst; | |
215 | return dst; | |
216 | ||
217 | tag_overflow: | |
3f38f309 | 218 | cpu_restore_state(CPU(cpu), GETPC()); |
a2ea4aa9 RH |
219 | helper_raise_exception(env, TT_TOVF); |
220 | } | |
221 | ||
222 | target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, | |
223 | target_ulong src2) | |
224 | { | |
3f38f309 | 225 | SPARCCPU *cpu = sparc_env_get_cpu(env); |
a2ea4aa9 RH |
226 | target_ulong dst; |
227 | ||
228 | /* Tag overflow occurs if either input has bits 0 or 1 set. */ | |
229 | if ((src1 | src2) & 3) { | |
230 | goto tag_overflow; | |
231 | } | |
232 | ||
233 | dst = src1 - src2; | |
234 | ||
235 | /* Tag overflow occurs if the subtraction overflows. */ | |
236 | if ((src1 ^ src2) & (src1 ^ dst) & (1u << 31)) { | |
237 | goto tag_overflow; | |
238 | } | |
239 | ||
240 | /* Only modify the CC after any exceptions have been generated. */ | |
241 | env->cc_op = CC_OP_TSUBTV; | |
242 | env->cc_src = src1; | |
243 | env->cc_src2 = src2; | |
244 | env->cc_dst = dst; | |
245 | return dst; | |
246 | ||
247 | tag_overflow: | |
3f38f309 | 248 | cpu_restore_state(CPU(cpu), GETPC()); |
a2ea4aa9 RH |
249 | helper_raise_exception(env, TT_TOVF); |
250 | } | |
d1c36ba7 RH |
251 | |
252 | #ifndef TARGET_SPARC64 | |
253 | void helper_power_down(CPUSPARCState *env) | |
254 | { | |
259186a7 AF |
255 | CPUState *cs = CPU(sparc_env_get_cpu(env)); |
256 | ||
257 | cs->halted = 1; | |
27103424 | 258 | cs->exception_index = EXCP_HLT; |
d1c36ba7 RH |
259 | env->pc = env->npc; |
260 | env->npc = env->pc + 4; | |
5638d180 | 261 | cpu_loop_exit(cs); |
d1c36ba7 RH |
262 | } |
263 | #endif |