[mirror_qemu.git] / target-sparc / helper.c

/*
 *  sparc helpers
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

//#define DEBUG_MMU

/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

#if defined(CONFIG_USER_ONLY)

int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu)
{
    if (rw & 2)
        env->exception_index = TT_TFAULT;
    else
        env->exception_index = TT_DFAULT;
    return 1;
}

#else

#ifndef TARGET_SPARC64
/*
 * Sparc V8 Reference MMU (SRMMU)
 */
static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

static const int perm_table[2][8] = {
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC
    },
    {
        PAGE_READ,
        PAGE_READ | PAGE_WRITE,
        PAGE_READ | PAGE_EXEC,
        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
        PAGE_EXEC,
        PAGE_READ,
        0,
        0,
    }
};

int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
                          int *access_index, target_ulong address, int rw,
                          int mmu_idx)
{
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
    uint32_t pde;
    target_ulong virt_addr;
    int error_code = 0, is_dirty, is_user;
    unsigned long page_offset;

    is_user = mmu_idx == MMU_USER_IDX;
    virt_addr = address & TARGET_PAGE_MASK;

    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
        // Boot mode: instruction fetches are taken from PROM
        if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
            *physical = env->prom_addr | (address & 0x7ffffULL);
            *prot = PAGE_READ | PAGE_EXEC;
            return 0;
        }
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        return 0;
    }

    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
    *physical = 0xffffffffffff0000ULL;

    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
        return 1 << 2;
    case 2: /* L0 PTE, maybe should not happen? */
    case 3: /* Reserved */
        return 4 << 2;
    case 1: /* L0 PDE */
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
            return (1 << 8) | (1 << 2);
        case 3: /* Reserved */
            return (1 << 8) | (4 << 2);
        case 1: /* L1 PDE */
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
                return (2 << 8) | (1 << 2);
            case 3: /* Reserved */
                return (2 << 8) | (4 << 2);
            case 1: /* L2 PDE */
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                    return (3 << 8) | (1 << 2);
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return (3 << 8) | (4 << 2);
                case 2: /* L3 PTE */
                    virt_addr = address & TARGET_PAGE_MASK;
                    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
                }
                break;
            case 2: /* L2 PTE */
                virt_addr = address & ~0x3ffff;
                page_offset = address & 0x3ffff;
            }
            break;
        case 2: /* L1 PTE */
            virt_addr = address & ~0xffffff;
            page_offset = address & 0xffffff;
        }
    }

    /* update page modified and dirty bits */
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
        pde |= PG_ACCESSED_MASK;
        if (is_dirty)
            pde |= PG_MODIFIED_MASK;
        stl_phys_notdirty(pde_ptr, pde);
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
    error_code = access_table[*access_index][access_perms];
    if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
        return error_code;

    /* the page can be put in the TLB */
    *prot = perm_table[is_user][access_perms];
    if (!(pde & PG_MODIFIED_MASK)) {
        /* only set write access if already dirty... otherwise wait
           for dirty access */
        *prot &= ~PAGE_WRITE;
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
    *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
    return error_code;
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int mmu_idx, int is_softmmu)
{
    target_phys_addr_t paddr;
    target_ulong vaddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
    if (error_code == 0) {
        vaddr = address & TARGET_PAGE_MASK;
        paddr &= TARGET_PAGE_MASK;
#ifdef DEBUG_MMU
        printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
               TARGET_FMT_lx "\n", address, paddr, vaddr);
#endif
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
        return ret;
    }

    if (env->mmuregs[3]) /* Fault status register */
        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
    env->mmuregs[4] = address; /* Fault address register */

    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
        vaddr = address & TARGET_PAGE_MASK;
        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
        return ret;
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
    }
}

target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
    pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
        (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
        return 0;
    case 1: /* L1 PDE */
        if (mmulev == 3)
            return pde;
        pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

        switch (pde & PTE_ENTRYTYPE_MASK) {
        default:
        case 0: /* Invalid */
        case 3: /* Reserved */
            return 0;
        case 2: /* L1 PTE */
            return pde;
        case 1: /* L2 PDE */
            if (mmulev == 2)
                return pde;
            pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

            switch (pde & PTE_ENTRYTYPE_MASK) {
            default:
            case 0: /* Invalid */
            case 3: /* Reserved */
                return 0;
            case 2: /* L2 PTE */
                return pde;
            case 1: /* L3 PDE */
                if (mmulev == 1)
                    return pde;
                pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

                switch (pde & PTE_ENTRYTYPE_MASK) {
                default:
                case 0: /* Invalid */
                case 1: /* PDE, should not happen */
                case 3: /* Reserved */
                    return 0;
                case 2: /* L3 PTE */
                    return pde;
                }
            }
        }
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    target_ulong va, va1, va2;
    unsigned int n, m, o;
    target_phys_addr_t pde_ptr, pa;
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);
    printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
           (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
        pde = mmu_probe(env, va, 2);
        if (pde) {
            pa = cpu_get_phys_page_debug(env, va);
            printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
                   " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
            for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
                pde = mmu_probe(env, va1, 1);
                if (pde) {
                    pa = cpu_get_phys_page_debug(env, va1);
                    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
                           " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
                    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
                        pde = mmu_probe(env, va2, 0);
                        if (pde) {
                            pa = cpu_get_phys_page_debug(env, va2);
                            printf("  VA: " TARGET_FMT_lx ", PA: "
                                   TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
                                   va2, pa, pde);
                        }
                    }
                }
            }
        }
    }
    printf("MMU dump ends\n");
}
#endif /* DEBUG_MMU */

#else /* !TARGET_SPARC64 */
/*
 * UltraSparc IIi I/DMMUs
 */
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
                          int *access_index, target_ulong address, int rw,
                          int is_user)
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
        return 0;
    }

    for (i = 0; i < 64; i++) {
        switch ((env->dtlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
            break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->dtlb_tte[i] & 0x4) && is_user) ||
                (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
                if (env->dmmuregs[3]) /* Fault status register */
                    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
                env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
                env->dmmuregs[4] = address; /* Fault address register */
                env->exception_index = TT_DFAULT;
#ifdef DEBUG_MMU
                printf("DFAULT at 0x%" PRIx64 "\n", address);
#endif
                return 1;
            }
            *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
            *prot = PAGE_READ;
            if (env->dtlb_tte[i] & 0x2)
                *prot |= PAGE_WRITE;
            return 0;
        }
    }
#ifdef DEBUG_MMU
    printf("DMISS at 0x%" PRIx64 "\n", address);
#endif
    env->exception_index = TT_DMISS;
    return 1;
}

static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
                          int *access_index, target_ulong address, int rw,
                          int is_user)
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
        *physical = address;
        *prot = PAGE_EXEC;
        return 0;
    }

    for (i = 0; i < 64; i++) {
        switch ((env->itlb_tte[i] >> 61) & 3) {
        default:
        case 0x0: // 8k
            mask = 0xffffffffffffe000ULL;
            break;
        case 0x1: // 64k
            mask = 0xffffffffffff0000ULL;
            break;
        case 0x2: // 512k
            mask = 0xfffffffffff80000ULL;
            break;
        case 0x3: // 4M
            mask = 0xffffffffffc00000ULL;
                break;
        }
        // ctx match, vaddr match?
        if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
            (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
            // valid, access ok?
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
                ((env->itlb_tte[i] & 0x4) && is_user)) {
                if (env->immuregs[3]) /* Fault status register */
                    env->immuregs[3] = 2; /* overflow (not read before another fault) */
                env->immuregs[3] |= (is_user << 3) | 1;
                env->exception_index = TT_TFAULT;
#ifdef DEBUG_MMU
                printf("TFAULT at 0x%" PRIx64 "\n", address);
#endif
                return 1;
            }
            *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
            *prot = PAGE_EXEC;
            return 0;
        }
    }
#ifdef DEBUG_MMU
    printf("TMISS at 0x%" PRIx64 "\n", address);
#endif
    env->exception_index = TT_TMISS;
    return 1;
}

int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
                          int *access_index, target_ulong address, int rw,
                          int mmu_idx)
{
    int is_user = mmu_idx == MMU_USER_IDX;

    if (rw == 2)
        return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
    else
        return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int mmu_idx, int is_softmmu)
{
    target_ulong virt_addr, vaddr;
    target_phys_addr_t paddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
    if (error_code == 0) {
        virt_addr = address & TARGET_PAGE_MASK;
        vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
#ifdef DEBUG_MMU
        printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
#endif
        ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
        return ret;
    }
    // XXX
    return 1;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    unsigned int i;
    const char *mask;

    printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
    if ((env->lsu & DMMU_E) == 0) {
        printf("DMMU disabled\n");
    } else {
        printf("DMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->dtlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
                       env->dtlb_tag[i] & ~0x1fffULL,
                       env->dtlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->dtlb_tte[i] & 0x4? "priv": "user",
                       env->dtlb_tte[i] & 0x2? "RW": "RO",
                       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
                       env->dtlb_tag[i] & 0x1fffULL);
            }
        }
    }
    if ((env->lsu & IMMU_E) == 0) {
        printf("IMMU disabled\n");
    } else {
        printf("IMMU dump:\n");
        for (i = 0; i < 64; i++) {
            switch ((env->itlb_tte[i] >> 61) & 3) {
            default:
            case 0x0:
                mask = "  8k";
                break;
            case 0x1:
                mask = " 64k";
                break;
            case 0x2:
                mask = "512k";
                break;
            case 0x3:
                mask = "  4M";
                break;
            }
            if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
                printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
                       env->itlb_tag[i] & ~0x1fffULL,
                       env->itlb_tte[i] & 0x1ffffffe000ULL,
                       mask,
                       env->itlb_tte[i] & 0x4? "priv": "user",
                       env->itlb_tte[i] & 0x40? "locked": "unlocked",
                       env->itlb_tag[i] & 0x1fffULL);
            }
        }
    }
}
#endif /* DEBUG_MMU */

#endif /* TARGET_SPARC64 */
#endif /* !CONFIG_USER_ONLY */

void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}

#ifdef TARGET_SPARC64
#if !defined(CONFIG_USER_ONLY)
#include "qemu-common.h"
#include "hw/irq.h"
#include "qemu-timer.h"
#endif

void do_tick_set_count(void *opaque, uint64_t count)
{
#if !defined(CONFIG_USER_ONLY)
    ptimer_set_count(opaque, -count);
#endif
}

uint64_t do_tick_get_count(void *opaque)
{
#if !defined(CONFIG_USER_ONLY)
    return -ptimer_get_count(opaque);
#else
    return 0;
#endif
}

void do_tick_set_limit(void *opaque, uint64_t limit)
{
#if !defined(CONFIG_USER_ONLY)
    ptimer_set_limit(opaque, -limit, 0);
#endif
}
#endif
Commit	Line	Data
e8af50a3 FB	1	/*
e8af50a3 FB	2	* sparc helpers
5fafdf24	3	*
83469015	4	* Copyright (c) 2003-2005 Fabrice Bellard
e8af50a3 FB	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
ee5bbe38 FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e8af50a3	30
e80cfcfc	31	//#define DEBUG_MMU
e8af50a3	32
e8af50a3	33	/* Sparc MMU emulation */
e8af50a3	34
e8af50a3 FB	35	/* thread support */
	36
	37	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
	38
	39	void cpu_lock(void)
	40	{
	41	spin_lock(&global_cpu_lock);
	42	}
	43
	44	void cpu_unlock(void)
	45	{
	46	spin_unlock(&global_cpu_lock);
	47	}
	48
5fafdf24	49	#if defined(CONFIG_USER_ONLY)
9d893301 FB	50
9d893301 FB	51	int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
6ebbf390	52	int mmu_idx, int is_softmmu)
9d893301	53	{
878d3096 FB	54	if (rw & 2)
	55	env->exception_index = TT_TFAULT;
	56	else
	57	env->exception_index = TT_DFAULT;
9d893301 FB	58	return 1;
	59	}
	60
	61	#else
e8af50a3	62
3475187d	63	#ifndef TARGET_SPARC64
83469015 FB	64	/*
	65	* Sparc V8 Reference MMU (SRMMU)
	66	*/
e8af50a3 FB	67	static const int access_table[8][8] = {
	68	{ 0, 0, 0, 0, 2, 0, 3, 3 },
	69	{ 0, 0, 0, 0, 2, 0, 0, 0 },
	70	{ 2, 2, 0, 0, 0, 2, 3, 3 },
	71	{ 2, 2, 0, 0, 0, 2, 0, 0 },
	72	{ 2, 0, 2, 0, 2, 2, 3, 3 },
	73	{ 2, 0, 2, 0, 2, 0, 2, 0 },
	74	{ 2, 2, 2, 0, 2, 2, 3, 3 },
	75	{ 2, 2, 2, 0, 2, 2, 2, 0 }
	76	};
	77
227671c9 FB	78	static const int perm_table[2][8] = {
	79	{
	80	PAGE_READ,
	81	PAGE_READ \| PAGE_WRITE,
	82	PAGE_READ \| PAGE_EXEC,
	83	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC,
	84	PAGE_EXEC,
	85	PAGE_READ \| PAGE_WRITE,
	86	PAGE_READ \| PAGE_EXEC,
	87	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC
	88	},
	89	{
	90	PAGE_READ,
	91	PAGE_READ \| PAGE_WRITE,
	92	PAGE_READ \| PAGE_EXEC,
	93	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC,
	94	PAGE_EXEC,
	95	PAGE_READ,
	96	0,
	97	0,
	98	}
e8af50a3 FB	99	};
e8af50a3 FB	100
af7bf89b	101	int get_physical_address (CPUState env, target_phys_addr_t physical, int *prot,
0f8a249a	102	int *access_index, target_ulong address, int rw,
6ebbf390	103	int mmu_idx)
e8af50a3	104	{
e80cfcfc FB	105	int access_perms = 0;
e80cfcfc FB	106	target_phys_addr_t pde_ptr;
af7bf89b FB	107	uint32_t pde;
af7bf89b FB	108	target_ulong virt_addr;
6ebbf390	109	int error_code = 0, is_dirty, is_user;
e80cfcfc	110	unsigned long page_offset;
e8af50a3	111
6ebbf390	112	is_user = mmu_idx == MMU_USER_IDX;
e8af50a3	113	virt_addr = address & TARGET_PAGE_MASK;
40ce0a9a	114
e8af50a3	115	if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
40ce0a9a	116	// Boot mode: instruction fetches are taken from PROM
6d5f237a	117	if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
58a770f3	118	*physical = env->prom_addr \| (address & 0x7ffffULL);
40ce0a9a BS	119	*prot = PAGE_READ \| PAGE_EXEC;
	120	return 0;
	121	}
0f8a249a	122	*physical = address;
227671c9	123	*prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
e80cfcfc	124	return 0;
e8af50a3 FB	125	}
e8af50a3 FB	126
7483750d	127	*access_index = ((rw & 1) << 2) \| (rw & 2) \| (is_user? 0 : 1);
5dcb6b91	128	*physical = 0xffffffffffff0000ULL;
7483750d	129
e8af50a3 FB	130	/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
e8af50a3 FB	131	/* Context base + context number */
3deaeab7	132	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
49be8030	133	pde = ldl_phys(pde_ptr);
e8af50a3 FB	134
	135	/* Ctx pde */
	136	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	137	default:
e8af50a3	138	case 0: /* Invalid */
0f8a249a	139	return 1 << 2;
e80cfcfc	140	case 2: /* L0 PTE, maybe should not happen? */
e8af50a3	141	case 3: /* Reserved */
7483750d	142	return 4 << 2;
e80cfcfc	143	case 1: /* L0 PDE */
0f8a249a	144	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
49be8030	145	pde = ldl_phys(pde_ptr);
e8af50a3	146
0f8a249a BS	147	switch (pde & PTE_ENTRYTYPE_MASK) {
	148	default:
	149	case 0: /* Invalid */
	150	return (1 << 8) \| (1 << 2);
	151	case 3: /* Reserved */
	152	return (1 << 8) \| (4 << 2);
	153	case 1: /* L1 PDE */
	154	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
49be8030	155	pde = ldl_phys(pde_ptr);
e8af50a3	156
0f8a249a BS	157	switch (pde & PTE_ENTRYTYPE_MASK) {
	158	default:
	159	case 0: /* Invalid */
	160	return (2 << 8) \| (1 << 2);
	161	case 3: /* Reserved */
	162	return (2 << 8) \| (4 << 2);
	163	case 1: /* L2 PDE */
	164	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
49be8030	165	pde = ldl_phys(pde_ptr);
e8af50a3	166
0f8a249a BS	167	switch (pde & PTE_ENTRYTYPE_MASK) {
	168	default:
	169	case 0: /* Invalid */
	170	return (3 << 8) \| (1 << 2);
	171	case 1: /* PDE, should not happen */
	172	case 3: /* Reserved */
	173	return (3 << 8) \| (4 << 2);
	174	case 2: /* L3 PTE */
	175	virt_addr = address & TARGET_PAGE_MASK;
	176	page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
	177	}
	178	break;
	179	case 2: /* L2 PTE */
	180	virt_addr = address & ~0x3ffff;
	181	page_offset = address & 0x3ffff;
	182	}
	183	break;
	184	case 2: /* L1 PTE */
	185	virt_addr = address & ~0xffffff;
	186	page_offset = address & 0xffffff;
	187	}
e8af50a3 FB	188	}
	189
	190	/* update page modified and dirty bits */
b769d8fe	191	is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
e8af50a3	192	if (!(pde & PG_ACCESSED_MASK) \|\| is_dirty) {
0f8a249a BS	193	pde \|= PG_ACCESSED_MASK;
	194	if (is_dirty)
	195	pde \|= PG_MODIFIED_MASK;
49be8030	196	stl_phys_notdirty(pde_ptr, pde);
e8af50a3	197	}
e8af50a3	198	/* check access */
e8af50a3	199	access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
e80cfcfc	200	error_code = access_table[*access_index][access_perms];
d8e3326c	201	if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
0f8a249a	202	return error_code;
e8af50a3 FB	203
e8af50a3 FB	204	/* the page can be put in the TLB */
227671c9 FB	205	*prot = perm_table[is_user][access_perms];
227671c9 FB	206	if (!(pde & PG_MODIFIED_MASK)) {
e8af50a3 FB	207	/* only set write access if already dirty... otherwise wait
e8af50a3 FB	208	for dirty access */
227671c9	209	*prot &= ~PAGE_WRITE;
e8af50a3 FB	210	}
	211
	212	/* Even if large ptes, we map only one 4KB page in the cache to
	213	avoid filling it too fast */
5dcb6b91	214	*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
6f7e9aec	215	return error_code;
e80cfcfc FB	216	}
	217
	218	/* Perform address translation */
af7bf89b	219	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	220	int mmu_idx, int is_softmmu)
e80cfcfc	221	{
af7bf89b	222	target_phys_addr_t paddr;
5dcb6b91	223	target_ulong vaddr;
e80cfcfc	224	int error_code = 0, prot, ret = 0, access_index;
e8af50a3	225
6ebbf390	226	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
e80cfcfc	227	if (error_code == 0) {
0f8a249a BS	228	vaddr = address & TARGET_PAGE_MASK;
0f8a249a BS	229	paddr &= TARGET_PAGE_MASK;
9e61bde5	230	#ifdef DEBUG_MMU
0f8a249a	231	printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
5dcb6b91	232	TARGET_FMT_lx "\n", address, paddr, vaddr);
9e61bde5	233	#endif
6ebbf390	234	ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
0f8a249a	235	return ret;
e80cfcfc	236	}
e8af50a3	237
e8af50a3	238	if (env->mmuregs[3]) /* Fault status register */
0f8a249a	239	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
7483750d	240	env->mmuregs[3] \|= (access_index << 5) \| error_code \| 2;
e8af50a3 FB	241	env->mmuregs[4] = address; /* Fault address register */
e8af50a3 FB	242
878d3096	243	if ((env->mmuregs[0] & MMU_NF) \|\| env->psret == 0) {
6f7e9aec FB	244	// No fault mode: if a mapping is available, just override
	245	// permissions. If no mapping is available, redirect accesses to
	246	// neverland. Fake/overridden mappings will be flushed when
	247	// switching to normal mode.
0f8a249a	248	vaddr = address & TARGET_PAGE_MASK;
227671c9	249	prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
6ebbf390	250	ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
0f8a249a	251	return ret;
7483750d FB	252	} else {
	253	if (rw & 2)
	254	env->exception_index = TT_TFAULT;
	255	else
	256	env->exception_index = TT_DFAULT;
	257	return 1;
878d3096	258	}
e8af50a3	259	}
24741ef3 FB	260
	261	target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
	262	{
	263	target_phys_addr_t pde_ptr;
	264	uint32_t pde;
	265
	266	/* Context base + context number */
5dcb6b91 BS	267	pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
5dcb6b91 BS	268	(env->mmuregs[2] << 2);
24741ef3 FB	269	pde = ldl_phys(pde_ptr);
	270
	271	switch (pde & PTE_ENTRYTYPE_MASK) {
	272	default:
	273	case 0: /* Invalid */
	274	case 2: /* PTE, maybe should not happen? */
	275	case 3: /* Reserved */
0f8a249a	276	return 0;
24741ef3	277	case 1: /* L1 PDE */
0f8a249a BS	278	if (mmulev == 3)
	279	return pde;
	280	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
24741ef3 FB	281	pde = ldl_phys(pde_ptr);
24741ef3 FB	282
0f8a249a BS	283	switch (pde & PTE_ENTRYTYPE_MASK) {
	284	default:
	285	case 0: /* Invalid */
	286	case 3: /* Reserved */
	287	return 0;
	288	case 2: /* L1 PTE */
	289	return pde;
	290	case 1: /* L2 PDE */
	291	if (mmulev == 2)
	292	return pde;
	293	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
24741ef3 FB	294	pde = ldl_phys(pde_ptr);
24741ef3 FB	295
0f8a249a BS	296	switch (pde & PTE_ENTRYTYPE_MASK) {
	297	default:
	298	case 0: /* Invalid */
	299	case 3: /* Reserved */
	300	return 0;
	301	case 2: /* L2 PTE */
	302	return pde;
	303	case 1: /* L3 PDE */
	304	if (mmulev == 1)
	305	return pde;
	306	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
24741ef3 FB	307	pde = ldl_phys(pde_ptr);
24741ef3 FB	308
0f8a249a BS	309	switch (pde & PTE_ENTRYTYPE_MASK) {
	310	default:
	311	case 0: /* Invalid */
	312	case 1: /* PDE, should not happen */
	313	case 3: /* Reserved */
	314	return 0;
	315	case 2: /* L3 PTE */
	316	return pde;
	317	}
	318	}
	319	}
24741ef3 FB	320	}
	321	return 0;
	322	}
	323
	324	#ifdef DEBUG_MMU
	325	void dump_mmu(CPUState *env)
	326	{
5dcb6b91 BS	327	target_ulong va, va1, va2;
	328	unsigned int n, m, o;
	329	target_phys_addr_t pde_ptr, pa;
24741ef3 FB	330	uint32_t pde;
	331
	332	printf("MMU dump:\n");
	333	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
	334	pde = ldl_phys(pde_ptr);
5dcb6b91 BS	335	printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
5dcb6b91 BS	336	(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
24741ef3	337	for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
0f8a249a BS	338	pde = mmu_probe(env, va, 2);
	339	if (pde) {
	340	pa = cpu_get_phys_page_debug(env, va);
	341	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
5dcb6b91	342	" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
0f8a249a BS	343	for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
	344	pde = mmu_probe(env, va1, 1);
	345	if (pde) {
	346	pa = cpu_get_phys_page_debug(env, va1);
	347	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
5dcb6b91	348	" PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
0f8a249a BS	349	for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
	350	pde = mmu_probe(env, va2, 0);
	351	if (pde) {
	352	pa = cpu_get_phys_page_debug(env, va2);
	353	printf(" VA: " TARGET_FMT_lx ", PA: "
5dcb6b91 BS	354	TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
5dcb6b91 BS	355	va2, pa, pde);
0f8a249a BS	356	}
	357	}
	358	}
	359	}
	360	}
24741ef3 FB	361	}
	362	printf("MMU dump ends\n");
	363	}
	364	#endif /* DEBUG_MMU */
	365
	366	#else /* !TARGET_SPARC64 */
83469015 FB	367	/*
	368	* UltraSparc IIi I/DMMUs
	369	*/
3475187d	370	static int get_physical_address_data(CPUState env, target_phys_addr_t physical, int *prot,
0f8a249a BS	371	int *access_index, target_ulong address, int rw,
0f8a249a BS	372	int is_user)
3475187d FB	373	{
	374	target_ulong mask;
	375	unsigned int i;
	376
	377	if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
0f8a249a BS	378	*physical = address;
0f8a249a BS	379	*prot = PAGE_READ \| PAGE_WRITE;
3475187d FB	380	return 0;
	381	}
	382
	383	for (i = 0; i < 64; i++) {
0f8a249a BS	384	switch ((env->dtlb_tte[i] >> 61) & 3) {
	385	default:
	386	case 0x0: // 8k
	387	mask = 0xffffffffffffe000ULL;
	388	break;
	389	case 0x1: // 64k
	390	mask = 0xffffffffffff0000ULL;
	391	break;
	392	case 0x2: // 512k
	393	mask = 0xfffffffffff80000ULL;
	394	break;
	395	case 0x3: // 4M
	396	mask = 0xffffffffffc00000ULL;
	397	break;
	398	}
	399	// ctx match, vaddr match?
	400	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
	401	(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
	402	// valid, access ok?
	403	if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 \|\|
	404	((env->dtlb_tte[i] & 0x4) && is_user) \|\|
	405	(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
	406	if (env->dmmuregs[3]) /* Fault status register */
	407	env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
	408	env->dmmuregs[3] \|= (is_user << 3) \| ((rw == 1) << 2) \| 1;
	409	env->dmmuregs[4] = address; /* Fault address register */
	410	env->exception_index = TT_DFAULT;
83469015	411	#ifdef DEBUG_MMU
0f8a249a	412	printf("DFAULT at 0x%" PRIx64 "\n", address);
83469015	413	#endif
0f8a249a BS	414	return 1;
	415	}
	416	*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	417	*prot = PAGE_READ;
	418	if (env->dtlb_tte[i] & 0x2)
	419	*prot \|= PAGE_WRITE;
	420	return 0;
	421	}
3475187d	422	}
83469015	423	#ifdef DEBUG_MMU
26a76461	424	printf("DMISS at 0x%" PRIx64 "\n", address);
83469015 FB	425	#endif
83469015 FB	426	env->exception_index = TT_DMISS;
3475187d FB	427	return 1;
	428	}
	429
	430	static int get_physical_address_code(CPUState env, target_phys_addr_t physical, int *prot,
0f8a249a BS	431	int *access_index, target_ulong address, int rw,
0f8a249a BS	432	int is_user)
3475187d FB	433	{
	434	target_ulong mask;
	435	unsigned int i;
	436
	437	if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
0f8a249a BS	438	*physical = address;
0f8a249a BS	439	*prot = PAGE_EXEC;
3475187d FB	440	return 0;
3475187d FB	441	}
83469015	442
3475187d	443	for (i = 0; i < 64; i++) {
0f8a249a BS	444	switch ((env->itlb_tte[i] >> 61) & 3) {
	445	default:
	446	case 0x0: // 8k
	447	mask = 0xffffffffffffe000ULL;
	448	break;
	449	case 0x1: // 64k
	450	mask = 0xffffffffffff0000ULL;
	451	break;
	452	case 0x2: // 512k
	453	mask = 0xfffffffffff80000ULL;
	454	break;
	455	case 0x3: // 4M
	456	mask = 0xffffffffffc00000ULL;
	457	break;
	458	}
	459	// ctx match, vaddr match?
	460	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
	461	(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
	462	// valid, access ok?
	463	if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 \|\|
	464	((env->itlb_tte[i] & 0x4) && is_user)) {
	465	if (env->immuregs[3]) /* Fault status register */
	466	env->immuregs[3] = 2; /* overflow (not read before another fault) */
	467	env->immuregs[3] \|= (is_user << 3) \| 1;
	468	env->exception_index = TT_TFAULT;
83469015	469	#ifdef DEBUG_MMU
0f8a249a	470	printf("TFAULT at 0x%" PRIx64 "\n", address);
83469015	471	#endif
0f8a249a BS	472	return 1;
	473	}
	474	*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	475	*prot = PAGE_EXEC;
	476	return 0;
	477	}
3475187d	478	}
83469015	479	#ifdef DEBUG_MMU
26a76461	480	printf("TMISS at 0x%" PRIx64 "\n", address);
83469015 FB	481	#endif
83469015 FB	482	env->exception_index = TT_TMISS;
3475187d FB	483	return 1;
	484	}
	485
	486	int get_physical_address(CPUState env, target_phys_addr_t physical, int *prot,
0f8a249a	487	int *access_index, target_ulong address, int rw,
6ebbf390	488	int mmu_idx)
3475187d	489	{
6ebbf390 JM	490	int is_user = mmu_idx == MMU_USER_IDX;
6ebbf390 JM	491
3475187d	492	if (rw == 2)
0f8a249a	493	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
3475187d	494	else
0f8a249a	495	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
3475187d FB	496	}
	497
	498	/* Perform address translation */
	499	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	500	int mmu_idx, int is_softmmu)
3475187d	501	{
83469015	502	target_ulong virt_addr, vaddr;
3475187d	503	target_phys_addr_t paddr;
3475187d FB	504	int error_code = 0, prot, ret = 0, access_index;
3475187d FB	505
6ebbf390	506	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
3475187d	507	if (error_code == 0) {
0f8a249a BS	508	virt_addr = address & TARGET_PAGE_MASK;
0f8a249a BS	509	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
83469015	510	#ifdef DEBUG_MMU
0f8a249a	511	printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
83469015	512	#endif
6ebbf390	513	ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
0f8a249a	514	return ret;
3475187d FB	515	}
	516	// XXX
	517	return 1;
	518	}
	519
83469015 FB	520	#ifdef DEBUG_MMU
	521	void dump_mmu(CPUState *env)
	522	{
	523	unsigned int i;
	524	const char *mask;
	525
26a76461	526	printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
83469015	527	if ((env->lsu & DMMU_E) == 0) {
0f8a249a	528	printf("DMMU disabled\n");
83469015	529	} else {
0f8a249a BS	530	printf("DMMU dump:\n");
	531	for (i = 0; i < 64; i++) {
	532	switch ((env->dtlb_tte[i] >> 61) & 3) {
	533	default:
	534	case 0x0:
	535	mask = " 8k";
	536	break;
	537	case 0x1:
	538	mask = " 64k";
	539	break;
	540	case 0x2:
	541	mask = "512k";
	542	break;
	543	case 0x3:
	544	mask = " 4M";
	545	break;
	546	}
	547	if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
	548	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
	549	env->dtlb_tag[i] & ~0x1fffULL,
	550	env->dtlb_tte[i] & 0x1ffffffe000ULL,
	551	mask,
	552	env->dtlb_tte[i] & 0x4? "priv": "user",
	553	env->dtlb_tte[i] & 0x2? "RW": "RO",
	554	env->dtlb_tte[i] & 0x40? "locked": "unlocked",
	555	env->dtlb_tag[i] & 0x1fffULL);
	556	}
	557	}
83469015 FB	558	}
83469015 FB	559	if ((env->lsu & IMMU_E) == 0) {
0f8a249a	560	printf("IMMU disabled\n");
83469015	561	} else {
0f8a249a BS	562	printf("IMMU dump:\n");
	563	for (i = 0; i < 64; i++) {
	564	switch ((env->itlb_tte[i] >> 61) & 3) {
	565	default:
	566	case 0x0:
	567	mask = " 8k";
	568	break;
	569	case 0x1:
	570	mask = " 64k";
	571	break;
	572	case 0x2:
	573	mask = "512k";
	574	break;
	575	case 0x3:
	576	mask = " 4M";
	577	break;
	578	}
	579	if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
	580	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
	581	env->itlb_tag[i] & ~0x1fffULL,
	582	env->itlb_tte[i] & 0x1ffffffe000ULL,
	583	mask,
	584	env->itlb_tte[i] & 0x4? "priv": "user",
	585	env->itlb_tte[i] & 0x40? "locked": "unlocked",
	586	env->itlb_tag[i] & 0x1fffULL);
	587	}
	588	}
83469015 FB	589	}
83469015 FB	590	}
24741ef3 FB	591	#endif /* DEBUG_MMU */
	592
	593	#endif /* TARGET_SPARC64 */
	594	#endif /* !CONFIG_USER_ONLY */
	595
	596	void memcpy32(target_ulong dst, const target_ulong src)
	597	{
	598	dst[0] = src[0];
	599	dst[1] = src[1];
	600	dst[2] = src[2];
	601	dst[3] = src[3];
	602	dst[4] = src[4];
	603	dst[5] = src[5];
	604	dst[6] = src[6];
	605	dst[7] = src[7];
	606	}
87ecb68b PB	607
	608	#ifdef TARGET_SPARC64
	609	#if !defined(CONFIG_USER_ONLY)
	610	#include "qemu-common.h"
	611	#include "hw/irq.h"
	612	#include "qemu-timer.h"
	613	#endif
	614
	615	void do_tick_set_count(void *opaque, uint64_t count)
	616	{
	617	#if !defined(CONFIG_USER_ONLY)
	618	ptimer_set_count(opaque, -count);
	619	#endif
	620	}
	621
	622	uint64_t do_tick_get_count(void *opaque)
	623	{
	624	#if !defined(CONFIG_USER_ONLY)
	625	return -ptimer_get_count(opaque);
	626	#else
	627	return 0;
	628	#endif
	629	}
	630
	631	void do_tick_set_limit(void *opaque, uint64_t limit)
	632	{
	633	#if !defined(CONFIG_USER_ONLY)
	634	ptimer_set_limit(opaque, -limit, 0);
	635	#endif
	636	}
	637	#endif