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Commit | Line | Data |
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e8af50a3 FB |
1 | /* |
2 | * sparc helpers | |
5fafdf24 | 3 | * |
83469015 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
e8af50a3 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
e8af50a3 | 19 | */ |
ee5bbe38 FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
ca10f867 | 30 | #include "qemu-common.h" |
e8af50a3 | 31 | |
e80cfcfc | 32 | //#define DEBUG_MMU |
64a88d5d | 33 | //#define DEBUG_FEATURES |
e8af50a3 | 34 | |
22548760 | 35 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
c48fcb47 | 36 | |
e8af50a3 | 37 | /* Sparc MMU emulation */ |
e8af50a3 | 38 | |
e8af50a3 FB |
39 | /* thread support */ |
40 | ||
797d5db0 | 41 | static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
e8af50a3 FB |
42 | |
43 | void cpu_lock(void) | |
44 | { | |
45 | spin_lock(&global_cpu_lock); | |
46 | } | |
47 | ||
48 | void cpu_unlock(void) | |
49 | { | |
50 | spin_unlock(&global_cpu_lock); | |
51 | } | |
52 | ||
5fafdf24 | 53 | #if defined(CONFIG_USER_ONLY) |
9d893301 | 54 | |
22548760 | 55 | int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
6ebbf390 | 56 | int mmu_idx, int is_softmmu) |
9d893301 | 57 | { |
878d3096 | 58 | if (rw & 2) |
22548760 | 59 | env1->exception_index = TT_TFAULT; |
878d3096 | 60 | else |
22548760 | 61 | env1->exception_index = TT_DFAULT; |
9d893301 FB |
62 | return 1; |
63 | } | |
64 | ||
65 | #else | |
e8af50a3 | 66 | |
3475187d | 67 | #ifndef TARGET_SPARC64 |
83469015 FB |
68 | /* |
69 | * Sparc V8 Reference MMU (SRMMU) | |
70 | */ | |
e8af50a3 | 71 | static const int access_table[8][8] = { |
a764a566 BS |
72 | { 0, 0, 0, 0, 8, 0, 12, 12 }, |
73 | { 0, 0, 0, 0, 8, 0, 0, 0 }, | |
74 | { 8, 8, 0, 0, 0, 8, 12, 12 }, | |
75 | { 8, 8, 0, 0, 0, 8, 0, 0 }, | |
76 | { 8, 0, 8, 0, 8, 8, 12, 12 }, | |
77 | { 8, 0, 8, 0, 8, 0, 8, 0 }, | |
78 | { 8, 8, 8, 0, 8, 8, 12, 12 }, | |
79 | { 8, 8, 8, 0, 8, 8, 8, 0 } | |
e8af50a3 FB |
80 | }; |
81 | ||
227671c9 FB |
82 | static const int perm_table[2][8] = { |
83 | { | |
84 | PAGE_READ, | |
85 | PAGE_READ | PAGE_WRITE, | |
86 | PAGE_READ | PAGE_EXEC, | |
87 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, | |
88 | PAGE_EXEC, | |
89 | PAGE_READ | PAGE_WRITE, | |
90 | PAGE_READ | PAGE_EXEC, | |
91 | PAGE_READ | PAGE_WRITE | PAGE_EXEC | |
92 | }, | |
93 | { | |
94 | PAGE_READ, | |
95 | PAGE_READ | PAGE_WRITE, | |
96 | PAGE_READ | PAGE_EXEC, | |
97 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, | |
98 | PAGE_EXEC, | |
99 | PAGE_READ, | |
100 | 0, | |
101 | 0, | |
102 | } | |
e8af50a3 FB |
103 | }; |
104 | ||
c48fcb47 BS |
105 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
106 | int *prot, int *access_index, | |
107 | target_ulong address, int rw, int mmu_idx) | |
e8af50a3 | 108 | { |
e80cfcfc FB |
109 | int access_perms = 0; |
110 | target_phys_addr_t pde_ptr; | |
af7bf89b FB |
111 | uint32_t pde; |
112 | target_ulong virt_addr; | |
6ebbf390 | 113 | int error_code = 0, is_dirty, is_user; |
e80cfcfc | 114 | unsigned long page_offset; |
e8af50a3 | 115 | |
6ebbf390 | 116 | is_user = mmu_idx == MMU_USER_IDX; |
e8af50a3 | 117 | virt_addr = address & TARGET_PAGE_MASK; |
40ce0a9a | 118 | |
e8af50a3 | 119 | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
40ce0a9a | 120 | // Boot mode: instruction fetches are taken from PROM |
5578ceab | 121 | if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { |
58a770f3 | 122 | *physical = env->prom_addr | (address & 0x7ffffULL); |
40ce0a9a BS |
123 | *prot = PAGE_READ | PAGE_EXEC; |
124 | return 0; | |
125 | } | |
0f8a249a | 126 | *physical = address; |
227671c9 | 127 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
e80cfcfc | 128 | return 0; |
e8af50a3 FB |
129 | } |
130 | ||
7483750d | 131 | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
5dcb6b91 | 132 | *physical = 0xffffffffffff0000ULL; |
7483750d | 133 | |
e8af50a3 FB |
134 | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ |
135 | /* Context base + context number */ | |
3deaeab7 | 136 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
49be8030 | 137 | pde = ldl_phys(pde_ptr); |
e8af50a3 FB |
138 | |
139 | /* Ctx pde */ | |
140 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
e80cfcfc | 141 | default: |
e8af50a3 | 142 | case 0: /* Invalid */ |
0f8a249a | 143 | return 1 << 2; |
e80cfcfc | 144 | case 2: /* L0 PTE, maybe should not happen? */ |
e8af50a3 | 145 | case 3: /* Reserved */ |
7483750d | 146 | return 4 << 2; |
e80cfcfc | 147 | case 1: /* L0 PDE */ |
0f8a249a | 148 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
49be8030 | 149 | pde = ldl_phys(pde_ptr); |
e8af50a3 | 150 | |
0f8a249a BS |
151 | switch (pde & PTE_ENTRYTYPE_MASK) { |
152 | default: | |
153 | case 0: /* Invalid */ | |
154 | return (1 << 8) | (1 << 2); | |
155 | case 3: /* Reserved */ | |
156 | return (1 << 8) | (4 << 2); | |
157 | case 1: /* L1 PDE */ | |
158 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); | |
49be8030 | 159 | pde = ldl_phys(pde_ptr); |
e8af50a3 | 160 | |
0f8a249a BS |
161 | switch (pde & PTE_ENTRYTYPE_MASK) { |
162 | default: | |
163 | case 0: /* Invalid */ | |
164 | return (2 << 8) | (1 << 2); | |
165 | case 3: /* Reserved */ | |
166 | return (2 << 8) | (4 << 2); | |
167 | case 1: /* L2 PDE */ | |
168 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); | |
49be8030 | 169 | pde = ldl_phys(pde_ptr); |
e8af50a3 | 170 | |
0f8a249a BS |
171 | switch (pde & PTE_ENTRYTYPE_MASK) { |
172 | default: | |
173 | case 0: /* Invalid */ | |
174 | return (3 << 8) | (1 << 2); | |
175 | case 1: /* PDE, should not happen */ | |
176 | case 3: /* Reserved */ | |
177 | return (3 << 8) | (4 << 2); | |
178 | case 2: /* L3 PTE */ | |
179 | virt_addr = address & TARGET_PAGE_MASK; | |
77f193da BS |
180 | page_offset = (address & TARGET_PAGE_MASK) & |
181 | (TARGET_PAGE_SIZE - 1); | |
0f8a249a BS |
182 | } |
183 | break; | |
184 | case 2: /* L2 PTE */ | |
185 | virt_addr = address & ~0x3ffff; | |
186 | page_offset = address & 0x3ffff; | |
187 | } | |
188 | break; | |
189 | case 2: /* L1 PTE */ | |
190 | virt_addr = address & ~0xffffff; | |
191 | page_offset = address & 0xffffff; | |
192 | } | |
e8af50a3 FB |
193 | } |
194 | ||
195 | /* update page modified and dirty bits */ | |
b769d8fe | 196 | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK); |
e8af50a3 | 197 | if (!(pde & PG_ACCESSED_MASK) || is_dirty) { |
0f8a249a BS |
198 | pde |= PG_ACCESSED_MASK; |
199 | if (is_dirty) | |
200 | pde |= PG_MODIFIED_MASK; | |
49be8030 | 201 | stl_phys_notdirty(pde_ptr, pde); |
e8af50a3 | 202 | } |
e8af50a3 | 203 | /* check access */ |
e8af50a3 | 204 | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
e80cfcfc | 205 | error_code = access_table[*access_index][access_perms]; |
d8e3326c | 206 | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
0f8a249a | 207 | return error_code; |
e8af50a3 FB |
208 | |
209 | /* the page can be put in the TLB */ | |
227671c9 FB |
210 | *prot = perm_table[is_user][access_perms]; |
211 | if (!(pde & PG_MODIFIED_MASK)) { | |
e8af50a3 FB |
212 | /* only set write access if already dirty... otherwise wait |
213 | for dirty access */ | |
227671c9 | 214 | *prot &= ~PAGE_WRITE; |
e8af50a3 FB |
215 | } |
216 | ||
217 | /* Even if large ptes, we map only one 4KB page in the cache to | |
218 | avoid filling it too fast */ | |
5dcb6b91 | 219 | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset; |
6f7e9aec | 220 | return error_code; |
e80cfcfc FB |
221 | } |
222 | ||
223 | /* Perform address translation */ | |
af7bf89b | 224 | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 225 | int mmu_idx, int is_softmmu) |
e80cfcfc | 226 | { |
af7bf89b | 227 | target_phys_addr_t paddr; |
5dcb6b91 | 228 | target_ulong vaddr; |
e80cfcfc | 229 | int error_code = 0, prot, ret = 0, access_index; |
e8af50a3 | 230 | |
77f193da BS |
231 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
232 | address, rw, mmu_idx); | |
e80cfcfc | 233 | if (error_code == 0) { |
0f8a249a BS |
234 | vaddr = address & TARGET_PAGE_MASK; |
235 | paddr &= TARGET_PAGE_MASK; | |
9e61bde5 | 236 | #ifdef DEBUG_MMU |
0f8a249a | 237 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
5dcb6b91 | 238 | TARGET_FMT_lx "\n", address, paddr, vaddr); |
9e61bde5 | 239 | #endif |
6ebbf390 | 240 | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
0f8a249a | 241 | return ret; |
e80cfcfc | 242 | } |
e8af50a3 | 243 | |
e8af50a3 | 244 | if (env->mmuregs[3]) /* Fault status register */ |
0f8a249a | 245 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
7483750d | 246 | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
e8af50a3 FB |
247 | env->mmuregs[4] = address; /* Fault address register */ |
248 | ||
878d3096 | 249 | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
6f7e9aec FB |
250 | // No fault mode: if a mapping is available, just override |
251 | // permissions. If no mapping is available, redirect accesses to | |
252 | // neverland. Fake/overridden mappings will be flushed when | |
253 | // switching to normal mode. | |
0f8a249a | 254 | vaddr = address & TARGET_PAGE_MASK; |
227671c9 | 255 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
6ebbf390 | 256 | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
0f8a249a | 257 | return ret; |
7483750d FB |
258 | } else { |
259 | if (rw & 2) | |
260 | env->exception_index = TT_TFAULT; | |
261 | else | |
262 | env->exception_index = TT_DFAULT; | |
263 | return 1; | |
878d3096 | 264 | } |
e8af50a3 | 265 | } |
24741ef3 FB |
266 | |
267 | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev) | |
268 | { | |
269 | target_phys_addr_t pde_ptr; | |
270 | uint32_t pde; | |
271 | ||
272 | /* Context base + context number */ | |
5dcb6b91 BS |
273 | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
274 | (env->mmuregs[2] << 2); | |
24741ef3 FB |
275 | pde = ldl_phys(pde_ptr); |
276 | ||
277 | switch (pde & PTE_ENTRYTYPE_MASK) { | |
278 | default: | |
279 | case 0: /* Invalid */ | |
280 | case 2: /* PTE, maybe should not happen? */ | |
281 | case 3: /* Reserved */ | |
0f8a249a | 282 | return 0; |
24741ef3 | 283 | case 1: /* L1 PDE */ |
0f8a249a BS |
284 | if (mmulev == 3) |
285 | return pde; | |
286 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); | |
24741ef3 FB |
287 | pde = ldl_phys(pde_ptr); |
288 | ||
0f8a249a BS |
289 | switch (pde & PTE_ENTRYTYPE_MASK) { |
290 | default: | |
291 | case 0: /* Invalid */ | |
292 | case 3: /* Reserved */ | |
293 | return 0; | |
294 | case 2: /* L1 PTE */ | |
295 | return pde; | |
296 | case 1: /* L2 PDE */ | |
297 | if (mmulev == 2) | |
298 | return pde; | |
299 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); | |
24741ef3 FB |
300 | pde = ldl_phys(pde_ptr); |
301 | ||
0f8a249a BS |
302 | switch (pde & PTE_ENTRYTYPE_MASK) { |
303 | default: | |
304 | case 0: /* Invalid */ | |
305 | case 3: /* Reserved */ | |
306 | return 0; | |
307 | case 2: /* L2 PTE */ | |
308 | return pde; | |
309 | case 1: /* L3 PDE */ | |
310 | if (mmulev == 1) | |
311 | return pde; | |
312 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); | |
24741ef3 FB |
313 | pde = ldl_phys(pde_ptr); |
314 | ||
0f8a249a BS |
315 | switch (pde & PTE_ENTRYTYPE_MASK) { |
316 | default: | |
317 | case 0: /* Invalid */ | |
318 | case 1: /* PDE, should not happen */ | |
319 | case 3: /* Reserved */ | |
320 | return 0; | |
321 | case 2: /* L3 PTE */ | |
322 | return pde; | |
323 | } | |
324 | } | |
325 | } | |
24741ef3 FB |
326 | } |
327 | return 0; | |
328 | } | |
329 | ||
330 | #ifdef DEBUG_MMU | |
331 | void dump_mmu(CPUState *env) | |
332 | { | |
5dcb6b91 BS |
333 | target_ulong va, va1, va2; |
334 | unsigned int n, m, o; | |
335 | target_phys_addr_t pde_ptr, pa; | |
24741ef3 FB |
336 | uint32_t pde; |
337 | ||
338 | printf("MMU dump:\n"); | |
339 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); | |
340 | pde = ldl_phys(pde_ptr); | |
5dcb6b91 BS |
341 | printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
342 | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); | |
24741ef3 | 343 | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
0f8a249a BS |
344 | pde = mmu_probe(env, va, 2); |
345 | if (pde) { | |
346 | pa = cpu_get_phys_page_debug(env, va); | |
347 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx | |
5dcb6b91 | 348 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
0f8a249a BS |
349 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
350 | pde = mmu_probe(env, va1, 1); | |
351 | if (pde) { | |
352 | pa = cpu_get_phys_page_debug(env, va1); | |
353 | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx | |
5dcb6b91 | 354 | " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
0f8a249a BS |
355 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
356 | pde = mmu_probe(env, va2, 0); | |
357 | if (pde) { | |
358 | pa = cpu_get_phys_page_debug(env, va2); | |
359 | printf(" VA: " TARGET_FMT_lx ", PA: " | |
5dcb6b91 BS |
360 | TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
361 | va2, pa, pde); | |
0f8a249a BS |
362 | } |
363 | } | |
364 | } | |
365 | } | |
366 | } | |
24741ef3 FB |
367 | } |
368 | printf("MMU dump ends\n"); | |
369 | } | |
370 | #endif /* DEBUG_MMU */ | |
371 | ||
372 | #else /* !TARGET_SPARC64 */ | |
83469015 FB |
373 | /* |
374 | * UltraSparc IIi I/DMMUs | |
375 | */ | |
77f193da BS |
376 | static int get_physical_address_data(CPUState *env, |
377 | target_phys_addr_t *physical, int *prot, | |
22548760 | 378 | target_ulong address, int rw, int is_user) |
3475187d FB |
379 | { |
380 | target_ulong mask; | |
381 | unsigned int i; | |
382 | ||
383 | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ | |
0f8a249a BS |
384 | *physical = address; |
385 | *prot = PAGE_READ | PAGE_WRITE; | |
3475187d FB |
386 | return 0; |
387 | } | |
388 | ||
389 | for (i = 0; i < 64; i++) { | |
0f8a249a BS |
390 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
391 | default: | |
392 | case 0x0: // 8k | |
393 | mask = 0xffffffffffffe000ULL; | |
394 | break; | |
395 | case 0x1: // 64k | |
396 | mask = 0xffffffffffff0000ULL; | |
397 | break; | |
398 | case 0x2: // 512k | |
399 | mask = 0xfffffffffff80000ULL; | |
400 | break; | |
401 | case 0x3: // 4M | |
402 | mask = 0xffffffffffc00000ULL; | |
403 | break; | |
404 | } | |
afdf8109 | 405 | // ctx match, vaddr match, valid? |
0f8a249a | 406 | if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
afdf8109 BS |
407 | (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL) && |
408 | (env->dtlb_tte[i] & 0x8000000000000000ULL)) { | |
409 | // access ok? | |
410 | if (((env->dtlb_tte[i] & 0x4) && is_user) || | |
0f8a249a BS |
411 | (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
412 | if (env->dmmuregs[3]) /* Fault status register */ | |
77f193da BS |
413 | env->dmmuregs[3] = 2; /* overflow (not read before |
414 | another fault) */ | |
0f8a249a BS |
415 | env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
416 | env->dmmuregs[4] = address; /* Fault address register */ | |
417 | env->exception_index = TT_DFAULT; | |
83469015 | 418 | #ifdef DEBUG_MMU |
0f8a249a | 419 | printf("DFAULT at 0x%" PRIx64 "\n", address); |
83469015 | 420 | #endif |
0f8a249a BS |
421 | return 1; |
422 | } | |
77f193da BS |
423 | *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + |
424 | (address & ~mask & 0x1fffffff000ULL); | |
0f8a249a BS |
425 | *prot = PAGE_READ; |
426 | if (env->dtlb_tte[i] & 0x2) | |
427 | *prot |= PAGE_WRITE; | |
428 | return 0; | |
429 | } | |
3475187d | 430 | } |
83469015 | 431 | #ifdef DEBUG_MMU |
26a76461 | 432 | printf("DMISS at 0x%" PRIx64 "\n", address); |
83469015 | 433 | #endif |
f617a9a6 | 434 | env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
83469015 | 435 | env->exception_index = TT_DMISS; |
3475187d FB |
436 | return 1; |
437 | } | |
438 | ||
77f193da BS |
439 | static int get_physical_address_code(CPUState *env, |
440 | target_phys_addr_t *physical, int *prot, | |
22548760 | 441 | target_ulong address, int is_user) |
3475187d FB |
442 | { |
443 | target_ulong mask; | |
444 | unsigned int i; | |
445 | ||
446 | if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ | |
0f8a249a BS |
447 | *physical = address; |
448 | *prot = PAGE_EXEC; | |
3475187d FB |
449 | return 0; |
450 | } | |
83469015 | 451 | |
3475187d | 452 | for (i = 0; i < 64; i++) { |
0f8a249a BS |
453 | switch ((env->itlb_tte[i] >> 61) & 3) { |
454 | default: | |
455 | case 0x0: // 8k | |
456 | mask = 0xffffffffffffe000ULL; | |
457 | break; | |
458 | case 0x1: // 64k | |
459 | mask = 0xffffffffffff0000ULL; | |
460 | break; | |
461 | case 0x2: // 512k | |
462 | mask = 0xfffffffffff80000ULL; | |
463 | break; | |
464 | case 0x3: // 4M | |
465 | mask = 0xffffffffffc00000ULL; | |
466 | break; | |
467 | } | |
afdf8109 | 468 | // ctx match, vaddr match, valid? |
0f8a249a | 469 | if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
afdf8109 BS |
470 | (address & mask) == (env->itlb_tag[i] & ~0x1fffULL) && |
471 | (env->itlb_tte[i] & 0x8000000000000000ULL)) { | |
472 | // access ok? | |
473 | if ((env->itlb_tte[i] & 0x4) && is_user) { | |
0f8a249a | 474 | if (env->immuregs[3]) /* Fault status register */ |
77f193da BS |
475 | env->immuregs[3] = 2; /* overflow (not read before |
476 | another fault) */ | |
0f8a249a BS |
477 | env->immuregs[3] |= (is_user << 3) | 1; |
478 | env->exception_index = TT_TFAULT; | |
83469015 | 479 | #ifdef DEBUG_MMU |
0f8a249a | 480 | printf("TFAULT at 0x%" PRIx64 "\n", address); |
83469015 | 481 | #endif |
0f8a249a BS |
482 | return 1; |
483 | } | |
77f193da BS |
484 | *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + |
485 | (address & ~mask & 0x1fffffff000ULL); | |
0f8a249a BS |
486 | *prot = PAGE_EXEC; |
487 | return 0; | |
488 | } | |
3475187d | 489 | } |
83469015 | 490 | #ifdef DEBUG_MMU |
26a76461 | 491 | printf("TMISS at 0x%" PRIx64 "\n", address); |
83469015 | 492 | #endif |
f617a9a6 | 493 | env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
83469015 | 494 | env->exception_index = TT_TMISS; |
3475187d FB |
495 | return 1; |
496 | } | |
497 | ||
c48fcb47 BS |
498 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
499 | int *prot, int *access_index, | |
500 | target_ulong address, int rw, int mmu_idx) | |
3475187d | 501 | { |
6ebbf390 JM |
502 | int is_user = mmu_idx == MMU_USER_IDX; |
503 | ||
3475187d | 504 | if (rw == 2) |
22548760 BS |
505 | return get_physical_address_code(env, physical, prot, address, |
506 | is_user); | |
3475187d | 507 | else |
22548760 BS |
508 | return get_physical_address_data(env, physical, prot, address, rw, |
509 | is_user); | |
3475187d FB |
510 | } |
511 | ||
512 | /* Perform address translation */ | |
513 | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
6ebbf390 | 514 | int mmu_idx, int is_softmmu) |
3475187d | 515 | { |
83469015 | 516 | target_ulong virt_addr, vaddr; |
3475187d | 517 | target_phys_addr_t paddr; |
3475187d FB |
518 | int error_code = 0, prot, ret = 0, access_index; |
519 | ||
77f193da BS |
520 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
521 | address, rw, mmu_idx); | |
3475187d | 522 | if (error_code == 0) { |
0f8a249a | 523 | virt_addr = address & TARGET_PAGE_MASK; |
77f193da BS |
524 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
525 | (TARGET_PAGE_SIZE - 1)); | |
83469015 | 526 | #ifdef DEBUG_MMU |
77f193da BS |
527 | printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 |
528 | "\n", address, paddr, vaddr); | |
83469015 | 529 | #endif |
6ebbf390 | 530 | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
0f8a249a | 531 | return ret; |
3475187d FB |
532 | } |
533 | // XXX | |
534 | return 1; | |
535 | } | |
536 | ||
83469015 FB |
537 | #ifdef DEBUG_MMU |
538 | void dump_mmu(CPUState *env) | |
539 | { | |
540 | unsigned int i; | |
541 | const char *mask; | |
542 | ||
77f193da BS |
543 | printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", |
544 | env->dmmuregs[1], env->dmmuregs[2]); | |
83469015 | 545 | if ((env->lsu & DMMU_E) == 0) { |
0f8a249a | 546 | printf("DMMU disabled\n"); |
83469015 | 547 | } else { |
0f8a249a BS |
548 | printf("DMMU dump:\n"); |
549 | for (i = 0; i < 64; i++) { | |
550 | switch ((env->dtlb_tte[i] >> 61) & 3) { | |
551 | default: | |
552 | case 0x0: | |
553 | mask = " 8k"; | |
554 | break; | |
555 | case 0x1: | |
556 | mask = " 64k"; | |
557 | break; | |
558 | case 0x2: | |
559 | mask = "512k"; | |
560 | break; | |
561 | case 0x3: | |
562 | mask = " 4M"; | |
563 | break; | |
564 | } | |
565 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { | |
77f193da BS |
566 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
567 | ", %s, %s, %s, %s, ctx %" PRId64 "\n", | |
0f8a249a BS |
568 | env->dtlb_tag[i] & ~0x1fffULL, |
569 | env->dtlb_tte[i] & 0x1ffffffe000ULL, | |
570 | mask, | |
571 | env->dtlb_tte[i] & 0x4? "priv": "user", | |
572 | env->dtlb_tte[i] & 0x2? "RW": "RO", | |
573 | env->dtlb_tte[i] & 0x40? "locked": "unlocked", | |
574 | env->dtlb_tag[i] & 0x1fffULL); | |
575 | } | |
576 | } | |
83469015 FB |
577 | } |
578 | if ((env->lsu & IMMU_E) == 0) { | |
0f8a249a | 579 | printf("IMMU disabled\n"); |
83469015 | 580 | } else { |
0f8a249a BS |
581 | printf("IMMU dump:\n"); |
582 | for (i = 0; i < 64; i++) { | |
583 | switch ((env->itlb_tte[i] >> 61) & 3) { | |
584 | default: | |
585 | case 0x0: | |
586 | mask = " 8k"; | |
587 | break; | |
588 | case 0x1: | |
589 | mask = " 64k"; | |
590 | break; | |
591 | case 0x2: | |
592 | mask = "512k"; | |
593 | break; | |
594 | case 0x3: | |
595 | mask = " 4M"; | |
596 | break; | |
597 | } | |
598 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { | |
77f193da BS |
599 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
600 | ", %s, %s, %s, ctx %" PRId64 "\n", | |
0f8a249a BS |
601 | env->itlb_tag[i] & ~0x1fffULL, |
602 | env->itlb_tte[i] & 0x1ffffffe000ULL, | |
603 | mask, | |
604 | env->itlb_tte[i] & 0x4? "priv": "user", | |
605 | env->itlb_tte[i] & 0x40? "locked": "unlocked", | |
606 | env->itlb_tag[i] & 0x1fffULL); | |
607 | } | |
608 | } | |
83469015 FB |
609 | } |
610 | } | |
24741ef3 FB |
611 | #endif /* DEBUG_MMU */ |
612 | ||
613 | #endif /* TARGET_SPARC64 */ | |
614 | #endif /* !CONFIG_USER_ONLY */ | |
615 | ||
c48fcb47 BS |
616 | |
617 | #if defined(CONFIG_USER_ONLY) | |
618 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | |
619 | { | |
620 | return addr; | |
621 | } | |
622 | ||
623 | #else | |
624 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | |
625 | { | |
626 | target_phys_addr_t phys_addr; | |
627 | int prot, access_index; | |
628 | ||
629 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, | |
630 | MMU_KERNEL_IDX) != 0) | |
631 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, | |
632 | 0, MMU_KERNEL_IDX) != 0) | |
633 | return -1; | |
634 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) | |
635 | return -1; | |
636 | return phys_addr; | |
637 | } | |
638 | #endif | |
639 | ||
c48fcb47 BS |
640 | void cpu_reset(CPUSPARCState *env) |
641 | { | |
eca1bdf4 AL |
642 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
643 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
644 | log_cpu_state(env, 0); | |
645 | } | |
646 | ||
c48fcb47 BS |
647 | tlb_flush(env, 1); |
648 | env->cwp = 0; | |
649 | env->wim = 1; | |
650 | env->regwptr = env->regbase + (env->cwp * 16); | |
651 | #if defined(CONFIG_USER_ONLY) | |
c48fcb47 | 652 | #ifdef TARGET_SPARC64 |
1a14026e BS |
653 | env->cleanwin = env->nwindows - 2; |
654 | env->cansave = env->nwindows - 2; | |
c48fcb47 BS |
655 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
656 | env->asi = 0x82; // Primary no-fault | |
657 | #endif | |
658 | #else | |
659 | env->psret = 0; | |
660 | env->psrs = 1; | |
661 | env->psrps = 1; | |
662 | #ifdef TARGET_SPARC64 | |
663 | env->pstate = PS_PRIV; | |
664 | env->hpstate = HS_PRIV; | |
c19148bd | 665 | env->tsptr = &env->ts[env->tl & MAXTL_MASK]; |
415fc906 | 666 | env->lsu = 0; |
c48fcb47 | 667 | #else |
c48fcb47 | 668 | env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
5578ceab | 669 | env->mmuregs[0] |= env->def->mmu_bm; |
c48fcb47 | 670 | #endif |
e87231d4 | 671 | env->pc = 0; |
c48fcb47 BS |
672 | env->npc = env->pc + 4; |
673 | #endif | |
674 | } | |
675 | ||
64a88d5d | 676 | static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
c48fcb47 | 677 | { |
64a88d5d | 678 | sparc_def_t def1, *def = &def1; |
c48fcb47 | 679 | |
64a88d5d BS |
680 | if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
681 | return -1; | |
c48fcb47 | 682 | |
5578ceab BS |
683 | env->def = qemu_mallocz(sizeof(*def)); |
684 | memcpy(env->def, def, sizeof(*def)); | |
685 | #if defined(CONFIG_USER_ONLY) | |
686 | if ((env->def->features & CPU_FEATURE_FLOAT)) | |
687 | env->def->features |= CPU_FEATURE_FLOAT128; | |
688 | #endif | |
c48fcb47 BS |
689 | env->cpu_model_str = cpu_model; |
690 | env->version = def->iu_version; | |
691 | env->fsr = def->fpu_version; | |
1a14026e | 692 | env->nwindows = def->nwindows; |
c48fcb47 | 693 | #if !defined(TARGET_SPARC64) |
c48fcb47 BS |
694 | env->mmuregs[0] |= def->mmu_version; |
695 | cpu_sparc_set_id(env, 0); | |
963262de | 696 | env->mxccregs[7] |= def->mxcc_version; |
1a14026e | 697 | #else |
fb79ceb9 | 698 | env->mmu_version = def->mmu_version; |
c19148bd BS |
699 | env->maxtl = def->maxtl; |
700 | env->version |= def->maxtl << 8; | |
1a14026e | 701 | env->version |= def->nwindows - 1; |
c48fcb47 | 702 | #endif |
64a88d5d BS |
703 | return 0; |
704 | } | |
705 | ||
706 | static void cpu_sparc_close(CPUSPARCState *env) | |
707 | { | |
5578ceab | 708 | free(env->def); |
64a88d5d BS |
709 | free(env); |
710 | } | |
711 | ||
712 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) | |
713 | { | |
714 | CPUSPARCState *env; | |
715 | ||
716 | env = qemu_mallocz(sizeof(CPUSPARCState)); | |
64a88d5d | 717 | cpu_exec_init(env); |
c48fcb47 BS |
718 | |
719 | gen_intermediate_code_init(env); | |
720 | ||
64a88d5d BS |
721 | if (cpu_sparc_register(env, cpu_model) < 0) { |
722 | cpu_sparc_close(env); | |
723 | return NULL; | |
724 | } | |
c48fcb47 BS |
725 | cpu_reset(env); |
726 | ||
727 | return env; | |
728 | } | |
729 | ||
730 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) | |
731 | { | |
732 | #if !defined(TARGET_SPARC64) | |
733 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; | |
734 | #endif | |
735 | } | |
736 | ||
737 | static const sparc_def_t sparc_defs[] = { | |
738 | #ifdef TARGET_SPARC64 | |
739 | { | |
740 | .name = "Fujitsu Sparc64", | |
c19148bd | 741 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
c48fcb47 | 742 | .fpu_version = 0x00000000, |
fb79ceb9 | 743 | .mmu_version = mmu_us_12, |
1a14026e | 744 | .nwindows = 4, |
c19148bd | 745 | .maxtl = 4, |
64a88d5d | 746 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
747 | }, |
748 | { | |
749 | .name = "Fujitsu Sparc64 III", | |
c19148bd | 750 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
c48fcb47 | 751 | .fpu_version = 0x00000000, |
fb79ceb9 | 752 | .mmu_version = mmu_us_12, |
1a14026e | 753 | .nwindows = 5, |
c19148bd | 754 | .maxtl = 4, |
64a88d5d | 755 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
756 | }, |
757 | { | |
758 | .name = "Fujitsu Sparc64 IV", | |
c19148bd | 759 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
c48fcb47 | 760 | .fpu_version = 0x00000000, |
fb79ceb9 | 761 | .mmu_version = mmu_us_12, |
1a14026e | 762 | .nwindows = 8, |
c19148bd | 763 | .maxtl = 5, |
64a88d5d | 764 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
765 | }, |
766 | { | |
767 | .name = "Fujitsu Sparc64 V", | |
c19148bd | 768 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
c48fcb47 | 769 | .fpu_version = 0x00000000, |
fb79ceb9 | 770 | .mmu_version = mmu_us_12, |
1a14026e | 771 | .nwindows = 8, |
c19148bd | 772 | .maxtl = 5, |
64a88d5d | 773 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
774 | }, |
775 | { | |
776 | .name = "TI UltraSparc I", | |
c19148bd | 777 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
c48fcb47 | 778 | .fpu_version = 0x00000000, |
fb79ceb9 | 779 | .mmu_version = mmu_us_12, |
1a14026e | 780 | .nwindows = 8, |
c19148bd | 781 | .maxtl = 5, |
64a88d5d | 782 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
783 | }, |
784 | { | |
785 | .name = "TI UltraSparc II", | |
c19148bd | 786 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
c48fcb47 | 787 | .fpu_version = 0x00000000, |
fb79ceb9 | 788 | .mmu_version = mmu_us_12, |
1a14026e | 789 | .nwindows = 8, |
c19148bd | 790 | .maxtl = 5, |
64a88d5d | 791 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
792 | }, |
793 | { | |
794 | .name = "TI UltraSparc IIi", | |
c19148bd | 795 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
c48fcb47 | 796 | .fpu_version = 0x00000000, |
fb79ceb9 | 797 | .mmu_version = mmu_us_12, |
1a14026e | 798 | .nwindows = 8, |
c19148bd | 799 | .maxtl = 5, |
64a88d5d | 800 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
801 | }, |
802 | { | |
803 | .name = "TI UltraSparc IIe", | |
c19148bd | 804 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
c48fcb47 | 805 | .fpu_version = 0x00000000, |
fb79ceb9 | 806 | .mmu_version = mmu_us_12, |
1a14026e | 807 | .nwindows = 8, |
c19148bd | 808 | .maxtl = 5, |
64a88d5d | 809 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
810 | }, |
811 | { | |
812 | .name = "Sun UltraSparc III", | |
c19148bd | 813 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
c48fcb47 | 814 | .fpu_version = 0x00000000, |
fb79ceb9 | 815 | .mmu_version = mmu_us_12, |
1a14026e | 816 | .nwindows = 8, |
c19148bd | 817 | .maxtl = 5, |
64a88d5d | 818 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
819 | }, |
820 | { | |
821 | .name = "Sun UltraSparc III Cu", | |
c19148bd | 822 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
c48fcb47 | 823 | .fpu_version = 0x00000000, |
fb79ceb9 | 824 | .mmu_version = mmu_us_3, |
1a14026e | 825 | .nwindows = 8, |
c19148bd | 826 | .maxtl = 5, |
64a88d5d | 827 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
828 | }, |
829 | { | |
830 | .name = "Sun UltraSparc IIIi", | |
c19148bd | 831 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
c48fcb47 | 832 | .fpu_version = 0x00000000, |
fb79ceb9 | 833 | .mmu_version = mmu_us_12, |
1a14026e | 834 | .nwindows = 8, |
c19148bd | 835 | .maxtl = 5, |
64a88d5d | 836 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
837 | }, |
838 | { | |
839 | .name = "Sun UltraSparc IV", | |
c19148bd | 840 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
c48fcb47 | 841 | .fpu_version = 0x00000000, |
fb79ceb9 | 842 | .mmu_version = mmu_us_4, |
1a14026e | 843 | .nwindows = 8, |
c19148bd | 844 | .maxtl = 5, |
64a88d5d | 845 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
846 | }, |
847 | { | |
848 | .name = "Sun UltraSparc IV+", | |
c19148bd | 849 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
c48fcb47 | 850 | .fpu_version = 0x00000000, |
fb79ceb9 | 851 | .mmu_version = mmu_us_12, |
1a14026e | 852 | .nwindows = 8, |
c19148bd | 853 | .maxtl = 5, |
fb79ceb9 | 854 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
c48fcb47 BS |
855 | }, |
856 | { | |
857 | .name = "Sun UltraSparc IIIi+", | |
c19148bd | 858 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
c48fcb47 | 859 | .fpu_version = 0x00000000, |
fb79ceb9 | 860 | .mmu_version = mmu_us_3, |
1a14026e | 861 | .nwindows = 8, |
c19148bd | 862 | .maxtl = 5, |
64a88d5d | 863 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 | 864 | }, |
c7ba218d BS |
865 | { |
866 | .name = "Sun UltraSparc T1", | |
867 | // defined in sparc_ifu_fdp.v and ctu.h | |
c19148bd | 868 | .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
c7ba218d BS |
869 | .fpu_version = 0x00000000, |
870 | .mmu_version = mmu_sun4v, | |
871 | .nwindows = 8, | |
c19148bd | 872 | .maxtl = 6, |
c7ba218d BS |
873 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
874 | | CPU_FEATURE_GL, | |
875 | }, | |
876 | { | |
877 | .name = "Sun UltraSparc T2", | |
878 | // defined in tlu_asi_ctl.v and n2_revid_cust.v | |
c19148bd | 879 | .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
c7ba218d BS |
880 | .fpu_version = 0x00000000, |
881 | .mmu_version = mmu_sun4v, | |
882 | .nwindows = 8, | |
c19148bd | 883 | .maxtl = 6, |
c7ba218d BS |
884 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
885 | | CPU_FEATURE_GL, | |
886 | }, | |
c48fcb47 BS |
887 | { |
888 | .name = "NEC UltraSparc I", | |
c19148bd | 889 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
c48fcb47 | 890 | .fpu_version = 0x00000000, |
fb79ceb9 | 891 | .mmu_version = mmu_us_12, |
1a14026e | 892 | .nwindows = 8, |
c19148bd | 893 | .maxtl = 5, |
64a88d5d | 894 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
895 | }, |
896 | #else | |
897 | { | |
898 | .name = "Fujitsu MB86900", | |
899 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
900 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
901 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ | |
902 | .mmu_bm = 0x00004000, | |
903 | .mmu_ctpr_mask = 0x007ffff0, | |
904 | .mmu_cxr_mask = 0x0000003f, | |
905 | .mmu_sfsr_mask = 0xffffffff, | |
906 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 907 | .nwindows = 7, |
e30b4678 | 908 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
c48fcb47 BS |
909 | }, |
910 | { | |
911 | .name = "Fujitsu MB86904", | |
912 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
913 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
914 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ | |
915 | .mmu_bm = 0x00004000, | |
916 | .mmu_ctpr_mask = 0x00ffffc0, | |
917 | .mmu_cxr_mask = 0x000000ff, | |
918 | .mmu_sfsr_mask = 0x00016fff, | |
919 | .mmu_trcr_mask = 0x00ffffff, | |
1a14026e | 920 | .nwindows = 8, |
64a88d5d | 921 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
922 | }, |
923 | { | |
924 | .name = "Fujitsu MB86907", | |
925 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
926 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
927 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ | |
928 | .mmu_bm = 0x00004000, | |
929 | .mmu_ctpr_mask = 0xffffffc0, | |
930 | .mmu_cxr_mask = 0x000000ff, | |
931 | .mmu_sfsr_mask = 0x00016fff, | |
932 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 933 | .nwindows = 8, |
64a88d5d | 934 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
935 | }, |
936 | { | |
937 | .name = "LSI L64811", | |
938 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ | |
939 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ | |
940 | .mmu_version = 0x10 << 24, | |
941 | .mmu_bm = 0x00004000, | |
942 | .mmu_ctpr_mask = 0x007ffff0, | |
943 | .mmu_cxr_mask = 0x0000003f, | |
944 | .mmu_sfsr_mask = 0xffffffff, | |
945 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 946 | .nwindows = 8, |
e30b4678 BS |
947 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
948 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
949 | }, |
950 | { | |
951 | .name = "Cypress CY7C601", | |
952 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ | |
953 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
954 | .mmu_version = 0x10 << 24, | |
955 | .mmu_bm = 0x00004000, | |
956 | .mmu_ctpr_mask = 0x007ffff0, | |
957 | .mmu_cxr_mask = 0x0000003f, | |
958 | .mmu_sfsr_mask = 0xffffffff, | |
959 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 960 | .nwindows = 8, |
e30b4678 BS |
961 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
962 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
963 | }, |
964 | { | |
965 | .name = "Cypress CY7C611", | |
966 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ | |
967 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ | |
968 | .mmu_version = 0x10 << 24, | |
969 | .mmu_bm = 0x00004000, | |
970 | .mmu_ctpr_mask = 0x007ffff0, | |
971 | .mmu_cxr_mask = 0x0000003f, | |
972 | .mmu_sfsr_mask = 0xffffffff, | |
973 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 974 | .nwindows = 8, |
e30b4678 BS |
975 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
976 | CPU_FEATURE_FSMULD, | |
c48fcb47 | 977 | }, |
c48fcb47 BS |
978 | { |
979 | .name = "TI MicroSparc I", | |
980 | .iu_version = 0x41000000, | |
981 | .fpu_version = 4 << 17, | |
982 | .mmu_version = 0x41000000, | |
983 | .mmu_bm = 0x00004000, | |
984 | .mmu_ctpr_mask = 0x007ffff0, | |
985 | .mmu_cxr_mask = 0x0000003f, | |
986 | .mmu_sfsr_mask = 0x00016fff, | |
987 | .mmu_trcr_mask = 0x0000003f, | |
1a14026e | 988 | .nwindows = 7, |
e30b4678 BS |
989 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
990 | CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | | |
991 | CPU_FEATURE_FMUL, | |
c48fcb47 BS |
992 | }, |
993 | { | |
994 | .name = "TI MicroSparc II", | |
995 | .iu_version = 0x42000000, | |
996 | .fpu_version = 4 << 17, | |
997 | .mmu_version = 0x02000000, | |
998 | .mmu_bm = 0x00004000, | |
999 | .mmu_ctpr_mask = 0x00ffffc0, | |
1000 | .mmu_cxr_mask = 0x000000ff, | |
1001 | .mmu_sfsr_mask = 0x00016fff, | |
1002 | .mmu_trcr_mask = 0x00ffffff, | |
1a14026e | 1003 | .nwindows = 8, |
64a88d5d | 1004 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1005 | }, |
1006 | { | |
1007 | .name = "TI MicroSparc IIep", | |
1008 | .iu_version = 0x42000000, | |
1009 | .fpu_version = 4 << 17, | |
1010 | .mmu_version = 0x04000000, | |
1011 | .mmu_bm = 0x00004000, | |
1012 | .mmu_ctpr_mask = 0x00ffffc0, | |
1013 | .mmu_cxr_mask = 0x000000ff, | |
1014 | .mmu_sfsr_mask = 0x00016bff, | |
1015 | .mmu_trcr_mask = 0x00ffffff, | |
1a14026e | 1016 | .nwindows = 8, |
64a88d5d | 1017 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 | 1018 | }, |
b5154bde BS |
1019 | { |
1020 | .name = "TI SuperSparc 40", // STP1020NPGA | |
963262de | 1021 | .iu_version = 0x41000000, // SuperSPARC 2.x |
b5154bde | 1022 | .fpu_version = 0 << 17, |
963262de | 1023 | .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC |
b5154bde BS |
1024 | .mmu_bm = 0x00002000, |
1025 | .mmu_ctpr_mask = 0xffffffc0, | |
1026 | .mmu_cxr_mask = 0x0000ffff, | |
1027 | .mmu_sfsr_mask = 0xffffffff, | |
1028 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1029 | .nwindows = 8, |
b5154bde BS |
1030 | .features = CPU_DEFAULT_FEATURES, |
1031 | }, | |
1032 | { | |
1033 | .name = "TI SuperSparc 50", // STP1020PGA | |
963262de | 1034 | .iu_version = 0x40000000, // SuperSPARC 3.x |
b5154bde | 1035 | .fpu_version = 0 << 17, |
963262de | 1036 | .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
b5154bde BS |
1037 | .mmu_bm = 0x00002000, |
1038 | .mmu_ctpr_mask = 0xffffffc0, | |
1039 | .mmu_cxr_mask = 0x0000ffff, | |
1040 | .mmu_sfsr_mask = 0xffffffff, | |
1041 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1042 | .nwindows = 8, |
b5154bde BS |
1043 | .features = CPU_DEFAULT_FEATURES, |
1044 | }, | |
c48fcb47 BS |
1045 | { |
1046 | .name = "TI SuperSparc 51", | |
963262de | 1047 | .iu_version = 0x40000000, // SuperSPARC 3.x |
c48fcb47 | 1048 | .fpu_version = 0 << 17, |
963262de | 1049 | .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
c48fcb47 BS |
1050 | .mmu_bm = 0x00002000, |
1051 | .mmu_ctpr_mask = 0xffffffc0, | |
1052 | .mmu_cxr_mask = 0x0000ffff, | |
1053 | .mmu_sfsr_mask = 0xffffffff, | |
1054 | .mmu_trcr_mask = 0xffffffff, | |
963262de | 1055 | .mxcc_version = 0x00000104, |
1a14026e | 1056 | .nwindows = 8, |
64a88d5d | 1057 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 | 1058 | }, |
b5154bde BS |
1059 | { |
1060 | .name = "TI SuperSparc 60", // STP1020APGA | |
963262de | 1061 | .iu_version = 0x40000000, // SuperSPARC 3.x |
b5154bde | 1062 | .fpu_version = 0 << 17, |
963262de | 1063 | .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
b5154bde BS |
1064 | .mmu_bm = 0x00002000, |
1065 | .mmu_ctpr_mask = 0xffffffc0, | |
1066 | .mmu_cxr_mask = 0x0000ffff, | |
1067 | .mmu_sfsr_mask = 0xffffffff, | |
1068 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1069 | .nwindows = 8, |
b5154bde BS |
1070 | .features = CPU_DEFAULT_FEATURES, |
1071 | }, | |
c48fcb47 BS |
1072 | { |
1073 | .name = "TI SuperSparc 61", | |
963262de | 1074 | .iu_version = 0x44000000, // SuperSPARC 3.x |
c48fcb47 | 1075 | .fpu_version = 0 << 17, |
963262de BS |
1076 | .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1077 | .mmu_bm = 0x00002000, | |
1078 | .mmu_ctpr_mask = 0xffffffc0, | |
1079 | .mmu_cxr_mask = 0x0000ffff, | |
1080 | .mmu_sfsr_mask = 0xffffffff, | |
1081 | .mmu_trcr_mask = 0xffffffff, | |
1082 | .mxcc_version = 0x00000104, | |
1083 | .nwindows = 8, | |
1084 | .features = CPU_DEFAULT_FEATURES, | |
1085 | }, | |
1086 | { | |
1087 | .name = "TI SuperSparc II", | |
1088 | .iu_version = 0x40000000, // SuperSPARC II 1.x | |
1089 | .fpu_version = 0 << 17, | |
1090 | .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC | |
c48fcb47 BS |
1091 | .mmu_bm = 0x00002000, |
1092 | .mmu_ctpr_mask = 0xffffffc0, | |
1093 | .mmu_cxr_mask = 0x0000ffff, | |
1094 | .mmu_sfsr_mask = 0xffffffff, | |
1095 | .mmu_trcr_mask = 0xffffffff, | |
963262de | 1096 | .mxcc_version = 0x00000104, |
1a14026e | 1097 | .nwindows = 8, |
64a88d5d | 1098 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1099 | }, |
1100 | { | |
1101 | .name = "Ross RT625", | |
1102 | .iu_version = 0x1e000000, | |
1103 | .fpu_version = 1 << 17, | |
1104 | .mmu_version = 0x1e000000, | |
1105 | .mmu_bm = 0x00004000, | |
1106 | .mmu_ctpr_mask = 0x007ffff0, | |
1107 | .mmu_cxr_mask = 0x0000003f, | |
1108 | .mmu_sfsr_mask = 0xffffffff, | |
1109 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1110 | .nwindows = 8, |
64a88d5d | 1111 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1112 | }, |
1113 | { | |
1114 | .name = "Ross RT620", | |
1115 | .iu_version = 0x1f000000, | |
1116 | .fpu_version = 1 << 17, | |
1117 | .mmu_version = 0x1f000000, | |
1118 | .mmu_bm = 0x00004000, | |
1119 | .mmu_ctpr_mask = 0x007ffff0, | |
1120 | .mmu_cxr_mask = 0x0000003f, | |
1121 | .mmu_sfsr_mask = 0xffffffff, | |
1122 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1123 | .nwindows = 8, |
64a88d5d | 1124 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1125 | }, |
1126 | { | |
1127 | .name = "BIT B5010", | |
1128 | .iu_version = 0x20000000, | |
1129 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ | |
1130 | .mmu_version = 0x20000000, | |
1131 | .mmu_bm = 0x00004000, | |
1132 | .mmu_ctpr_mask = 0x007ffff0, | |
1133 | .mmu_cxr_mask = 0x0000003f, | |
1134 | .mmu_sfsr_mask = 0xffffffff, | |
1135 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1136 | .nwindows = 8, |
e30b4678 BS |
1137 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1138 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1139 | }, |
1140 | { | |
1141 | .name = "Matsushita MN10501", | |
1142 | .iu_version = 0x50000000, | |
1143 | .fpu_version = 0 << 17, | |
1144 | .mmu_version = 0x50000000, | |
1145 | .mmu_bm = 0x00004000, | |
1146 | .mmu_ctpr_mask = 0x007ffff0, | |
1147 | .mmu_cxr_mask = 0x0000003f, | |
1148 | .mmu_sfsr_mask = 0xffffffff, | |
1149 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1150 | .nwindows = 8, |
e30b4678 BS |
1151 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
1152 | CPU_FEATURE_FSMULD, | |
c48fcb47 BS |
1153 | }, |
1154 | { | |
1155 | .name = "Weitek W8601", | |
1156 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ | |
1157 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ | |
1158 | .mmu_version = 0x10 << 24, | |
1159 | .mmu_bm = 0x00004000, | |
1160 | .mmu_ctpr_mask = 0x007ffff0, | |
1161 | .mmu_cxr_mask = 0x0000003f, | |
1162 | .mmu_sfsr_mask = 0xffffffff, | |
1163 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1164 | .nwindows = 8, |
64a88d5d | 1165 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1166 | }, |
1167 | { | |
1168 | .name = "LEON2", | |
1169 | .iu_version = 0xf2000000, | |
1170 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1171 | .mmu_version = 0xf2000000, | |
1172 | .mmu_bm = 0x00004000, | |
1173 | .mmu_ctpr_mask = 0x007ffff0, | |
1174 | .mmu_cxr_mask = 0x0000003f, | |
1175 | .mmu_sfsr_mask = 0xffffffff, | |
1176 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1177 | .nwindows = 8, |
64a88d5d | 1178 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1179 | }, |
1180 | { | |
1181 | .name = "LEON3", | |
1182 | .iu_version = 0xf3000000, | |
1183 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | |
1184 | .mmu_version = 0xf3000000, | |
1185 | .mmu_bm = 0x00004000, | |
1186 | .mmu_ctpr_mask = 0x007ffff0, | |
1187 | .mmu_cxr_mask = 0x0000003f, | |
1188 | .mmu_sfsr_mask = 0xffffffff, | |
1189 | .mmu_trcr_mask = 0xffffffff, | |
1a14026e | 1190 | .nwindows = 8, |
64a88d5d | 1191 | .features = CPU_DEFAULT_FEATURES, |
c48fcb47 BS |
1192 | }, |
1193 | #endif | |
1194 | }; | |
1195 | ||
64a88d5d BS |
1196 | static const char * const feature_name[] = { |
1197 | "float", | |
1198 | "float128", | |
1199 | "swap", | |
1200 | "mul", | |
1201 | "div", | |
1202 | "flush", | |
1203 | "fsqrt", | |
1204 | "fmul", | |
1205 | "vis1", | |
1206 | "vis2", | |
e30b4678 | 1207 | "fsmuld", |
fb79ceb9 BS |
1208 | "hypv", |
1209 | "cmt", | |
1210 | "gl", | |
64a88d5d BS |
1211 | }; |
1212 | ||
1213 | static void print_features(FILE *f, | |
1214 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
1215 | uint32_t features, const char *prefix) | |
c48fcb47 BS |
1216 | { |
1217 | unsigned int i; | |
1218 | ||
64a88d5d BS |
1219 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1220 | if (feature_name[i] && (features & (1 << i))) { | |
1221 | if (prefix) | |
1222 | (*cpu_fprintf)(f, "%s", prefix); | |
1223 | (*cpu_fprintf)(f, "%s ", feature_name[i]); | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) | |
1228 | { | |
1229 | unsigned int i; | |
1230 | ||
1231 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) | |
1232 | if (feature_name[i] && !strcmp(flagname, feature_name[i])) { | |
1233 | *features |= 1 << i; | |
1234 | return; | |
1235 | } | |
1236 | fprintf(stderr, "CPU feature %s not found\n", flagname); | |
1237 | } | |
1238 | ||
22548760 | 1239 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
64a88d5d BS |
1240 | { |
1241 | unsigned int i; | |
1242 | const sparc_def_t *def = NULL; | |
1243 | char *s = strdup(cpu_model); | |
1244 | char *featurestr, *name = strtok(s, ","); | |
1245 | uint32_t plus_features = 0; | |
1246 | uint32_t minus_features = 0; | |
1247 | long long iu_version; | |
1a14026e | 1248 | uint32_t fpu_version, mmu_version, nwindows; |
64a88d5d | 1249 | |
b1503cda | 1250 | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
c48fcb47 | 1251 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
64a88d5d | 1252 | def = &sparc_defs[i]; |
c48fcb47 BS |
1253 | } |
1254 | } | |
64a88d5d BS |
1255 | if (!def) |
1256 | goto error; | |
1257 | memcpy(cpu_def, def, sizeof(*def)); | |
1258 | ||
1259 | featurestr = strtok(NULL, ","); | |
1260 | while (featurestr) { | |
1261 | char *val; | |
1262 | ||
1263 | if (featurestr[0] == '+') { | |
1264 | add_flagname_to_bitmaps(featurestr + 1, &plus_features); | |
1265 | } else if (featurestr[0] == '-') { | |
1266 | add_flagname_to_bitmaps(featurestr + 1, &minus_features); | |
1267 | } else if ((val = strchr(featurestr, '='))) { | |
1268 | *val = 0; val++; | |
1269 | if (!strcmp(featurestr, "iu_version")) { | |
1270 | char *err; | |
1271 | ||
1272 | iu_version = strtoll(val, &err, 0); | |
1273 | if (!*val || *err) { | |
1274 | fprintf(stderr, "bad numerical value %s\n", val); | |
1275 | goto error; | |
1276 | } | |
1277 | cpu_def->iu_version = iu_version; | |
1278 | #ifdef DEBUG_FEATURES | |
1279 | fprintf(stderr, "iu_version %llx\n", iu_version); | |
1280 | #endif | |
1281 | } else if (!strcmp(featurestr, "fpu_version")) { | |
1282 | char *err; | |
1283 | ||
1284 | fpu_version = strtol(val, &err, 0); | |
1285 | if (!*val || *err) { | |
1286 | fprintf(stderr, "bad numerical value %s\n", val); | |
1287 | goto error; | |
1288 | } | |
1289 | cpu_def->fpu_version = fpu_version; | |
1290 | #ifdef DEBUG_FEATURES | |
1291 | fprintf(stderr, "fpu_version %llx\n", fpu_version); | |
1292 | #endif | |
1293 | } else if (!strcmp(featurestr, "mmu_version")) { | |
1294 | char *err; | |
1295 | ||
1296 | mmu_version = strtol(val, &err, 0); | |
1297 | if (!*val || *err) { | |
1298 | fprintf(stderr, "bad numerical value %s\n", val); | |
1299 | goto error; | |
1300 | } | |
1301 | cpu_def->mmu_version = mmu_version; | |
1302 | #ifdef DEBUG_FEATURES | |
1303 | fprintf(stderr, "mmu_version %llx\n", mmu_version); | |
1a14026e BS |
1304 | #endif |
1305 | } else if (!strcmp(featurestr, "nwindows")) { | |
1306 | char *err; | |
1307 | ||
1308 | nwindows = strtol(val, &err, 0); | |
1309 | if (!*val || *err || nwindows > MAX_NWINDOWS || | |
1310 | nwindows < MIN_NWINDOWS) { | |
1311 | fprintf(stderr, "bad numerical value %s\n", val); | |
1312 | goto error; | |
1313 | } | |
1314 | cpu_def->nwindows = nwindows; | |
1315 | #ifdef DEBUG_FEATURES | |
1316 | fprintf(stderr, "nwindows %d\n", nwindows); | |
64a88d5d BS |
1317 | #endif |
1318 | } else { | |
1319 | fprintf(stderr, "unrecognized feature %s\n", featurestr); | |
1320 | goto error; | |
1321 | } | |
1322 | } else { | |
77f193da BS |
1323 | fprintf(stderr, "feature string `%s' not in format " |
1324 | "(+feature|-feature|feature=xyz)\n", featurestr); | |
64a88d5d BS |
1325 | goto error; |
1326 | } | |
1327 | featurestr = strtok(NULL, ","); | |
1328 | } | |
1329 | cpu_def->features |= plus_features; | |
1330 | cpu_def->features &= ~minus_features; | |
1331 | #ifdef DEBUG_FEATURES | |
1332 | print_features(stderr, fprintf, cpu_def->features, NULL); | |
1333 | #endif | |
1334 | free(s); | |
1335 | return 0; | |
1336 | ||
1337 | error: | |
1338 | free(s); | |
1339 | return -1; | |
c48fcb47 BS |
1340 | } |
1341 | ||
77f193da | 1342 | void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
c48fcb47 BS |
1343 | { |
1344 | unsigned int i; | |
1345 | ||
b1503cda | 1346 | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1a14026e | 1347 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ", |
c48fcb47 BS |
1348 | sparc_defs[i].name, |
1349 | sparc_defs[i].iu_version, | |
1350 | sparc_defs[i].fpu_version, | |
1a14026e BS |
1351 | sparc_defs[i].mmu_version, |
1352 | sparc_defs[i].nwindows); | |
77f193da BS |
1353 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1354 | ~sparc_defs[i].features, "-"); | |
1355 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & | |
1356 | sparc_defs[i].features, "+"); | |
64a88d5d | 1357 | (*cpu_fprintf)(f, "\n"); |
c48fcb47 | 1358 | } |
f76981b1 BS |
1359 | (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): "); |
1360 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL); | |
64a88d5d | 1361 | (*cpu_fprintf)(f, "\n"); |
f76981b1 BS |
1362 | (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): "); |
1363 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL); | |
1364 | (*cpu_fprintf)(f, "\n"); | |
1365 | (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version " | |
1366 | "fpu_version mmu_version nwindows\n"); | |
c48fcb47 BS |
1367 | } |
1368 | ||
c48fcb47 BS |
1369 | void cpu_dump_state(CPUState *env, FILE *f, |
1370 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
1371 | int flags) | |
1372 | { | |
1373 | int i, x; | |
1374 | ||
77f193da BS |
1375 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1376 | env->npc); | |
c48fcb47 BS |
1377 | cpu_fprintf(f, "General Registers:\n"); |
1378 | for (i = 0; i < 4; i++) | |
1379 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); | |
1380 | cpu_fprintf(f, "\n"); | |
1381 | for (; i < 8; i++) | |
1382 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); | |
1383 | cpu_fprintf(f, "\nCurrent Register Window:\n"); | |
1384 | for (x = 0; x < 3; x++) { | |
1385 | for (i = 0; i < 4; i++) | |
1386 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
1387 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, | |
1388 | env->regwptr[i + x * 8]); | |
1389 | cpu_fprintf(f, "\n"); | |
1390 | for (; i < 8; i++) | |
1391 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", | |
1392 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, | |
1393 | env->regwptr[i + x * 8]); | |
1394 | cpu_fprintf(f, "\n"); | |
1395 | } | |
1396 | cpu_fprintf(f, "\nFloating Point Registers:\n"); | |
1397 | for (i = 0; i < 32; i++) { | |
1398 | if ((i & 3) == 0) | |
1399 | cpu_fprintf(f, "%%f%02d:", i); | |
a37ee56c | 1400 | cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
c48fcb47 BS |
1401 | if ((i & 3) == 3) |
1402 | cpu_fprintf(f, "\n"); | |
1403 | } | |
1404 | #ifdef TARGET_SPARC64 | |
1405 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", | |
1406 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); | |
77f193da BS |
1407 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d " |
1408 | "cleanwin %d cwp %d\n", | |
c48fcb47 | 1409 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
1a14026e | 1410 | env->cleanwin, env->nwindows - 1 - env->cwp); |
c48fcb47 | 1411 | #else |
d78f3995 BS |
1412 | |
1413 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') | |
1414 | ||
77f193da BS |
1415 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", |
1416 | GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), | |
1417 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), | |
1418 | env->psrs?'S':'-', env->psrps?'P':'-', | |
1419 | env->psret?'E':'-', env->wim); | |
c48fcb47 | 1420 | #endif |
3a3b925d | 1421 | cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr); |
c48fcb47 | 1422 | } |