[mirror_qemu.git] / target-sparc / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "qemu/timer.h"

#include "cpu.h"

void cpu_save(QEMUFile *f, void *opaque)
{
    CPUSPARCState *env = opaque;
    int i;
    uint32_t tmp;

    // if env->cwp == env->nwindows - 1, this will set the ins of the last
    // window as the outs of the first window
    cpu_set_cwp(env, env->cwp);

    for(i = 0; i < 8; i++)
        qemu_put_betls(f, &env->gregs[i]);
    qemu_put_be32s(f, &env->nwindows);
    for(i = 0; i < env->nwindows * 16; i++)
        qemu_put_betls(f, &env->regbase[i]);

    /* FPU */
    for (i = 0; i < TARGET_DPREGS; i++) {
        qemu_put_be32(f, env->fpr[i].l.upper);
        qemu_put_be32(f, env->fpr[i].l.lower);
    }

    qemu_put_betls(f, &env->pc);
    qemu_put_betls(f, &env->npc);
    qemu_put_betls(f, &env->y);
    tmp = cpu_get_psr(env);
    qemu_put_be32(f, tmp);
    qemu_put_betls(f, &env->fsr);
    qemu_put_betls(f, &env->tbr);
    tmp = env->interrupt_index;
    qemu_put_be32(f, tmp);
    qemu_put_be32s(f, &env->pil_in);
#ifndef TARGET_SPARC64
    qemu_put_be32s(f, &env->wim);
    /* MMU */
    for (i = 0; i < 32; i++)
        qemu_put_be32s(f, &env->mmuregs[i]);
    for (i = 0; i < 4; i++) {
        qemu_put_be64s(f, &env->mxccdata[i]);
    }
    for (i = 0; i < 8; i++) {
        qemu_put_be64s(f, &env->mxccregs[i]);
    }
    qemu_put_be32s(f, &env->mmubpctrv);
    qemu_put_be32s(f, &env->mmubpctrc);
    qemu_put_be32s(f, &env->mmubpctrs);
    qemu_put_be64s(f, &env->mmubpaction);
    for (i = 0; i < 4; i++) {
        qemu_put_be64s(f, &env->mmubpregs[i]);
    }
#else
    qemu_put_be64s(f, &env->lsu);
    for (i = 0; i < 16; i++) {
        qemu_put_be64s(f, &env->immuregs[i]);
        qemu_put_be64s(f, &env->dmmuregs[i]);
    }
    for (i = 0; i < 64; i++) {
        qemu_put_be64s(f, &env->itlb[i].tag);
        qemu_put_be64s(f, &env->itlb[i].tte);
        qemu_put_be64s(f, &env->dtlb[i].tag);
        qemu_put_be64s(f, &env->dtlb[i].tte);
    }
    qemu_put_be32s(f, &env->mmu_version);
    for (i = 0; i < MAXTL_MAX; i++) {
        qemu_put_be64s(f, &env->ts[i].tpc);
        qemu_put_be64s(f, &env->ts[i].tnpc);
        qemu_put_be64s(f, &env->ts[i].tstate);
        qemu_put_be32s(f, &env->ts[i].tt);
    }
    qemu_put_be32s(f, &env->xcc);
    qemu_put_be32s(f, &env->asi);
    qemu_put_be32s(f, &env->pstate);
    qemu_put_be32s(f, &env->tl);
    qemu_put_be32s(f, &env->cansave);
    qemu_put_be32s(f, &env->canrestore);
    qemu_put_be32s(f, &env->otherwin);
    qemu_put_be32s(f, &env->wstate);
    qemu_put_be32s(f, &env->cleanwin);
    for (i = 0; i < 8; i++)
        qemu_put_be64s(f, &env->agregs[i]);
    for (i = 0; i < 8; i++)
        qemu_put_be64s(f, &env->bgregs[i]);
    for (i = 0; i < 8; i++)
        qemu_put_be64s(f, &env->igregs[i]);
    for (i = 0; i < 8; i++)
        qemu_put_be64s(f, &env->mgregs[i]);
    qemu_put_be64s(f, &env->fprs);
    qemu_put_be64s(f, &env->tick_cmpr);
    qemu_put_be64s(f, &env->stick_cmpr);
    cpu_put_timer(f, env->tick);
    cpu_put_timer(f, env->stick);
    qemu_put_be64s(f, &env->gsr);
    qemu_put_be32s(f, &env->gl);
    qemu_put_be64s(f, &env->hpstate);
    for (i = 0; i < MAXTL_MAX; i++)
        qemu_put_be64s(f, &env->htstate[i]);
    qemu_put_be64s(f, &env->hintp);
    qemu_put_be64s(f, &env->htba);
    qemu_put_be64s(f, &env->hver);
    qemu_put_be64s(f, &env->hstick_cmpr);
    qemu_put_be64s(f, &env->ssr);
    cpu_put_timer(f, env->hstick);
#endif
}

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUSPARCState *env = opaque;
    SPARCCPU *cpu = sparc_env_get_cpu(env);
    int i;
    uint32_t tmp;

    if (version_id < 6)
        return -EINVAL;
    for(i = 0; i < 8; i++)
        qemu_get_betls(f, &env->gregs[i]);
    qemu_get_be32s(f, &env->nwindows);
    for(i = 0; i < env->nwindows * 16; i++)
        qemu_get_betls(f, &env->regbase[i]);

    /* FPU */
    for (i = 0; i < TARGET_DPREGS; i++) {
        env->fpr[i].l.upper = qemu_get_be32(f);
        env->fpr[i].l.lower = qemu_get_be32(f);
    }

    qemu_get_betls(f, &env->pc);
    qemu_get_betls(f, &env->npc);
    qemu_get_betls(f, &env->y);
    tmp = qemu_get_be32(f);
    env->cwp = 0; /* needed to ensure that the wrapping registers are
                     correctly updated */
    cpu_put_psr(env, tmp);
    qemu_get_betls(f, &env->fsr);
    qemu_get_betls(f, &env->tbr);
    tmp = qemu_get_be32(f);
    env->interrupt_index = tmp;
    qemu_get_be32s(f, &env->pil_in);
#ifndef TARGET_SPARC64
    qemu_get_be32s(f, &env->wim);
    /* MMU */
    for (i = 0; i < 32; i++)
        qemu_get_be32s(f, &env->mmuregs[i]);
    for (i = 0; i < 4; i++) {
        qemu_get_be64s(f, &env->mxccdata[i]);
    }
    for (i = 0; i < 8; i++) {
        qemu_get_be64s(f, &env->mxccregs[i]);
    }
    qemu_get_be32s(f, &env->mmubpctrv);
    qemu_get_be32s(f, &env->mmubpctrc);
    qemu_get_be32s(f, &env->mmubpctrs);
    qemu_get_be64s(f, &env->mmubpaction);
    for (i = 0; i < 4; i++) {
        qemu_get_be64s(f, &env->mmubpregs[i]);
    }
#else
    qemu_get_be64s(f, &env->lsu);
    for (i = 0; i < 16; i++) {
        qemu_get_be64s(f, &env->immuregs[i]);
        qemu_get_be64s(f, &env->dmmuregs[i]);
    }
    for (i = 0; i < 64; i++) {
        qemu_get_be64s(f, &env->itlb[i].tag);
        qemu_get_be64s(f, &env->itlb[i].tte);
        qemu_get_be64s(f, &env->dtlb[i].tag);
        qemu_get_be64s(f, &env->dtlb[i].tte);
    }
    qemu_get_be32s(f, &env->mmu_version);
    for (i = 0; i < MAXTL_MAX; i++) {
        qemu_get_be64s(f, &env->ts[i].tpc);
        qemu_get_be64s(f, &env->ts[i].tnpc);
        qemu_get_be64s(f, &env->ts[i].tstate);
        qemu_get_be32s(f, &env->ts[i].tt);
    }
    qemu_get_be32s(f, &env->xcc);
    qemu_get_be32s(f, &env->asi);
    qemu_get_be32s(f, &env->pstate);
    qemu_get_be32s(f, &env->tl);
    qemu_get_be32s(f, &env->cansave);
    qemu_get_be32s(f, &env->canrestore);
    qemu_get_be32s(f, &env->otherwin);
    qemu_get_be32s(f, &env->wstate);
    qemu_get_be32s(f, &env->cleanwin);
    for (i = 0; i < 8; i++)
        qemu_get_be64s(f, &env->agregs[i]);
    for (i = 0; i < 8; i++)
        qemu_get_be64s(f, &env->bgregs[i]);
    for (i = 0; i < 8; i++)
        qemu_get_be64s(f, &env->igregs[i]);
    for (i = 0; i < 8; i++)
        qemu_get_be64s(f, &env->mgregs[i]);
    qemu_get_be64s(f, &env->fprs);
    qemu_get_be64s(f, &env->tick_cmpr);
    qemu_get_be64s(f, &env->stick_cmpr);
    cpu_get_timer(f, env->tick);
    cpu_get_timer(f, env->stick);
    qemu_get_be64s(f, &env->gsr);
    qemu_get_be32s(f, &env->gl);
    qemu_get_be64s(f, &env->hpstate);
    for (i = 0; i < MAXTL_MAX; i++)
        qemu_get_be64s(f, &env->htstate[i]);
    qemu_get_be64s(f, &env->hintp);
    qemu_get_be64s(f, &env->htba);
    qemu_get_be64s(f, &env->hver);
    qemu_get_be64s(f, &env->hstick_cmpr);
    qemu_get_be64s(f, &env->ssr);
    cpu_get_timer(f, env->hstick);
#endif
    tlb_flush(CPU(cpu), 1);
    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
8dd3dca3 AJ	2	#include "hw/boards.h"
1de7afc9	3	#include "qemu/timer.h"
8dd3dca3	4
2b41f10e	5	#include "cpu.h"
8dd3dca3	6
8dd3dca3 AJ	7	void cpu_save(QEMUFile f, void opaque)
8dd3dca3 AJ	8	{
c5f9864e	9	CPUSPARCState *env = opaque;
8dd3dca3 AJ	10	int i;
	11	uint32_t tmp;
	12
a7a044f2 BS	13	// if env->cwp == env->nwindows - 1, this will set the ins of the last
	14	// window as the outs of the first window
	15	cpu_set_cwp(env, env->cwp);
	16
8dd3dca3 AJ	17	for(i = 0; i < 8; i++)
8dd3dca3 AJ	18	qemu_put_betls(f, &env->gregs[i]);
1a14026e BS	19	qemu_put_be32s(f, &env->nwindows);
1a14026e BS	20	for(i = 0; i < env->nwindows * 16; i++)
8dd3dca3 AJ	21	qemu_put_betls(f, &env->regbase[i]);
	22
	23	/* FPU */
30038fd8 RH	24	for (i = 0; i < TARGET_DPREGS; i++) {
	25	qemu_put_be32(f, env->fpr[i].l.upper);
	26	qemu_put_be32(f, env->fpr[i].l.lower);
8dd3dca3 AJ	27	}
	28
	29	qemu_put_betls(f, &env->pc);
	30	qemu_put_betls(f, &env->npc);
	31	qemu_put_betls(f, &env->y);
5a834bb4	32	tmp = cpu_get_psr(env);
8dd3dca3 AJ	33	qemu_put_be32(f, tmp);
	34	qemu_put_betls(f, &env->fsr);
	35	qemu_put_betls(f, &env->tbr);
a7a044f2 BS	36	tmp = env->interrupt_index;
	37	qemu_put_be32(f, tmp);
	38	qemu_put_be32s(f, &env->pil_in);
8dd3dca3 AJ	39	#ifndef TARGET_SPARC64
	40	qemu_put_be32s(f, &env->wim);
	41	/* MMU */
0b8f1b10	42	for (i = 0; i < 32; i++)
8dd3dca3	43	qemu_put_be32s(f, &env->mmuregs[i]);
4d2c2b77 BS	44	for (i = 0; i < 4; i++) {
	45	qemu_put_be64s(f, &env->mxccdata[i]);
	46	}
	47	for (i = 0; i < 8; i++) {
	48	qemu_put_be64s(f, &env->mxccregs[i]);
	49	}
	50	qemu_put_be32s(f, &env->mmubpctrv);
	51	qemu_put_be32s(f, &env->mmubpctrc);
	52	qemu_put_be32s(f, &env->mmubpctrs);
	53	qemu_put_be64s(f, &env->mmubpaction);
	54	for (i = 0; i < 4; i++) {
	55	qemu_put_be64s(f, &env->mmubpregs[i]);
	56	}
0b8f1b10 BS	57	#else
	58	qemu_put_be64s(f, &env->lsu);
	59	for (i = 0; i < 16; i++) {
	60	qemu_put_be64s(f, &env->immuregs[i]);
	61	qemu_put_be64s(f, &env->dmmuregs[i]);
	62	}
	63	for (i = 0; i < 64; i++) {
6e8e7d4c IK	64	qemu_put_be64s(f, &env->itlb[i].tag);
	65	qemu_put_be64s(f, &env->itlb[i].tte);
	66	qemu_put_be64s(f, &env->dtlb[i].tag);
	67	qemu_put_be64s(f, &env->dtlb[i].tte);
0b8f1b10 BS	68	}
0b8f1b10 BS	69	qemu_put_be32s(f, &env->mmu_version);
c19148bd	70	for (i = 0; i < MAXTL_MAX; i++) {
0b8f1b10 BS	71	qemu_put_be64s(f, &env->ts[i].tpc);
	72	qemu_put_be64s(f, &env->ts[i].tnpc);
	73	qemu_put_be64s(f, &env->ts[i].tstate);
	74	qemu_put_be32s(f, &env->ts[i].tt);
	75	}
	76	qemu_put_be32s(f, &env->xcc);
	77	qemu_put_be32s(f, &env->asi);
	78	qemu_put_be32s(f, &env->pstate);
	79	qemu_put_be32s(f, &env->tl);
	80	qemu_put_be32s(f, &env->cansave);
	81	qemu_put_be32s(f, &env->canrestore);
	82	qemu_put_be32s(f, &env->otherwin);
	83	qemu_put_be32s(f, &env->wstate);
	84	qemu_put_be32s(f, &env->cleanwin);
	85	for (i = 0; i < 8; i++)
	86	qemu_put_be64s(f, &env->agregs[i]);
	87	for (i = 0; i < 8; i++)
	88	qemu_put_be64s(f, &env->bgregs[i]);
	89	for (i = 0; i < 8; i++)
	90	qemu_put_be64s(f, &env->igregs[i]);
	91	for (i = 0; i < 8; i++)
	92	qemu_put_be64s(f, &env->mgregs[i]);
	93	qemu_put_be64s(f, &env->fprs);
	94	qemu_put_be64s(f, &env->tick_cmpr);
	95	qemu_put_be64s(f, &env->stick_cmpr);
8f4efc55 IK	96	cpu_put_timer(f, env->tick);
8f4efc55 IK	97	cpu_put_timer(f, env->stick);
0b8f1b10 BS	98	qemu_put_be64s(f, &env->gsr);
	99	qemu_put_be32s(f, &env->gl);
	100	qemu_put_be64s(f, &env->hpstate);
c19148bd	101	for (i = 0; i < MAXTL_MAX; i++)
0b8f1b10 BS	102	qemu_put_be64s(f, &env->htstate[i]);
	103	qemu_put_be64s(f, &env->hintp);
	104	qemu_put_be64s(f, &env->htba);
	105	qemu_put_be64s(f, &env->hver);
	106	qemu_put_be64s(f, &env->hstick_cmpr);
	107	qemu_put_be64s(f, &env->ssr);
8f4efc55	108	cpu_put_timer(f, env->hstick);
8dd3dca3 AJ	109	#endif
	110	}
	111
	112	int cpu_load(QEMUFile f, void opaque, int version_id)
	113	{
c5f9864e	114	CPUSPARCState *env = opaque;
00c8cb0a	115	SPARCCPU *cpu = sparc_env_get_cpu(env);
8dd3dca3 AJ	116	int i;
	117	uint32_t tmp;
	118
8f4efc55	119	if (version_id < 6)
1a14026e	120	return -EINVAL;
8dd3dca3 AJ	121	for(i = 0; i < 8; i++)
8dd3dca3 AJ	122	qemu_get_betls(f, &env->gregs[i]);
1a14026e BS	123	qemu_get_be32s(f, &env->nwindows);
1a14026e BS	124	for(i = 0; i < env->nwindows * 16; i++)
8dd3dca3 AJ	125	qemu_get_betls(f, &env->regbase[i]);
	126
	127	/* FPU */
30038fd8 RH	128	for (i = 0; i < TARGET_DPREGS; i++) {
	129	env->fpr[i].l.upper = qemu_get_be32(f);
	130	env->fpr[i].l.lower = qemu_get_be32(f);
8dd3dca3 AJ	131	}
	132
	133	qemu_get_betls(f, &env->pc);
	134	qemu_get_betls(f, &env->npc);
	135	qemu_get_betls(f, &env->y);
	136	tmp = qemu_get_be32(f);
	137	env->cwp = 0; /* needed to ensure that the wrapping registers are
	138	correctly updated */
5a834bb4	139	cpu_put_psr(env, tmp);
8dd3dca3 AJ	140	qemu_get_betls(f, &env->fsr);
8dd3dca3 AJ	141	qemu_get_betls(f, &env->tbr);
a7a044f2 BS	142	tmp = qemu_get_be32(f);
	143	env->interrupt_index = tmp;
	144	qemu_get_be32s(f, &env->pil_in);
8dd3dca3 AJ	145	#ifndef TARGET_SPARC64
	146	qemu_get_be32s(f, &env->wim);
	147	/* MMU */
0b8f1b10	148	for (i = 0; i < 32; i++)
8dd3dca3	149	qemu_get_be32s(f, &env->mmuregs[i]);
4d2c2b77 BS	150	for (i = 0; i < 4; i++) {
	151	qemu_get_be64s(f, &env->mxccdata[i]);
	152	}
	153	for (i = 0; i < 8; i++) {
	154	qemu_get_be64s(f, &env->mxccregs[i]);
	155	}
	156	qemu_get_be32s(f, &env->mmubpctrv);
	157	qemu_get_be32s(f, &env->mmubpctrc);
	158	qemu_get_be32s(f, &env->mmubpctrs);
	159	qemu_get_be64s(f, &env->mmubpaction);
	160	for (i = 0; i < 4; i++) {
	161	qemu_get_be64s(f, &env->mmubpregs[i]);
	162	}
0b8f1b10 BS	163	#else
	164	qemu_get_be64s(f, &env->lsu);
	165	for (i = 0; i < 16; i++) {
	166	qemu_get_be64s(f, &env->immuregs[i]);
	167	qemu_get_be64s(f, &env->dmmuregs[i]);
	168	}
	169	for (i = 0; i < 64; i++) {
6e8e7d4c IK	170	qemu_get_be64s(f, &env->itlb[i].tag);
	171	qemu_get_be64s(f, &env->itlb[i].tte);
	172	qemu_get_be64s(f, &env->dtlb[i].tag);
	173	qemu_get_be64s(f, &env->dtlb[i].tte);
0b8f1b10 BS	174	}
0b8f1b10 BS	175	qemu_get_be32s(f, &env->mmu_version);
c19148bd	176	for (i = 0; i < MAXTL_MAX; i++) {
0b8f1b10 BS	177	qemu_get_be64s(f, &env->ts[i].tpc);
	178	qemu_get_be64s(f, &env->ts[i].tnpc);
	179	qemu_get_be64s(f, &env->ts[i].tstate);
	180	qemu_get_be32s(f, &env->ts[i].tt);
	181	}
	182	qemu_get_be32s(f, &env->xcc);
	183	qemu_get_be32s(f, &env->asi);
	184	qemu_get_be32s(f, &env->pstate);
	185	qemu_get_be32s(f, &env->tl);
0b8f1b10 BS	186	qemu_get_be32s(f, &env->cansave);
	187	qemu_get_be32s(f, &env->canrestore);
	188	qemu_get_be32s(f, &env->otherwin);
	189	qemu_get_be32s(f, &env->wstate);
	190	qemu_get_be32s(f, &env->cleanwin);
	191	for (i = 0; i < 8; i++)
	192	qemu_get_be64s(f, &env->agregs[i]);
	193	for (i = 0; i < 8; i++)
	194	qemu_get_be64s(f, &env->bgregs[i]);
	195	for (i = 0; i < 8; i++)
	196	qemu_get_be64s(f, &env->igregs[i]);
	197	for (i = 0; i < 8; i++)
	198	qemu_get_be64s(f, &env->mgregs[i]);
	199	qemu_get_be64s(f, &env->fprs);
	200	qemu_get_be64s(f, &env->tick_cmpr);
	201	qemu_get_be64s(f, &env->stick_cmpr);
8f4efc55 IK	202	cpu_get_timer(f, env->tick);
8f4efc55 IK	203	cpu_get_timer(f, env->stick);
0b8f1b10 BS	204	qemu_get_be64s(f, &env->gsr);
	205	qemu_get_be32s(f, &env->gl);
	206	qemu_get_be64s(f, &env->hpstate);
c19148bd	207	for (i = 0; i < MAXTL_MAX; i++)
0b8f1b10 BS	208	qemu_get_be64s(f, &env->htstate[i]);
	209	qemu_get_be64s(f, &env->hintp);
	210	qemu_get_be64s(f, &env->htba);
	211	qemu_get_be64s(f, &env->hver);
	212	qemu_get_be64s(f, &env->hstick_cmpr);
	213	qemu_get_be64s(f, &env->ssr);
8f4efc55	214	cpu_get_timer(f, env->hstick);
8dd3dca3	215	#endif
00c8cb0a	216	tlb_flush(CPU(cpu), 1);
8dd3dca3 AJ	217	return 0;
8dd3dca3 AJ	218	}