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Common cpu_loop_exit prototype
[mirror_qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
1a2fb1c0 3#include "helper.h"
0828b448
BS		 4#if !defined(CONFIG_USER_ONLY)
5#include "softmmu_exec.h"
6#endif /* !defined(CONFIG_USER_ONLY) */
e8af50a3 7
e80cfcfc 8//#define DEBUG_MMU
952a328f 9//#define DEBUG_MXCC
94554550 10//#define DEBUG_UNALIGNED
6c36d3fa 11//#define DEBUG_UNASSIGNED
8543e2cf 12//#define DEBUG_ASI
d81fd722 13//#define DEBUG_PCALL
e80cfcfc 14
952a328f
BS		 15#ifdef DEBUG_MMU
16#define DPRINTF_MMU(fmt, args...) \
17do { printf("MMU: " fmt , ##args); } while (0)
18#else
22548760 19#define DPRINTF_MMU(fmt, args...) do {} while (0)
952a328f
BS		 20#endif
21
22#ifdef DEBUG_MXCC
23#define DPRINTF_MXCC(fmt, args...) \
24do { printf("MXCC: " fmt , ##args); } while (0)
25#else
22548760 26#define DPRINTF_MXCC(fmt, args...) do {} while (0)
952a328f
BS		 27#endif
28
8543e2cf
BS		 29#ifdef DEBUG_ASI
30#define DPRINTF_ASI(fmt, args...) \
31do { printf("ASI: " fmt , ##args); } while (0)
32#else
22548760 33#define DPRINTF_ASI(fmt, args...) do {} while (0)
8543e2cf
BS		 34#endif
35
2cade6a3
BS		 36#ifdef TARGET_SPARC64
37#ifndef TARGET_ABI32
38#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
c2bc0e38 39#else
2cade6a3
BS		 40#define AM_CHECK(env1) (1)
41#endif
c2bc0e38
BS		 42#endif
43
2cade6a3
BS		 44static inline void address_mask(CPUState *env1, target_ulong *addr)
45{
46#ifdef TARGET_SPARC64
47 if (AM_CHECK(env1))
48 *addr &= 0xffffffffULL;
49#endif
50}
51
9d893301
FB		 52void raise_exception(int tt)
53{
54 env->exception_index = tt;
55 cpu_loop_exit();
3b46e624 56}
9d893301 57
a7812ae4
PB		 58void HELPER(raise_exception)(int tt)
59{
60 raise_exception(tt);
61}
62
91736d37
BS		 63static inline void set_cwp(int new_cwp)
64{
65 cpu_set_cwp(env, new_cwp);
66}
67
2b29924f
BS		 68void helper_check_align(target_ulong addr, uint32_t align)
69{
c2bc0e38
BS		 70 if (addr & align) {
71#ifdef DEBUG_UNALIGNED
72 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
73 "\n", addr, env->pc);
74#endif
2b29924f 75 raise_exception(TT_UNALIGNED);
c2bc0e38 76 }
2b29924f
BS		 77}
78
44e7757c
BS		 79#define F_HELPER(name, p) void helper_f##name##p(void)
80
44e7757c 81#define F_BINOP(name) \
714547bb 82 float32 helper_f ## name ## s (float32 src1, float32 src2) \
44e7757c 83 { \
714547bb 84 return float32_ ## name (src1, src2, &env->fp_status); \
44e7757c
BS		 85 } \
86 F_HELPER(name, d) \
87 { \
88 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
4e14008f
BS		 89 } \
90 F_HELPER(name, q) \
91 { \
92 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44e7757c 93 }
44e7757c
BS		 94
95F_BINOP(add);
96F_BINOP(sub);
97F_BINOP(mul);
98F_BINOP(div);
99#undef F_BINOP
100
d84763bc 101void helper_fsmuld(float32 src1, float32 src2)
1a2fb1c0 102{
d84763bc
BS		 103 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
104 float32_to_float64(src2, &env->fp_status),
44e7757c
BS		 105 &env->fp_status);
106}
1a2fb1c0 107
4e14008f
BS		 108void helper_fdmulq(void)
109{
110 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
111 float64_to_float128(DT1, &env->fp_status),
112 &env->fp_status);
113}
4e14008f 114
714547bb 115float32 helper_fnegs(float32 src)
44e7757c 116{
714547bb 117 return float32_chs(src);
417454b0
BS		 118}
119
44e7757c
BS		 120#ifdef TARGET_SPARC64
121F_HELPER(neg, d)
7e8c2b6c 122{
44e7757c 123 DT0 = float64_chs(DT1);
7e8c2b6c 124}
4e14008f 125
4e14008f
BS		 126F_HELPER(neg, q)
127{
128 QT0 = float128_chs(QT1);
129}
130#endif
44e7757c
BS		 131
132/* Integer to float conversion. */
714547bb 133float32 helper_fitos(int32_t src)
a0c4cb4a 134{
714547bb 135 return int32_to_float32(src, &env->fp_status);
a0c4cb4a
FB		 136}
137
d84763bc 138void helper_fitod(int32_t src)
a0c4cb4a 139{
d84763bc 140 DT0 = int32_to_float64(src, &env->fp_status);
a0c4cb4a 141}
9c2b428e 142
c5d04e99 143void helper_fitoq(int32_t src)
4e14008f 144{
c5d04e99 145 QT0 = int32_to_float128(src, &env->fp_status);
4e14008f 146}
4e14008f 147
1e64e78d 148#ifdef TARGET_SPARC64
d84763bc 149float32 helper_fxtos(void)
1e64e78d 150{
d84763bc 151 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1e64e78d
BS		 152}
153
44e7757c 154F_HELPER(xto, d)
1e64e78d 155{
1e64e78d 156 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1e64e78d 157}
64a88d5d 158
4e14008f
BS		 159F_HELPER(xto, q)
160{
161 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
162}
163#endif
44e7757c
BS		 164#undef F_HELPER
165
166/* floating point conversion */
d84763bc 167float32 helper_fdtos(void)
44e7757c 168{
d84763bc 169 return float64_to_float32(DT1, &env->fp_status);
44e7757c
BS		 170}
171
d84763bc 172void helper_fstod(float32 src)
44e7757c 173{
d84763bc 174 DT0 = float32_to_float64(src, &env->fp_status);
44e7757c 175}
9c2b428e 176
c5d04e99 177float32 helper_fqtos(void)
4e14008f 178{
c5d04e99 179 return float128_to_float32(QT1, &env->fp_status);
4e14008f
BS		 180}
181
c5d04e99 182void helper_fstoq(float32 src)
4e14008f 183{
c5d04e99 184 QT0 = float32_to_float128(src, &env->fp_status);
4e14008f
BS		 185}
186
187void helper_fqtod(void)
188{
189 DT0 = float128_to_float64(QT1, &env->fp_status);
190}
191
192void helper_fdtoq(void)
193{
194 QT0 = float64_to_float128(DT1, &env->fp_status);
195}
4e14008f 196
44e7757c 197/* Float to integer conversion. */
714547bb 198int32_t helper_fstoi(float32 src)
44e7757c 199{
714547bb 200 return float32_to_int32_round_to_zero(src, &env->fp_status);
44e7757c
BS		 201}
202
d84763bc 203int32_t helper_fdtoi(void)
44e7757c 204{
d84763bc 205 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
44e7757c
BS		 206}
207
c5d04e99 208int32_t helper_fqtoi(void)
4e14008f 209{
c5d04e99 210 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
4e14008f 211}
4e14008f 212
44e7757c 213#ifdef TARGET_SPARC64
d84763bc 214void helper_fstox(float32 src)
44e7757c 215{
d84763bc 216 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
44e7757c
BS		 217}
218
219void helper_fdtox(void)
220{
221 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
222}
223
4e14008f
BS		 224void helper_fqtox(void)
225{
226 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
227}
4e14008f 228
44e7757c
BS		 229void helper_faligndata(void)
230{
231 uint64_t tmp;
232
233 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
06057e6f
BS		 234 /* on many architectures a shift of 64 does nothing */
235 if ((env->gsr & 7) != 0) {
236 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
237 }
44e7757c
BS		 238 *((uint64_t *)&DT0) = tmp;
239}
240
44e7757c
BS		 241#ifdef WORDS_BIGENDIAN
242#define VIS_B64(n) b[7 - (n)]
243#define VIS_W64(n) w[3 - (n)]
244#define VIS_SW64(n) sw[3 - (n)]
245#define VIS_L64(n) l[1 - (n)]
246#define VIS_B32(n) b[3 - (n)]
247#define VIS_W32(n) w[1 - (n)]
248#else
249#define VIS_B64(n) b[n]
250#define VIS_W64(n) w[n]
251#define VIS_SW64(n) sw[n]
252#define VIS_L64(n) l[n]
253#define VIS_B32(n) b[n]
254#define VIS_W32(n) w[n]
255#endif
256
257typedef union {
258 uint8_t b[8];
259 uint16_t w[4];
260 int16_t sw[4];
261 uint32_t l[2];
262 float64 d;
263} vis64;
264
265typedef union {
266 uint8_t b[4];
267 uint16_t w[2];
268 uint32_t l;
269 float32 f;
270} vis32;
271
272void helper_fpmerge(void)
273{
274 vis64 s, d;
275
276 s.d = DT0;
277 d.d = DT1;
278
279 // Reverse calculation order to handle overlap
280 d.VIS_B64(7) = s.VIS_B64(3);
281 d.VIS_B64(6) = d.VIS_B64(3);
282 d.VIS_B64(5) = s.VIS_B64(2);
283 d.VIS_B64(4) = d.VIS_B64(2);
284 d.VIS_B64(3) = s.VIS_B64(1);
285 d.VIS_B64(2) = d.VIS_B64(1);
286 d.VIS_B64(1) = s.VIS_B64(0);
287 //d.VIS_B64(0) = d.VIS_B64(0);
288
289 DT0 = d.d;
290}
291
292void helper_fmul8x16(void)
293{
294 vis64 s, d;
295 uint32_t tmp;
296
297 s.d = DT0;
298 d.d = DT1;
299
300#define PMUL(r) \
301 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
302 if ((tmp & 0xff) > 0x7f) \
303 tmp += 0x100; \
304 d.VIS_W64(r) = tmp >> 8;
305
306 PMUL(0);
307 PMUL(1);
308 PMUL(2);
309 PMUL(3);
310#undef PMUL
311
312 DT0 = d.d;
313}
314
315void helper_fmul8x16al(void)
316{
317 vis64 s, d;
318 uint32_t tmp;
319
320 s.d = DT0;
321 d.d = DT1;
322
323#define PMUL(r) \
324 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
325 if ((tmp & 0xff) > 0x7f) \
326 tmp += 0x100; \
327 d.VIS_W64(r) = tmp >> 8;
328
329 PMUL(0);
330 PMUL(1);
331 PMUL(2);
332 PMUL(3);
333#undef PMUL
334
335 DT0 = d.d;
336}
337
338void helper_fmul8x16au(void)
339{
340 vis64 s, d;
341 uint32_t tmp;
342
343 s.d = DT0;
344 d.d = DT1;
345
346#define PMUL(r) \
347 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
348 if ((tmp & 0xff) > 0x7f) \
349 tmp += 0x100; \
350 d.VIS_W64(r) = tmp >> 8;
351
352 PMUL(0);
353 PMUL(1);
354 PMUL(2);
355 PMUL(3);
356#undef PMUL
357
358 DT0 = d.d;
359}
360
361void helper_fmul8sux16(void)
362{
363 vis64 s, d;
364 uint32_t tmp;
365
366 s.d = DT0;
367 d.d = DT1;
368
369#define PMUL(r) \
370 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
371 if ((tmp & 0xff) > 0x7f) \
372 tmp += 0x100; \
373 d.VIS_W64(r) = tmp >> 8;
374
375 PMUL(0);
376 PMUL(1);
377 PMUL(2);
378 PMUL(3);
379#undef PMUL
380
381 DT0 = d.d;
382}
383
384void helper_fmul8ulx16(void)
385{
386 vis64 s, d;
387 uint32_t tmp;
388
389 s.d = DT0;
390 d.d = DT1;
391
392#define PMUL(r) \
393 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
394 if ((tmp & 0xff) > 0x7f) \
395 tmp += 0x100; \
396 d.VIS_W64(r) = tmp >> 8;
397
398 PMUL(0);
399 PMUL(1);
400 PMUL(2);
401 PMUL(3);
402#undef PMUL
403
404 DT0 = d.d;
405}
406
407void helper_fmuld8sux16(void)
408{
409 vis64 s, d;
410 uint32_t tmp;
411
412 s.d = DT0;
413 d.d = DT1;
414
415#define PMUL(r) \
416 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
417 if ((tmp & 0xff) > 0x7f) \
418 tmp += 0x100; \
419 d.VIS_L64(r) = tmp;
420
421 // Reverse calculation order to handle overlap
422 PMUL(1);
423 PMUL(0);
424#undef PMUL
425
426 DT0 = d.d;
427}
428
429void helper_fmuld8ulx16(void)
430{
431 vis64 s, d;
432 uint32_t tmp;
433
434 s.d = DT0;
435 d.d = DT1;
436
437#define PMUL(r) \
438 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
439 if ((tmp & 0xff) > 0x7f) \
440 tmp += 0x100; \
441 d.VIS_L64(r) = tmp;
442
443 // Reverse calculation order to handle overlap
444 PMUL(1);
445 PMUL(0);
446#undef PMUL
447
448 DT0 = d.d;
449}
450
451void helper_fexpand(void)
452{
453 vis32 s;
454 vis64 d;
455
456 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
457 d.d = DT1;
c55bda30
BS		 458 d.VIS_W64(0) = s.VIS_B32(0) << 4;
459 d.VIS_W64(1) = s.VIS_B32(1) << 4;
460 d.VIS_W64(2) = s.VIS_B32(2) << 4;
461 d.VIS_W64(3) = s.VIS_B32(3) << 4;
44e7757c
BS		 462
463 DT0 = d.d;
464}
465
466#define VIS_HELPER(name, F) \
467 void name##16(void) \
468 { \
469 vis64 s, d; \
470 \
471 s.d = DT0; \
472 d.d = DT1; \
473 \
474 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
475 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
476 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
477 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
478 \
479 DT0 = d.d; \
480 } \
481 \
1d01299d 482 uint32_t name##16s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 483 { \
484 vis32 s, d; \
485 \
1d01299d
BS		 486 s.l = src1; \
487 d.l = src2; \
44e7757c
BS		 488 \
489 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
490 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
491 \
1d01299d 492 return d.l; \
44e7757c
BS		 493 } \
494 \
495 void name##32(void) \
496 { \
497 vis64 s, d; \
498 \
499 s.d = DT0; \
500 d.d = DT1; \
501 \
502 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
503 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
504 \
505 DT0 = d.d; \
506 } \
507 \
1d01299d 508 uint32_t name##32s(uint32_t src1, uint32_t src2) \
44e7757c
BS		 509 { \
510 vis32 s, d; \
511 \
1d01299d
BS		 512 s.l = src1; \
513 d.l = src2; \
44e7757c
BS		 514 \
515 d.l = F(d.l, s.l); \
516 \
1d01299d 517 return d.l; \
44e7757c
BS		 518 }
519
520#define FADD(a, b) ((a) + (b))
521#define FSUB(a, b) ((a) - (b))
522VIS_HELPER(helper_fpadd, FADD)
523VIS_HELPER(helper_fpsub, FSUB)
524
525#define VIS_CMPHELPER(name, F) \
526 void name##16(void) \
527 { \
528 vis64 s, d; \
529 \
530 s.d = DT0; \
531 d.d = DT1; \
532 \
533 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
534 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
535 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
536 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
537 \
538 DT0 = d.d; \
539 } \
540 \
541 void name##32(void) \
542 { \
543 vis64 s, d; \
544 \
545 s.d = DT0; \
546 d.d = DT1; \
547 \
548 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
549 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
550 \
551 DT0 = d.d; \
552 }
553
554#define FCMPGT(a, b) ((a) > (b))
555#define FCMPEQ(a, b) ((a) == (b))
556#define FCMPLE(a, b) ((a) <= (b))
557#define FCMPNE(a, b) ((a) != (b))
558
559VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
560VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
561VIS_CMPHELPER(helper_fcmple, FCMPLE)
562VIS_CMPHELPER(helper_fcmpne, FCMPNE)
563#endif
564
565void helper_check_ieee_exceptions(void)
566{
567 target_ulong status;
568
569 status = get_float_exception_flags(&env->fp_status);
570 if (status) {
571 /* Copy IEEE 754 flags into FSR */
572 if (status & float_flag_invalid)
573 env->fsr |= FSR_NVC;
574 if (status & float_flag_overflow)
575 env->fsr |= FSR_OFC;
576 if (status & float_flag_underflow)
577 env->fsr |= FSR_UFC;
578 if (status & float_flag_divbyzero)
579 env->fsr |= FSR_DZC;
580 if (status & float_flag_inexact)
581 env->fsr |= FSR_NXC;
582
583 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
584 /* Unmasked exception, generate a trap */
585 env->fsr |= FSR_FTT_IEEE_EXCP;
586 raise_exception(TT_FP_EXCP);
587 } else {
588 /* Accumulate exceptions */
589 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
590 }
591 }
592}
593
594void helper_clear_float_exceptions(void)
595{
596 set_float_exception_flags(0, &env->fp_status);
597}
598
714547bb 599float32 helper_fabss(float32 src)
e8af50a3 600{
714547bb 601 return float32_abs(src);
e8af50a3
FB		 602}
603
3475187d 604#ifdef TARGET_SPARC64
7e8c2b6c 605void helper_fabsd(void)
3475187d
FB		 606{
607 DT0 = float64_abs(DT1);
608}
4e14008f 609
4e14008f
BS		 610void helper_fabsq(void)
611{
612 QT0 = float128_abs(QT1);
613}
614#endif
3475187d 615
714547bb 616float32 helper_fsqrts(float32 src)
e8af50a3 617{
714547bb 618 return float32_sqrt(src, &env->fp_status);
e8af50a3
FB		 619}
620
7e8c2b6c 621void helper_fsqrtd(void)
e8af50a3 622{
7a0e1f41 623 DT0 = float64_sqrt(DT1, &env->fp_status);
e8af50a3
FB		 624}
625
4e14008f
BS		 626void helper_fsqrtq(void)
627{
628 QT0 = float128_sqrt(QT1, &env->fp_status);
629}
4e14008f 630
417454b0 631#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
7e8c2b6c 632 void glue(helper_, name) (void) \
65ce8c2f 633 { \
1a2fb1c0
BS		 634 target_ulong new_fsr; \
635 \
65ce8c2f
FB		 636 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
637 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
638 case float_relation_unordered: \
1a2fb1c0 639 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 640 if ((env->fsr & FSR_NVM) || TRAP) { \
1a2fb1c0 641 env->fsr |= new_fsr; \
417454b0
BS		 642 env->fsr |= FSR_NVC; \
643 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 644 raise_exception(TT_FP_EXCP); \
645 } else { \
646 env->fsr |= FSR_NVA; \
647 } \
648 break; \
649 case float_relation_less: \
1a2fb1c0 650 new_fsr = FSR_FCC0 << FS; \
65ce8c2f
FB		 651 break; \
652 case float_relation_greater: \
1a2fb1c0 653 new_fsr = FSR_FCC1 << FS; \
65ce8c2f
FB		 654 break; \
655 default: \
1a2fb1c0 656 new_fsr = 0; \
65ce8c2f
FB		 657 break; \
658 } \
1a2fb1c0 659 env->fsr |= new_fsr; \
e8af50a3 660 }
714547bb
BS		 661#define GEN_FCMPS(name, size, FS, TRAP) \
662 void glue(helper_, name)(float32 src1, float32 src2) \
663 { \
664 target_ulong new_fsr; \
665 \
666 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
667 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
668 case float_relation_unordered: \
669 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
670 if ((env->fsr & FSR_NVM) || TRAP) { \
671 env->fsr |= new_fsr; \
672 env->fsr |= FSR_NVC; \
673 env->fsr |= FSR_FTT_IEEE_EXCP; \
674 raise_exception(TT_FP_EXCP); \
675 } else { \
676 env->fsr |= FSR_NVA; \
677 } \
678 break; \
679 case float_relation_less: \
680 new_fsr = FSR_FCC0 << FS; \
681 break; \
682 case float_relation_greater: \
683 new_fsr = FSR_FCC1 << FS; \
684 break; \
685 default: \
686 new_fsr = 0; \
687 break; \
688 } \
689 env->fsr |= new_fsr; \
690 }
e8af50a3 691
714547bb 692GEN_FCMPS(fcmps, float32, 0, 0);
417454b0
BS		 693GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
694
714547bb 695GEN_FCMPS(fcmpes, float32, 0, 1);
417454b0 696GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 697
4e14008f
BS		 698GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
699GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
4e14008f 700
3475187d 701#ifdef TARGET_SPARC64
714547bb 702GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
417454b0 703GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
64a88d5d 704GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
417454b0 705
714547bb 706GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
417454b0 707GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
64a88d5d 708GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
417454b0 709
714547bb 710GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
417454b0 711GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
64a88d5d 712GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
417454b0 713
714547bb 714GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
417454b0 715GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
64a88d5d 716GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
3475187d 717
714547bb 718GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
417454b0 719GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
64a88d5d 720GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
3475187d 721
714547bb 722GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
417454b0 723GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
4e14008f
BS		 724GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
725#endif
714547bb 726#undef GEN_FCMPS
3475187d 727
77f193da
BS		 728#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
729 defined(DEBUG_MXCC)
952a328f
BS		 730static void dump_mxcc(CPUState *env)
731{
732 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
77f193da
BS		 733 env->mxccdata[0], env->mxccdata[1],
734 env->mxccdata[2], env->mxccdata[3]);
952a328f
BS		 735 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
736 " %016llx %016llx %016llx %016llx\n",
77f193da
BS		 737 env->mxccregs[0], env->mxccregs[1],
738 env->mxccregs[2], env->mxccregs[3],
739 env->mxccregs[4], env->mxccregs[5],
740 env->mxccregs[6], env->mxccregs[7]);
952a328f
BS		 741}
742#endif
743
1a2fb1c0
BS		 744#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
745 && defined(DEBUG_ASI)
746static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
747 uint64_t r1)
8543e2cf
BS		 748{
749 switch (size)
750 {
751 case 1:
1a2fb1c0
BS		 752 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
753 addr, asi, r1 & 0xff);
8543e2cf
BS		 754 break;
755 case 2:
1a2fb1c0
BS		 756 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
757 addr, asi, r1 & 0xffff);
8543e2cf
BS		 758 break;
759 case 4:
1a2fb1c0
BS		 760 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
761 addr, asi, r1 & 0xffffffff);
8543e2cf
BS		 762 break;
763 case 8:
1a2fb1c0
BS		 764 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
765 addr, asi, r1);
8543e2cf
BS		 766 break;
767 }
768}
769#endif
770
1a2fb1c0
BS		 771#ifndef TARGET_SPARC64
772#ifndef CONFIG_USER_ONLY
773uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
e8af50a3 774{
1a2fb1c0 775 uint64_t ret = 0;
8543e2cf 776#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1a2fb1c0 777 uint32_t last_addr = addr;
952a328f 778#endif
e80cfcfc 779
c2bc0e38 780 helper_check_align(addr, size - 1);
e80cfcfc 781 switch (asi) {
6c36d3fa 782 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 783 switch (addr) {
952a328f 784 case 0x01c00a00: /* MXCC control register */
1a2fb1c0
BS		 785 if (size == 8)
786 ret = env->mxccregs[3];
787 else
77f193da
BS		 788 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
789 size);
952a328f
BS		 790 break;
791 case 0x01c00a04: /* MXCC control register */
792 if (size == 4)
793 ret = env->mxccregs[3];
794 else
77f193da
BS		 795 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
796 size);
952a328f 797 break;
295db113
BS		 798 case 0x01c00c00: /* Module reset register */
799 if (size == 8) {
1a2fb1c0 800 ret = env->mxccregs[5];
295db113
BS		 801 // should we do something here?
802 } else
77f193da
BS		 803 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
804 size);
295db113 805 break;
952a328f 806 case 0x01c00f00: /* MBus port address register */
1a2fb1c0
BS		 807 if (size == 8)
808 ret = env->mxccregs[7];
809 else
77f193da
BS		 810 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
811 size);
952a328f
BS		 812 break;
813 default:
77f193da
BS		 814 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
815 size);
952a328f
BS		 816 break;
817 }
77f193da 818 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
9827e450 819 "addr = %08x -> ret = %" PRIx64 ","
1a2fb1c0 820 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
952a328f
BS		 821#ifdef DEBUG_MXCC
822 dump_mxcc(env);
823#endif
6c36d3fa 824 break;
e8af50a3 825 case 3: /* MMU probe */
0f8a249a
BS		 826 {
827 int mmulev;
828
1a2fb1c0 829 mmulev = (addr >> 8) & 15;
0f8a249a
BS		 830 if (mmulev > 4)
831 ret = 0;
1a2fb1c0
BS		 832 else
833 ret = mmu_probe(env, addr, mmulev);
834 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
835 addr, mmulev, ret);
0f8a249a
BS		 836 }
837 break;
e8af50a3 838 case 4: /* read MMU regs */
0f8a249a 839 {
1a2fb1c0 840 int reg = (addr >> 8) & 0x1f;
3b46e624 841
0f8a249a
BS		 842 ret = env->mmuregs[reg];
843 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 844 env->mmuregs[3] = 0;
845 else if (reg == 0x13) /* Fault status read */
846 ret = env->mmuregs[3];
847 else if (reg == 0x14) /* Fault address read */
848 ret = env->mmuregs[4];
1a2fb1c0 849 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
0f8a249a
BS		 850 }
851 break;
045380be
BS		 852 case 5: // Turbosparc ITLB Diagnostic
853 case 6: // Turbosparc DTLB Diagnostic
854 case 7: // Turbosparc IOTLB Diagnostic
855 break;
6c36d3fa
BS		 856 case 9: /* Supervisor code access */
857 switch(size) {
858 case 1:
1a2fb1c0 859 ret = ldub_code(addr);
6c36d3fa
BS		 860 break;
861 case 2:
a4e7dd52 862 ret = lduw_code(addr);
6c36d3fa
BS		 863 break;
864 default:
865 case 4:
a4e7dd52 866 ret = ldl_code(addr);
6c36d3fa
BS		 867 break;
868 case 8:
a4e7dd52 869 ret = ldq_code(addr);
6c36d3fa
BS		 870 break;
871 }
872 break;
81ad8ba2
BS		 873 case 0xa: /* User data access */
874 switch(size) {
875 case 1:
1a2fb1c0 876 ret = ldub_user(addr);
81ad8ba2
BS		 877 break;
878 case 2:
a4e7dd52 879 ret = lduw_user(addr);
81ad8ba2
BS		 880 break;
881 default:
882 case 4:
a4e7dd52 883 ret = ldl_user(addr);
81ad8ba2
BS		 884 break;
885 case 8:
a4e7dd52 886 ret = ldq_user(addr);
81ad8ba2
BS		 887 break;
888 }
889 break;
890 case 0xb: /* Supervisor data access */
891 switch(size) {
892 case 1:
1a2fb1c0 893 ret = ldub_kernel(addr);
81ad8ba2
BS		 894 break;
895 case 2:
a4e7dd52 896 ret = lduw_kernel(addr);
81ad8ba2
BS		 897 break;
898 default:
899 case 4:
a4e7dd52 900 ret = ldl_kernel(addr);
81ad8ba2
BS		 901 break;
902 case 8:
a4e7dd52 903 ret = ldq_kernel(addr);
81ad8ba2
BS		 904 break;
905 }
906 break;
6c36d3fa
BS		 907 case 0xc: /* I-cache tag */
908 case 0xd: /* I-cache data */
909 case 0xe: /* D-cache tag */
910 case 0xf: /* D-cache data */
911 break;
912 case 0x20: /* MMU passthrough */
02aab46a
FB		 913 switch(size) {
914 case 1:
1a2fb1c0 915 ret = ldub_phys(addr);
02aab46a
FB		 916 break;
917 case 2:
a4e7dd52 918 ret = lduw_phys(addr);
02aab46a
FB		 919 break;
920 default:
921 case 4:
a4e7dd52 922 ret = ldl_phys(addr);
02aab46a 923 break;
9e61bde5 924 case 8:
a4e7dd52 925 ret = ldq_phys(addr);
0f8a249a 926 break;
02aab46a 927 }
0f8a249a 928 break;
7d85892b 929 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
5dcb6b91
BS		 930 switch(size) {
931 case 1:
1a2fb1c0 932 ret = ldub_phys((target_phys_addr_t)addr
5dcb6b91
BS		 933 | ((target_phys_addr_t)(asi & 0xf) << 32));
934 break;
935 case 2:
a4e7dd52 936 ret = lduw_phys((target_phys_addr_t)addr
5dcb6b91
BS		 937 | ((target_phys_addr_t)(asi & 0xf) << 32));
938 break;
939 default:
940 case 4:
a4e7dd52 941 ret = ldl_phys((target_phys_addr_t)addr
5dcb6b91
BS		 942 | ((target_phys_addr_t)(asi & 0xf) << 32));
943 break;
944 case 8:
a4e7dd52 945 ret = ldq_phys((target_phys_addr_t)addr
5dcb6b91 946 | ((target_phys_addr_t)(asi & 0xf) << 32));
0f8a249a 947 break;
5dcb6b91 948 }
0f8a249a 949 break;
045380be
BS		 950 case 0x30: // Turbosparc secondary cache diagnostic
951 case 0x31: // Turbosparc RAM snoop
952 case 0x32: // Turbosparc page table descriptor diagnostic
666c87aa
BS		 953 case 0x39: /* data cache diagnostic register */
954 ret = 0;
955 break;
045380be 956 case 8: /* User code access, XXX */
e8af50a3 957 default:
e18231a3 958 do_unassigned_access(addr, 0, 0, asi, size);
0f8a249a
BS		 959 ret = 0;
960 break;
e8af50a3 961 }
81ad8ba2
BS		 962 if (sign) {
963 switch(size) {
964 case 1:
1a2fb1c0 965 ret = (int8_t) ret;
e32664fb 966 break;
81ad8ba2 967 case 2:
1a2fb1c0
BS		 968 ret = (int16_t) ret;
969 break;
970 case 4:
971 ret = (int32_t) ret;
e32664fb 972 break;
81ad8ba2 973 default:
81ad8ba2
BS		 974 break;
975 }
976 }
8543e2cf 977#ifdef DEBUG_ASI
1a2fb1c0 978 dump_asi("read ", last_addr, asi, size, ret);
8543e2cf 979#endif
1a2fb1c0 980 return ret;
e8af50a3
FB		 981}
982
1a2fb1c0 983void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
e8af50a3 984{
c2bc0e38 985 helper_check_align(addr, size - 1);
e8af50a3 986 switch(asi) {
6c36d3fa 987 case 2: /* SuperSparc MXCC registers */
1a2fb1c0 988 switch (addr) {
952a328f
BS		 989 case 0x01c00000: /* MXCC stream data register 0 */
990 if (size == 8)
1a2fb1c0 991 env->mxccdata[0] = val;
952a328f 992 else
77f193da
BS		 993 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
994 size);
952a328f
BS		 995 break;
996 case 0x01c00008: /* MXCC stream data register 1 */
997 if (size == 8)
1a2fb1c0 998 env->mxccdata[1] = val;
952a328f 999 else
77f193da
BS		 1000 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1001 size);
952a328f
BS		 1002 break;
1003 case 0x01c00010: /* MXCC stream data register 2 */
1004 if (size == 8)
1a2fb1c0 1005 env->mxccdata[2] = val;
952a328f 1006 else
77f193da
BS		 1007 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1008 size);
952a328f
BS		 1009 break;
1010 case 0x01c00018: /* MXCC stream data register 3 */
1011 if (size == 8)
1a2fb1c0 1012 env->mxccdata[3] = val;
952a328f 1013 else
77f193da
BS		 1014 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1015 size);
952a328f
BS		 1016 break;
1017 case 0x01c00100: /* MXCC stream source */
1018 if (size == 8)
1a2fb1c0 1019 env->mxccregs[0] = val;
952a328f 1020 else
77f193da
BS		 1021 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1022 size);
1023 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1024 0);
1025 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1026 8);
1027 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1028 16);
1029 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1030 24);
952a328f
BS		 1031 break;
1032 case 0x01c00200: /* MXCC stream destination */
1033 if (size == 8)
1a2fb1c0 1034 env->mxccregs[1] = val;
952a328f 1035 else
77f193da
BS		 1036 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1037 size);
1038 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1039 env->mxccdata[0]);
1040 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1041 env->mxccdata[1]);
1042 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1043 env->mxccdata[2]);
1044 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1045 env->mxccdata[3]);
952a328f
BS		 1046 break;
1047 case 0x01c00a00: /* MXCC control register */
1048 if (size == 8)
1a2fb1c0 1049 env->mxccregs[3] = val;
952a328f 1050 else
77f193da
BS		 1051 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1052 size);
952a328f
BS		 1053 break;
1054 case 0x01c00a04: /* MXCC control register */
1055 if (size == 4)
9f4576f0 1056 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
77f193da 1057 | val;
952a328f 1058 else
77f193da
BS		 1059 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1060 size);
952a328f
BS		 1061 break;
1062 case 0x01c00e00: /* MXCC error register */
bbf7d96b 1063 // writing a 1 bit clears the error
952a328f 1064 if (size == 8)
1a2fb1c0 1065 env->mxccregs[6] &= ~val;
952a328f 1066 else
77f193da
BS		 1067 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1068 size);
952a328f
BS		 1069 break;
1070 case 0x01c00f00: /* MBus port address register */
1071 if (size == 8)
1a2fb1c0 1072 env->mxccregs[7] = val;
952a328f 1073 else
77f193da
BS		 1074 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1075 size);
952a328f
BS		 1076 break;
1077 default:
77f193da
BS		 1078 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1079 size);
952a328f
BS		 1080 break;
1081 }
9827e450
BS		 1082 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1083 asi, size, addr, val);
952a328f
BS		 1084#ifdef DEBUG_MXCC
1085 dump_mxcc(env);
1086#endif
6c36d3fa 1087 break;
e8af50a3 1088 case 3: /* MMU flush */
0f8a249a
BS		 1089 {
1090 int mmulev;
e80cfcfc 1091
1a2fb1c0 1092 mmulev = (addr >> 8) & 15;
952a328f 1093 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 1094 switch (mmulev) {
1095 case 0: // flush page
1a2fb1c0 1096 tlb_flush_page(env, addr & 0xfffff000);
0f8a249a
BS		 1097 break;
1098 case 1: // flush segment (256k)
1099 case 2: // flush region (16M)
1100 case 3: // flush context (4G)
1101 case 4: // flush entire
1102 tlb_flush(env, 1);
1103 break;
1104 default:
1105 break;
1106 }
55754d9e 1107#ifdef DEBUG_MMU
0f8a249a 1108 dump_mmu(env);
55754d9e 1109#endif
0f8a249a 1110 }
8543e2cf 1111 break;
e8af50a3 1112 case 4: /* write MMU regs */
0f8a249a 1113 {
1a2fb1c0 1114 int reg = (addr >> 8) & 0x1f;
0f8a249a 1115 uint32_t oldreg;
3b46e624 1116
0f8a249a 1117 oldreg = env->mmuregs[reg];
55754d9e 1118 switch(reg) {
3deaeab7 1119 case 0: // Control Register
3dd9a152 1120 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1a2fb1c0 1121 (val & 0x00ffffff);
0f8a249a
BS		 1122 // Mappings generated during no-fault mode or MMU
1123 // disabled mode are invalid in normal mode
5578ceab
BS		 1124 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1125 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
55754d9e
FB		 1126 tlb_flush(env, 1);
1127 break;
3deaeab7 1128 case 1: // Context Table Pointer Register
5578ceab 1129 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
3deaeab7
BS		 1130 break;
1131 case 2: // Context Register
5578ceab 1132 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
55754d9e
FB		 1133 if (oldreg != env->mmuregs[reg]) {
1134 /* we flush when the MMU context changes because
1135 QEMU has no MMU context support */
1136 tlb_flush(env, 1);
1137 }
1138 break;
3deaeab7
BS		 1139 case 3: // Synchronous Fault Status Register with Clear
1140 case 4: // Synchronous Fault Address Register
1141 break;
1142 case 0x10: // TLB Replacement Control Register
5578ceab 1143 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
55754d9e 1144 break;
3deaeab7 1145 case 0x13: // Synchronous Fault Status Register with Read and Clear
5578ceab 1146 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
3dd9a152 1147 break;
3deaeab7 1148 case 0x14: // Synchronous Fault Address Register
1a2fb1c0 1149 env->mmuregs[4] = val;
3dd9a152 1150 break;
55754d9e 1151 default:
1a2fb1c0 1152 env->mmuregs[reg] = val;
55754d9e
FB		 1153 break;
1154 }
55754d9e 1155 if (oldreg != env->mmuregs[reg]) {
77f193da
BS		 1156 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1157 reg, oldreg, env->mmuregs[reg]);
55754d9e 1158 }
952a328f 1159#ifdef DEBUG_MMU
0f8a249a 1160 dump_mmu(env);
55754d9e 1161#endif
0f8a249a 1162 }
8543e2cf 1163 break;
045380be
BS		 1164 case 5: // Turbosparc ITLB Diagnostic
1165 case 6: // Turbosparc DTLB Diagnostic
1166 case 7: // Turbosparc IOTLB Diagnostic
1167 break;
81ad8ba2
BS		 1168 case 0xa: /* User data access */
1169 switch(size) {
1170 case 1:
1a2fb1c0 1171 stb_user(addr, val);
81ad8ba2
BS		 1172 break;
1173 case 2:
a4e7dd52 1174 stw_user(addr, val);
81ad8ba2
BS		 1175 break;
1176 default:
1177 case 4:
a4e7dd52 1178 stl_user(addr, val);
81ad8ba2
BS		 1179 break;
1180 case 8:
a4e7dd52 1181 stq_user(addr, val);
81ad8ba2
BS		 1182 break;
1183 }
1184 break;
1185 case 0xb: /* Supervisor data access */
1186 switch(size) {
1187 case 1:
1a2fb1c0 1188 stb_kernel(addr, val);
81ad8ba2
BS		 1189 break;
1190 case 2:
a4e7dd52 1191 stw_kernel(addr, val);
81ad8ba2
BS		 1192 break;
1193 default:
1194 case 4:
a4e7dd52 1195 stl_kernel(addr, val);
81ad8ba2
BS		 1196 break;
1197 case 8:
a4e7dd52 1198 stq_kernel(addr, val);
81ad8ba2
BS		 1199 break;
1200 }
1201 break;
6c36d3fa
BS		 1202 case 0xc: /* I-cache tag */
1203 case 0xd: /* I-cache data */
1204 case 0xe: /* D-cache tag */
1205 case 0xf: /* D-cache data */
1206 case 0x10: /* I/D-cache flush page */
1207 case 0x11: /* I/D-cache flush segment */
1208 case 0x12: /* I/D-cache flush region */
1209 case 0x13: /* I/D-cache flush context */
1210 case 0x14: /* I/D-cache flush user */
1211 break;
e80cfcfc 1212 case 0x17: /* Block copy, sta access */
0f8a249a 1213 {
1a2fb1c0
BS		 1214 // val = src
1215 // addr = dst
0f8a249a 1216 // copy 32 bytes
6c36d3fa 1217 unsigned int i;
1a2fb1c0 1218 uint32_t src = val & ~3, dst = addr & ~3, temp;
3b46e624 1219
6c36d3fa
BS		 1220 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1221 temp = ldl_kernel(src);
1222 stl_kernel(dst, temp);
1223 }
0f8a249a 1224 }
8543e2cf 1225 break;
e80cfcfc 1226 case 0x1f: /* Block fill, stda access */
0f8a249a 1227 {
1a2fb1c0
BS		 1228 // addr = dst
1229 // fill 32 bytes with val
6c36d3fa 1230 unsigned int i;
1a2fb1c0 1231 uint32_t dst = addr & 7;
6c36d3fa
BS		 1232
1233 for (i = 0; i < 32; i += 8, dst += 8)
1234 stq_kernel(dst, val);
0f8a249a 1235 }
8543e2cf 1236 break;
6c36d3fa 1237 case 0x20: /* MMU passthrough */
0f8a249a 1238 {
02aab46a
FB		 1239 switch(size) {
1240 case 1:
1a2fb1c0 1241 stb_phys(addr, val);
02aab46a
FB		 1242 break;
1243 case 2:
a4e7dd52 1244 stw_phys(addr, val);
02aab46a
FB		 1245 break;
1246 case 4:
1247 default:
a4e7dd52 1248 stl_phys(addr, val);
02aab46a 1249 break;
9e61bde5 1250 case 8:
a4e7dd52 1251 stq_phys(addr, val);
9e61bde5 1252 break;
02aab46a 1253 }
0f8a249a 1254 }
8543e2cf 1255 break;
045380be 1256 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
0f8a249a 1257 {
5dcb6b91
BS		 1258 switch(size) {
1259 case 1:
1a2fb1c0
BS		 1260 stb_phys((target_phys_addr_t)addr
1261 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1262 break;
1263 case 2:
a4e7dd52 1264 stw_phys((target_phys_addr_t)addr
1a2fb1c0 1265 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1266 break;
1267 case 4:
1268 default:
a4e7dd52 1269 stl_phys((target_phys_addr_t)addr
1a2fb1c0 1270 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1271 break;
1272 case 8:
a4e7dd52 1273 stq_phys((target_phys_addr_t)addr
1a2fb1c0 1274 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
5dcb6b91
BS		 1275 break;
1276 }
0f8a249a 1277 }
8543e2cf 1278 break;
045380be
BS		 1279 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1280 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1281 // Turbosparc snoop RAM
77f193da
BS		 1282 case 0x32: // store buffer control or Turbosparc page table
1283 // descriptor diagnostic
6c36d3fa
BS		 1284 case 0x36: /* I-cache flash clear */
1285 case 0x37: /* D-cache flash clear */
666c87aa
BS		 1286 case 0x38: /* breakpoint diagnostics */
1287 case 0x4c: /* breakpoint action */
6c36d3fa 1288 break;
045380be 1289 case 8: /* User code access, XXX */
6c36d3fa 1290 case 9: /* Supervisor code access, XXX */
e8af50a3 1291 default:
e18231a3 1292 do_unassigned_access(addr, 1, 0, asi, size);
8543e2cf 1293 break;
e8af50a3 1294 }
8543e2cf 1295#ifdef DEBUG_ASI
1a2fb1c0 1296 dump_asi("write", addr, asi, size, val);
8543e2cf 1297#endif
e8af50a3
FB		 1298}
1299
81ad8ba2
BS		 1300#endif /* CONFIG_USER_ONLY */
1301#else /* TARGET_SPARC64 */
1302
1303#ifdef CONFIG_USER_ONLY
1a2fb1c0 1304uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
81ad8ba2
BS		 1305{
1306 uint64_t ret = 0;
1a2fb1c0
BS		 1307#if defined(DEBUG_ASI)
1308 target_ulong last_addr = addr;
1309#endif
81ad8ba2
BS		 1310
1311 if (asi < 0x80)
1312 raise_exception(TT_PRIV_ACT);
1313
c2bc0e38 1314 helper_check_align(addr, size - 1);
2cade6a3 1315 address_mask(env, &addr);
c2bc0e38 1316
81ad8ba2 1317 switch (asi) {
81ad8ba2 1318 case 0x82: // Primary no-fault
81ad8ba2 1319 case 0x8a: // Primary no-fault LE
e83ce550
BS		 1320 if (page_check_range(addr, size, PAGE_READ) == -1) {
1321#ifdef DEBUG_ASI
1322 dump_asi("read ", last_addr, asi, size, ret);
1323#endif
1324 return 0;
1325 }
1326 // Fall through
1327 case 0x80: // Primary
1328 case 0x88: // Primary LE
81ad8ba2
BS		 1329 {
1330 switch(size) {
1331 case 1:
1a2fb1c0 1332 ret = ldub_raw(addr);
81ad8ba2
BS		 1333 break;
1334 case 2:
a4e7dd52 1335 ret = lduw_raw(addr);
81ad8ba2
BS		 1336 break;
1337 case 4:
a4e7dd52 1338 ret = ldl_raw(addr);
81ad8ba2
BS		 1339 break;
1340 default:
1341 case 8:
a4e7dd52 1342 ret = ldq_raw(addr);
81ad8ba2
BS		 1343 break;
1344 }
1345 }
1346 break;
81ad8ba2 1347 case 0x83: // Secondary no-fault
81ad8ba2 1348 case 0x8b: // Secondary no-fault LE
e83ce550
BS		 1349 if (page_check_range(addr, size, PAGE_READ) == -1) {
1350#ifdef DEBUG_ASI
1351 dump_asi("read ", last_addr, asi, size, ret);
1352#endif
1353 return 0;
1354 }
1355 // Fall through
1356 case 0x81: // Secondary
1357 case 0x89: // Secondary LE
81ad8ba2
BS		 1358 // XXX
1359 break;
1360 default:
1361 break;
1362 }
1363
1364 /* Convert from little endian */
1365 switch (asi) {
1366 case 0x88: // Primary LE
1367 case 0x89: // Secondary LE
1368 case 0x8a: // Primary no-fault LE
1369 case 0x8b: // Secondary no-fault LE
1370 switch(size) {
1371 case 2:
1372 ret = bswap16(ret);
e32664fb 1373 break;
81ad8ba2
BS		 1374 case 4:
1375 ret = bswap32(ret);
e32664fb 1376 break;
81ad8ba2
BS		 1377 case 8:
1378 ret = bswap64(ret);
e32664fb 1379 break;
81ad8ba2
BS		 1380 default:
1381 break;
1382 }
1383 default:
1384 break;
1385 }
1386
1387 /* Convert to signed number */
1388 if (sign) {
1389 switch(size) {
1390 case 1:
1391 ret = (int8_t) ret;
e32664fb 1392 break;
81ad8ba2
BS		 1393 case 2:
1394 ret = (int16_t) ret;
e32664fb 1395 break;
81ad8ba2
BS		 1396 case 4:
1397 ret = (int32_t) ret;
e32664fb 1398 break;
81ad8ba2
BS		 1399 default:
1400 break;
1401 }
1402 }
1a2fb1c0
BS		 1403#ifdef DEBUG_ASI
1404 dump_asi("read ", last_addr, asi, size, ret);
1405#endif
1406 return ret;
81ad8ba2
BS		 1407}
1408
1a2fb1c0 1409void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
81ad8ba2 1410{
1a2fb1c0
BS		 1411#ifdef DEBUG_ASI
1412 dump_asi("write", addr, asi, size, val);
1413#endif
81ad8ba2
BS		 1414 if (asi < 0x80)
1415 raise_exception(TT_PRIV_ACT);
1416
c2bc0e38 1417 helper_check_align(addr, size - 1);
2cade6a3 1418 address_mask(env, &addr);
c2bc0e38 1419
81ad8ba2
BS		 1420 /* Convert to little endian */
1421 switch (asi) {
1422 case 0x88: // Primary LE
1423 case 0x89: // Secondary LE
1424 switch(size) {
1425 case 2:
1a2fb1c0 1426 addr = bswap16(addr);
e32664fb 1427 break;
81ad8ba2 1428 case 4:
1a2fb1c0 1429 addr = bswap32(addr);
e32664fb 1430 break;
81ad8ba2 1431 case 8:
1a2fb1c0 1432 addr = bswap64(addr);
e32664fb 1433 break;
81ad8ba2
BS		 1434 default:
1435 break;
1436 }
1437 default:
1438 break;
1439 }
1440
1441 switch(asi) {
1442 case 0x80: // Primary
1443 case 0x88: // Primary LE
1444 {
1445 switch(size) {
1446 case 1:
1a2fb1c0 1447 stb_raw(addr, val);
81ad8ba2
BS		 1448 break;
1449 case 2:
a4e7dd52 1450 stw_raw(addr, val);
81ad8ba2
BS		 1451 break;
1452 case 4:
a4e7dd52 1453 stl_raw(addr, val);
81ad8ba2
BS		 1454 break;
1455 case 8:
1456 default:
a4e7dd52 1457 stq_raw(addr, val);
81ad8ba2
BS		 1458 break;
1459 }
1460 }
1461 break;
1462 case 0x81: // Secondary
1463 case 0x89: // Secondary LE
1464 // XXX
1465 return;
1466
1467 case 0x82: // Primary no-fault, RO
1468 case 0x83: // Secondary no-fault, RO
1469 case 0x8a: // Primary no-fault LE, RO
1470 case 0x8b: // Secondary no-fault LE, RO
1471 default:
e18231a3 1472 do_unassigned_access(addr, 1, 0, 1, size);
81ad8ba2
BS		 1473 return;
1474 }
1475}
1476
1477#else /* CONFIG_USER_ONLY */
3475187d 1478
1a2fb1c0 1479uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
3475187d 1480{
83469015 1481 uint64_t ret = 0;
1a2fb1c0
BS		 1482#if defined(DEBUG_ASI)
1483 target_ulong last_addr = addr;
1484#endif
3475187d 1485
6f27aba6 1486 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 1487 || ((env->def->features & CPU_FEATURE_HYPV)
1488 && asi >= 0x30 && asi < 0x80
fb79ceb9 1489 && !(env->hpstate & HS_PRIV)))
0f8a249a 1490 raise_exception(TT_PRIV_ACT);
3475187d 1491
c2bc0e38 1492 helper_check_align(addr, size - 1);
3475187d 1493 switch (asi) {
e83ce550
BS		 1494 case 0x82: // Primary no-fault
1495 case 0x8a: // Primary no-fault LE
1496 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1497#ifdef DEBUG_ASI
1498 dump_asi("read ", last_addr, asi, size, ret);
1499#endif
1500 return 0;
1501 }
1502 // Fall through
81ad8ba2
BS		 1503 case 0x10: // As if user primary
1504 case 0x18: // As if user primary LE
1505 case 0x80: // Primary
81ad8ba2 1506 case 0x88: // Primary LE
c99657d3
BS		 1507 case 0xe2: // UA2007 Primary block init
1508 case 0xe3: // UA2007 Secondary block init
81ad8ba2 1509 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
5578ceab
BS		 1510 if ((env->def->features & CPU_FEATURE_HYPV)
1511 && env->hpstate & HS_PRIV) {
6f27aba6
BS		 1512 switch(size) {
1513 case 1:
1a2fb1c0 1514 ret = ldub_hypv(addr);
6f27aba6
BS		 1515 break;
1516 case 2:
a4e7dd52 1517 ret = lduw_hypv(addr);
6f27aba6
BS		 1518 break;
1519 case 4:
a4e7dd52 1520 ret = ldl_hypv(addr);
6f27aba6
BS		 1521 break;
1522 default:
1523 case 8:
a4e7dd52 1524 ret = ldq_hypv(addr);
6f27aba6
BS		 1525 break;
1526 }
1527 } else {
1528 switch(size) {
1529 case 1:
1a2fb1c0 1530 ret = ldub_kernel(addr);
6f27aba6
BS		 1531 break;
1532 case 2:
a4e7dd52 1533 ret = lduw_kernel(addr);
6f27aba6
BS		 1534 break;
1535 case 4:
a4e7dd52 1536 ret = ldl_kernel(addr);
6f27aba6
BS		 1537 break;
1538 default:
1539 case 8:
a4e7dd52 1540 ret = ldq_kernel(addr);
6f27aba6
BS		 1541 break;
1542 }
81ad8ba2
BS		 1543 }
1544 } else {
1545 switch(size) {
1546 case 1:
1a2fb1c0 1547 ret = ldub_user(addr);
81ad8ba2
BS		 1548 break;
1549 case 2:
a4e7dd52 1550 ret = lduw_user(addr);
81ad8ba2
BS		 1551 break;
1552 case 4:
a4e7dd52 1553 ret = ldl_user(addr);
81ad8ba2
BS		 1554 break;
1555 default:
1556 case 8:
a4e7dd52 1557 ret = ldq_user(addr);
81ad8ba2
BS		 1558 break;
1559 }
1560 }
1561 break;
3475187d
FB		 1562 case 0x14: // Bypass
1563 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1564 case 0x1c: // Bypass LE
1565 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1566 {
02aab46a
FB		 1567 switch(size) {
1568 case 1:
1a2fb1c0 1569 ret = ldub_phys(addr);
02aab46a
FB		 1570 break;
1571 case 2:
a4e7dd52 1572 ret = lduw_phys(addr);
02aab46a
FB		 1573 break;
1574 case 4:
a4e7dd52 1575 ret = ldl_phys(addr);
02aab46a
FB		 1576 break;
1577 default:
1578 case 8:
a4e7dd52 1579 ret = ldq_phys(addr);
02aab46a
FB		 1580 break;
1581 }
0f8a249a
BS		 1582 break;
1583 }
db166940
BS		 1584 case 0x24: // Nucleus quad LDD 128 bit atomic
1585 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1586 // Only ldda allowed
1587 raise_exception(TT_ILL_INSN);
1588 return 0;
e83ce550
BS		 1589 case 0x83: // Secondary no-fault
1590 case 0x8b: // Secondary no-fault LE
1591 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1592#ifdef DEBUG_ASI
1593 dump_asi("read ", last_addr, asi, size, ret);
1594#endif
1595 return 0;
1596 }
1597 // Fall through
83469015
FB		 1598 case 0x04: // Nucleus
1599 case 0x0c: // Nucleus Little Endian (LE)
83469015 1600 case 0x11: // As if user secondary
83469015 1601 case 0x19: // As if user secondary LE
83469015 1602 case 0x4a: // UPA config
81ad8ba2 1603 case 0x81: // Secondary
83469015 1604 case 0x89: // Secondary LE
0f8a249a
BS		 1605 // XXX
1606 break;
3475187d 1607 case 0x45: // LSU
0f8a249a
BS		 1608 ret = env->lsu;
1609 break;
3475187d 1610 case 0x50: // I-MMU regs
0f8a249a 1611 {
1a2fb1c0 1612 int reg = (addr >> 3) & 0xf;
3475187d 1613
0f8a249a
BS		 1614 ret = env->immuregs[reg];
1615 break;
1616 }
3475187d
FB		 1617 case 0x51: // I-MMU 8k TSB pointer
1618 case 0x52: // I-MMU 64k TSB pointer
0f8a249a
BS		 1619 // XXX
1620 break;
a5a52cf2
BS		 1621 case 0x55: // I-MMU data access
1622 {
1623 int reg = (addr >> 3) & 0x3f;
1624
1625 ret = env->itlb_tte[reg];
1626 break;
1627 }
83469015 1628 case 0x56: // I-MMU tag read
0f8a249a 1629 {
43e9e742 1630 int reg = (addr >> 3) & 0x3f;
0f8a249a 1631
43e9e742 1632 ret = env->itlb_tag[reg];
0f8a249a
BS		 1633 break;
1634 }
3475187d 1635 case 0x58: // D-MMU regs
0f8a249a 1636 {
1a2fb1c0 1637 int reg = (addr >> 3) & 0xf;
3475187d 1638
0f8a249a
BS		 1639 ret = env->dmmuregs[reg];
1640 break;
1641 }
a5a52cf2
BS		 1642 case 0x5d: // D-MMU data access
1643 {
1644 int reg = (addr >> 3) & 0x3f;
1645
1646 ret = env->dtlb_tte[reg];
1647 break;
1648 }
83469015 1649 case 0x5e: // D-MMU tag read
0f8a249a 1650 {
43e9e742 1651 int reg = (addr >> 3) & 0x3f;
0f8a249a 1652
43e9e742 1653 ret = env->dtlb_tag[reg];
0f8a249a
BS		 1654 break;
1655 }
f7350b47
BS		 1656 case 0x46: // D-cache data
1657 case 0x47: // D-cache tag access
a5a52cf2
BS		 1658 case 0x4b: // E-cache error enable
1659 case 0x4c: // E-cache asynchronous fault status
1660 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 1661 case 0x4e: // E-cache tag data
1662 case 0x66: // I-cache instruction access
1663 case 0x67: // I-cache tag access
1664 case 0x6e: // I-cache predecode
1665 case 0x6f: // I-cache LRU etc.
1666 case 0x76: // E-cache tag
1667 case 0x7e: // E-cache tag
1668 break;
3475187d
FB		 1669 case 0x59: // D-MMU 8k TSB pointer
1670 case 0x5a: // D-MMU 64k TSB pointer
1671 case 0x5b: // D-MMU data pointer
83469015
FB		 1672 case 0x48: // Interrupt dispatch, RO
1673 case 0x49: // Interrupt data receive
1674 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1675 // XXX
1676 break;
3475187d
FB		 1677 case 0x54: // I-MMU data in, WO
1678 case 0x57: // I-MMU demap, WO
1679 case 0x5c: // D-MMU data in, WO
1680 case 0x5f: // D-MMU demap, WO
83469015 1681 case 0x77: // Interrupt vector, WO
3475187d 1682 default:
e18231a3 1683 do_unassigned_access(addr, 0, 0, 1, size);
0f8a249a
BS		 1684 ret = 0;
1685 break;
3475187d 1686 }
81ad8ba2
BS		 1687
1688 /* Convert from little endian */
1689 switch (asi) {
1690 case 0x0c: // Nucleus Little Endian (LE)
1691 case 0x18: // As if user primary LE
1692 case 0x19: // As if user secondary LE
1693 case 0x1c: // Bypass LE
1694 case 0x1d: // Bypass, non-cacheable LE
1695 case 0x88: // Primary LE
1696 case 0x89: // Secondary LE
1697 case 0x8a: // Primary no-fault LE
1698 case 0x8b: // Secondary no-fault LE
1699 switch(size) {
1700 case 2:
1701 ret = bswap16(ret);
e32664fb 1702 break;
81ad8ba2
BS		 1703 case 4:
1704 ret = bswap32(ret);
e32664fb 1705 break;
81ad8ba2
BS		 1706 case 8:
1707 ret = bswap64(ret);
e32664fb 1708 break;
81ad8ba2
BS		 1709 default:
1710 break;
1711 }
1712 default:
1713 break;
1714 }
1715
1716 /* Convert to signed number */
1717 if (sign) {
1718 switch(size) {
1719 case 1:
1720 ret = (int8_t) ret;
e32664fb 1721 break;
81ad8ba2
BS		 1722 case 2:
1723 ret = (int16_t) ret;
e32664fb 1724 break;
81ad8ba2
BS		 1725 case 4:
1726 ret = (int32_t) ret;
e32664fb 1727 break;
81ad8ba2
BS		 1728 default:
1729 break;
1730 }
1731 }
1a2fb1c0
BS		 1732#ifdef DEBUG_ASI
1733 dump_asi("read ", last_addr, asi, size, ret);
1734#endif
1735 return ret;
3475187d
FB		 1736}
1737
1a2fb1c0 1738void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
3475187d 1739{
1a2fb1c0
BS		 1740#ifdef DEBUG_ASI
1741 dump_asi("write", addr, asi, size, val);
1742#endif
6f27aba6 1743 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 1744 || ((env->def->features & CPU_FEATURE_HYPV)
1745 && asi >= 0x30 && asi < 0x80
fb79ceb9 1746 && !(env->hpstate & HS_PRIV)))
0f8a249a 1747 raise_exception(TT_PRIV_ACT);
3475187d 1748
c2bc0e38 1749 helper_check_align(addr, size - 1);
81ad8ba2
BS		 1750 /* Convert to little endian */
1751 switch (asi) {
1752 case 0x0c: // Nucleus Little Endian (LE)
1753 case 0x18: // As if user primary LE
1754 case 0x19: // As if user secondary LE
1755 case 0x1c: // Bypass LE
1756 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1757 case 0x88: // Primary LE
1758 case 0x89: // Secondary LE
1759 switch(size) {
1760 case 2:
1a2fb1c0 1761 addr = bswap16(addr);
e32664fb 1762 break;
81ad8ba2 1763 case 4:
1a2fb1c0 1764 addr = bswap32(addr);
e32664fb 1765 break;
81ad8ba2 1766 case 8:
1a2fb1c0 1767 addr = bswap64(addr);
e32664fb 1768 break;
81ad8ba2
BS		 1769 default:
1770 break;
1771 }
1772 default:
1773 break;
1774 }
1775
3475187d 1776 switch(asi) {
81ad8ba2
BS		 1777 case 0x10: // As if user primary
1778 case 0x18: // As if user primary LE
1779 case 0x80: // Primary
1780 case 0x88: // Primary LE
c99657d3
BS		 1781 case 0xe2: // UA2007 Primary block init
1782 case 0xe3: // UA2007 Secondary block init
81ad8ba2 1783 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
5578ceab
BS		 1784 if ((env->def->features & CPU_FEATURE_HYPV)
1785 && env->hpstate & HS_PRIV) {
6f27aba6
BS		 1786 switch(size) {
1787 case 1:
1a2fb1c0 1788 stb_hypv(addr, val);
6f27aba6
BS		 1789 break;
1790 case 2:
a4e7dd52 1791 stw_hypv(addr, val);
6f27aba6
BS		 1792 break;
1793 case 4:
a4e7dd52 1794 stl_hypv(addr, val);
6f27aba6
BS		 1795 break;
1796 case 8:
1797 default:
a4e7dd52 1798 stq_hypv(addr, val);
6f27aba6
BS		 1799 break;
1800 }
1801 } else {
1802 switch(size) {
1803 case 1:
1a2fb1c0 1804 stb_kernel(addr, val);
6f27aba6
BS		 1805 break;
1806 case 2:
a4e7dd52 1807 stw_kernel(addr, val);
6f27aba6
BS		 1808 break;
1809 case 4:
a4e7dd52 1810 stl_kernel(addr, val);
6f27aba6
BS		 1811 break;
1812 case 8:
1813 default:
a4e7dd52 1814 stq_kernel(addr, val);
6f27aba6
BS		 1815 break;
1816 }
81ad8ba2
BS		 1817 }
1818 } else {
1819 switch(size) {
1820 case 1:
1a2fb1c0 1821 stb_user(addr, val);
81ad8ba2
BS		 1822 break;
1823 case 2:
a4e7dd52 1824 stw_user(addr, val);
81ad8ba2
BS		 1825 break;
1826 case 4:
a4e7dd52 1827 stl_user(addr, val);
81ad8ba2
BS		 1828 break;
1829 case 8:
1830 default:
a4e7dd52 1831 stq_user(addr, val);
81ad8ba2
BS		 1832 break;
1833 }
1834 }
1835 break;
3475187d
FB		 1836 case 0x14: // Bypass
1837 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1838 case 0x1c: // Bypass LE
1839 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1840 {
02aab46a
FB		 1841 switch(size) {
1842 case 1:
1a2fb1c0 1843 stb_phys(addr, val);
02aab46a
FB		 1844 break;
1845 case 2:
a4e7dd52 1846 stw_phys(addr, val);
02aab46a
FB		 1847 break;
1848 case 4:
a4e7dd52 1849 stl_phys(addr, val);
02aab46a
FB		 1850 break;
1851 case 8:
1852 default:
a4e7dd52 1853 stq_phys(addr, val);
02aab46a
FB		 1854 break;
1855 }
0f8a249a
BS		 1856 }
1857 return;
db166940
BS		 1858 case 0x24: // Nucleus quad LDD 128 bit atomic
1859 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1860 // Only ldda allowed
1861 raise_exception(TT_ILL_INSN);
1862 return;
83469015
FB		 1863 case 0x04: // Nucleus
1864 case 0x0c: // Nucleus Little Endian (LE)
83469015 1865 case 0x11: // As if user secondary
83469015 1866 case 0x19: // As if user secondary LE
83469015 1867 case 0x4a: // UPA config
51996525 1868 case 0x81: // Secondary
83469015 1869 case 0x89: // Secondary LE
0f8a249a
BS		 1870 // XXX
1871 return;
3475187d 1872 case 0x45: // LSU
0f8a249a
BS		 1873 {
1874 uint64_t oldreg;
1875
1876 oldreg = env->lsu;
1a2fb1c0 1877 env->lsu = val & (DMMU_E | IMMU_E);
0f8a249a
BS		 1878 // Mappings generated during D/I MMU disabled mode are
1879 // invalid in normal mode
1880 if (oldreg != env->lsu) {
77f193da
BS		 1881 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1882 oldreg, env->lsu);
83469015 1883#ifdef DEBUG_MMU
0f8a249a 1884 dump_mmu(env);
83469015 1885#endif
0f8a249a
BS		 1886 tlb_flush(env, 1);
1887 }
1888 return;
1889 }
3475187d 1890 case 0x50: // I-MMU regs
0f8a249a 1891 {
1a2fb1c0 1892 int reg = (addr >> 3) & 0xf;
0f8a249a 1893 uint64_t oldreg;
3b46e624 1894
0f8a249a 1895 oldreg = env->immuregs[reg];
3475187d
FB		 1896 switch(reg) {
1897 case 0: // RO
1898 case 4:
1899 return;
1900 case 1: // Not in I-MMU
1901 case 2:
1902 case 7:
1903 case 8:
1904 return;
1905 case 3: // SFSR
1a2fb1c0
BS		 1906 if ((val & 1) == 0)
1907 val = 0; // Clear SFSR
3475187d
FB		 1908 break;
1909 case 5: // TSB access
1910 case 6: // Tag access
1911 default:
1912 break;
1913 }
1a2fb1c0 1914 env->immuregs[reg] = val;
3475187d 1915 if (oldreg != env->immuregs[reg]) {
77f193da
BS		 1916 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
1917 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1918 }
952a328f 1919#ifdef DEBUG_MMU
0f8a249a 1920 dump_mmu(env);
3475187d 1921#endif
0f8a249a
BS		 1922 return;
1923 }
3475187d 1924 case 0x54: // I-MMU data in
0f8a249a
BS		 1925 {
1926 unsigned int i;
1927
1928 // Try finding an invalid entry
1929 for (i = 0; i < 64; i++) {
1930 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1931 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1932 env->itlb_tte[i] = val;
0f8a249a
BS		 1933 return;
1934 }
1935 }
1936 // Try finding an unlocked entry
1937 for (i = 0; i < 64; i++) {
1938 if ((env->itlb_tte[i] & 0x40) == 0) {
1939 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1940 env->itlb_tte[i] = val;
0f8a249a
BS		 1941 return;
1942 }
1943 }
1944 // error state?
1945 return;
1946 }
3475187d 1947 case 0x55: // I-MMU data access
0f8a249a 1948 {
cc6747f4
BS		 1949 // TODO: auto demap
1950
1a2fb1c0 1951 unsigned int i = (addr >> 3) & 0x3f;
3475187d 1952
0f8a249a 1953 env->itlb_tag[i] = env->immuregs[6];
1a2fb1c0 1954 env->itlb_tte[i] = val;
0f8a249a
BS		 1955 return;
1956 }
3475187d 1957 case 0x57: // I-MMU demap
cc6747f4
BS		 1958 {
1959 unsigned int i;
1960
1961 for (i = 0; i < 64; i++) {
1962 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
1963 target_ulong mask = 0xffffffffffffe000ULL;
1964
1965 mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
1966 if ((val & mask) == (env->itlb_tag[i] & mask)) {
1967 env->itlb_tag[i] = 0;
1968 env->itlb_tte[i] = 0;
1969 }
1970 return;
1971 }
1972 }
1973 }
0f8a249a 1974 return;
3475187d 1975 case 0x58: // D-MMU regs
0f8a249a 1976 {
1a2fb1c0 1977 int reg = (addr >> 3) & 0xf;
0f8a249a 1978 uint64_t oldreg;
3b46e624 1979
0f8a249a 1980 oldreg = env->dmmuregs[reg];
3475187d
FB		 1981 switch(reg) {
1982 case 0: // RO
1983 case 4:
1984 return;
1985 case 3: // SFSR
1a2fb1c0
BS		 1986 if ((val & 1) == 0) {
1987 val = 0; // Clear SFSR, Fault address
0f8a249a
BS		 1988 env->dmmuregs[4] = 0;
1989 }
1a2fb1c0 1990 env->dmmuregs[reg] = val;
3475187d
FB		 1991 break;
1992 case 1: // Primary context
1993 case 2: // Secondary context
1994 case 5: // TSB access
1995 case 6: // Tag access
1996 case 7: // Virtual Watchpoint
1997 case 8: // Physical Watchpoint
1998 default:
1999 break;
2000 }
1a2fb1c0 2001 env->dmmuregs[reg] = val;
3475187d 2002 if (oldreg != env->dmmuregs[reg]) {
77f193da
BS		 2003 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
2004 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 2005 }
952a328f 2006#ifdef DEBUG_MMU
0f8a249a 2007 dump_mmu(env);
3475187d 2008#endif
0f8a249a
BS		 2009 return;
2010 }
3475187d 2011 case 0x5c: // D-MMU data in
0f8a249a
BS		 2012 {
2013 unsigned int i;
2014
2015 // Try finding an invalid entry
2016 for (i = 0; i < 64; i++) {
2017 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
2018 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2019 env->dtlb_tte[i] = val;
0f8a249a
BS		 2020 return;
2021 }
2022 }
2023 // Try finding an unlocked entry
2024 for (i = 0; i < 64; i++) {
2025 if ((env->dtlb_tte[i] & 0x40) == 0) {
2026 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2027 env->dtlb_tte[i] = val;
0f8a249a
BS		 2028 return;
2029 }
2030 }
2031 // error state?
2032 return;
2033 }
3475187d 2034 case 0x5d: // D-MMU data access
0f8a249a 2035 {
1a2fb1c0 2036 unsigned int i = (addr >> 3) & 0x3f;
3475187d 2037
0f8a249a 2038 env->dtlb_tag[i] = env->dmmuregs[6];
1a2fb1c0 2039 env->dtlb_tte[i] = val;
0f8a249a
BS		 2040 return;
2041 }
3475187d 2042 case 0x5f: // D-MMU demap
cc6747f4
BS		 2043 {
2044 unsigned int i;
2045
2046 for (i = 0; i < 64; i++) {
2047 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
2048 target_ulong mask = 0xffffffffffffe000ULL;
2049
2050 mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
2051 if ((val & mask) == (env->dtlb_tag[i] & mask)) {
2052 env->dtlb_tag[i] = 0;
2053 env->dtlb_tte[i] = 0;
2054 }
2055 return;
2056 }
2057 }
2058 }
2059 return;
83469015 2060 case 0x49: // Interrupt data receive
0f8a249a
BS		 2061 // XXX
2062 return;
f7350b47
BS		 2063 case 0x46: // D-cache data
2064 case 0x47: // D-cache tag access
a5a52cf2
BS		 2065 case 0x4b: // E-cache error enable
2066 case 0x4c: // E-cache asynchronous fault status
2067 case 0x4d: // E-cache asynchronous fault address
f7350b47
BS		 2068 case 0x4e: // E-cache tag data
2069 case 0x66: // I-cache instruction access
2070 case 0x67: // I-cache tag access
2071 case 0x6e: // I-cache predecode
2072 case 0x6f: // I-cache LRU etc.
2073 case 0x76: // E-cache tag
2074 case 0x7e: // E-cache tag
2075 return;
3475187d
FB		 2076 case 0x51: // I-MMU 8k TSB pointer, RO
2077 case 0x52: // I-MMU 64k TSB pointer, RO
2078 case 0x56: // I-MMU tag read, RO
2079 case 0x59: // D-MMU 8k TSB pointer, RO
2080 case 0x5a: // D-MMU 64k TSB pointer, RO
2081 case 0x5b: // D-MMU data pointer, RO
2082 case 0x5e: // D-MMU tag read, RO
83469015
FB		 2083 case 0x48: // Interrupt dispatch, RO
2084 case 0x7f: // Incoming interrupt vector, RO
2085 case 0x82: // Primary no-fault, RO
2086 case 0x83: // Secondary no-fault, RO
2087 case 0x8a: // Primary no-fault LE, RO
2088 case 0x8b: // Secondary no-fault LE, RO
3475187d 2089 default:
e18231a3 2090 do_unassigned_access(addr, 1, 0, 1, size);
0f8a249a 2091 return;
3475187d
FB		 2092 }
2093}
81ad8ba2 2094#endif /* CONFIG_USER_ONLY */
3391c818 2095
db166940
BS		 2096void helper_ldda_asi(target_ulong addr, int asi, int rd)
2097{
db166940 2098 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
5578ceab
BS		 2099 || ((env->def->features & CPU_FEATURE_HYPV)
2100 && asi >= 0x30 && asi < 0x80
fb79ceb9 2101 && !(env->hpstate & HS_PRIV)))
db166940
BS		 2102 raise_exception(TT_PRIV_ACT);
2103
2104 switch (asi) {
2105 case 0x24: // Nucleus quad LDD 128 bit atomic
2106 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2107 helper_check_align(addr, 0xf);
2108 if (rd == 0) {
2109 env->gregs[1] = ldq_kernel(addr + 8);
2110 if (asi == 0x2c)
2111 bswap64s(&env->gregs[1]);
2112 } else if (rd < 8) {
2113 env->gregs[rd] = ldq_kernel(addr);
2114 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2115 if (asi == 0x2c) {
2116 bswap64s(&env->gregs[rd]);
2117 bswap64s(&env->gregs[rd + 1]);
2118 }
2119 } else {
2120 env->regwptr[rd] = ldq_kernel(addr);
2121 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2122 if (asi == 0x2c) {
2123 bswap64s(&env->regwptr[rd]);
2124 bswap64s(&env->regwptr[rd + 1]);
2125 }
2126 }
2127 break;
2128 default:
2129 helper_check_align(addr, 0x3);
2130 if (rd == 0)
2131 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2132 else if (rd < 8) {
2133 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2134 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2135 } else {
2136 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2137 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2138 }
2139 break;
2140 }
2141}
2142
1a2fb1c0 2143void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2144{
3391c818 2145 unsigned int i;
1a2fb1c0 2146 target_ulong val;
3391c818 2147
c2bc0e38 2148 helper_check_align(addr, 3);
3391c818
BS		 2149 switch (asi) {
2150 case 0xf0: // Block load primary
2151 case 0xf1: // Block load secondary
2152 case 0xf8: // Block load primary LE
2153 case 0xf9: // Block load secondary LE
51996525
BS		 2154 if (rd & 7) {
2155 raise_exception(TT_ILL_INSN);
2156 return;
2157 }
c2bc0e38 2158 helper_check_align(addr, 0x3f);
51996525 2159 for (i = 0; i < 16; i++) {
77f193da
BS		 2160 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2161 0);
1a2fb1c0 2162 addr += 4;
3391c818 2163 }
3391c818
BS		 2164
2165 return;
2166 default:
2167 break;
2168 }
2169
1a2fb1c0 2170 val = helper_ld_asi(addr, asi, size, 0);
3391c818
BS		 2171 switch(size) {
2172 default:
2173 case 4:
714547bb 2174 *((uint32_t *)&env->fpr[rd]) = val;
3391c818
BS		 2175 break;
2176 case 8:
1a2fb1c0 2177 *((int64_t *)&DT0) = val;
3391c818 2178 break;
1f587329
BS		 2179 case 16:
2180 // XXX
2181 break;
3391c818 2182 }
3391c818
BS		 2183}
2184
1a2fb1c0 2185void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
3391c818 2186{
3391c818 2187 unsigned int i;
1a2fb1c0 2188 target_ulong val = 0;
3391c818 2189
c2bc0e38 2190 helper_check_align(addr, 3);
3391c818 2191 switch (asi) {
c99657d3
BS		 2192 case 0xe0: // UA2007 Block commit store primary (cache flush)
2193 case 0xe1: // UA2007 Block commit store secondary (cache flush)
3391c818
BS		 2194 case 0xf0: // Block store primary
2195 case 0xf1: // Block store secondary
2196 case 0xf8: // Block store primary LE
2197 case 0xf9: // Block store secondary LE
51996525
BS		 2198 if (rd & 7) {
2199 raise_exception(TT_ILL_INSN);
2200 return;
2201 }
c2bc0e38 2202 helper_check_align(addr, 0x3f);
51996525 2203 for (i = 0; i < 16; i++) {
1a2fb1c0
BS		 2204 val = *(uint32_t *)&env->fpr[rd++];
2205 helper_st_asi(addr, val, asi & 0x8f, 4);
2206 addr += 4;
3391c818 2207 }
3391c818
BS		 2208
2209 return;
2210 default:
2211 break;
2212 }
2213
2214 switch(size) {
2215 default:
2216 case 4:
714547bb 2217 val = *((uint32_t *)&env->fpr[rd]);
3391c818
BS		 2218 break;
2219 case 8:
1a2fb1c0 2220 val = *((int64_t *)&DT0);
3391c818 2221 break;
1f587329
BS		 2222 case 16:
2223 // XXX
2224 break;
3391c818 2225 }
1a2fb1c0
BS		 2226 helper_st_asi(addr, val, asi, size);
2227}
2228
2229target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2230 target_ulong val2, uint32_t asi)
2231{
2232 target_ulong ret;
2233
1121f879 2234 val2 &= 0xffffffffUL;
1a2fb1c0
BS		 2235 ret = helper_ld_asi(addr, asi, 4, 0);
2236 ret &= 0xffffffffUL;
1121f879
BS		 2237 if (val2 == ret)
2238 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
1a2fb1c0 2239 return ret;
3391c818
BS		 2240}
2241
1a2fb1c0
BS		 2242target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2243 target_ulong val2, uint32_t asi)
2244{
2245 target_ulong ret;
2246
2247 ret = helper_ld_asi(addr, asi, 8, 0);
1121f879
BS		 2248 if (val2 == ret)
2249 helper_st_asi(addr, val1, asi, 8);
1a2fb1c0
BS		 2250 return ret;
2251}
81ad8ba2 2252#endif /* TARGET_SPARC64 */
3475187d
FB		 2253
2254#ifndef TARGET_SPARC64
1a2fb1c0 2255void helper_rett(void)
e8af50a3 2256{
af7bf89b
FB		 2257 unsigned int cwp;
2258
d4218d99
BS		 2259 if (env->psret == 1)
2260 raise_exception(TT_ILL_INSN);
2261
e8af50a3 2262 env->psret = 1;
1a14026e 2263 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
e8af50a3
FB		 2264 if (env->wim & (1 << cwp)) {
2265 raise_exception(TT_WIN_UNF);
2266 }
2267 set_cwp(cwp);
2268 env->psrs = env->psrps;
2269}
3475187d 2270#endif
e8af50a3 2271
3b89f26c
BS		 2272target_ulong helper_udiv(target_ulong a, target_ulong b)
2273{
2274 uint64_t x0;
2275 uint32_t x1;
2276
7621a90d 2277 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3b89f26c
BS		 2278 x1 = b;
2279
2280 if (x1 == 0) {
2281 raise_exception(TT_DIV_ZERO);
2282 }
2283
2284 x0 = x0 / x1;
2285 if (x0 > 0xffffffff) {
2286 env->cc_src2 = 1;
2287 return 0xffffffff;
2288 } else {
2289 env->cc_src2 = 0;
2290 return x0;
2291 }
2292}
2293
2294target_ulong helper_sdiv(target_ulong a, target_ulong b)
2295{
2296 int64_t x0;
2297 int32_t x1;
2298
7621a90d 2299 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
3b89f26c
BS		 2300 x1 = b;
2301
2302 if (x1 == 0) {
2303 raise_exception(TT_DIV_ZERO);
2304 }
2305
2306 x0 = x0 / x1;
2307 if ((int32_t) x0 != x0) {
2308 env->cc_src2 = 1;
2309 return x0 < 0? 0x80000000: 0x7fffffff;
2310 } else {
2311 env->cc_src2 = 0;
2312 return x0;
2313 }
2314}
2315
7fa76c0b
BS		 2316void helper_stdf(target_ulong addr, int mem_idx)
2317{
c2bc0e38 2318 helper_check_align(addr, 7);
7fa76c0b
BS		 2319#if !defined(CONFIG_USER_ONLY)
2320 switch (mem_idx) {
2321 case 0:
c2bc0e38 2322 stfq_user(addr, DT0);
7fa76c0b
BS		 2323 break;
2324 case 1:
c2bc0e38 2325 stfq_kernel(addr, DT0);
7fa76c0b
BS		 2326 break;
2327#ifdef TARGET_SPARC64
2328 case 2:
c2bc0e38 2329 stfq_hypv(addr, DT0);
7fa76c0b
BS		 2330 break;
2331#endif
2332 default:
2333 break;
2334 }
2335#else
2cade6a3 2336 address_mask(env, &addr);
c2bc0e38 2337 stfq_raw(addr, DT0);
7fa76c0b
BS		 2338#endif
2339}
2340
2341void helper_lddf(target_ulong addr, int mem_idx)
2342{
c2bc0e38 2343 helper_check_align(addr, 7);
7fa76c0b
BS		 2344#if !defined(CONFIG_USER_ONLY)
2345 switch (mem_idx) {
2346 case 0:
c2bc0e38 2347 DT0 = ldfq_user(addr);
7fa76c0b
BS		 2348 break;
2349 case 1:
c2bc0e38 2350 DT0 = ldfq_kernel(addr);
7fa76c0b
BS		 2351 break;
2352#ifdef TARGET_SPARC64
2353 case 2:
c2bc0e38 2354 DT0 = ldfq_hypv(addr);
7fa76c0b
BS		 2355 break;
2356#endif
2357 default:
2358 break;
2359 }
2360#else
2cade6a3 2361 address_mask(env, &addr);
c2bc0e38 2362 DT0 = ldfq_raw(addr);
7fa76c0b
BS		 2363#endif
2364}
2365
64a88d5d 2366void helper_ldqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 2367{
2368 // XXX add 128 bit load
2369 CPU_QuadU u;
2370
c2bc0e38 2371 helper_check_align(addr, 7);
64a88d5d
BS		 2372#if !defined(CONFIG_USER_ONLY)
2373 switch (mem_idx) {
2374 case 0:
c2bc0e38
BS		 2375 u.ll.upper = ldq_user(addr);
2376 u.ll.lower = ldq_user(addr + 8);
64a88d5d
BS		 2377 QT0 = u.q;
2378 break;
2379 case 1:
c2bc0e38
BS		 2380 u.ll.upper = ldq_kernel(addr);
2381 u.ll.lower = ldq_kernel(addr + 8);
64a88d5d
BS		 2382 QT0 = u.q;
2383 break;
2384#ifdef TARGET_SPARC64
2385 case 2:
c2bc0e38
BS		 2386 u.ll.upper = ldq_hypv(addr);
2387 u.ll.lower = ldq_hypv(addr + 8);
64a88d5d
BS		 2388 QT0 = u.q;
2389 break;
2390#endif
2391 default:
2392 break;
2393 }
2394#else
2cade6a3 2395 address_mask(env, &addr);
c2bc0e38
BS		 2396 u.ll.upper = ldq_raw(addr);
2397 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
7fa76c0b 2398 QT0 = u.q;
64a88d5d 2399#endif
7fa76c0b
BS		 2400}
2401
64a88d5d 2402void helper_stqf(target_ulong addr, int mem_idx)
7fa76c0b
BS		 2403{
2404 // XXX add 128 bit store
2405 CPU_QuadU u;
2406
c2bc0e38 2407 helper_check_align(addr, 7);
64a88d5d
BS		 2408#if !defined(CONFIG_USER_ONLY)
2409 switch (mem_idx) {
2410 case 0:
2411 u.q = QT0;
c2bc0e38
BS		 2412 stq_user(addr, u.ll.upper);
2413 stq_user(addr + 8, u.ll.lower);
64a88d5d
BS		 2414 break;
2415 case 1:
2416 u.q = QT0;
c2bc0e38
BS		 2417 stq_kernel(addr, u.ll.upper);
2418 stq_kernel(addr + 8, u.ll.lower);
64a88d5d
BS		 2419 break;
2420#ifdef TARGET_SPARC64
2421 case 2:
2422 u.q = QT0;
c2bc0e38
BS		 2423 stq_hypv(addr, u.ll.upper);
2424 stq_hypv(addr + 8, u.ll.lower);
64a88d5d
BS		 2425 break;
2426#endif
2427 default:
2428 break;
2429 }
2430#else
7fa76c0b 2431 u.q = QT0;
2cade6a3 2432 address_mask(env, &addr);
c2bc0e38
BS		 2433 stq_raw(addr, u.ll.upper);
2434 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
7fa76c0b 2435#endif
64a88d5d 2436}
7fa76c0b 2437
3a3b925d 2438static inline void set_fsr(void)
e8af50a3 2439{
7a0e1f41 2440 int rnd_mode;
bb5529bb 2441
e8af50a3
FB		 2442 switch (env->fsr & FSR_RD_MASK) {
2443 case FSR_RD_NEAREST:
7a0e1f41 2444 rnd_mode = float_round_nearest_even;
0f8a249a 2445 break;
ed910241 2446 default:
e8af50a3 2447 case FSR_RD_ZERO:
7a0e1f41 2448 rnd_mode = float_round_to_zero;
0f8a249a 2449 break;
e8af50a3 2450 case FSR_RD_POS:
7a0e1f41 2451 rnd_mode = float_round_up;
0f8a249a 2452 break;
e8af50a3 2453 case FSR_RD_NEG:
7a0e1f41 2454 rnd_mode = float_round_down;
0f8a249a 2455 break;
e8af50a3 2456 }
7a0e1f41 2457 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 2458}
e80cfcfc 2459
3a3b925d 2460void helper_ldfsr(uint32_t new_fsr)
bb5529bb 2461{
3a3b925d
BS		 2462 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
2463 set_fsr();
bb5529bb
BS		 2464}
2465
3a3b925d
BS		 2466#ifdef TARGET_SPARC64
2467void helper_ldxfsr(uint64_t new_fsr)
2468{
2469 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
2470 set_fsr();
2471}
2472#endif
2473
bb5529bb 2474void helper_debug(void)
e80cfcfc
FB		 2475{
2476 env->exception_index = EXCP_DEBUG;
2477 cpu_loop_exit();
2478}
af7bf89b 2479
3475187d 2480#ifndef TARGET_SPARC64
72a9747b
BS		 2481/* XXX: use another pointer for %iN registers to avoid slow wrapping
2482 handling ? */
2483void helper_save(void)
2484{
2485 uint32_t cwp;
2486
1a14026e 2487 cwp = cpu_cwp_dec(env, env->cwp - 1);
72a9747b
BS		 2488 if (env->wim & (1 << cwp)) {
2489 raise_exception(TT_WIN_OVF);
2490 }
2491 set_cwp(cwp);
2492}
2493
2494void helper_restore(void)
2495{
2496 uint32_t cwp;
2497
1a14026e 2498 cwp = cpu_cwp_inc(env, env->cwp + 1);
72a9747b
BS		 2499 if (env->wim & (1 << cwp)) {
2500 raise_exception(TT_WIN_UNF);
2501 }
2502 set_cwp(cwp);
2503}
2504
1a2fb1c0 2505void helper_wrpsr(target_ulong new_psr)
af7bf89b 2506{
1a14026e 2507 if ((new_psr & PSR_CWP) >= env->nwindows)
d4218d99
BS		 2508 raise_exception(TT_ILL_INSN);
2509 else
1a2fb1c0 2510 PUT_PSR(env, new_psr);
af7bf89b
FB		 2511}
2512
1a2fb1c0 2513target_ulong helper_rdpsr(void)
af7bf89b 2514{
1a2fb1c0 2515 return GET_PSR(env);
af7bf89b 2516}
3475187d
FB		 2517
2518#else
72a9747b
BS		 2519/* XXX: use another pointer for %iN registers to avoid slow wrapping
2520 handling ? */
2521void helper_save(void)
2522{
2523 uint32_t cwp;
2524
1a14026e 2525 cwp = cpu_cwp_dec(env, env->cwp - 1);
72a9747b
BS		 2526 if (env->cansave == 0) {
2527 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2528 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2529 ((env->wstate & 0x7) << 2)));
2530 } else {
2531 if (env->cleanwin - env->canrestore == 0) {
2532 // XXX Clean windows without trap
2533 raise_exception(TT_CLRWIN);
2534 } else {
2535 env->cansave--;
2536 env->canrestore++;
2537 set_cwp(cwp);
2538 }
2539 }
2540}
2541
2542void helper_restore(void)
2543{
2544 uint32_t cwp;
2545
1a14026e 2546 cwp = cpu_cwp_inc(env, env->cwp + 1);
72a9747b
BS		 2547 if (env->canrestore == 0) {
2548 raise_exception(TT_FILL | (env->otherwin != 0 ?
2549 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2550 ((env->wstate & 0x7) << 2)));
2551 } else {
2552 env->cansave++;
2553 env->canrestore--;
2554 set_cwp(cwp);
2555 }
2556}
2557
2558void helper_flushw(void)
2559{
1a14026e 2560 if (env->cansave != env->nwindows - 2) {
72a9747b
BS		 2561 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2562 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2563 ((env->wstate & 0x7) << 2)));
2564 }
2565}
2566
2567void helper_saved(void)
2568{
2569 env->cansave++;
2570 if (env->otherwin == 0)
2571 env->canrestore--;
2572 else
2573 env->otherwin--;
2574}
2575
2576void helper_restored(void)
2577{
2578 env->canrestore++;
1a14026e 2579 if (env->cleanwin < env->nwindows - 1)
72a9747b
BS		 2580 env->cleanwin++;
2581 if (env->otherwin == 0)
2582 env->cansave--;
2583 else
2584 env->otherwin--;
2585}
2586
d35527d9
BS		 2587target_ulong helper_rdccr(void)
2588{
2589 return GET_CCR(env);
2590}
2591
2592void helper_wrccr(target_ulong new_ccr)
2593{
2594 PUT_CCR(env, new_ccr);
2595}
2596
2597// CWP handling is reversed in V9, but we still use the V8 register
2598// order.
2599target_ulong helper_rdcwp(void)
2600{
2601 return GET_CWP64(env);
2602}
2603
2604void helper_wrcwp(target_ulong new_cwp)
2605{
2606 PUT_CWP64(env, new_cwp);
2607}
3475187d 2608
1f5063fb
BS		 2609// This function uses non-native bit order
2610#define GET_FIELD(X, FROM, TO) \
2611 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2612
2613// This function uses the order in the manuals, i.e. bit 0 is 2^0
2614#define GET_FIELD_SP(X, FROM, TO) \
2615 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2616
2617target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2618{
2619 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2620 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2621 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2622 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2623 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2624 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2625 (((pixel_addr >> 55) & 1) << 4) |
2626 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2627 GET_FIELD_SP(pixel_addr, 11, 12);
2628}
2629
2630target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2631{
2632 uint64_t tmp;
2633
2634 tmp = addr + offset;
2635 env->gsr &= ~7ULL;
2636 env->gsr |= tmp & 7ULL;
2637 return tmp & ~7ULL;
2638}
2639
1a2fb1c0 2640target_ulong helper_popc(target_ulong val)
3475187d 2641{
1a2fb1c0 2642 return ctpop64(val);
3475187d 2643}
83469015
FB		 2644
2645static inline uint64_t *get_gregset(uint64_t pstate)
2646{
2647 switch (pstate) {
2648 default:
2649 case 0:
0f8a249a 2650 return env->bgregs;
83469015 2651 case PS_AG:
0f8a249a 2652 return env->agregs;
83469015 2653 case PS_MG:
0f8a249a 2654 return env->mgregs;
83469015 2655 case PS_IG:
0f8a249a 2656 return env->igregs;
83469015
FB		 2657 }
2658}
2659
91736d37 2660static inline void change_pstate(uint64_t new_pstate)
83469015 2661{
8f1f22f6 2662 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 2663 uint64_t *src, *dst;
2664
83469015
FB		 2665 pstate_regs = env->pstate & 0xc01;
2666 new_pstate_regs = new_pstate & 0xc01;
2667 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 2668 // Switch global register bank
2669 src = get_gregset(new_pstate_regs);
2670 dst = get_gregset(pstate_regs);
2671 memcpy32(dst, env->gregs);
2672 memcpy32(env->gregs, src);
83469015
FB		 2673 }
2674 env->pstate = new_pstate;
2675}
2676
1a2fb1c0 2677void helper_wrpstate(target_ulong new_state)
8f1f22f6 2678{
5578ceab 2679 if (!(env->def->features & CPU_FEATURE_GL))
fb79ceb9 2680 change_pstate(new_state & 0xf3f);
8f1f22f6
BS		 2681}
2682
1a2fb1c0 2683void helper_done(void)
83469015 2684{
375ee38b
BS		 2685 env->pc = env->tsptr->tpc;
2686 env->npc = env->tsptr->tnpc + 4;
2687 PUT_CCR(env, env->tsptr->tstate >> 32);
2688 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2689 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2690 PUT_CWP64(env, env->tsptr->tstate & 0xff);
e6bf7d70 2691 env->tl--;
c19148bd 2692 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
83469015
FB		 2693}
2694
1a2fb1c0 2695void helper_retry(void)
83469015 2696{
375ee38b
BS		 2697 env->pc = env->tsptr->tpc;
2698 env->npc = env->tsptr->tnpc;
2699 PUT_CCR(env, env->tsptr->tstate >> 32);
2700 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2701 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2702 PUT_CWP64(env, env->tsptr->tstate & 0xff);
e6bf7d70 2703 env->tl--;
c19148bd 2704 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
83469015 2705}
9d926598
BS		 2706
2707void helper_set_softint(uint64_t value)
2708{
2709 env->softint |= (uint32_t)value;
2710}
2711
2712void helper_clear_softint(uint64_t value)
2713{
2714 env->softint &= (uint32_t)~value;
2715}
2716
2717void helper_write_softint(uint64_t value)
2718{
2719 env->softint = (uint32_t)value;
2720}
3475187d 2721#endif
ee5bbe38 2722
91736d37 2723void helper_flush(target_ulong addr)
ee5bbe38 2724{
91736d37
BS		 2725 addr &= ~7;
2726 tb_invalidate_page_range(addr, addr + 8);
ee5bbe38
FB		 2727}
2728
91736d37
BS		 2729#ifdef TARGET_SPARC64
2730#ifdef DEBUG_PCALL
2731static const char * const excp_names[0x80] = {
2732 [TT_TFAULT] = "Instruction Access Fault",
2733 [TT_TMISS] = "Instruction Access MMU Miss",
2734 [TT_CODE_ACCESS] = "Instruction Access Error",
2735 [TT_ILL_INSN] = "Illegal Instruction",
2736 [TT_PRIV_INSN] = "Privileged Instruction",
2737 [TT_NFPU_INSN] = "FPU Disabled",
2738 [TT_FP_EXCP] = "FPU Exception",
2739 [TT_TOVF] = "Tag Overflow",
2740 [TT_CLRWIN] = "Clean Windows",
2741 [TT_DIV_ZERO] = "Division By Zero",
2742 [TT_DFAULT] = "Data Access Fault",
2743 [TT_DMISS] = "Data Access MMU Miss",
2744 [TT_DATA_ACCESS] = "Data Access Error",
2745 [TT_DPROT] = "Data Protection Error",
2746 [TT_UNALIGNED] = "Unaligned Memory Access",
2747 [TT_PRIV_ACT] = "Privileged Action",
2748 [TT_EXTINT | 0x1] = "External Interrupt 1",
2749 [TT_EXTINT | 0x2] = "External Interrupt 2",
2750 [TT_EXTINT | 0x3] = "External Interrupt 3",
2751 [TT_EXTINT | 0x4] = "External Interrupt 4",
2752 [TT_EXTINT | 0x5] = "External Interrupt 5",
2753 [TT_EXTINT | 0x6] = "External Interrupt 6",
2754 [TT_EXTINT | 0x7] = "External Interrupt 7",
2755 [TT_EXTINT | 0x8] = "External Interrupt 8",
2756 [TT_EXTINT | 0x9] = "External Interrupt 9",
2757 [TT_EXTINT | 0xa] = "External Interrupt 10",
2758 [TT_EXTINT | 0xb] = "External Interrupt 11",
2759 [TT_EXTINT | 0xc] = "External Interrupt 12",
2760 [TT_EXTINT | 0xd] = "External Interrupt 13",
2761 [TT_EXTINT | 0xe] = "External Interrupt 14",
2762 [TT_EXTINT | 0xf] = "External Interrupt 15",
2763};
2764#endif
2765
2766void do_interrupt(CPUState *env)
2767{
2768 int intno = env->exception_index;
2769
2770#ifdef DEBUG_PCALL
2771 if (loglevel & CPU_LOG_INT) {
2772 static int count;
2773 const char *name;
2774
2775 if (intno < 0 || intno >= 0x180)
2776 name = "Unknown";
2777 else if (intno >= 0x100)
2778 name = "Trap Instruction";
2779 else if (intno >= 0xc0)
2780 name = "Window Fill";
2781 else if (intno >= 0x80)
2782 name = "Window Spill";
2783 else {
2784 name = excp_names[intno];
2785 if (!name)
2786 name = "Unknown";
2787 }
2788
2789 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2790 " SP=%016" PRIx64 "\n",
2791 count, name, intno,
2792 env->pc,
2793 env->npc, env->regwptr[6]);
2794 cpu_dump_state(env, logfile, fprintf, 0);
2795#if 0
2796 {
2797 int i;
2798 uint8_t *ptr;
2799
2800 fprintf(logfile, " code=");
2801 ptr = (uint8_t *)env->pc;
2802 for(i = 0; i < 16; i++) {
2803 fprintf(logfile, " %02x", ldub(ptr + i));
2804 }
2805 fprintf(logfile, "\n");
2806 }
2807#endif
2808 count++;
2809 }
2810#endif
2811#if !defined(CONFIG_USER_ONLY)
2812 if (env->tl >= env->maxtl) {
2813 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
2814 " Error state", env->exception_index, env->tl, env->maxtl);
2815 return;
2816 }
2817#endif
2818 if (env->tl < env->maxtl - 1) {
2819 env->tl++;
2820 } else {
2821 env->pstate |= PS_RED;
2822 if (env->tl < env->maxtl)
2823 env->tl++;
2824 }
2825 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2826 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2827 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2828 GET_CWP64(env);
2829 env->tsptr->tpc = env->pc;
2830 env->tsptr->tnpc = env->npc;
2831 env->tsptr->tt = intno;
2832 if (!(env->def->features & CPU_FEATURE_GL)) {
2833 switch (intno) {
2834 case TT_IVEC:
2835 change_pstate(PS_PEF | PS_PRIV | PS_IG);
2836 break;
2837 case TT_TFAULT:
2838 case TT_TMISS:
2839 case TT_DFAULT:
2840 case TT_DMISS:
2841 case TT_DPROT:
2842 change_pstate(PS_PEF | PS_PRIV | PS_MG);
2843 break;
2844 default:
2845 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2846 break;
2847 }
2848 }
2849 if (intno == TT_CLRWIN)
2850 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
2851 else if ((intno & 0x1c0) == TT_SPILL)
2852 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
2853 else if ((intno & 0x1c0) == TT_FILL)
2854 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
2855 env->tbr &= ~0x7fffULL;
2856 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2857 env->pc = env->tbr;
2858 env->npc = env->pc + 4;
2859 env->exception_index = 0;
ee5bbe38 2860}
91736d37
BS		 2861#else
2862#ifdef DEBUG_PCALL
2863static const char * const excp_names[0x80] = {
2864 [TT_TFAULT] = "Instruction Access Fault",
2865 [TT_ILL_INSN] = "Illegal Instruction",
2866 [TT_PRIV_INSN] = "Privileged Instruction",
2867 [TT_NFPU_INSN] = "FPU Disabled",
2868 [TT_WIN_OVF] = "Window Overflow",
2869 [TT_WIN_UNF] = "Window Underflow",
2870 [TT_UNALIGNED] = "Unaligned Memory Access",
2871 [TT_FP_EXCP] = "FPU Exception",
2872 [TT_DFAULT] = "Data Access Fault",
2873 [TT_TOVF] = "Tag Overflow",
2874 [TT_EXTINT | 0x1] = "External Interrupt 1",
2875 [TT_EXTINT | 0x2] = "External Interrupt 2",
2876 [TT_EXTINT | 0x3] = "External Interrupt 3",
2877 [TT_EXTINT | 0x4] = "External Interrupt 4",
2878 [TT_EXTINT | 0x5] = "External Interrupt 5",
2879 [TT_EXTINT | 0x6] = "External Interrupt 6",
2880 [TT_EXTINT | 0x7] = "External Interrupt 7",
2881 [TT_EXTINT | 0x8] = "External Interrupt 8",
2882 [TT_EXTINT | 0x9] = "External Interrupt 9",
2883 [TT_EXTINT | 0xa] = "External Interrupt 10",
2884 [TT_EXTINT | 0xb] = "External Interrupt 11",
2885 [TT_EXTINT | 0xc] = "External Interrupt 12",
2886 [TT_EXTINT | 0xd] = "External Interrupt 13",
2887 [TT_EXTINT | 0xe] = "External Interrupt 14",
2888 [TT_EXTINT | 0xf] = "External Interrupt 15",
2889 [TT_TOVF] = "Tag Overflow",
2890 [TT_CODE_ACCESS] = "Instruction Access Error",
2891 [TT_DATA_ACCESS] = "Data Access Error",
2892 [TT_DIV_ZERO] = "Division By Zero",
2893 [TT_NCP_INSN] = "Coprocessor Disabled",
2894};
2895#endif
ee5bbe38 2896
91736d37 2897void do_interrupt(CPUState *env)
ee5bbe38 2898{
91736d37
BS		 2899 int cwp, intno = env->exception_index;
2900
2901#ifdef DEBUG_PCALL
2902 if (loglevel & CPU_LOG_INT) {
2903 static int count;
2904 const char *name;
2905
2906 if (intno < 0 || intno >= 0x100)
2907 name = "Unknown";
2908 else if (intno >= 0x80)
2909 name = "Trap Instruction";
2910 else {
2911 name = excp_names[intno];
2912 if (!name)
2913 name = "Unknown";
2914 }
2915
2916 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2917 count, name, intno,
2918 env->pc,
2919 env->npc, env->regwptr[6]);
2920 cpu_dump_state(env, logfile, fprintf, 0);
2921#if 0
2922 {
2923 int i;
2924 uint8_t *ptr;
2925
2926 fprintf(logfile, " code=");
2927 ptr = (uint8_t *)env->pc;
2928 for(i = 0; i < 16; i++) {
2929 fprintf(logfile, " %02x", ldub(ptr + i));
2930 }
2931 fprintf(logfile, "\n");
2932 }
2933#endif
2934 count++;
2935 }
2936#endif
2937#if !defined(CONFIG_USER_ONLY)
2938 if (env->psret == 0) {
2939 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
2940 env->exception_index);
2941 return;
2942 }
2943#endif
2944 env->psret = 0;
2945 cwp = cpu_cwp_dec(env, env->cwp - 1);
2946 cpu_set_cwp(env, cwp);
2947 env->regwptr[9] = env->pc;
2948 env->regwptr[10] = env->npc;
2949 env->psrps = env->psrs;
2950 env->psrs = 1;
2951 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2952 env->pc = env->tbr;
2953 env->npc = env->pc + 4;
2954 env->exception_index = 0;
ee5bbe38 2955}
91736d37 2956#endif
ee5bbe38 2957
5fafdf24 2958#if !defined(CONFIG_USER_ONLY)
ee5bbe38 2959
d2889a3e
BS		 2960static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2961 void *retaddr);
2962
ee5bbe38 2963#define MMUSUFFIX _mmu
d2889a3e 2964#define ALIGNED_ONLY
ee5bbe38
FB		 2965
2966#define SHIFT 0
2967#include "softmmu_template.h"
2968
2969#define SHIFT 1
2970#include "softmmu_template.h"
2971
2972#define SHIFT 2
2973#include "softmmu_template.h"
2974
2975#define SHIFT 3
2976#include "softmmu_template.h"
2977
c2bc0e38
BS		 2978/* XXX: make it generic ? */
2979static void cpu_restore_state2(void *retaddr)
2980{
2981 TranslationBlock *tb;
2982 unsigned long pc;
2983
2984 if (retaddr) {
2985 /* now we have a real cpu fault */
2986 pc = (unsigned long)retaddr;
2987 tb = tb_find_pc(pc);
2988 if (tb) {
2989 /* the PC is inside the translated code. It means that we have
2990 a virtual CPU fault */
2991 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
2992 }
2993 }
2994}
2995
d2889a3e
BS		 2996static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2997 void *retaddr)
2998{
94554550 2999#ifdef DEBUG_UNALIGNED
c2bc0e38
BS		 3000 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
3001 "\n", addr, env->pc);
94554550 3002#endif
c2bc0e38 3003 cpu_restore_state2(retaddr);
94554550 3004 raise_exception(TT_UNALIGNED);
d2889a3e 3005}
ee5bbe38
FB		 3006
3007/* try to fill the TLB and return an exception if error. If retaddr is
3008 NULL, it means that the function was called in C code (i.e. not
3009 from generated code or from helper.c) */
3010/* XXX: fix it to restore all registers */
6ebbf390 3011void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38 3012{
ee5bbe38 3013 int ret;
ee5bbe38
FB		 3014 CPUState *saved_env;
3015
3016 /* XXX: hack to restore env in all cases, even if not called from
3017 generated code */
3018 saved_env = env;
3019 env = cpu_single_env;
3020
6ebbf390 3021 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38 3022 if (ret) {
c2bc0e38 3023 cpu_restore_state2(retaddr);
ee5bbe38
FB		 3024 cpu_loop_exit();
3025 }
3026 env = saved_env;
3027}
3028
3029#endif
6c36d3fa
BS		 3030
3031#ifndef TARGET_SPARC64
5dcb6b91 3032void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 3033 int is_asi, int size)
6c36d3fa
BS		 3034{
3035 CPUState *saved_env;
3036
3037 /* XXX: hack to restore env in all cases, even if not called from
3038 generated code */
3039 saved_env = env;
3040 env = cpu_single_env;
8543e2cf
BS		 3041#ifdef DEBUG_UNASSIGNED
3042 if (is_asi)
e18231a3 3043 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
77f193da 3044 " asi 0x%02x from " TARGET_FMT_lx "\n",
e18231a3
BS		 3045 is_exec ? "exec" : is_write ? "write" : "read", size,
3046 size == 1 ? "" : "s", addr, is_asi, env->pc);
8543e2cf 3047 else
e18231a3
BS		 3048 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3049 " from " TARGET_FMT_lx "\n",
3050 is_exec ? "exec" : is_write ? "write" : "read", size,
3051 size == 1 ? "" : "s", addr, env->pc);
8543e2cf 3052#endif
6c36d3fa 3053 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 3054 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 3055 if (is_asi)
3056 env->mmuregs[3] |= 1 << 16;
3057 if (env->psrs)
3058 env->mmuregs[3] |= 1 << 5;
3059 if (is_exec)
3060 env->mmuregs[3] |= 1 << 6;
3061 if (is_write)
3062 env->mmuregs[3] |= 1 << 7;
3063 env->mmuregs[3] |= (5 << 2) | 2;
3064 env->mmuregs[4] = addr; /* Fault address register */
3065 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1b2e93c1
BS		 3066 if (is_exec)
3067 raise_exception(TT_CODE_ACCESS);
3068 else
3069 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 3070 }
3071 env = saved_env;
3072}
3073#else
5dcb6b91 3074void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 3075 int is_asi, int size)
6c36d3fa
BS		 3076{
3077#ifdef DEBUG_UNASSIGNED
3078 CPUState *saved_env;
3079
3080 /* XXX: hack to restore env in all cases, even if not called from
3081 generated code */
3082 saved_env = env;
3083 env = cpu_single_env;
77f193da
BS		 3084 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3085 "\n", addr, env->pc);
6c36d3fa
BS		 3086 env = saved_env;
3087#endif
1b2e93c1
BS		 3088 if (is_exec)
3089 raise_exception(TT_CODE_ACCESS);
3090 else
3091 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 3092}
3093#endif
20c9f095 3094
f4b1a842
BS		 3095#ifdef TARGET_SPARC64
3096void helper_tick_set_count(void *opaque, uint64_t count)
3097{
3098#if !defined(CONFIG_USER_ONLY)
3099 cpu_tick_set_count(opaque, count);
3100#endif
3101}
3102
3103uint64_t helper_tick_get_count(void *opaque)
3104{
3105#if !defined(CONFIG_USER_ONLY)
3106 return cpu_tick_get_count(opaque);
3107#else
3108 return 0;
3109#endif
3110}
3111
3112void helper_tick_set_limit(void *opaque, uint64_t limit)
3113{
3114#if !defined(CONFIG_USER_ONLY)
3115 cpu_tick_set_limit(opaque, limit);
3116#endif
3117}
3118#endif
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