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Commit | Line | Data |
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e8af50a3 | 1 | #include "exec.h" |
eed152bb | 2 | #include "host-utils.h" |
1a2fb1c0 | 3 | #include "helper.h" |
e8af50a3 | 4 | |
e80cfcfc | 5 | //#define DEBUG_MMU |
952a328f | 6 | //#define DEBUG_MXCC |
94554550 | 7 | //#define DEBUG_UNALIGNED |
6c36d3fa | 8 | //#define DEBUG_UNASSIGNED |
8543e2cf | 9 | //#define DEBUG_ASI |
d81fd722 | 10 | //#define DEBUG_PCALL |
7e8695ed | 11 | //#define DEBUG_PSTATE |
e80cfcfc | 12 | |
952a328f | 13 | #ifdef DEBUG_MMU |
001faf32 BS |
14 | #define DPRINTF_MMU(fmt, ...) \ |
15 | do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) | |
952a328f | 16 | #else |
001faf32 | 17 | #define DPRINTF_MMU(fmt, ...) do {} while (0) |
952a328f BS |
18 | #endif |
19 | ||
20 | #ifdef DEBUG_MXCC | |
001faf32 BS |
21 | #define DPRINTF_MXCC(fmt, ...) \ |
22 | do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) | |
952a328f | 23 | #else |
001faf32 | 24 | #define DPRINTF_MXCC(fmt, ...) do {} while (0) |
952a328f BS |
25 | #endif |
26 | ||
8543e2cf | 27 | #ifdef DEBUG_ASI |
001faf32 BS |
28 | #define DPRINTF_ASI(fmt, ...) \ |
29 | do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) | |
8543e2cf BS |
30 | #endif |
31 | ||
7e8695ed IK |
32 | #ifdef DEBUG_PSTATE |
33 | #define DPRINTF_PSTATE(fmt, ...) \ | |
34 | do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) | |
35 | #else | |
36 | #define DPRINTF_PSTATE(fmt, ...) do {} while (0) | |
37 | #endif | |
38 | ||
2cade6a3 BS |
39 | #ifdef TARGET_SPARC64 |
40 | #ifndef TARGET_ABI32 | |
41 | #define AM_CHECK(env1) ((env1)->pstate & PS_AM) | |
c2bc0e38 | 42 | #else |
2cade6a3 BS |
43 | #define AM_CHECK(env1) (1) |
44 | #endif | |
c2bc0e38 BS |
45 | #endif |
46 | ||
21ffd181 BS |
47 | #define DT0 (env->dt0) |
48 | #define DT1 (env->dt1) | |
49 | #define QT0 (env->qt0) | |
50 | #define QT1 (env->qt1) | |
51 | ||
3c7b48b7 PB |
52 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
53 | static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, | |
54 | int is_asi, int size); | |
55 | #endif | |
56 | ||
9c22a623 | 57 | #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) |
697a77e6 IK |
58 | // Calculates TSB pointer value for fault page size 8k or 64k |
59 | static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register, | |
60 | uint64_t tag_access_register, | |
61 | int page_size) | |
62 | { | |
63 | uint64_t tsb_base = tsb_register & ~0x1fffULL; | |
6e8e7d4c IK |
64 | int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; |
65 | int tsb_size = tsb_register & 0xf; | |
697a77e6 IK |
66 | |
67 | // discard lower 13 bits which hold tag access context | |
68 | uint64_t tag_access_va = tag_access_register & ~0x1fffULL; | |
69 | ||
70 | // now reorder bits | |
71 | uint64_t tsb_base_mask = ~0x1fffULL; | |
72 | uint64_t va = tag_access_va; | |
73 | ||
74 | // move va bits to correct position | |
75 | if (page_size == 8*1024) { | |
76 | va >>= 9; | |
77 | } else if (page_size == 64*1024) { | |
78 | va >>= 12; | |
79 | } | |
80 | ||
81 | if (tsb_size) { | |
82 | tsb_base_mask <<= tsb_size; | |
83 | } | |
84 | ||
85 | // calculate tsb_base mask and adjust va if split is in use | |
86 | if (tsb_split) { | |
87 | if (page_size == 8*1024) { | |
88 | va &= ~(1ULL << (13 + tsb_size)); | |
89 | } else if (page_size == 64*1024) { | |
90 | va |= (1ULL << (13 + tsb_size)); | |
91 | } | |
92 | tsb_base_mask <<= 1; | |
93 | } | |
94 | ||
95 | return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; | |
96 | } | |
97 | ||
98 | // Calculates tag target register value by reordering bits | |
99 | // in tag access register | |
100 | static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) | |
101 | { | |
102 | return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); | |
103 | } | |
104 | ||
f707726e IK |
105 | static void replace_tlb_entry(SparcTLBEntry *tlb, |
106 | uint64_t tlb_tag, uint64_t tlb_tte, | |
107 | CPUState *env1) | |
6e8e7d4c IK |
108 | { |
109 | target_ulong mask, size, va, offset; | |
110 | ||
111 | // flush page range if translation is valid | |
f707726e | 112 | if (TTE_IS_VALID(tlb->tte)) { |
6e8e7d4c IK |
113 | |
114 | mask = 0xffffffffffffe000ULL; | |
115 | mask <<= 3 * ((tlb->tte >> 61) & 3); | |
116 | size = ~mask + 1; | |
117 | ||
118 | va = tlb->tag & mask; | |
119 | ||
120 | for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { | |
121 | tlb_flush_page(env1, va + offset); | |
122 | } | |
123 | } | |
124 | ||
125 | tlb->tag = tlb_tag; | |
126 | tlb->tte = tlb_tte; | |
127 | } | |
128 | ||
129 | static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, | |
f707726e | 130 | const char* strmmu, CPUState *env1) |
6e8e7d4c IK |
131 | { |
132 | unsigned int i; | |
133 | target_ulong mask; | |
299b520c IK |
134 | uint64_t context; |
135 | ||
136 | int is_demap_context = (demap_addr >> 6) & 1; | |
137 | ||
138 | // demap context | |
139 | switch ((demap_addr >> 4) & 3) { | |
140 | case 0: // primary | |
141 | context = env1->dmmu.mmu_primary_context; | |
142 | break; | |
143 | case 1: // secondary | |
144 | context = env1->dmmu.mmu_secondary_context; | |
145 | break; | |
146 | case 2: // nucleus | |
147 | context = 0; | |
148 | break; | |
149 | case 3: // reserved | |
150 | default: | |
151 | return; | |
152 | } | |
6e8e7d4c IK |
153 | |
154 | for (i = 0; i < 64; i++) { | |
f707726e | 155 | if (TTE_IS_VALID(tlb[i].tte)) { |
6e8e7d4c | 156 | |
299b520c IK |
157 | if (is_demap_context) { |
158 | // will remove non-global entries matching context value | |
159 | if (TTE_IS_GLOBAL(tlb[i].tte) || | |
160 | !tlb_compare_context(&tlb[i], context)) { | |
161 | continue; | |
162 | } | |
163 | } else { | |
164 | // demap page | |
165 | // will remove any entry matching VA | |
166 | mask = 0xffffffffffffe000ULL; | |
167 | mask <<= 3 * ((tlb[i].tte >> 61) & 3); | |
168 | ||
169 | if (!compare_masked(demap_addr, tlb[i].tag, mask)) { | |
170 | continue; | |
171 | } | |
172 | ||
173 | // entry should be global or matching context value | |
174 | if (!TTE_IS_GLOBAL(tlb[i].tte) && | |
175 | !tlb_compare_context(&tlb[i], context)) { | |
176 | continue; | |
177 | } | |
178 | } | |
6e8e7d4c | 179 | |
299b520c | 180 | replace_tlb_entry(&tlb[i], 0, 0, env1); |
6e8e7d4c | 181 | #ifdef DEBUG_MMU |
299b520c IK |
182 | DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); |
183 | dump_mmu(env1); | |
6e8e7d4c | 184 | #endif |
6e8e7d4c IK |
185 | } |
186 | } | |
6e8e7d4c IK |
187 | } |
188 | ||
f707726e IK |
189 | static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, |
190 | uint64_t tlb_tag, uint64_t tlb_tte, | |
191 | const char* strmmu, CPUState *env1) | |
192 | { | |
193 | unsigned int i, replace_used; | |
194 | ||
195 | // Try replacing invalid entry | |
196 | for (i = 0; i < 64; i++) { | |
197 | if (!TTE_IS_VALID(tlb[i].tte)) { | |
198 | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); | |
199 | #ifdef DEBUG_MMU | |
200 | DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); | |
201 | dump_mmu(env1); | |
202 | #endif | |
203 | return; | |
204 | } | |
205 | } | |
206 | ||
207 | // All entries are valid, try replacing unlocked entry | |
208 | ||
209 | for (replace_used = 0; replace_used < 2; ++replace_used) { | |
210 | ||
211 | // Used entries are not replaced on first pass | |
212 | ||
213 | for (i = 0; i < 64; i++) { | |
214 | if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { | |
215 | ||
216 | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); | |
217 | #ifdef DEBUG_MMU | |
218 | DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", | |
219 | strmmu, (replace_used?"used":"unused"), i); | |
220 | dump_mmu(env1); | |
221 | #endif | |
222 | return; | |
223 | } | |
224 | } | |
225 | ||
226 | // Now reset used bit and search for unused entries again | |
227 | ||
228 | for (i = 0; i < 64; i++) { | |
229 | TTE_SET_UNUSED(tlb[i].tte); | |
230 | } | |
231 | } | |
232 | ||
233 | #ifdef DEBUG_MMU | |
234 | DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu); | |
235 | #endif | |
236 | // error state? | |
237 | } | |
238 | ||
697a77e6 IK |
239 | #endif |
240 | ||
41db525e | 241 | static inline target_ulong address_mask(CPUState *env1, target_ulong addr) |
2cade6a3 BS |
242 | { |
243 | #ifdef TARGET_SPARC64 | |
244 | if (AM_CHECK(env1)) | |
41db525e | 245 | addr &= 0xffffffffULL; |
2cade6a3 | 246 | #endif |
41db525e | 247 | return addr; |
2cade6a3 BS |
248 | } |
249 | ||
1295001c IK |
250 | /* returns true if access using this ASI is to have address translated by MMU |
251 | otherwise access is to raw physical address */ | |
252 | static inline int is_translating_asi(int asi) | |
253 | { | |
254 | #ifdef TARGET_SPARC64 | |
255 | /* Ultrasparc IIi translating asi | |
256 | - note this list is defined by cpu implementation | |
257 | */ | |
258 | switch (asi) { | |
259 | case 0x04 ... 0x11: | |
260 | case 0x18 ... 0x19: | |
261 | case 0x24 ... 0x2C: | |
262 | case 0x70 ... 0x73: | |
263 | case 0x78 ... 0x79: | |
264 | case 0x80 ... 0xFF: | |
265 | return 1; | |
266 | ||
267 | default: | |
268 | return 0; | |
269 | } | |
270 | #else | |
271 | /* TODO: check sparc32 bits */ | |
272 | return 0; | |
273 | #endif | |
274 | } | |
275 | ||
276 | static inline target_ulong asi_address_mask(CPUState *env1, | |
277 | int asi, target_ulong addr) | |
278 | { | |
279 | if (is_translating_asi(asi)) { | |
280 | return address_mask(env, addr); | |
281 | } else { | |
282 | return addr; | |
283 | } | |
284 | } | |
285 | ||
f4a5a5ba | 286 | static void raise_exception(int tt) |
9d893301 FB |
287 | { |
288 | env->exception_index = tt; | |
289 | cpu_loop_exit(); | |
3b46e624 | 290 | } |
9d893301 | 291 | |
a7812ae4 PB |
292 | void HELPER(raise_exception)(int tt) |
293 | { | |
294 | raise_exception(tt); | |
295 | } | |
296 | ||
2b29924f BS |
297 | void helper_check_align(target_ulong addr, uint32_t align) |
298 | { | |
c2bc0e38 BS |
299 | if (addr & align) { |
300 | #ifdef DEBUG_UNALIGNED | |
301 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx | |
302 | "\n", addr, env->pc); | |
303 | #endif | |
2b29924f | 304 | raise_exception(TT_UNALIGNED); |
c2bc0e38 | 305 | } |
2b29924f BS |
306 | } |
307 | ||
44e7757c BS |
308 | #define F_HELPER(name, p) void helper_f##name##p(void) |
309 | ||
44e7757c | 310 | #define F_BINOP(name) \ |
714547bb | 311 | float32 helper_f ## name ## s (float32 src1, float32 src2) \ |
44e7757c | 312 | { \ |
714547bb | 313 | return float32_ ## name (src1, src2, &env->fp_status); \ |
44e7757c BS |
314 | } \ |
315 | F_HELPER(name, d) \ | |
316 | { \ | |
317 | DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ | |
4e14008f BS |
318 | } \ |
319 | F_HELPER(name, q) \ | |
320 | { \ | |
321 | QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \ | |
44e7757c | 322 | } |
44e7757c BS |
323 | |
324 | F_BINOP(add); | |
325 | F_BINOP(sub); | |
326 | F_BINOP(mul); | |
327 | F_BINOP(div); | |
328 | #undef F_BINOP | |
329 | ||
d84763bc | 330 | void helper_fsmuld(float32 src1, float32 src2) |
1a2fb1c0 | 331 | { |
d84763bc BS |
332 | DT0 = float64_mul(float32_to_float64(src1, &env->fp_status), |
333 | float32_to_float64(src2, &env->fp_status), | |
44e7757c BS |
334 | &env->fp_status); |
335 | } | |
1a2fb1c0 | 336 | |
4e14008f BS |
337 | void helper_fdmulq(void) |
338 | { | |
339 | QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status), | |
340 | float64_to_float128(DT1, &env->fp_status), | |
341 | &env->fp_status); | |
342 | } | |
4e14008f | 343 | |
714547bb | 344 | float32 helper_fnegs(float32 src) |
44e7757c | 345 | { |
714547bb | 346 | return float32_chs(src); |
417454b0 BS |
347 | } |
348 | ||
44e7757c BS |
349 | #ifdef TARGET_SPARC64 |
350 | F_HELPER(neg, d) | |
7e8c2b6c | 351 | { |
44e7757c | 352 | DT0 = float64_chs(DT1); |
7e8c2b6c | 353 | } |
4e14008f | 354 | |
4e14008f BS |
355 | F_HELPER(neg, q) |
356 | { | |
357 | QT0 = float128_chs(QT1); | |
358 | } | |
359 | #endif | |
44e7757c BS |
360 | |
361 | /* Integer to float conversion. */ | |
714547bb | 362 | float32 helper_fitos(int32_t src) |
a0c4cb4a | 363 | { |
714547bb | 364 | return int32_to_float32(src, &env->fp_status); |
a0c4cb4a FB |
365 | } |
366 | ||
d84763bc | 367 | void helper_fitod(int32_t src) |
a0c4cb4a | 368 | { |
d84763bc | 369 | DT0 = int32_to_float64(src, &env->fp_status); |
a0c4cb4a | 370 | } |
9c2b428e | 371 | |
c5d04e99 | 372 | void helper_fitoq(int32_t src) |
4e14008f | 373 | { |
c5d04e99 | 374 | QT0 = int32_to_float128(src, &env->fp_status); |
4e14008f | 375 | } |
4e14008f | 376 | |
1e64e78d | 377 | #ifdef TARGET_SPARC64 |
d84763bc | 378 | float32 helper_fxtos(void) |
1e64e78d | 379 | { |
d84763bc | 380 | return int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
1e64e78d BS |
381 | } |
382 | ||
44e7757c | 383 | F_HELPER(xto, d) |
1e64e78d | 384 | { |
1e64e78d | 385 | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
1e64e78d | 386 | } |
64a88d5d | 387 | |
4e14008f BS |
388 | F_HELPER(xto, q) |
389 | { | |
390 | QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status); | |
391 | } | |
392 | #endif | |
44e7757c BS |
393 | #undef F_HELPER |
394 | ||
395 | /* floating point conversion */ | |
d84763bc | 396 | float32 helper_fdtos(void) |
44e7757c | 397 | { |
d84763bc | 398 | return float64_to_float32(DT1, &env->fp_status); |
44e7757c BS |
399 | } |
400 | ||
d84763bc | 401 | void helper_fstod(float32 src) |
44e7757c | 402 | { |
d84763bc | 403 | DT0 = float32_to_float64(src, &env->fp_status); |
44e7757c | 404 | } |
9c2b428e | 405 | |
c5d04e99 | 406 | float32 helper_fqtos(void) |
4e14008f | 407 | { |
c5d04e99 | 408 | return float128_to_float32(QT1, &env->fp_status); |
4e14008f BS |
409 | } |
410 | ||
c5d04e99 | 411 | void helper_fstoq(float32 src) |
4e14008f | 412 | { |
c5d04e99 | 413 | QT0 = float32_to_float128(src, &env->fp_status); |
4e14008f BS |
414 | } |
415 | ||
416 | void helper_fqtod(void) | |
417 | { | |
418 | DT0 = float128_to_float64(QT1, &env->fp_status); | |
419 | } | |
420 | ||
421 | void helper_fdtoq(void) | |
422 | { | |
423 | QT0 = float64_to_float128(DT1, &env->fp_status); | |
424 | } | |
4e14008f | 425 | |
44e7757c | 426 | /* Float to integer conversion. */ |
714547bb | 427 | int32_t helper_fstoi(float32 src) |
44e7757c | 428 | { |
714547bb | 429 | return float32_to_int32_round_to_zero(src, &env->fp_status); |
44e7757c BS |
430 | } |
431 | ||
d84763bc | 432 | int32_t helper_fdtoi(void) |
44e7757c | 433 | { |
d84763bc | 434 | return float64_to_int32_round_to_zero(DT1, &env->fp_status); |
44e7757c BS |
435 | } |
436 | ||
c5d04e99 | 437 | int32_t helper_fqtoi(void) |
4e14008f | 438 | { |
c5d04e99 | 439 | return float128_to_int32_round_to_zero(QT1, &env->fp_status); |
4e14008f | 440 | } |
4e14008f | 441 | |
44e7757c | 442 | #ifdef TARGET_SPARC64 |
d84763bc | 443 | void helper_fstox(float32 src) |
44e7757c | 444 | { |
d84763bc | 445 | *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status); |
44e7757c BS |
446 | } |
447 | ||
448 | void helper_fdtox(void) | |
449 | { | |
450 | *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); | |
451 | } | |
452 | ||
4e14008f BS |
453 | void helper_fqtox(void) |
454 | { | |
455 | *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status); | |
456 | } | |
4e14008f | 457 | |
44e7757c BS |
458 | void helper_faligndata(void) |
459 | { | |
460 | uint64_t tmp; | |
461 | ||
462 | tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); | |
06057e6f BS |
463 | /* on many architectures a shift of 64 does nothing */ |
464 | if ((env->gsr & 7) != 0) { | |
465 | tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); | |
466 | } | |
44e7757c BS |
467 | *((uint64_t *)&DT0) = tmp; |
468 | } | |
469 | ||
e2542fe2 | 470 | #ifdef HOST_WORDS_BIGENDIAN |
44e7757c BS |
471 | #define VIS_B64(n) b[7 - (n)] |
472 | #define VIS_W64(n) w[3 - (n)] | |
473 | #define VIS_SW64(n) sw[3 - (n)] | |
474 | #define VIS_L64(n) l[1 - (n)] | |
475 | #define VIS_B32(n) b[3 - (n)] | |
476 | #define VIS_W32(n) w[1 - (n)] | |
477 | #else | |
478 | #define VIS_B64(n) b[n] | |
479 | #define VIS_W64(n) w[n] | |
480 | #define VIS_SW64(n) sw[n] | |
481 | #define VIS_L64(n) l[n] | |
482 | #define VIS_B32(n) b[n] | |
483 | #define VIS_W32(n) w[n] | |
484 | #endif | |
485 | ||
486 | typedef union { | |
487 | uint8_t b[8]; | |
488 | uint16_t w[4]; | |
489 | int16_t sw[4]; | |
490 | uint32_t l[2]; | |
491 | float64 d; | |
492 | } vis64; | |
493 | ||
494 | typedef union { | |
495 | uint8_t b[4]; | |
496 | uint16_t w[2]; | |
497 | uint32_t l; | |
498 | float32 f; | |
499 | } vis32; | |
500 | ||
501 | void helper_fpmerge(void) | |
502 | { | |
503 | vis64 s, d; | |
504 | ||
505 | s.d = DT0; | |
506 | d.d = DT1; | |
507 | ||
508 | // Reverse calculation order to handle overlap | |
509 | d.VIS_B64(7) = s.VIS_B64(3); | |
510 | d.VIS_B64(6) = d.VIS_B64(3); | |
511 | d.VIS_B64(5) = s.VIS_B64(2); | |
512 | d.VIS_B64(4) = d.VIS_B64(2); | |
513 | d.VIS_B64(3) = s.VIS_B64(1); | |
514 | d.VIS_B64(2) = d.VIS_B64(1); | |
515 | d.VIS_B64(1) = s.VIS_B64(0); | |
516 | //d.VIS_B64(0) = d.VIS_B64(0); | |
517 | ||
518 | DT0 = d.d; | |
519 | } | |
520 | ||
521 | void helper_fmul8x16(void) | |
522 | { | |
523 | vis64 s, d; | |
524 | uint32_t tmp; | |
525 | ||
526 | s.d = DT0; | |
527 | d.d = DT1; | |
528 | ||
529 | #define PMUL(r) \ | |
530 | tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ | |
531 | if ((tmp & 0xff) > 0x7f) \ | |
532 | tmp += 0x100; \ | |
533 | d.VIS_W64(r) = tmp >> 8; | |
534 | ||
535 | PMUL(0); | |
536 | PMUL(1); | |
537 | PMUL(2); | |
538 | PMUL(3); | |
539 | #undef PMUL | |
540 | ||
541 | DT0 = d.d; | |
542 | } | |
543 | ||
544 | void helper_fmul8x16al(void) | |
545 | { | |
546 | vis64 s, d; | |
547 | uint32_t tmp; | |
548 | ||
549 | s.d = DT0; | |
550 | d.d = DT1; | |
551 | ||
552 | #define PMUL(r) \ | |
553 | tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \ | |
554 | if ((tmp & 0xff) > 0x7f) \ | |
555 | tmp += 0x100; \ | |
556 | d.VIS_W64(r) = tmp >> 8; | |
557 | ||
558 | PMUL(0); | |
559 | PMUL(1); | |
560 | PMUL(2); | |
561 | PMUL(3); | |
562 | #undef PMUL | |
563 | ||
564 | DT0 = d.d; | |
565 | } | |
566 | ||
567 | void helper_fmul8x16au(void) | |
568 | { | |
569 | vis64 s, d; | |
570 | uint32_t tmp; | |
571 | ||
572 | s.d = DT0; | |
573 | d.d = DT1; | |
574 | ||
575 | #define PMUL(r) \ | |
576 | tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \ | |
577 | if ((tmp & 0xff) > 0x7f) \ | |
578 | tmp += 0x100; \ | |
579 | d.VIS_W64(r) = tmp >> 8; | |
580 | ||
581 | PMUL(0); | |
582 | PMUL(1); | |
583 | PMUL(2); | |
584 | PMUL(3); | |
585 | #undef PMUL | |
586 | ||
587 | DT0 = d.d; | |
588 | } | |
589 | ||
590 | void helper_fmul8sux16(void) | |
591 | { | |
592 | vis64 s, d; | |
593 | uint32_t tmp; | |
594 | ||
595 | s.d = DT0; | |
596 | d.d = DT1; | |
597 | ||
598 | #define PMUL(r) \ | |
599 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ | |
600 | if ((tmp & 0xff) > 0x7f) \ | |
601 | tmp += 0x100; \ | |
602 | d.VIS_W64(r) = tmp >> 8; | |
603 | ||
604 | PMUL(0); | |
605 | PMUL(1); | |
606 | PMUL(2); | |
607 | PMUL(3); | |
608 | #undef PMUL | |
609 | ||
610 | DT0 = d.d; | |
611 | } | |
612 | ||
613 | void helper_fmul8ulx16(void) | |
614 | { | |
615 | vis64 s, d; | |
616 | uint32_t tmp; | |
617 | ||
618 | s.d = DT0; | |
619 | d.d = DT1; | |
620 | ||
621 | #define PMUL(r) \ | |
622 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ | |
623 | if ((tmp & 0xff) > 0x7f) \ | |
624 | tmp += 0x100; \ | |
625 | d.VIS_W64(r) = tmp >> 8; | |
626 | ||
627 | PMUL(0); | |
628 | PMUL(1); | |
629 | PMUL(2); | |
630 | PMUL(3); | |
631 | #undef PMUL | |
632 | ||
633 | DT0 = d.d; | |
634 | } | |
635 | ||
636 | void helper_fmuld8sux16(void) | |
637 | { | |
638 | vis64 s, d; | |
639 | uint32_t tmp; | |
640 | ||
641 | s.d = DT0; | |
642 | d.d = DT1; | |
643 | ||
644 | #define PMUL(r) \ | |
645 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ | |
646 | if ((tmp & 0xff) > 0x7f) \ | |
647 | tmp += 0x100; \ | |
648 | d.VIS_L64(r) = tmp; | |
649 | ||
650 | // Reverse calculation order to handle overlap | |
651 | PMUL(1); | |
652 | PMUL(0); | |
653 | #undef PMUL | |
654 | ||
655 | DT0 = d.d; | |
656 | } | |
657 | ||
658 | void helper_fmuld8ulx16(void) | |
659 | { | |
660 | vis64 s, d; | |
661 | uint32_t tmp; | |
662 | ||
663 | s.d = DT0; | |
664 | d.d = DT1; | |
665 | ||
666 | #define PMUL(r) \ | |
667 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ | |
668 | if ((tmp & 0xff) > 0x7f) \ | |
669 | tmp += 0x100; \ | |
670 | d.VIS_L64(r) = tmp; | |
671 | ||
672 | // Reverse calculation order to handle overlap | |
673 | PMUL(1); | |
674 | PMUL(0); | |
675 | #undef PMUL | |
676 | ||
677 | DT0 = d.d; | |
678 | } | |
679 | ||
680 | void helper_fexpand(void) | |
681 | { | |
682 | vis32 s; | |
683 | vis64 d; | |
684 | ||
685 | s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff); | |
686 | d.d = DT1; | |
c55bda30 BS |
687 | d.VIS_W64(0) = s.VIS_B32(0) << 4; |
688 | d.VIS_W64(1) = s.VIS_B32(1) << 4; | |
689 | d.VIS_W64(2) = s.VIS_B32(2) << 4; | |
690 | d.VIS_W64(3) = s.VIS_B32(3) << 4; | |
44e7757c BS |
691 | |
692 | DT0 = d.d; | |
693 | } | |
694 | ||
695 | #define VIS_HELPER(name, F) \ | |
696 | void name##16(void) \ | |
697 | { \ | |
698 | vis64 s, d; \ | |
699 | \ | |
700 | s.d = DT0; \ | |
701 | d.d = DT1; \ | |
702 | \ | |
703 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ | |
704 | d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ | |
705 | d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ | |
706 | d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ | |
707 | \ | |
708 | DT0 = d.d; \ | |
709 | } \ | |
710 | \ | |
1d01299d | 711 | uint32_t name##16s(uint32_t src1, uint32_t src2) \ |
44e7757c BS |
712 | { \ |
713 | vis32 s, d; \ | |
714 | \ | |
1d01299d BS |
715 | s.l = src1; \ |
716 | d.l = src2; \ | |
44e7757c BS |
717 | \ |
718 | d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ | |
719 | d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ | |
720 | \ | |
1d01299d | 721 | return d.l; \ |
44e7757c BS |
722 | } \ |
723 | \ | |
724 | void name##32(void) \ | |
725 | { \ | |
726 | vis64 s, d; \ | |
727 | \ | |
728 | s.d = DT0; \ | |
729 | d.d = DT1; \ | |
730 | \ | |
731 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ | |
732 | d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ | |
733 | \ | |
734 | DT0 = d.d; \ | |
735 | } \ | |
736 | \ | |
1d01299d | 737 | uint32_t name##32s(uint32_t src1, uint32_t src2) \ |
44e7757c BS |
738 | { \ |
739 | vis32 s, d; \ | |
740 | \ | |
1d01299d BS |
741 | s.l = src1; \ |
742 | d.l = src2; \ | |
44e7757c BS |
743 | \ |
744 | d.l = F(d.l, s.l); \ | |
745 | \ | |
1d01299d | 746 | return d.l; \ |
44e7757c BS |
747 | } |
748 | ||
749 | #define FADD(a, b) ((a) + (b)) | |
750 | #define FSUB(a, b) ((a) - (b)) | |
751 | VIS_HELPER(helper_fpadd, FADD) | |
752 | VIS_HELPER(helper_fpsub, FSUB) | |
753 | ||
754 | #define VIS_CMPHELPER(name, F) \ | |
755 | void name##16(void) \ | |
756 | { \ | |
757 | vis64 s, d; \ | |
758 | \ | |
759 | s.d = DT0; \ | |
760 | d.d = DT1; \ | |
761 | \ | |
762 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \ | |
763 | d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \ | |
764 | d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \ | |
765 | d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \ | |
766 | \ | |
767 | DT0 = d.d; \ | |
768 | } \ | |
769 | \ | |
770 | void name##32(void) \ | |
771 | { \ | |
772 | vis64 s, d; \ | |
773 | \ | |
774 | s.d = DT0; \ | |
775 | d.d = DT1; \ | |
776 | \ | |
777 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \ | |
778 | d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \ | |
779 | \ | |
780 | DT0 = d.d; \ | |
781 | } | |
782 | ||
783 | #define FCMPGT(a, b) ((a) > (b)) | |
784 | #define FCMPEQ(a, b) ((a) == (b)) | |
785 | #define FCMPLE(a, b) ((a) <= (b)) | |
786 | #define FCMPNE(a, b) ((a) != (b)) | |
787 | ||
788 | VIS_CMPHELPER(helper_fcmpgt, FCMPGT) | |
789 | VIS_CMPHELPER(helper_fcmpeq, FCMPEQ) | |
790 | VIS_CMPHELPER(helper_fcmple, FCMPLE) | |
791 | VIS_CMPHELPER(helper_fcmpne, FCMPNE) | |
792 | #endif | |
793 | ||
794 | void helper_check_ieee_exceptions(void) | |
795 | { | |
796 | target_ulong status; | |
797 | ||
798 | status = get_float_exception_flags(&env->fp_status); | |
799 | if (status) { | |
800 | /* Copy IEEE 754 flags into FSR */ | |
801 | if (status & float_flag_invalid) | |
802 | env->fsr |= FSR_NVC; | |
803 | if (status & float_flag_overflow) | |
804 | env->fsr |= FSR_OFC; | |
805 | if (status & float_flag_underflow) | |
806 | env->fsr |= FSR_UFC; | |
807 | if (status & float_flag_divbyzero) | |
808 | env->fsr |= FSR_DZC; | |
809 | if (status & float_flag_inexact) | |
810 | env->fsr |= FSR_NXC; | |
811 | ||
812 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { | |
813 | /* Unmasked exception, generate a trap */ | |
814 | env->fsr |= FSR_FTT_IEEE_EXCP; | |
815 | raise_exception(TT_FP_EXCP); | |
816 | } else { | |
817 | /* Accumulate exceptions */ | |
818 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; | |
819 | } | |
820 | } | |
821 | } | |
822 | ||
823 | void helper_clear_float_exceptions(void) | |
824 | { | |
825 | set_float_exception_flags(0, &env->fp_status); | |
826 | } | |
827 | ||
714547bb | 828 | float32 helper_fabss(float32 src) |
e8af50a3 | 829 | { |
714547bb | 830 | return float32_abs(src); |
e8af50a3 FB |
831 | } |
832 | ||
3475187d | 833 | #ifdef TARGET_SPARC64 |
7e8c2b6c | 834 | void helper_fabsd(void) |
3475187d FB |
835 | { |
836 | DT0 = float64_abs(DT1); | |
837 | } | |
4e14008f | 838 | |
4e14008f BS |
839 | void helper_fabsq(void) |
840 | { | |
841 | QT0 = float128_abs(QT1); | |
842 | } | |
843 | #endif | |
3475187d | 844 | |
714547bb | 845 | float32 helper_fsqrts(float32 src) |
e8af50a3 | 846 | { |
714547bb | 847 | return float32_sqrt(src, &env->fp_status); |
e8af50a3 FB |
848 | } |
849 | ||
7e8c2b6c | 850 | void helper_fsqrtd(void) |
e8af50a3 | 851 | { |
7a0e1f41 | 852 | DT0 = float64_sqrt(DT1, &env->fp_status); |
e8af50a3 FB |
853 | } |
854 | ||
4e14008f BS |
855 | void helper_fsqrtq(void) |
856 | { | |
857 | QT0 = float128_sqrt(QT1, &env->fp_status); | |
858 | } | |
4e14008f | 859 | |
417454b0 | 860 | #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \ |
7e8c2b6c | 861 | void glue(helper_, name) (void) \ |
65ce8c2f | 862 | { \ |
1a2fb1c0 BS |
863 | target_ulong new_fsr; \ |
864 | \ | |
65ce8c2f FB |
865 | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
866 | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ | |
867 | case float_relation_unordered: \ | |
1a2fb1c0 | 868 | new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ |
417454b0 | 869 | if ((env->fsr & FSR_NVM) || TRAP) { \ |
1a2fb1c0 | 870 | env->fsr |= new_fsr; \ |
417454b0 BS |
871 | env->fsr |= FSR_NVC; \ |
872 | env->fsr |= FSR_FTT_IEEE_EXCP; \ | |
65ce8c2f FB |
873 | raise_exception(TT_FP_EXCP); \ |
874 | } else { \ | |
875 | env->fsr |= FSR_NVA; \ | |
876 | } \ | |
877 | break; \ | |
878 | case float_relation_less: \ | |
1a2fb1c0 | 879 | new_fsr = FSR_FCC0 << FS; \ |
65ce8c2f FB |
880 | break; \ |
881 | case float_relation_greater: \ | |
1a2fb1c0 | 882 | new_fsr = FSR_FCC1 << FS; \ |
65ce8c2f FB |
883 | break; \ |
884 | default: \ | |
1a2fb1c0 | 885 | new_fsr = 0; \ |
65ce8c2f FB |
886 | break; \ |
887 | } \ | |
1a2fb1c0 | 888 | env->fsr |= new_fsr; \ |
e8af50a3 | 889 | } |
714547bb BS |
890 | #define GEN_FCMPS(name, size, FS, TRAP) \ |
891 | void glue(helper_, name)(float32 src1, float32 src2) \ | |
892 | { \ | |
893 | target_ulong new_fsr; \ | |
894 | \ | |
895 | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ | |
896 | switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \ | |
897 | case float_relation_unordered: \ | |
898 | new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ | |
899 | if ((env->fsr & FSR_NVM) || TRAP) { \ | |
900 | env->fsr |= new_fsr; \ | |
901 | env->fsr |= FSR_NVC; \ | |
902 | env->fsr |= FSR_FTT_IEEE_EXCP; \ | |
903 | raise_exception(TT_FP_EXCP); \ | |
904 | } else { \ | |
905 | env->fsr |= FSR_NVA; \ | |
906 | } \ | |
907 | break; \ | |
908 | case float_relation_less: \ | |
909 | new_fsr = FSR_FCC0 << FS; \ | |
910 | break; \ | |
911 | case float_relation_greater: \ | |
912 | new_fsr = FSR_FCC1 << FS; \ | |
913 | break; \ | |
914 | default: \ | |
915 | new_fsr = 0; \ | |
916 | break; \ | |
917 | } \ | |
918 | env->fsr |= new_fsr; \ | |
919 | } | |
e8af50a3 | 920 | |
714547bb | 921 | GEN_FCMPS(fcmps, float32, 0, 0); |
417454b0 BS |
922 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
923 | ||
714547bb | 924 | GEN_FCMPS(fcmpes, float32, 0, 1); |
417454b0 | 925 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
3475187d | 926 | |
4e14008f BS |
927 | GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); |
928 | GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); | |
4e14008f | 929 | |
8393617c BS |
930 | static uint32_t compute_all_flags(void) |
931 | { | |
932 | return env->psr & PSR_ICC; | |
933 | } | |
934 | ||
935 | static uint32_t compute_C_flags(void) | |
936 | { | |
937 | return env->psr & PSR_CARRY; | |
938 | } | |
939 | ||
5a4bb580 | 940 | static inline uint32_t get_NZ_icc(int32_t dst) |
bdf9f35d BS |
941 | { |
942 | uint32_t ret = 0; | |
943 | ||
5a4bb580 RH |
944 | if (dst == 0) { |
945 | ret = PSR_ZERO; | |
946 | } else if (dst < 0) { | |
947 | ret = PSR_NEG; | |
948 | } | |
bdf9f35d BS |
949 | return ret; |
950 | } | |
951 | ||
8393617c BS |
952 | #ifdef TARGET_SPARC64 |
953 | static uint32_t compute_all_flags_xcc(void) | |
954 | { | |
955 | return env->xcc & PSR_ICC; | |
956 | } | |
957 | ||
958 | static uint32_t compute_C_flags_xcc(void) | |
959 | { | |
960 | return env->xcc & PSR_CARRY; | |
961 | } | |
962 | ||
5a4bb580 | 963 | static inline uint32_t get_NZ_xcc(target_long dst) |
bdf9f35d BS |
964 | { |
965 | uint32_t ret = 0; | |
966 | ||
5a4bb580 RH |
967 | if (!dst) { |
968 | ret = PSR_ZERO; | |
969 | } else if (dst < 0) { | |
970 | ret = PSR_NEG; | |
971 | } | |
bdf9f35d BS |
972 | return ret; |
973 | } | |
974 | #endif | |
975 | ||
6c78ea32 BS |
976 | static inline uint32_t get_V_div_icc(target_ulong src2) |
977 | { | |
978 | uint32_t ret = 0; | |
979 | ||
5a4bb580 RH |
980 | if (src2 != 0) { |
981 | ret = PSR_OVF; | |
982 | } | |
6c78ea32 BS |
983 | return ret; |
984 | } | |
985 | ||
986 | static uint32_t compute_all_div(void) | |
987 | { | |
988 | uint32_t ret; | |
989 | ||
990 | ret = get_NZ_icc(CC_DST); | |
991 | ret |= get_V_div_icc(CC_SRC2); | |
992 | return ret; | |
993 | } | |
994 | ||
995 | static uint32_t compute_C_div(void) | |
996 | { | |
997 | return 0; | |
998 | } | |
999 | ||
5a4bb580 | 1000 | static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1) |
bdf9f35d BS |
1001 | { |
1002 | uint32_t ret = 0; | |
1003 | ||
5a4bb580 RH |
1004 | if (dst < src1) { |
1005 | ret = PSR_CARRY; | |
1006 | } | |
bdf9f35d BS |
1007 | return ret; |
1008 | } | |
1009 | ||
5a4bb580 RH |
1010 | static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1, |
1011 | uint32_t src2) | |
bdf9f35d BS |
1012 | { |
1013 | uint32_t ret = 0; | |
1014 | ||
5a4bb580 RH |
1015 | if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) { |
1016 | ret = PSR_CARRY; | |
1017 | } | |
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1, | |
1022 | uint32_t src2) | |
1023 | { | |
1024 | uint32_t ret = 0; | |
1025 | ||
1026 | if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) { | |
1027 | ret = PSR_OVF; | |
1028 | } | |
bdf9f35d BS |
1029 | return ret; |
1030 | } | |
1031 | ||
bdf9f35d BS |
1032 | #ifdef TARGET_SPARC64 |
1033 | static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1) | |
1034 | { | |
1035 | uint32_t ret = 0; | |
1036 | ||
5a4bb580 RH |
1037 | if (dst < src1) { |
1038 | ret = PSR_CARRY; | |
1039 | } | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1, | |
1044 | target_ulong src2) | |
1045 | { | |
1046 | uint32_t ret = 0; | |
1047 | ||
1048 | if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) { | |
1049 | ret = PSR_CARRY; | |
1050 | } | |
bdf9f35d BS |
1051 | return ret; |
1052 | } | |
1053 | ||
1054 | static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1, | |
1055 | target_ulong src2) | |
1056 | { | |
1057 | uint32_t ret = 0; | |
1058 | ||
5a4bb580 RH |
1059 | if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) { |
1060 | ret = PSR_OVF; | |
1061 | } | |
bdf9f35d BS |
1062 | return ret; |
1063 | } | |
1064 | ||
1065 | static uint32_t compute_all_add_xcc(void) | |
1066 | { | |
1067 | uint32_t ret; | |
1068 | ||
1069 | ret = get_NZ_xcc(CC_DST); | |
1070 | ret |= get_C_add_xcc(CC_DST, CC_SRC); | |
1071 | ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); | |
1072 | return ret; | |
1073 | } | |
1074 | ||
1075 | static uint32_t compute_C_add_xcc(void) | |
1076 | { | |
1077 | return get_C_add_xcc(CC_DST, CC_SRC); | |
1078 | } | |
8393617c BS |
1079 | #endif |
1080 | ||
3e6ba503 | 1081 | static uint32_t compute_all_add(void) |
789c91ef BS |
1082 | { |
1083 | uint32_t ret; | |
1084 | ||
1085 | ret = get_NZ_icc(CC_DST); | |
5a4bb580 | 1086 | ret |= get_C_add_icc(CC_DST, CC_SRC); |
789c91ef BS |
1087 | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1088 | return ret; | |
1089 | } | |
1090 | ||
3e6ba503 | 1091 | static uint32_t compute_C_add(void) |
789c91ef | 1092 | { |
5a4bb580 | 1093 | return get_C_add_icc(CC_DST, CC_SRC); |
789c91ef BS |
1094 | } |
1095 | ||
1096 | #ifdef TARGET_SPARC64 | |
1097 | static uint32_t compute_all_addx_xcc(void) | |
1098 | { | |
1099 | uint32_t ret; | |
1100 | ||
1101 | ret = get_NZ_xcc(CC_DST); | |
5a4bb580 | 1102 | ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
789c91ef BS |
1103 | ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1104 | return ret; | |
1105 | } | |
1106 | ||
1107 | static uint32_t compute_C_addx_xcc(void) | |
1108 | { | |
1109 | uint32_t ret; | |
1110 | ||
5a4bb580 | 1111 | ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
789c91ef BS |
1112 | return ret; |
1113 | } | |
1114 | #endif | |
1115 | ||
5a4bb580 RH |
1116 | static uint32_t compute_all_addx(void) |
1117 | { | |
1118 | uint32_t ret; | |
1119 | ||
1120 | ret = get_NZ_icc(CC_DST); | |
1121 | ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); | |
1122 | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); | |
1123 | return ret; | |
1124 | } | |
1125 | ||
1126 | static uint32_t compute_C_addx(void) | |
1127 | { | |
1128 | uint32_t ret; | |
1129 | ||
1130 | ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); | |
1131 | return ret; | |
1132 | } | |
1133 | ||
3b2d1e92 BS |
1134 | static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2) |
1135 | { | |
1136 | uint32_t ret = 0; | |
1137 | ||
5a4bb580 RH |
1138 | if ((src1 | src2) & 0x3) { |
1139 | ret = PSR_OVF; | |
1140 | } | |
3b2d1e92 BS |
1141 | return ret; |
1142 | } | |
1143 | ||
1144 | static uint32_t compute_all_tadd(void) | |
1145 | { | |
1146 | uint32_t ret; | |
1147 | ||
1148 | ret = get_NZ_icc(CC_DST); | |
5a4bb580 | 1149 | ret |= get_C_add_icc(CC_DST, CC_SRC); |
3b2d1e92 BS |
1150 | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1151 | ret |= get_V_tag_icc(CC_SRC, CC_SRC2); | |
1152 | return ret; | |
1153 | } | |
1154 | ||
3b2d1e92 BS |
1155 | static uint32_t compute_all_taddtv(void) |
1156 | { | |
1157 | uint32_t ret; | |
1158 | ||
1159 | ret = get_NZ_icc(CC_DST); | |
5a4bb580 | 1160 | ret |= get_C_add_icc(CC_DST, CC_SRC); |
3b2d1e92 BS |
1161 | return ret; |
1162 | } | |
1163 | ||
5a4bb580 | 1164 | static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2) |
3b2d1e92 | 1165 | { |
5a4bb580 RH |
1166 | uint32_t ret = 0; |
1167 | ||
1168 | if (src1 < src2) { | |
1169 | ret = PSR_CARRY; | |
1170 | } | |
1171 | return ret; | |
3b2d1e92 BS |
1172 | } |
1173 | ||
5a4bb580 RH |
1174 | static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1, |
1175 | uint32_t src2) | |
d4b0d468 BS |
1176 | { |
1177 | uint32_t ret = 0; | |
1178 | ||
5a4bb580 RH |
1179 | if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) { |
1180 | ret = PSR_CARRY; | |
1181 | } | |
d4b0d468 BS |
1182 | return ret; |
1183 | } | |
1184 | ||
5a4bb580 RH |
1185 | static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1, |
1186 | uint32_t src2) | |
d4b0d468 BS |
1187 | { |
1188 | uint32_t ret = 0; | |
1189 | ||
5a4bb580 RH |
1190 | if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) { |
1191 | ret = PSR_OVF; | |
1192 | } | |
d4b0d468 BS |
1193 | return ret; |
1194 | } | |
1195 | ||
d4b0d468 BS |
1196 | |
1197 | #ifdef TARGET_SPARC64 | |
1198 | static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2) | |
1199 | { | |
1200 | uint32_t ret = 0; | |
1201 | ||
5a4bb580 RH |
1202 | if (src1 < src2) { |
1203 | ret = PSR_CARRY; | |
1204 | } | |
1205 | return ret; | |
1206 | } | |
1207 | ||
1208 | static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1, | |
1209 | target_ulong src2) | |
1210 | { | |
1211 | uint32_t ret = 0; | |
1212 | ||
1213 | if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) { | |
1214 | ret = PSR_CARRY; | |
1215 | } | |
d4b0d468 BS |
1216 | return ret; |
1217 | } | |
1218 | ||
1219 | static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1, | |
1220 | target_ulong src2) | |
1221 | { | |
1222 | uint32_t ret = 0; | |
1223 | ||
5a4bb580 RH |
1224 | if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) { |
1225 | ret = PSR_OVF; | |
1226 | } | |
d4b0d468 BS |
1227 | return ret; |
1228 | } | |
1229 | ||
1230 | static uint32_t compute_all_sub_xcc(void) | |
1231 | { | |
1232 | uint32_t ret; | |
1233 | ||
1234 | ret = get_NZ_xcc(CC_DST); | |
1235 | ret |= get_C_sub_xcc(CC_SRC, CC_SRC2); | |
1236 | ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); | |
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | static uint32_t compute_C_sub_xcc(void) | |
1241 | { | |
1242 | return get_C_sub_xcc(CC_SRC, CC_SRC2); | |
1243 | } | |
1244 | #endif | |
1245 | ||
3e6ba503 | 1246 | static uint32_t compute_all_sub(void) |
2ca1d92b BS |
1247 | { |
1248 | uint32_t ret; | |
1249 | ||
1250 | ret = get_NZ_icc(CC_DST); | |
5a4bb580 | 1251 | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
2ca1d92b BS |
1252 | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1253 | return ret; | |
1254 | } | |
1255 | ||
3e6ba503 | 1256 | static uint32_t compute_C_sub(void) |
2ca1d92b | 1257 | { |
5a4bb580 | 1258 | return get_C_sub_icc(CC_SRC, CC_SRC2); |
2ca1d92b BS |
1259 | } |
1260 | ||
1261 | #ifdef TARGET_SPARC64 | |
1262 | static uint32_t compute_all_subx_xcc(void) | |
1263 | { | |
1264 | uint32_t ret; | |
1265 | ||
1266 | ret = get_NZ_xcc(CC_DST); | |
5a4bb580 | 1267 | ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
2ca1d92b BS |
1268 | ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | static uint32_t compute_C_subx_xcc(void) | |
1273 | { | |
1274 | uint32_t ret; | |
1275 | ||
5a4bb580 | 1276 | ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
2ca1d92b BS |
1277 | return ret; |
1278 | } | |
1279 | #endif | |
1280 | ||
5a4bb580 | 1281 | static uint32_t compute_all_subx(void) |
3b2d1e92 BS |
1282 | { |
1283 | uint32_t ret; | |
1284 | ||
1285 | ret = get_NZ_icc(CC_DST); | |
5a4bb580 | 1286 | ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
3b2d1e92 | 1287 | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
3b2d1e92 BS |
1288 | return ret; |
1289 | } | |
1290 | ||
5a4bb580 | 1291 | static uint32_t compute_C_subx(void) |
3b2d1e92 | 1292 | { |
5a4bb580 RH |
1293 | uint32_t ret; |
1294 | ||
1295 | ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); | |
1296 | return ret; | |
3b2d1e92 BS |
1297 | } |
1298 | ||
5a4bb580 | 1299 | static uint32_t compute_all_tsub(void) |
3b2d1e92 BS |
1300 | { |
1301 | uint32_t ret; | |
1302 | ||
1303 | ret = get_NZ_icc(CC_DST); | |
5a4bb580 RH |
1304 | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1305 | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); | |
1306 | ret |= get_V_tag_icc(CC_SRC, CC_SRC2); | |
3b2d1e92 BS |
1307 | return ret; |
1308 | } | |
1309 | ||
5a4bb580 | 1310 | static uint32_t compute_all_tsubtv(void) |
3b2d1e92 | 1311 | { |
5a4bb580 RH |
1312 | uint32_t ret; |
1313 | ||
1314 | ret = get_NZ_icc(CC_DST); | |
1315 | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); | |
1316 | return ret; | |
3b2d1e92 BS |
1317 | } |
1318 | ||
38482a77 BS |
1319 | static uint32_t compute_all_logic(void) |
1320 | { | |
1321 | return get_NZ_icc(CC_DST); | |
1322 | } | |
1323 | ||
1324 | static uint32_t compute_C_logic(void) | |
1325 | { | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | #ifdef TARGET_SPARC64 | |
1330 | static uint32_t compute_all_logic_xcc(void) | |
1331 | { | |
1332 | return get_NZ_xcc(CC_DST); | |
1333 | } | |
1334 | #endif | |
1335 | ||
8393617c BS |
1336 | typedef struct CCTable { |
1337 | uint32_t (*compute_all)(void); /* return all the flags */ | |
1338 | uint32_t (*compute_c)(void); /* return the C flag */ | |
1339 | } CCTable; | |
1340 | ||
1341 | static const CCTable icc_table[CC_OP_NB] = { | |
1342 | /* CC_OP_DYNAMIC should never happen */ | |
1343 | [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, | |
6c78ea32 | 1344 | [CC_OP_DIV] = { compute_all_div, compute_C_div }, |
bdf9f35d | 1345 | [CC_OP_ADD] = { compute_all_add, compute_C_add }, |
5a4bb580 RH |
1346 | [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, |
1347 | [CC_OP_TADD] = { compute_all_tadd, compute_C_add }, | |
1348 | [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add }, | |
d4b0d468 | 1349 | [CC_OP_SUB] = { compute_all_sub, compute_C_sub }, |
5a4bb580 RH |
1350 | [CC_OP_SUBX] = { compute_all_subx, compute_C_subx }, |
1351 | [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub }, | |
1352 | [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub }, | |
38482a77 | 1353 | [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, |
8393617c BS |
1354 | }; |
1355 | ||
1356 | #ifdef TARGET_SPARC64 | |
1357 | static const CCTable xcc_table[CC_OP_NB] = { | |
1358 | /* CC_OP_DYNAMIC should never happen */ | |
1359 | [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, | |
6c78ea32 | 1360 | [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic }, |
bdf9f35d | 1361 | [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
789c91ef | 1362 | [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, |
3b2d1e92 BS |
1363 | [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1364 | [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc }, | |
d4b0d468 | 1365 | [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
2ca1d92b | 1366 | [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc }, |
3b2d1e92 BS |
1367 | [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1368 | [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc }, | |
38482a77 | 1369 | [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, |
8393617c BS |
1370 | }; |
1371 | #endif | |
1372 | ||
1373 | void helper_compute_psr(void) | |
1374 | { | |
1375 | uint32_t new_psr; | |
1376 | ||
1377 | new_psr = icc_table[CC_OP].compute_all(); | |
1378 | env->psr = new_psr; | |
1379 | #ifdef TARGET_SPARC64 | |
1380 | new_psr = xcc_table[CC_OP].compute_all(); | |
1381 | env->xcc = new_psr; | |
1382 | #endif | |
1383 | CC_OP = CC_OP_FLAGS; | |
1384 | } | |
1385 | ||
70c48285 | 1386 | uint32_t helper_compute_C_icc(void) |
8393617c BS |
1387 | { |
1388 | uint32_t ret; | |
1389 | ||
1390 | ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT; | |
1391 | return ret; | |
1392 | } | |
1393 | ||
5a834bb4 BS |
1394 | static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
1395 | { | |
1396 | dst[0] = src[0]; | |
1397 | dst[1] = src[1]; | |
1398 | dst[2] = src[2]; | |
1399 | dst[3] = src[3]; | |
1400 | dst[4] = src[4]; | |
1401 | dst[5] = src[5]; | |
1402 | dst[6] = src[6]; | |
1403 | dst[7] = src[7]; | |
1404 | } | |
1405 | ||
1406 | static void set_cwp(int new_cwp) | |
1407 | { | |
1408 | /* put the modified wrap registers at their proper location */ | |
1409 | if (env->cwp == env->nwindows - 1) { | |
1410 | memcpy32(env->regbase, env->regbase + env->nwindows * 16); | |
1411 | } | |
1412 | env->cwp = new_cwp; | |
1413 | ||
1414 | /* put the wrap registers at their temporary location */ | |
1415 | if (new_cwp == env->nwindows - 1) { | |
1416 | memcpy32(env->regbase + env->nwindows * 16, env->regbase); | |
1417 | } | |
1418 | env->regwptr = env->regbase + (new_cwp * 16); | |
1419 | } | |
1420 | ||
1421 | void cpu_set_cwp(CPUState *env1, int new_cwp) | |
1422 | { | |
1423 | CPUState *saved_env; | |
1424 | ||
1425 | saved_env = env; | |
1426 | env = env1; | |
1427 | set_cwp(new_cwp); | |
1428 | env = saved_env; | |
1429 | } | |
1430 | ||
1431 | static target_ulong get_psr(void) | |
1432 | { | |
1433 | helper_compute_psr(); | |
1434 | ||
1435 | #if !defined (TARGET_SPARC64) | |
1436 | return env->version | (env->psr & PSR_ICC) | | |
1437 | (env->psref? PSR_EF : 0) | | |
1438 | (env->psrpil << 8) | | |
1439 | (env->psrs? PSR_S : 0) | | |
1440 | (env->psrps? PSR_PS : 0) | | |
1441 | (env->psret? PSR_ET : 0) | env->cwp; | |
1442 | #else | |
2aae2b8e | 1443 | return env->psr & PSR_ICC; |
5a834bb4 BS |
1444 | #endif |
1445 | } | |
1446 | ||
1447 | target_ulong cpu_get_psr(CPUState *env1) | |
1448 | { | |
1449 | CPUState *saved_env; | |
1450 | target_ulong ret; | |
1451 | ||
1452 | saved_env = env; | |
1453 | env = env1; | |
1454 | ret = get_psr(); | |
1455 | env = saved_env; | |
1456 | return ret; | |
1457 | } | |
1458 | ||
1459 | static void put_psr(target_ulong val) | |
1460 | { | |
1461 | env->psr = val & PSR_ICC; | |
2aae2b8e | 1462 | #if !defined (TARGET_SPARC64) |
5a834bb4 BS |
1463 | env->psref = (val & PSR_EF)? 1 : 0; |
1464 | env->psrpil = (val & PSR_PIL) >> 8; | |
2aae2b8e | 1465 | #endif |
5a834bb4 BS |
1466 | #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) |
1467 | cpu_check_irqs(env); | |
1468 | #endif | |
2aae2b8e | 1469 | #if !defined (TARGET_SPARC64) |
5a834bb4 BS |
1470 | env->psrs = (val & PSR_S)? 1 : 0; |
1471 | env->psrps = (val & PSR_PS)? 1 : 0; | |
5a834bb4 | 1472 | env->psret = (val & PSR_ET)? 1 : 0; |
5a834bb4 | 1473 | set_cwp(val & PSR_CWP); |
2aae2b8e | 1474 | #endif |
5a834bb4 BS |
1475 | env->cc_op = CC_OP_FLAGS; |
1476 | } | |
1477 | ||
1478 | void cpu_put_psr(CPUState *env1, target_ulong val) | |
1479 | { | |
1480 | CPUState *saved_env; | |
1481 | ||
1482 | saved_env = env; | |
1483 | env = env1; | |
1484 | put_psr(val); | |
1485 | env = saved_env; | |
1486 | } | |
1487 | ||
1488 | static int cwp_inc(int cwp) | |
1489 | { | |
1490 | if (unlikely(cwp >= env->nwindows)) { | |
1491 | cwp -= env->nwindows; | |
1492 | } | |
1493 | return cwp; | |
1494 | } | |
1495 | ||
1496 | int cpu_cwp_inc(CPUState *env1, int cwp) | |
1497 | { | |
1498 | CPUState *saved_env; | |
1499 | target_ulong ret; | |
1500 | ||
1501 | saved_env = env; | |
1502 | env = env1; | |
1503 | ret = cwp_inc(cwp); | |
1504 | env = saved_env; | |
1505 | return ret; | |
1506 | } | |
1507 | ||
1508 | static int cwp_dec(int cwp) | |
1509 | { | |
1510 | if (unlikely(cwp < 0)) { | |
1511 | cwp += env->nwindows; | |
1512 | } | |
1513 | return cwp; | |
1514 | } | |
1515 | ||
1516 | int cpu_cwp_dec(CPUState *env1, int cwp) | |
1517 | { | |
1518 | CPUState *saved_env; | |
1519 | target_ulong ret; | |
1520 | ||
1521 | saved_env = env; | |
1522 | env = env1; | |
1523 | ret = cwp_dec(cwp); | |
1524 | env = saved_env; | |
1525 | return ret; | |
1526 | } | |
1527 | ||
3475187d | 1528 | #ifdef TARGET_SPARC64 |
714547bb | 1529 | GEN_FCMPS(fcmps_fcc1, float32, 22, 0); |
417454b0 | 1530 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
64a88d5d | 1531 | GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); |
417454b0 | 1532 | |
714547bb | 1533 | GEN_FCMPS(fcmps_fcc2, float32, 24, 0); |
417454b0 | 1534 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
64a88d5d | 1535 | GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); |
417454b0 | 1536 | |
714547bb | 1537 | GEN_FCMPS(fcmps_fcc3, float32, 26, 0); |
417454b0 | 1538 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
64a88d5d | 1539 | GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); |
417454b0 | 1540 | |
714547bb | 1541 | GEN_FCMPS(fcmpes_fcc1, float32, 22, 1); |
417454b0 | 1542 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
64a88d5d | 1543 | GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); |
3475187d | 1544 | |
714547bb | 1545 | GEN_FCMPS(fcmpes_fcc2, float32, 24, 1); |
417454b0 | 1546 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
64a88d5d | 1547 | GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); |
3475187d | 1548 | |
714547bb | 1549 | GEN_FCMPS(fcmpes_fcc3, float32, 26, 1); |
417454b0 | 1550 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
4e14008f BS |
1551 | GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
1552 | #endif | |
714547bb | 1553 | #undef GEN_FCMPS |
3475187d | 1554 | |
77f193da BS |
1555 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ |
1556 | defined(DEBUG_MXCC) | |
952a328f BS |
1557 | static void dump_mxcc(CPUState *env) |
1558 | { | |
0bf9e31a BS |
1559 | printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1560 | "\n", | |
77f193da BS |
1561 | env->mxccdata[0], env->mxccdata[1], |
1562 | env->mxccdata[2], env->mxccdata[3]); | |
0bf9e31a BS |
1563 | printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1564 | "\n" | |
1565 | " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 | |
1566 | "\n", | |
77f193da BS |
1567 | env->mxccregs[0], env->mxccregs[1], |
1568 | env->mxccregs[2], env->mxccregs[3], | |
1569 | env->mxccregs[4], env->mxccregs[5], | |
1570 | env->mxccregs[6], env->mxccregs[7]); | |
952a328f BS |
1571 | } |
1572 | #endif | |
1573 | ||
1a2fb1c0 BS |
1574 | #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ |
1575 | && defined(DEBUG_ASI) | |
1576 | static void dump_asi(const char *txt, target_ulong addr, int asi, int size, | |
1577 | uint64_t r1) | |
8543e2cf BS |
1578 | { |
1579 | switch (size) | |
1580 | { | |
1581 | case 1: | |
1a2fb1c0 BS |
1582 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
1583 | addr, asi, r1 & 0xff); | |
8543e2cf BS |
1584 | break; |
1585 | case 2: | |
1a2fb1c0 BS |
1586 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
1587 | addr, asi, r1 & 0xffff); | |
8543e2cf BS |
1588 | break; |
1589 | case 4: | |
1a2fb1c0 BS |
1590 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
1591 | addr, asi, r1 & 0xffffffff); | |
8543e2cf BS |
1592 | break; |
1593 | case 8: | |
1a2fb1c0 BS |
1594 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
1595 | addr, asi, r1); | |
8543e2cf BS |
1596 | break; |
1597 | } | |
1598 | } | |
1599 | #endif | |
1600 | ||
1a2fb1c0 BS |
1601 | #ifndef TARGET_SPARC64 |
1602 | #ifndef CONFIG_USER_ONLY | |
1603 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) | |
e8af50a3 | 1604 | { |
1a2fb1c0 | 1605 | uint64_t ret = 0; |
8543e2cf | 1606 | #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) |
1a2fb1c0 | 1607 | uint32_t last_addr = addr; |
952a328f | 1608 | #endif |
e80cfcfc | 1609 | |
c2bc0e38 | 1610 | helper_check_align(addr, size - 1); |
e80cfcfc | 1611 | switch (asi) { |
6c36d3fa | 1612 | case 2: /* SuperSparc MXCC registers */ |
1a2fb1c0 | 1613 | switch (addr) { |
952a328f | 1614 | case 0x01c00a00: /* MXCC control register */ |
1a2fb1c0 BS |
1615 | if (size == 8) |
1616 | ret = env->mxccregs[3]; | |
1617 | else | |
77f193da BS |
1618 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1619 | size); | |
952a328f BS |
1620 | break; |
1621 | case 0x01c00a04: /* MXCC control register */ | |
1622 | if (size == 4) | |
1623 | ret = env->mxccregs[3]; | |
1624 | else | |
77f193da BS |
1625 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1626 | size); | |
952a328f | 1627 | break; |
295db113 BS |
1628 | case 0x01c00c00: /* Module reset register */ |
1629 | if (size == 8) { | |
1a2fb1c0 | 1630 | ret = env->mxccregs[5]; |
295db113 BS |
1631 | // should we do something here? |
1632 | } else | |
77f193da BS |
1633 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1634 | size); | |
295db113 | 1635 | break; |
952a328f | 1636 | case 0x01c00f00: /* MBus port address register */ |
1a2fb1c0 BS |
1637 | if (size == 8) |
1638 | ret = env->mxccregs[7]; | |
1639 | else | |
77f193da BS |
1640 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1641 | size); | |
952a328f BS |
1642 | break; |
1643 | default: | |
77f193da BS |
1644 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, |
1645 | size); | |
952a328f BS |
1646 | break; |
1647 | } | |
77f193da | 1648 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " |
9827e450 | 1649 | "addr = %08x -> ret = %" PRIx64 "," |
1a2fb1c0 | 1650 | "addr = %08x\n", asi, size, sign, last_addr, ret, addr); |
952a328f BS |
1651 | #ifdef DEBUG_MXCC |
1652 | dump_mxcc(env); | |
1653 | #endif | |
6c36d3fa | 1654 | break; |
e8af50a3 | 1655 | case 3: /* MMU probe */ |
0f8a249a BS |
1656 | { |
1657 | int mmulev; | |
1658 | ||
1a2fb1c0 | 1659 | mmulev = (addr >> 8) & 15; |
0f8a249a BS |
1660 | if (mmulev > 4) |
1661 | ret = 0; | |
1a2fb1c0 BS |
1662 | else |
1663 | ret = mmu_probe(env, addr, mmulev); | |
1664 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", | |
1665 | addr, mmulev, ret); | |
0f8a249a BS |
1666 | } |
1667 | break; | |
e8af50a3 | 1668 | case 4: /* read MMU regs */ |
0f8a249a | 1669 | { |
1a2fb1c0 | 1670 | int reg = (addr >> 8) & 0x1f; |
3b46e624 | 1671 | |
0f8a249a BS |
1672 | ret = env->mmuregs[reg]; |
1673 | if (reg == 3) /* Fault status cleared on read */ | |
3dd9a152 BS |
1674 | env->mmuregs[3] = 0; |
1675 | else if (reg == 0x13) /* Fault status read */ | |
1676 | ret = env->mmuregs[3]; | |
1677 | else if (reg == 0x14) /* Fault address read */ | |
1678 | ret = env->mmuregs[4]; | |
1a2fb1c0 | 1679 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
0f8a249a BS |
1680 | } |
1681 | break; | |
045380be BS |
1682 | case 5: // Turbosparc ITLB Diagnostic |
1683 | case 6: // Turbosparc DTLB Diagnostic | |
1684 | case 7: // Turbosparc IOTLB Diagnostic | |
1685 | break; | |
6c36d3fa BS |
1686 | case 9: /* Supervisor code access */ |
1687 | switch(size) { | |
1688 | case 1: | |
1a2fb1c0 | 1689 | ret = ldub_code(addr); |
6c36d3fa BS |
1690 | break; |
1691 | case 2: | |
a4e7dd52 | 1692 | ret = lduw_code(addr); |
6c36d3fa BS |
1693 | break; |
1694 | default: | |
1695 | case 4: | |
a4e7dd52 | 1696 | ret = ldl_code(addr); |
6c36d3fa BS |
1697 | break; |
1698 | case 8: | |
a4e7dd52 | 1699 | ret = ldq_code(addr); |
6c36d3fa BS |
1700 | break; |
1701 | } | |
1702 | break; | |
81ad8ba2 BS |
1703 | case 0xa: /* User data access */ |
1704 | switch(size) { | |
1705 | case 1: | |
1a2fb1c0 | 1706 | ret = ldub_user(addr); |
81ad8ba2 BS |
1707 | break; |
1708 | case 2: | |
a4e7dd52 | 1709 | ret = lduw_user(addr); |
81ad8ba2 BS |
1710 | break; |
1711 | default: | |
1712 | case 4: | |
a4e7dd52 | 1713 | ret = ldl_user(addr); |
81ad8ba2 BS |
1714 | break; |
1715 | case 8: | |
a4e7dd52 | 1716 | ret = ldq_user(addr); |
81ad8ba2 BS |
1717 | break; |
1718 | } | |
1719 | break; | |
1720 | case 0xb: /* Supervisor data access */ | |
1721 | switch(size) { | |
1722 | case 1: | |
1a2fb1c0 | 1723 | ret = ldub_kernel(addr); |
81ad8ba2 BS |
1724 | break; |
1725 | case 2: | |
a4e7dd52 | 1726 | ret = lduw_kernel(addr); |
81ad8ba2 BS |
1727 | break; |
1728 | default: | |
1729 | case 4: | |
a4e7dd52 | 1730 | ret = ldl_kernel(addr); |
81ad8ba2 BS |
1731 | break; |
1732 | case 8: | |
a4e7dd52 | 1733 | ret = ldq_kernel(addr); |
81ad8ba2 BS |
1734 | break; |
1735 | } | |
1736 | break; | |
6c36d3fa BS |
1737 | case 0xc: /* I-cache tag */ |
1738 | case 0xd: /* I-cache data */ | |
1739 | case 0xe: /* D-cache tag */ | |
1740 | case 0xf: /* D-cache data */ | |
1741 | break; | |
1742 | case 0x20: /* MMU passthrough */ | |
02aab46a FB |
1743 | switch(size) { |
1744 | case 1: | |
1a2fb1c0 | 1745 | ret = ldub_phys(addr); |
02aab46a FB |
1746 | break; |
1747 | case 2: | |
a4e7dd52 | 1748 | ret = lduw_phys(addr); |
02aab46a FB |
1749 | break; |
1750 | default: | |
1751 | case 4: | |
a4e7dd52 | 1752 | ret = ldl_phys(addr); |
02aab46a | 1753 | break; |
9e61bde5 | 1754 | case 8: |
a4e7dd52 | 1755 | ret = ldq_phys(addr); |
0f8a249a | 1756 | break; |
02aab46a | 1757 | } |
0f8a249a | 1758 | break; |
7d85892b | 1759 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
5dcb6b91 BS |
1760 | switch(size) { |
1761 | case 1: | |
c227f099 AL |
1762 | ret = ldub_phys((target_phys_addr_t)addr |
1763 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
5dcb6b91 BS |
1764 | break; |
1765 | case 2: | |
c227f099 AL |
1766 | ret = lduw_phys((target_phys_addr_t)addr |
1767 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
5dcb6b91 BS |
1768 | break; |
1769 | default: | |
1770 | case 4: | |
c227f099 AL |
1771 | ret = ldl_phys((target_phys_addr_t)addr |
1772 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
5dcb6b91 BS |
1773 | break; |
1774 | case 8: | |
c227f099 AL |
1775 | ret = ldq_phys((target_phys_addr_t)addr |
1776 | | ((target_phys_addr_t)(asi & 0xf) << 32)); | |
0f8a249a | 1777 | break; |
5dcb6b91 | 1778 | } |
0f8a249a | 1779 | break; |
045380be BS |
1780 | case 0x30: // Turbosparc secondary cache diagnostic |
1781 | case 0x31: // Turbosparc RAM snoop | |
1782 | case 0x32: // Turbosparc page table descriptor diagnostic | |
666c87aa | 1783 | case 0x39: /* data cache diagnostic register */ |
da7ed379 | 1784 | case 0x4c: /* SuperSPARC MMU Breakpoint Action register */ |
666c87aa BS |
1785 | ret = 0; |
1786 | break; | |
4017190e BS |
1787 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ |
1788 | { | |
1789 | int reg = (addr >> 8) & 3; | |
1790 | ||
1791 | switch(reg) { | |
1792 | case 0: /* Breakpoint Value (Addr) */ | |
1793 | ret = env->mmubpregs[reg]; | |
1794 | break; | |
1795 | case 1: /* Breakpoint Mask */ | |
1796 | ret = env->mmubpregs[reg]; | |
1797 | break; | |
1798 | case 2: /* Breakpoint Control */ | |
1799 | ret = env->mmubpregs[reg]; | |
1800 | break; | |
1801 | case 3: /* Breakpoint Status */ | |
1802 | ret = env->mmubpregs[reg]; | |
1803 | env->mmubpregs[reg] = 0ULL; | |
1804 | break; | |
1805 | } | |
0bf9e31a BS |
1806 | DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, |
1807 | ret); | |
4017190e BS |
1808 | } |
1809 | break; | |
045380be | 1810 | case 8: /* User code access, XXX */ |
e8af50a3 | 1811 | default: |
e18231a3 | 1812 | do_unassigned_access(addr, 0, 0, asi, size); |
0f8a249a BS |
1813 | ret = 0; |
1814 | break; | |
e8af50a3 | 1815 | } |
81ad8ba2 BS |
1816 | if (sign) { |
1817 | switch(size) { | |
1818 | case 1: | |
1a2fb1c0 | 1819 | ret = (int8_t) ret; |
e32664fb | 1820 | break; |
81ad8ba2 | 1821 | case 2: |
1a2fb1c0 BS |
1822 | ret = (int16_t) ret; |
1823 | break; | |
1824 | case 4: | |
1825 | ret = (int32_t) ret; | |
e32664fb | 1826 | break; |
81ad8ba2 | 1827 | default: |
81ad8ba2 BS |
1828 | break; |
1829 | } | |
1830 | } | |
8543e2cf | 1831 | #ifdef DEBUG_ASI |
1a2fb1c0 | 1832 | dump_asi("read ", last_addr, asi, size, ret); |
8543e2cf | 1833 | #endif |
1a2fb1c0 | 1834 | return ret; |
e8af50a3 FB |
1835 | } |
1836 | ||
1a2fb1c0 | 1837 | void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
e8af50a3 | 1838 | { |
c2bc0e38 | 1839 | helper_check_align(addr, size - 1); |
e8af50a3 | 1840 | switch(asi) { |
6c36d3fa | 1841 | case 2: /* SuperSparc MXCC registers */ |
1a2fb1c0 | 1842 | switch (addr) { |
952a328f BS |
1843 | case 0x01c00000: /* MXCC stream data register 0 */ |
1844 | if (size == 8) | |
1a2fb1c0 | 1845 | env->mxccdata[0] = val; |
952a328f | 1846 | else |
77f193da BS |
1847 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1848 | size); | |
952a328f BS |
1849 | break; |
1850 | case 0x01c00008: /* MXCC stream data register 1 */ | |
1851 | if (size == 8) | |
1a2fb1c0 | 1852 | env->mxccdata[1] = val; |
952a328f | 1853 | else |
77f193da BS |
1854 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1855 | size); | |
952a328f BS |
1856 | break; |
1857 | case 0x01c00010: /* MXCC stream data register 2 */ | |
1858 | if (size == 8) | |
1a2fb1c0 | 1859 | env->mxccdata[2] = val; |
952a328f | 1860 | else |
77f193da BS |
1861 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1862 | size); | |
952a328f BS |
1863 | break; |
1864 | case 0x01c00018: /* MXCC stream data register 3 */ | |
1865 | if (size == 8) | |
1a2fb1c0 | 1866 | env->mxccdata[3] = val; |
952a328f | 1867 | else |
77f193da BS |
1868 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1869 | size); | |
952a328f BS |
1870 | break; |
1871 | case 0x01c00100: /* MXCC stream source */ | |
1872 | if (size == 8) | |
1a2fb1c0 | 1873 | env->mxccregs[0] = val; |
952a328f | 1874 | else |
77f193da BS |
1875 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1876 | size); | |
1877 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
1878 | 0); | |
1879 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
1880 | 8); | |
1881 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
1882 | 16); | |
1883 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
1884 | 24); | |
952a328f BS |
1885 | break; |
1886 | case 0x01c00200: /* MXCC stream destination */ | |
1887 | if (size == 8) | |
1a2fb1c0 | 1888 | env->mxccregs[1] = val; |
952a328f | 1889 | else |
77f193da BS |
1890 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1891 | size); | |
1892 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, | |
1893 | env->mxccdata[0]); | |
1894 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, | |
1895 | env->mxccdata[1]); | |
1896 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, | |
1897 | env->mxccdata[2]); | |
1898 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, | |
1899 | env->mxccdata[3]); | |
952a328f BS |
1900 | break; |
1901 | case 0x01c00a00: /* MXCC control register */ | |
1902 | if (size == 8) | |
1a2fb1c0 | 1903 | env->mxccregs[3] = val; |
952a328f | 1904 | else |
77f193da BS |
1905 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1906 | size); | |
952a328f BS |
1907 | break; |
1908 | case 0x01c00a04: /* MXCC control register */ | |
1909 | if (size == 4) | |
9f4576f0 | 1910 | env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) |
77f193da | 1911 | | val; |
952a328f | 1912 | else |
77f193da BS |
1913 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1914 | size); | |
952a328f BS |
1915 | break; |
1916 | case 0x01c00e00: /* MXCC error register */ | |
bbf7d96b | 1917 | // writing a 1 bit clears the error |
952a328f | 1918 | if (size == 8) |
1a2fb1c0 | 1919 | env->mxccregs[6] &= ~val; |
952a328f | 1920 | else |
77f193da BS |
1921 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1922 | size); | |
952a328f BS |
1923 | break; |
1924 | case 0x01c00f00: /* MBus port address register */ | |
1925 | if (size == 8) | |
1a2fb1c0 | 1926 | env->mxccregs[7] = val; |
952a328f | 1927 | else |
77f193da BS |
1928 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, |
1929 | size); | |
952a328f BS |
1930 | break; |
1931 | default: | |
77f193da BS |
1932 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, |
1933 | size); | |
952a328f BS |
1934 | break; |
1935 | } | |
9827e450 BS |
1936 | DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", |
1937 | asi, size, addr, val); | |
952a328f BS |
1938 | #ifdef DEBUG_MXCC |
1939 | dump_mxcc(env); | |
1940 | #endif | |
6c36d3fa | 1941 | break; |
e8af50a3 | 1942 | case 3: /* MMU flush */ |
0f8a249a BS |
1943 | { |
1944 | int mmulev; | |
e80cfcfc | 1945 | |
1a2fb1c0 | 1946 | mmulev = (addr >> 8) & 15; |
952a328f | 1947 | DPRINTF_MMU("mmu flush level %d\n", mmulev); |
0f8a249a BS |
1948 | switch (mmulev) { |
1949 | case 0: // flush page | |
1a2fb1c0 | 1950 | tlb_flush_page(env, addr & 0xfffff000); |
0f8a249a BS |
1951 | break; |
1952 | case 1: // flush segment (256k) | |
1953 | case 2: // flush region (16M) | |
1954 | case 3: // flush context (4G) | |
1955 | case 4: // flush entire | |
1956 | tlb_flush(env, 1); | |
1957 | break; | |
1958 | default: | |
1959 | break; | |
1960 | } | |
55754d9e | 1961 | #ifdef DEBUG_MMU |
0f8a249a | 1962 | dump_mmu(env); |
55754d9e | 1963 | #endif |
0f8a249a | 1964 | } |
8543e2cf | 1965 | break; |
e8af50a3 | 1966 | case 4: /* write MMU regs */ |
0f8a249a | 1967 | { |
1a2fb1c0 | 1968 | int reg = (addr >> 8) & 0x1f; |
0f8a249a | 1969 | uint32_t oldreg; |
3b46e624 | 1970 | |
0f8a249a | 1971 | oldreg = env->mmuregs[reg]; |
55754d9e | 1972 | switch(reg) { |
3deaeab7 | 1973 | case 0: // Control Register |
3dd9a152 | 1974 | env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | |
1a2fb1c0 | 1975 | (val & 0x00ffffff); |
0f8a249a BS |
1976 | // Mappings generated during no-fault mode or MMU |
1977 | // disabled mode are invalid in normal mode | |
5578ceab BS |
1978 | if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) != |
1979 | (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) | |
55754d9e FB |
1980 | tlb_flush(env, 1); |
1981 | break; | |
3deaeab7 | 1982 | case 1: // Context Table Pointer Register |
5578ceab | 1983 | env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; |
3deaeab7 BS |
1984 | break; |
1985 | case 2: // Context Register | |
5578ceab | 1986 | env->mmuregs[reg] = val & env->def->mmu_cxr_mask; |
55754d9e FB |
1987 | if (oldreg != env->mmuregs[reg]) { |
1988 | /* we flush when the MMU context changes because | |
1989 | QEMU has no MMU context support */ | |
1990 | tlb_flush(env, 1); | |
1991 | } | |
1992 | break; | |
3deaeab7 BS |
1993 | case 3: // Synchronous Fault Status Register with Clear |
1994 | case 4: // Synchronous Fault Address Register | |
1995 | break; | |
1996 | case 0x10: // TLB Replacement Control Register | |
5578ceab | 1997 | env->mmuregs[reg] = val & env->def->mmu_trcr_mask; |
55754d9e | 1998 | break; |
3deaeab7 | 1999 | case 0x13: // Synchronous Fault Status Register with Read and Clear |
5578ceab | 2000 | env->mmuregs[3] = val & env->def->mmu_sfsr_mask; |
3dd9a152 | 2001 | break; |
3deaeab7 | 2002 | case 0x14: // Synchronous Fault Address Register |
1a2fb1c0 | 2003 | env->mmuregs[4] = val; |
3dd9a152 | 2004 | break; |
55754d9e | 2005 | default: |
1a2fb1c0 | 2006 | env->mmuregs[reg] = val; |
55754d9e FB |
2007 | break; |
2008 | } | |
55754d9e | 2009 | if (oldreg != env->mmuregs[reg]) { |
77f193da BS |
2010 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", |
2011 | reg, oldreg, env->mmuregs[reg]); | |
55754d9e | 2012 | } |
952a328f | 2013 | #ifdef DEBUG_MMU |
0f8a249a | 2014 | dump_mmu(env); |
55754d9e | 2015 | #endif |
0f8a249a | 2016 | } |
8543e2cf | 2017 | break; |
045380be BS |
2018 | case 5: // Turbosparc ITLB Diagnostic |
2019 | case 6: // Turbosparc DTLB Diagnostic | |
2020 | case 7: // Turbosparc IOTLB Diagnostic | |
2021 | break; | |
81ad8ba2 BS |
2022 | case 0xa: /* User data access */ |
2023 | switch(size) { | |
2024 | case 1: | |
1a2fb1c0 | 2025 | stb_user(addr, val); |
81ad8ba2 BS |
2026 | break; |
2027 | case 2: | |
a4e7dd52 | 2028 | stw_user(addr, val); |
81ad8ba2 BS |
2029 | break; |
2030 | default: | |
2031 | case 4: | |
a4e7dd52 | 2032 | stl_user(addr, val); |
81ad8ba2 BS |
2033 | break; |
2034 | case 8: | |
a4e7dd52 | 2035 | stq_user(addr, val); |
81ad8ba2 BS |
2036 | break; |
2037 | } | |
2038 | break; | |
2039 | case 0xb: /* Supervisor data access */ | |
2040 | switch(size) { | |
2041 | case 1: | |
1a2fb1c0 | 2042 | stb_kernel(addr, val); |
81ad8ba2 BS |
2043 | break; |
2044 | case 2: | |
a4e7dd52 | 2045 | stw_kernel(addr, val); |
81ad8ba2 BS |
2046 | break; |
2047 | default: | |
2048 | case 4: | |
a4e7dd52 | 2049 | stl_kernel(addr, val); |
81ad8ba2 BS |
2050 | break; |
2051 | case 8: | |
a4e7dd52 | 2052 | stq_kernel(addr, val); |
81ad8ba2 BS |
2053 | break; |
2054 | } | |
2055 | break; | |
6c36d3fa BS |
2056 | case 0xc: /* I-cache tag */ |
2057 | case 0xd: /* I-cache data */ | |
2058 | case 0xe: /* D-cache tag */ | |
2059 | case 0xf: /* D-cache data */ | |
2060 | case 0x10: /* I/D-cache flush page */ | |
2061 | case 0x11: /* I/D-cache flush segment */ | |
2062 | case 0x12: /* I/D-cache flush region */ | |
2063 | case 0x13: /* I/D-cache flush context */ | |
2064 | case 0x14: /* I/D-cache flush user */ | |
2065 | break; | |
e80cfcfc | 2066 | case 0x17: /* Block copy, sta access */ |
0f8a249a | 2067 | { |
1a2fb1c0 BS |
2068 | // val = src |
2069 | // addr = dst | |
0f8a249a | 2070 | // copy 32 bytes |
6c36d3fa | 2071 | unsigned int i; |
1a2fb1c0 | 2072 | uint32_t src = val & ~3, dst = addr & ~3, temp; |
3b46e624 | 2073 | |
6c36d3fa BS |
2074 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
2075 | temp = ldl_kernel(src); | |
2076 | stl_kernel(dst, temp); | |
2077 | } | |
0f8a249a | 2078 | } |
8543e2cf | 2079 | break; |
e80cfcfc | 2080 | case 0x1f: /* Block fill, stda access */ |
0f8a249a | 2081 | { |
1a2fb1c0 BS |
2082 | // addr = dst |
2083 | // fill 32 bytes with val | |
6c36d3fa | 2084 | unsigned int i; |
1a2fb1c0 | 2085 | uint32_t dst = addr & 7; |
6c36d3fa BS |
2086 | |
2087 | for (i = 0; i < 32; i += 8, dst += 8) | |
2088 | stq_kernel(dst, val); | |
0f8a249a | 2089 | } |
8543e2cf | 2090 | break; |
6c36d3fa | 2091 | case 0x20: /* MMU passthrough */ |
0f8a249a | 2092 | { |
02aab46a FB |
2093 | switch(size) { |
2094 | case 1: | |
1a2fb1c0 | 2095 | stb_phys(addr, val); |
02aab46a FB |
2096 | break; |
2097 | case 2: | |
a4e7dd52 | 2098 | stw_phys(addr, val); |
02aab46a FB |
2099 | break; |
2100 | case 4: | |
2101 | default: | |
a4e7dd52 | 2102 | stl_phys(addr, val); |
02aab46a | 2103 | break; |
9e61bde5 | 2104 | case 8: |
a4e7dd52 | 2105 | stq_phys(addr, val); |
9e61bde5 | 2106 | break; |
02aab46a | 2107 | } |
0f8a249a | 2108 | } |
8543e2cf | 2109 | break; |
045380be | 2110 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
0f8a249a | 2111 | { |
5dcb6b91 BS |
2112 | switch(size) { |
2113 | case 1: | |
c227f099 AL |
2114 | stb_phys((target_phys_addr_t)addr |
2115 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
2116 | break; |
2117 | case 2: | |
c227f099 AL |
2118 | stw_phys((target_phys_addr_t)addr |
2119 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
2120 | break; |
2121 | case 4: | |
2122 | default: | |
c227f099 AL |
2123 | stl_phys((target_phys_addr_t)addr |
2124 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
2125 | break; |
2126 | case 8: | |
c227f099 AL |
2127 | stq_phys((target_phys_addr_t)addr |
2128 | | ((target_phys_addr_t)(asi & 0xf) << 32), val); | |
5dcb6b91 BS |
2129 | break; |
2130 | } | |
0f8a249a | 2131 | } |
8543e2cf | 2132 | break; |
045380be BS |
2133 | case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
2134 | case 0x31: // store buffer data, Ross RT620 I-cache flush or | |
2135 | // Turbosparc snoop RAM | |
77f193da BS |
2136 | case 0x32: // store buffer control or Turbosparc page table |
2137 | // descriptor diagnostic | |
6c36d3fa BS |
2138 | case 0x36: /* I-cache flash clear */ |
2139 | case 0x37: /* D-cache flash clear */ | |
666c87aa | 2140 | case 0x4c: /* breakpoint action */ |
6c36d3fa | 2141 | break; |
4017190e BS |
2142 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ |
2143 | { | |
2144 | int reg = (addr >> 8) & 3; | |
2145 | ||
2146 | switch(reg) { | |
2147 | case 0: /* Breakpoint Value (Addr) */ | |
2148 | env->mmubpregs[reg] = (val & 0xfffffffffULL); | |
2149 | break; | |
2150 | case 1: /* Breakpoint Mask */ | |
2151 | env->mmubpregs[reg] = (val & 0xfffffffffULL); | |
2152 | break; | |
2153 | case 2: /* Breakpoint Control */ | |
2154 | env->mmubpregs[reg] = (val & 0x7fULL); | |
2155 | break; | |
2156 | case 3: /* Breakpoint Status */ | |
2157 | env->mmubpregs[reg] = (val & 0xfULL); | |
2158 | break; | |
2159 | } | |
0bf9e31a | 2160 | DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, |
4017190e BS |
2161 | env->mmuregs[reg]); |
2162 | } | |
2163 | break; | |
045380be | 2164 | case 8: /* User code access, XXX */ |
6c36d3fa | 2165 | case 9: /* Supervisor code access, XXX */ |
e8af50a3 | 2166 | default: |
e18231a3 | 2167 | do_unassigned_access(addr, 1, 0, asi, size); |
8543e2cf | 2168 | break; |
e8af50a3 | 2169 | } |
8543e2cf | 2170 | #ifdef DEBUG_ASI |
1a2fb1c0 | 2171 | dump_asi("write", addr, asi, size, val); |
8543e2cf | 2172 | #endif |
e8af50a3 FB |
2173 | } |
2174 | ||
81ad8ba2 BS |
2175 | #endif /* CONFIG_USER_ONLY */ |
2176 | #else /* TARGET_SPARC64 */ | |
2177 | ||
2178 | #ifdef CONFIG_USER_ONLY | |
1a2fb1c0 | 2179 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
81ad8ba2 BS |
2180 | { |
2181 | uint64_t ret = 0; | |
1a2fb1c0 BS |
2182 | #if defined(DEBUG_ASI) |
2183 | target_ulong last_addr = addr; | |
2184 | #endif | |
81ad8ba2 BS |
2185 | |
2186 | if (asi < 0x80) | |
2187 | raise_exception(TT_PRIV_ACT); | |
2188 | ||
c2bc0e38 | 2189 | helper_check_align(addr, size - 1); |
1295001c | 2190 | addr = asi_address_mask(env, asi, addr); |
c2bc0e38 | 2191 | |
81ad8ba2 | 2192 | switch (asi) { |
81ad8ba2 | 2193 | case 0x82: // Primary no-fault |
81ad8ba2 | 2194 | case 0x8a: // Primary no-fault LE |
e83ce550 BS |
2195 | if (page_check_range(addr, size, PAGE_READ) == -1) { |
2196 | #ifdef DEBUG_ASI | |
2197 | dump_asi("read ", last_addr, asi, size, ret); | |
2198 | #endif | |
2199 | return 0; | |
2200 | } | |
2201 | // Fall through | |
2202 | case 0x80: // Primary | |
2203 | case 0x88: // Primary LE | |
81ad8ba2 BS |
2204 | { |
2205 | switch(size) { | |
2206 | case 1: | |
1a2fb1c0 | 2207 | ret = ldub_raw(addr); |
81ad8ba2 BS |
2208 | break; |
2209 | case 2: | |
a4e7dd52 | 2210 | ret = lduw_raw(addr); |
81ad8ba2 BS |
2211 | break; |
2212 | case 4: | |
a4e7dd52 | 2213 | ret = ldl_raw(addr); |
81ad8ba2 BS |
2214 | break; |
2215 | default: | |
2216 | case 8: | |
a4e7dd52 | 2217 | ret = ldq_raw(addr); |
81ad8ba2 BS |
2218 | break; |
2219 | } | |
2220 | } | |
2221 | break; | |
81ad8ba2 | 2222 | case 0x83: // Secondary no-fault |
81ad8ba2 | 2223 | case 0x8b: // Secondary no-fault LE |
e83ce550 BS |
2224 | if (page_check_range(addr, size, PAGE_READ) == -1) { |
2225 | #ifdef DEBUG_ASI | |
2226 | dump_asi("read ", last_addr, asi, size, ret); | |
2227 | #endif | |
2228 | return 0; | |
2229 | } | |
2230 | // Fall through | |
2231 | case 0x81: // Secondary | |
2232 | case 0x89: // Secondary LE | |
81ad8ba2 BS |
2233 | // XXX |
2234 | break; | |
2235 | default: | |
2236 | break; | |
2237 | } | |
2238 | ||
2239 | /* Convert from little endian */ | |
2240 | switch (asi) { | |
2241 | case 0x88: // Primary LE | |
2242 | case 0x89: // Secondary LE | |
2243 | case 0x8a: // Primary no-fault LE | |
2244 | case 0x8b: // Secondary no-fault LE | |
2245 | switch(size) { | |
2246 | case 2: | |
2247 | ret = bswap16(ret); | |
e32664fb | 2248 | break; |
81ad8ba2 BS |
2249 | case 4: |
2250 | ret = bswap32(ret); | |
e32664fb | 2251 | break; |
81ad8ba2 BS |
2252 | case 8: |
2253 | ret = bswap64(ret); | |
e32664fb | 2254 | break; |
81ad8ba2 BS |
2255 | default: |
2256 | break; | |
2257 | } | |
2258 | default: | |
2259 | break; | |
2260 | } | |
2261 | ||
2262 | /* Convert to signed number */ | |
2263 | if (sign) { | |
2264 | switch(size) { | |
2265 | case 1: | |
2266 | ret = (int8_t) ret; | |
e32664fb | 2267 | break; |
81ad8ba2 BS |
2268 | case 2: |
2269 | ret = (int16_t) ret; | |
e32664fb | 2270 | break; |
81ad8ba2 BS |
2271 | case 4: |
2272 | ret = (int32_t) ret; | |
e32664fb | 2273 | break; |
81ad8ba2 BS |
2274 | default: |
2275 | break; | |
2276 | } | |
2277 | } | |
1a2fb1c0 BS |
2278 | #ifdef DEBUG_ASI |
2279 | dump_asi("read ", last_addr, asi, size, ret); | |
2280 | #endif | |
2281 | return ret; | |
81ad8ba2 BS |
2282 | } |
2283 | ||
1a2fb1c0 | 2284 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
81ad8ba2 | 2285 | { |
1a2fb1c0 BS |
2286 | #ifdef DEBUG_ASI |
2287 | dump_asi("write", addr, asi, size, val); | |
2288 | #endif | |
81ad8ba2 BS |
2289 | if (asi < 0x80) |
2290 | raise_exception(TT_PRIV_ACT); | |
2291 | ||
c2bc0e38 | 2292 | helper_check_align(addr, size - 1); |
1295001c | 2293 | addr = asi_address_mask(env, asi, addr); |
c2bc0e38 | 2294 | |
81ad8ba2 BS |
2295 | /* Convert to little endian */ |
2296 | switch (asi) { | |
2297 | case 0x88: // Primary LE | |
2298 | case 0x89: // Secondary LE | |
2299 | switch(size) { | |
2300 | case 2: | |
5b0f0bec | 2301 | val = bswap16(val); |
e32664fb | 2302 | break; |
81ad8ba2 | 2303 | case 4: |
5b0f0bec | 2304 | val = bswap32(val); |
e32664fb | 2305 | break; |
81ad8ba2 | 2306 | case 8: |
5b0f0bec | 2307 | val = bswap64(val); |
e32664fb | 2308 | break; |
81ad8ba2 BS |
2309 | default: |
2310 | break; | |
2311 | } | |
2312 | default: | |
2313 | break; | |
2314 | } | |
2315 | ||
2316 | switch(asi) { | |
2317 | case 0x80: // Primary | |
2318 | case 0x88: // Primary LE | |
2319 | { | |
2320 | switch(size) { | |
2321 | case 1: | |
1a2fb1c0 | 2322 | stb_raw(addr, val); |
81ad8ba2 BS |
2323 | break; |
2324 | case 2: | |
a4e7dd52 | 2325 | stw_raw(addr, val); |
81ad8ba2 BS |
2326 | break; |
2327 | case 4: | |
a4e7dd52 | 2328 | stl_raw(addr, val); |
81ad8ba2 BS |
2329 | break; |
2330 | case 8: | |
2331 | default: | |
a4e7dd52 | 2332 | stq_raw(addr, val); |
81ad8ba2 BS |
2333 | break; |
2334 | } | |
2335 | } | |
2336 | break; | |
2337 | case 0x81: // Secondary | |
2338 | case 0x89: // Secondary LE | |
2339 | // XXX | |
2340 | return; | |
2341 | ||
2342 | case 0x82: // Primary no-fault, RO | |
2343 | case 0x83: // Secondary no-fault, RO | |
2344 | case 0x8a: // Primary no-fault LE, RO | |
2345 | case 0x8b: // Secondary no-fault LE, RO | |
2346 | default: | |
e18231a3 | 2347 | do_unassigned_access(addr, 1, 0, 1, size); |
81ad8ba2 BS |
2348 | return; |
2349 | } | |
2350 | } | |
2351 | ||
2352 | #else /* CONFIG_USER_ONLY */ | |
3475187d | 2353 | |
1a2fb1c0 | 2354 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
3475187d | 2355 | { |
83469015 | 2356 | uint64_t ret = 0; |
1a2fb1c0 BS |
2357 | #if defined(DEBUG_ASI) |
2358 | target_ulong last_addr = addr; | |
2359 | #endif | |
3475187d | 2360 | |
01b5d4e5 IK |
2361 | asi &= 0xff; |
2362 | ||
6f27aba6 | 2363 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2aae2b8e | 2364 | || (cpu_has_hypervisor(env) |
5578ceab | 2365 | && asi >= 0x30 && asi < 0x80 |
fb79ceb9 | 2366 | && !(env->hpstate & HS_PRIV))) |
0f8a249a | 2367 | raise_exception(TT_PRIV_ACT); |
3475187d | 2368 | |
c2bc0e38 | 2369 | helper_check_align(addr, size - 1); |
1295001c IK |
2370 | addr = asi_address_mask(env, asi, addr); |
2371 | ||
3475187d | 2372 | switch (asi) { |
e83ce550 BS |
2373 | case 0x82: // Primary no-fault |
2374 | case 0x8a: // Primary no-fault LE | |
2065061e IK |
2375 | case 0x83: // Secondary no-fault |
2376 | case 0x8b: // Secondary no-fault LE | |
2377 | { | |
2378 | /* secondary space access has lowest asi bit equal to 1 */ | |
2379 | int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX | |
2380 | : MMU_KERNEL_SECONDARY_IDX; | |
2381 | ||
2382 | if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) { | |
e83ce550 | 2383 | #ifdef DEBUG_ASI |
2065061e | 2384 | dump_asi("read ", last_addr, asi, size, ret); |
e83ce550 | 2385 | #endif |
2065061e IK |
2386 | return 0; |
2387 | } | |
e83ce550 BS |
2388 | } |
2389 | // Fall through | |
81ad8ba2 | 2390 | case 0x10: // As if user primary |
2065061e | 2391 | case 0x11: // As if user secondary |
81ad8ba2 | 2392 | case 0x18: // As if user primary LE |
2065061e | 2393 | case 0x19: // As if user secondary LE |
81ad8ba2 | 2394 | case 0x80: // Primary |
2065061e | 2395 | case 0x81: // Secondary |
81ad8ba2 | 2396 | case 0x88: // Primary LE |
2065061e | 2397 | case 0x89: // Secondary LE |
c99657d3 BS |
2398 | case 0xe2: // UA2007 Primary block init |
2399 | case 0xe3: // UA2007 Secondary block init | |
81ad8ba2 | 2400 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2aae2b8e | 2401 | if (cpu_hypervisor_mode(env)) { |
6f27aba6 BS |
2402 | switch(size) { |
2403 | case 1: | |
1a2fb1c0 | 2404 | ret = ldub_hypv(addr); |
6f27aba6 BS |
2405 | break; |
2406 | case 2: | |
a4e7dd52 | 2407 | ret = lduw_hypv(addr); |
6f27aba6 BS |
2408 | break; |
2409 | case 4: | |
a4e7dd52 | 2410 | ret = ldl_hypv(addr); |
6f27aba6 BS |
2411 | break; |
2412 | default: | |
2413 | case 8: | |
a4e7dd52 | 2414 | ret = ldq_hypv(addr); |
6f27aba6 BS |
2415 | break; |
2416 | } | |
2417 | } else { | |
2065061e IK |
2418 | /* secondary space access has lowest asi bit equal to 1 */ |
2419 | if (asi & 1) { | |
2420 | switch(size) { | |
2421 | case 1: | |
2422 | ret = ldub_kernel_secondary(addr); | |
2423 | break; | |
2424 | case 2: | |
2425 | ret = lduw_kernel_secondary(addr); | |
2426 | break; | |
2427 | case 4: | |
2428 | ret = ldl_kernel_secondary(addr); | |
2429 | break; | |
2430 | default: | |
2431 | case 8: | |
2432 | ret = ldq_kernel_secondary(addr); | |
2433 | break; | |
2434 | } | |
2435 | } else { | |
2436 | switch(size) { | |
2437 | case 1: | |
2438 | ret = ldub_kernel(addr); | |
2439 | break; | |
2440 | case 2: | |
2441 | ret = lduw_kernel(addr); | |
2442 | break; | |
2443 | case 4: | |
2444 | ret = ldl_kernel(addr); | |
2445 | break; | |
2446 | default: | |
2447 | case 8: | |
2448 | ret = ldq_kernel(addr); | |
2449 | break; | |
2450 | } | |
2451 | } | |
2452 | } | |
2453 | } else { | |
2454 | /* secondary space access has lowest asi bit equal to 1 */ | |
2455 | if (asi & 1) { | |
6f27aba6 BS |
2456 | switch(size) { |
2457 | case 1: | |
2065061e | 2458 | ret = ldub_user_secondary(addr); |
6f27aba6 BS |
2459 | break; |
2460 | case 2: | |
2065061e | 2461 | ret = lduw_user_secondary(addr); |
6f27aba6 BS |
2462 | break; |
2463 | case 4: | |
2065061e | 2464 | ret = ldl_user_secondary(addr); |
6f27aba6 BS |
2465 | break; |
2466 | default: | |
2467 | case 8: | |
2065061e IK |
2468 | ret = ldq_user_secondary(addr); |
2469 | break; | |
2470 | } | |
2471 | } else { | |
2472 | switch(size) { | |
2473 | case 1: | |
2474 | ret = ldub_user(addr); | |
2475 | break; | |
2476 | case 2: | |
2477 | ret = lduw_user(addr); | |
2478 | break; | |
2479 | case 4: | |
2480 | ret = ldl_user(addr); | |
2481 | break; | |
2482 | default: | |
2483 | case 8: | |
2484 | ret = ldq_user(addr); | |
6f27aba6 BS |
2485 | break; |
2486 | } | |
81ad8ba2 BS |
2487 | } |
2488 | } | |
2489 | break; | |
3475187d FB |
2490 | case 0x14: // Bypass |
2491 | case 0x15: // Bypass, non-cacheable | |
81ad8ba2 BS |
2492 | case 0x1c: // Bypass LE |
2493 | case 0x1d: // Bypass, non-cacheable LE | |
0f8a249a | 2494 | { |
02aab46a FB |
2495 | switch(size) { |
2496 | case 1: | |
1a2fb1c0 | 2497 | ret = ldub_phys(addr); |
02aab46a FB |
2498 | break; |
2499 | case 2: | |
a4e7dd52 | 2500 | ret = lduw_phys(addr); |
02aab46a FB |
2501 | break; |
2502 | case 4: | |
a4e7dd52 | 2503 | ret = ldl_phys(addr); |
02aab46a FB |
2504 | break; |
2505 | default: | |
2506 | case 8: | |
a4e7dd52 | 2507 | ret = ldq_phys(addr); |
02aab46a FB |
2508 | break; |
2509 | } | |
0f8a249a BS |
2510 | break; |
2511 | } | |
db166940 BS |
2512 | case 0x24: // Nucleus quad LDD 128 bit atomic |
2513 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE | |
2514 | // Only ldda allowed | |
2515 | raise_exception(TT_ILL_INSN); | |
2516 | return 0; | |
83469015 FB |
2517 | case 0x04: // Nucleus |
2518 | case 0x0c: // Nucleus Little Endian (LE) | |
2065061e IK |
2519 | { |
2520 | switch(size) { | |
2521 | case 1: | |
2522 | ret = ldub_nucleus(addr); | |
2523 | break; | |
2524 | case 2: | |
2525 | ret = lduw_nucleus(addr); | |
2526 | break; | |
2527 | case 4: | |
2528 | ret = ldl_nucleus(addr); | |
2529 | break; | |
2530 | default: | |
2531 | case 8: | |
2532 | ret = ldq_nucleus(addr); | |
2533 | break; | |
2534 | } | |
2535 | break; | |
2536 | } | |
83469015 | 2537 | case 0x4a: // UPA config |
0f8a249a BS |
2538 | // XXX |
2539 | break; | |
3475187d | 2540 | case 0x45: // LSU |
0f8a249a BS |
2541 | ret = env->lsu; |
2542 | break; | |
3475187d | 2543 | case 0x50: // I-MMU regs |
0f8a249a | 2544 | { |
1a2fb1c0 | 2545 | int reg = (addr >> 3) & 0xf; |
3475187d | 2546 | |
697a77e6 IK |
2547 | if (reg == 0) { |
2548 | // I-TSB Tag Target register | |
6e8e7d4c | 2549 | ret = ultrasparc_tag_target(env->immu.tag_access); |
697a77e6 IK |
2550 | } else { |
2551 | ret = env->immuregs[reg]; | |
2552 | } | |
2553 | ||
0f8a249a BS |
2554 | break; |
2555 | } | |
3475187d | 2556 | case 0x51: // I-MMU 8k TSB pointer |
697a77e6 IK |
2557 | { |
2558 | // env->immuregs[5] holds I-MMU TSB register value | |
2559 | // env->immuregs[6] holds I-MMU Tag Access register value | |
6e8e7d4c | 2560 | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
697a77e6 IK |
2561 | 8*1024); |
2562 | break; | |
2563 | } | |
3475187d | 2564 | case 0x52: // I-MMU 64k TSB pointer |
697a77e6 IK |
2565 | { |
2566 | // env->immuregs[5] holds I-MMU TSB register value | |
2567 | // env->immuregs[6] holds I-MMU Tag Access register value | |
6e8e7d4c | 2568 | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
697a77e6 IK |
2569 | 64*1024); |
2570 | break; | |
2571 | } | |
a5a52cf2 BS |
2572 | case 0x55: // I-MMU data access |
2573 | { | |
2574 | int reg = (addr >> 3) & 0x3f; | |
2575 | ||
6e8e7d4c | 2576 | ret = env->itlb[reg].tte; |
a5a52cf2 BS |
2577 | break; |
2578 | } | |
83469015 | 2579 | case 0x56: // I-MMU tag read |
0f8a249a | 2580 | { |
43e9e742 | 2581 | int reg = (addr >> 3) & 0x3f; |
0f8a249a | 2582 | |
6e8e7d4c | 2583 | ret = env->itlb[reg].tag; |
0f8a249a BS |
2584 | break; |
2585 | } | |
3475187d | 2586 | case 0x58: // D-MMU regs |
0f8a249a | 2587 | { |
1a2fb1c0 | 2588 | int reg = (addr >> 3) & 0xf; |
3475187d | 2589 | |
697a77e6 IK |
2590 | if (reg == 0) { |
2591 | // D-TSB Tag Target register | |
6e8e7d4c | 2592 | ret = ultrasparc_tag_target(env->dmmu.tag_access); |
697a77e6 IK |
2593 | } else { |
2594 | ret = env->dmmuregs[reg]; | |
2595 | } | |
2596 | break; | |
2597 | } | |
2598 | case 0x59: // D-MMU 8k TSB pointer | |
2599 | { | |
2600 | // env->dmmuregs[5] holds D-MMU TSB register value | |
2601 | // env->dmmuregs[6] holds D-MMU Tag Access register value | |
6e8e7d4c | 2602 | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
697a77e6 IK |
2603 | 8*1024); |
2604 | break; | |
2605 | } | |
2606 | case 0x5a: // D-MMU 64k TSB pointer | |
2607 | { | |
2608 | // env->dmmuregs[5] holds D-MMU TSB register value | |
2609 | // env->dmmuregs[6] holds D-MMU Tag Access register value | |
6e8e7d4c | 2610 | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
697a77e6 | 2611 | 64*1024); |
0f8a249a BS |
2612 | break; |
2613 | } | |
a5a52cf2 BS |
2614 | case 0x5d: // D-MMU data access |
2615 | { | |
2616 | int reg = (addr >> 3) & 0x3f; | |
2617 | ||
6e8e7d4c | 2618 | ret = env->dtlb[reg].tte; |
a5a52cf2 BS |
2619 | break; |
2620 | } | |
83469015 | 2621 | case 0x5e: // D-MMU tag read |
0f8a249a | 2622 | { |
43e9e742 | 2623 | int reg = (addr >> 3) & 0x3f; |
0f8a249a | 2624 | |
6e8e7d4c | 2625 | ret = env->dtlb[reg].tag; |
0f8a249a BS |
2626 | break; |
2627 | } | |
f7350b47 BS |
2628 | case 0x46: // D-cache data |
2629 | case 0x47: // D-cache tag access | |
a5a52cf2 BS |
2630 | case 0x4b: // E-cache error enable |
2631 | case 0x4c: // E-cache asynchronous fault status | |
2632 | case 0x4d: // E-cache asynchronous fault address | |
f7350b47 BS |
2633 | case 0x4e: // E-cache tag data |
2634 | case 0x66: // I-cache instruction access | |
2635 | case 0x67: // I-cache tag access | |
2636 | case 0x6e: // I-cache predecode | |
2637 | case 0x6f: // I-cache LRU etc. | |
2638 | case 0x76: // E-cache tag | |
2639 | case 0x7e: // E-cache tag | |
2640 | break; | |
3475187d | 2641 | case 0x5b: // D-MMU data pointer |
83469015 FB |
2642 | case 0x48: // Interrupt dispatch, RO |
2643 | case 0x49: // Interrupt data receive | |
2644 | case 0x7f: // Incoming interrupt vector, RO | |
0f8a249a BS |
2645 | // XXX |
2646 | break; | |
3475187d FB |
2647 | case 0x54: // I-MMU data in, WO |
2648 | case 0x57: // I-MMU demap, WO | |
2649 | case 0x5c: // D-MMU data in, WO | |
2650 | case 0x5f: // D-MMU demap, WO | |
83469015 | 2651 | case 0x77: // Interrupt vector, WO |
3475187d | 2652 | default: |
e18231a3 | 2653 | do_unassigned_access(addr, 0, 0, 1, size); |
0f8a249a BS |
2654 | ret = 0; |
2655 | break; | |
3475187d | 2656 | } |
81ad8ba2 BS |
2657 | |
2658 | /* Convert from little endian */ | |
2659 | switch (asi) { | |
2660 | case 0x0c: // Nucleus Little Endian (LE) | |
2661 | case 0x18: // As if user primary LE | |
2662 | case 0x19: // As if user secondary LE | |
2663 | case 0x1c: // Bypass LE | |
2664 | case 0x1d: // Bypass, non-cacheable LE | |
2665 | case 0x88: // Primary LE | |
2666 | case 0x89: // Secondary LE | |
2667 | case 0x8a: // Primary no-fault LE | |
2668 | case 0x8b: // Secondary no-fault LE | |
2669 | switch(size) { | |
2670 | case 2: | |
2671 | ret = bswap16(ret); | |
e32664fb | 2672 | break; |
81ad8ba2 BS |
2673 | case 4: |
2674 | ret = bswap32(ret); | |
e32664fb | 2675 | break; |
81ad8ba2 BS |
2676 | case 8: |
2677 | ret = bswap64(ret); | |
e32664fb | 2678 | break; |
81ad8ba2 BS |
2679 | default: |
2680 | break; | |
2681 | } | |
2682 | default: | |
2683 | break; | |
2684 | } | |
2685 | ||
2686 | /* Convert to signed number */ | |
2687 | if (sign) { | |
2688 | switch(size) { | |
2689 | case 1: | |
2690 | ret = (int8_t) ret; | |
e32664fb | 2691 | break; |
81ad8ba2 BS |
2692 | case 2: |
2693 | ret = (int16_t) ret; | |
e32664fb | 2694 | break; |
81ad8ba2 BS |
2695 | case 4: |
2696 | ret = (int32_t) ret; | |
e32664fb | 2697 | break; |
81ad8ba2 BS |
2698 | default: |
2699 | break; | |
2700 | } | |
2701 | } | |
1a2fb1c0 BS |
2702 | #ifdef DEBUG_ASI |
2703 | dump_asi("read ", last_addr, asi, size, ret); | |
2704 | #endif | |
2705 | return ret; | |
3475187d FB |
2706 | } |
2707 | ||
1a2fb1c0 | 2708 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
3475187d | 2709 | { |
1a2fb1c0 BS |
2710 | #ifdef DEBUG_ASI |
2711 | dump_asi("write", addr, asi, size, val); | |
2712 | #endif | |
01b5d4e5 IK |
2713 | |
2714 | asi &= 0xff; | |
2715 | ||
6f27aba6 | 2716 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2aae2b8e | 2717 | || (cpu_has_hypervisor(env) |
5578ceab | 2718 | && asi >= 0x30 && asi < 0x80 |
fb79ceb9 | 2719 | && !(env->hpstate & HS_PRIV))) |
0f8a249a | 2720 | raise_exception(TT_PRIV_ACT); |
3475187d | 2721 | |
c2bc0e38 | 2722 | helper_check_align(addr, size - 1); |
1295001c IK |
2723 | addr = asi_address_mask(env, asi, addr); |
2724 | ||
81ad8ba2 BS |
2725 | /* Convert to little endian */ |
2726 | switch (asi) { | |
2727 | case 0x0c: // Nucleus Little Endian (LE) | |
2728 | case 0x18: // As if user primary LE | |
2729 | case 0x19: // As if user secondary LE | |
2730 | case 0x1c: // Bypass LE | |
2731 | case 0x1d: // Bypass, non-cacheable LE | |
81ad8ba2 BS |
2732 | case 0x88: // Primary LE |
2733 | case 0x89: // Secondary LE | |
2734 | switch(size) { | |
2735 | case 2: | |
5b0f0bec | 2736 | val = bswap16(val); |
e32664fb | 2737 | break; |
81ad8ba2 | 2738 | case 4: |
5b0f0bec | 2739 | val = bswap32(val); |
e32664fb | 2740 | break; |
81ad8ba2 | 2741 | case 8: |
5b0f0bec | 2742 | val = bswap64(val); |
e32664fb | 2743 | break; |
81ad8ba2 BS |
2744 | default: |
2745 | break; | |
2746 | } | |
2747 | default: | |
2748 | break; | |
2749 | } | |
2750 | ||
3475187d | 2751 | switch(asi) { |
81ad8ba2 | 2752 | case 0x10: // As if user primary |
2065061e | 2753 | case 0x11: // As if user secondary |
81ad8ba2 | 2754 | case 0x18: // As if user primary LE |
2065061e | 2755 | case 0x19: // As if user secondary LE |
81ad8ba2 | 2756 | case 0x80: // Primary |
2065061e | 2757 | case 0x81: // Secondary |
81ad8ba2 | 2758 | case 0x88: // Primary LE |
2065061e | 2759 | case 0x89: // Secondary LE |
c99657d3 BS |
2760 | case 0xe2: // UA2007 Primary block init |
2761 | case 0xe3: // UA2007 Secondary block init | |
81ad8ba2 | 2762 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2aae2b8e | 2763 | if (cpu_hypervisor_mode(env)) { |
6f27aba6 BS |
2764 | switch(size) { |
2765 | case 1: | |
1a2fb1c0 | 2766 | stb_hypv(addr, val); |
6f27aba6 BS |
2767 | break; |
2768 | case 2: | |
a4e7dd52 | 2769 | stw_hypv(addr, val); |
6f27aba6 BS |
2770 | break; |
2771 | case 4: | |
a4e7dd52 | 2772 | stl_hypv(addr, val); |
6f27aba6 BS |
2773 | break; |
2774 | case 8: | |
2775 | default: | |
a4e7dd52 | 2776 | stq_hypv(addr, val); |
6f27aba6 BS |
2777 | break; |
2778 | } | |
2779 | } else { | |
2065061e IK |
2780 | /* secondary space access has lowest asi bit equal to 1 */ |
2781 | if (asi & 1) { | |
2782 | switch(size) { | |
2783 | case 1: | |
2784 | stb_kernel_secondary(addr, val); | |
2785 | break; | |
2786 | case 2: | |
2787 | stw_kernel_secondary(addr, val); | |
2788 | break; | |
2789 | case 4: | |
2790 | stl_kernel_secondary(addr, val); | |
2791 | break; | |
2792 | case 8: | |
2793 | default: | |
2794 | stq_kernel_secondary(addr, val); | |
2795 | break; | |
2796 | } | |
2797 | } else { | |
2798 | switch(size) { | |
2799 | case 1: | |
2800 | stb_kernel(addr, val); | |
2801 | break; | |
2802 | case 2: | |
2803 | stw_kernel(addr, val); | |
2804 | break; | |
2805 | case 4: | |
2806 | stl_kernel(addr, val); | |
2807 | break; | |
2808 | case 8: | |
2809 | default: | |
2810 | stq_kernel(addr, val); | |
2811 | break; | |
2812 | } | |
2813 | } | |
2814 | } | |
2815 | } else { | |
2816 | /* secondary space access has lowest asi bit equal to 1 */ | |
2817 | if (asi & 1) { | |
6f27aba6 BS |
2818 | switch(size) { |
2819 | case 1: | |
2065061e | 2820 | stb_user_secondary(addr, val); |
6f27aba6 BS |
2821 | break; |
2822 | case 2: | |
2065061e | 2823 | stw_user_secondary(addr, val); |
6f27aba6 BS |
2824 | break; |
2825 | case 4: | |
2065061e | 2826 | stl_user_secondary(addr, val); |
6f27aba6 BS |
2827 | break; |
2828 | case 8: | |
2829 | default: | |
2065061e IK |
2830 | stq_user_secondary(addr, val); |
2831 | break; | |
2832 | } | |
2833 | } else { | |
2834 | switch(size) { | |
2835 | case 1: | |
2836 | stb_user(addr, val); | |
2837 | break; | |
2838 | case 2: | |
2839 | stw_user(addr, val); | |
2840 | break; | |
2841 | case 4: | |
2842 | stl_user(addr, val); | |
2843 | break; | |
2844 | case 8: | |
2845 | default: | |
2846 | stq_user(addr, val); | |
6f27aba6 BS |
2847 | break; |
2848 | } | |
81ad8ba2 BS |
2849 | } |
2850 | } | |
2851 | break; | |
3475187d FB |
2852 | case 0x14: // Bypass |
2853 | case 0x15: // Bypass, non-cacheable | |
81ad8ba2 BS |
2854 | case 0x1c: // Bypass LE |
2855 | case 0x1d: // Bypass, non-cacheable LE | |
0f8a249a | 2856 | { |
02aab46a FB |
2857 | switch(size) { |
2858 | case 1: | |
1a2fb1c0 | 2859 | stb_phys(addr, val); |
02aab46a FB |
2860 | break; |
2861 | case 2: | |
a4e7dd52 | 2862 | stw_phys(addr, val); |
02aab46a FB |
2863 | break; |
2864 | case 4: | |
a4e7dd52 | 2865 | stl_phys(addr, val); |
02aab46a FB |
2866 | break; |
2867 | case 8: | |
2868 | default: | |
a4e7dd52 | 2869 | stq_phys(addr, val); |
02aab46a FB |
2870 | break; |
2871 | } | |
0f8a249a BS |
2872 | } |
2873 | return; | |
db166940 BS |
2874 | case 0x24: // Nucleus quad LDD 128 bit atomic |
2875 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE | |
2876 | // Only ldda allowed | |
2877 | raise_exception(TT_ILL_INSN); | |
2878 | return; | |
83469015 FB |
2879 | case 0x04: // Nucleus |
2880 | case 0x0c: // Nucleus Little Endian (LE) | |
2065061e IK |
2881 | { |
2882 | switch(size) { | |
2883 | case 1: | |
2884 | stb_nucleus(addr, val); | |
2885 | break; | |
2886 | case 2: | |
2887 | stw_nucleus(addr, val); | |
2888 | break; | |
2889 | case 4: | |
2890 | stl_nucleus(addr, val); | |
2891 | break; | |
2892 | default: | |
2893 | case 8: | |
2894 | stq_nucleus(addr, val); | |
2895 | break; | |
2896 | } | |
2897 | break; | |
2898 | } | |
2899 | ||
83469015 | 2900 | case 0x4a: // UPA config |
0f8a249a BS |
2901 | // XXX |
2902 | return; | |
3475187d | 2903 | case 0x45: // LSU |
0f8a249a BS |
2904 | { |
2905 | uint64_t oldreg; | |
2906 | ||
2907 | oldreg = env->lsu; | |
1a2fb1c0 | 2908 | env->lsu = val & (DMMU_E | IMMU_E); |
0f8a249a BS |
2909 | // Mappings generated during D/I MMU disabled mode are |
2910 | // invalid in normal mode | |
2911 | if (oldreg != env->lsu) { | |
77f193da BS |
2912 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", |
2913 | oldreg, env->lsu); | |
83469015 | 2914 | #ifdef DEBUG_MMU |
0f8a249a | 2915 | dump_mmu(env); |
83469015 | 2916 | #endif |
0f8a249a BS |
2917 | tlb_flush(env, 1); |
2918 | } | |
2919 | return; | |
2920 | } | |
3475187d | 2921 | case 0x50: // I-MMU regs |
0f8a249a | 2922 | { |
1a2fb1c0 | 2923 | int reg = (addr >> 3) & 0xf; |
0f8a249a | 2924 | uint64_t oldreg; |
3b46e624 | 2925 | |
0f8a249a | 2926 | oldreg = env->immuregs[reg]; |
3475187d FB |
2927 | switch(reg) { |
2928 | case 0: // RO | |
3475187d FB |
2929 | return; |
2930 | case 1: // Not in I-MMU | |
2931 | case 2: | |
3475187d FB |
2932 | return; |
2933 | case 3: // SFSR | |
1a2fb1c0 BS |
2934 | if ((val & 1) == 0) |
2935 | val = 0; // Clear SFSR | |
6e8e7d4c | 2936 | env->immu.sfsr = val; |
3475187d | 2937 | break; |
6e8e7d4c IK |
2938 | case 4: // RO |
2939 | return; | |
3475187d | 2940 | case 5: // TSB access |
6e8e7d4c IK |
2941 | DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" |
2942 | PRIx64 "\n", env->immu.tsb, val); | |
2943 | env->immu.tsb = val; | |
2944 | break; | |
3475187d | 2945 | case 6: // Tag access |
6e8e7d4c IK |
2946 | env->immu.tag_access = val; |
2947 | break; | |
2948 | case 7: | |
2949 | case 8: | |
2950 | return; | |
3475187d FB |
2951 | default: |
2952 | break; | |
2953 | } | |
6e8e7d4c | 2954 | |
3475187d | 2955 | if (oldreg != env->immuregs[reg]) { |
6e8e7d4c | 2956 | DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
77f193da | 2957 | PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
3475187d | 2958 | } |
952a328f | 2959 | #ifdef DEBUG_MMU |
0f8a249a | 2960 | dump_mmu(env); |
3475187d | 2961 | #endif |
0f8a249a BS |
2962 | return; |
2963 | } | |
3475187d | 2964 | case 0x54: // I-MMU data in |
f707726e IK |
2965 | replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env); |
2966 | return; | |
3475187d | 2967 | case 0x55: // I-MMU data access |
0f8a249a | 2968 | { |
cc6747f4 BS |
2969 | // TODO: auto demap |
2970 | ||
1a2fb1c0 | 2971 | unsigned int i = (addr >> 3) & 0x3f; |
3475187d | 2972 | |
f707726e | 2973 | replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env); |
6e8e7d4c IK |
2974 | |
2975 | #ifdef DEBUG_MMU | |
f707726e | 2976 | DPRINTF_MMU("immu data access replaced entry [%i]\n", i); |
6e8e7d4c IK |
2977 | dump_mmu(env); |
2978 | #endif | |
0f8a249a BS |
2979 | return; |
2980 | } | |
3475187d | 2981 | case 0x57: // I-MMU demap |
170f4c55 | 2982 | demap_tlb(env->itlb, addr, "immu", env); |
0f8a249a | 2983 | return; |
3475187d | 2984 | case 0x58: // D-MMU regs |
0f8a249a | 2985 | { |
1a2fb1c0 | 2986 | int reg = (addr >> 3) & 0xf; |
0f8a249a | 2987 | uint64_t oldreg; |
3b46e624 | 2988 | |
0f8a249a | 2989 | oldreg = env->dmmuregs[reg]; |
3475187d FB |
2990 | switch(reg) { |
2991 | case 0: // RO | |
2992 | case 4: | |
2993 | return; | |
2994 | case 3: // SFSR | |
1a2fb1c0 BS |
2995 | if ((val & 1) == 0) { |
2996 | val = 0; // Clear SFSR, Fault address | |
6e8e7d4c | 2997 | env->dmmu.sfar = 0; |
0f8a249a | 2998 | } |
6e8e7d4c | 2999 | env->dmmu.sfsr = val; |
3475187d FB |
3000 | break; |
3001 | case 1: // Primary context | |
6e8e7d4c | 3002 | env->dmmu.mmu_primary_context = val; |
664a65b0 IK |
3003 | /* can be optimized to only flush MMU_USER_IDX |
3004 | and MMU_KERNEL_IDX entries */ | |
3005 | tlb_flush(env, 1); | |
6e8e7d4c | 3006 | break; |
3475187d | 3007 | case 2: // Secondary context |
6e8e7d4c | 3008 | env->dmmu.mmu_secondary_context = val; |
664a65b0 IK |
3009 | /* can be optimized to only flush MMU_USER_SECONDARY_IDX |
3010 | and MMU_KERNEL_SECONDARY_IDX entries */ | |
3011 | tlb_flush(env, 1); | |
6e8e7d4c | 3012 | break; |
3475187d | 3013 | case 5: // TSB access |
6e8e7d4c IK |
3014 | DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" |
3015 | PRIx64 "\n", env->dmmu.tsb, val); | |
3016 | env->dmmu.tsb = val; | |
3017 | break; | |
3475187d | 3018 | case 6: // Tag access |
6e8e7d4c IK |
3019 | env->dmmu.tag_access = val; |
3020 | break; | |
3475187d FB |
3021 | case 7: // Virtual Watchpoint |
3022 | case 8: // Physical Watchpoint | |
3023 | default: | |
6e8e7d4c | 3024 | env->dmmuregs[reg] = val; |
3475187d FB |
3025 | break; |
3026 | } | |
6e8e7d4c | 3027 | |
3475187d | 3028 | if (oldreg != env->dmmuregs[reg]) { |
6e8e7d4c | 3029 | DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
77f193da | 3030 | PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
3475187d | 3031 | } |
952a328f | 3032 | #ifdef DEBUG_MMU |
0f8a249a | 3033 | dump_mmu(env); |
3475187d | 3034 | #endif |
0f8a249a BS |
3035 | return; |
3036 | } | |
3475187d | 3037 | case 0x5c: // D-MMU data in |
f707726e IK |
3038 | replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env); |
3039 | return; | |
3475187d | 3040 | case 0x5d: // D-MMU data access |
0f8a249a | 3041 | { |
1a2fb1c0 | 3042 | unsigned int i = (addr >> 3) & 0x3f; |
3475187d | 3043 | |
f707726e IK |
3044 | replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env); |
3045 | ||
6e8e7d4c | 3046 | #ifdef DEBUG_MMU |
f707726e | 3047 | DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); |
6e8e7d4c IK |
3048 | dump_mmu(env); |
3049 | #endif | |
0f8a249a BS |
3050 | return; |
3051 | } | |
3475187d | 3052 | case 0x5f: // D-MMU demap |
170f4c55 | 3053 | demap_tlb(env->dtlb, addr, "dmmu", env); |
cc6747f4 | 3054 | return; |
83469015 | 3055 | case 0x49: // Interrupt data receive |
0f8a249a BS |
3056 | // XXX |
3057 | return; | |
f7350b47 BS |
3058 | case 0x46: // D-cache data |
3059 | case 0x47: // D-cache tag access | |
a5a52cf2 BS |
3060 | case 0x4b: // E-cache error enable |
3061 | case 0x4c: // E-cache asynchronous fault status | |
3062 | case 0x4d: // E-cache asynchronous fault address | |
f7350b47 BS |
3063 | case 0x4e: // E-cache tag data |
3064 | case 0x66: // I-cache instruction access | |
3065 | case 0x67: // I-cache tag access | |
3066 | case 0x6e: // I-cache predecode | |
3067 | case 0x6f: // I-cache LRU etc. | |
3068 | case 0x76: // E-cache tag | |
3069 | case 0x7e: // E-cache tag | |
3070 | return; | |
3475187d FB |
3071 | case 0x51: // I-MMU 8k TSB pointer, RO |
3072 | case 0x52: // I-MMU 64k TSB pointer, RO | |
3073 | case 0x56: // I-MMU tag read, RO | |
3074 | case 0x59: // D-MMU 8k TSB pointer, RO | |
3075 | case 0x5a: // D-MMU 64k TSB pointer, RO | |
3076 | case 0x5b: // D-MMU data pointer, RO | |
3077 | case 0x5e: // D-MMU tag read, RO | |
83469015 FB |
3078 | case 0x48: // Interrupt dispatch, RO |
3079 | case 0x7f: // Incoming interrupt vector, RO | |
3080 | case 0x82: // Primary no-fault, RO | |
3081 | case 0x83: // Secondary no-fault, RO | |
3082 | case 0x8a: // Primary no-fault LE, RO | |
3083 | case 0x8b: // Secondary no-fault LE, RO | |
3475187d | 3084 | default: |
e18231a3 | 3085 | do_unassigned_access(addr, 1, 0, 1, size); |
0f8a249a | 3086 | return; |
3475187d FB |
3087 | } |
3088 | } | |
81ad8ba2 | 3089 | #endif /* CONFIG_USER_ONLY */ |
3391c818 | 3090 | |
db166940 BS |
3091 | void helper_ldda_asi(target_ulong addr, int asi, int rd) |
3092 | { | |
db166940 | 3093 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2aae2b8e | 3094 | || (cpu_has_hypervisor(env) |
5578ceab | 3095 | && asi >= 0x30 && asi < 0x80 |
fb79ceb9 | 3096 | && !(env->hpstate & HS_PRIV))) |
db166940 BS |
3097 | raise_exception(TT_PRIV_ACT); |
3098 | ||
1295001c IK |
3099 | addr = asi_address_mask(env, asi, addr); |
3100 | ||
db166940 | 3101 | switch (asi) { |
03ae77d6 | 3102 | #if !defined(CONFIG_USER_ONLY) |
db166940 BS |
3103 | case 0x24: // Nucleus quad LDD 128 bit atomic |
3104 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE | |
3105 | helper_check_align(addr, 0xf); | |
3106 | if (rd == 0) { | |
54a3c0f0 | 3107 | env->gregs[1] = ldq_nucleus(addr + 8); |
db166940 BS |
3108 | if (asi == 0x2c) |
3109 | bswap64s(&env->gregs[1]); | |
3110 | } else if (rd < 8) { | |
54a3c0f0 IK |
3111 | env->gregs[rd] = ldq_nucleus(addr); |
3112 | env->gregs[rd + 1] = ldq_nucleus(addr + 8); | |
db166940 BS |
3113 | if (asi == 0x2c) { |
3114 | bswap64s(&env->gregs[rd]); | |
3115 | bswap64s(&env->gregs[rd + 1]); | |
3116 | } | |
3117 | } else { | |
54a3c0f0 IK |
3118 | env->regwptr[rd] = ldq_nucleus(addr); |
3119 | env->regwptr[rd + 1] = ldq_nucleus(addr + 8); | |
db166940 BS |
3120 | if (asi == 0x2c) { |
3121 | bswap64s(&env->regwptr[rd]); | |
3122 | bswap64s(&env->regwptr[rd + 1]); | |
3123 | } | |
3124 | } | |
3125 | break; | |
03ae77d6 | 3126 | #endif |
db166940 BS |
3127 | default: |
3128 | helper_check_align(addr, 0x3); | |
3129 | if (rd == 0) | |
3130 | env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0); | |
3131 | else if (rd < 8) { | |
3132 | env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0); | |
3133 | env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); | |
3134 | } else { | |
3135 | env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0); | |
3136 | env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); | |
3137 | } | |
3138 | break; | |
3139 | } | |
3140 | } | |
3141 | ||
1a2fb1c0 | 3142 | void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
3391c818 | 3143 | { |
3391c818 | 3144 | unsigned int i; |
1a2fb1c0 | 3145 | target_ulong val; |
3391c818 | 3146 | |
c2bc0e38 | 3147 | helper_check_align(addr, 3); |
1295001c IK |
3148 | addr = asi_address_mask(env, asi, addr); |
3149 | ||
3391c818 BS |
3150 | switch (asi) { |
3151 | case 0xf0: // Block load primary | |
3152 | case 0xf1: // Block load secondary | |
3153 | case 0xf8: // Block load primary LE | |
3154 | case 0xf9: // Block load secondary LE | |
51996525 BS |
3155 | if (rd & 7) { |
3156 | raise_exception(TT_ILL_INSN); | |
3157 | return; | |
3158 | } | |
c2bc0e38 | 3159 | helper_check_align(addr, 0x3f); |
51996525 | 3160 | for (i = 0; i < 16; i++) { |
77f193da BS |
3161 | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, |
3162 | 0); | |
1a2fb1c0 | 3163 | addr += 4; |
3391c818 | 3164 | } |
3391c818 BS |
3165 | |
3166 | return; | |
3167 | default: | |
3168 | break; | |
3169 | } | |
3170 | ||
1a2fb1c0 | 3171 | val = helper_ld_asi(addr, asi, size, 0); |
3391c818 BS |
3172 | switch(size) { |
3173 | default: | |
3174 | case 4: | |
714547bb | 3175 | *((uint32_t *)&env->fpr[rd]) = val; |
3391c818 BS |
3176 | break; |
3177 | case 8: | |
1a2fb1c0 | 3178 | *((int64_t *)&DT0) = val; |
3391c818 | 3179 | break; |
1f587329 BS |
3180 | case 16: |
3181 | // XXX | |
3182 | break; | |
3391c818 | 3183 | } |
3391c818 BS |
3184 | } |
3185 | ||
1a2fb1c0 | 3186 | void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
3391c818 | 3187 | { |
3391c818 | 3188 | unsigned int i; |
1a2fb1c0 | 3189 | target_ulong val = 0; |
3391c818 | 3190 | |
c2bc0e38 | 3191 | helper_check_align(addr, 3); |
1295001c IK |
3192 | addr = asi_address_mask(env, asi, addr); |
3193 | ||
3391c818 | 3194 | switch (asi) { |
c99657d3 BS |
3195 | case 0xe0: // UA2007 Block commit store primary (cache flush) |
3196 | case 0xe1: // UA2007 Block commit store secondary (cache flush) | |
3391c818 BS |
3197 | case 0xf0: // Block store primary |
3198 | case 0xf1: // Block store secondary | |
3199 | case 0xf8: // Block store primary LE | |
3200 | case 0xf9: // Block store secondary LE | |
51996525 BS |
3201 | if (rd & 7) { |
3202 | raise_exception(TT_ILL_INSN); | |
3203 | return; | |
3204 | } | |
c2bc0e38 | 3205 | helper_check_align(addr, 0x3f); |
51996525 | 3206 | for (i = 0; i < 16; i++) { |
1a2fb1c0 BS |
3207 | val = *(uint32_t *)&env->fpr[rd++]; |
3208 | helper_st_asi(addr, val, asi & 0x8f, 4); | |
3209 | addr += 4; | |
3391c818 | 3210 | } |
3391c818 BS |
3211 | |
3212 | return; | |
3213 | default: | |
3214 | break; | |
3215 | } | |
3216 | ||
3217 | switch(size) { | |
3218 | default: | |
3219 | case 4: | |
714547bb | 3220 | val = *((uint32_t *)&env->fpr[rd]); |
3391c818 BS |
3221 | break; |
3222 | case 8: | |
1a2fb1c0 | 3223 | val = *((int64_t *)&DT0); |
3391c818 | 3224 | break; |
1f587329 BS |
3225 | case 16: |
3226 | // XXX | |
3227 | break; | |
3391c818 | 3228 | } |
1a2fb1c0 BS |
3229 | helper_st_asi(addr, val, asi, size); |
3230 | } | |
3231 | ||
3232 | target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, | |
3233 | target_ulong val2, uint32_t asi) | |
3234 | { | |
3235 | target_ulong ret; | |
3236 | ||
1121f879 | 3237 | val2 &= 0xffffffffUL; |
1a2fb1c0 BS |
3238 | ret = helper_ld_asi(addr, asi, 4, 0); |
3239 | ret &= 0xffffffffUL; | |
1121f879 BS |
3240 | if (val2 == ret) |
3241 | helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4); | |
1a2fb1c0 | 3242 | return ret; |
3391c818 BS |
3243 | } |
3244 | ||
1a2fb1c0 BS |
3245 | target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
3246 | target_ulong val2, uint32_t asi) | |
3247 | { | |
3248 | target_ulong ret; | |
3249 | ||
3250 | ret = helper_ld_asi(addr, asi, 8, 0); | |
1121f879 BS |
3251 | if (val2 == ret) |
3252 | helper_st_asi(addr, val1, asi, 8); | |
1a2fb1c0 BS |
3253 | return ret; |
3254 | } | |
81ad8ba2 | 3255 | #endif /* TARGET_SPARC64 */ |
3475187d FB |
3256 | |
3257 | #ifndef TARGET_SPARC64 | |
1a2fb1c0 | 3258 | void helper_rett(void) |
e8af50a3 | 3259 | { |
af7bf89b FB |
3260 | unsigned int cwp; |
3261 | ||
d4218d99 BS |
3262 | if (env->psret == 1) |
3263 | raise_exception(TT_ILL_INSN); | |
3264 | ||
e8af50a3 | 3265 | env->psret = 1; |
5a834bb4 | 3266 | cwp = cwp_inc(env->cwp + 1) ; |
e8af50a3 FB |
3267 | if (env->wim & (1 << cwp)) { |
3268 | raise_exception(TT_WIN_UNF); | |
3269 | } | |
3270 | set_cwp(cwp); | |
3271 | env->psrs = env->psrps; | |
3272 | } | |
3475187d | 3273 | #endif |
e8af50a3 | 3274 | |
3b89f26c BS |
3275 | target_ulong helper_udiv(target_ulong a, target_ulong b) |
3276 | { | |
3277 | uint64_t x0; | |
3278 | uint32_t x1; | |
3279 | ||
7621a90d | 3280 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3b89f26c BS |
3281 | x1 = b; |
3282 | ||
3283 | if (x1 == 0) { | |
3284 | raise_exception(TT_DIV_ZERO); | |
3285 | } | |
3286 | ||
3287 | x0 = x0 / x1; | |
3288 | if (x0 > 0xffffffff) { | |
3289 | env->cc_src2 = 1; | |
3290 | return 0xffffffff; | |
3291 | } else { | |
3292 | env->cc_src2 = 0; | |
3293 | return x0; | |
3294 | } | |
3295 | } | |
3296 | ||
3297 | target_ulong helper_sdiv(target_ulong a, target_ulong b) | |
3298 | { | |
3299 | int64_t x0; | |
3300 | int32_t x1; | |
3301 | ||
7621a90d | 3302 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3b89f26c BS |
3303 | x1 = b; |
3304 | ||
3305 | if (x1 == 0) { | |
3306 | raise_exception(TT_DIV_ZERO); | |
3307 | } | |
3308 | ||
3309 | x0 = x0 / x1; | |
3310 | if ((int32_t) x0 != x0) { | |
3311 | env->cc_src2 = 1; | |
3312 | return x0 < 0? 0x80000000: 0x7fffffff; | |
3313 | } else { | |
3314 | env->cc_src2 = 0; | |
3315 | return x0; | |
3316 | } | |
3317 | } | |
3318 | ||
7fa76c0b BS |
3319 | void helper_stdf(target_ulong addr, int mem_idx) |
3320 | { | |
c2bc0e38 | 3321 | helper_check_align(addr, 7); |
7fa76c0b BS |
3322 | #if !defined(CONFIG_USER_ONLY) |
3323 | switch (mem_idx) { | |
3324 | case 0: | |
c2bc0e38 | 3325 | stfq_user(addr, DT0); |
7fa76c0b BS |
3326 | break; |
3327 | case 1: | |
c2bc0e38 | 3328 | stfq_kernel(addr, DT0); |
7fa76c0b BS |
3329 | break; |
3330 | #ifdef TARGET_SPARC64 | |
3331 | case 2: | |
c2bc0e38 | 3332 | stfq_hypv(addr, DT0); |
7fa76c0b BS |
3333 | break; |
3334 | #endif | |
3335 | default: | |
3336 | break; | |
3337 | } | |
3338 | #else | |
41db525e | 3339 | stfq_raw(address_mask(env, addr), DT0); |
7fa76c0b BS |
3340 | #endif |
3341 | } | |
3342 | ||
3343 | void helper_lddf(target_ulong addr, int mem_idx) | |
3344 | { | |
c2bc0e38 | 3345 | helper_check_align(addr, 7); |
7fa76c0b BS |
3346 | #if !defined(CONFIG_USER_ONLY) |
3347 | switch (mem_idx) { | |
3348 | case 0: | |
c2bc0e38 | 3349 | DT0 = ldfq_user(addr); |
7fa76c0b BS |
3350 | break; |
3351 | case 1: | |
c2bc0e38 | 3352 | DT0 = ldfq_kernel(addr); |
7fa76c0b BS |
3353 | break; |
3354 | #ifdef TARGET_SPARC64 | |
3355 | case 2: | |
c2bc0e38 | 3356 | DT0 = ldfq_hypv(addr); |
7fa76c0b BS |
3357 | break; |
3358 | #endif | |
3359 | default: | |
3360 | break; | |
3361 | } | |
3362 | #else | |
41db525e | 3363 | DT0 = ldfq_raw(address_mask(env, addr)); |
7fa76c0b BS |
3364 | #endif |
3365 | } | |
3366 | ||
64a88d5d | 3367 | void helper_ldqf(target_ulong addr, int mem_idx) |
7fa76c0b BS |
3368 | { |
3369 | // XXX add 128 bit load | |
3370 | CPU_QuadU u; | |
3371 | ||
c2bc0e38 | 3372 | helper_check_align(addr, 7); |
64a88d5d BS |
3373 | #if !defined(CONFIG_USER_ONLY) |
3374 | switch (mem_idx) { | |
3375 | case 0: | |
c2bc0e38 BS |
3376 | u.ll.upper = ldq_user(addr); |
3377 | u.ll.lower = ldq_user(addr + 8); | |
64a88d5d BS |
3378 | QT0 = u.q; |
3379 | break; | |
3380 | case 1: | |
c2bc0e38 BS |
3381 | u.ll.upper = ldq_kernel(addr); |
3382 | u.ll.lower = ldq_kernel(addr + 8); | |
64a88d5d BS |
3383 | QT0 = u.q; |
3384 | break; | |
3385 | #ifdef TARGET_SPARC64 | |
3386 | case 2: | |
c2bc0e38 BS |
3387 | u.ll.upper = ldq_hypv(addr); |
3388 | u.ll.lower = ldq_hypv(addr + 8); | |
64a88d5d BS |
3389 | QT0 = u.q; |
3390 | break; | |
3391 | #endif | |
3392 | default: | |
3393 | break; | |
3394 | } | |
3395 | #else | |
41db525e RH |
3396 | u.ll.upper = ldq_raw(address_mask(env, addr)); |
3397 | u.ll.lower = ldq_raw(address_mask(env, addr + 8)); | |
7fa76c0b | 3398 | QT0 = u.q; |
64a88d5d | 3399 | #endif |
7fa76c0b BS |
3400 | } |
3401 | ||
64a88d5d | 3402 | void helper_stqf(target_ulong addr, int mem_idx) |
7fa76c0b BS |
3403 | { |
3404 | // XXX add 128 bit store | |
3405 | CPU_QuadU u; | |
3406 | ||
c2bc0e38 | 3407 | helper_check_align(addr, 7); |
64a88d5d BS |
3408 | #if !defined(CONFIG_USER_ONLY) |
3409 | switch (mem_idx) { | |
3410 | case 0: | |
3411 | u.q = QT0; | |
c2bc0e38 BS |
3412 | stq_user(addr, u.ll.upper); |
3413 | stq_user(addr + 8, u.ll.lower); | |
64a88d5d BS |
3414 | break; |
3415 | case 1: | |
3416 | u.q = QT0; | |
c2bc0e38 BS |
3417 | stq_kernel(addr, u.ll.upper); |
3418 | stq_kernel(addr + 8, u.ll.lower); | |
64a88d5d BS |
3419 | break; |
3420 | #ifdef TARGET_SPARC64 | |
3421 | case 2: | |
3422 | u.q = QT0; | |
c2bc0e38 BS |
3423 | stq_hypv(addr, u.ll.upper); |
3424 | stq_hypv(addr + 8, u.ll.lower); | |
64a88d5d BS |
3425 | break; |
3426 | #endif | |
3427 | default: | |
3428 | break; | |
3429 | } | |
3430 | #else | |
7fa76c0b | 3431 | u.q = QT0; |
41db525e RH |
3432 | stq_raw(address_mask(env, addr), u.ll.upper); |
3433 | stq_raw(address_mask(env, addr + 8), u.ll.lower); | |
7fa76c0b | 3434 | #endif |
64a88d5d | 3435 | } |
7fa76c0b | 3436 | |
3a3b925d | 3437 | static inline void set_fsr(void) |
e8af50a3 | 3438 | { |
7a0e1f41 | 3439 | int rnd_mode; |
bb5529bb | 3440 | |
e8af50a3 FB |
3441 | switch (env->fsr & FSR_RD_MASK) { |
3442 | case FSR_RD_NEAREST: | |
7a0e1f41 | 3443 | rnd_mode = float_round_nearest_even; |
0f8a249a | 3444 | break; |
ed910241 | 3445 | default: |
e8af50a3 | 3446 | case FSR_RD_ZERO: |
7a0e1f41 | 3447 | rnd_mode = float_round_to_zero; |
0f8a249a | 3448 | break; |
e8af50a3 | 3449 | case FSR_RD_POS: |
7a0e1f41 | 3450 | rnd_mode = float_round_up; |
0f8a249a | 3451 | break; |
e8af50a3 | 3452 | case FSR_RD_NEG: |
7a0e1f41 | 3453 | rnd_mode = float_round_down; |
0f8a249a | 3454 | break; |
e8af50a3 | 3455 | } |
7a0e1f41 | 3456 | set_float_rounding_mode(rnd_mode, &env->fp_status); |
e8af50a3 | 3457 | } |
e80cfcfc | 3458 | |
3a3b925d | 3459 | void helper_ldfsr(uint32_t new_fsr) |
bb5529bb | 3460 | { |
3a3b925d BS |
3461 | env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK); |
3462 | set_fsr(); | |
bb5529bb BS |
3463 | } |
3464 | ||
3a3b925d BS |
3465 | #ifdef TARGET_SPARC64 |
3466 | void helper_ldxfsr(uint64_t new_fsr) | |
3467 | { | |
3468 | env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK); | |
3469 | set_fsr(); | |
3470 | } | |
3471 | #endif | |
3472 | ||
bb5529bb | 3473 | void helper_debug(void) |
e80cfcfc FB |
3474 | { |
3475 | env->exception_index = EXCP_DEBUG; | |
3476 | cpu_loop_exit(); | |
3477 | } | |
af7bf89b | 3478 | |
3475187d | 3479 | #ifndef TARGET_SPARC64 |
72a9747b BS |
3480 | /* XXX: use another pointer for %iN registers to avoid slow wrapping |
3481 | handling ? */ | |
3482 | void helper_save(void) | |
3483 | { | |
3484 | uint32_t cwp; | |
3485 | ||
5a834bb4 | 3486 | cwp = cwp_dec(env->cwp - 1); |
72a9747b BS |
3487 | if (env->wim & (1 << cwp)) { |
3488 | raise_exception(TT_WIN_OVF); | |
3489 | } | |
3490 | set_cwp(cwp); | |
3491 | } | |
3492 | ||
3493 | void helper_restore(void) | |
3494 | { | |
3495 | uint32_t cwp; | |
3496 | ||
5a834bb4 | 3497 | cwp = cwp_inc(env->cwp + 1); |
72a9747b BS |
3498 | if (env->wim & (1 << cwp)) { |
3499 | raise_exception(TT_WIN_UNF); | |
3500 | } | |
3501 | set_cwp(cwp); | |
3502 | } | |
3503 | ||
1a2fb1c0 | 3504 | void helper_wrpsr(target_ulong new_psr) |
af7bf89b | 3505 | { |
5a834bb4 | 3506 | if ((new_psr & PSR_CWP) >= env->nwindows) { |
d4218d99 | 3507 | raise_exception(TT_ILL_INSN); |
5a834bb4 BS |
3508 | } else { |
3509 | cpu_put_psr(env, new_psr); | |
3510 | } | |
af7bf89b FB |
3511 | } |
3512 | ||
1a2fb1c0 | 3513 | target_ulong helper_rdpsr(void) |
af7bf89b | 3514 | { |
5a834bb4 | 3515 | return get_psr(); |
af7bf89b | 3516 | } |
3475187d FB |
3517 | |
3518 | #else | |
72a9747b BS |
3519 | /* XXX: use another pointer for %iN registers to avoid slow wrapping |
3520 | handling ? */ | |
3521 | void helper_save(void) | |
3522 | { | |
3523 | uint32_t cwp; | |
3524 | ||
5a834bb4 | 3525 | cwp = cwp_dec(env->cwp - 1); |
72a9747b BS |
3526 | if (env->cansave == 0) { |
3527 | raise_exception(TT_SPILL | (env->otherwin != 0 ? | |
3528 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): | |
3529 | ((env->wstate & 0x7) << 2))); | |
3530 | } else { | |
3531 | if (env->cleanwin - env->canrestore == 0) { | |
3532 | // XXX Clean windows without trap | |
3533 | raise_exception(TT_CLRWIN); | |
3534 | } else { | |
3535 | env->cansave--; | |
3536 | env->canrestore++; | |
3537 | set_cwp(cwp); | |
3538 | } | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | void helper_restore(void) | |
3543 | { | |
3544 | uint32_t cwp; | |
3545 | ||
5a834bb4 | 3546 | cwp = cwp_inc(env->cwp + 1); |
72a9747b BS |
3547 | if (env->canrestore == 0) { |
3548 | raise_exception(TT_FILL | (env->otherwin != 0 ? | |
3549 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): | |
3550 | ((env->wstate & 0x7) << 2))); | |
3551 | } else { | |
3552 | env->cansave++; | |
3553 | env->canrestore--; | |
3554 | set_cwp(cwp); | |
3555 | } | |
3556 | } | |
3557 | ||
3558 | void helper_flushw(void) | |
3559 | { | |
1a14026e | 3560 | if (env->cansave != env->nwindows - 2) { |
72a9747b BS |
3561 | raise_exception(TT_SPILL | (env->otherwin != 0 ? |
3562 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): | |
3563 | ((env->wstate & 0x7) << 2))); | |
3564 | } | |
3565 | } | |
3566 | ||
3567 | void helper_saved(void) | |
3568 | { | |
3569 | env->cansave++; | |
3570 | if (env->otherwin == 0) | |
3571 | env->canrestore--; | |
3572 | else | |
3573 | env->otherwin--; | |
3574 | } | |
3575 | ||
3576 | void helper_restored(void) | |
3577 | { | |
3578 | env->canrestore++; | |
1a14026e | 3579 | if (env->cleanwin < env->nwindows - 1) |
72a9747b BS |
3580 | env->cleanwin++; |
3581 | if (env->otherwin == 0) | |
3582 | env->cansave--; | |
3583 | else | |
3584 | env->otherwin--; | |
3585 | } | |
3586 | ||
5a834bb4 BS |
3587 | static target_ulong get_ccr(void) |
3588 | { | |
3589 | target_ulong psr; | |
3590 | ||
3591 | psr = get_psr(); | |
3592 | ||
3593 | return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); | |
3594 | } | |
3595 | ||
3596 | target_ulong cpu_get_ccr(CPUState *env1) | |
3597 | { | |
3598 | CPUState *saved_env; | |
3599 | target_ulong ret; | |
3600 | ||
3601 | saved_env = env; | |
3602 | env = env1; | |
3603 | ret = get_ccr(); | |
3604 | env = saved_env; | |
3605 | return ret; | |
3606 | } | |
3607 | ||
3608 | static void put_ccr(target_ulong val) | |
3609 | { | |
3610 | target_ulong tmp = val; | |
3611 | ||
3612 | env->xcc = (tmp >> 4) << 20; | |
3613 | env->psr = (tmp & 0xf) << 20; | |
3614 | CC_OP = CC_OP_FLAGS; | |
3615 | } | |
3616 | ||
3617 | void cpu_put_ccr(CPUState *env1, target_ulong val) | |
3618 | { | |
3619 | CPUState *saved_env; | |
3620 | ||
3621 | saved_env = env; | |
3622 | env = env1; | |
3623 | put_ccr(val); | |
3624 | env = saved_env; | |
3625 | } | |
3626 | ||
3627 | static target_ulong get_cwp64(void) | |
3628 | { | |
3629 | return env->nwindows - 1 - env->cwp; | |
3630 | } | |
3631 | ||
3632 | target_ulong cpu_get_cwp64(CPUState *env1) | |
3633 | { | |
3634 | CPUState *saved_env; | |
3635 | target_ulong ret; | |
3636 | ||
3637 | saved_env = env; | |
3638 | env = env1; | |
3639 | ret = get_cwp64(); | |
3640 | env = saved_env; | |
3641 | return ret; | |
3642 | } | |
3643 | ||
3644 | static void put_cwp64(int cwp) | |
3645 | { | |
3646 | if (unlikely(cwp >= env->nwindows || cwp < 0)) { | |
3647 | cwp %= env->nwindows; | |
3648 | } | |
3649 | set_cwp(env->nwindows - 1 - cwp); | |
3650 | } | |
3651 | ||
3652 | void cpu_put_cwp64(CPUState *env1, int cwp) | |
3653 | { | |
3654 | CPUState *saved_env; | |
3655 | ||
3656 | saved_env = env; | |
3657 | env = env1; | |
3658 | put_cwp64(cwp); | |
3659 | env = saved_env; | |
3660 | } | |
3661 | ||
d35527d9 BS |
3662 | target_ulong helper_rdccr(void) |
3663 | { | |
5a834bb4 | 3664 | return get_ccr(); |
d35527d9 BS |
3665 | } |
3666 | ||
3667 | void helper_wrccr(target_ulong new_ccr) | |
3668 | { | |
5a834bb4 | 3669 | put_ccr(new_ccr); |
d35527d9 BS |
3670 | } |
3671 | ||
3672 | // CWP handling is reversed in V9, but we still use the V8 register | |
3673 | // order. | |
3674 | target_ulong helper_rdcwp(void) | |
3675 | { | |
5a834bb4 | 3676 | return get_cwp64(); |
d35527d9 BS |
3677 | } |
3678 | ||
3679 | void helper_wrcwp(target_ulong new_cwp) | |
3680 | { | |
5a834bb4 | 3681 | put_cwp64(new_cwp); |
d35527d9 | 3682 | } |
3475187d | 3683 | |
1f5063fb BS |
3684 | // This function uses non-native bit order |
3685 | #define GET_FIELD(X, FROM, TO) \ | |
3686 | ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) | |
3687 | ||
3688 | // This function uses the order in the manuals, i.e. bit 0 is 2^0 | |
3689 | #define GET_FIELD_SP(X, FROM, TO) \ | |
3690 | GET_FIELD(X, 63 - (TO), 63 - (FROM)) | |
3691 | ||
3692 | target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) | |
3693 | { | |
3694 | return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | | |
3695 | (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) | | |
3696 | (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) | | |
3697 | (GET_FIELD_SP(pixel_addr, 56, 59) << 13) | | |
3698 | (GET_FIELD_SP(pixel_addr, 35, 38) << 9) | | |
3699 | (GET_FIELD_SP(pixel_addr, 13, 16) << 5) | | |
3700 | (((pixel_addr >> 55) & 1) << 4) | | |
3701 | (GET_FIELD_SP(pixel_addr, 33, 34) << 2) | | |
3702 | GET_FIELD_SP(pixel_addr, 11, 12); | |
3703 | } | |
3704 | ||
3705 | target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) | |
3706 | { | |
3707 | uint64_t tmp; | |
3708 | ||
3709 | tmp = addr + offset; | |
3710 | env->gsr &= ~7ULL; | |
3711 | env->gsr |= tmp & 7ULL; | |
3712 | return tmp & ~7ULL; | |
3713 | } | |
3714 | ||
1a2fb1c0 | 3715 | target_ulong helper_popc(target_ulong val) |
3475187d | 3716 | { |
1a2fb1c0 | 3717 | return ctpop64(val); |
3475187d | 3718 | } |
83469015 | 3719 | |
d780a466 | 3720 | static inline uint64_t *get_gregset(uint32_t pstate) |
83469015 FB |
3721 | { |
3722 | switch (pstate) { | |
3723 | default: | |
7e8695ed IK |
3724 | DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n", |
3725 | pstate, | |
3726 | (pstate & PS_IG) ? " IG" : "", | |
3727 | (pstate & PS_MG) ? " MG" : "", | |
3728 | (pstate & PS_AG) ? " AG" : ""); | |
3729 | /* pass through to normal set of global registers */ | |
83469015 | 3730 | case 0: |
0f8a249a | 3731 | return env->bgregs; |
83469015 | 3732 | case PS_AG: |
0f8a249a | 3733 | return env->agregs; |
83469015 | 3734 | case PS_MG: |
0f8a249a | 3735 | return env->mgregs; |
83469015 | 3736 | case PS_IG: |
0f8a249a | 3737 | return env->igregs; |
83469015 FB |
3738 | } |
3739 | } | |
3740 | ||
d780a466 | 3741 | static inline void change_pstate(uint32_t new_pstate) |
83469015 | 3742 | { |
d780a466 | 3743 | uint32_t pstate_regs, new_pstate_regs; |
83469015 FB |
3744 | uint64_t *src, *dst; |
3745 | ||
5210977a IK |
3746 | if (env->def->features & CPU_FEATURE_GL) { |
3747 | // PS_AG is not implemented in this case | |
3748 | new_pstate &= ~PS_AG; | |
3749 | } | |
3750 | ||
83469015 FB |
3751 | pstate_regs = env->pstate & 0xc01; |
3752 | new_pstate_regs = new_pstate & 0xc01; | |
5210977a | 3753 | |
83469015 | 3754 | if (new_pstate_regs != pstate_regs) { |
7e8695ed IK |
3755 | DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n", |
3756 | pstate_regs, new_pstate_regs); | |
0f8a249a BS |
3757 | // Switch global register bank |
3758 | src = get_gregset(new_pstate_regs); | |
3759 | dst = get_gregset(pstate_regs); | |
3760 | memcpy32(dst, env->gregs); | |
3761 | memcpy32(env->gregs, src); | |
83469015 | 3762 | } |
7e8695ed IK |
3763 | else { |
3764 | DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n", | |
3765 | new_pstate_regs); | |
3766 | } | |
83469015 FB |
3767 | env->pstate = new_pstate; |
3768 | } | |
3769 | ||
1a2fb1c0 | 3770 | void helper_wrpstate(target_ulong new_state) |
8f1f22f6 | 3771 | { |
5210977a | 3772 | change_pstate(new_state & 0xf3f); |
4dc28134 IK |
3773 | |
3774 | #if !defined(CONFIG_USER_ONLY) | |
3775 | if (cpu_interrupts_enabled(env)) { | |
3776 | cpu_check_irqs(env); | |
3777 | } | |
3778 | #endif | |
8f1f22f6 BS |
3779 | } |
3780 | ||
1fae7b70 IK |
3781 | void helper_wrpil(target_ulong new_pil) |
3782 | { | |
3783 | #if !defined(CONFIG_USER_ONLY) | |
3784 | DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n", | |
3785 | env->psrpil, (uint32_t)new_pil); | |
3786 | ||
3787 | env->psrpil = new_pil; | |
3788 | ||
3789 | if (cpu_interrupts_enabled(env)) { | |
3790 | cpu_check_irqs(env); | |
3791 | } | |
3792 | #endif | |
3793 | } | |
3794 | ||
1a2fb1c0 | 3795 | void helper_done(void) |
83469015 | 3796 | { |
8194f35a IK |
3797 | trap_state* tsptr = cpu_tsptr(env); |
3798 | ||
3723cd09 | 3799 | env->pc = tsptr->tnpc; |
8194f35a | 3800 | env->npc = tsptr->tnpc + 4; |
5a834bb4 | 3801 | put_ccr(tsptr->tstate >> 32); |
8194f35a IK |
3802 | env->asi = (tsptr->tstate >> 24) & 0xff; |
3803 | change_pstate((tsptr->tstate >> 8) & 0xf3f); | |
5a834bb4 | 3804 | put_cwp64(tsptr->tstate & 0xff); |
e6bf7d70 | 3805 | env->tl--; |
4dc28134 IK |
3806 | |
3807 | DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl); | |
3808 | ||
3809 | #if !defined(CONFIG_USER_ONLY) | |
3810 | if (cpu_interrupts_enabled(env)) { | |
3811 | cpu_check_irqs(env); | |
3812 | } | |
3813 | #endif | |
83469015 FB |
3814 | } |
3815 | ||
1a2fb1c0 | 3816 | void helper_retry(void) |
83469015 | 3817 | { |
8194f35a IK |
3818 | trap_state* tsptr = cpu_tsptr(env); |
3819 | ||
3820 | env->pc = tsptr->tpc; | |
3821 | env->npc = tsptr->tnpc; | |
5a834bb4 | 3822 | put_ccr(tsptr->tstate >> 32); |
8194f35a IK |
3823 | env->asi = (tsptr->tstate >> 24) & 0xff; |
3824 | change_pstate((tsptr->tstate >> 8) & 0xf3f); | |
5a834bb4 | 3825 | put_cwp64(tsptr->tstate & 0xff); |
e6bf7d70 | 3826 | env->tl--; |
4dc28134 IK |
3827 | |
3828 | DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl); | |
3829 | ||
3830 | #if !defined(CONFIG_USER_ONLY) | |
3831 | if (cpu_interrupts_enabled(env)) { | |
3832 | cpu_check_irqs(env); | |
3833 | } | |
3834 | #endif | |
3835 | } | |
3836 | ||
3837 | static void do_modify_softint(const char* operation, uint32_t value) | |
3838 | { | |
3839 | if (env->softint != value) { | |
3840 | env->softint = value; | |
3841 | DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint); | |
3842 | #if !defined(CONFIG_USER_ONLY) | |
3843 | if (cpu_interrupts_enabled(env)) { | |
3844 | cpu_check_irqs(env); | |
3845 | } | |
3846 | #endif | |
3847 | } | |
83469015 | 3848 | } |
9d926598 BS |
3849 | |
3850 | void helper_set_softint(uint64_t value) | |
3851 | { | |
4dc28134 | 3852 | do_modify_softint("helper_set_softint", env->softint | (uint32_t)value); |
9d926598 BS |
3853 | } |
3854 | ||
3855 | void helper_clear_softint(uint64_t value) | |
3856 | { | |
4dc28134 | 3857 | do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value); |
9d926598 BS |
3858 | } |
3859 | ||
3860 | void helper_write_softint(uint64_t value) | |
3861 | { | |
4dc28134 | 3862 | do_modify_softint("helper_write_softint", (uint32_t)value); |
9d926598 | 3863 | } |
3475187d | 3864 | #endif |
ee5bbe38 | 3865 | |
91736d37 | 3866 | void helper_flush(target_ulong addr) |
ee5bbe38 | 3867 | { |
91736d37 BS |
3868 | addr &= ~7; |
3869 | tb_invalidate_page_range(addr, addr + 8); | |
ee5bbe38 FB |
3870 | } |
3871 | ||
91736d37 BS |
3872 | #ifdef TARGET_SPARC64 |
3873 | #ifdef DEBUG_PCALL | |
3874 | static const char * const excp_names[0x80] = { | |
3875 | [TT_TFAULT] = "Instruction Access Fault", | |
3876 | [TT_TMISS] = "Instruction Access MMU Miss", | |
3877 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
3878 | [TT_ILL_INSN] = "Illegal Instruction", | |
3879 | [TT_PRIV_INSN] = "Privileged Instruction", | |
3880 | [TT_NFPU_INSN] = "FPU Disabled", | |
3881 | [TT_FP_EXCP] = "FPU Exception", | |
3882 | [TT_TOVF] = "Tag Overflow", | |
3883 | [TT_CLRWIN] = "Clean Windows", | |
3884 | [TT_DIV_ZERO] = "Division By Zero", | |
3885 | [TT_DFAULT] = "Data Access Fault", | |
3886 | [TT_DMISS] = "Data Access MMU Miss", | |
3887 | [TT_DATA_ACCESS] = "Data Access Error", | |
3888 | [TT_DPROT] = "Data Protection Error", | |
3889 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
3890 | [TT_PRIV_ACT] = "Privileged Action", | |
3891 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
3892 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
3893 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
3894 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
3895 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
3896 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
3897 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
3898 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
3899 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
3900 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
3901 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
3902 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
3903 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
3904 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
3905 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
3906 | }; | |
3907 | #endif | |
3908 | ||
8194f35a IK |
3909 | trap_state* cpu_tsptr(CPUState* env) |
3910 | { | |
3911 | return &env->ts[env->tl & MAXTL_MASK]; | |
3912 | } | |
3913 | ||
91736d37 BS |
3914 | void do_interrupt(CPUState *env) |
3915 | { | |
3916 | int intno = env->exception_index; | |
8194f35a | 3917 | trap_state* tsptr; |
91736d37 BS |
3918 | |
3919 | #ifdef DEBUG_PCALL | |
8fec2b8c | 3920 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
91736d37 BS |
3921 | static int count; |
3922 | const char *name; | |
3923 | ||
3924 | if (intno < 0 || intno >= 0x180) | |
3925 | name = "Unknown"; | |
3926 | else if (intno >= 0x100) | |
3927 | name = "Trap Instruction"; | |
3928 | else if (intno >= 0xc0) | |
3929 | name = "Window Fill"; | |
3930 | else if (intno >= 0x80) | |
3931 | name = "Window Spill"; | |
3932 | else { | |
3933 | name = excp_names[intno]; | |
3934 | if (!name) | |
3935 | name = "Unknown"; | |
3936 | } | |
3937 | ||
93fcfe39 | 3938 | qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
91736d37 BS |
3939 | " SP=%016" PRIx64 "\n", |
3940 | count, name, intno, | |
3941 | env->pc, | |
3942 | env->npc, env->regwptr[6]); | |
93fcfe39 | 3943 | log_cpu_state(env, 0); |
91736d37 BS |
3944 | #if 0 |
3945 | { | |
3946 | int i; | |
3947 | uint8_t *ptr; | |
3948 | ||
93fcfe39 | 3949 | qemu_log(" code="); |
91736d37 BS |
3950 | ptr = (uint8_t *)env->pc; |
3951 | for(i = 0; i < 16; i++) { | |
93fcfe39 | 3952 | qemu_log(" %02x", ldub(ptr + i)); |
91736d37 | 3953 | } |
93fcfe39 | 3954 | qemu_log("\n"); |
91736d37 BS |
3955 | } |
3956 | #endif | |
3957 | count++; | |
3958 | } | |
3959 | #endif | |
3960 | #if !defined(CONFIG_USER_ONLY) | |
3961 | if (env->tl >= env->maxtl) { | |
3962 | cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," | |
3963 | " Error state", env->exception_index, env->tl, env->maxtl); | |
3964 | return; | |
3965 | } | |
3966 | #endif | |
3967 | if (env->tl < env->maxtl - 1) { | |
3968 | env->tl++; | |
3969 | } else { | |
3970 | env->pstate |= PS_RED; | |
3971 | if (env->tl < env->maxtl) | |
3972 | env->tl++; | |
3973 | } | |
8194f35a IK |
3974 | tsptr = cpu_tsptr(env); |
3975 | ||
5a834bb4 | 3976 | tsptr->tstate = (get_ccr() << 32) | |
91736d37 | 3977 | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
5a834bb4 | 3978 | get_cwp64(); |
8194f35a IK |
3979 | tsptr->tpc = env->pc; |
3980 | tsptr->tnpc = env->npc; | |
3981 | tsptr->tt = intno; | |
5210977a IK |
3982 | |
3983 | switch (intno) { | |
3984 | case TT_IVEC: | |
3985 | change_pstate(PS_PEF | PS_PRIV | PS_IG); | |
3986 | break; | |
3987 | case TT_TFAULT: | |
5210977a | 3988 | case TT_DFAULT: |
87f6d3f6 IK |
3989 | case TT_TMISS ... TT_TMISS + 3: |
3990 | case TT_DMISS ... TT_DMISS + 3: | |
3991 | case TT_DPROT ... TT_DPROT + 3: | |
5210977a IK |
3992 | change_pstate(PS_PEF | PS_PRIV | PS_MG); |
3993 | break; | |
3994 | default: | |
3995 | change_pstate(PS_PEF | PS_PRIV | PS_AG); | |
3996 | break; | |
91736d37 | 3997 | } |
5210977a | 3998 | |
5a834bb4 BS |
3999 | if (intno == TT_CLRWIN) { |
4000 | set_cwp(cwp_dec(env->cwp - 1)); | |
4001 | } else if ((intno & 0x1c0) == TT_SPILL) { | |
4002 | set_cwp(cwp_dec(env->cwp - env->cansave - 2)); | |
4003 | } else if ((intno & 0x1c0) == TT_FILL) { | |
4004 | set_cwp(cwp_inc(env->cwp + 1)); | |
4005 | } | |
91736d37 BS |
4006 | env->tbr &= ~0x7fffULL; |
4007 | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); | |
4008 | env->pc = env->tbr; | |
4009 | env->npc = env->pc + 4; | |
821b19fe | 4010 | env->exception_index = -1; |
ee5bbe38 | 4011 | } |
91736d37 BS |
4012 | #else |
4013 | #ifdef DEBUG_PCALL | |
4014 | static const char * const excp_names[0x80] = { | |
4015 | [TT_TFAULT] = "Instruction Access Fault", | |
4016 | [TT_ILL_INSN] = "Illegal Instruction", | |
4017 | [TT_PRIV_INSN] = "Privileged Instruction", | |
4018 | [TT_NFPU_INSN] = "FPU Disabled", | |
4019 | [TT_WIN_OVF] = "Window Overflow", | |
4020 | [TT_WIN_UNF] = "Window Underflow", | |
4021 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
4022 | [TT_FP_EXCP] = "FPU Exception", | |
4023 | [TT_DFAULT] = "Data Access Fault", | |
4024 | [TT_TOVF] = "Tag Overflow", | |
4025 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
4026 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
4027 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
4028 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
4029 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
4030 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
4031 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
4032 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
4033 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
4034 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
4035 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
4036 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
4037 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
4038 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
4039 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
4040 | [TT_TOVF] = "Tag Overflow", | |
4041 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
4042 | [TT_DATA_ACCESS] = "Data Access Error", | |
4043 | [TT_DIV_ZERO] = "Division By Zero", | |
4044 | [TT_NCP_INSN] = "Coprocessor Disabled", | |
4045 | }; | |
4046 | #endif | |
ee5bbe38 | 4047 | |
91736d37 | 4048 | void do_interrupt(CPUState *env) |
ee5bbe38 | 4049 | { |
91736d37 BS |
4050 | int cwp, intno = env->exception_index; |
4051 | ||
4052 | #ifdef DEBUG_PCALL | |
8fec2b8c | 4053 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
91736d37 BS |
4054 | static int count; |
4055 | const char *name; | |
4056 | ||
4057 | if (intno < 0 || intno >= 0x100) | |
4058 | name = "Unknown"; | |
4059 | else if (intno >= 0x80) | |
4060 | name = "Trap Instruction"; | |
4061 | else { | |
4062 | name = excp_names[intno]; | |
4063 | if (!name) | |
4064 | name = "Unknown"; | |
4065 | } | |
4066 | ||
93fcfe39 | 4067 | qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", |
91736d37 BS |
4068 | count, name, intno, |
4069 | env->pc, | |
4070 | env->npc, env->regwptr[6]); | |
93fcfe39 | 4071 | log_cpu_state(env, 0); |
91736d37 BS |
4072 | #if 0 |
4073 | { | |
4074 | int i; | |
4075 | uint8_t *ptr; | |
4076 | ||
93fcfe39 | 4077 | qemu_log(" code="); |
91736d37 BS |
4078 | ptr = (uint8_t *)env->pc; |
4079 | for(i = 0; i < 16; i++) { | |
93fcfe39 | 4080 | qemu_log(" %02x", ldub(ptr + i)); |
91736d37 | 4081 | } |
93fcfe39 | 4082 | qemu_log("\n"); |
91736d37 BS |
4083 | } |
4084 | #endif | |
4085 | count++; | |
4086 | } | |
4087 | #endif | |
4088 | #if !defined(CONFIG_USER_ONLY) | |
4089 | if (env->psret == 0) { | |
4090 | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", | |
4091 | env->exception_index); | |
4092 | return; | |
4093 | } | |
4094 | #endif | |
4095 | env->psret = 0; | |
5a834bb4 BS |
4096 | cwp = cwp_dec(env->cwp - 1); |
4097 | set_cwp(cwp); | |
91736d37 BS |
4098 | env->regwptr[9] = env->pc; |
4099 | env->regwptr[10] = env->npc; | |
4100 | env->psrps = env->psrs; | |
4101 | env->psrs = 1; | |
4102 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); | |
4103 | env->pc = env->tbr; | |
4104 | env->npc = env->pc + 4; | |
95372a39 | 4105 | env->exception_index = -1; |
ee5bbe38 | 4106 | } |
91736d37 | 4107 | #endif |
ee5bbe38 | 4108 | |
5fafdf24 | 4109 | #if !defined(CONFIG_USER_ONLY) |
ee5bbe38 | 4110 | |
d2889a3e BS |
4111 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4112 | void *retaddr); | |
4113 | ||
ee5bbe38 | 4114 | #define MMUSUFFIX _mmu |
d2889a3e | 4115 | #define ALIGNED_ONLY |
ee5bbe38 FB |
4116 | |
4117 | #define SHIFT 0 | |
4118 | #include "softmmu_template.h" | |
4119 | ||
4120 | #define SHIFT 1 | |
4121 | #include "softmmu_template.h" | |
4122 | ||
4123 | #define SHIFT 2 | |
4124 | #include "softmmu_template.h" | |
4125 | ||
4126 | #define SHIFT 3 | |
4127 | #include "softmmu_template.h" | |
4128 | ||
c2bc0e38 BS |
4129 | /* XXX: make it generic ? */ |
4130 | static void cpu_restore_state2(void *retaddr) | |
4131 | { | |
4132 | TranslationBlock *tb; | |
4133 | unsigned long pc; | |
4134 | ||
4135 | if (retaddr) { | |
4136 | /* now we have a real cpu fault */ | |
4137 | pc = (unsigned long)retaddr; | |
4138 | tb = tb_find_pc(pc); | |
4139 | if (tb) { | |
4140 | /* the PC is inside the translated code. It means that we have | |
4141 | a virtual CPU fault */ | |
4142 | cpu_restore_state(tb, env, pc, (void *)(long)env->cond); | |
4143 | } | |
4144 | } | |
4145 | } | |
4146 | ||
d2889a3e BS |
4147 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4148 | void *retaddr) | |
4149 | { | |
94554550 | 4150 | #ifdef DEBUG_UNALIGNED |
c2bc0e38 BS |
4151 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
4152 | "\n", addr, env->pc); | |
94554550 | 4153 | #endif |
c2bc0e38 | 4154 | cpu_restore_state2(retaddr); |
94554550 | 4155 | raise_exception(TT_UNALIGNED); |
d2889a3e | 4156 | } |
ee5bbe38 FB |
4157 | |
4158 | /* try to fill the TLB and return an exception if error. If retaddr is | |
4159 | NULL, it means that the function was called in C code (i.e. not | |
4160 | from generated code or from helper.c) */ | |
4161 | /* XXX: fix it to restore all registers */ | |
6ebbf390 | 4162 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
ee5bbe38 | 4163 | { |
ee5bbe38 | 4164 | int ret; |
ee5bbe38 FB |
4165 | CPUState *saved_env; |
4166 | ||
4167 | /* XXX: hack to restore env in all cases, even if not called from | |
4168 | generated code */ | |
4169 | saved_env = env; | |
4170 | env = cpu_single_env; | |
4171 | ||
6ebbf390 | 4172 | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
ee5bbe38 | 4173 | if (ret) { |
c2bc0e38 | 4174 | cpu_restore_state2(retaddr); |
ee5bbe38 FB |
4175 | cpu_loop_exit(); |
4176 | } | |
4177 | env = saved_env; | |
4178 | } | |
4179 | ||
3c7b48b7 | 4180 | #endif /* !CONFIG_USER_ONLY */ |
6c36d3fa BS |
4181 | |
4182 | #ifndef TARGET_SPARC64 | |
3c7b48b7 | 4183 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 4184 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
e18231a3 | 4185 | int is_asi, int size) |
6c36d3fa BS |
4186 | { |
4187 | CPUState *saved_env; | |
576c2cdc | 4188 | int fault_type; |
6c36d3fa BS |
4189 | |
4190 | /* XXX: hack to restore env in all cases, even if not called from | |
4191 | generated code */ | |
4192 | saved_env = env; | |
4193 | env = cpu_single_env; | |
8543e2cf BS |
4194 | #ifdef DEBUG_UNASSIGNED |
4195 | if (is_asi) | |
e18231a3 | 4196 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx |
77f193da | 4197 | " asi 0x%02x from " TARGET_FMT_lx "\n", |
e18231a3 BS |
4198 | is_exec ? "exec" : is_write ? "write" : "read", size, |
4199 | size == 1 ? "" : "s", addr, is_asi, env->pc); | |
8543e2cf | 4200 | else |
e18231a3 BS |
4201 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx |
4202 | " from " TARGET_FMT_lx "\n", | |
4203 | is_exec ? "exec" : is_write ? "write" : "read", size, | |
4204 | size == 1 ? "" : "s", addr, env->pc); | |
8543e2cf | 4205 | #endif |
576c2cdc AT |
4206 | /* Don't overwrite translation and access faults */ |
4207 | fault_type = (env->mmuregs[3] & 0x1c) >> 2; | |
4208 | if ((fault_type > 4) || (fault_type == 0)) { | |
4209 | env->mmuregs[3] = 0; /* Fault status register */ | |
4210 | if (is_asi) | |
4211 | env->mmuregs[3] |= 1 << 16; | |
4212 | if (env->psrs) | |
4213 | env->mmuregs[3] |= 1 << 5; | |
4214 | if (is_exec) | |
4215 | env->mmuregs[3] |= 1 << 6; | |
4216 | if (is_write) | |
4217 | env->mmuregs[3] |= 1 << 7; | |
4218 | env->mmuregs[3] |= (5 << 2) | 2; | |
4219 | /* SuperSPARC will never place instruction fault addresses in the FAR */ | |
4220 | if (!is_exec) { | |
4221 | env->mmuregs[4] = addr; /* Fault address register */ | |
4222 | } | |
4223 | } | |
4224 | /* overflow (same type fault was not read before another fault) */ | |
4225 | if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { | |
4226 | env->mmuregs[3] |= 1; | |
4227 | } | |
4228 | ||
6c36d3fa | 4229 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
1b2e93c1 BS |
4230 | if (is_exec) |
4231 | raise_exception(TT_CODE_ACCESS); | |
4232 | else | |
4233 | raise_exception(TT_DATA_ACCESS); | |
6c36d3fa | 4234 | } |
576c2cdc AT |
4235 | |
4236 | /* flush neverland mappings created during no-fault mode, | |
4237 | so the sequential MMU faults report proper fault types */ | |
4238 | if (env->mmuregs[0] & MMU_NF) { | |
4239 | tlb_flush(env, 1); | |
4240 | } | |
15e7c451 AT |
4241 | |
4242 | env = saved_env; | |
6c36d3fa | 4243 | } |
3c7b48b7 PB |
4244 | #endif |
4245 | #else | |
4246 | #if defined(CONFIG_USER_ONLY) | |
4247 | static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, | |
4248 | int is_asi, int size) | |
6c36d3fa | 4249 | #else |
c227f099 | 4250 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
e18231a3 | 4251 | int is_asi, int size) |
3c7b48b7 | 4252 | #endif |
6c36d3fa | 4253 | { |
6c36d3fa BS |
4254 | CPUState *saved_env; |
4255 | ||
4256 | /* XXX: hack to restore env in all cases, even if not called from | |
4257 | generated code */ | |
4258 | saved_env = env; | |
4259 | env = cpu_single_env; | |
dffbe217 IK |
4260 | |
4261 | #ifdef DEBUG_UNASSIGNED | |
77f193da BS |
4262 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
4263 | "\n", addr, env->pc); | |
6c36d3fa | 4264 | #endif |
dffbe217 | 4265 | |
1b2e93c1 BS |
4266 | if (is_exec) |
4267 | raise_exception(TT_CODE_ACCESS); | |
4268 | else | |
4269 | raise_exception(TT_DATA_ACCESS); | |
dffbe217 IK |
4270 | |
4271 | env = saved_env; | |
6c36d3fa BS |
4272 | } |
4273 | #endif | |
20c9f095 | 4274 | |
3c7b48b7 | 4275 | |
f4b1a842 BS |
4276 | #ifdef TARGET_SPARC64 |
4277 | void helper_tick_set_count(void *opaque, uint64_t count) | |
4278 | { | |
4279 | #if !defined(CONFIG_USER_ONLY) | |
4280 | cpu_tick_set_count(opaque, count); | |
4281 | #endif | |
4282 | } | |
4283 | ||
4284 | uint64_t helper_tick_get_count(void *opaque) | |
4285 | { | |
4286 | #if !defined(CONFIG_USER_ONLY) | |
4287 | return cpu_tick_get_count(opaque); | |
4288 | #else | |
4289 | return 0; | |
4290 | #endif | |
4291 | } | |
4292 | ||
4293 | void helper_tick_set_limit(void *opaque, uint64_t limit) | |
4294 | { | |
4295 | #if !defined(CONFIG_USER_ONLY) | |
4296 | cpu_tick_set_limit(opaque, limit); | |
4297 | #endif | |
4298 | } | |
4299 | #endif |