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Convert movr and (partially) movcc to TCG
[mirror_qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
bd497938 28*/
7a3f1944
FB		 29
30#include <stdarg.h>
31#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <inttypes.h>
35
36#include "cpu.h"
37#include "exec-all.h"
38#include "disas.h"
1a2fb1c0 39#include "helper.h"
57fec1fe 40#include "tcg-op.h"
7a3f1944
FB		 41
42#define DEBUG_DISAS
43
72cbca10
FB		 44#define DYNAMIC_PC 1 /* dynamic pc value */
45#define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
47
1a2fb1c0
BS		 48/* global register indexes */
49static TCGv cpu_env, cpu_T[3], cpu_regwptr;
50/* local register indexes (only used inside old micro ops) */
51static TCGv cpu_tmp0;
52
7a3f1944 53typedef struct DisasContext {
0f8a249a
BS		 54 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 56 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 57 int is_br;
e8af50a3 58 int mem_idx;
a80dde08 59 int fpu_enabled;
cf495bcf 60 struct TranslationBlock *tb;
7a3f1944
FB		 61} DisasContext;
62
aaed909a
FB		 63typedef struct sparc_def_t sparc_def_t;
64
62724a37
BS		 65struct sparc_def_t {
66 const unsigned char *name;
67 target_ulong iu_version;
68 uint32_t fpu_version;
69 uint32_t mmu_version;
6d5f237a 70 uint32_t mmu_bm;
3deaeab7
BS		 71 uint32_t mmu_ctpr_mask;
72 uint32_t mmu_cxr_mask;
73 uint32_t mmu_sfsr_mask;
74 uint32_t mmu_trcr_mask;
62724a37
BS		 75};
76
aaed909a
FB		 77static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
78
7a3f1944
FB		 79extern FILE *logfile;
80extern int loglevel;
81
3475187d 82// This function uses non-native bit order
7a3f1944
FB		 83#define GET_FIELD(X, FROM, TO) \
84 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
85
3475187d
FB		 86// This function uses the order in the manuals, i.e. bit 0 is 2^0
87#define GET_FIELD_SP(X, FROM, TO) \
88 GET_FIELD(X, 31 - (TO), 31 - (FROM))
89
90#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 91#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 92
93#ifdef TARGET_SPARC64
0387d928 94#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 95#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 96#else
c185970a 97#define DFPREG(r) (r & 0x1e)
1f587329 98#define QFPREG(r) (r & 0x1c)
3475187d
FB		 99#endif
100
101static int sign_extend(int x, int len)
102{
103 len = 32 - len;
104 return (x << len) >> len;
105}
106
7a3f1944
FB		 107#define IS_IMM (insn & (1<<13))
108
cf495bcf 109static void disas_sparc_insn(DisasContext * dc);
7a3f1944 110
3475187d
FB		 111#ifdef TARGET_SPARC64
112#define GEN32(func, NAME) \
a68156d0 113static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 114NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
115NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
116NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
117NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
118NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
119NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
120NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
121NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
122NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
123NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
124NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
125NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
126}; \
127static inline void func(int n) \
128{ \
129 NAME ## _table[n](); \
130}
131#else
e8af50a3 132#define GEN32(func, NAME) \
a68156d0 133static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 134NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
135NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
136NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
137NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
138NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
139NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
140NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
141NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
142}; \
143static inline void func(int n) \
144{ \
145 NAME ## _table[n](); \
146}
3475187d 147#endif
e8af50a3
FB		 148
149/* floating point registers moves */
150GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
151GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 152GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
153GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 154
155GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
156GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 157GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
158GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 159
1f587329
BS		 160#if defined(CONFIG_USER_ONLY)
161GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
162GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
163GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
164GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
165#endif
166
81ad8ba2
BS		 167/* moves */
168#ifdef CONFIG_USER_ONLY
3475187d 169#define supervisor(dc) 0
81ad8ba2 170#ifdef TARGET_SPARC64
e9ebed4d 171#define hypervisor(dc) 0
81ad8ba2 172#endif
3475187d 173#define gen_op_ldst(name) gen_op_##name##_raw()
3475187d 174#else
6f27aba6 175#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 176#ifdef TARGET_SPARC64
177#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6
BS		 178#define OP_LD_TABLE(width) \
179 static GenOpFunc * const gen_op_##width[] = { \
180 &gen_op_##width##_user, \
181 &gen_op_##width##_kernel, \
182 &gen_op_##width##_hypv, \
183 };
184#else
0f8a249a 185#define OP_LD_TABLE(width) \
a68156d0 186 static GenOpFunc * const gen_op_##width[] = { \
0f8a249a
BS		 187 &gen_op_##width##_user, \
188 &gen_op_##width##_kernel, \
81ad8ba2 189 };
3475187d 190#endif
6f27aba6
BS		 191#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
192#endif
e8af50a3 193
81ad8ba2 194#ifndef CONFIG_USER_ONLY
b25deda7
BS		 195#ifdef __i386__
196OP_LD_TABLE(std);
197#endif /* __i386__ */
e8af50a3
FB		 198OP_LD_TABLE(stf);
199OP_LD_TABLE(stdf);
200OP_LD_TABLE(ldf);
201OP_LD_TABLE(lddf);
81ad8ba2
BS		 202#endif
203
1a2fb1c0
BS		 204#ifdef TARGET_ABI32
205#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
206#else
207#define ABI32_MASK(addr)
208#endif
3391c818 209
1a2fb1c0 210static inline void gen_movl_simm_T1(int32_t val)
81ad8ba2 211{
1a2fb1c0 212 tcg_gen_movi_tl(cpu_T[1], val);
81ad8ba2
BS		 213}
214
1a2fb1c0 215static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 216{
1a2fb1c0
BS		 217 if (reg == 0)
218 tcg_gen_movi_tl(tn, 0);
219 else if (reg < 8)
220 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
221 else {
222 tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX
223 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 224 }
225}
226
1a2fb1c0 227static inline void gen_movl_reg_T0(int reg)
81ad8ba2 228{
1a2fb1c0 229 gen_movl_reg_TN(reg, cpu_T[0]);
81ad8ba2
BS		 230}
231
1a2fb1c0 232static inline void gen_movl_reg_T1(int reg)
81ad8ba2 233{
1a2fb1c0 234 gen_movl_reg_TN(reg, cpu_T[1]);
81ad8ba2
BS		 235}
236
b25deda7
BS		 237#ifdef __i386__
238static inline void gen_movl_reg_T2(int reg)
239{
240 gen_movl_reg_TN(reg, cpu_T[2]);
241}
242
243#endif /* __i386__ */
1a2fb1c0 244static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 245{
1a2fb1c0
BS		 246 if (reg == 0)
247 return;
248 else if (reg < 8)
249 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
250 else {
251 tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX
252 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 253 }
254}
255
1a2fb1c0 256static inline void gen_movl_T0_reg(int reg)
3475187d 257{
1a2fb1c0 258 gen_movl_TN_reg(reg, cpu_T[0]);
3475187d
FB		 259}
260
1a2fb1c0 261static inline void gen_movl_T1_reg(int reg)
3475187d 262{
1a2fb1c0 263 gen_movl_TN_reg(reg, cpu_T[1]);
3475187d
FB		 264}
265
1a2fb1c0 266static inline void gen_op_movl_T0_env(size_t offset)
7a3f1944 267{
1a2fb1c0 268 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 269}
270
1a2fb1c0 271static inline void gen_op_movl_env_T0(size_t offset)
7a3f1944 272{
1a2fb1c0 273 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 274}
275
1a2fb1c0 276static inline void gen_op_movtl_T0_env(size_t offset)
7a3f1944 277{
1a2fb1c0 278 tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 279}
280
1a2fb1c0 281static inline void gen_op_movtl_env_T0(size_t offset)
7a3f1944 282{
1a2fb1c0 283 tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 284}
285
1a2fb1c0 286static inline void gen_op_add_T1_T0(void)
7a3f1944 287{
1a2fb1c0 288 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 289}
290
1a2fb1c0 291static inline void gen_op_or_T1_T0(void)
7a3f1944 292{
1a2fb1c0 293 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 294}
295
1a2fb1c0 296static inline void gen_op_xor_T1_T0(void)
7a3f1944 297{
1a2fb1c0 298 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 299}
300
3475187d
FB		 301static inline void gen_jmp_im(target_ulong pc)
302{
1a2fb1c0
BS		 303 tcg_gen_movi_tl(cpu_tmp0, pc);
304 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
3475187d
FB		 305}
306
307static inline void gen_movl_npc_im(target_ulong npc)
308{
1a2fb1c0
BS		 309 tcg_gen_movi_tl(cpu_tmp0, npc);
310 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
3475187d
FB		 311}
312
5fafdf24 313static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 314 target_ulong pc, target_ulong npc)
315{
316 TranslationBlock *tb;
317
318 tb = s->tb;
319 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
320 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
321 /* jump to same page: we can use a direct jump */
57fec1fe 322 tcg_gen_goto_tb(tb_num);
6e256c93
FB		 323 gen_jmp_im(pc);
324 gen_movl_npc_im(npc);
57fec1fe 325 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 326 } else {
327 /* jump to another page: currently not optimized */
328 gen_jmp_im(pc);
329 gen_movl_npc_im(npc);
57fec1fe 330 tcg_gen_exit_tb(0);
6e256c93
FB		 331 }
332}
333
46525e1f
BS		 334static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
335 target_ulong pc2)
83469015
FB		 336{
337 int l1;
338
339 l1 = gen_new_label();
340
341 gen_op_jz_T2_label(l1);
342
6e256c93 343 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 344
345 gen_set_label(l1);
6e256c93 346 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 347}
348
46525e1f
BS		 349static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
350 target_ulong pc2)
83469015
FB		 351{
352 int l1;
353
354 l1 = gen_new_label();
355
356 gen_op_jz_T2_label(l1);
357
6e256c93 358 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 359
360 gen_set_label(l1);
6e256c93 361 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 362}
363
46525e1f
BS		 364static inline void gen_branch(DisasContext *dc, target_ulong pc,
365 target_ulong npc)
83469015 366{
6e256c93 367 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 368}
369
46525e1f 370static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
83469015
FB		 371{
372 int l1, l2;
373
374 l1 = gen_new_label();
375 l2 = gen_new_label();
376 gen_op_jz_T2_label(l1);
377
378 gen_movl_npc_im(npc1);
379 gen_op_jmp_label(l2);
380
381 gen_set_label(l1);
382 gen_movl_npc_im(npc2);
383 gen_set_label(l2);
384}
385
386/* call this function before using T2 as it may have been set for a jump */
387static inline void flush_T2(DisasContext * dc)
388{
389 if (dc->npc == JUMP_PC) {
46525e1f 390 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
83469015
FB		 391 dc->npc = DYNAMIC_PC;
392 }
393}
394
72cbca10
FB		 395static inline void save_npc(DisasContext * dc)
396{
397 if (dc->npc == JUMP_PC) {
46525e1f 398 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 399 dc->npc = DYNAMIC_PC;
400 } else if (dc->npc != DYNAMIC_PC) {
3475187d 401 gen_movl_npc_im(dc->npc);
72cbca10
FB		 402 }
403}
404
405static inline void save_state(DisasContext * dc)
406{
3475187d 407 gen_jmp_im(dc->pc);
72cbca10
FB		 408 save_npc(dc);
409}
410
0bee699e
FB		 411static inline void gen_mov_pc_npc(DisasContext * dc)
412{
413 if (dc->npc == JUMP_PC) {
46525e1f 414 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
38bc628b
BS		 415 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
416 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 417 dc->pc = DYNAMIC_PC;
418 } else if (dc->npc == DYNAMIC_PC) {
38bc628b
BS		 419 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
420 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 421 dc->pc = DYNAMIC_PC;
422 } else {
423 dc->pc = dc->npc;
424 }
425}
426
38bc628b
BS		 427static inline void gen_op_next_insn(void)
428{
429 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
430 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
431 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
432 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
433}
434
3475187d
FB		 435static GenOpFunc * const gen_cond[2][16] = {
436 {
0f8a249a
BS		 437 gen_op_eval_bn,
438 gen_op_eval_be,
439 gen_op_eval_ble,
440 gen_op_eval_bl,
441 gen_op_eval_bleu,
442 gen_op_eval_bcs,
443 gen_op_eval_bneg,
444 gen_op_eval_bvs,
445 gen_op_eval_ba,
446 gen_op_eval_bne,
447 gen_op_eval_bg,
448 gen_op_eval_bge,
449 gen_op_eval_bgu,
450 gen_op_eval_bcc,
451 gen_op_eval_bpos,
452 gen_op_eval_bvc,
3475187d
FB		 453 },
454 {
455#ifdef TARGET_SPARC64
0f8a249a
BS		 456 gen_op_eval_bn,
457 gen_op_eval_xbe,
458 gen_op_eval_xble,
459 gen_op_eval_xbl,
460 gen_op_eval_xbleu,
461 gen_op_eval_xbcs,
462 gen_op_eval_xbneg,
463 gen_op_eval_xbvs,
464 gen_op_eval_ba,
465 gen_op_eval_xbne,
466 gen_op_eval_xbg,
467 gen_op_eval_xbge,
468 gen_op_eval_xbgu,
469 gen_op_eval_xbcc,
470 gen_op_eval_xbpos,
471 gen_op_eval_xbvc,
3475187d
FB		 472#endif
473 },
474};
475
476static GenOpFunc * const gen_fcond[4][16] = {
477 {
0f8a249a
BS		 478 gen_op_eval_bn,
479 gen_op_eval_fbne,
480 gen_op_eval_fblg,
481 gen_op_eval_fbul,
482 gen_op_eval_fbl,
483 gen_op_eval_fbug,
484 gen_op_eval_fbg,
485 gen_op_eval_fbu,
486 gen_op_eval_ba,
487 gen_op_eval_fbe,
488 gen_op_eval_fbue,
489 gen_op_eval_fbge,
490 gen_op_eval_fbuge,
491 gen_op_eval_fble,
492 gen_op_eval_fbule,
493 gen_op_eval_fbo,
3475187d
FB		 494 },
495#ifdef TARGET_SPARC64
496 {
0f8a249a
BS		 497 gen_op_eval_bn,
498 gen_op_eval_fbne_fcc1,
499 gen_op_eval_fblg_fcc1,
500 gen_op_eval_fbul_fcc1,
501 gen_op_eval_fbl_fcc1,
502 gen_op_eval_fbug_fcc1,
503 gen_op_eval_fbg_fcc1,
504 gen_op_eval_fbu_fcc1,
505 gen_op_eval_ba,
506 gen_op_eval_fbe_fcc1,
507 gen_op_eval_fbue_fcc1,
508 gen_op_eval_fbge_fcc1,
509 gen_op_eval_fbuge_fcc1,
510 gen_op_eval_fble_fcc1,
511 gen_op_eval_fbule_fcc1,
512 gen_op_eval_fbo_fcc1,
3475187d
FB		 513 },
514 {
0f8a249a
BS		 515 gen_op_eval_bn,
516 gen_op_eval_fbne_fcc2,
517 gen_op_eval_fblg_fcc2,
518 gen_op_eval_fbul_fcc2,
519 gen_op_eval_fbl_fcc2,
520 gen_op_eval_fbug_fcc2,
521 gen_op_eval_fbg_fcc2,
522 gen_op_eval_fbu_fcc2,
523 gen_op_eval_ba,
524 gen_op_eval_fbe_fcc2,
525 gen_op_eval_fbue_fcc2,
526 gen_op_eval_fbge_fcc2,
527 gen_op_eval_fbuge_fcc2,
528 gen_op_eval_fble_fcc2,
529 gen_op_eval_fbule_fcc2,
530 gen_op_eval_fbo_fcc2,
3475187d
FB		 531 },
532 {
0f8a249a
BS		 533 gen_op_eval_bn,
534 gen_op_eval_fbne_fcc3,
535 gen_op_eval_fblg_fcc3,
536 gen_op_eval_fbul_fcc3,
537 gen_op_eval_fbl_fcc3,
538 gen_op_eval_fbug_fcc3,
539 gen_op_eval_fbg_fcc3,
540 gen_op_eval_fbu_fcc3,
541 gen_op_eval_ba,
542 gen_op_eval_fbe_fcc3,
543 gen_op_eval_fbue_fcc3,
544 gen_op_eval_fbge_fcc3,
545 gen_op_eval_fbuge_fcc3,
546 gen_op_eval_fble_fcc3,
547 gen_op_eval_fbule_fcc3,
548 gen_op_eval_fbo_fcc3,
3475187d
FB		 549 },
550#else
551 {}, {}, {},
552#endif
553};
7a3f1944 554
3475187d
FB		 555#ifdef TARGET_SPARC64
556static void gen_cond_reg(int cond)
e8af50a3 557{
0f8a249a
BS		 558 switch (cond) {
559 case 0x1:
560 gen_op_eval_brz();
561 break;
562 case 0x2:
563 gen_op_eval_brlez();
564 break;
565 case 0x3:
566 gen_op_eval_brlz();
567 break;
568 case 0x5:
569 gen_op_eval_brnz();
570 break;
571 case 0x6:
572 gen_op_eval_brgz();
573 break;
e8af50a3 574 default:
0f8a249a
BS		 575 case 0x7:
576 gen_op_eval_brgez();
577 break;
578 }
e8af50a3 579}
00f219bf
BS		 580
581// Inverted logic
582static const int gen_tcg_cond_reg[8] = {
583 -1,
584 TCG_COND_NE,
585 TCG_COND_GT,
586 TCG_COND_GE,
587 -1,
588 TCG_COND_EQ,
589 TCG_COND_LE,
590 TCG_COND_LT,
591};
3475187d 592#endif
cf495bcf 593
0bee699e 594/* XXX: potentially incorrect if dynamic npc */
3475187d 595static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 596{
cf495bcf 597 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 598 target_ulong target = dc->pc + offset;
5fafdf24 599
cf495bcf 600 if (cond == 0x0) {
0f8a249a
BS		 601 /* unconditional not taken */
602 if (a) {
603 dc->pc = dc->npc + 4;
604 dc->npc = dc->pc + 4;
605 } else {
606 dc->pc = dc->npc;
607 dc->npc = dc->pc + 4;
608 }
cf495bcf 609 } else if (cond == 0x8) {
0f8a249a
BS		 610 /* unconditional taken */
611 if (a) {
612 dc->pc = target;
613 dc->npc = dc->pc + 4;
614 } else {
615 dc->pc = dc->npc;
616 dc->npc = target;
617 }
cf495bcf 618 } else {
72cbca10 619 flush_T2(dc);
3475187d 620 gen_cond[cc][cond]();
0f8a249a
BS		 621 if (a) {
622 gen_branch_a(dc, target, dc->npc);
cf495bcf 623 dc->is_br = 1;
0f8a249a 624 } else {
cf495bcf 625 dc->pc = dc->npc;
72cbca10
FB		 626 dc->jump_pc[0] = target;
627 dc->jump_pc[1] = dc->npc + 4;
628 dc->npc = JUMP_PC;
0f8a249a 629 }
cf495bcf 630 }
7a3f1944
FB		 631}
632
0bee699e 633/* XXX: potentially incorrect if dynamic npc */
3475187d 634static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 635{
636 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 637 target_ulong target = dc->pc + offset;
638
e8af50a3 639 if (cond == 0x0) {
0f8a249a
BS		 640 /* unconditional not taken */
641 if (a) {
642 dc->pc = dc->npc + 4;
643 dc->npc = dc->pc + 4;
644 } else {
645 dc->pc = dc->npc;
646 dc->npc = dc->pc + 4;
647 }
e8af50a3 648 } else if (cond == 0x8) {
0f8a249a
BS		 649 /* unconditional taken */
650 if (a) {
651 dc->pc = target;
652 dc->npc = dc->pc + 4;
653 } else {
654 dc->pc = dc->npc;
655 dc->npc = target;
656 }
e8af50a3
FB		 657 } else {
658 flush_T2(dc);
3475187d 659 gen_fcond[cc][cond]();
0f8a249a
BS		 660 if (a) {
661 gen_branch_a(dc, target, dc->npc);
e8af50a3 662 dc->is_br = 1;
0f8a249a 663 } else {
e8af50a3
FB		 664 dc->pc = dc->npc;
665 dc->jump_pc[0] = target;
666 dc->jump_pc[1] = dc->npc + 4;
667 dc->npc = JUMP_PC;
0f8a249a 668 }
e8af50a3
FB		 669 }
670}
671
3475187d
FB		 672#ifdef TARGET_SPARC64
673/* XXX: potentially incorrect if dynamic npc */
674static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 675{
3475187d
FB		 676 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
677 target_ulong target = dc->pc + offset;
678
679 flush_T2(dc);
680 gen_cond_reg(cond);
681 if (a) {
0f8a249a
BS		 682 gen_branch_a(dc, target, dc->npc);
683 dc->is_br = 1;
3475187d 684 } else {
0f8a249a
BS		 685 dc->pc = dc->npc;
686 dc->jump_pc[0] = target;
687 dc->jump_pc[1] = dc->npc + 4;
688 dc->npc = JUMP_PC;
3475187d 689 }
7a3f1944
FB		 690}
691
3475187d
FB		 692static GenOpFunc * const gen_fcmps[4] = {
693 gen_op_fcmps,
694 gen_op_fcmps_fcc1,
695 gen_op_fcmps_fcc2,
696 gen_op_fcmps_fcc3,
697};
698
699static GenOpFunc * const gen_fcmpd[4] = {
700 gen_op_fcmpd,
701 gen_op_fcmpd_fcc1,
702 gen_op_fcmpd_fcc2,
703 gen_op_fcmpd_fcc3,
704};
417454b0 705
1f587329
BS		 706#if defined(CONFIG_USER_ONLY)
707static GenOpFunc * const gen_fcmpq[4] = {
708 gen_op_fcmpq,
709 gen_op_fcmpq_fcc1,
710 gen_op_fcmpq_fcc2,
711 gen_op_fcmpq_fcc3,
712};
713#endif
714
417454b0
BS		 715static GenOpFunc * const gen_fcmpes[4] = {
716 gen_op_fcmpes,
717 gen_op_fcmpes_fcc1,
718 gen_op_fcmpes_fcc2,
719 gen_op_fcmpes_fcc3,
720};
721
722static GenOpFunc * const gen_fcmped[4] = {
723 gen_op_fcmped,
724 gen_op_fcmped_fcc1,
725 gen_op_fcmped_fcc2,
726 gen_op_fcmped_fcc3,
727};
728
1f587329
BS		 729#if defined(CONFIG_USER_ONLY)
730static GenOpFunc * const gen_fcmpeq[4] = {
731 gen_op_fcmpeq,
732 gen_op_fcmpeq_fcc1,
733 gen_op_fcmpeq_fcc2,
734 gen_op_fcmpeq_fcc3,
735};
736#endif
3475187d
FB		 737#endif
738
a80dde08
FB		 739static int gen_trap_ifnofpu(DisasContext * dc)
740{
741#if !defined(CONFIG_USER_ONLY)
742 if (!dc->fpu_enabled) {
743 save_state(dc);
744 gen_op_exception(TT_NFPU_INSN);
745 dc->is_br = 1;
746 return 1;
747 }
748#endif
749 return 0;
750}
751
1a2fb1c0
BS		 752/* asi moves */
753#ifdef TARGET_SPARC64
754static inline void gen_ld_asi(int insn, int size, int sign)
755{
756 int asi, offset;
757 TCGv r_size, r_sign;
758
759 r_size = tcg_temp_new(TCG_TYPE_I32);
760 r_sign = tcg_temp_new(TCG_TYPE_I32);
761 tcg_gen_movi_i32(r_size, size);
762 tcg_gen_movi_i32(r_sign, sign);
763 if (IS_IMM) {
764 offset = GET_FIELD(insn, 25, 31);
765 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
766 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
767 } else {
768 asi = GET_FIELD(insn, 19, 26);
769 tcg_gen_movi_i32(cpu_T[1], asi);
770 }
771 tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
772 r_sign);
773}
774
775static inline void gen_st_asi(int insn, int size)
776{
777 int asi, offset;
778 TCGv r_asi, r_size;
779
780 r_asi = tcg_temp_new(TCG_TYPE_I32);
781 r_size = tcg_temp_new(TCG_TYPE_I32);
782 tcg_gen_movi_i32(r_size, size);
783 if (IS_IMM) {
784 offset = GET_FIELD(insn, 25, 31);
785 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
786 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
787 } else {
788 asi = GET_FIELD(insn, 19, 26);
789 tcg_gen_movi_i32(r_asi, asi);
790 }
791 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
792}
793
794static inline void gen_ldf_asi(int insn, int size, int rd)
795{
796 int asi, offset;
797 TCGv r_asi, r_size, r_rd;
798
799 r_asi = tcg_temp_new(TCG_TYPE_I32);
800 r_size = tcg_temp_new(TCG_TYPE_I32);
801 r_rd = tcg_temp_new(TCG_TYPE_I32);
802 tcg_gen_movi_i32(r_size, size);
803 tcg_gen_movi_i32(r_rd, rd);
804 if (IS_IMM) {
805 offset = GET_FIELD(insn, 25, 31);
806 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
807 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
808 } else {
809 asi = GET_FIELD(insn, 19, 26);
810 tcg_gen_movi_i32(r_asi, asi);
811 }
812 tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
813}
814
815static inline void gen_stf_asi(int insn, int size, int rd)
816{
817 int asi, offset;
818 TCGv r_asi, r_size, r_rd;
819
820 r_asi = tcg_temp_new(TCG_TYPE_I32);
821 r_size = tcg_temp_new(TCG_TYPE_I32);
822 r_rd = tcg_temp_new(TCG_TYPE_I32);
823 tcg_gen_movi_i32(r_size, size);
824 tcg_gen_movi_i32(r_rd, rd);
825 if (IS_IMM) {
826 offset = GET_FIELD(insn, 25, 31);
827 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
828 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
829 } else {
830 asi = GET_FIELD(insn, 19, 26);
831 tcg_gen_movi_i32(r_asi, asi);
832 }
833 tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
834}
835
836static inline void gen_swap_asi(int insn)
837{
838 int asi, offset;
839 TCGv r_size, r_sign, r_temp;
840
841 r_size = tcg_temp_new(TCG_TYPE_I32);
842 r_sign = tcg_temp_new(TCG_TYPE_I32);
843 r_temp = tcg_temp_new(TCG_TYPE_I32);
844 tcg_gen_movi_i32(r_size, 4);
845 tcg_gen_movi_i32(r_sign, 0);
846 if (IS_IMM) {
847 offset = GET_FIELD(insn, 25, 31);
848 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
849 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
850 } else {
851 asi = GET_FIELD(insn, 19, 26);
852 tcg_gen_movi_i32(cpu_T[1], asi);
853 }
854 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
855 r_sign);
856 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
857 tcg_gen_mov_i32(cpu_T[1], r_temp);
858}
859
860static inline void gen_ldda_asi(int insn)
861{
862 int asi, offset;
863 TCGv r_size, r_sign, r_dword;
864
865 r_size = tcg_temp_new(TCG_TYPE_I32);
866 r_sign = tcg_temp_new(TCG_TYPE_I32);
867 r_dword = tcg_temp_new(TCG_TYPE_I64);
868 tcg_gen_movi_i32(r_size, 8);
869 tcg_gen_movi_i32(r_sign, 0);
870 if (IS_IMM) {
871 offset = GET_FIELD(insn, 25, 31);
872 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
873 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
874 } else {
875 asi = GET_FIELD(insn, 19, 26);
876 tcg_gen_movi_i32(cpu_T[1], asi);
877 }
878 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
879 r_sign);
880 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
881 tcg_gen_shri_i64(r_dword, r_dword, 32);
882 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
883}
884
885static inline void gen_cas_asi(int insn, int rd)
886{
887 int asi, offset;
888 TCGv r_val1, r_asi;
889
890 r_val1 = tcg_temp_new(TCG_TYPE_I32);
891 r_asi = tcg_temp_new(TCG_TYPE_I32);
892 gen_movl_reg_TN(rd, r_val1);
893 if (IS_IMM) {
894 offset = GET_FIELD(insn, 25, 31);
895 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
896 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
897 } else {
898 asi = GET_FIELD(insn, 19, 26);
899 tcg_gen_movi_i32(r_asi, asi);
900 }
901 tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
902 r_asi);
903}
904
905static inline void gen_casx_asi(int insn, int rd)
906{
907 int asi, offset;
908 TCGv r_val1, r_asi;
909
910 r_val1 = tcg_temp_new(TCG_TYPE_I64);
911 r_asi = tcg_temp_new(TCG_TYPE_I32);
912 gen_movl_reg_TN(rd, r_val1);
913 if (IS_IMM) {
914 offset = GET_FIELD(insn, 25, 31);
915 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
916 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
917 } else {
918 asi = GET_FIELD(insn, 19, 26);
919 tcg_gen_movi_i32(r_asi, asi);
920 }
921 tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
922 r_asi);
923}
924
925#elif !defined(CONFIG_USER_ONLY)
926
927static inline void gen_ld_asi(int insn, int size, int sign)
928{
929 int asi;
930 TCGv r_size, r_sign, r_dword;
931
932 r_size = tcg_temp_new(TCG_TYPE_I32);
933 r_sign = tcg_temp_new(TCG_TYPE_I32);
934 r_dword = tcg_temp_new(TCG_TYPE_I64);
935 tcg_gen_movi_i32(r_size, size);
936 tcg_gen_movi_i32(r_sign, sign);
937 asi = GET_FIELD(insn, 19, 26);
938 tcg_gen_movi_i32(cpu_T[1], asi);
939 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
940 r_sign);
941 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
942}
943
944static inline void gen_st_asi(int insn, int size)
945{
946 int asi;
947 TCGv r_dword, r_asi, r_size;
948
949 r_dword = tcg_temp_new(TCG_TYPE_I64);
950 tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
951 r_asi = tcg_temp_new(TCG_TYPE_I32);
952 r_size = tcg_temp_new(TCG_TYPE_I32);
953 asi = GET_FIELD(insn, 19, 26);
954 tcg_gen_movi_i32(r_asi, asi);
955 tcg_gen_movi_i32(r_size, size);
956 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
957}
958
959static inline void gen_swap_asi(int insn)
960{
961 int asi;
962 TCGv r_size, r_sign, r_temp;
963
964 r_size = tcg_temp_new(TCG_TYPE_I32);
965 r_sign = tcg_temp_new(TCG_TYPE_I32);
966 r_temp = tcg_temp_new(TCG_TYPE_I32);
967 tcg_gen_movi_i32(r_size, 4);
968 tcg_gen_movi_i32(r_sign, 0);
969 asi = GET_FIELD(insn, 19, 26);
970 tcg_gen_movi_i32(cpu_T[1], asi);
971 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
972 r_sign);
973 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
974 tcg_gen_mov_i32(cpu_T[1], r_temp);
975}
976
977static inline void gen_ldda_asi(int insn)
978{
979 int asi;
980 TCGv r_size, r_sign, r_dword;
981
982 r_size = tcg_temp_new(TCG_TYPE_I32);
983 r_sign = tcg_temp_new(TCG_TYPE_I32);
984 r_dword = tcg_temp_new(TCG_TYPE_I64);
985 tcg_gen_movi_i32(r_size, 8);
986 tcg_gen_movi_i32(r_sign, 0);
987 asi = GET_FIELD(insn, 19, 26);
988 tcg_gen_movi_i32(cpu_T[1], asi);
989 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
990 r_sign);
991 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
992 tcg_gen_shri_i64(r_dword, r_dword, 32);
993 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
994}
995#endif
996
997#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
998static inline void gen_ldstub_asi(int insn)
999{
1000 int asi;
1001 TCGv r_dword, r_asi, r_size;
1002
1003 gen_ld_asi(insn, 1, 0);
1004
1005 r_dword = tcg_temp_new(TCG_TYPE_I64);
1006 r_asi = tcg_temp_new(TCG_TYPE_I32);
1007 r_size = tcg_temp_new(TCG_TYPE_I32);
1008 asi = GET_FIELD(insn, 19, 26);
1009 tcg_gen_movi_i32(r_dword, 0xff);
1010 tcg_gen_movi_i32(r_asi, asi);
1011 tcg_gen_movi_i32(r_size, 1);
1012 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1013}
1014#endif
1015
38bc628b
BS		 1016static inline void gen_mov_reg_C(TCGv reg)
1017{
1018 tcg_gen_ld_i32(reg, cpu_env, offsetof(CPUSPARCState, psr));
1019 tcg_gen_shri_i32(reg, reg, 20);
1020 tcg_gen_andi_i32(reg, reg, 0x1);
1021}
1022
0bee699e 1023/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1024static void disas_sparc_insn(DisasContext * dc)
1025{
1026 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1027
0fa85d43 1028 insn = ldl_code(dc->pc);
cf495bcf 1029 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1030
cf495bcf
FB		 1031 rd = GET_FIELD(insn, 2, 6);
1032 switch (opc) {
0f8a249a
BS		 1033 case 0: /* branches/sethi */
1034 {
1035 unsigned int xop = GET_FIELD(insn, 7, 9);
1036 int32_t target;
1037 switch (xop) {
3475187d 1038#ifdef TARGET_SPARC64
0f8a249a
BS		 1039 case 0x1: /* V9 BPcc */
1040 {
1041 int cc;
1042
1043 target = GET_FIELD_SP(insn, 0, 18);
1044 target = sign_extend(target, 18);
1045 target <<= 2;
1046 cc = GET_FIELD_SP(insn, 20, 21);
1047 if (cc == 0)
1048 do_branch(dc, target, insn, 0);
1049 else if (cc == 2)
1050 do_branch(dc, target, insn, 1);
1051 else
1052 goto illegal_insn;
1053 goto jmp_insn;
1054 }
1055 case 0x3: /* V9 BPr */
1056 {
1057 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1058 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1059 target = sign_extend(target, 16);
1060 target <<= 2;
1061 rs1 = GET_FIELD(insn, 13, 17);
1062 gen_movl_reg_T0(rs1);
1063 do_branch_reg(dc, target, insn);
1064 goto jmp_insn;
1065 }
1066 case 0x5: /* V9 FBPcc */
1067 {
1068 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1069 if (gen_trap_ifnofpu(dc))
1070 goto jmp_insn;
0f8a249a
BS		 1071 target = GET_FIELD_SP(insn, 0, 18);
1072 target = sign_extend(target, 19);
1073 target <<= 2;
1074 do_fbranch(dc, target, insn, cc);
1075 goto jmp_insn;
1076 }
a4d17f19 1077#else
0f8a249a
BS		 1078 case 0x7: /* CBN+x */
1079 {
1080 goto ncp_insn;
1081 }
1082#endif
1083 case 0x2: /* BN+x */
1084 {
1085 target = GET_FIELD(insn, 10, 31);
1086 target = sign_extend(target, 22);
1087 target <<= 2;
1088 do_branch(dc, target, insn, 0);
1089 goto jmp_insn;
1090 }
1091 case 0x6: /* FBN+x */
1092 {
a80dde08
FB		 1093 if (gen_trap_ifnofpu(dc))
1094 goto jmp_insn;
0f8a249a
BS		 1095 target = GET_FIELD(insn, 10, 31);
1096 target = sign_extend(target, 22);
1097 target <<= 2;
1098 do_fbranch(dc, target, insn, 0);
1099 goto jmp_insn;
1100 }
1101 case 0x4: /* SETHI */
e80cfcfc
FB		 1102#define OPTIM
1103#if defined(OPTIM)
0f8a249a 1104 if (rd) { // nop
e80cfcfc 1105#endif
0f8a249a 1106 uint32_t value = GET_FIELD(insn, 10, 31);
1a2fb1c0 1107 tcg_gen_movi_tl(cpu_T[0], value << 10);
0f8a249a 1108 gen_movl_T0_reg(rd);
e80cfcfc 1109#if defined(OPTIM)
0f8a249a 1110 }
e80cfcfc 1111#endif
0f8a249a
BS		 1112 break;
1113 case 0x0: /* UNIMPL */
1114 default:
3475187d 1115 goto illegal_insn;
0f8a249a
BS		 1116 }
1117 break;
1118 }
1119 break;
cf495bcf 1120 case 1:
0f8a249a
BS		 1121 /*CALL*/ {
1122 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1123
1a2fb1c0 1124 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 1125 gen_movl_T0_reg(15);
1126 target += dc->pc;
0bee699e 1127 gen_mov_pc_npc(dc);
0f8a249a
BS		 1128 dc->npc = target;
1129 }
1130 goto jmp_insn;
1131 case 2: /* FPU & Logical Operations */
1132 {
1133 unsigned int xop = GET_FIELD(insn, 7, 12);
1134 if (xop == 0x3a) { /* generate trap */
cf495bcf 1135 int cond;
3475187d 1136
cf495bcf
FB		 1137 rs1 = GET_FIELD(insn, 13, 17);
1138 gen_movl_reg_T0(rs1);
0f8a249a
BS		 1139 if (IS_IMM) {
1140 rs2 = GET_FIELD(insn, 25, 31);
1a2fb1c0 1141 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
cf495bcf
FB		 1142 } else {
1143 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 1144#if defined(OPTIM)
0f8a249a 1145 if (rs2 != 0) {
e80cfcfc 1146#endif
0f8a249a
BS		 1147 gen_movl_reg_T1(rs2);
1148 gen_op_add_T1_T0();
e80cfcfc 1149#if defined(OPTIM)
0f8a249a 1150 }
e80cfcfc 1151#endif
cf495bcf 1152 }
cf495bcf
FB		 1153 cond = GET_FIELD(insn, 3, 6);
1154 if (cond == 0x8) {
a80dde08 1155 save_state(dc);
1a2fb1c0 1156 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
af7bf89b 1157 } else if (cond != 0) {
3475187d 1158#ifdef TARGET_SPARC64
0f8a249a
BS		 1159 /* V9 icc/xcc */
1160 int cc = GET_FIELD_SP(insn, 11, 12);
1161 flush_T2(dc);
a80dde08 1162 save_state(dc);
0f8a249a
BS		 1163 if (cc == 0)
1164 gen_cond[0][cond]();
1165 else if (cc == 2)
1166 gen_cond[1][cond]();
1167 else
1168 goto illegal_insn;
3475187d 1169#else
0f8a249a 1170 flush_T2(dc);
a80dde08 1171 save_state(dc);
0f8a249a 1172 gen_cond[0][cond]();
3475187d 1173#endif
1a2fb1c0 1174 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]);
cf495bcf 1175 }
a80dde08 1176 gen_op_next_insn();
57fec1fe 1177 tcg_gen_exit_tb(0);
a80dde08
FB		 1178 dc->is_br = 1;
1179 goto jmp_insn;
cf495bcf
FB		 1180 } else if (xop == 0x28) {
1181 rs1 = GET_FIELD(insn, 13, 17);
1182 switch(rs1) {
1183 case 0: /* rdy */
65fe7b09
BS		 1184#ifndef TARGET_SPARC64
1185 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1186 manual, rdy on the microSPARC
1187 II */
1188 case 0x0f: /* stbar in the SPARCv8 manual,
1189 rdy on the microSPARC II */
1190 case 0x10 ... 0x1f: /* implementation-dependent in the
1191 SPARCv8 manual, rdy on the
1192 microSPARC II */
1193#endif
1194 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1195 gen_movl_T0_reg(rd);
1196 break;
3475187d 1197#ifdef TARGET_SPARC64
0f8a249a 1198 case 0x2: /* V9 rdccr */
3475187d
FB		 1199 gen_op_rdccr();
1200 gen_movl_T0_reg(rd);
1201 break;
0f8a249a
BS		 1202 case 0x3: /* V9 rdasi */
1203 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
3475187d
FB		 1204 gen_movl_T0_reg(rd);
1205 break;
0f8a249a 1206 case 0x4: /* V9 rdtick */
3475187d
FB		 1207 gen_op_rdtick();
1208 gen_movl_T0_reg(rd);
1209 break;
0f8a249a 1210 case 0x5: /* V9 rdpc */
1a2fb1c0 1211 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 1212 gen_movl_T0_reg(rd);
1213 break;
1214 case 0x6: /* V9 rdfprs */
1215 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
3475187d
FB		 1216 gen_movl_T0_reg(rd);
1217 break;
65fe7b09
BS		 1218 case 0xf: /* V9 membar */
1219 break; /* no effect */
0f8a249a 1220 case 0x13: /* Graphics Status */
725cb90b
FB		 1221 if (gen_trap_ifnofpu(dc))
1222 goto jmp_insn;
0f8a249a 1223 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
725cb90b
FB		 1224 gen_movl_T0_reg(rd);
1225 break;
0f8a249a
BS		 1226 case 0x17: /* Tick compare */
1227 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
83469015
FB		 1228 gen_movl_T0_reg(rd);
1229 break;
0f8a249a 1230 case 0x18: /* System tick */
20c9f095 1231 gen_op_rdstick();
83469015
FB		 1232 gen_movl_T0_reg(rd);
1233 break;
0f8a249a
BS		 1234 case 0x19: /* System tick compare */
1235 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
83469015
FB		 1236 gen_movl_T0_reg(rd);
1237 break;
0f8a249a
BS		 1238 case 0x10: /* Performance Control */
1239 case 0x11: /* Performance Instrumentation Counter */
1240 case 0x12: /* Dispatch Control */
1241 case 0x14: /* Softint set, WO */
1242 case 0x15: /* Softint clear, WO */
1243 case 0x16: /* Softint write */
3475187d
FB		 1244#endif
1245 default:
cf495bcf
FB		 1246 goto illegal_insn;
1247 }
e8af50a3 1248#if !defined(CONFIG_USER_ONLY)
e9ebed4d 1249 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 1250#ifndef TARGET_SPARC64
0f8a249a
BS		 1251 if (!supervisor(dc))
1252 goto priv_insn;
1a2fb1c0 1253 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
e9ebed4d
BS		 1254#else
1255 if (!hypervisor(dc))
1256 goto priv_insn;
1257 rs1 = GET_FIELD(insn, 13, 17);
1258 switch (rs1) {
1259 case 0: // hpstate
1260 // gen_op_rdhpstate();
1261 break;
1262 case 1: // htstate
1263 // gen_op_rdhtstate();
1264 break;
1265 case 3: // hintp
1266 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1267 break;
1268 case 5: // htba
1269 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1270 break;
1271 case 6: // hver
1272 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1273 break;
1274 case 31: // hstick_cmpr
1275 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1276 break;
1277 default:
1278 goto illegal_insn;
1279 }
1280#endif
e8af50a3
FB		 1281 gen_movl_T0_reg(rd);
1282 break;
3475187d 1283 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 1284 if (!supervisor(dc))
1285 goto priv_insn;
3475187d
FB		 1286#ifdef TARGET_SPARC64
1287 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1288 switch (rs1) {
1289 case 0: // tpc
1290 gen_op_rdtpc();
1291 break;
1292 case 1: // tnpc
1293 gen_op_rdtnpc();
1294 break;
1295 case 2: // tstate
1296 gen_op_rdtstate();
1297 break;
1298 case 3: // tt
1299 gen_op_rdtt();
1300 break;
1301 case 4: // tick
1302 gen_op_rdtick();
1303 break;
1304 case 5: // tba
1305 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1306 break;
1307 case 6: // pstate
1a2fb1c0 1308 gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 1309 break;
1310 case 7: // tl
1311 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1312 break;
1313 case 8: // pil
1314 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1315 break;
1316 case 9: // cwp
1317 gen_op_rdcwp();
1318 break;
1319 case 10: // cansave
1320 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1321 break;
1322 case 11: // canrestore
1323 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1324 break;
1325 case 12: // cleanwin
1326 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1327 break;
1328 case 13: // otherwin
1329 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1330 break;
1331 case 14: // wstate
1332 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1333 break;
e9ebed4d
BS		 1334 case 16: // UA2005 gl
1335 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1336 break;
1337 case 26: // UA2005 strand status
1338 if (!hypervisor(dc))
1339 goto priv_insn;
1340 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1341 break;
0f8a249a
BS		 1342 case 31: // ver
1343 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1344 break;
1345 case 15: // fq
1346 default:
1347 goto illegal_insn;
1348 }
3475187d 1349#else
0f8a249a 1350 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
3475187d 1351#endif
e8af50a3
FB		 1352 gen_movl_T0_reg(rd);
1353 break;
3475187d
FB		 1354 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1355#ifdef TARGET_SPARC64
0f8a249a 1356 gen_op_flushw();
3475187d 1357#else
0f8a249a
BS		 1358 if (!supervisor(dc))
1359 goto priv_insn;
1360 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1361 gen_movl_T0_reg(rd);
3475187d 1362#endif
e8af50a3
FB		 1363 break;
1364#endif
0f8a249a 1365 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 1366 if (gen_trap_ifnofpu(dc))
1367 goto jmp_insn;
0f8a249a 1368 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 1369 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1370 rs2 = GET_FIELD(insn, 27, 31);
1371 xop = GET_FIELD(insn, 18, 26);
1372 switch (xop) {
1373 case 0x1: /* fmovs */
1374 gen_op_load_fpr_FT0(rs2);
1375 gen_op_store_FT0_fpr(rd);
1376 break;
1377 case 0x5: /* fnegs */
1378 gen_op_load_fpr_FT1(rs2);
1379 gen_op_fnegs();
1380 gen_op_store_FT0_fpr(rd);
1381 break;
1382 case 0x9: /* fabss */
1383 gen_op_load_fpr_FT1(rs2);
1384 gen_op_fabss();
1385 gen_op_store_FT0_fpr(rd);
1386 break;
1387 case 0x29: /* fsqrts */
1388 gen_op_load_fpr_FT1(rs2);
1389 gen_op_fsqrts();
1390 gen_op_store_FT0_fpr(rd);
1391 break;
1392 case 0x2a: /* fsqrtd */
1393 gen_op_load_fpr_DT1(DFPREG(rs2));
1394 gen_op_fsqrtd();
1395 gen_op_store_DT0_fpr(DFPREG(rd));
1396 break;
1397 case 0x2b: /* fsqrtq */
1f587329
BS		 1398#if defined(CONFIG_USER_ONLY)
1399 gen_op_load_fpr_QT1(QFPREG(rs2));
1400 gen_op_fsqrtq();
1401 gen_op_store_QT0_fpr(QFPREG(rd));
1402 break;
1403#else
0f8a249a 1404 goto nfpu_insn;
1f587329 1405#endif
0f8a249a
BS		 1406 case 0x41:
1407 gen_op_load_fpr_FT0(rs1);
1408 gen_op_load_fpr_FT1(rs2);
1409 gen_op_fadds();
1410 gen_op_store_FT0_fpr(rd);
1411 break;
1412 case 0x42:
1413 gen_op_load_fpr_DT0(DFPREG(rs1));
1414 gen_op_load_fpr_DT1(DFPREG(rs2));
1415 gen_op_faddd();
1416 gen_op_store_DT0_fpr(DFPREG(rd));
1417 break;
1418 case 0x43: /* faddq */
1f587329
BS		 1419#if defined(CONFIG_USER_ONLY)
1420 gen_op_load_fpr_QT0(QFPREG(rs1));
1421 gen_op_load_fpr_QT1(QFPREG(rs2));
1422 gen_op_faddq();
1423 gen_op_store_QT0_fpr(QFPREG(rd));
1424 break;
1425#else
0f8a249a 1426 goto nfpu_insn;
1f587329 1427#endif
0f8a249a
BS		 1428 case 0x45:
1429 gen_op_load_fpr_FT0(rs1);
1430 gen_op_load_fpr_FT1(rs2);
1431 gen_op_fsubs();
1432 gen_op_store_FT0_fpr(rd);
1433 break;
1434 case 0x46:
1435 gen_op_load_fpr_DT0(DFPREG(rs1));
1436 gen_op_load_fpr_DT1(DFPREG(rs2));
1437 gen_op_fsubd();
1438 gen_op_store_DT0_fpr(DFPREG(rd));
1439 break;
1440 case 0x47: /* fsubq */
1f587329
BS		 1441#if defined(CONFIG_USER_ONLY)
1442 gen_op_load_fpr_QT0(QFPREG(rs1));
1443 gen_op_load_fpr_QT1(QFPREG(rs2));
1444 gen_op_fsubq();
1445 gen_op_store_QT0_fpr(QFPREG(rd));
1446 break;
1447#else
0f8a249a 1448 goto nfpu_insn;
1f587329 1449#endif
0f8a249a
BS		 1450 case 0x49:
1451 gen_op_load_fpr_FT0(rs1);
1452 gen_op_load_fpr_FT1(rs2);
1453 gen_op_fmuls();
1454 gen_op_store_FT0_fpr(rd);
1455 break;
1456 case 0x4a:
1457 gen_op_load_fpr_DT0(DFPREG(rs1));
1458 gen_op_load_fpr_DT1(DFPREG(rs2));
1459 gen_op_fmuld();
2382dc6b 1460 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1461 break;
1462 case 0x4b: /* fmulq */
1f587329
BS		 1463#if defined(CONFIG_USER_ONLY)
1464 gen_op_load_fpr_QT0(QFPREG(rs1));
1465 gen_op_load_fpr_QT1(QFPREG(rs2));
1466 gen_op_fmulq();
1467 gen_op_store_QT0_fpr(QFPREG(rd));
1468 break;
1469#else
0f8a249a 1470 goto nfpu_insn;
1f587329 1471#endif
0f8a249a
BS		 1472 case 0x4d:
1473 gen_op_load_fpr_FT0(rs1);
1474 gen_op_load_fpr_FT1(rs2);
1475 gen_op_fdivs();
1476 gen_op_store_FT0_fpr(rd);
1477 break;
1478 case 0x4e:
1479 gen_op_load_fpr_DT0(DFPREG(rs1));
1480 gen_op_load_fpr_DT1(DFPREG(rs2));
1481 gen_op_fdivd();
1482 gen_op_store_DT0_fpr(DFPREG(rd));
1483 break;
1484 case 0x4f: /* fdivq */
1f587329
BS		 1485#if defined(CONFIG_USER_ONLY)
1486 gen_op_load_fpr_QT0(QFPREG(rs1));
1487 gen_op_load_fpr_QT1(QFPREG(rs2));
1488 gen_op_fdivq();
1489 gen_op_store_QT0_fpr(QFPREG(rd));
1490 break;
1491#else
0f8a249a 1492 goto nfpu_insn;
1f587329 1493#endif
0f8a249a
BS		 1494 case 0x69:
1495 gen_op_load_fpr_FT0(rs1);
1496 gen_op_load_fpr_FT1(rs2);
1497 gen_op_fsmuld();
1498 gen_op_store_DT0_fpr(DFPREG(rd));
1499 break;
1500 case 0x6e: /* fdmulq */
1f587329
BS		 1501#if defined(CONFIG_USER_ONLY)
1502 gen_op_load_fpr_DT0(DFPREG(rs1));
1503 gen_op_load_fpr_DT1(DFPREG(rs2));
1504 gen_op_fdmulq();
1505 gen_op_store_QT0_fpr(QFPREG(rd));
1506 break;
1507#else
0f8a249a 1508 goto nfpu_insn;
1f587329 1509#endif
0f8a249a
BS		 1510 case 0xc4:
1511 gen_op_load_fpr_FT1(rs2);
1512 gen_op_fitos();
1513 gen_op_store_FT0_fpr(rd);
1514 break;
1515 case 0xc6:
1516 gen_op_load_fpr_DT1(DFPREG(rs2));
1517 gen_op_fdtos();
1518 gen_op_store_FT0_fpr(rd);
1519 break;
1520 case 0xc7: /* fqtos */
1f587329
BS		 1521#if defined(CONFIG_USER_ONLY)
1522 gen_op_load_fpr_QT1(QFPREG(rs2));
1523 gen_op_fqtos();
1524 gen_op_store_FT0_fpr(rd);
1525 break;
1526#else
0f8a249a 1527 goto nfpu_insn;
1f587329 1528#endif
0f8a249a
BS		 1529 case 0xc8:
1530 gen_op_load_fpr_FT1(rs2);
1531 gen_op_fitod();
1532 gen_op_store_DT0_fpr(DFPREG(rd));
1533 break;
1534 case 0xc9:
1535 gen_op_load_fpr_FT1(rs2);
1536 gen_op_fstod();
1537 gen_op_store_DT0_fpr(DFPREG(rd));
1538 break;
1539 case 0xcb: /* fqtod */
1f587329
BS		 1540#if defined(CONFIG_USER_ONLY)
1541 gen_op_load_fpr_QT1(QFPREG(rs2));
1542 gen_op_fqtod();
1543 gen_op_store_DT0_fpr(DFPREG(rd));
1544 break;
1545#else
0f8a249a 1546 goto nfpu_insn;
1f587329 1547#endif
0f8a249a 1548 case 0xcc: /* fitoq */
1f587329
BS		 1549#if defined(CONFIG_USER_ONLY)
1550 gen_op_load_fpr_FT1(rs2);
1551 gen_op_fitoq();
1552 gen_op_store_QT0_fpr(QFPREG(rd));
1553 break;
1554#else
0f8a249a 1555 goto nfpu_insn;
1f587329 1556#endif
0f8a249a 1557 case 0xcd: /* fstoq */
1f587329
BS		 1558#if defined(CONFIG_USER_ONLY)
1559 gen_op_load_fpr_FT1(rs2);
1560 gen_op_fstoq();
1561 gen_op_store_QT0_fpr(QFPREG(rd));
1562 break;
1563#else
0f8a249a 1564 goto nfpu_insn;
1f587329 1565#endif
0f8a249a 1566 case 0xce: /* fdtoq */
1f587329
BS		 1567#if defined(CONFIG_USER_ONLY)
1568 gen_op_load_fpr_DT1(DFPREG(rs2));
1569 gen_op_fdtoq();
1570 gen_op_store_QT0_fpr(QFPREG(rd));
1571 break;
1572#else
0f8a249a 1573 goto nfpu_insn;
1f587329 1574#endif
0f8a249a
BS		 1575 case 0xd1:
1576 gen_op_load_fpr_FT1(rs2);
1577 gen_op_fstoi();
1578 gen_op_store_FT0_fpr(rd);
1579 break;
1580 case 0xd2:
2382dc6b 1581 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1582 gen_op_fdtoi();
1583 gen_op_store_FT0_fpr(rd);
1584 break;
1585 case 0xd3: /* fqtoi */
1f587329
BS		 1586#if defined(CONFIG_USER_ONLY)
1587 gen_op_load_fpr_QT1(QFPREG(rs2));
1588 gen_op_fqtoi();
1589 gen_op_store_FT0_fpr(rd);
1590 break;
1591#else
0f8a249a 1592 goto nfpu_insn;
1f587329 1593#endif
3475187d 1594#ifdef TARGET_SPARC64
0f8a249a
BS		 1595 case 0x2: /* V9 fmovd */
1596 gen_op_load_fpr_DT0(DFPREG(rs2));
1597 gen_op_store_DT0_fpr(DFPREG(rd));
1598 break;
1f587329
BS		 1599 case 0x3: /* V9 fmovq */
1600#if defined(CONFIG_USER_ONLY)
1601 gen_op_load_fpr_QT0(QFPREG(rs2));
1602 gen_op_store_QT0_fpr(QFPREG(rd));
1603 break;
1604#else
1605 goto nfpu_insn;
1606#endif
0f8a249a
BS		 1607 case 0x6: /* V9 fnegd */
1608 gen_op_load_fpr_DT1(DFPREG(rs2));
1609 gen_op_fnegd();
1610 gen_op_store_DT0_fpr(DFPREG(rd));
1611 break;
1f587329
BS		 1612 case 0x7: /* V9 fnegq */
1613#if defined(CONFIG_USER_ONLY)
1614 gen_op_load_fpr_QT1(QFPREG(rs2));
1615 gen_op_fnegq();
1616 gen_op_store_QT0_fpr(QFPREG(rd));
1617 break;
1618#else
1619 goto nfpu_insn;
1620#endif
0f8a249a
BS		 1621 case 0xa: /* V9 fabsd */
1622 gen_op_load_fpr_DT1(DFPREG(rs2));
1623 gen_op_fabsd();
1624 gen_op_store_DT0_fpr(DFPREG(rd));
1625 break;
1f587329
BS		 1626 case 0xb: /* V9 fabsq */
1627#if defined(CONFIG_USER_ONLY)
1628 gen_op_load_fpr_QT1(QFPREG(rs2));
1629 gen_op_fabsq();
1630 gen_op_store_QT0_fpr(QFPREG(rd));
1631 break;
1632#else
1633 goto nfpu_insn;
1634#endif
0f8a249a
BS		 1635 case 0x81: /* V9 fstox */
1636 gen_op_load_fpr_FT1(rs2);
1637 gen_op_fstox();
1638 gen_op_store_DT0_fpr(DFPREG(rd));
1639 break;
1640 case 0x82: /* V9 fdtox */
1641 gen_op_load_fpr_DT1(DFPREG(rs2));
1642 gen_op_fdtox();
1643 gen_op_store_DT0_fpr(DFPREG(rd));
1644 break;
1f587329
BS		 1645 case 0x83: /* V9 fqtox */
1646#if defined(CONFIG_USER_ONLY)
1647 gen_op_load_fpr_QT1(QFPREG(rs2));
1648 gen_op_fqtox();
1649 gen_op_store_DT0_fpr(DFPREG(rd));
1650 break;
1651#else
1652 goto nfpu_insn;
1653#endif
0f8a249a
BS		 1654 case 0x84: /* V9 fxtos */
1655 gen_op_load_fpr_DT1(DFPREG(rs2));
1656 gen_op_fxtos();
1657 gen_op_store_FT0_fpr(rd);
1658 break;
1659 case 0x88: /* V9 fxtod */
1660 gen_op_load_fpr_DT1(DFPREG(rs2));
1661 gen_op_fxtod();
1662 gen_op_store_DT0_fpr(DFPREG(rd));
1663 break;
0f8a249a 1664 case 0x8c: /* V9 fxtoq */
1f587329
BS		 1665#if defined(CONFIG_USER_ONLY)
1666 gen_op_load_fpr_DT1(DFPREG(rs2));
1667 gen_op_fxtoq();
1668 gen_op_store_QT0_fpr(QFPREG(rd));
1669 break;
1670#else
0f8a249a 1671 goto nfpu_insn;
1f587329 1672#endif
0f8a249a
BS		 1673#endif
1674 default:
1675 goto illegal_insn;
1676 }
1677 } else if (xop == 0x35) { /* FPU Operations */
3475187d 1678#ifdef TARGET_SPARC64
0f8a249a 1679 int cond;
3475187d 1680#endif
a80dde08
FB		 1681 if (gen_trap_ifnofpu(dc))
1682 goto jmp_insn;
0f8a249a 1683 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 1684 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1685 rs2 = GET_FIELD(insn, 27, 31);
1686 xop = GET_FIELD(insn, 18, 26);
3475187d 1687#ifdef TARGET_SPARC64
0f8a249a
BS		 1688 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1689 cond = GET_FIELD_SP(insn, 14, 17);
1690 gen_op_load_fpr_FT0(rd);
1691 gen_op_load_fpr_FT1(rs2);
1692 rs1 = GET_FIELD(insn, 13, 17);
1693 gen_movl_reg_T0(rs1);
1694 flush_T2(dc);
1695 gen_cond_reg(cond);
1696 gen_op_fmovs_cc();
1697 gen_op_store_FT0_fpr(rd);
1698 break;
1699 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1700 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1701 gen_op_load_fpr_DT0(DFPREG(rd));
1702 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1703 flush_T2(dc);
1704 rs1 = GET_FIELD(insn, 13, 17);
1705 gen_movl_reg_T0(rs1);
1706 gen_cond_reg(cond);
1707 gen_op_fmovs_cc();
2382dc6b 1708 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1709 break;
1710 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1f587329
BS		 1711#if defined(CONFIG_USER_ONLY)
1712 cond = GET_FIELD_SP(insn, 14, 17);
1713 gen_op_load_fpr_QT0(QFPREG(rd));
1714 gen_op_load_fpr_QT1(QFPREG(rs2));
1715 flush_T2(dc);
1716 rs1 = GET_FIELD(insn, 13, 17);
1717 gen_movl_reg_T0(rs1);
1718 gen_cond_reg(cond);
1719 gen_op_fmovq_cc();
1720 gen_op_store_QT0_fpr(QFPREG(rd));
1721 break;
1722#else
0f8a249a 1723 goto nfpu_insn;
1f587329 1724#endif
0f8a249a
BS		 1725 }
1726#endif
1727 switch (xop) {
3475187d 1728#ifdef TARGET_SPARC64
0f8a249a
BS		 1729 case 0x001: /* V9 fmovscc %fcc0 */
1730 cond = GET_FIELD_SP(insn, 14, 17);
1731 gen_op_load_fpr_FT0(rd);
1732 gen_op_load_fpr_FT1(rs2);
1733 flush_T2(dc);
1734 gen_fcond[0][cond]();
1735 gen_op_fmovs_cc();
1736 gen_op_store_FT0_fpr(rd);
1737 break;
1738 case 0x002: /* V9 fmovdcc %fcc0 */
1739 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1740 gen_op_load_fpr_DT0(DFPREG(rd));
1741 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1742 flush_T2(dc);
1743 gen_fcond[0][cond]();
1744 gen_op_fmovd_cc();
2382dc6b 1745 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1746 break;
1747 case 0x003: /* V9 fmovqcc %fcc0 */
1f587329
BS		 1748#if defined(CONFIG_USER_ONLY)
1749 cond = GET_FIELD_SP(insn, 14, 17);
1750 gen_op_load_fpr_QT0(QFPREG(rd));
1751 gen_op_load_fpr_QT1(QFPREG(rs2));
1752 flush_T2(dc);
1753 gen_fcond[0][cond]();
1754 gen_op_fmovq_cc();
1755 gen_op_store_QT0_fpr(QFPREG(rd));
1756 break;
1757#else
0f8a249a 1758 goto nfpu_insn;
1f587329 1759#endif
0f8a249a
BS		 1760 case 0x041: /* V9 fmovscc %fcc1 */
1761 cond = GET_FIELD_SP(insn, 14, 17);
1762 gen_op_load_fpr_FT0(rd);
1763 gen_op_load_fpr_FT1(rs2);
1764 flush_T2(dc);
1765 gen_fcond[1][cond]();
1766 gen_op_fmovs_cc();
1767 gen_op_store_FT0_fpr(rd);
1768 break;
1769 case 0x042: /* V9 fmovdcc %fcc1 */
1770 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1771 gen_op_load_fpr_DT0(DFPREG(rd));
1772 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1773 flush_T2(dc);
1774 gen_fcond[1][cond]();
1775 gen_op_fmovd_cc();
2382dc6b 1776 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1777 break;
1778 case 0x043: /* V9 fmovqcc %fcc1 */
1f587329
BS		 1779#if defined(CONFIG_USER_ONLY)
1780 cond = GET_FIELD_SP(insn, 14, 17);
1781 gen_op_load_fpr_QT0(QFPREG(rd));
1782 gen_op_load_fpr_QT1(QFPREG(rs2));
1783 flush_T2(dc);
1784 gen_fcond[1][cond]();
1785 gen_op_fmovq_cc();
1786 gen_op_store_QT0_fpr(QFPREG(rd));
1787 break;
1788#else
0f8a249a 1789 goto nfpu_insn;
1f587329 1790#endif
0f8a249a
BS		 1791 case 0x081: /* V9 fmovscc %fcc2 */
1792 cond = GET_FIELD_SP(insn, 14, 17);
1793 gen_op_load_fpr_FT0(rd);
1794 gen_op_load_fpr_FT1(rs2);
1795 flush_T2(dc);
1796 gen_fcond[2][cond]();
1797 gen_op_fmovs_cc();
1798 gen_op_store_FT0_fpr(rd);
1799 break;
1800 case 0x082: /* V9 fmovdcc %fcc2 */
1801 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1802 gen_op_load_fpr_DT0(DFPREG(rd));
1803 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1804 flush_T2(dc);
1805 gen_fcond[2][cond]();
1806 gen_op_fmovd_cc();
2382dc6b 1807 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1808 break;
1809 case 0x083: /* V9 fmovqcc %fcc2 */
1f587329
BS		 1810#if defined(CONFIG_USER_ONLY)
1811 cond = GET_FIELD_SP(insn, 14, 17);
1812 gen_op_load_fpr_QT0(rd);
1813 gen_op_load_fpr_QT1(rs2);
1814 flush_T2(dc);
1815 gen_fcond[2][cond]();
1816 gen_op_fmovq_cc();
1817 gen_op_store_QT0_fpr(rd);
1818 break;
1819#else
0f8a249a 1820 goto nfpu_insn;
1f587329 1821#endif
0f8a249a
BS		 1822 case 0x0c1: /* V9 fmovscc %fcc3 */
1823 cond = GET_FIELD_SP(insn, 14, 17);
1824 gen_op_load_fpr_FT0(rd);
1825 gen_op_load_fpr_FT1(rs2);
1826 flush_T2(dc);
1827 gen_fcond[3][cond]();
1828 gen_op_fmovs_cc();
1829 gen_op_store_FT0_fpr(rd);
1830 break;
1831 case 0x0c2: /* V9 fmovdcc %fcc3 */
1832 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1833 gen_op_load_fpr_DT0(DFPREG(rd));
1834 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1835 flush_T2(dc);
1836 gen_fcond[3][cond]();
1837 gen_op_fmovd_cc();
2382dc6b 1838 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1839 break;
1840 case 0x0c3: /* V9 fmovqcc %fcc3 */
1f587329
BS		 1841#if defined(CONFIG_USER_ONLY)
1842 cond = GET_FIELD_SP(insn, 14, 17);
1843 gen_op_load_fpr_QT0(QFPREG(rd));
1844 gen_op_load_fpr_QT1(QFPREG(rs2));
1845 flush_T2(dc);
1846 gen_fcond[3][cond]();
1847 gen_op_fmovq_cc();
1848 gen_op_store_QT0_fpr(QFPREG(rd));
1849 break;
1850#else
0f8a249a 1851 goto nfpu_insn;
1f587329 1852#endif
0f8a249a
BS		 1853 case 0x101: /* V9 fmovscc %icc */
1854 cond = GET_FIELD_SP(insn, 14, 17);
1855 gen_op_load_fpr_FT0(rd);
1856 gen_op_load_fpr_FT1(rs2);
1857 flush_T2(dc);
1858 gen_cond[0][cond]();
1859 gen_op_fmovs_cc();
1860 gen_op_store_FT0_fpr(rd);
1861 break;
1862 case 0x102: /* V9 fmovdcc %icc */
1863 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1864 gen_op_load_fpr_DT0(DFPREG(rd));
1865 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1866 flush_T2(dc);
1867 gen_cond[0][cond]();
1868 gen_op_fmovd_cc();
2382dc6b 1869 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1870 break;
1871 case 0x103: /* V9 fmovqcc %icc */
1f587329
BS		 1872#if defined(CONFIG_USER_ONLY)
1873 cond = GET_FIELD_SP(insn, 14, 17);
1874 gen_op_load_fpr_QT0(rd);
1875 gen_op_load_fpr_QT1(rs2);
1876 flush_T2(dc);
1877 gen_cond[0][cond]();
1878 gen_op_fmovq_cc();
1879 gen_op_store_QT0_fpr(rd);
1880 break;
1881#else
0f8a249a 1882 goto nfpu_insn;
1f587329 1883#endif
0f8a249a
BS		 1884 case 0x181: /* V9 fmovscc %xcc */
1885 cond = GET_FIELD_SP(insn, 14, 17);
1886 gen_op_load_fpr_FT0(rd);
1887 gen_op_load_fpr_FT1(rs2);
1888 flush_T2(dc);
1889 gen_cond[1][cond]();
1890 gen_op_fmovs_cc();
1891 gen_op_store_FT0_fpr(rd);
1892 break;
1893 case 0x182: /* V9 fmovdcc %xcc */
1894 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1895 gen_op_load_fpr_DT0(DFPREG(rd));
1896 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1897 flush_T2(dc);
1898 gen_cond[1][cond]();
1899 gen_op_fmovd_cc();
2382dc6b 1900 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1901 break;
1902 case 0x183: /* V9 fmovqcc %xcc */
1f587329
BS		 1903#if defined(CONFIG_USER_ONLY)
1904 cond = GET_FIELD_SP(insn, 14, 17);
1905 gen_op_load_fpr_QT0(rd);
1906 gen_op_load_fpr_QT1(rs2);
1907 flush_T2(dc);
1908 gen_cond[1][cond]();
1909 gen_op_fmovq_cc();
1910 gen_op_store_QT0_fpr(rd);
1911 break;
1912#else
0f8a249a
BS		 1913 goto nfpu_insn;
1914#endif
1f587329
BS		 1915#endif
1916 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 1917 gen_op_load_fpr_FT0(rs1);
1918 gen_op_load_fpr_FT1(rs2);
3475187d 1919#ifdef TARGET_SPARC64
0f8a249a 1920 gen_fcmps[rd & 3]();
3475187d 1921#else
0f8a249a 1922 gen_op_fcmps();
3475187d 1923#endif
0f8a249a 1924 break;
1f587329 1925 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 1926 gen_op_load_fpr_DT0(DFPREG(rs1));
1927 gen_op_load_fpr_DT1(DFPREG(rs2));
3475187d 1928#ifdef TARGET_SPARC64
0f8a249a 1929 gen_fcmpd[rd & 3]();
3475187d 1930#else
0f8a249a
BS		 1931 gen_op_fcmpd();
1932#endif
1933 break;
1f587329
BS		 1934 case 0x53: /* fcmpq, V9 %fcc */
1935#if defined(CONFIG_USER_ONLY)
1936 gen_op_load_fpr_QT0(QFPREG(rs1));
1937 gen_op_load_fpr_QT1(QFPREG(rs2));
1938#ifdef TARGET_SPARC64
1939 gen_fcmpq[rd & 3]();
1940#else
1941 gen_op_fcmpq();
1942#endif
1943 break;
1944#else /* !defined(CONFIG_USER_ONLY) */
0f8a249a 1945 goto nfpu_insn;
1f587329 1946#endif
0f8a249a
BS		 1947 case 0x55: /* fcmpes, V9 %fcc */
1948 gen_op_load_fpr_FT0(rs1);
1949 gen_op_load_fpr_FT1(rs2);
3475187d 1950#ifdef TARGET_SPARC64
0f8a249a 1951 gen_fcmpes[rd & 3]();
3475187d 1952#else
0f8a249a 1953 gen_op_fcmpes();
3475187d 1954#endif
0f8a249a
BS		 1955 break;
1956 case 0x56: /* fcmped, V9 %fcc */
1957 gen_op_load_fpr_DT0(DFPREG(rs1));
1958 gen_op_load_fpr_DT1(DFPREG(rs2));
3475187d 1959#ifdef TARGET_SPARC64
0f8a249a 1960 gen_fcmped[rd & 3]();
3475187d 1961#else
0f8a249a
BS		 1962 gen_op_fcmped();
1963#endif
1964 break;
1f587329
BS		 1965 case 0x57: /* fcmpeq, V9 %fcc */
1966#if defined(CONFIG_USER_ONLY)
1967 gen_op_load_fpr_QT0(QFPREG(rs1));
1968 gen_op_load_fpr_QT1(QFPREG(rs2));
1969#ifdef TARGET_SPARC64
1970 gen_fcmpeq[rd & 3]();
1971#else
1972 gen_op_fcmpeq();
1973#endif
1974 break;
1975#else/* !defined(CONFIG_USER_ONLY) */
0f8a249a 1976 goto nfpu_insn;
1f587329 1977#endif
0f8a249a
BS		 1978 default:
1979 goto illegal_insn;
1980 }
e80cfcfc 1981#if defined(OPTIM)
0f8a249a
BS		 1982 } else if (xop == 0x2) {
1983 // clr/mov shortcut
e80cfcfc
FB		 1984
1985 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 1986 if (rs1 == 0) {
1a2fb1c0 1987 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a
BS		 1988 if (IS_IMM) { /* immediate */
1989 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 1990 tcg_gen_movi_tl(cpu_T[0], (int)rs2);
0f8a249a
BS		 1991 } else { /* register */
1992 rs2 = GET_FIELD(insn, 27, 31);
1a2fb1c0 1993 gen_movl_reg_T0(rs2);
0f8a249a 1994 }
0f8a249a
BS		 1995 } else {
1996 gen_movl_reg_T0(rs1);
1997 if (IS_IMM) { /* immediate */
0f8a249a 1998 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 1999 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 2000 } else { /* register */
2001 // or x, %g0, y -> mov T1, x; mov y, T1
2002 rs2 = GET_FIELD(insn, 27, 31);
2003 if (rs2 != 0) {
2004 gen_movl_reg_T1(rs2);
2005 gen_op_or_T1_T0();
2006 }
2007 }
0f8a249a 2008 }
1a2fb1c0 2009 gen_movl_T0_reg(rd);
83469015
FB		 2010#endif
2011#ifdef TARGET_SPARC64
0f8a249a 2012 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015 2013 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2014 gen_movl_reg_T0(rs1);
2015 if (IS_IMM) { /* immediate */
83469015 2016 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2017 if (insn & (1 << 12)) {
2018 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2019 } else {
2020 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2021 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2022 }
0f8a249a 2023 } else { /* register */
83469015
FB		 2024 rs2 = GET_FIELD(insn, 27, 31);
2025 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2026 if (insn & (1 << 12)) {
2027 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2028 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2029 } else {
2030 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2031 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2032 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2033 }
83469015 2034 }
0f8a249a
BS		 2035 gen_movl_T0_reg(rd);
2036 } else if (xop == 0x26) { /* srl, V9 srlx */
83469015 2037 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2038 gen_movl_reg_T0(rs1);
2039 if (IS_IMM) { /* immediate */
83469015 2040 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2041 if (insn & (1 << 12)) {
2042 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2043 } else {
2044 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2045 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2046 }
0f8a249a 2047 } else { /* register */
83469015
FB		 2048 rs2 = GET_FIELD(insn, 27, 31);
2049 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2050 if (insn & (1 << 12)) {
2051 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2052 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2053 } else {
2054 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2055 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2056 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2057 }
83469015 2058 }
0f8a249a
BS		 2059 gen_movl_T0_reg(rd);
2060 } else if (xop == 0x27) { /* sra, V9 srax */
83469015 2061 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2062 gen_movl_reg_T0(rs1);
2063 if (IS_IMM) { /* immediate */
83469015 2064 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2065 if (insn & (1 << 12)) {
2066 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2067 } else {
2068 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2069 tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2070 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2071 }
0f8a249a 2072 } else { /* register */
83469015
FB		 2073 rs2 = GET_FIELD(insn, 27, 31);
2074 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2075 if (insn & (1 << 12)) {
2076 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2077 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2078 } else {
2079 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2080 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2081 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2082 }
83469015 2083 }
0f8a249a 2084 gen_movl_T0_reg(rd);
e80cfcfc 2085#endif
fcc72045 2086 } else if (xop < 0x36) {
e80cfcfc 2087 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2088 gen_movl_reg_T0(rs1);
2089 if (IS_IMM) { /* immediate */
cf495bcf 2090 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 2091 gen_movl_simm_T1(rs2);
0f8a249a 2092 } else { /* register */
cf495bcf
FB		 2093 rs2 = GET_FIELD(insn, 27, 31);
2094 gen_movl_reg_T1(rs2);
2095 }
2096 if (xop < 0x20) {
2097 switch (xop & ~0x10) {
2098 case 0x0:
2099 if (xop & 0x10)
2100 gen_op_add_T1_T0_cc();
2101 else
2102 gen_op_add_T1_T0();
2103 break;
2104 case 0x1:
1a2fb1c0 2105 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2106 if (xop & 0x10)
2107 gen_op_logic_T0_cc();
2108 break;
2109 case 0x2:
1a2fb1c0 2110 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
0f8a249a
BS		 2111 if (xop & 0x10)
2112 gen_op_logic_T0_cc();
2113 break;
cf495bcf 2114 case 0x3:
1a2fb1c0 2115 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2116 if (xop & 0x10)
2117 gen_op_logic_T0_cc();
2118 break;
2119 case 0x4:
2120 if (xop & 0x10)
2121 gen_op_sub_T1_T0_cc();
2122 else
1a2fb1c0 2123 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2124 break;
2125 case 0x5:
2126 gen_op_andn_T1_T0();
2127 if (xop & 0x10)
2128 gen_op_logic_T0_cc();
2129 break;
2130 case 0x6:
2131 gen_op_orn_T1_T0();
2132 if (xop & 0x10)
2133 gen_op_logic_T0_cc();
2134 break;
2135 case 0x7:
2136 gen_op_xnor_T1_T0();
2137 if (xop & 0x10)
2138 gen_op_logic_T0_cc();
2139 break;
2140 case 0x8:
cf495bcf 2141 if (xop & 0x10)
af7bf89b 2142 gen_op_addx_T1_T0_cc();
38bc628b
BS		 2143 else {
2144 gen_mov_reg_C(cpu_tmp0);
2145 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2146 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2147 }
cf495bcf 2148 break;
ded3ab80 2149#ifdef TARGET_SPARC64
0f8a249a 2150 case 0x9: /* V9 mulx */
1a2fb1c0 2151 tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
ded3ab80
PB		 2152 break;
2153#endif
cf495bcf
FB		 2154 case 0xa:
2155 gen_op_umul_T1_T0();
2156 if (xop & 0x10)
2157 gen_op_logic_T0_cc();
2158 break;
2159 case 0xb:
2160 gen_op_smul_T1_T0();
2161 if (xop & 0x10)
2162 gen_op_logic_T0_cc();
2163 break;
2164 case 0xc:
cf495bcf 2165 if (xop & 0x10)
af7bf89b 2166 gen_op_subx_T1_T0_cc();
38bc628b
BS		 2167 else {
2168 gen_mov_reg_C(cpu_tmp0);
2169 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2170 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2171 }
cf495bcf 2172 break;
ded3ab80 2173#ifdef TARGET_SPARC64
0f8a249a 2174 case 0xd: /* V9 udivx */
ded3ab80
PB		 2175 gen_op_udivx_T1_T0();
2176 break;
2177#endif
cf495bcf
FB		 2178 case 0xe:
2179 gen_op_udiv_T1_T0();
2180 if (xop & 0x10)
2181 gen_op_div_cc();
2182 break;
2183 case 0xf:
2184 gen_op_sdiv_T1_T0();
2185 if (xop & 0x10)
2186 gen_op_div_cc();
2187 break;
2188 default:
2189 goto illegal_insn;
2190 }
0f8a249a 2191 gen_movl_T0_reg(rd);
cf495bcf
FB		 2192 } else {
2193 switch (xop) {
0f8a249a
BS		 2194 case 0x20: /* taddcc */
2195 gen_op_tadd_T1_T0_cc();
2196 gen_movl_T0_reg(rd);
2197 break;
2198 case 0x21: /* tsubcc */
2199 gen_op_tsub_T1_T0_cc();
2200 gen_movl_T0_reg(rd);
2201 break;
2202 case 0x22: /* taddcctv */
90251fb9 2203 save_state(dc);
0f8a249a
BS		 2204 gen_op_tadd_T1_T0_ccTV();
2205 gen_movl_T0_reg(rd);
2206 break;
2207 case 0x23: /* tsubcctv */
90251fb9 2208 save_state(dc);
0f8a249a
BS		 2209 gen_op_tsub_T1_T0_ccTV();
2210 gen_movl_T0_reg(rd);
2211 break;
cf495bcf
FB		 2212 case 0x24: /* mulscc */
2213 gen_op_mulscc_T1_T0();
2214 gen_movl_T0_reg(rd);
2215 break;
83469015 2216#ifndef TARGET_SPARC64
0f8a249a 2217 case 0x25: /* sll */
1a2fb1c0
BS		 2218 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
2219 tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2220 gen_movl_T0_reg(rd);
2221 break;
83469015 2222 case 0x26: /* srl */
1a2fb1c0
BS		 2223 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
2224 tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2225 gen_movl_T0_reg(rd);
2226 break;
83469015 2227 case 0x27: /* sra */
1a2fb1c0
BS		 2228 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
2229 tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2230 gen_movl_T0_reg(rd);
2231 break;
83469015 2232#endif
cf495bcf
FB		 2233 case 0x30:
2234 {
cf495bcf 2235 switch(rd) {
3475187d 2236 case 0: /* wry */
0f8a249a
BS		 2237 gen_op_xor_T1_T0();
2238 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 2239 break;
65fe7b09
BS		 2240#ifndef TARGET_SPARC64
2241 case 0x01 ... 0x0f: /* undefined in the
2242 SPARCv8 manual, nop
2243 on the microSPARC
2244 II */
2245 case 0x10 ... 0x1f: /* implementation-dependent
2246 in the SPARCv8
2247 manual, nop on the
2248 microSPARC II */
2249 break;
2250#else
0f8a249a 2251 case 0x2: /* V9 wrccr */
ee0b03fd 2252 gen_op_xor_T1_T0();
3475187d 2253 gen_op_wrccr();
0f8a249a
BS		 2254 break;
2255 case 0x3: /* V9 wrasi */
ee0b03fd 2256 gen_op_xor_T1_T0();
0f8a249a
BS		 2257 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2258 break;
2259 case 0x6: /* V9 wrfprs */
2260 gen_op_xor_T1_T0();
2261 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 2262 save_state(dc);
2263 gen_op_next_insn();
57fec1fe 2264 tcg_gen_exit_tb(0);
3299908c 2265 dc->is_br = 1;
0f8a249a
BS		 2266 break;
2267 case 0xf: /* V9 sir, nop if user */
3475187d 2268#if !defined(CONFIG_USER_ONLY)
0f8a249a 2269 if (supervisor(dc))
1a2fb1c0 2270 ; // XXX
3475187d 2271#endif
0f8a249a
BS		 2272 break;
2273 case 0x13: /* Graphics Status */
725cb90b
FB		 2274 if (gen_trap_ifnofpu(dc))
2275 goto jmp_insn;
ee0b03fd 2276 gen_op_xor_T1_T0();
0f8a249a
BS		 2277 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2278 break;
2279 case 0x17: /* Tick compare */
83469015 2280#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2281 if (!supervisor(dc))
2282 goto illegal_insn;
83469015 2283#endif
ee0b03fd 2284 gen_op_xor_T1_T0();
20c9f095
BS		 2285 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2286 gen_op_wrtick_cmpr();
0f8a249a
BS		 2287 break;
2288 case 0x18: /* System tick */
83469015 2289#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2290 if (!supervisor(dc))
2291 goto illegal_insn;
83469015 2292#endif
ee0b03fd 2293 gen_op_xor_T1_T0();
20c9f095 2294 gen_op_wrstick();
0f8a249a
BS		 2295 break;
2296 case 0x19: /* System tick compare */
83469015 2297#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2298 if (!supervisor(dc))
2299 goto illegal_insn;
3475187d 2300#endif
ee0b03fd 2301 gen_op_xor_T1_T0();
20c9f095
BS		 2302 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2303 gen_op_wrstick_cmpr();
0f8a249a 2304 break;
83469015 2305
0f8a249a
BS		 2306 case 0x10: /* Performance Control */
2307 case 0x11: /* Performance Instrumentation Counter */
2308 case 0x12: /* Dispatch Control */
2309 case 0x14: /* Softint set */
2310 case 0x15: /* Softint clear */
2311 case 0x16: /* Softint write */
83469015 2312#endif
3475187d 2313 default:
cf495bcf
FB		 2314 goto illegal_insn;
2315 }
2316 }
2317 break;
e8af50a3 2318#if !defined(CONFIG_USER_ONLY)
af7bf89b 2319 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 2320 {
0f8a249a
BS		 2321 if (!supervisor(dc))
2322 goto priv_insn;
3475187d 2323#ifdef TARGET_SPARC64
0f8a249a
BS		 2324 switch (rd) {
2325 case 0:
2326 gen_op_saved();
2327 break;
2328 case 1:
2329 gen_op_restored();
2330 break;
e9ebed4d
BS		 2331 case 2: /* UA2005 allclean */
2332 case 3: /* UA2005 otherw */
2333 case 4: /* UA2005 normalw */
2334 case 5: /* UA2005 invalw */
2335 // XXX
0f8a249a 2336 default:
3475187d
FB		 2337 goto illegal_insn;
2338 }
2339#else
e8af50a3 2340 gen_op_xor_T1_T0();
1a2fb1c0 2341 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
9e61bde5
FB		 2342 save_state(dc);
2343 gen_op_next_insn();
57fec1fe 2344 tcg_gen_exit_tb(0);
0f8a249a 2345 dc->is_br = 1;
3475187d 2346#endif
e8af50a3
FB		 2347 }
2348 break;
af7bf89b 2349 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 2350 {
0f8a249a
BS		 2351 if (!supervisor(dc))
2352 goto priv_insn;
e8af50a3 2353 gen_op_xor_T1_T0();
3475187d 2354#ifdef TARGET_SPARC64
0f8a249a
BS		 2355 switch (rd) {
2356 case 0: // tpc
2357 gen_op_wrtpc();
2358 break;
2359 case 1: // tnpc
2360 gen_op_wrtnpc();
2361 break;
2362 case 2: // tstate
2363 gen_op_wrtstate();
2364 break;
2365 case 3: // tt
2366 gen_op_wrtt();
2367 break;
2368 case 4: // tick
2369 gen_op_wrtick();
2370 break;
2371 case 5: // tba
2372 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2373 break;
2374 case 6: // pstate
ded3ab80 2375 save_state(dc);
1a2fb1c0 2376 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
ded3ab80 2377 gen_op_next_insn();
57fec1fe 2378 tcg_gen_exit_tb(0);
ded3ab80 2379 dc->is_br = 1;
0f8a249a
BS		 2380 break;
2381 case 7: // tl
2382 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2383 break;
2384 case 8: // pil
2385 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2386 break;
2387 case 9: // cwp
2388 gen_op_wrcwp();
2389 break;
2390 case 10: // cansave
2391 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2392 break;
2393 case 11: // canrestore
2394 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2395 break;
2396 case 12: // cleanwin
2397 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2398 break;
2399 case 13: // otherwin
2400 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2401 break;
2402 case 14: // wstate
2403 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2404 break;
e9ebed4d
BS		 2405 case 16: // UA2005 gl
2406 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2407 break;
2408 case 26: // UA2005 strand status
2409 if (!hypervisor(dc))
2410 goto priv_insn;
2411 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2412 break;
0f8a249a
BS		 2413 default:
2414 goto illegal_insn;
2415 }
3475187d 2416#else
1a2fb1c0
BS		 2417 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
2418 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3475187d 2419#endif
e8af50a3
FB		 2420 }
2421 break;
e9ebed4d 2422 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 2423 {
e9ebed4d 2424#ifndef TARGET_SPARC64
0f8a249a
BS		 2425 if (!supervisor(dc))
2426 goto priv_insn;
e8af50a3 2427 gen_op_xor_T1_T0();
e9ebed4d
BS		 2428 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2429#else
2430 if (!hypervisor(dc))
2431 goto priv_insn;
2432 gen_op_xor_T1_T0();
2433 switch (rd) {
2434 case 0: // hpstate
2435 // XXX gen_op_wrhpstate();
2436 save_state(dc);
2437 gen_op_next_insn();
57fec1fe 2438 tcg_gen_exit_tb(0);
e9ebed4d
BS		 2439 dc->is_br = 1;
2440 break;
2441 case 1: // htstate
2442 // XXX gen_op_wrhtstate();
2443 break;
2444 case 3: // hintp
2445 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2446 break;
2447 case 5: // htba
2448 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2449 break;
2450 case 31: // hstick_cmpr
20c9f095
BS		 2451 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2452 gen_op_wrhstick_cmpr();
e9ebed4d
BS		 2453 break;
2454 case 6: // hver readonly
2455 default:
2456 goto illegal_insn;
2457 }
2458#endif
e8af50a3
FB		 2459 }
2460 break;
2461#endif
3475187d 2462#ifdef TARGET_SPARC64
0f8a249a
BS		 2463 case 0x2c: /* V9 movcc */
2464 {
2465 int cc = GET_FIELD_SP(insn, 11, 12);
2466 int cond = GET_FIELD_SP(insn, 14, 17);
00f219bf
BS		 2467 TCGv r_zero;
2468 int l1;
2469
0f8a249a
BS		 2470 flush_T2(dc);
2471 if (insn & (1 << 18)) {
2472 if (cc == 0)
2473 gen_cond[0][cond]();
2474 else if (cc == 2)
2475 gen_cond[1][cond]();
2476 else
2477 goto illegal_insn;
2478 } else {
2479 gen_fcond[cc][cond]();
2480 }
00f219bf
BS		 2481
2482 l1 = gen_new_label();
2483
2484 r_zero = tcg_temp_new(TCG_TYPE_TL);
2485 tcg_gen_movi_tl(r_zero, 0);
2486 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1);
2487 if (IS_IMM) { /* immediate */
2488 rs2 = GET_FIELD_SPs(insn, 0, 10);
2489 gen_movl_simm_T1(rs2);
2490 } else {
2491 rs2 = GET_FIELD_SP(insn, 0, 4);
2492 gen_movl_reg_T1(rs2);
2493 }
2494 gen_movl_T1_reg(rd);
2495 gen_set_label(l1);
0f8a249a
BS		 2496 break;
2497 }
2498 case 0x2d: /* V9 sdivx */
3475187d 2499 gen_op_sdivx_T1_T0();
0f8a249a
BS		 2500 gen_movl_T0_reg(rd);
2501 break;
2502 case 0x2e: /* V9 popc */
2503 {
2504 if (IS_IMM) { /* immediate */
2505 rs2 = GET_FIELD_SPs(insn, 0, 12);
2506 gen_movl_simm_T1(rs2);
2507 // XXX optimize: popc(constant)
2508 }
2509 else {
2510 rs2 = GET_FIELD_SP(insn, 0, 4);
2511 gen_movl_reg_T1(rs2);
2512 }
1a2fb1c0
BS		 2513 tcg_gen_helper_1_1(helper_popc, cpu_T[0],
2514 cpu_T[1]);
0f8a249a
BS		 2515 gen_movl_T0_reg(rd);
2516 }
2517 case 0x2f: /* V9 movr */
2518 {
2519 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 2520 TCGv r_zero;
2521 int l1;
2522
0f8a249a 2523 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2524 gen_movl_reg_T0(rs1);
00f219bf
BS		 2525
2526 l1 = gen_new_label();
2527
2528 r_zero = tcg_temp_new(TCG_TYPE_TL);
2529 tcg_gen_movi_tl(r_zero, 0);
2530 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
0f8a249a
BS		 2531 if (IS_IMM) { /* immediate */
2532 rs2 = GET_FIELD_SPs(insn, 0, 9);
2533 gen_movl_simm_T1(rs2);
00f219bf 2534 } else {
0f8a249a
BS		 2535 rs2 = GET_FIELD_SP(insn, 0, 4);
2536 gen_movl_reg_T1(rs2);
2537 }
00f219bf
BS		 2538 gen_movl_T1_reg(rd);
2539 gen_set_label(l1);
0f8a249a
BS		 2540 break;
2541 }
2542#endif
2543 default:
2544 goto illegal_insn;
2545 }
2546 }
3299908c
BS		 2547 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2548#ifdef TARGET_SPARC64
2549 int opf = GET_FIELD_SP(insn, 5, 13);
2550 rs1 = GET_FIELD(insn, 13, 17);
2551 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 2552 if (gen_trap_ifnofpu(dc))
2553 goto jmp_insn;
3299908c
BS		 2554
2555 switch (opf) {
e9ebed4d
BS		 2556 case 0x000: /* VIS I edge8cc */
2557 case 0x001: /* VIS II edge8n */
2558 case 0x002: /* VIS I edge8lcc */
2559 case 0x003: /* VIS II edge8ln */
2560 case 0x004: /* VIS I edge16cc */
2561 case 0x005: /* VIS II edge16n */
2562 case 0x006: /* VIS I edge16lcc */
2563 case 0x007: /* VIS II edge16ln */
2564 case 0x008: /* VIS I edge32cc */
2565 case 0x009: /* VIS II edge32n */
2566 case 0x00a: /* VIS I edge32lcc */
2567 case 0x00b: /* VIS II edge32ln */
2568 // XXX
2569 goto illegal_insn;
2570 case 0x010: /* VIS I array8 */
2571 gen_movl_reg_T0(rs1);
2572 gen_movl_reg_T1(rs2);
2573 gen_op_array8();
2574 gen_movl_T0_reg(rd);
2575 break;
2576 case 0x012: /* VIS I array16 */
2577 gen_movl_reg_T0(rs1);
2578 gen_movl_reg_T1(rs2);
2579 gen_op_array16();
2580 gen_movl_T0_reg(rd);
2581 break;
2582 case 0x014: /* VIS I array32 */
2583 gen_movl_reg_T0(rs1);
2584 gen_movl_reg_T1(rs2);
2585 gen_op_array32();
2586 gen_movl_T0_reg(rd);
2587 break;
3299908c 2588 case 0x018: /* VIS I alignaddr */
3299908c
BS		 2589 gen_movl_reg_T0(rs1);
2590 gen_movl_reg_T1(rs2);
2591 gen_op_alignaddr();
2592 gen_movl_T0_reg(rd);
2593 break;
e9ebed4d 2594 case 0x019: /* VIS II bmask */
3299908c 2595 case 0x01a: /* VIS I alignaddrl */
3299908c 2596 // XXX
e9ebed4d
BS		 2597 goto illegal_insn;
2598 case 0x020: /* VIS I fcmple16 */
2382dc6b
BS		 2599 gen_op_load_fpr_DT0(DFPREG(rs1));
2600 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2601 gen_op_fcmple16();
2382dc6b 2602 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2603 break;
2604 case 0x022: /* VIS I fcmpne16 */
2382dc6b
BS		 2605 gen_op_load_fpr_DT0(DFPREG(rs1));
2606 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2607 gen_op_fcmpne16();
2382dc6b 2608 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 2609 break;
e9ebed4d 2610 case 0x024: /* VIS I fcmple32 */
2382dc6b
BS		 2611 gen_op_load_fpr_DT0(DFPREG(rs1));
2612 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2613 gen_op_fcmple32();
2382dc6b 2614 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2615 break;
2616 case 0x026: /* VIS I fcmpne32 */
2382dc6b
BS		 2617 gen_op_load_fpr_DT0(DFPREG(rs1));
2618 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2619 gen_op_fcmpne32();
2382dc6b 2620 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2621 break;
2622 case 0x028: /* VIS I fcmpgt16 */
2382dc6b
BS		 2623 gen_op_load_fpr_DT0(DFPREG(rs1));
2624 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2625 gen_op_fcmpgt16();
2382dc6b 2626 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2627 break;
2628 case 0x02a: /* VIS I fcmpeq16 */
2382dc6b
BS		 2629 gen_op_load_fpr_DT0(DFPREG(rs1));
2630 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2631 gen_op_fcmpeq16();
2382dc6b 2632 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2633 break;
2634 case 0x02c: /* VIS I fcmpgt32 */
2382dc6b
BS		 2635 gen_op_load_fpr_DT0(DFPREG(rs1));
2636 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2637 gen_op_fcmpgt32();
2382dc6b 2638 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2639 break;
2640 case 0x02e: /* VIS I fcmpeq32 */
2382dc6b
BS		 2641 gen_op_load_fpr_DT0(DFPREG(rs1));
2642 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2643 gen_op_fcmpeq32();
2382dc6b 2644 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2645 break;
2646 case 0x031: /* VIS I fmul8x16 */
2382dc6b
BS		 2647 gen_op_load_fpr_DT0(DFPREG(rs1));
2648 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2649 gen_op_fmul8x16();
2382dc6b 2650 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2651 break;
2652 case 0x033: /* VIS I fmul8x16au */
2382dc6b
BS		 2653 gen_op_load_fpr_DT0(DFPREG(rs1));
2654 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2655 gen_op_fmul8x16au();
2382dc6b 2656 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2657 break;
2658 case 0x035: /* VIS I fmul8x16al */
2382dc6b
BS		 2659 gen_op_load_fpr_DT0(DFPREG(rs1));
2660 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2661 gen_op_fmul8x16al();
2382dc6b 2662 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2663 break;
2664 case 0x036: /* VIS I fmul8sux16 */
2382dc6b
BS		 2665 gen_op_load_fpr_DT0(DFPREG(rs1));
2666 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2667 gen_op_fmul8sux16();
2382dc6b 2668 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2669 break;
2670 case 0x037: /* VIS I fmul8ulx16 */
2382dc6b
BS		 2671 gen_op_load_fpr_DT0(DFPREG(rs1));
2672 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2673 gen_op_fmul8ulx16();
2382dc6b 2674 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2675 break;
2676 case 0x038: /* VIS I fmuld8sux16 */
2382dc6b
BS		 2677 gen_op_load_fpr_DT0(DFPREG(rs1));
2678 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2679 gen_op_fmuld8sux16();
2382dc6b 2680 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2681 break;
2682 case 0x039: /* VIS I fmuld8ulx16 */
2382dc6b
BS		 2683 gen_op_load_fpr_DT0(DFPREG(rs1));
2684 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2685 gen_op_fmuld8ulx16();
2382dc6b 2686 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2687 break;
2688 case 0x03a: /* VIS I fpack32 */
2689 case 0x03b: /* VIS I fpack16 */
2690 case 0x03d: /* VIS I fpackfix */
2691 case 0x03e: /* VIS I pdist */
2692 // XXX
2693 goto illegal_insn;
3299908c 2694 case 0x048: /* VIS I faligndata */
2382dc6b
BS		 2695 gen_op_load_fpr_DT0(DFPREG(rs1));
2696 gen_op_load_fpr_DT1(DFPREG(rs2));
3299908c 2697 gen_op_faligndata();
2382dc6b 2698 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 2699 break;
e9ebed4d 2700 case 0x04b: /* VIS I fpmerge */
2382dc6b
BS		 2701 gen_op_load_fpr_DT0(DFPREG(rs1));
2702 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2703 gen_op_fpmerge();
2382dc6b 2704 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2705 break;
2706 case 0x04c: /* VIS II bshuffle */
2707 // XXX
2708 goto illegal_insn;
2709 case 0x04d: /* VIS I fexpand */
2382dc6b
BS		 2710 gen_op_load_fpr_DT0(DFPREG(rs1));
2711 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2712 gen_op_fexpand();
2382dc6b 2713 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2714 break;
2715 case 0x050: /* VIS I fpadd16 */
2382dc6b
BS		 2716 gen_op_load_fpr_DT0(DFPREG(rs1));
2717 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2718 gen_op_fpadd16();
2382dc6b 2719 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2720 break;
2721 case 0x051: /* VIS I fpadd16s */
2722 gen_op_load_fpr_FT0(rs1);
2723 gen_op_load_fpr_FT1(rs2);
2724 gen_op_fpadd16s();
2725 gen_op_store_FT0_fpr(rd);
2726 break;
2727 case 0x052: /* VIS I fpadd32 */
2382dc6b
BS		 2728 gen_op_load_fpr_DT0(DFPREG(rs1));
2729 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2730 gen_op_fpadd32();
2382dc6b 2731 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2732 break;
2733 case 0x053: /* VIS I fpadd32s */
2734 gen_op_load_fpr_FT0(rs1);
2735 gen_op_load_fpr_FT1(rs2);
2736 gen_op_fpadd32s();
2737 gen_op_store_FT0_fpr(rd);
2738 break;
2739 case 0x054: /* VIS I fpsub16 */
2382dc6b
BS		 2740 gen_op_load_fpr_DT0(DFPREG(rs1));
2741 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2742 gen_op_fpsub16();
2382dc6b 2743 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2744 break;
2745 case 0x055: /* VIS I fpsub16s */
2746 gen_op_load_fpr_FT0(rs1);
2747 gen_op_load_fpr_FT1(rs2);
2748 gen_op_fpsub16s();
2749 gen_op_store_FT0_fpr(rd);
2750 break;
2751 case 0x056: /* VIS I fpsub32 */
2382dc6b
BS		 2752 gen_op_load_fpr_DT0(DFPREG(rs1));
2753 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2754 gen_op_fpadd32();
2382dc6b 2755 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2756 break;
2757 case 0x057: /* VIS I fpsub32s */
2758 gen_op_load_fpr_FT0(rs1);
2759 gen_op_load_fpr_FT1(rs2);
2760 gen_op_fpsub32s();
2761 gen_op_store_FT0_fpr(rd);
2762 break;
3299908c 2763 case 0x060: /* VIS I fzero */
3299908c 2764 gen_op_movl_DT0_0();
2382dc6b 2765 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 2766 break;
2767 case 0x061: /* VIS I fzeros */
3299908c
BS		 2768 gen_op_movl_FT0_0();
2769 gen_op_store_FT0_fpr(rd);
2770 break;
e9ebed4d 2771 case 0x062: /* VIS I fnor */
2382dc6b
BS		 2772 gen_op_load_fpr_DT0(DFPREG(rs1));
2773 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2774 gen_op_fnor();
2382dc6b 2775 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2776 break;
2777 case 0x063: /* VIS I fnors */
2778 gen_op_load_fpr_FT0(rs1);
2779 gen_op_load_fpr_FT1(rs2);
2780 gen_op_fnors();
2781 gen_op_store_FT0_fpr(rd);
2782 break;
2783 case 0x064: /* VIS I fandnot2 */
2382dc6b
BS		 2784 gen_op_load_fpr_DT1(DFPREG(rs1));
2785 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 2786 gen_op_fandnot();
2382dc6b 2787 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2788 break;
2789 case 0x065: /* VIS I fandnot2s */
2790 gen_op_load_fpr_FT1(rs1);
2791 gen_op_load_fpr_FT0(rs2);
2792 gen_op_fandnots();
2793 gen_op_store_FT0_fpr(rd);
2794 break;
2795 case 0x066: /* VIS I fnot2 */
2382dc6b 2796 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2797 gen_op_fnot();
2382dc6b 2798 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2799 break;
2800 case 0x067: /* VIS I fnot2s */
2801 gen_op_load_fpr_FT1(rs2);
2802 gen_op_fnot();
2803 gen_op_store_FT0_fpr(rd);
2804 break;
2805 case 0x068: /* VIS I fandnot1 */
2382dc6b
BS		 2806 gen_op_load_fpr_DT0(DFPREG(rs1));
2807 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2808 gen_op_fandnot();
2382dc6b 2809 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2810 break;
2811 case 0x069: /* VIS I fandnot1s */
2812 gen_op_load_fpr_FT0(rs1);
2813 gen_op_load_fpr_FT1(rs2);
2814 gen_op_fandnots();
2815 gen_op_store_FT0_fpr(rd);
2816 break;
2817 case 0x06a: /* VIS I fnot1 */
2382dc6b 2818 gen_op_load_fpr_DT1(DFPREG(rs1));
e9ebed4d 2819 gen_op_fnot();
2382dc6b 2820 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2821 break;
2822 case 0x06b: /* VIS I fnot1s */
2823 gen_op_load_fpr_FT1(rs1);
2824 gen_op_fnot();
2825 gen_op_store_FT0_fpr(rd);
2826 break;
2827 case 0x06c: /* VIS I fxor */
2382dc6b
BS		 2828 gen_op_load_fpr_DT0(DFPREG(rs1));
2829 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2830 gen_op_fxor();
2382dc6b 2831 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2832 break;
2833 case 0x06d: /* VIS I fxors */
2834 gen_op_load_fpr_FT0(rs1);
2835 gen_op_load_fpr_FT1(rs2);
2836 gen_op_fxors();
2837 gen_op_store_FT0_fpr(rd);
2838 break;
2839 case 0x06e: /* VIS I fnand */
2382dc6b
BS		 2840 gen_op_load_fpr_DT0(DFPREG(rs1));
2841 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2842 gen_op_fnand();
2382dc6b 2843 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2844 break;
2845 case 0x06f: /* VIS I fnands */
2846 gen_op_load_fpr_FT0(rs1);
2847 gen_op_load_fpr_FT1(rs2);
2848 gen_op_fnands();
2849 gen_op_store_FT0_fpr(rd);
2850 break;
2851 case 0x070: /* VIS I fand */
2382dc6b
BS		 2852 gen_op_load_fpr_DT0(DFPREG(rs1));
2853 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2854 gen_op_fand();
2382dc6b 2855 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2856 break;
2857 case 0x071: /* VIS I fands */
2858 gen_op_load_fpr_FT0(rs1);
2859 gen_op_load_fpr_FT1(rs2);
2860 gen_op_fands();
2861 gen_op_store_FT0_fpr(rd);
2862 break;
2863 case 0x072: /* VIS I fxnor */
2382dc6b
BS		 2864 gen_op_load_fpr_DT0(DFPREG(rs1));
2865 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2866 gen_op_fxnor();
2382dc6b 2867 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2868 break;
2869 case 0x073: /* VIS I fxnors */
2870 gen_op_load_fpr_FT0(rs1);
2871 gen_op_load_fpr_FT1(rs2);
2872 gen_op_fxnors();
2873 gen_op_store_FT0_fpr(rd);
2874 break;
3299908c 2875 case 0x074: /* VIS I fsrc1 */
2382dc6b
BS		 2876 gen_op_load_fpr_DT0(DFPREG(rs1));
2877 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 2878 break;
2879 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 2880 gen_op_load_fpr_FT0(rs1);
2881 gen_op_store_FT0_fpr(rd);
2882 break;
e9ebed4d 2883 case 0x076: /* VIS I fornot2 */
2382dc6b
BS		 2884 gen_op_load_fpr_DT1(DFPREG(rs1));
2885 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 2886 gen_op_fornot();
2382dc6b 2887 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2888 break;
2889 case 0x077: /* VIS I fornot2s */
2890 gen_op_load_fpr_FT1(rs1);
2891 gen_op_load_fpr_FT0(rs2);
2892 gen_op_fornots();
2893 gen_op_store_FT0_fpr(rd);
2894 break;
3299908c 2895 case 0x078: /* VIS I fsrc2 */
2382dc6b
BS		 2896 gen_op_load_fpr_DT0(DFPREG(rs2));
2897 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 2898 break;
2899 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 2900 gen_op_load_fpr_FT0(rs2);
2901 gen_op_store_FT0_fpr(rd);
2902 break;
e9ebed4d 2903 case 0x07a: /* VIS I fornot1 */
2382dc6b
BS		 2904 gen_op_load_fpr_DT0(DFPREG(rs1));
2905 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2906 gen_op_fornot();
2382dc6b 2907 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2908 break;
2909 case 0x07b: /* VIS I fornot1s */
2910 gen_op_load_fpr_FT0(rs1);
2911 gen_op_load_fpr_FT1(rs2);
2912 gen_op_fornots();
2913 gen_op_store_FT0_fpr(rd);
2914 break;
2915 case 0x07c: /* VIS I for */
2382dc6b
BS		 2916 gen_op_load_fpr_DT0(DFPREG(rs1));
2917 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2918 gen_op_for();
2382dc6b 2919 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2920 break;
2921 case 0x07d: /* VIS I fors */
2922 gen_op_load_fpr_FT0(rs1);
2923 gen_op_load_fpr_FT1(rs2);
2924 gen_op_fors();
2925 gen_op_store_FT0_fpr(rd);
2926 break;
3299908c 2927 case 0x07e: /* VIS I fone */
3299908c 2928 gen_op_movl_DT0_1();
2382dc6b 2929 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 2930 break;
2931 case 0x07f: /* VIS I fones */
3299908c
BS		 2932 gen_op_movl_FT0_1();
2933 gen_op_store_FT0_fpr(rd);
2934 break;
e9ebed4d
BS		 2935 case 0x080: /* VIS I shutdown */
2936 case 0x081: /* VIS II siam */
2937 // XXX
2938 goto illegal_insn;
3299908c
BS		 2939 default:
2940 goto illegal_insn;
2941 }
2942#else
0f8a249a 2943 goto ncp_insn;
3299908c
BS		 2944#endif
2945 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 2946#ifdef TARGET_SPARC64
0f8a249a 2947 goto illegal_insn;
fcc72045 2948#else
0f8a249a 2949 goto ncp_insn;
fcc72045 2950#endif
3475187d 2951#ifdef TARGET_SPARC64
0f8a249a 2952 } else if (xop == 0x39) { /* V9 return */
3475187d 2953 rs1 = GET_FIELD(insn, 13, 17);
1ad21e69 2954 save_state(dc);
0f8a249a
BS		 2955 gen_movl_reg_T0(rs1);
2956 if (IS_IMM) { /* immediate */
2957 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2958 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 2959 } else { /* register */
3475187d
FB		 2960 rs2 = GET_FIELD(insn, 27, 31);
2961#if defined(OPTIM)
0f8a249a 2962 if (rs2) {
3475187d 2963#endif
0f8a249a
BS		 2964 gen_movl_reg_T1(rs2);
2965 gen_op_add_T1_T0();
3475187d 2966#if defined(OPTIM)
0f8a249a 2967 }
3475187d
FB		 2968#endif
2969 }
0f8a249a
BS		 2970 gen_op_restore();
2971 gen_mov_pc_npc(dc);
6ea4a6c8 2972 gen_op_check_align_T0_3();
1a2fb1c0 2973 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 2974 dc->npc = DYNAMIC_PC;
2975 goto jmp_insn;
3475187d 2976#endif
0f8a249a 2977 } else {
e80cfcfc 2978 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2979 gen_movl_reg_T0(rs1);
2980 if (IS_IMM) { /* immediate */
2981 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2982 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 2983 } else { /* register */
e80cfcfc
FB		 2984 rs2 = GET_FIELD(insn, 27, 31);
2985#if defined(OPTIM)
0f8a249a 2986 if (rs2) {
e80cfcfc 2987#endif
0f8a249a
BS		 2988 gen_movl_reg_T1(rs2);
2989 gen_op_add_T1_T0();
e80cfcfc 2990#if defined(OPTIM)
0f8a249a 2991 }
e8af50a3 2992#endif
cf495bcf 2993 }
0f8a249a
BS		 2994 switch (xop) {
2995 case 0x38: /* jmpl */
2996 {
2997 if (rd != 0) {
1a2fb1c0 2998 tcg_gen_movi_tl(cpu_T[1], dc->pc);
0f8a249a
BS		 2999 gen_movl_T1_reg(rd);
3000 }
0bee699e 3001 gen_mov_pc_npc(dc);
6ea4a6c8 3002 gen_op_check_align_T0_3();
1a2fb1c0 3003 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3004 dc->npc = DYNAMIC_PC;
3005 }
3006 goto jmp_insn;
3475187d 3007#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 3008 case 0x39: /* rett, V9 return */
3009 {
3010 if (!supervisor(dc))
3011 goto priv_insn;
0bee699e 3012 gen_mov_pc_npc(dc);
6ea4a6c8 3013 gen_op_check_align_T0_3();
1a2fb1c0 3014 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a 3015 dc->npc = DYNAMIC_PC;
1a2fb1c0 3016 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 3017 }
3018 goto jmp_insn;
3019#endif
3020 case 0x3b: /* flush */
1a2fb1c0 3021 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
0f8a249a
BS		 3022 break;
3023 case 0x3c: /* save */
3024 save_state(dc);
3025 gen_op_save();
3026 gen_movl_T0_reg(rd);
3027 break;
3028 case 0x3d: /* restore */
3029 save_state(dc);
3030 gen_op_restore();
3031 gen_movl_T0_reg(rd);
3032 break;
3475187d 3033#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 3034 case 0x3e: /* V9 done/retry */
3035 {
3036 switch (rd) {
3037 case 0:
3038 if (!supervisor(dc))
3039 goto priv_insn;
3040 dc->npc = DYNAMIC_PC;
3041 dc->pc = DYNAMIC_PC;
1a2fb1c0 3042 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 3043 goto jmp_insn;
3044 case 1:
3045 if (!supervisor(dc))
3046 goto priv_insn;
3047 dc->npc = DYNAMIC_PC;
3048 dc->pc = DYNAMIC_PC;
1a2fb1c0 3049 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 3050 goto jmp_insn;
3051 default:
3052 goto illegal_insn;
3053 }
3054 }
3055 break;
3056#endif
3057 default:
3058 goto illegal_insn;
3059 }
cf495bcf 3060 }
0f8a249a
BS		 3061 break;
3062 }
3063 break;
3064 case 3: /* load/store instructions */
3065 {
3066 unsigned int xop = GET_FIELD(insn, 7, 12);
3067 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 3068 save_state(dc);
0f8a249a 3069 gen_movl_reg_T0(rs1);
81ad8ba2
BS		 3070 if (xop == 0x3c || xop == 0x3e)
3071 {
3072 rs2 = GET_FIELD(insn, 27, 31);
3073 gen_movl_reg_T1(rs2);
3074 }
3075 else if (IS_IMM) { /* immediate */
0f8a249a 3076 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3077 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 3078 } else { /* register */
3079 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 3080#if defined(OPTIM)
0f8a249a 3081 if (rs2 != 0) {
e80cfcfc 3082#endif
0f8a249a
BS		 3083 gen_movl_reg_T1(rs2);
3084 gen_op_add_T1_T0();
e80cfcfc 3085#if defined(OPTIM)
0f8a249a 3086 }
e80cfcfc 3087#endif
0f8a249a 3088 }
2f2ecb83
BS		 3089 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
3090 (xop > 0x17 && xop <= 0x1d ) ||
3091 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 3092 switch (xop) {
1a2fb1c0 3093 case 0x0: /* load unsigned word */
6ea4a6c8 3094 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3095 ABI32_MASK(cpu_T[0]);
3096 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3097 break;
3098 case 0x1: /* load unsigned byte */
1a2fb1c0
BS		 3099 ABI32_MASK(cpu_T[0]);
3100 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3101 break;
3102 case 0x2: /* load unsigned halfword */
6ea4a6c8 3103 gen_op_check_align_T0_1();
1a2fb1c0
BS		 3104 ABI32_MASK(cpu_T[0]);
3105 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3106 break;
3107 case 0x3: /* load double word */
0f8a249a 3108 if (rd & 1)
d4218d99 3109 goto illegal_insn;
1a2fb1c0
BS		 3110 else {
3111 TCGv r_dword;
3112
3113 r_dword = tcg_temp_new(TCG_TYPE_I64);
3114 gen_op_check_align_T0_7();
3115 ABI32_MASK(cpu_T[0]);
3116 tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
3117 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
3118 gen_movl_T0_reg(rd + 1);
3119 tcg_gen_shri_i64(r_dword, r_dword, 32);
3120 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
3121 }
0f8a249a
BS		 3122 break;
3123 case 0x9: /* load signed byte */
1a2fb1c0
BS		 3124 ABI32_MASK(cpu_T[0]);
3125 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3126 break;
3127 case 0xa: /* load signed halfword */
6ea4a6c8 3128 gen_op_check_align_T0_1();
1a2fb1c0
BS		 3129 ABI32_MASK(cpu_T[0]);
3130 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3131 break;
3132 case 0xd: /* ldstub -- XXX: should be atomically */
1a2fb1c0
BS		 3133 tcg_gen_movi_i32(cpu_tmp0, 0xff);
3134 ABI32_MASK(cpu_T[0]);
3135 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
3136 tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3137 break;
3138 case 0x0f: /* swap register with memory. Also atomically */
6ea4a6c8 3139 gen_op_check_align_T0_3();
0f8a249a 3140 gen_movl_reg_T1(rd);
1a2fb1c0
BS		 3141 ABI32_MASK(cpu_T[0]);
3142 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
3143 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
3144 tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
0f8a249a 3145 break;
3475187d 3146#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 3147 case 0x10: /* load word alternate */
3475187d 3148#ifndef TARGET_SPARC64
0f8a249a
BS		 3149 if (IS_IMM)
3150 goto illegal_insn;
3151 if (!supervisor(dc))
3152 goto priv_insn;
6ea4a6c8 3153#endif
8f577d3d 3154 gen_op_check_align_T0_3();
81ad8ba2 3155 gen_ld_asi(insn, 4, 0);
0f8a249a
BS		 3156 break;
3157 case 0x11: /* load unsigned byte alternate */
3475187d 3158#ifndef TARGET_SPARC64
0f8a249a
BS		 3159 if (IS_IMM)
3160 goto illegal_insn;
3161 if (!supervisor(dc))
3162 goto priv_insn;
3163#endif
81ad8ba2 3164 gen_ld_asi(insn, 1, 0);
0f8a249a
BS		 3165 break;
3166 case 0x12: /* load unsigned halfword alternate */
3475187d 3167#ifndef TARGET_SPARC64
0f8a249a
BS		 3168 if (IS_IMM)
3169 goto illegal_insn;
3170 if (!supervisor(dc))
3171 goto priv_insn;
3475187d 3172#endif
8f577d3d 3173 gen_op_check_align_T0_1();
81ad8ba2 3174 gen_ld_asi(insn, 2, 0);
0f8a249a
BS		 3175 break;
3176 case 0x13: /* load double word alternate */
3475187d 3177#ifndef TARGET_SPARC64
0f8a249a
BS		 3178 if (IS_IMM)
3179 goto illegal_insn;
3180 if (!supervisor(dc))
3181 goto priv_insn;
3475187d 3182#endif
0f8a249a 3183 if (rd & 1)
d4218d99 3184 goto illegal_insn;
6ea4a6c8 3185 gen_op_check_align_T0_7();
81ad8ba2 3186 gen_ldda_asi(insn);
0f8a249a
BS		 3187 gen_movl_T0_reg(rd + 1);
3188 break;
3189 case 0x19: /* load signed byte alternate */
3475187d 3190#ifndef TARGET_SPARC64
0f8a249a
BS		 3191 if (IS_IMM)
3192 goto illegal_insn;
3193 if (!supervisor(dc))
3194 goto priv_insn;
3195#endif
81ad8ba2 3196 gen_ld_asi(insn, 1, 1);
0f8a249a
BS		 3197 break;
3198 case 0x1a: /* load signed halfword alternate */
3475187d 3199#ifndef TARGET_SPARC64
0f8a249a
BS		 3200 if (IS_IMM)
3201 goto illegal_insn;
3202 if (!supervisor(dc))
3203 goto priv_insn;
3475187d 3204#endif
8f577d3d 3205 gen_op_check_align_T0_1();
81ad8ba2 3206 gen_ld_asi(insn, 2, 1);
0f8a249a
BS		 3207 break;
3208 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 3209#ifndef TARGET_SPARC64
0f8a249a
BS		 3210 if (IS_IMM)
3211 goto illegal_insn;
3212 if (!supervisor(dc))
3213 goto priv_insn;
3214#endif
81ad8ba2 3215 gen_ldstub_asi(insn);
0f8a249a
BS		 3216 break;
3217 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 3218#ifndef TARGET_SPARC64
0f8a249a
BS		 3219 if (IS_IMM)
3220 goto illegal_insn;
3221 if (!supervisor(dc))
3222 goto priv_insn;
6ea4a6c8 3223#endif
8f577d3d 3224 gen_op_check_align_T0_3();
81ad8ba2
BS		 3225 gen_movl_reg_T1(rd);
3226 gen_swap_asi(insn);
0f8a249a 3227 break;
3475187d
FB		 3228
3229#ifndef TARGET_SPARC64
0f8a249a
BS		 3230 case 0x30: /* ldc */
3231 case 0x31: /* ldcsr */
3232 case 0x33: /* lddc */
3233 goto ncp_insn;
3475187d
FB		 3234#endif
3235#endif
3236#ifdef TARGET_SPARC64
0f8a249a 3237 case 0x08: /* V9 ldsw */
6ea4a6c8 3238 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3239 ABI32_MASK(cpu_T[0]);
3240 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3241 break;
3242 case 0x0b: /* V9 ldx */
6ea4a6c8 3243 gen_op_check_align_T0_7();
1a2fb1c0
BS		 3244 ABI32_MASK(cpu_T[0]);
3245 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3246 break;
3247 case 0x18: /* V9 ldswa */
6ea4a6c8 3248 gen_op_check_align_T0_3();
81ad8ba2 3249 gen_ld_asi(insn, 4, 1);
0f8a249a
BS		 3250 break;
3251 case 0x1b: /* V9 ldxa */
6ea4a6c8 3252 gen_op_check_align_T0_7();
81ad8ba2 3253 gen_ld_asi(insn, 8, 0);
0f8a249a
BS		 3254 break;
3255 case 0x2d: /* V9 prefetch, no effect */
3256 goto skip_move;
3257 case 0x30: /* V9 ldfa */
6ea4a6c8 3258 gen_op_check_align_T0_3();
2382dc6b 3259 gen_ldf_asi(insn, 4, rd);
81ad8ba2 3260 goto skip_move;
0f8a249a 3261 case 0x33: /* V9 lddfa */
3391c818 3262 gen_op_check_align_T0_3();
2382dc6b 3263 gen_ldf_asi(insn, 8, DFPREG(rd));
81ad8ba2 3264 goto skip_move;
0f8a249a
BS		 3265 case 0x3d: /* V9 prefetcha, no effect */
3266 goto skip_move;
3267 case 0x32: /* V9 ldqfa */
1f587329
BS		 3268#if defined(CONFIG_USER_ONLY)
3269 gen_op_check_align_T0_3();
2382dc6b 3270 gen_ldf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 3271 goto skip_move;
3272#else
0f8a249a 3273 goto nfpu_insn;
1f587329 3274#endif
0f8a249a
BS		 3275#endif
3276 default:
3277 goto illegal_insn;
3278 }
3279 gen_movl_T1_reg(rd);
3475187d 3280#ifdef TARGET_SPARC64
0f8a249a 3281 skip_move: ;
3475187d 3282#endif
0f8a249a 3283 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 3284 if (gen_trap_ifnofpu(dc))
3285 goto jmp_insn;
0f8a249a
BS		 3286 switch (xop) {
3287 case 0x20: /* load fpreg */
6ea4a6c8 3288 gen_op_check_align_T0_3();
0f8a249a
BS		 3289 gen_op_ldst(ldf);
3290 gen_op_store_FT0_fpr(rd);
3291 break;
3292 case 0x21: /* load fsr */
6ea4a6c8 3293 gen_op_check_align_T0_3();
0f8a249a
BS		 3294 gen_op_ldst(ldf);
3295 gen_op_ldfsr();
3296 break;
3297 case 0x22: /* load quad fpreg */
1f587329
BS		 3298#if defined(CONFIG_USER_ONLY)
3299 gen_op_check_align_T0_7();
3300 gen_op_ldst(ldqf);
3301 gen_op_store_QT0_fpr(QFPREG(rd));
3302 break;
3303#else
0f8a249a 3304 goto nfpu_insn;
1f587329 3305#endif
0f8a249a 3306 case 0x23: /* load double fpreg */
6ea4a6c8 3307 gen_op_check_align_T0_7();
0f8a249a
BS		 3308 gen_op_ldst(lddf);
3309 gen_op_store_DT0_fpr(DFPREG(rd));
3310 break;
3311 default:
3312 goto illegal_insn;
3313 }
3314 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3315 xop == 0xe || xop == 0x1e) {
3316 gen_movl_reg_T1(rd);
3317 switch (xop) {
1a2fb1c0 3318 case 0x4: /* store word */
6ea4a6c8 3319 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3320 ABI32_MASK(cpu_T[0]);
3321 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 3322 break;
1a2fb1c0
BS		 3323 case 0x5: /* store byte */
3324 ABI32_MASK(cpu_T[0]);
3325 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 3326 break;
1a2fb1c0 3327 case 0x6: /* store halfword */
6ea4a6c8 3328 gen_op_check_align_T0_1();
1a2fb1c0
BS		 3329 ABI32_MASK(cpu_T[0]);
3330 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 3331 break;
1a2fb1c0 3332 case 0x7: /* store double word */
0f8a249a 3333 if (rd & 1)
d4218d99 3334 goto illegal_insn;
b25deda7 3335#ifndef __i386__
1a2fb1c0
BS		 3336 else {
3337 TCGv r_dword, r_low;
3338
3339 gen_op_check_align_T0_7();
3340 r_dword = tcg_temp_new(TCG_TYPE_I64);
3341 r_low = tcg_temp_new(TCG_TYPE_I32);
3342 gen_movl_reg_TN(rd + 1, r_low);
3343 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
3344 r_low);
3345 tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
3346 }
b25deda7
BS		 3347#else /* __i386__ */
3348 gen_op_check_align_T0_7();
3349 flush_T2(dc);
3350 gen_movl_reg_T2(rd + 1);
3351 gen_op_ldst(std);
3352#endif /* __i386__ */
0f8a249a 3353 break;
3475187d 3354#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 3355 case 0x14: /* store word alternate */
3475187d 3356#ifndef TARGET_SPARC64
0f8a249a
BS		 3357 if (IS_IMM)
3358 goto illegal_insn;
3359 if (!supervisor(dc))
3360 goto priv_insn;
6ea4a6c8 3361#endif
6ea4a6c8 3362 gen_op_check_align_T0_3();
81ad8ba2 3363 gen_st_asi(insn, 4);
d39c0b99 3364 break;
1a2fb1c0 3365 case 0x15: /* store byte alternate */
3475187d 3366#ifndef TARGET_SPARC64
0f8a249a
BS		 3367 if (IS_IMM)
3368 goto illegal_insn;
3369 if (!supervisor(dc))
3370 goto priv_insn;
3475187d 3371#endif
81ad8ba2 3372 gen_st_asi(insn, 1);
d39c0b99 3373 break;
1a2fb1c0 3374 case 0x16: /* store halfword alternate */
3475187d 3375#ifndef TARGET_SPARC64
0f8a249a
BS		 3376 if (IS_IMM)
3377 goto illegal_insn;
3378 if (!supervisor(dc))
3379 goto priv_insn;
6ea4a6c8 3380#endif
6ea4a6c8 3381 gen_op_check_align_T0_1();
81ad8ba2 3382 gen_st_asi(insn, 2);
d39c0b99 3383 break;
1a2fb1c0 3384 case 0x17: /* store double word alternate */
3475187d 3385#ifndef TARGET_SPARC64
0f8a249a
BS		 3386 if (IS_IMM)
3387 goto illegal_insn;
3388 if (!supervisor(dc))
3389 goto priv_insn;
3475187d 3390#endif
0f8a249a 3391 if (rd & 1)
d4218d99 3392 goto illegal_insn;
1a2fb1c0
BS		 3393 else {
3394 int asi;
3395 TCGv r_dword, r_temp, r_size;
3396
3397 gen_op_check_align_T0_7();
3398 r_dword = tcg_temp_new(TCG_TYPE_I64);
3399 r_temp = tcg_temp_new(TCG_TYPE_I32);
3400 r_size = tcg_temp_new(TCG_TYPE_I32);
3401 gen_movl_reg_TN(rd + 1, r_temp);
3402 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
3403 r_temp);
3404#ifdef TARGET_SPARC64
3405 if (IS_IMM) {
3406 int offset;
3407
3408 offset = GET_FIELD(insn, 25, 31);
3409 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
3410 tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
3411 } else {
3412#endif
3413 asi = GET_FIELD(insn, 19, 26);
3414 tcg_gen_movi_i32(r_temp, asi);
3415#ifdef TARGET_SPARC64
3416 }
3417#endif
3418 tcg_gen_movi_i32(r_size, 8);
3419 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
3420 }
d39c0b99 3421 break;
e80cfcfc 3422#endif
3475187d 3423#ifdef TARGET_SPARC64
0f8a249a 3424 case 0x0e: /* V9 stx */
6ea4a6c8 3425 gen_op_check_align_T0_7();
1a2fb1c0
BS		 3426 ABI32_MASK(cpu_T[0]);
3427 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3428 break;
3429 case 0x1e: /* V9 stxa */
6ea4a6c8 3430 gen_op_check_align_T0_7();
81ad8ba2 3431 gen_st_asi(insn, 8);
0f8a249a 3432 break;
3475187d 3433#endif
0f8a249a
BS		 3434 default:
3435 goto illegal_insn;
3436 }
3437 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 3438 if (gen_trap_ifnofpu(dc))
3439 goto jmp_insn;
0f8a249a
BS		 3440 switch (xop) {
3441 case 0x24:
6ea4a6c8 3442 gen_op_check_align_T0_3();
e8af50a3 3443 gen_op_load_fpr_FT0(rd);
0f8a249a
BS		 3444 gen_op_ldst(stf);
3445 break;
3446 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8
BS		 3447#ifdef CONFIG_USER_ONLY
3448 gen_op_check_align_T0_3();
3449#endif
0f8a249a
BS		 3450 gen_op_stfsr();
3451 gen_op_ldst(stf);
3452 break;
1f587329
BS		 3453 case 0x26:
3454#ifdef TARGET_SPARC64
3455#if defined(CONFIG_USER_ONLY)
3456 /* V9 stqf, store quad fpreg */
3457 gen_op_check_align_T0_7();
3458 gen_op_load_fpr_QT0(QFPREG(rd));
3459 gen_op_ldst(stqf);
3460 break;
3461#else
3462 goto nfpu_insn;
3463#endif
3464#else /* !TARGET_SPARC64 */
3465 /* stdfq, store floating point queue */
3466#if defined(CONFIG_USER_ONLY)
3467 goto illegal_insn;
3468#else
0f8a249a
BS		 3469 if (!supervisor(dc))
3470 goto priv_insn;
3471 if (gen_trap_ifnofpu(dc))
3472 goto jmp_insn;
3473 goto nfq_insn;
1f587329 3474#endif
0f8a249a
BS		 3475#endif
3476 case 0x27:
6ea4a6c8 3477 gen_op_check_align_T0_7();
3475187d 3478 gen_op_load_fpr_DT0(DFPREG(rd));
0f8a249a
BS		 3479 gen_op_ldst(stdf);
3480 break;
3481 default:
3482 goto illegal_insn;
3483 }
3484 } else if (xop > 0x33 && xop < 0x3f) {
3485 switch (xop) {
a4d17f19 3486#ifdef TARGET_SPARC64
0f8a249a 3487 case 0x34: /* V9 stfa */
6ea4a6c8 3488 gen_op_check_align_T0_3();
3391c818 3489 gen_op_load_fpr_FT0(rd);
2382dc6b 3490 gen_stf_asi(insn, 4, rd);
0f8a249a 3491 break;
1f587329
BS		 3492 case 0x36: /* V9 stqfa */
3493#if defined(CONFIG_USER_ONLY)
3494 gen_op_check_align_T0_7();
3495 gen_op_load_fpr_QT0(QFPREG(rd));
2382dc6b 3496 gen_stf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 3497 break;
3498#else
3499 goto nfpu_insn;
3500#endif
0f8a249a 3501 case 0x37: /* V9 stdfa */
3391c818
BS		 3502 gen_op_check_align_T0_3();
3503 gen_op_load_fpr_DT0(DFPREG(rd));
2382dc6b 3504 gen_stf_asi(insn, 8, DFPREG(rd));
0f8a249a
BS		 3505 break;
3506 case 0x3c: /* V9 casa */
6ea4a6c8 3507 gen_op_check_align_T0_3();
1a2fb1c0 3508 gen_cas_asi(insn, rd);
81ad8ba2 3509 gen_movl_T1_reg(rd);
0f8a249a
BS		 3510 break;
3511 case 0x3e: /* V9 casxa */
6ea4a6c8 3512 gen_op_check_align_T0_7();
1a2fb1c0 3513 gen_casx_asi(insn, rd);
81ad8ba2 3514 gen_movl_T1_reg(rd);
0f8a249a 3515 break;
a4d17f19 3516#else
0f8a249a
BS		 3517 case 0x34: /* stc */
3518 case 0x35: /* stcsr */
3519 case 0x36: /* stdcq */
3520 case 0x37: /* stdc */
3521 goto ncp_insn;
3522#endif
3523 default:
3524 goto illegal_insn;
3525 }
e8af50a3 3526 }
0f8a249a
BS		 3527 else
3528 goto illegal_insn;
3529 }
3530 break;
cf495bcf
FB		 3531 }
3532 /* default case for non jump instructions */
72cbca10 3533 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 3534 dc->pc = DYNAMIC_PC;
3535 gen_op_next_insn();
72cbca10
FB		 3536 } else if (dc->npc == JUMP_PC) {
3537 /* we can do a static jump */
46525e1f 3538 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 3539 dc->is_br = 1;
3540 } else {
0f8a249a
BS		 3541 dc->pc = dc->npc;
3542 dc->npc = dc->npc + 4;
cf495bcf 3543 }
e80cfcfc 3544 jmp_insn:
cf495bcf
FB		 3545 return;
3546 illegal_insn:
72cbca10 3547 save_state(dc);
cf495bcf
FB		 3548 gen_op_exception(TT_ILL_INSN);
3549 dc->is_br = 1;
e8af50a3 3550 return;
e80cfcfc 3551#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 3552 priv_insn:
3553 save_state(dc);
3554 gen_op_exception(TT_PRIV_INSN);
3555 dc->is_br = 1;
e80cfcfc 3556 return;
e80cfcfc
FB		 3557 nfpu_insn:
3558 save_state(dc);
3559 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3560 dc->is_br = 1;
fcc72045 3561 return;
1f587329 3562#ifndef TARGET_SPARC64
9143e598
BS		 3563 nfq_insn:
3564 save_state(dc);
3565 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3566 dc->is_br = 1;
3567 return;
3568#endif
1f587329 3569#endif
fcc72045
BS		 3570#ifndef TARGET_SPARC64
3571 ncp_insn:
3572 save_state(dc);
3573 gen_op_exception(TT_NCP_INSN);
3574 dc->is_br = 1;
3575 return;
3576#endif
7a3f1944
FB		 3577}
3578
1a2fb1c0
BS		 3579static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
3580{
3581}
3582
cf495bcf 3583static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 3584 int spc, CPUSPARCState *env)
7a3f1944 3585{
72cbca10 3586 target_ulong pc_start, last_pc;
cf495bcf
FB		 3587 uint16_t *gen_opc_end;
3588 DisasContext dc1, *dc = &dc1;
e8af50a3 3589 int j, lj = -1;
cf495bcf
FB		 3590
3591 memset(dc, 0, sizeof(DisasContext));
cf495bcf 3592 dc->tb = tb;
72cbca10 3593 pc_start = tb->pc;
cf495bcf 3594 dc->pc = pc_start;
e80cfcfc 3595 last_pc = dc->pc;
72cbca10 3596 dc->npc = (target_ulong) tb->cs_base;
6f27aba6
BS		 3597 dc->mem_idx = cpu_mmu_index(env);
3598 dc->fpu_enabled = cpu_fpu_enabled(env);
cf495bcf 3599 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 3600
1a2fb1c0
BS		 3601 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
3602 cpu_regwptr = tcg_temp_new(TCG_TYPE_PTR); // XXX
3603
cf495bcf 3604 do {
e8af50a3
FB		 3605 if (env->nb_breakpoints > 0) {
3606 for(j = 0; j < env->nb_breakpoints; j++) {
3607 if (env->breakpoints[j] == dc->pc) {
0f8a249a
BS		 3608 if (dc->pc != pc_start)
3609 save_state(dc);
1a2fb1c0 3610 tcg_gen_helper_0_0(helper_debug);
57fec1fe 3611 tcg_gen_exit_tb(0);
0f8a249a 3612 dc->is_br = 1;
e80cfcfc 3613 goto exit_gen_loop;
e8af50a3
FB		 3614 }
3615 }
3616 }
3617 if (spc) {
3618 if (loglevel > 0)
3619 fprintf(logfile, "Search PC...\n");
3620 j = gen_opc_ptr - gen_opc_buf;
3621 if (lj < j) {
3622 lj++;
3623 while (lj < j)
3624 gen_opc_instr_start[lj++] = 0;
3625 gen_opc_pc[lj] = dc->pc;
3626 gen_opc_npc[lj] = dc->npc;
3627 gen_opc_instr_start[lj] = 1;
3628 }
3629 }
0f8a249a
BS		 3630 last_pc = dc->pc;
3631 disas_sparc_insn(dc);
3632
3633 if (dc->is_br)
3634 break;
3635 /* if the next PC is different, we abort now */
3636 if (dc->pc != (last_pc + 4))
3637 break;
d39c0b99
FB		 3638 /* if we reach a page boundary, we stop generation so that the
3639 PC of a TT_TFAULT exception is always in the right page */
3640 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3641 break;
e80cfcfc
FB		 3642 /* if single step mode, we generate only one instruction and
3643 generate an exception */
3644 if (env->singlestep_enabled) {
3475187d 3645 gen_jmp_im(dc->pc);
57fec1fe 3646 tcg_gen_exit_tb(0);
e80cfcfc
FB		 3647 break;
3648 }
cf495bcf 3649 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 3650 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 3651
3652 exit_gen_loop:
72cbca10 3653 if (!dc->is_br) {
5fafdf24 3654 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 3655 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3656 /* static PC and NPC: we can use direct chaining */
46525e1f 3657 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 3658 } else {
3659 if (dc->pc != DYNAMIC_PC)
3475187d 3660 gen_jmp_im(dc->pc);
72cbca10 3661 save_npc(dc);
57fec1fe 3662 tcg_gen_exit_tb(0);
72cbca10
FB		 3663 }
3664 }
cf495bcf 3665 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 3666 if (spc) {
3667 j = gen_opc_ptr - gen_opc_buf;
3668 lj++;
3669 while (lj <= j)
3670 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 3671#if 0
3672 if (loglevel > 0) {
3673 page_dump(logfile);
3674 }
3675#endif
c3278b7b
FB		 3676 gen_opc_jump_pc[0] = dc->jump_pc[0];
3677 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 3678 } else {
e80cfcfc 3679 tb->size = last_pc + 4 - pc_start;
e8af50a3 3680 }
7a3f1944 3681#ifdef DEBUG_DISAS
e19e89a5 3682 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 3683 fprintf(logfile, "--------------\n");
3684 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3685 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3686 fprintf(logfile, "\n");
cf495bcf 3687 }
7a3f1944 3688#endif
cf495bcf 3689 return 0;
7a3f1944
FB		 3690}
3691
cf495bcf 3692int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3693{
e8af50a3 3694 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 3695}
3696
cf495bcf 3697int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3698{
e8af50a3 3699 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 3700}
3701
e80cfcfc
FB		 3702void cpu_reset(CPUSPARCState *env)
3703{
bb05683b 3704 tlb_flush(env, 1);
cf495bcf
FB		 3705 env->cwp = 0;
3706 env->wim = 1;
3707 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 3708#if defined(CONFIG_USER_ONLY)
cf495bcf 3709 env->user_mode_only = 1;
5ef54116 3710#ifdef TARGET_SPARC64
6ef905f6
BS		 3711 env->cleanwin = NWINDOWS - 2;
3712 env->cansave = NWINDOWS - 2;
3713 env->pstate = PS_RMO | PS_PEF | PS_IE;
3714 env->asi = 0x82; // Primary no-fault
5ef54116 3715#endif
e8af50a3 3716#else
32af58f9 3717 env->psret = 0;
e8af50a3 3718 env->psrs = 1;
0bee699e 3719 env->psrps = 1;
3475187d 3720#ifdef TARGET_SPARC64
83469015 3721 env->pstate = PS_PRIV;
6f27aba6 3722 env->hpstate = HS_PRIV;
83469015 3723 env->pc = 0x1fff0000000ULL;
3475187d 3724#else
40ce0a9a 3725 env->pc = 0;
32af58f9 3726 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
6d5f237a 3727 env->mmuregs[0] |= env->mmu_bm;
3475187d 3728#endif
83469015 3729 env->npc = env->pc + 4;
e8af50a3 3730#endif
e80cfcfc
FB		 3731}
3732
aaed909a 3733CPUSPARCState *cpu_sparc_init(const char *cpu_model)
e80cfcfc
FB		 3734{
3735 CPUSPARCState *env;
aaed909a 3736 const sparc_def_t *def;
1a2fb1c0 3737 static int inited;
aaed909a
FB		 3738
3739 def = cpu_sparc_find_by_name(cpu_model);
3740 if (!def)
3741 return NULL;
e80cfcfc 3742
c68ea704
FB		 3743 env = qemu_mallocz(sizeof(CPUSPARCState));
3744 if (!env)
0f8a249a 3745 return NULL;
c68ea704 3746 cpu_exec_init(env);
01ba9816 3747 env->cpu_model_str = cpu_model;
aaed909a
FB		 3748 env->version = def->iu_version;
3749 env->fsr = def->fpu_version;
3750#if !defined(TARGET_SPARC64)
3751 env->mmu_bm = def->mmu_bm;
3deaeab7
BS		 3752 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
3753 env->mmu_cxr_mask = def->mmu_cxr_mask;
3754 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
3755 env->mmu_trcr_mask = def->mmu_trcr_mask;
aaed909a
FB		 3756 env->mmuregs[0] |= def->mmu_version;
3757 cpu_sparc_set_id(env, 0);
3758#endif
1a2fb1c0
BS		 3759
3760 /* init various static tables */
3761 if (!inited) {
3762 inited = 1;
3763
3764 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
3765 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3766 //#if TARGET_LONG_BITS > HOST_LONG_BITS
3767#ifdef TARGET_SPARC64
3768 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3769 TCG_AREG0, offsetof(CPUState, t0), "T0");
3770 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3771 TCG_AREG0, offsetof(CPUState, t1), "T1");
3772 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
3773 TCG_AREG0, offsetof(CPUState, t2), "T2");
3774#else
3775 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3776 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3777 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
3778#endif
3779 }
3780
aaed909a
FB		 3781 cpu_reset(env);
3782
3783 return env;
3784}
3785
3786void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
3787{
3788#if !defined(TARGET_SPARC64)
3789 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
3790#endif
7a3f1944
FB		 3791}
3792
62724a37
BS		 3793static const sparc_def_t sparc_defs[] = {
3794#ifdef TARGET_SPARC64
7d77bf20
BS		 3795 {
3796 .name = "Fujitsu Sparc64",
3797 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
3798 | (MAXTL << 8) | (NWINDOWS - 1)),
3799 .fpu_version = 0x00000000,
3800 .mmu_version = 0,
3801 },
3802 {
3803 .name = "Fujitsu Sparc64 III",
3804 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
3805 | (MAXTL << 8) | (NWINDOWS - 1)),
3806 .fpu_version = 0x00000000,
3807 .mmu_version = 0,
3808 },
3809 {
3810 .name = "Fujitsu Sparc64 IV",
3811 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
3812 | (MAXTL << 8) | (NWINDOWS - 1)),
3813 .fpu_version = 0x00000000,
3814 .mmu_version = 0,
3815 },
3816 {
3817 .name = "Fujitsu Sparc64 V",
3818 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
3819 | (MAXTL << 8) | (NWINDOWS - 1)),
3820 .fpu_version = 0x00000000,
3821 .mmu_version = 0,
3822 },
3823 {
3824 .name = "TI UltraSparc I",
3825 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
3826 | (MAXTL << 8) | (NWINDOWS - 1)),
3827 .fpu_version = 0x00000000,
3828 .mmu_version = 0,
3829 },
62724a37
BS		 3830 {
3831 .name = "TI UltraSparc II",
7d77bf20
BS		 3832 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
3833 | (MAXTL << 8) | (NWINDOWS - 1)),
3834 .fpu_version = 0x00000000,
3835 .mmu_version = 0,
3836 },
3837 {
3838 .name = "TI UltraSparc IIi",
3839 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
3840 | (MAXTL << 8) | (NWINDOWS - 1)),
3841 .fpu_version = 0x00000000,
3842 .mmu_version = 0,
3843 },
3844 {
3845 .name = "TI UltraSparc IIe",
3846 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
3847 | (MAXTL << 8) | (NWINDOWS - 1)),
3848 .fpu_version = 0x00000000,
3849 .mmu_version = 0,
3850 },
3851 {
3852 .name = "Sun UltraSparc III",
3853 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
3854 | (MAXTL << 8) | (NWINDOWS - 1)),
3855 .fpu_version = 0x00000000,
3856 .mmu_version = 0,
3857 },
3858 {
3859 .name = "Sun UltraSparc III Cu",
3860 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
3861 | (MAXTL << 8) | (NWINDOWS - 1)),
3862 .fpu_version = 0x00000000,
3863 .mmu_version = 0,
3864 },
3865 {
3866 .name = "Sun UltraSparc IIIi",
3867 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
3868 | (MAXTL << 8) | (NWINDOWS - 1)),
3869 .fpu_version = 0x00000000,
3870 .mmu_version = 0,
3871 },
3872 {
3873 .name = "Sun UltraSparc IV",
3874 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
3875 | (MAXTL << 8) | (NWINDOWS - 1)),
3876 .fpu_version = 0x00000000,
3877 .mmu_version = 0,
3878 },
3879 {
3880 .name = "Sun UltraSparc IV+",
3881 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
3882 | (MAXTL << 8) | (NWINDOWS - 1)),
3883 .fpu_version = 0x00000000,
3884 .mmu_version = 0,
3885 },
3886 {
3887 .name = "Sun UltraSparc IIIi+",
3888 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
3889 | (MAXTL << 8) | (NWINDOWS - 1)),
3890 .fpu_version = 0x00000000,
3891 .mmu_version = 0,
3892 },
3893 {
3894 .name = "NEC UltraSparc I",
3895 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
62724a37
BS		 3896 | (MAXTL << 8) | (NWINDOWS - 1)),
3897 .fpu_version = 0x00000000,
3898 .mmu_version = 0,
3899 },
3900#else
406f82e8
BS		 3901 {
3902 .name = "Fujitsu MB86900",
3903 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
3904 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3905 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
3906 .mmu_bm = 0x00004000,
3deaeab7
BS		 3907 .mmu_ctpr_mask = 0x007ffff0,
3908 .mmu_cxr_mask = 0x0000003f,
3909 .mmu_sfsr_mask = 0xffffffff,
3910 .mmu_trcr_mask = 0xffffffff,
406f82e8 3911 },
62724a37
BS		 3912 {
3913 .name = "Fujitsu MB86904",
3914 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3915 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3916 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
6d5f237a 3917 .mmu_bm = 0x00004000,
3deaeab7
BS		 3918 .mmu_ctpr_mask = 0x00ffffc0,
3919 .mmu_cxr_mask = 0x000000ff,
3920 .mmu_sfsr_mask = 0x00016fff,
3921 .mmu_trcr_mask = 0x00ffffff,
62724a37 3922 },
e0353fe2 3923 {
5ef62c5c
BS		 3924 .name = "Fujitsu MB86907",
3925 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3926 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3927 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
6d5f237a 3928 .mmu_bm = 0x00004000,
3deaeab7
BS		 3929 .mmu_ctpr_mask = 0xffffffc0,
3930 .mmu_cxr_mask = 0x000000ff,
3931 .mmu_sfsr_mask = 0x00016fff,
3932 .mmu_trcr_mask = 0xffffffff,
5ef62c5c 3933 },
406f82e8
BS		 3934 {
3935 .name = "LSI L64811",
3936 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
3937 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
3938 .mmu_version = 0x10 << 24,
3939 .mmu_bm = 0x00004000,
3deaeab7
BS		 3940 .mmu_ctpr_mask = 0x007ffff0,
3941 .mmu_cxr_mask = 0x0000003f,
3942 .mmu_sfsr_mask = 0xffffffff,
3943 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 3944 },
3945 {
3946 .name = "Cypress CY7C601",
3947 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
3948 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
3949 .mmu_version = 0x10 << 24,
3950 .mmu_bm = 0x00004000,
3deaeab7
BS		 3951 .mmu_ctpr_mask = 0x007ffff0,
3952 .mmu_cxr_mask = 0x0000003f,
3953 .mmu_sfsr_mask = 0xffffffff,
3954 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 3955 },
3956 {
3957 .name = "Cypress CY7C611",
3958 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
3959 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
3960 .mmu_version = 0x10 << 24,
3961 .mmu_bm = 0x00004000,
3deaeab7
BS		 3962 .mmu_ctpr_mask = 0x007ffff0,
3963 .mmu_cxr_mask = 0x0000003f,
3964 .mmu_sfsr_mask = 0xffffffff,
3965 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 3966 },
3967 {
3968 .name = "TI SuperSparc II",
3969 .iu_version = 0x40000000,
3970 .fpu_version = 0 << 17,
3971 .mmu_version = 0x04000000,
3972 .mmu_bm = 0x00002000,
3deaeab7
BS		 3973 .mmu_ctpr_mask = 0xffffffc0,
3974 .mmu_cxr_mask = 0x0000ffff,
3975 .mmu_sfsr_mask = 0xffffffff,
3976 .mmu_trcr_mask = 0xffffffff,
406f82e8 3977 },
5ef62c5c
BS		 3978 {
3979 .name = "TI MicroSparc I",
3980 .iu_version = 0x41000000,
3981 .fpu_version = 4 << 17,
3982 .mmu_version = 0x41000000,
6d5f237a 3983 .mmu_bm = 0x00004000,
3deaeab7
BS		 3984 .mmu_ctpr_mask = 0x007ffff0,
3985 .mmu_cxr_mask = 0x0000003f,
3986 .mmu_sfsr_mask = 0x00016fff,
3987 .mmu_trcr_mask = 0x0000003f,
5ef62c5c
BS		 3988 },
3989 {
406f82e8
BS		 3990 .name = "TI MicroSparc II",
3991 .iu_version = 0x42000000,
3992 .fpu_version = 4 << 17,
3993 .mmu_version = 0x02000000,
3994 .mmu_bm = 0x00004000,
3deaeab7
BS		 3995 .mmu_ctpr_mask = 0x00ffffc0,
3996 .mmu_cxr_mask = 0x000000ff,
3997 .mmu_sfsr_mask = 0x00016bff,
3998 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 3999 },
4000 {
4001 .name = "TI MicroSparc IIep",
4002 .iu_version = 0x42000000,
4003 .fpu_version = 4 << 17,
4004 .mmu_version = 0x04000000,
4005 .mmu_bm = 0x00004000,
3deaeab7
BS		 4006 .mmu_ctpr_mask = 0x00ffffc0,
4007 .mmu_cxr_mask = 0x000000ff,
4008 .mmu_sfsr_mask = 0x00016bff,
4009 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4010 },
4011 {
4012 .name = "TI SuperSparc 51",
4013 .iu_version = 0x43000000,
5ef62c5c
BS		 4014 .fpu_version = 0 << 17,
4015 .mmu_version = 0x04000000,
6d5f237a 4016 .mmu_bm = 0x00002000,
3deaeab7
BS		 4017 .mmu_ctpr_mask = 0xffffffc0,
4018 .mmu_cxr_mask = 0x0000ffff,
4019 .mmu_sfsr_mask = 0xffffffff,
4020 .mmu_trcr_mask = 0xffffffff,
5ef62c5c
BS		 4021 },
4022 {
406f82e8
BS		 4023 .name = "TI SuperSparc 61",
4024 .iu_version = 0x44000000,
4025 .fpu_version = 0 << 17,
4026 .mmu_version = 0x04000000,
4027 .mmu_bm = 0x00002000,
3deaeab7
BS		 4028 .mmu_ctpr_mask = 0xffffffc0,
4029 .mmu_cxr_mask = 0x0000ffff,
4030 .mmu_sfsr_mask = 0xffffffff,
4031 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4032 },
4033 {
4034 .name = "Ross RT625",
5ef62c5c
BS		 4035 .iu_version = 0x1e000000,
4036 .fpu_version = 1 << 17,
406f82e8
BS		 4037 .mmu_version = 0x1e000000,
4038 .mmu_bm = 0x00004000,
3deaeab7
BS		 4039 .mmu_ctpr_mask = 0x007ffff0,
4040 .mmu_cxr_mask = 0x0000003f,
4041 .mmu_sfsr_mask = 0xffffffff,
4042 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4043 },
4044 {
4045 .name = "Ross RT620",
4046 .iu_version = 0x1f000000,
4047 .fpu_version = 1 << 17,
4048 .mmu_version = 0x1f000000,
4049 .mmu_bm = 0x00004000,
3deaeab7
BS		 4050 .mmu_ctpr_mask = 0x007ffff0,
4051 .mmu_cxr_mask = 0x0000003f,
4052 .mmu_sfsr_mask = 0xffffffff,
4053 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4054 },
4055 {
4056 .name = "BIT B5010",
4057 .iu_version = 0x20000000,
4058 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
4059 .mmu_version = 0x20000000,
4060 .mmu_bm = 0x00004000,
3deaeab7
BS		 4061 .mmu_ctpr_mask = 0x007ffff0,
4062 .mmu_cxr_mask = 0x0000003f,
4063 .mmu_sfsr_mask = 0xffffffff,
4064 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4065 },
4066 {
4067 .name = "Matsushita MN10501",
4068 .iu_version = 0x50000000,
4069 .fpu_version = 0 << 17,
4070 .mmu_version = 0x50000000,
4071 .mmu_bm = 0x00004000,
3deaeab7
BS		 4072 .mmu_ctpr_mask = 0x007ffff0,
4073 .mmu_cxr_mask = 0x0000003f,
4074 .mmu_sfsr_mask = 0xffffffff,
4075 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4076 },
4077 {
4078 .name = "Weitek W8601",
4079 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
4080 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
4081 .mmu_version = 0x10 << 24,
4082 .mmu_bm = 0x00004000,
3deaeab7
BS		 4083 .mmu_ctpr_mask = 0x007ffff0,
4084 .mmu_cxr_mask = 0x0000003f,
4085 .mmu_sfsr_mask = 0xffffffff,
4086 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4087 },
4088 {
4089 .name = "LEON2",
4090 .iu_version = 0xf2000000,
4091 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4092 .mmu_version = 0xf2000000,
4093 .mmu_bm = 0x00004000,
3deaeab7
BS		 4094 .mmu_ctpr_mask = 0x007ffff0,
4095 .mmu_cxr_mask = 0x0000003f,
4096 .mmu_sfsr_mask = 0xffffffff,
4097 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4098 },
4099 {
4100 .name = "LEON3",
4101 .iu_version = 0xf3000000,
4102 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4103 .mmu_version = 0xf3000000,
6d5f237a 4104 .mmu_bm = 0x00004000,
3deaeab7
BS		 4105 .mmu_ctpr_mask = 0x007ffff0,
4106 .mmu_cxr_mask = 0x0000003f,
4107 .mmu_sfsr_mask = 0xffffffff,
4108 .mmu_trcr_mask = 0xffffffff,
e0353fe2 4109 },
62724a37
BS		 4110#endif
4111};
4112
aaed909a 4113static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
62724a37 4114{
62724a37
BS		 4115 unsigned int i;
4116
62724a37
BS		 4117 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4118 if (strcasecmp(name, sparc_defs[i].name) == 0) {
aaed909a 4119 return &sparc_defs[i];
62724a37
BS		 4120 }
4121 }
aaed909a 4122 return NULL;
62724a37
BS		 4123}
4124
4125void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4126{
4127 unsigned int i;
4128
4129 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4130 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
4131 sparc_defs[i].name,
4132 sparc_defs[i].iu_version,
4133 sparc_defs[i].fpu_version,
4134 sparc_defs[i].mmu_version);
4135 }
4136}
4137
7a3f1944
FB		 4138#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
4139
5fafdf24 4140void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 4141 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4142 int flags)
7a3f1944 4143{
cf495bcf
FB		 4144 int i, x;
4145
af7bf89b 4146 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 4147 cpu_fprintf(f, "General Registers:\n");
cf495bcf 4148 for (i = 0; i < 4; i++)
0f8a249a 4149 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 4150 cpu_fprintf(f, "\n");
cf495bcf 4151 for (; i < 8; i++)
0f8a249a 4152 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 4153 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf 4154 for (x = 0; x < 3; x++) {
0f8a249a
BS		 4155 for (i = 0; i < 4; i++)
4156 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4157 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
4158 env->regwptr[i + x * 8]);
4159 cpu_fprintf(f, "\n");
4160 for (; i < 8; i++)
4161 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4162 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
4163 env->regwptr[i + x * 8]);
4164 cpu_fprintf(f, "\n");
cf495bcf 4165 }
7fe48483 4166 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 4167 for (i = 0; i < 32; i++) {
4168 if ((i & 3) == 0)
7fe48483
FB		 4169 cpu_fprintf(f, "%%f%02d:", i);
4170 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 4171 if ((i & 3) == 3)
7fe48483 4172 cpu_fprintf(f, "\n");
e8af50a3 4173 }
ded3ab80 4174#ifdef TARGET_SPARC64
3299908c 4175 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
0f8a249a 4176 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80 4177 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
0f8a249a
BS		 4178 env->cansave, env->canrestore, env->otherwin, env->wstate,
4179 env->cleanwin, NWINDOWS - 1 - env->cwp);
ded3ab80 4180#else
7fe48483 4181 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
0f8a249a
BS		 4182 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
4183 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
4184 env->psrs?'S':'-', env->psrps?'P':'-',
4185 env->psret?'E':'-', env->wim);
ded3ab80 4186#endif
3475187d 4187 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 4188}
edfcbd99 4189
e80cfcfc 4190#if defined(CONFIG_USER_ONLY)
9b3c35e0 4191target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 4192{
4193 return addr;
4194}
658138bc 4195
e80cfcfc 4196#else
af7bf89b
FB		 4197extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
4198 int *access_index, target_ulong address, int rw,
6ebbf390 4199 int mmu_idx);
0fa85d43 4200
9b3c35e0 4201target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 4202{
af7bf89b 4203 target_phys_addr_t phys_addr;
e80cfcfc
FB		 4204 int prot, access_index;
4205
9e31b9e2
BS		 4206 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
4207 MMU_KERNEL_IDX) != 0)
4208 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
4209 0, MMU_KERNEL_IDX) != 0)
6b1575b7 4210 return -1;
6c36d3fa
BS		 4211 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
4212 return -1;
e80cfcfc
FB		 4213 return phys_addr;
4214}
4215#endif
4216
658138bc
FB		 4217void helper_flush(target_ulong addr)
4218{
4219 addr &= ~7;
4220 tb_invalidate_page_range(addr, addr + 8);
4221}
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