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[mirror_qemu.git] / target-sparc / translate.c
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7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
7a3f1944
FB		 22#include <stdarg.h>
23#include <stdlib.h>
24#include <stdio.h>
25#include <string.h>
26#include <inttypes.h>
27
28#include "cpu.h"
29#include "exec-all.h"
30#include "disas.h"
1a2fb1c0 31#include "helper.h"
57fec1fe 32#include "tcg-op.h"
7a3f1944
FB		 33
34#define DEBUG_DISAS
35
72cbca10
FB		 36#define DYNAMIC_PC 1 /* dynamic pc value */
37#define JUMP_PC 2 /* dynamic pc value which takes only two values
38 according to jump_pc[T2] */
39
1a2fb1c0 40/* global register indexes */
d987963a 41static TCGv cpu_env, cpu_regwptr;
77f193da 42static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
48d5c82b 43static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
6ae20372 44static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
dc99a3f2
BS		 45#ifdef TARGET_SPARC64
46static TCGv cpu_xcc;
47#endif
1a2fb1c0 48/* local register indexes (only used inside old micro ops) */
8911f501 49static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
1a2fb1c0 50
2e70f6ef
PB		 51#include "gen-icount.h"
52
7a3f1944 53typedef struct DisasContext {
0f8a249a
BS		 54 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 56 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 57 int is_br;
e8af50a3 58 int mem_idx;
a80dde08 59 int fpu_enabled;
cf495bcf 60 struct TranslationBlock *tb;
64a88d5d 61 uint32_t features;
7a3f1944
FB		 62} DisasContext;
63
3475187d 64// This function uses non-native bit order
7a3f1944
FB		 65#define GET_FIELD(X, FROM, TO) \
66 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
67
3475187d
FB		 68// This function uses the order in the manuals, i.e. bit 0 is 2^0
69#define GET_FIELD_SP(X, FROM, TO) \
70 GET_FIELD(X, 31 - (TO), 31 - (FROM))
71
72#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 73#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 74
75#ifdef TARGET_SPARC64
19f329ad 76#define FFPREG(r) (r)
0387d928 77#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 78#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 79#else
19f329ad 80#define FFPREG(r) (r)
c185970a 81#define DFPREG(r) (r & 0x1e)
1f587329 82#define QFPREG(r) (r & 0x1c)
3475187d
FB		 83#endif
84
85static int sign_extend(int x, int len)
86{
87 len = 32 - len;
88 return (x << len) >> len;
89}
90
7a3f1944
FB		 91#define IS_IMM (insn & (1<<13))
92
ff07ec83
BS		 93/* floating point registers moves */
94static void gen_op_load_fpr_FT0(unsigned int src)
95{
8911f501
BS		 96 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
97 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
3475187d 98}
ff07ec83
BS		 99
100static void gen_op_load_fpr_FT1(unsigned int src)
101{
8911f501
BS		 102 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
103 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
e8af50a3
FB		 104}
105
ff07ec83
BS		 106static void gen_op_store_FT0_fpr(unsigned int dst)
107{
8911f501
BS		 108 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
109 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
ff07ec83
BS		 110}
111
112static void gen_op_load_fpr_DT0(unsigned int src)
113{
8911f501 114 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
77f193da
BS		 115 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
116 offsetof(CPU_DoubleU, l.upper));
8911f501 117 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
77f193da
BS		 118 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
119 offsetof(CPU_DoubleU, l.lower));
ff07ec83
BS		 120}
121
122static void gen_op_load_fpr_DT1(unsigned int src)
123{
8911f501 124 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
77f193da
BS		 125 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
126 offsetof(CPU_DoubleU, l.upper));
8911f501 127 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
77f193da
BS		 128 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
129 offsetof(CPU_DoubleU, l.lower));
ff07ec83
BS		 130}
131
132static void gen_op_store_DT0_fpr(unsigned int dst)
133{
77f193da
BS		 134 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
135 offsetof(CPU_DoubleU, l.upper));
8911f501 136 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
77f193da
BS		 137 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
138 offsetof(CPU_DoubleU, l.lower));
8911f501 139 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
ff07ec83
BS		 140}
141
ff07ec83
BS		 142static void gen_op_load_fpr_QT0(unsigned int src)
143{
8911f501 144 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
77f193da
BS		 145 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
146 offsetof(CPU_QuadU, l.upmost));
8911f501 147 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
77f193da
BS		 148 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
149 offsetof(CPU_QuadU, l.upper));
8911f501 150 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
77f193da
BS		 151 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
152 offsetof(CPU_QuadU, l.lower));
8911f501 153 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
77f193da
BS		 154 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
155 offsetof(CPU_QuadU, l.lowest));
ff07ec83
BS		 156}
157
158static void gen_op_load_fpr_QT1(unsigned int src)
159{
8911f501 160 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
77f193da
BS		 161 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
162 offsetof(CPU_QuadU, l.upmost));
8911f501 163 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
77f193da
BS		 164 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
165 offsetof(CPU_QuadU, l.upper));
8911f501 166 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
77f193da
BS		 167 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
168 offsetof(CPU_QuadU, l.lower));
8911f501 169 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
77f193da
BS		 170 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
171 offsetof(CPU_QuadU, l.lowest));
ff07ec83
BS		 172}
173
174static void gen_op_store_QT0_fpr(unsigned int dst)
175{
77f193da
BS		 176 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
177 offsetof(CPU_QuadU, l.upmost));
8911f501 178 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
77f193da
BS		 179 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
180 offsetof(CPU_QuadU, l.upper));
8911f501 181 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
77f193da
BS		 182 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
183 offsetof(CPU_QuadU, l.lower));
8911f501 184 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
77f193da
BS		 185 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
186 offsetof(CPU_QuadU, l.lowest));
8911f501 187 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
ff07ec83 188}
1f587329 189
81ad8ba2
BS		 190/* moves */
191#ifdef CONFIG_USER_ONLY
3475187d 192#define supervisor(dc) 0
81ad8ba2 193#ifdef TARGET_SPARC64
e9ebed4d 194#define hypervisor(dc) 0
81ad8ba2 195#endif
3475187d 196#else
6f27aba6 197#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 198#ifdef TARGET_SPARC64
199#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6 200#else
3475187d 201#endif
81ad8ba2
BS		 202#endif
203
1a2fb1c0 204#ifdef TARGET_ABI32
8911f501 205#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
1a2fb1c0
BS		 206#else
207#define ABI32_MASK(addr)
208#endif
3391c818 209
1a2fb1c0 210static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 211{
1a2fb1c0
BS		 212 if (reg == 0)
213 tcg_gen_movi_tl(tn, 0);
214 else if (reg < 8)
f5069b26 215 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
1a2fb1c0 216 else {
1a2fb1c0 217 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 218 }
219}
220
1a2fb1c0 221static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 222{
1a2fb1c0
BS		 223 if (reg == 0)
224 return;
225 else if (reg < 8)
f5069b26 226 tcg_gen_mov_tl(cpu_gregs[reg], tn);
1a2fb1c0 227 else {
1a2fb1c0 228 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 229 }
230}
231
5fafdf24 232static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 233 target_ulong pc, target_ulong npc)
234{
235 TranslationBlock *tb;
236
237 tb = s->tb;
238 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
239 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
240 /* jump to same page: we can use a direct jump */
57fec1fe 241 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 242 tcg_gen_movi_tl(cpu_pc, pc);
243 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 244 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 245 } else {
246 /* jump to another page: currently not optimized */
2f5680ee
BS		 247 tcg_gen_movi_tl(cpu_pc, pc);
248 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 249 tcg_gen_exit_tb(0);
6e256c93
FB		 250 }
251}
252
19f329ad
BS		 253// XXX suboptimal
254static inline void gen_mov_reg_N(TCGv reg, TCGv src)
255{
8911f501 256 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 257 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 258 tcg_gen_andi_tl(reg, reg, 0x1);
259}
260
261static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
262{
8911f501 263 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 264 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 265 tcg_gen_andi_tl(reg, reg, 0x1);
266}
267
268static inline void gen_mov_reg_V(TCGv reg, TCGv src)
269{
8911f501 270 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 271 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 272 tcg_gen_andi_tl(reg, reg, 0x1);
273}
274
275static inline void gen_mov_reg_C(TCGv reg, TCGv src)
276{
8911f501 277 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 278 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 279 tcg_gen_andi_tl(reg, reg, 0x1);
280}
281
ce5b3c3d 282static inline void gen_cc_clear_icc(void)
dc99a3f2
BS		 283{
284 tcg_gen_movi_i32(cpu_psr, 0);
ce5b3c3d
BS		 285}
286
dc99a3f2 287#ifdef TARGET_SPARC64
ce5b3c3d
BS		 288static inline void gen_cc_clear_xcc(void)
289{
dc99a3f2 290 tcg_gen_movi_i32(cpu_xcc, 0);
dc99a3f2 291}
ce5b3c3d 292#endif
dc99a3f2
BS		 293
294/* old op:
295 if (!T0)
296 env->psr |= PSR_ZERO;
297 if ((int32_t) T0 < 0)
298 env->psr |= PSR_NEG;
299*/
ce5b3c3d 300static inline void gen_cc_NZ_icc(TCGv dst)
dc99a3f2 301{
8911f501 302 TCGv r_temp;
dc99a3f2 303 int l1, l2;
dc99a3f2
BS		 304
305 l1 = gen_new_label();
306 l2 = gen_new_label();
8911f501
BS		 307 r_temp = tcg_temp_new(TCG_TYPE_TL);
308 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
cb63669a 309 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
dc99a3f2
BS		 310 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
311 gen_set_label(l1);
bdf46ea2 312 tcg_gen_ext_i32_tl(r_temp, dst);
cb63669a 313 tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
dc99a3f2
BS		 314 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
315 gen_set_label(l2);
2ea815ca 316 tcg_temp_free(r_temp);
ce5b3c3d
BS		 317}
318
dc99a3f2 319#ifdef TARGET_SPARC64
ce5b3c3d
BS		 320static inline void gen_cc_NZ_xcc(TCGv dst)
321{
322 int l1, l2;
323
324 l1 = gen_new_label();
325 l2 = gen_new_label();
cb63669a 326 tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
ce5b3c3d
BS		 327 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
328 gen_set_label(l1);
cb63669a 329 tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
ce5b3c3d
BS		 330 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
331 gen_set_label(l2);
dc99a3f2 332}
ce5b3c3d 333#endif
dc99a3f2
BS		 334
335/* old op:
336 if (T0 < src1)
337 env->psr |= PSR_CARRY;
338*/
ce5b3c3d 339static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
dc99a3f2 340{
8911f501 341 TCGv r_temp;
dc99a3f2
BS		 342 int l1;
343
344 l1 = gen_new_label();
8911f501
BS		 345 r_temp = tcg_temp_new(TCG_TYPE_TL);
346 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
347 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
dc99a3f2
BS		 348 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
349 gen_set_label(l1);
2ea815ca 350 tcg_temp_free(r_temp);
ce5b3c3d
BS		 351}
352
dc99a3f2 353#ifdef TARGET_SPARC64
ce5b3c3d
BS		 354static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
355{
356 int l1;
dc99a3f2 357
ce5b3c3d
BS		 358 l1 = gen_new_label();
359 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
360 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
361 gen_set_label(l1);
dc99a3f2 362}
ce5b3c3d 363#endif
dc99a3f2
BS		 364
365/* old op:
366 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
367 env->psr |= PSR_OVF;
368*/
ce5b3c3d 369static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 370{
0425bee5 371 TCGv r_temp;
dc99a3f2
BS		 372
373 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 374 tcg_gen_xor_tl(r_temp, src1, src2);
375 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 376 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
377 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
378 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
653ccb80
BS		 379 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
380 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
2ea815ca 381 tcg_temp_free(r_temp);
653ccb80 382 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
ce5b3c3d
BS		 383}
384
dc99a3f2 385#ifdef TARGET_SPARC64
ce5b3c3d
BS		 386static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
387{
388 TCGv r_temp;
ce5b3c3d
BS		 389
390 r_temp = tcg_temp_new(TCG_TYPE_TL);
391 tcg_gen_xor_tl(r_temp, src1, src2);
392 tcg_gen_xori_tl(r_temp, r_temp, -1);
393 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
394 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
395 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
653ccb80
BS		 396 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
397 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
2ea815ca 398 tcg_temp_free(r_temp);
653ccb80 399 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
dc99a3f2 400}
ce5b3c3d 401#endif
dc99a3f2
BS		 402
403static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
404{
2ea815ca 405 TCGv r_temp, r_const;
dc99a3f2
BS		 406 int l1;
407
408 l1 = gen_new_label();
409
410 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 411 tcg_gen_xor_tl(r_temp, src1, src2);
412 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 413 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
414 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
415 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
cb63669a 416 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
2ea815ca
BS		 417 r_const = tcg_const_i32(TT_TOVF);
418 tcg_gen_helper_0_1(raise_exception, r_const);
419 tcg_temp_free(r_const);
dc99a3f2 420 gen_set_label(l1);
2ea815ca 421 tcg_temp_free(r_temp);
dc99a3f2
BS		 422}
423
424static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
425{
426 int l1;
dc99a3f2
BS		 427
428 l1 = gen_new_label();
0425bee5
BS		 429 tcg_gen_or_tl(cpu_tmp0, src1, src2);
430 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
cb63669a 431 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
dc99a3f2
BS		 432 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
433 gen_set_label(l1);
434}
435
436static inline void gen_tag_tv(TCGv src1, TCGv src2)
437{
438 int l1;
2ea815ca 439 TCGv r_const;
dc99a3f2
BS		 440
441 l1 = gen_new_label();
0425bee5
BS		 442 tcg_gen_or_tl(cpu_tmp0, src1, src2);
443 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
cb63669a 444 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
2ea815ca
BS		 445 r_const = tcg_const_i32(TT_TOVF);
446 tcg_gen_helper_0_1(raise_exception, r_const);
447 tcg_temp_free(r_const);
dc99a3f2
BS		 448 gen_set_label(l1);
449}
450
4af984a7 451static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 452{
4af984a7 453 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 454 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 455 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 456 gen_cc_clear_icc();
ba28189b
BS		 457 gen_cc_NZ_icc(cpu_cc_dst);
458 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
459 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 460#ifdef TARGET_SPARC64
461 gen_cc_clear_xcc();
ba28189b
BS		 462 gen_cc_NZ_xcc(cpu_cc_dst);
463 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
464 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 465#endif
5c6a0628 466 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 467}
468
4af984a7 469static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 470{
4af984a7 471 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 472 tcg_gen_mov_tl(cpu_cc_src2, src2);
dc99a3f2 473 gen_mov_reg_C(cpu_tmp0, cpu_psr);
5c6a0628 474 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
ce5b3c3d 475 gen_cc_clear_icc();
5c6a0628 476 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
ce5b3c3d
BS		 477#ifdef TARGET_SPARC64
478 gen_cc_clear_xcc();
5c6a0628 479 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
ce5b3c3d 480#endif
5c6a0628 481 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
ba28189b
BS		 482 gen_cc_NZ_icc(cpu_cc_dst);
483 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
484 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 485#ifdef TARGET_SPARC64
ba28189b
BS		 486 gen_cc_NZ_xcc(cpu_cc_dst);
487 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
488 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 489#endif
5c6a0628 490 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 491}
492
4af984a7 493static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 494{
4af984a7 495 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 496 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 497 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 498 gen_cc_clear_icc();
ba28189b
BS		 499 gen_cc_NZ_icc(cpu_cc_dst);
500 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
501 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
6f551262 502 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 503#ifdef TARGET_SPARC64
504 gen_cc_clear_xcc();
ba28189b
BS		 505 gen_cc_NZ_xcc(cpu_cc_dst);
506 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
507 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 508#endif
5c6a0628 509 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 510}
511
4af984a7 512static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 513{
4af984a7 514 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 515 tcg_gen_mov_tl(cpu_cc_src2, src2);
516 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
5c6a0628
BS		 517 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
518 gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 519 gen_cc_clear_icc();
ba28189b
BS		 520 gen_cc_NZ_icc(cpu_cc_dst);
521 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
ce5b3c3d
BS		 522#ifdef TARGET_SPARC64
523 gen_cc_clear_xcc();
ba28189b
BS		 524 gen_cc_NZ_xcc(cpu_cc_dst);
525 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
526 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 527#endif
5c6a0628 528 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 529}
530
531/* old op:
532 if (src1 < T1)
533 env->psr |= PSR_CARRY;
534*/
ce5b3c3d 535static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
dc99a3f2 536{
8911f501 537 TCGv r_temp1, r_temp2;
dc99a3f2
BS		 538 int l1;
539
540 l1 = gen_new_label();
8911f501
BS		 541 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
542 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
543 tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
544 tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
545 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
dc99a3f2
BS		 546 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
547 gen_set_label(l1);
2ea815ca
BS		 548 tcg_temp_free(r_temp1);
549 tcg_temp_free(r_temp2);
ce5b3c3d
BS		 550}
551
dc99a3f2 552#ifdef TARGET_SPARC64
ce5b3c3d
BS		 553static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
554{
555 int l1;
dc99a3f2 556
ce5b3c3d
BS		 557 l1 = gen_new_label();
558 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
559 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
560 gen_set_label(l1);
dc99a3f2 561}
ce5b3c3d 562#endif
dc99a3f2
BS		 563
564/* old op:
565 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
566 env->psr |= PSR_OVF;
567*/
ce5b3c3d 568static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 569{
0425bee5 570 TCGv r_temp;
dc99a3f2
BS		 571
572 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 573 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 574 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
575 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
576 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
653ccb80
BS		 577 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
578 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
579 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
2ea815ca 580 tcg_temp_free(r_temp);
ce5b3c3d
BS		 581}
582
dc99a3f2 583#ifdef TARGET_SPARC64
ce5b3c3d
BS		 584static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
585{
586 TCGv r_temp;
ce5b3c3d
BS		 587
588 r_temp = tcg_temp_new(TCG_TYPE_TL);
589 tcg_gen_xor_tl(r_temp, src1, src2);
590 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
591 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
592 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
653ccb80
BS		 593 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
594 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
595 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
2ea815ca 596 tcg_temp_free(r_temp);
dc99a3f2 597}
ce5b3c3d 598#endif
dc99a3f2
BS		 599
600static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
601{
2ea815ca 602 TCGv r_temp, r_const;
dc99a3f2
BS		 603 int l1;
604
605 l1 = gen_new_label();
606
607 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 608 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 609 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
610 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
611 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
cb63669a 612 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
2ea815ca
BS		 613 r_const = tcg_const_i32(TT_TOVF);
614 tcg_gen_helper_0_1(raise_exception, r_const);
615 tcg_temp_free(r_const);
dc99a3f2 616 gen_set_label(l1);
2ea815ca 617 tcg_temp_free(r_temp);
dc99a3f2
BS		 618}
619
4af984a7 620static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 621{
4af984a7 622 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 623 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 624 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 625 gen_cc_clear_icc();
ba28189b 626 gen_cc_NZ_icc(cpu_cc_dst);
6f551262 627 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ba28189b 628 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 629#ifdef TARGET_SPARC64
630 gen_cc_clear_xcc();
ba28189b 631 gen_cc_NZ_xcc(cpu_cc_dst);
6f551262 632 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
ba28189b 633 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 634#endif
5c6a0628 635 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 636}
637
4af984a7 638static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 639{
4af984a7 640 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 641 tcg_gen_mov_tl(cpu_cc_src2, src2);
dc99a3f2 642 gen_mov_reg_C(cpu_tmp0, cpu_psr);
5c6a0628 643 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
ce5b3c3d 644 gen_cc_clear_icc();
5c6a0628 645 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
ce5b3c3d
BS		 646#ifdef TARGET_SPARC64
647 gen_cc_clear_xcc();
5c6a0628 648 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
ce5b3c3d 649#endif
5c6a0628 650 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
ba28189b
BS		 651 gen_cc_NZ_icc(cpu_cc_dst);
652 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
653 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 654#ifdef TARGET_SPARC64
ba28189b
BS		 655 gen_cc_NZ_xcc(cpu_cc_dst);
656 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
657 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 658#endif
5c6a0628 659 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 660}
661
4af984a7 662static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 663{
4af984a7 664 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 665 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 666 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 667 gen_cc_clear_icc();
ba28189b 668 gen_cc_NZ_icc(cpu_cc_dst);
6f551262 669 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ba28189b 670 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
6f551262 671 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 672#ifdef TARGET_SPARC64
673 gen_cc_clear_xcc();
ba28189b 674 gen_cc_NZ_xcc(cpu_cc_dst);
6f551262 675 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
ba28189b 676 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 677#endif
5c6a0628 678 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 679}
680
4af984a7 681static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 682{
4af984a7 683 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262
BS		 684 tcg_gen_mov_tl(cpu_cc_src2, src2);
685 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
5c6a0628
BS		 686 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
687 gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 688 gen_cc_clear_icc();
ba28189b 689 gen_cc_NZ_icc(cpu_cc_dst);
6f551262 690 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
ce5b3c3d
BS		 691#ifdef TARGET_SPARC64
692 gen_cc_clear_xcc();
ba28189b 693 gen_cc_NZ_xcc(cpu_cc_dst);
6f551262 694 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
ba28189b 695 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
ce5b3c3d 696#endif
5c6a0628 697 tcg_gen_mov_tl(dst, cpu_cc_dst);
dc99a3f2
BS		 698}
699
4af984a7 700static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 701{
7127fe84 702 TCGv r_temp, r_temp2;
6f551262 703 int l1;
d9bdab86
BS		 704
705 l1 = gen_new_label();
d9bdab86 706 r_temp = tcg_temp_new(TCG_TYPE_TL);
7127fe84 707 r_temp2 = tcg_temp_new(TCG_TYPE_I32);
d9bdab86
BS		 708
709 /* old op:
710 if (!(env->y & 1))
711 T1 = 0;
712 */
6f551262 713 tcg_gen_mov_tl(cpu_cc_src, src1);
7127fe84
BS		 714 tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
715 tcg_gen_trunc_tl_i32(r_temp2, r_temp);
716 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
4af984a7 717 tcg_gen_mov_tl(cpu_cc_src2, src2);
cb63669a 718 tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
d9bdab86 719 tcg_gen_movi_tl(cpu_cc_src2, 0);
6f551262 720 gen_set_label(l1);
d9bdab86
BS		 721
722 // b2 = T0 & 1;
723 // env->y = (b2 << 31) | (env->y >> 1);
6f551262 724 tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
7127fe84
BS		 725 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
726 tcg_gen_shli_i32(r_temp2, r_temp2, 31);
8911f501
BS		 727 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
728 tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
7127fe84 729 tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
2ea815ca 730 tcg_temp_free(r_temp2);
8911f501 731 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
d9bdab86
BS		 732
733 // b1 = N ^ V;
734 gen_mov_reg_N(cpu_tmp0, cpu_psr);
735 gen_mov_reg_V(r_temp, cpu_psr);
736 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
2ea815ca 737 tcg_temp_free(r_temp);
d9bdab86
BS		 738
739 // T0 = (b1 << 31) | (T0 >> 1);
740 // src1 = T0;
741 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
6f551262 742 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
d9bdab86
BS		 743 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
744
745 /* do addition and update flags */
5c6a0628 746 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 747
ce5b3c3d 748 gen_cc_clear_icc();
ba28189b
BS		 749 gen_cc_NZ_icc(cpu_cc_dst);
750 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
751 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
5c6a0628 752 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 753}
754
4af984a7 755static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139
BS		 756{
757 TCGv r_temp, r_temp2;
758
759 r_temp = tcg_temp_new(TCG_TYPE_I64);
760 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
761
4af984a7
BS		 762 tcg_gen_extu_tl_i64(r_temp, src2);
763 tcg_gen_extu_tl_i64(r_temp2, src1);
8879d139
BS		 764 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
765
766 tcg_gen_shri_i64(r_temp, r_temp2, 32);
767 tcg_gen_trunc_i64_i32(r_temp, r_temp);
768 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
2ea815ca 769 tcg_temp_free(r_temp);
8879d139 770#ifdef TARGET_SPARC64
4af984a7 771 tcg_gen_mov_i64(dst, r_temp2);
8879d139 772#else
4af984a7 773 tcg_gen_trunc_i64_tl(dst, r_temp2);
8879d139 774#endif
2ea815ca 775 tcg_temp_free(r_temp2);
8879d139
BS		 776}
777
4af984a7 778static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
8879d139
BS		 779{
780 TCGv r_temp, r_temp2;
781
782 r_temp = tcg_temp_new(TCG_TYPE_I64);
783 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
784
4af984a7
BS		 785 tcg_gen_ext_tl_i64(r_temp, src2);
786 tcg_gen_ext_tl_i64(r_temp2, src1);
8879d139
BS		 787 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
788
789 tcg_gen_shri_i64(r_temp, r_temp2, 32);
790 tcg_gen_trunc_i64_i32(r_temp, r_temp);
791 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
2ea815ca 792 tcg_temp_free(r_temp);
8879d139 793#ifdef TARGET_SPARC64
4af984a7 794 tcg_gen_mov_i64(dst, r_temp2);
8879d139 795#else
4af984a7 796 tcg_gen_trunc_i64_tl(dst, r_temp2);
8879d139 797#endif
2ea815ca 798 tcg_temp_free(r_temp2);
8879d139
BS		 799}
800
1a7b60e7 801#ifdef TARGET_SPARC64
8911f501 802static inline void gen_trap_ifdivzero_tl(TCGv divisor)
1a7b60e7 803{
2ea815ca 804 TCGv r_const;
1a7b60e7
BS		 805 int l1;
806
807 l1 = gen_new_label();
cb63669a 808 tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
2ea815ca
BS		 809 r_const = tcg_const_i32(TT_DIV_ZERO);
810 tcg_gen_helper_0_1(raise_exception, r_const);
811 tcg_temp_free(r_const);
1a7b60e7
BS		 812 gen_set_label(l1);
813}
814
4af984a7 815static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
1a7b60e7
BS		 816{
817 int l1, l2;
818
819 l1 = gen_new_label();
820 l2 = gen_new_label();
6f551262
BS		 821 tcg_gen_mov_tl(cpu_cc_src, src1);
822 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 823 gen_trap_ifdivzero_tl(cpu_cc_src2);
cb63669a
PB		 824 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
825 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
4af984a7 826 tcg_gen_movi_i64(dst, INT64_MIN);
06b3e1b3 827 tcg_gen_br(l2);
1a7b60e7 828 gen_set_label(l1);
6f551262 829 tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
1a7b60e7
BS		 830 gen_set_label(l2);
831}
832#endif
833
4af984a7 834static inline void gen_op_div_cc(TCGv dst)
dc99a3f2
BS		 835{
836 int l1;
dc99a3f2 837
ba28189b 838 tcg_gen_mov_tl(cpu_cc_dst, dst);
ce5b3c3d 839 gen_cc_clear_icc();
ba28189b 840 gen_cc_NZ_icc(cpu_cc_dst);
dc99a3f2 841 l1 = gen_new_label();
5c6a0628 842 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
dc99a3f2
BS		 843 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
844 gen_set_label(l1);
845}
846
4af984a7 847static inline void gen_op_logic_cc(TCGv dst)
dc99a3f2 848{
ba28189b
BS		 849 tcg_gen_mov_tl(cpu_cc_dst, dst);
850
ce5b3c3d 851 gen_cc_clear_icc();
ba28189b 852 gen_cc_NZ_icc(cpu_cc_dst);
ce5b3c3d
BS		 853#ifdef TARGET_SPARC64
854 gen_cc_clear_xcc();
ba28189b 855 gen_cc_NZ_xcc(cpu_cc_dst);
ce5b3c3d 856#endif
dc99a3f2
BS		 857}
858
19f329ad
BS		 859// 1
860static inline void gen_op_eval_ba(TCGv dst)
861{
862 tcg_gen_movi_tl(dst, 1);
863}
864
865// Z
866static inline void gen_op_eval_be(TCGv dst, TCGv src)
867{
868 gen_mov_reg_Z(dst, src);
869}
870
871// Z | (N ^ V)
872static inline void gen_op_eval_ble(TCGv dst, TCGv src)
873{
0425bee5 874 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 875 gen_mov_reg_V(dst, src);
0425bee5
BS		 876 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
877 gen_mov_reg_Z(cpu_tmp0, src);
878 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 879}
880
881// N ^ V
882static inline void gen_op_eval_bl(TCGv dst, TCGv src)
883{
0425bee5 884 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 885 gen_mov_reg_N(dst, src);
0425bee5 886 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 887}
888
889// C | Z
890static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
891{
0425bee5 892 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 893 gen_mov_reg_C(dst, src);
0425bee5 894 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 895}
896
897// C
898static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
899{
900 gen_mov_reg_C(dst, src);
901}
902
903// V
904static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
905{
906 gen_mov_reg_V(dst, src);
907}
908
909// 0
910static inline void gen_op_eval_bn(TCGv dst)
911{
912 tcg_gen_movi_tl(dst, 0);
913}
914
915// N
916static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
917{
918 gen_mov_reg_N(dst, src);
919}
920
921// !Z
922static inline void gen_op_eval_bne(TCGv dst, TCGv src)
923{
924 gen_mov_reg_Z(dst, src);
925 tcg_gen_xori_tl(dst, dst, 0x1);
926}
927
928// !(Z | (N ^ V))
929static inline void gen_op_eval_bg(TCGv dst, TCGv src)
930{
0425bee5 931 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 932 gen_mov_reg_V(dst, src);
0425bee5
BS		 933 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
934 gen_mov_reg_Z(cpu_tmp0, src);
935 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 936 tcg_gen_xori_tl(dst, dst, 0x1);
937}
938
939// !(N ^ V)
940static inline void gen_op_eval_bge(TCGv dst, TCGv src)
941{
0425bee5 942 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 943 gen_mov_reg_N(dst, src);
0425bee5 944 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 945 tcg_gen_xori_tl(dst, dst, 0x1);
946}
947
948// !(C | Z)
949static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
950{
0425bee5 951 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 952 gen_mov_reg_C(dst, src);
0425bee5 953 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 954 tcg_gen_xori_tl(dst, dst, 0x1);
955}
956
957// !C
958static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
959{
960 gen_mov_reg_C(dst, src);
961 tcg_gen_xori_tl(dst, dst, 0x1);
962}
963
964// !N
965static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
966{
967 gen_mov_reg_N(dst, src);
968 tcg_gen_xori_tl(dst, dst, 0x1);
969}
970
971// !V
972static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
973{
974 gen_mov_reg_V(dst, src);
975 tcg_gen_xori_tl(dst, dst, 0x1);
976}
977
978/*
979 FPSR bit field FCC1 | FCC0:
980 0 =
981 1 <
982 2 >
983 3 unordered
984*/
985static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
986 unsigned int fcc_offset)
987{
8911f501 988 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 989 tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 990 tcg_gen_andi_tl(reg, reg, 0x1);
991}
992
993static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
994 unsigned int fcc_offset)
995{
8911f501 996 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 997 tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 998 tcg_gen_andi_tl(reg, reg, 0x1);
999}
1000
1001// !0: FCC0 | FCC1
1002static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1003 unsigned int fcc_offset)
1004{
19f329ad 1005 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1006 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1007 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1008}
1009
1010// 1 or 2: FCC0 ^ FCC1
1011static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1012 unsigned int fcc_offset)
1013{
19f329ad 1014 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1015 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1016 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1017}
1018
1019// 1 or 3: FCC0
1020static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1021 unsigned int fcc_offset)
1022{
1023 gen_mov_reg_FCC0(dst, src, fcc_offset);
1024}
1025
1026// 1: FCC0 & !FCC1
1027static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1028 unsigned int fcc_offset)
1029{
19f329ad 1030 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1031 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1032 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1033 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1034}
1035
1036// 2 or 3: FCC1
1037static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1038 unsigned int fcc_offset)
1039{
1040 gen_mov_reg_FCC1(dst, src, fcc_offset);
1041}
1042
1043// 2: !FCC0 & FCC1
1044static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1045 unsigned int fcc_offset)
1046{
19f329ad
BS		 1047 gen_mov_reg_FCC0(dst, src, fcc_offset);
1048 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1049 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1050 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1051}
1052
1053// 3: FCC0 & FCC1
1054static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1055 unsigned int fcc_offset)
1056{
19f329ad 1057 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1058 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1059 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1060}
1061
1062// 0: !(FCC0 | FCC1)
1063static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1064 unsigned int fcc_offset)
1065{
19f329ad 1066 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1067 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1068 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1069 tcg_gen_xori_tl(dst, dst, 0x1);
1070}
1071
1072// 0 or 3: !(FCC0 ^ FCC1)
1073static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1074 unsigned int fcc_offset)
1075{
19f329ad 1076 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1077 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1078 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1079 tcg_gen_xori_tl(dst, dst, 0x1);
1080}
1081
1082// 0 or 2: !FCC0
1083static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1084 unsigned int fcc_offset)
1085{
1086 gen_mov_reg_FCC0(dst, src, fcc_offset);
1087 tcg_gen_xori_tl(dst, dst, 0x1);
1088}
1089
1090// !1: !(FCC0 & !FCC1)
1091static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1092 unsigned int fcc_offset)
1093{
19f329ad 1094 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1095 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1096 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1097 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1098 tcg_gen_xori_tl(dst, dst, 0x1);
1099}
1100
1101// 0 or 1: !FCC1
1102static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1103 unsigned int fcc_offset)
1104{
1105 gen_mov_reg_FCC1(dst, src, fcc_offset);
1106 tcg_gen_xori_tl(dst, dst, 0x1);
1107}
1108
1109// !2: !(!FCC0 & FCC1)
1110static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1111 unsigned int fcc_offset)
1112{
19f329ad
BS		 1113 gen_mov_reg_FCC0(dst, src, fcc_offset);
1114 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1115 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1116 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1117 tcg_gen_xori_tl(dst, dst, 0x1);
1118}
1119
1120// !3: !(FCC0 & FCC1)
1121static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1122 unsigned int fcc_offset)
1123{
19f329ad 1124 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1125 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1126 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1127 tcg_gen_xori_tl(dst, dst, 0x1);
1128}
1129
46525e1f 1130static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 1131 target_ulong pc2, TCGv r_cond)
83469015
FB		 1132{
1133 int l1;
1134
1135 l1 = gen_new_label();
1136
cb63669a 1137 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1138
6e256c93 1139 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1140
1141 gen_set_label(l1);
6e256c93 1142 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1143}
1144
46525e1f 1145static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 1146 target_ulong pc2, TCGv r_cond)
83469015
FB		 1147{
1148 int l1;
1149
1150 l1 = gen_new_label();
1151
cb63669a 1152 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1153
6e256c93 1154 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 1155
1156 gen_set_label(l1);
6e256c93 1157 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 1158}
1159
19f329ad
BS		 1160static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1161 TCGv r_cond)
83469015
FB		 1162{
1163 int l1, l2;
1164
1165 l1 = gen_new_label();
1166 l2 = gen_new_label();
19f329ad 1167
cb63669a 1168 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 1169
2f5680ee 1170 tcg_gen_movi_tl(cpu_npc, npc1);
06b3e1b3 1171 tcg_gen_br(l2);
83469015
FB		 1172
1173 gen_set_label(l1);
2f5680ee 1174 tcg_gen_movi_tl(cpu_npc, npc2);
83469015
FB		 1175 gen_set_label(l2);
1176}
1177
4af984a7
BS		 1178/* call this function before using the condition register as it may
1179 have been set for a jump */
1180static inline void flush_cond(DisasContext *dc, TCGv cond)
83469015
FB		 1181{
1182 if (dc->npc == JUMP_PC) {
4af984a7 1183 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
83469015
FB		 1184 dc->npc = DYNAMIC_PC;
1185 }
1186}
1187
4af984a7 1188static inline void save_npc(DisasContext *dc, TCGv cond)
72cbca10
FB		 1189{
1190 if (dc->npc == JUMP_PC) {
4af984a7 1191 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
72cbca10
FB		 1192 dc->npc = DYNAMIC_PC;
1193 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1194 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1195 }
1196}
1197
4af984a7 1198static inline void save_state(DisasContext *dc, TCGv cond)
72cbca10 1199{
2f5680ee 1200 tcg_gen_movi_tl(cpu_pc, dc->pc);
4af984a7 1201 save_npc(dc, cond);
72cbca10
FB		 1202}
1203
4af984a7 1204static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
0bee699e
FB		 1205{
1206 if (dc->npc == JUMP_PC) {
4af984a7 1207 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
48d5c82b 1208 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1209 dc->pc = DYNAMIC_PC;
1210 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1211 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1212 dc->pc = DYNAMIC_PC;
1213 } else {
1214 dc->pc = dc->npc;
1215 }
1216}
1217
38bc628b
BS		 1218static inline void gen_op_next_insn(void)
1219{
48d5c82b
BS		 1220 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1221 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1222}
1223
19f329ad
BS		 1224static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1225{
1226 TCGv r_src;
3475187d 1227
3475187d 1228#ifdef TARGET_SPARC64
19f329ad 1229 if (cc)
dc99a3f2 1230 r_src = cpu_xcc;
19f329ad 1231 else
dc99a3f2 1232 r_src = cpu_psr;
3475187d 1233#else
dc99a3f2 1234 r_src = cpu_psr;
3475187d 1235#endif
19f329ad
BS		 1236 switch (cond) {
1237 case 0x0:
1238 gen_op_eval_bn(r_dst);
1239 break;
1240 case 0x1:
1241 gen_op_eval_be(r_dst, r_src);
1242 break;
1243 case 0x2:
1244 gen_op_eval_ble(r_dst, r_src);
1245 break;
1246 case 0x3:
1247 gen_op_eval_bl(r_dst, r_src);
1248 break;
1249 case 0x4:
1250 gen_op_eval_bleu(r_dst, r_src);
1251 break;
1252 case 0x5:
1253 gen_op_eval_bcs(r_dst, r_src);
1254 break;
1255 case 0x6:
1256 gen_op_eval_bneg(r_dst, r_src);
1257 break;
1258 case 0x7:
1259 gen_op_eval_bvs(r_dst, r_src);
1260 break;
1261 case 0x8:
1262 gen_op_eval_ba(r_dst);
1263 break;
1264 case 0x9:
1265 gen_op_eval_bne(r_dst, r_src);
1266 break;
1267 case 0xa:
1268 gen_op_eval_bg(r_dst, r_src);
1269 break;
1270 case 0xb:
1271 gen_op_eval_bge(r_dst, r_src);
1272 break;
1273 case 0xc:
1274 gen_op_eval_bgu(r_dst, r_src);
1275 break;
1276 case 0xd:
1277 gen_op_eval_bcc(r_dst, r_src);
1278 break;
1279 case 0xe:
1280 gen_op_eval_bpos(r_dst, r_src);
1281 break;
1282 case 0xf:
1283 gen_op_eval_bvc(r_dst, r_src);
1284 break;
1285 }
1286}
7a3f1944 1287
19f329ad 1288static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
e8af50a3 1289{
19f329ad
BS		 1290 unsigned int offset;
1291
19f329ad
BS		 1292 switch (cc) {
1293 default:
1294 case 0x0:
1295 offset = 0;
1296 break;
1297 case 0x1:
1298 offset = 32 - 10;
1299 break;
1300 case 0x2:
1301 offset = 34 - 10;
1302 break;
1303 case 0x3:
1304 offset = 36 - 10;
1305 break;
1306 }
1307
1308 switch (cond) {
1309 case 0x0:
1310 gen_op_eval_bn(r_dst);
1311 break;
1312 case 0x1:
87e92502 1313 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1314 break;
1315 case 0x2:
87e92502 1316 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1317 break;
1318 case 0x3:
87e92502 1319 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1320 break;
1321 case 0x4:
87e92502 1322 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1323 break;
1324 case 0x5:
87e92502 1325 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1326 break;
1327 case 0x6:
87e92502 1328 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1329 break;
1330 case 0x7:
87e92502 1331 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1332 break;
1333 case 0x8:
1334 gen_op_eval_ba(r_dst);
1335 break;
1336 case 0x9:
87e92502 1337 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1338 break;
1339 case 0xa:
87e92502 1340 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1341 break;
1342 case 0xb:
87e92502 1343 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1344 break;
1345 case 0xc:
87e92502 1346 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1347 break;
1348 case 0xd:
87e92502 1349 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1350 break;
1351 case 0xe:
87e92502 1352 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1353 break;
1354 case 0xf:
87e92502 1355 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1356 break;
1357 }
e8af50a3 1358}
00f219bf 1359
19f329ad 1360#ifdef TARGET_SPARC64
00f219bf
BS		 1361// Inverted logic
1362static const int gen_tcg_cond_reg[8] = {
1363 -1,
1364 TCG_COND_NE,
1365 TCG_COND_GT,
1366 TCG_COND_GE,
1367 -1,
1368 TCG_COND_EQ,
1369 TCG_COND_LE,
1370 TCG_COND_LT,
1371};
19f329ad 1372
4af984a7 1373static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1374{
19f329ad
BS		 1375 int l1;
1376
1377 l1 = gen_new_label();
0425bee5 1378 tcg_gen_movi_tl(r_dst, 0);
cb63669a 1379 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
19f329ad
BS		 1380 tcg_gen_movi_tl(r_dst, 1);
1381 gen_set_label(l1);
1382}
3475187d 1383#endif
cf495bcf 1384
0bee699e 1385/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1386static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1387 TCGv r_cond)
7a3f1944 1388{
cf495bcf 1389 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1390 target_ulong target = dc->pc + offset;
5fafdf24 1391
cf495bcf 1392 if (cond == 0x0) {
0f8a249a
BS		 1393 /* unconditional not taken */
1394 if (a) {
1395 dc->pc = dc->npc + 4;
1396 dc->npc = dc->pc + 4;
1397 } else {
1398 dc->pc = dc->npc;
1399 dc->npc = dc->pc + 4;
1400 }
cf495bcf 1401 } else if (cond == 0x8) {
0f8a249a
BS		 1402 /* unconditional taken */
1403 if (a) {
1404 dc->pc = target;
1405 dc->npc = dc->pc + 4;
1406 } else {
1407 dc->pc = dc->npc;
1408 dc->npc = target;
1409 }
cf495bcf 1410 } else {
4af984a7
BS		 1411 flush_cond(dc, r_cond);
1412 gen_cond(r_cond, cc, cond);
0f8a249a 1413 if (a) {
4af984a7 1414 gen_branch_a(dc, target, dc->npc, r_cond);
cf495bcf 1415 dc->is_br = 1;
0f8a249a 1416 } else {
cf495bcf 1417 dc->pc = dc->npc;
72cbca10
FB		 1418 dc->jump_pc[0] = target;
1419 dc->jump_pc[1] = dc->npc + 4;
1420 dc->npc = JUMP_PC;
0f8a249a 1421 }
cf495bcf 1422 }
7a3f1944
FB		 1423}
1424
0bee699e 1425/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1426static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1427 TCGv r_cond)
e8af50a3
FB		 1428{
1429 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1430 target_ulong target = dc->pc + offset;
1431
e8af50a3 1432 if (cond == 0x0) {
0f8a249a
BS		 1433 /* unconditional not taken */
1434 if (a) {
1435 dc->pc = dc->npc + 4;
1436 dc->npc = dc->pc + 4;
1437 } else {
1438 dc->pc = dc->npc;
1439 dc->npc = dc->pc + 4;
1440 }
e8af50a3 1441 } else if (cond == 0x8) {
0f8a249a
BS		 1442 /* unconditional taken */
1443 if (a) {
1444 dc->pc = target;
1445 dc->npc = dc->pc + 4;
1446 } else {
1447 dc->pc = dc->npc;
1448 dc->npc = target;
1449 }
e8af50a3 1450 } else {
4af984a7
BS		 1451 flush_cond(dc, r_cond);
1452 gen_fcond(r_cond, cc, cond);
0f8a249a 1453 if (a) {
4af984a7 1454 gen_branch_a(dc, target, dc->npc, r_cond);
e8af50a3 1455 dc->is_br = 1;
0f8a249a 1456 } else {
e8af50a3
FB		 1457 dc->pc = dc->npc;
1458 dc->jump_pc[0] = target;
1459 dc->jump_pc[1] = dc->npc + 4;
1460 dc->npc = JUMP_PC;
0f8a249a 1461 }
e8af50a3
FB		 1462 }
1463}
1464
3475187d
FB		 1465#ifdef TARGET_SPARC64
1466/* XXX: potentially incorrect if dynamic npc */
4af984a7
BS		 1467static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1468 TCGv r_cond, TCGv r_reg)
7a3f1944 1469{
3475187d
FB		 1470 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1471 target_ulong target = dc->pc + offset;
1472
4af984a7
BS		 1473 flush_cond(dc, r_cond);
1474 gen_cond_reg(r_cond, cond, r_reg);
3475187d 1475 if (a) {
4af984a7 1476 gen_branch_a(dc, target, dc->npc, r_cond);
0f8a249a 1477 dc->is_br = 1;
3475187d 1478 } else {
0f8a249a
BS		 1479 dc->pc = dc->npc;
1480 dc->jump_pc[0] = target;
1481 dc->jump_pc[1] = dc->npc + 4;
1482 dc->npc = JUMP_PC;
3475187d 1483 }
7a3f1944
FB		 1484}
1485
3475187d 1486static GenOpFunc * const gen_fcmps[4] = {
7e8c2b6c
BS		 1487 helper_fcmps,
1488 helper_fcmps_fcc1,
1489 helper_fcmps_fcc2,
1490 helper_fcmps_fcc3,
3475187d
FB		 1491};
1492
1493static GenOpFunc * const gen_fcmpd[4] = {
7e8c2b6c
BS		 1494 helper_fcmpd,
1495 helper_fcmpd_fcc1,
1496 helper_fcmpd_fcc2,
1497 helper_fcmpd_fcc3,
3475187d 1498};
417454b0 1499
1f587329 1500static GenOpFunc * const gen_fcmpq[4] = {
7e8c2b6c
BS		 1501 helper_fcmpq,
1502 helper_fcmpq_fcc1,
1503 helper_fcmpq_fcc2,
1504 helper_fcmpq_fcc3,
1f587329 1505};
1f587329 1506
417454b0 1507static GenOpFunc * const gen_fcmpes[4] = {
7e8c2b6c
BS		 1508 helper_fcmpes,
1509 helper_fcmpes_fcc1,
1510 helper_fcmpes_fcc2,
1511 helper_fcmpes_fcc3,
417454b0
BS		 1512};
1513
1514static GenOpFunc * const gen_fcmped[4] = {
7e8c2b6c
BS		 1515 helper_fcmped,
1516 helper_fcmped_fcc1,
1517 helper_fcmped_fcc2,
1518 helper_fcmped_fcc3,
417454b0
BS		 1519};
1520
1f587329 1521static GenOpFunc * const gen_fcmpeq[4] = {
7e8c2b6c
BS		 1522 helper_fcmpeq,
1523 helper_fcmpeq_fcc1,
1524 helper_fcmpeq_fcc2,
1525 helper_fcmpeq_fcc3,
1f587329 1526};
7e8c2b6c
BS		 1527
1528static inline void gen_op_fcmps(int fccno)
1529{
1530 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1531}
1532
1533static inline void gen_op_fcmpd(int fccno)
1534{
1535 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1536}
1537
7e8c2b6c
BS		 1538static inline void gen_op_fcmpq(int fccno)
1539{
1540 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1541}
7e8c2b6c
BS		 1542
1543static inline void gen_op_fcmpes(int fccno)
1544{
1545 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1546}
1547
1548static inline void gen_op_fcmped(int fccno)
1549{
1550 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1551}
1552
7e8c2b6c
BS		 1553static inline void gen_op_fcmpeq(int fccno)
1554{
1555 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1556}
7e8c2b6c
BS		 1557
1558#else
1559
1560static inline void gen_op_fcmps(int fccno)
1561{
1562 tcg_gen_helper_0_0(helper_fcmps);
1563}
1564
1565static inline void gen_op_fcmpd(int fccno)
1566{
1567 tcg_gen_helper_0_0(helper_fcmpd);
1568}
1569
7e8c2b6c
BS		 1570static inline void gen_op_fcmpq(int fccno)
1571{
1572 tcg_gen_helper_0_0(helper_fcmpq);
1573}
7e8c2b6c
BS		 1574
1575static inline void gen_op_fcmpes(int fccno)
1576{
1577 tcg_gen_helper_0_0(helper_fcmpes);
1578}
1579
1580static inline void gen_op_fcmped(int fccno)
1581{
1582 tcg_gen_helper_0_0(helper_fcmped);
1583}
1584
7e8c2b6c
BS		 1585static inline void gen_op_fcmpeq(int fccno)
1586{
1587 tcg_gen_helper_0_0(helper_fcmpeq);
1588}
1589#endif
1590
134d77a1
BS		 1591static inline void gen_op_fpexception_im(int fsr_flags)
1592{
2ea815ca
BS		 1593 TCGv r_const;
1594
87e92502
BS		 1595 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1596 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca
BS		 1597 r_const = tcg_const_i32(TT_FP_EXCP);
1598 tcg_gen_helper_0_1(raise_exception, r_const);
1599 tcg_temp_free(r_const);
134d77a1
BS		 1600}
1601
4af984a7 1602static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
a80dde08
FB		 1603{
1604#if !defined(CONFIG_USER_ONLY)
1605 if (!dc->fpu_enabled) {
2ea815ca
BS		 1606 TCGv r_const;
1607
4af984a7 1608 save_state(dc, r_cond);
2ea815ca
BS		 1609 r_const = tcg_const_i32(TT_NFPU_INSN);
1610 tcg_gen_helper_0_1(raise_exception, r_const);
1611 tcg_temp_free(r_const);
a80dde08
FB		 1612 dc->is_br = 1;
1613 return 1;
1614 }
1615#endif
1616 return 0;
1617}
1618
7e8c2b6c
BS		 1619static inline void gen_op_clear_ieee_excp_and_FTT(void)
1620{
87e92502 1621 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
7e8c2b6c
BS		 1622}
1623
1624static inline void gen_clear_float_exceptions(void)
1625{
1626 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1627}
1628
1a2fb1c0
BS		 1629/* asi moves */
1630#ifdef TARGET_SPARC64
0425bee5 1631static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0
BS		 1632{
1633 int asi, offset;
0425bee5 1634 TCGv r_asi;
1a2fb1c0 1635
1a2fb1c0 1636 if (IS_IMM) {
0425bee5 1637 r_asi = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1638 offset = GET_FIELD(insn, 25, 31);
0425bee5
BS		 1639 tcg_gen_addi_tl(r_addr, r_addr, offset);
1640 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1a2fb1c0
BS		 1641 } else {
1642 asi = GET_FIELD(insn, 19, 26);
0425bee5 1643 r_asi = tcg_const_i32(asi);
1a2fb1c0 1644 }
0425bee5
BS		 1645 return r_asi;
1646}
1647
77f193da
BS		 1648static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1649 int sign)
0425bee5 1650{
2ea815ca 1651 TCGv r_asi, r_size, r_sign;
0425bee5 1652
4af984a7 1653 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1654 r_size = tcg_const_i32(size);
1655 r_sign = tcg_const_i32(sign);
1656 tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1657 tcg_temp_free(r_sign);
1658 tcg_temp_free(r_size);
1659 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1660}
1661
4af984a7 1662static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1663{
2ea815ca 1664 TCGv r_asi, r_size;
1a2fb1c0 1665
4af984a7 1666 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1667 r_size = tcg_const_i32(size);
1668 tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1669 tcg_temp_free(r_size);
1670 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1671}
1672
4af984a7 1673static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1674{
2ea815ca 1675 TCGv r_asi, r_size, r_rd;
1a2fb1c0 1676
4af984a7 1677 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1678 r_size = tcg_const_i32(size);
1679 r_rd = tcg_const_i32(rd);
1680 tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1681 tcg_temp_free(r_rd);
1682 tcg_temp_free(r_size);
1683 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1684}
1685
4af984a7 1686static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 1687{
2ea815ca 1688 TCGv r_asi, r_size, r_rd;
1a2fb1c0 1689
31741a27 1690 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1691 r_size = tcg_const_i32(size);
1692 r_rd = tcg_const_i32(rd);
1693 tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1694 tcg_temp_free(r_rd);
1695 tcg_temp_free(r_size);
1696 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1697}
1698
4af984a7 1699static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 1700{
2ea815ca 1701 TCGv r_asi, r_size, r_sign;
1a2fb1c0 1702
4af984a7 1703 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1704 r_size = tcg_const_i32(4);
1705 r_sign = tcg_const_i32(0);
1706 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1707 tcg_temp_free(r_sign);
1708 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1709 tcg_temp_free(r_size);
1710 tcg_temp_free(r_asi);
8d96d209 1711 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 1712}
1713
4af984a7 1714static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1a2fb1c0 1715{
2ea815ca 1716 TCGv r_asi, r_size, r_sign;
1a2fb1c0 1717
4af984a7 1718 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1719 r_size = tcg_const_i32(8);
1720 r_sign = tcg_const_i32(0);
1721 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1722 tcg_temp_free(r_sign);
1723 tcg_temp_free(r_size);
1724 tcg_temp_free(r_asi);
4af984a7 1725 tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
8911f501 1726 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 1727 tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
0425bee5
BS		 1728}
1729
4af984a7 1730static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5 1731{
2ea815ca 1732 TCGv r_temp, r_asi, r_size;
0425bee5 1733
8d96d209 1734 r_temp = tcg_temp_new(TCG_TYPE_TL);
0425bee5 1735 gen_movl_reg_TN(rd + 1, r_temp);
4af984a7 1736 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
0425bee5 1737 r_temp);
2ea815ca 1738 tcg_temp_free(r_temp);
4af984a7 1739 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1740 r_size = tcg_const_i32(8);
1741 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1742 tcg_temp_free(r_size);
1743 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1744}
1745
77f193da
BS		 1746static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1747 int rd)
1a2fb1c0 1748{
1a2fb1c0
BS		 1749 TCGv r_val1, r_asi;
1750
ef28fd86 1751 r_val1 = tcg_temp_new(TCG_TYPE_TL);
1a2fb1c0 1752 gen_movl_reg_TN(rd, r_val1);
4af984a7
BS		 1753 r_asi = gen_get_asi(insn, addr);
1754 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
2ea815ca
BS		 1755 tcg_temp_free(r_asi);
1756 tcg_temp_free(r_val1);
1a2fb1c0
BS		 1757}
1758
77f193da
BS		 1759static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1760 int rd)
1a2fb1c0 1761{
8911f501 1762 TCGv r_asi;
1a2fb1c0 1763
8911f501 1764 gen_movl_reg_TN(rd, cpu_tmp64);
4af984a7
BS		 1765 r_asi = gen_get_asi(insn, addr);
1766 tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
2ea815ca 1767 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1768}
1769
1770#elif !defined(CONFIG_USER_ONLY)
1771
77f193da
BS		 1772static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1773 int sign)
1a2fb1c0 1774{
2ea815ca 1775 TCGv r_asi, r_size, r_sign;
1a2fb1c0 1776
2ea815ca
BS		 1777 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1778 r_size = tcg_const_i32(size);
1779 r_sign = tcg_const_i32(sign);
1780 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1781 tcg_temp_free(r_sign);
1782 tcg_temp_free(r_size);
1783 tcg_temp_free(r_asi);
4af984a7 1784 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 1785}
1786
4af984a7 1787static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1788{
2ea815ca 1789 TCGv r_asi, r_size;
1a2fb1c0 1790
4af984a7 1791 tcg_gen_extu_tl_i64(cpu_tmp64, src);
2ea815ca
BS		 1792 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1793 r_size = tcg_const_i32(size);
1794 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1795 tcg_temp_free(r_size);
1796 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1797}
1798
4af984a7 1799static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 1800{
2ea815ca 1801 TCGv r_asi, r_size, r_sign;
1a2fb1c0 1802
2ea815ca
BS		 1803 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1804 r_size = tcg_const_i32(4);
1805 r_sign = tcg_const_i32(0);
1806 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1807 tcg_temp_free(r_sign);
1808 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1809 tcg_temp_free(r_size);
1810 tcg_temp_free(r_asi);
8d96d209 1811 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1a2fb1c0
BS		 1812}
1813
4af984a7 1814static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1a2fb1c0 1815{
2ea815ca 1816 TCGv r_asi, r_size, r_sign;
1a2fb1c0 1817
2ea815ca
BS		 1818 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1819 r_size = tcg_const_i32(8);
1820 r_sign = tcg_const_i32(0);
1821 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1822 tcg_temp_free(r_sign);
1823 tcg_temp_free(r_size);
1824 tcg_temp_free(r_asi);
4af984a7 1825 tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
8911f501 1826 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4af984a7 1827 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
0425bee5
BS		 1828}
1829
4af984a7 1830static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
0425bee5 1831{
2ea815ca 1832 TCGv r_temp, r_asi, r_size;
0425bee5 1833
8d96d209 1834 r_temp = tcg_temp_new(TCG_TYPE_TL);
0425bee5 1835 gen_movl_reg_TN(rd + 1, r_temp);
4af984a7 1836 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
2ea815ca
BS		 1837 tcg_temp_free(r_temp);
1838 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1839 r_size = tcg_const_i32(8);
1840 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1841 tcg_temp_free(r_size);
1842 tcg_temp_free(r_asi);
1a2fb1c0
BS		 1843}
1844#endif
1845
1846#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4af984a7 1847static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 1848{
2ea815ca 1849 TCGv r_val, r_asi, r_size;
1a2fb1c0 1850
4af984a7 1851 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 1852
2ea815ca
BS		 1853 r_val = tcg_const_i64(0xffULL);
1854 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1855 r_size = tcg_const_i32(1);
1856 tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1857 tcg_temp_free(r_size);
1858 tcg_temp_free(r_asi);
1859 tcg_temp_free(r_val);
1a2fb1c0
BS		 1860}
1861#endif
1862
9322a4bf
BS		 1863static inline TCGv get_src1(unsigned int insn, TCGv def)
1864{
1865 TCGv r_rs1 = def;
1866 unsigned int rs1;
1867
1868 rs1 = GET_FIELD(insn, 13, 17);
1869 if (rs1 == 0)
5c6a0628 1870 r_rs1 = tcg_const_tl(0); // XXX how to free?
9322a4bf 1871 else if (rs1 < 8)
5c6a0628 1872 r_rs1 = cpu_gregs[rs1];
9322a4bf
BS		 1873 else
1874 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1875 return r_rs1;
1876}
1877
a49d9390
BS		 1878static inline TCGv get_src2(unsigned int insn, TCGv def)
1879{
1880 TCGv r_rs2 = def;
1881 unsigned int rs2;
1882
1883 if (IS_IMM) { /* immediate */
1884 rs2 = GET_FIELDs(insn, 19, 31);
2ea815ca 1885 r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
a49d9390
BS		 1886 } else { /* register */
1887 rs2 = GET_FIELD(insn, 27, 31);
1888 if (rs2 == 0)
2ea815ca 1889 r_rs2 = tcg_const_tl(0); // XXX how to free?
a49d9390
BS		 1890 else if (rs2 < 8)
1891 r_rs2 = cpu_gregs[rs2];
1892 else
1893 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1894 }
1895 return r_rs2;
1896}
1897
64a88d5d
BS		 1898#define CHECK_IU_FEATURE(dc, FEATURE) \
1899 if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1900 goto illegal_insn;
1901#define CHECK_FPU_FEATURE(dc, FEATURE) \
1902 if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
1903 goto nfpu_insn;
1904
0bee699e 1905/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1906static void disas_sparc_insn(DisasContext * dc)
1907{
1908 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1909
a8c768c0
BS		 1910 if (unlikely(loglevel & CPU_LOG_TB_OP))
1911 tcg_gen_debug_insn_start(dc->pc);
0fa85d43 1912 insn = ldl_code(dc->pc);
cf495bcf 1913 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1914
cf495bcf 1915 rd = GET_FIELD(insn, 2, 6);
6ae20372 1916
5c6a0628
BS		 1917 cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1918 cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
6ae20372 1919
cf495bcf 1920 switch (opc) {
0f8a249a
BS		 1921 case 0: /* branches/sethi */
1922 {
1923 unsigned int xop = GET_FIELD(insn, 7, 9);
1924 int32_t target;
1925 switch (xop) {
3475187d 1926#ifdef TARGET_SPARC64
0f8a249a
BS		 1927 case 0x1: /* V9 BPcc */
1928 {
1929 int cc;
1930
1931 target = GET_FIELD_SP(insn, 0, 18);
1932 target = sign_extend(target, 18);
1933 target <<= 2;
1934 cc = GET_FIELD_SP(insn, 20, 21);
1935 if (cc == 0)
6ae20372 1936 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a 1937 else if (cc == 2)
6ae20372 1938 do_branch(dc, target, insn, 1, cpu_cond);
0f8a249a
BS		 1939 else
1940 goto illegal_insn;
1941 goto jmp_insn;
1942 }
1943 case 0x3: /* V9 BPr */
1944 {
1945 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1946 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1947 target = sign_extend(target, 16);
1948 target <<= 2;
9322a4bf 1949 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372 1950 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
0f8a249a
BS		 1951 goto jmp_insn;
1952 }
1953 case 0x5: /* V9 FBPcc */
1954 {
1955 int cc = GET_FIELD_SP(insn, 20, 21);
6ae20372 1956 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 1957 goto jmp_insn;
0f8a249a
BS		 1958 target = GET_FIELD_SP(insn, 0, 18);
1959 target = sign_extend(target, 19);
1960 target <<= 2;
6ae20372 1961 do_fbranch(dc, target, insn, cc, cpu_cond);
0f8a249a
BS		 1962 goto jmp_insn;
1963 }
a4d17f19 1964#else
0f8a249a
BS		 1965 case 0x7: /* CBN+x */
1966 {
1967 goto ncp_insn;
1968 }
1969#endif
1970 case 0x2: /* BN+x */
1971 {
1972 target = GET_FIELD(insn, 10, 31);
1973 target = sign_extend(target, 22);
1974 target <<= 2;
6ae20372 1975 do_branch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 1976 goto jmp_insn;
1977 }
1978 case 0x6: /* FBN+x */
1979 {
6ae20372 1980 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 1981 goto jmp_insn;
0f8a249a
BS		 1982 target = GET_FIELD(insn, 10, 31);
1983 target = sign_extend(target, 22);
1984 target <<= 2;
6ae20372 1985 do_fbranch(dc, target, insn, 0, cpu_cond);
0f8a249a
BS		 1986 goto jmp_insn;
1987 }
1988 case 0x4: /* SETHI */
0f8a249a 1989 if (rd) { // nop
0f8a249a 1990 uint32_t value = GET_FIELD(insn, 10, 31);
2ea815ca
BS		 1991 TCGv r_const;
1992
1993 r_const = tcg_const_tl(value << 10);
1994 gen_movl_TN_reg(rd, r_const);
1995 tcg_temp_free(r_const);
0f8a249a 1996 }
0f8a249a
BS		 1997 break;
1998 case 0x0: /* UNIMPL */
1999 default:
3475187d 2000 goto illegal_insn;
0f8a249a
BS		 2001 }
2002 break;
2003 }
2004 break;
cf495bcf 2005 case 1:
0f8a249a
BS		 2006 /*CALL*/ {
2007 target_long target = GET_FIELDs(insn, 2, 31) << 2;
2ea815ca 2008 TCGv r_const;
cf495bcf 2009
2ea815ca
BS		 2010 r_const = tcg_const_tl(dc->pc);
2011 gen_movl_TN_reg(15, r_const);
2012 tcg_temp_free(r_const);
0f8a249a 2013 target += dc->pc;
6ae20372 2014 gen_mov_pc_npc(dc, cpu_cond);
0f8a249a
BS		 2015 dc->npc = target;
2016 }
2017 goto jmp_insn;
2018 case 2: /* FPU & Logical Operations */
2019 {
2020 unsigned int xop = GET_FIELD(insn, 7, 12);
2021 if (xop == 0x3a) { /* generate trap */
cf495bcf 2022 int cond;
3475187d 2023
9322a4bf 2024 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 2025 if (IS_IMM) {
2026 rs2 = GET_FIELD(insn, 25, 31);
6ae20372 2027 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
cf495bcf
FB		 2028 } else {
2029 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 2030 if (rs2 != 0) {
6ae20372
BS		 2031 gen_movl_reg_TN(rs2, cpu_src2);
2032 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 2033 } else
2034 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 2035 }
cf495bcf
FB		 2036 cond = GET_FIELD(insn, 3, 6);
2037 if (cond == 0x8) {
6ae20372
BS		 2038 save_state(dc, cpu_cond);
2039 tcg_gen_helper_0_1(helper_trap, cpu_dst);
af7bf89b 2040 } else if (cond != 0) {
748b9d8e 2041 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
3475187d 2042#ifdef TARGET_SPARC64
0f8a249a
BS		 2043 /* V9 icc/xcc */
2044 int cc = GET_FIELD_SP(insn, 11, 12);
748b9d8e 2045
6ae20372 2046 save_state(dc, cpu_cond);
0f8a249a 2047 if (cc == 0)
748b9d8e 2048 gen_cond(r_cond, 0, cond);
0f8a249a 2049 else if (cc == 2)
748b9d8e 2050 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 2051 else
2052 goto illegal_insn;
3475187d 2053#else
6ae20372 2054 save_state(dc, cpu_cond);
748b9d8e 2055 gen_cond(r_cond, 0, cond);
3475187d 2056#endif
6ae20372 2057 tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2ea815ca 2058 tcg_temp_free(r_cond);
cf495bcf 2059 }
a80dde08 2060 gen_op_next_insn();
57fec1fe 2061 tcg_gen_exit_tb(0);
a80dde08
FB		 2062 dc->is_br = 1;
2063 goto jmp_insn;
cf495bcf
FB		 2064 } else if (xop == 0x28) {
2065 rs1 = GET_FIELD(insn, 13, 17);
2066 switch(rs1) {
2067 case 0: /* rdy */
65fe7b09
BS		 2068#ifndef TARGET_SPARC64
2069 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2070 manual, rdy on the microSPARC
2071 II */
2072 case 0x0f: /* stbar in the SPARCv8 manual,
2073 rdy on the microSPARC II */
2074 case 0x10 ... 0x1f: /* implementation-dependent in the
2075 SPARCv8 manual, rdy on the
2076 microSPARC II */
2077#endif
ece43b8d 2078 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
77f193da 2079 offsetof(CPUSPARCState, y));
ece43b8d 2080 gen_movl_TN_reg(rd, cpu_tmp0);
cf495bcf 2081 break;
3475187d 2082#ifdef TARGET_SPARC64
0f8a249a 2083 case 0x2: /* V9 rdccr */
6ae20372
BS		 2084 tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2085 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2086 break;
0f8a249a 2087 case 0x3: /* V9 rdasi */
77f193da
BS		 2088 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2089 offsetof(CPUSPARCState, asi));
6ae20372
BS		 2090 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2091 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2092 break;
0f8a249a 2093 case 0x4: /* V9 rdtick */
ccd4a219
BS		 2094 {
2095 TCGv r_tickptr;
2096
2097 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2098 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2099 offsetof(CPUState, tick));
6ae20372 2100 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2101 r_tickptr);
2ea815ca 2102 tcg_temp_free(r_tickptr);
6ae20372 2103 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2104 }
3475187d 2105 break;
0f8a249a 2106 case 0x5: /* V9 rdpc */
2ea815ca
BS		 2107 {
2108 TCGv r_const;
2109
2110 r_const = tcg_const_tl(dc->pc);
2111 gen_movl_TN_reg(rd, r_const);
2112 tcg_temp_free(r_const);
2113 }
0f8a249a
BS		 2114 break;
2115 case 0x6: /* V9 rdfprs */
77f193da
BS		 2116 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2117 offsetof(CPUSPARCState, fprs));
6ae20372
BS		 2118 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2119 gen_movl_TN_reg(rd, cpu_dst);
3475187d 2120 break;
65fe7b09
BS		 2121 case 0xf: /* V9 membar */
2122 break; /* no effect */
0f8a249a 2123 case 0x13: /* Graphics Status */
6ae20372 2124 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 2125 goto jmp_insn;
ece43b8d 2126 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
77f193da 2127 offsetof(CPUSPARCState, gsr));
ece43b8d 2128 gen_movl_TN_reg(rd, cpu_tmp0);
725cb90b 2129 break;
0f8a249a 2130 case 0x17: /* Tick compare */
ece43b8d 2131 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
77f193da 2132 offsetof(CPUSPARCState, tick_cmpr));
ece43b8d 2133 gen_movl_TN_reg(rd, cpu_tmp0);
83469015 2134 break;
0f8a249a 2135 case 0x18: /* System tick */
ccd4a219
BS		 2136 {
2137 TCGv r_tickptr;
2138
2139 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2140 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2141 offsetof(CPUState, stick));
6ae20372 2142 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
ccd4a219 2143 r_tickptr);
2ea815ca 2144 tcg_temp_free(r_tickptr);
6ae20372 2145 gen_movl_TN_reg(rd, cpu_dst);
ccd4a219 2146 }
83469015 2147 break;
0f8a249a 2148 case 0x19: /* System tick compare */
ece43b8d 2149 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
77f193da 2150 offsetof(CPUSPARCState, stick_cmpr));
ece43b8d 2151 gen_movl_TN_reg(rd, cpu_tmp0);
83469015 2152 break;
0f8a249a
BS		 2153 case 0x10: /* Performance Control */
2154 case 0x11: /* Performance Instrumentation Counter */
2155 case 0x12: /* Dispatch Control */
2156 case 0x14: /* Softint set, WO */
2157 case 0x15: /* Softint clear, WO */
2158 case 0x16: /* Softint write */
3475187d
FB		 2159#endif
2160 default:
cf495bcf
FB		 2161 goto illegal_insn;
2162 }
e8af50a3 2163#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2164 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2165#ifndef TARGET_SPARC64
0f8a249a
BS		 2166 if (!supervisor(dc))
2167 goto priv_insn;
6ae20372 2168 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
e9ebed4d
BS		 2169#else
2170 if (!hypervisor(dc))
2171 goto priv_insn;
2172 rs1 = GET_FIELD(insn, 13, 17);
2173 switch (rs1) {
2174 case 0: // hpstate
2175 // gen_op_rdhpstate();
2176 break;
2177 case 1: // htstate
2178 // gen_op_rdhtstate();
2179 break;
2180 case 3: // hintp
77f193da
BS		 2181 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2182 offsetof(CPUSPARCState, hintp));
6ae20372 2183 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2184 break;
2185 case 5: // htba
77f193da
BS		 2186 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2187 offsetof(CPUSPARCState, htba));
6ae20372 2188 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2189 break;
2190 case 6: // hver
77f193da
BS		 2191 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2192 offsetof(CPUSPARCState, hver));
6ae20372 2193 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
e9ebed4d
BS		 2194 break;
2195 case 31: // hstick_cmpr
6ae20372 2196 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
77f193da
BS		 2197 tcg_gen_st_i32(cpu_tmp32, cpu_env,
2198 offsetof(CPUSPARCState, hstick_cmpr));
e9ebed4d
BS		 2199 break;
2200 default:
2201 goto illegal_insn;
2202 }
2203#endif
6ae20372 2204 gen_movl_TN_reg(rd, cpu_dst);
e8af50a3 2205 break;
3475187d 2206 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 2207 if (!supervisor(dc))
2208 goto priv_insn;
3475187d
FB		 2209#ifdef TARGET_SPARC64
2210 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2211 switch (rs1) {
2212 case 0: // tpc
375ee38b
BS		 2213 {
2214 TCGv r_tsptr;
2215
2216 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2217 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2218 offsetof(CPUState, tsptr));
ece43b8d 2219 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2220 offsetof(trap_state, tpc));
2ea815ca 2221 tcg_temp_free(r_tsptr);
375ee38b 2222 }
0f8a249a
BS		 2223 break;
2224 case 1: // tnpc
375ee38b
BS		 2225 {
2226 TCGv r_tsptr;
2227
2228 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2229 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2230 offsetof(CPUState, tsptr));
ece43b8d 2231 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2232 offsetof(trap_state, tnpc));
2ea815ca 2233 tcg_temp_free(r_tsptr);
375ee38b 2234 }
0f8a249a
BS		 2235 break;
2236 case 2: // tstate
375ee38b
BS		 2237 {
2238 TCGv r_tsptr;
2239
2240 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2241 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2242 offsetof(CPUState, tsptr));
ece43b8d 2243 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2244 offsetof(trap_state, tstate));
2ea815ca 2245 tcg_temp_free(r_tsptr);
375ee38b 2246 }
0f8a249a
BS		 2247 break;
2248 case 3: // tt
375ee38b
BS		 2249 {
2250 TCGv r_tsptr;
2251
2252 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2253 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2254 offsetof(CPUState, tsptr));
ece43b8d 2255 tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
375ee38b 2256 offsetof(trap_state, tt));
2ea815ca 2257 tcg_temp_free(r_tsptr);
375ee38b 2258 }
0f8a249a
BS		 2259 break;
2260 case 4: // tick
ccd4a219
BS		 2261 {
2262 TCGv r_tickptr;
2263
2264 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2265 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2266 offsetof(CPUState, tick));
ece43b8d 2267 tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
ccd4a219 2268 r_tickptr);
ece43b8d 2269 gen_movl_TN_reg(rd, cpu_tmp0);
2ea815ca 2270 tcg_temp_free(r_tickptr);
ccd4a219 2271 }
0f8a249a
BS		 2272 break;
2273 case 5: // tba
ece43b8d 2274 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
77f193da 2275 offsetof(CPUSPARCState, tbr));
0f8a249a
BS		 2276 break;
2277 case 6: // pstate
77f193da
BS		 2278 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2279 offsetof(CPUSPARCState, pstate));
ece43b8d 2280 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2281 break;
2282 case 7: // tl
77f193da
BS		 2283 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2284 offsetof(CPUSPARCState, tl));
ece43b8d 2285 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2286 break;
2287 case 8: // pil
77f193da
BS		 2288 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2289 offsetof(CPUSPARCState, psrpil));
ece43b8d 2290 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2291 break;
2292 case 9: // cwp
ece43b8d 2293 tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
0f8a249a
BS		 2294 break;
2295 case 10: // cansave
77f193da
BS		 2296 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2297 offsetof(CPUSPARCState, cansave));
ece43b8d 2298 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2299 break;
2300 case 11: // canrestore
77f193da
BS		 2301 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2302 offsetof(CPUSPARCState, canrestore));
ece43b8d 2303 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2304 break;
2305 case 12: // cleanwin
77f193da
BS		 2306 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2307 offsetof(CPUSPARCState, cleanwin));
ece43b8d 2308 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2309 break;
2310 case 13: // otherwin
77f193da
BS		 2311 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2312 offsetof(CPUSPARCState, otherwin));
ece43b8d 2313 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a
BS		 2314 break;
2315 case 14: // wstate
77f193da
BS		 2316 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2317 offsetof(CPUSPARCState, wstate));
ece43b8d 2318 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
0f8a249a 2319 break;
e9ebed4d 2320 case 16: // UA2005 gl
77f193da
BS		 2321 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2322 offsetof(CPUSPARCState, gl));
ece43b8d 2323 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
e9ebed4d
BS		 2324 break;
2325 case 26: // UA2005 strand status
2326 if (!hypervisor(dc))
2327 goto priv_insn;
77f193da
BS		 2328 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2329 offsetof(CPUSPARCState, ssr));
ece43b8d 2330 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
e9ebed4d 2331 break;
0f8a249a 2332 case 31: // ver
ece43b8d 2333 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
77f193da 2334 offsetof(CPUSPARCState, version));
0f8a249a
BS		 2335 break;
2336 case 15: // fq
2337 default:
2338 goto illegal_insn;
2339 }
3475187d 2340#else
77f193da
BS		 2341 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2342 offsetof(CPUSPARCState, wim));
ece43b8d 2343 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
3475187d 2344#endif
ece43b8d 2345 gen_movl_TN_reg(rd, cpu_tmp0);
e8af50a3 2346 break;
3475187d
FB		 2347 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2348#ifdef TARGET_SPARC64
72a9747b 2349 tcg_gen_helper_0_0(helper_flushw);
3475187d 2350#else
0f8a249a
BS		 2351 if (!supervisor(dc))
2352 goto priv_insn;
ece43b8d
BS		 2353 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2354 gen_movl_TN_reg(rd, cpu_tmp0);
3475187d 2355#endif
e8af50a3
FB		 2356 break;
2357#endif
0f8a249a 2358 } else if (xop == 0x34) { /* FPU Operations */
6ae20372 2359 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2360 goto jmp_insn;
0f8a249a 2361 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2362 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2363 rs2 = GET_FIELD(insn, 27, 31);
2364 xop = GET_FIELD(insn, 18, 26);
2365 switch (xop) {
2366 case 0x1: /* fmovs */
2367 gen_op_load_fpr_FT0(rs2);
2368 gen_op_store_FT0_fpr(rd);
2369 break;
2370 case 0x5: /* fnegs */
2371 gen_op_load_fpr_FT1(rs2);
44e7757c 2372 tcg_gen_helper_0_0(helper_fnegs);
0f8a249a
BS		 2373 gen_op_store_FT0_fpr(rd);
2374 break;
2375 case 0x9: /* fabss */
2376 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2377 tcg_gen_helper_0_0(helper_fabss);
0f8a249a
BS		 2378 gen_op_store_FT0_fpr(rd);
2379 break;
2380 case 0x29: /* fsqrts */
64a88d5d 2381 CHECK_FPU_FEATURE(dc, FSQRT);
0f8a249a 2382 gen_op_load_fpr_FT1(rs2);
7e8c2b6c
BS		 2383 gen_clear_float_exceptions();
2384 tcg_gen_helper_0_0(helper_fsqrts);
2385 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2386 gen_op_store_FT0_fpr(rd);
2387 break;
2388 case 0x2a: /* fsqrtd */
64a88d5d 2389 CHECK_FPU_FEATURE(dc, FSQRT);
0f8a249a 2390 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c
BS		 2391 gen_clear_float_exceptions();
2392 tcg_gen_helper_0_0(helper_fsqrtd);
2393 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2394 gen_op_store_DT0_fpr(DFPREG(rd));
2395 break;
2396 case 0x2b: /* fsqrtq */
64a88d5d 2397 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2398 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c
BS		 2399 gen_clear_float_exceptions();
2400 tcg_gen_helper_0_0(helper_fsqrtq);
2401 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2402 gen_op_store_QT0_fpr(QFPREG(rd));
2403 break;
0f8a249a
BS		 2404 case 0x41:
2405 gen_op_load_fpr_FT0(rs1);
2406 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2407 gen_clear_float_exceptions();
44e7757c 2408 tcg_gen_helper_0_0(helper_fadds);
7e8c2b6c 2409 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2410 gen_op_store_FT0_fpr(rd);
2411 break;
2412 case 0x42:
2413 gen_op_load_fpr_DT0(DFPREG(rs1));
2414 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2415 gen_clear_float_exceptions();
44e7757c 2416 tcg_gen_helper_0_0(helper_faddd);
7e8c2b6c 2417 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2418 gen_op_store_DT0_fpr(DFPREG(rd));
2419 break;
2420 case 0x43: /* faddq */
64a88d5d 2421 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2422 gen_op_load_fpr_QT0(QFPREG(rs1));
2423 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2424 gen_clear_float_exceptions();
44e7757c 2425 tcg_gen_helper_0_0(helper_faddq);
7e8c2b6c 2426 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2427 gen_op_store_QT0_fpr(QFPREG(rd));
2428 break;
0f8a249a
BS		 2429 case 0x45:
2430 gen_op_load_fpr_FT0(rs1);
2431 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2432 gen_clear_float_exceptions();
44e7757c 2433 tcg_gen_helper_0_0(helper_fsubs);
7e8c2b6c 2434 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2435 gen_op_store_FT0_fpr(rd);
2436 break;
2437 case 0x46:
2438 gen_op_load_fpr_DT0(DFPREG(rs1));
2439 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2440 gen_clear_float_exceptions();
44e7757c 2441 tcg_gen_helper_0_0(helper_fsubd);
7e8c2b6c 2442 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2443 gen_op_store_DT0_fpr(DFPREG(rd));
2444 break;
2445 case 0x47: /* fsubq */
64a88d5d 2446 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2447 gen_op_load_fpr_QT0(QFPREG(rs1));
2448 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2449 gen_clear_float_exceptions();
44e7757c 2450 tcg_gen_helper_0_0(helper_fsubq);
7e8c2b6c 2451 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2452 gen_op_store_QT0_fpr(QFPREG(rd));
2453 break;
64a88d5d
BS		 2454 case 0x49: /* fmuls */
2455 CHECK_FPU_FEATURE(dc, FMUL);
0f8a249a
BS		 2456 gen_op_load_fpr_FT0(rs1);
2457 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2458 gen_clear_float_exceptions();
44e7757c 2459 tcg_gen_helper_0_0(helper_fmuls);
7e8c2b6c 2460 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2461 gen_op_store_FT0_fpr(rd);
2462 break;
64a88d5d
BS		 2463 case 0x4a: /* fmuld */
2464 CHECK_FPU_FEATURE(dc, FMUL);
0f8a249a
BS		 2465 gen_op_load_fpr_DT0(DFPREG(rs1));
2466 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2467 gen_clear_float_exceptions();
44e7757c 2468 tcg_gen_helper_0_0(helper_fmuld);
7e8c2b6c 2469 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2382dc6b 2470 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2471 break;
2472 case 0x4b: /* fmulq */
64a88d5d
BS		 2473 CHECK_FPU_FEATURE(dc, FLOAT128);
2474 CHECK_FPU_FEATURE(dc, FMUL);
1f587329
BS		 2475 gen_op_load_fpr_QT0(QFPREG(rs1));
2476 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2477 gen_clear_float_exceptions();
44e7757c 2478 tcg_gen_helper_0_0(helper_fmulq);
7e8c2b6c 2479 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2480 gen_op_store_QT0_fpr(QFPREG(rd));
2481 break;
0f8a249a
BS		 2482 case 0x4d:
2483 gen_op_load_fpr_FT0(rs1);
2484 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2485 gen_clear_float_exceptions();
44e7757c 2486 tcg_gen_helper_0_0(helper_fdivs);
7e8c2b6c 2487 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2488 gen_op_store_FT0_fpr(rd);
2489 break;
2490 case 0x4e:
2491 gen_op_load_fpr_DT0(DFPREG(rs1));
2492 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2493 gen_clear_float_exceptions();
44e7757c 2494 tcg_gen_helper_0_0(helper_fdivd);
7e8c2b6c 2495 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2496 gen_op_store_DT0_fpr(DFPREG(rd));
2497 break;
2498 case 0x4f: /* fdivq */
64a88d5d 2499 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2500 gen_op_load_fpr_QT0(QFPREG(rs1));
2501 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2502 gen_clear_float_exceptions();
44e7757c 2503 tcg_gen_helper_0_0(helper_fdivq);
7e8c2b6c 2504 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2505 gen_op_store_QT0_fpr(QFPREG(rd));
2506 break;
0f8a249a 2507 case 0x69:
e30b4678 2508 CHECK_FPU_FEATURE(dc, FSMULD);
0f8a249a
BS		 2509 gen_op_load_fpr_FT0(rs1);
2510 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2511 gen_clear_float_exceptions();
44e7757c 2512 tcg_gen_helper_0_0(helper_fsmuld);
7e8c2b6c 2513 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2514 gen_op_store_DT0_fpr(DFPREG(rd));
2515 break;
2516 case 0x6e: /* fdmulq */
64a88d5d 2517 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2518 gen_op_load_fpr_DT0(DFPREG(rs1));
2519 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2520 gen_clear_float_exceptions();
44e7757c 2521 tcg_gen_helper_0_0(helper_fdmulq);
7e8c2b6c 2522 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2523 gen_op_store_QT0_fpr(QFPREG(rd));
2524 break;
0f8a249a
BS		 2525 case 0xc4:
2526 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2527 gen_clear_float_exceptions();
44e7757c 2528 tcg_gen_helper_0_0(helper_fitos);
7e8c2b6c 2529 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2530 gen_op_store_FT0_fpr(rd);
2531 break;
2532 case 0xc6:
2533 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2534 gen_clear_float_exceptions();
44e7757c 2535 tcg_gen_helper_0_0(helper_fdtos);
7e8c2b6c 2536 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2537 gen_op_store_FT0_fpr(rd);
2538 break;
2539 case 0xc7: /* fqtos */
64a88d5d 2540 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2541 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2542 gen_clear_float_exceptions();
44e7757c 2543 tcg_gen_helper_0_0(helper_fqtos);
7e8c2b6c 2544 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2545 gen_op_store_FT0_fpr(rd);
2546 break;
0f8a249a
BS		 2547 case 0xc8:
2548 gen_op_load_fpr_FT1(rs2);
44e7757c 2549 tcg_gen_helper_0_0(helper_fitod);
0f8a249a
BS		 2550 gen_op_store_DT0_fpr(DFPREG(rd));
2551 break;
2552 case 0xc9:
2553 gen_op_load_fpr_FT1(rs2);
44e7757c 2554 tcg_gen_helper_0_0(helper_fstod);
0f8a249a
BS		 2555 gen_op_store_DT0_fpr(DFPREG(rd));
2556 break;
2557 case 0xcb: /* fqtod */
64a88d5d 2558 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2559 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2560 gen_clear_float_exceptions();
44e7757c 2561 tcg_gen_helper_0_0(helper_fqtod);
7e8c2b6c 2562 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2563 gen_op_store_DT0_fpr(DFPREG(rd));
2564 break;
0f8a249a 2565 case 0xcc: /* fitoq */
64a88d5d 2566 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2567 gen_op_load_fpr_FT1(rs2);
44e7757c 2568 tcg_gen_helper_0_0(helper_fitoq);
1f587329
BS		 2569 gen_op_store_QT0_fpr(QFPREG(rd));
2570 break;
0f8a249a 2571 case 0xcd: /* fstoq */
64a88d5d 2572 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2573 gen_op_load_fpr_FT1(rs2);
44e7757c 2574 tcg_gen_helper_0_0(helper_fstoq);
1f587329
BS		 2575 gen_op_store_QT0_fpr(QFPREG(rd));
2576 break;
0f8a249a 2577 case 0xce: /* fdtoq */
64a88d5d 2578 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2579 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 2580 tcg_gen_helper_0_0(helper_fdtoq);
1f587329
BS		 2581 gen_op_store_QT0_fpr(QFPREG(rd));
2582 break;
0f8a249a
BS		 2583 case 0xd1:
2584 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2585 gen_clear_float_exceptions();
44e7757c 2586 tcg_gen_helper_0_0(helper_fstoi);
7e8c2b6c 2587 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2588 gen_op_store_FT0_fpr(rd);
2589 break;
2590 case 0xd2:
2382dc6b 2591 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2592 gen_clear_float_exceptions();
44e7757c 2593 tcg_gen_helper_0_0(helper_fdtoi);
7e8c2b6c 2594 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2595 gen_op_store_FT0_fpr(rd);
2596 break;
2597 case 0xd3: /* fqtoi */
64a88d5d 2598 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2599 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2600 gen_clear_float_exceptions();
44e7757c 2601 tcg_gen_helper_0_0(helper_fqtoi);
7e8c2b6c 2602 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2603 gen_op_store_FT0_fpr(rd);
2604 break;
3475187d 2605#ifdef TARGET_SPARC64
0f8a249a
BS		 2606 case 0x2: /* V9 fmovd */
2607 gen_op_load_fpr_DT0(DFPREG(rs2));
2608 gen_op_store_DT0_fpr(DFPREG(rd));
2609 break;
1f587329 2610 case 0x3: /* V9 fmovq */
64a88d5d 2611 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2612 gen_op_load_fpr_QT0(QFPREG(rs2));
2613 gen_op_store_QT0_fpr(QFPREG(rd));
2614 break;
0f8a249a
BS		 2615 case 0x6: /* V9 fnegd */
2616 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 2617 tcg_gen_helper_0_0(helper_fnegd);
0f8a249a
BS		 2618 gen_op_store_DT0_fpr(DFPREG(rd));
2619 break;
1f587329 2620 case 0x7: /* V9 fnegq */
64a88d5d 2621 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2622 gen_op_load_fpr_QT1(QFPREG(rs2));
44e7757c 2623 tcg_gen_helper_0_0(helper_fnegq);
1f587329
BS		 2624 gen_op_store_QT0_fpr(QFPREG(rd));
2625 break;
0f8a249a
BS		 2626 case 0xa: /* V9 fabsd */
2627 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2628 tcg_gen_helper_0_0(helper_fabsd);
0f8a249a
BS		 2629 gen_op_store_DT0_fpr(DFPREG(rd));
2630 break;
1f587329 2631 case 0xb: /* V9 fabsq */
64a88d5d 2632 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2633 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2634 tcg_gen_helper_0_0(helper_fabsq);
1f587329
BS		 2635 gen_op_store_QT0_fpr(QFPREG(rd));
2636 break;
0f8a249a
BS		 2637 case 0x81: /* V9 fstox */
2638 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2639 gen_clear_float_exceptions();
44e7757c 2640 tcg_gen_helper_0_0(helper_fstox);
7e8c2b6c 2641 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2642 gen_op_store_DT0_fpr(DFPREG(rd));
2643 break;
2644 case 0x82: /* V9 fdtox */
2645 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2646 gen_clear_float_exceptions();
44e7757c 2647 tcg_gen_helper_0_0(helper_fdtox);
7e8c2b6c 2648 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2649 gen_op_store_DT0_fpr(DFPREG(rd));
2650 break;
1f587329 2651 case 0x83: /* V9 fqtox */
64a88d5d 2652 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2653 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2654 gen_clear_float_exceptions();
44e7757c 2655 tcg_gen_helper_0_0(helper_fqtox);
7e8c2b6c 2656 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2657 gen_op_store_DT0_fpr(DFPREG(rd));
2658 break;
0f8a249a
BS		 2659 case 0x84: /* V9 fxtos */
2660 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2661 gen_clear_float_exceptions();
44e7757c 2662 tcg_gen_helper_0_0(helper_fxtos);
7e8c2b6c 2663 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2664 gen_op_store_FT0_fpr(rd);
2665 break;
2666 case 0x88: /* V9 fxtod */
2667 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2668 gen_clear_float_exceptions();
44e7757c 2669 tcg_gen_helper_0_0(helper_fxtod);
7e8c2b6c 2670 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2671 gen_op_store_DT0_fpr(DFPREG(rd));
2672 break;
0f8a249a 2673 case 0x8c: /* V9 fxtoq */
64a88d5d 2674 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329 2675 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2676 gen_clear_float_exceptions();
44e7757c 2677 tcg_gen_helper_0_0(helper_fxtoq);
7e8c2b6c 2678 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2679 gen_op_store_QT0_fpr(QFPREG(rd));
2680 break;
0f8a249a
BS		 2681#endif
2682 default:
2683 goto illegal_insn;
2684 }
2685 } else if (xop == 0x35) { /* FPU Operations */
3475187d 2686#ifdef TARGET_SPARC64
0f8a249a 2687 int cond;
3475187d 2688#endif
6ae20372 2689 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 2690 goto jmp_insn;
0f8a249a 2691 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 2692 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2693 rs2 = GET_FIELD(insn, 27, 31);
2694 xop = GET_FIELD(insn, 18, 26);
3475187d 2695#ifdef TARGET_SPARC64
0f8a249a 2696 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 2697 int l1;
2698
2699 l1 = gen_new_label();
0f8a249a 2700 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2701 cpu_src1 = get_src1(insn, cpu_src1);
cb63669a
PB		 2702 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2703 0, l1);
19f329ad 2704 gen_op_load_fpr_FT0(rs2);
0f8a249a 2705 gen_op_store_FT0_fpr(rd);
dcf24905 2706 gen_set_label(l1);
0f8a249a
BS		 2707 break;
2708 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 2709 int l1;
2710
2711 l1 = gen_new_label();
0f8a249a 2712 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2713 cpu_src1 = get_src1(insn, cpu_src1);
cb63669a
PB		 2714 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2715 0, l1);
19f329ad 2716 gen_op_load_fpr_DT0(DFPREG(rs2));
2382dc6b 2717 gen_op_store_DT0_fpr(DFPREG(rd));
dcf24905 2718 gen_set_label(l1);
0f8a249a
BS		 2719 break;
2720 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
dcf24905
BS		 2721 int l1;
2722
64a88d5d 2723 CHECK_FPU_FEATURE(dc, FLOAT128);
dcf24905 2724 l1 = gen_new_label();
1f587329 2725 cond = GET_FIELD_SP(insn, 14, 17);
9322a4bf 2726 cpu_src1 = get_src1(insn, cpu_src1);
cb63669a
PB		 2727 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2728 0, l1);
19f329ad 2729 gen_op_load_fpr_QT0(QFPREG(rs2));
1f587329 2730 gen_op_store_QT0_fpr(QFPREG(rd));
dcf24905 2731 gen_set_label(l1);
1f587329 2732 break;
0f8a249a
BS		 2733 }
2734#endif
2735 switch (xop) {
3475187d 2736#ifdef TARGET_SPARC64
19f329ad
BS		 2737#define FMOVCC(size_FDQ, fcc) \
2738 { \
0425bee5 2739 TCGv r_cond; \
19f329ad
BS		 2740 int l1; \
2741 \
2742 l1 = gen_new_label(); \
19f329ad 2743 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2744 cond = GET_FIELD_SP(insn, 14, 17); \
2745 gen_fcond(r_cond, fcc, cond); \
cb63669a
PB		 2746 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2747 0, l1); \
77f193da
BS		 2748 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2749 (glue(size_FDQ, FPREG(rs2))); \
2750 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2751 (glue(size_FDQ, FPREG(rd))); \
19f329ad 2752 gen_set_label(l1); \
2ea815ca 2753 tcg_temp_free(r_cond); \
19f329ad 2754 }
0f8a249a 2755 case 0x001: /* V9 fmovscc %fcc0 */
19f329ad 2756 FMOVCC(F, 0);
0f8a249a
BS		 2757 break;
2758 case 0x002: /* V9 fmovdcc %fcc0 */
19f329ad 2759 FMOVCC(D, 0);
0f8a249a
BS		 2760 break;
2761 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 2762 CHECK_FPU_FEATURE(dc, FLOAT128);
19f329ad 2763 FMOVCC(Q, 0);
1f587329 2764 break;
0f8a249a 2765 case 0x041: /* V9 fmovscc %fcc1 */
19f329ad 2766 FMOVCC(F, 1);
0f8a249a
BS		 2767 break;
2768 case 0x042: /* V9 fmovdcc %fcc1 */
19f329ad 2769 FMOVCC(D, 1);
0f8a249a
BS		 2770 break;
2771 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 2772 CHECK_FPU_FEATURE(dc, FLOAT128);
19f329ad 2773 FMOVCC(Q, 1);
1f587329 2774 break;
0f8a249a 2775 case 0x081: /* V9 fmovscc %fcc2 */
19f329ad 2776 FMOVCC(F, 2);
0f8a249a
BS		 2777 break;
2778 case 0x082: /* V9 fmovdcc %fcc2 */
19f329ad 2779 FMOVCC(D, 2);
0f8a249a
BS		 2780 break;
2781 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 2782 CHECK_FPU_FEATURE(dc, FLOAT128);
19f329ad 2783 FMOVCC(Q, 2);
1f587329 2784 break;
0f8a249a 2785 case 0x0c1: /* V9 fmovscc %fcc3 */
19f329ad 2786 FMOVCC(F, 3);
0f8a249a
BS		 2787 break;
2788 case 0x0c2: /* V9 fmovdcc %fcc3 */
19f329ad 2789 FMOVCC(D, 3);
0f8a249a
BS		 2790 break;
2791 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 2792 CHECK_FPU_FEATURE(dc, FLOAT128);
19f329ad 2793 FMOVCC(Q, 3);
1f587329 2794 break;
19f329ad
BS		 2795#undef FMOVCC
2796#define FMOVCC(size_FDQ, icc) \
2797 { \
0425bee5 2798 TCGv r_cond; \
19f329ad
BS		 2799 int l1; \
2800 \
2801 l1 = gen_new_label(); \
19f329ad 2802 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2803 cond = GET_FIELD_SP(insn, 14, 17); \
2804 gen_cond(r_cond, icc, cond); \
cb63669a
PB		 2805 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2806 0, l1); \
77f193da
BS		 2807 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2808 (glue(size_FDQ, FPREG(rs2))); \
2809 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2810 (glue(size_FDQ, FPREG(rd))); \
19f329ad 2811 gen_set_label(l1); \
2ea815ca 2812 tcg_temp_free(r_cond); \
19f329ad
BS		 2813 }
2814
0f8a249a 2815 case 0x101: /* V9 fmovscc %icc */
19f329ad 2816 FMOVCC(F, 0);
0f8a249a
BS		 2817 break;
2818 case 0x102: /* V9 fmovdcc %icc */
19f329ad 2819 FMOVCC(D, 0);
0f8a249a 2820 case 0x103: /* V9 fmovqcc %icc */
64a88d5d
BS		 2821 CHECK_FPU_FEATURE(dc, FLOAT128);
2822 FMOVCC(Q, 0);
1f587329 2823 break;
0f8a249a 2824 case 0x181: /* V9 fmovscc %xcc */
19f329ad 2825 FMOVCC(F, 1);
0f8a249a
BS		 2826 break;
2827 case 0x182: /* V9 fmovdcc %xcc */
19f329ad 2828 FMOVCC(D, 1);
0f8a249a
BS		 2829 break;
2830 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 2831 CHECK_FPU_FEATURE(dc, FLOAT128);
19f329ad 2832 FMOVCC(Q, 1);
1f587329 2833 break;
19f329ad 2834#undef FMOVCC
1f587329
BS		 2835#endif
2836 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 2837 gen_op_load_fpr_FT0(rs1);
2838 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2839 gen_op_fcmps(rd & 3);
0f8a249a 2840 break;
1f587329 2841 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 2842 gen_op_load_fpr_DT0(DFPREG(rs1));
2843 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2844 gen_op_fcmpd(rd & 3);
0f8a249a 2845 break;
1f587329 2846 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 2847 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2848 gen_op_load_fpr_QT0(QFPREG(rs1));
2849 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2850 gen_op_fcmpq(rd & 3);
1f587329 2851 break;
0f8a249a
BS		 2852 case 0x55: /* fcmpes, V9 %fcc */
2853 gen_op_load_fpr_FT0(rs1);
2854 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2855 gen_op_fcmpes(rd & 3);
0f8a249a
BS		 2856 break;
2857 case 0x56: /* fcmped, V9 %fcc */
2858 gen_op_load_fpr_DT0(DFPREG(rs1));
2859 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2860 gen_op_fcmped(rd & 3);
0f8a249a 2861 break;
1f587329 2862 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 2863 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 2864 gen_op_load_fpr_QT0(QFPREG(rs1));
2865 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2866 gen_op_fcmpeq(rd & 3);
1f587329 2867 break;
0f8a249a
BS		 2868 default:
2869 goto illegal_insn;
2870 }
0f8a249a
BS		 2871 } else if (xop == 0x2) {
2872 // clr/mov shortcut
e80cfcfc
FB		 2873
2874 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2875 if (rs1 == 0) {
1a2fb1c0 2876 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a 2877 if (IS_IMM) { /* immediate */
2ea815ca
BS		 2878 TCGv r_const;
2879
0f8a249a 2880 rs2 = GET_FIELDs(insn, 19, 31);
2ea815ca
BS		 2881 r_const = tcg_const_tl((int)rs2);
2882 gen_movl_TN_reg(rd, r_const);
2883 tcg_temp_free(r_const);
0f8a249a
BS		 2884 } else { /* register */
2885 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2886 gen_movl_reg_TN(rs2, cpu_dst);
9c6c6662 2887 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2888 }
0f8a249a 2889 } else {
9322a4bf 2890 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2891 if (IS_IMM) { /* immediate */
0f8a249a 2892 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 2893 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
9c6c6662 2894 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 2895 } else { /* register */
2896 // or x, %g0, y -> mov T1, x; mov y, T1
2897 rs2 = GET_FIELD(insn, 27, 31);
2898 if (rs2 != 0) {
6ae20372
BS		 2899 gen_movl_reg_TN(rs2, cpu_src2);
2900 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
9c6c6662 2901 gen_movl_TN_reg(rd, cpu_dst);
6f551262 2902 } else
9c6c6662 2903 gen_movl_TN_reg(rd, cpu_src1);
0f8a249a 2904 }
0f8a249a 2905 }
83469015 2906#ifdef TARGET_SPARC64
0f8a249a 2907 } else if (xop == 0x25) { /* sll, V9 sllx */
9322a4bf 2908 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2909 if (IS_IMM) { /* immediate */
83469015 2910 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2911 if (insn & (1 << 12)) {
6ae20372 2912 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2913 } else {
6ae20372
BS		 2914 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2915 tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2916 }
0f8a249a 2917 } else { /* register */
83469015 2918 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2919 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2920 if (insn & (1 << 12)) {
6ae20372
BS		 2921 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2922 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2923 } else {
6ae20372
BS		 2924 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2925 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2926 tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2927 }
83469015 2928 }
6ae20372 2929 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2930 } else if (xop == 0x26) { /* srl, V9 srlx */
9322a4bf 2931 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2932 if (IS_IMM) { /* immediate */
83469015 2933 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2934 if (insn & (1 << 12)) {
6ae20372 2935 tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2936 } else {
6ae20372
BS		 2937 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2938 tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2939 }
0f8a249a 2940 } else { /* register */
83469015 2941 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2942 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2943 if (insn & (1 << 12)) {
6ae20372
BS		 2944 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2945 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2946 } else {
6ae20372
BS		 2947 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2948 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2949 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2950 }
83469015 2951 }
6ae20372 2952 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 2953 } else if (xop == 0x27) { /* sra, V9 srax */
9322a4bf 2954 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a 2955 if (IS_IMM) { /* immediate */
83469015 2956 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0 2957 if (insn & (1 << 12)) {
6ae20372 2958 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
1a2fb1c0 2959 } else {
6ae20372
BS		 2960 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2961 tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2962 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
1a2fb1c0 2963 }
0f8a249a 2964 } else { /* register */
83469015 2965 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 2966 gen_movl_reg_TN(rs2, cpu_src2);
1a2fb1c0 2967 if (insn & (1 << 12)) {
6ae20372
BS		 2968 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2969 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 2970 } else {
6ae20372
BS		 2971 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2972 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2973 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 2974 }
83469015 2975 }
6ae20372 2976 gen_movl_TN_reg(rd, cpu_dst);
e80cfcfc 2977#endif
fcc72045 2978 } else if (xop < 0x36) {
9322a4bf 2979 cpu_src1 = get_src1(insn, cpu_src1);
a49d9390 2980 cpu_src2 = get_src2(insn, cpu_src2);
cf495bcf
FB		 2981 if (xop < 0x20) {
2982 switch (xop & ~0x10) {
2983 case 0x0:
2984 if (xop & 0x10)
6ae20372 2985 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2986 else
6ae20372 2987 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf
FB		 2988 break;
2989 case 0x1:
6ae20372 2990 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 2991 if (xop & 0x10)
6ae20372 2992 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 2993 break;
2994 case 0x2:
6ae20372 2995 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
0f8a249a 2996 if (xop & 0x10)
6ae20372 2997 gen_op_logic_cc(cpu_dst);
0f8a249a 2998 break;
cf495bcf 2999 case 0x3:
6ae20372 3000 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3001 if (xop & 0x10)
6ae20372 3002 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 3003 break;
3004 case 0x4:
3005 if (xop & 0x10)
6ae20372 3006 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3007 else
6ae20372 3008 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
cf495bcf
FB		 3009 break;
3010 case 0x5:
6ae20372
BS		 3011 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3012 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 3013 if (xop & 0x10)
6ae20372 3014 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 3015 break;
3016 case 0x6:
6ae20372
BS		 3017 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 3019 if (xop & 0x10)
6ae20372 3020 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 3021 break;
3022 case 0x7:
6ae20372
BS		 3023 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
cf495bcf 3025 if (xop & 0x10)
6ae20372 3026 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 3027 break;
3028 case 0x8:
cf495bcf 3029 if (xop & 0x10)
6ae20372 3030 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
38bc628b 3031 else {
dc99a3f2 3032 gen_mov_reg_C(cpu_tmp0, cpu_psr);
6ae20372
BS		 3033 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3034 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
38bc628b 3035 }
cf495bcf 3036 break;
ded3ab80 3037#ifdef TARGET_SPARC64
0f8a249a 3038 case 0x9: /* V9 mulx */
6ae20372 3039 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3040 break;
3041#endif
cf495bcf 3042 case 0xa:
64a88d5d 3043 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3044 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3045 if (xop & 0x10)
6ae20372 3046 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 3047 break;
3048 case 0xb:
64a88d5d 3049 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3050 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
cf495bcf 3051 if (xop & 0x10)
6ae20372 3052 gen_op_logic_cc(cpu_dst);
cf495bcf
FB		 3053 break;
3054 case 0xc:
cf495bcf 3055 if (xop & 0x10)
6ae20372 3056 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
38bc628b 3057 else {
dc99a3f2 3058 gen_mov_reg_C(cpu_tmp0, cpu_psr);
6ae20372
BS		 3059 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3060 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
38bc628b 3061 }
cf495bcf 3062 break;
ded3ab80 3063#ifdef TARGET_SPARC64
0f8a249a 3064 case 0xd: /* V9 udivx */
07bf2857
BS		 3065 tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3066 tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3067 gen_trap_ifdivzero_tl(cpu_cc_src2);
3068 tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
ded3ab80
PB		 3069 break;
3070#endif
cf495bcf 3071 case 0xe:
64a88d5d 3072 CHECK_IU_FEATURE(dc, DIV);
77f193da
BS		 3073 tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3074 cpu_src2);
cf495bcf 3075 if (xop & 0x10)
6ae20372 3076 gen_op_div_cc(cpu_dst);
cf495bcf
FB		 3077 break;
3078 case 0xf:
64a88d5d 3079 CHECK_IU_FEATURE(dc, DIV);
77f193da
BS		 3080 tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3081 cpu_src2);
cf495bcf 3082 if (xop & 0x10)
6ae20372 3083 gen_op_div_cc(cpu_dst);
cf495bcf
FB		 3084 break;
3085 default:
3086 goto illegal_insn;
3087 }
6ae20372 3088 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf
FB		 3089 } else {
3090 switch (xop) {
0f8a249a 3091 case 0x20: /* taddcc */
6ae20372
BS		 3092 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3093 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3094 break;
3095 case 0x21: /* tsubcc */
6ae20372
BS		 3096 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3097 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3098 break;
3099 case 0x22: /* taddcctv */
6ae20372
BS		 3100 save_state(dc, cpu_cond);
3101 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3102 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3103 break;
3104 case 0x23: /* tsubcctv */
6ae20372
BS		 3105 save_state(dc, cpu_cond);
3106 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3107 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 3108 break;
cf495bcf 3109 case 0x24: /* mulscc */
6ae20372
BS		 3110 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3111 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3112 break;
83469015 3113#ifndef TARGET_SPARC64
0f8a249a 3114 case 0x25: /* sll */
e35298cd
BS		 3115 if (IS_IMM) { /* immediate */
3116 rs2 = GET_FIELDs(insn, 20, 31);
3117 tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3118 } else { /* register */
3119 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3120 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3121 }
6ae20372 3122 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3123 break;
83469015 3124 case 0x26: /* srl */
e35298cd
BS		 3125 if (IS_IMM) { /* immediate */
3126 rs2 = GET_FIELDs(insn, 20, 31);
3127 tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3128 } else { /* register */
3129 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3130 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3131 }
6ae20372 3132 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3133 break;
83469015 3134 case 0x27: /* sra */
e35298cd
BS		 3135 if (IS_IMM) { /* immediate */
3136 rs2 = GET_FIELDs(insn, 20, 31);
3137 tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3138 } else { /* register */
3139 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3140 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3141 }
6ae20372 3142 gen_movl_TN_reg(rd, cpu_dst);
cf495bcf 3143 break;
83469015 3144#endif
cf495bcf
FB		 3145 case 0x30:
3146 {
cf495bcf 3147 switch(rd) {
3475187d 3148 case 0: /* wry */
ece43b8d
BS		 3149 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3150 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da 3151 offsetof(CPUSPARCState, y));
cf495bcf 3152 break;
65fe7b09
BS		 3153#ifndef TARGET_SPARC64
3154 case 0x01 ... 0x0f: /* undefined in the
3155 SPARCv8 manual, nop
3156 on the microSPARC
3157 II */
3158 case 0x10 ... 0x1f: /* implementation-dependent
3159 in the SPARCv8
3160 manual, nop on the
3161 microSPARC II */
3162 break;
3163#else
0f8a249a 3164 case 0x2: /* V9 wrccr */
6ae20372
BS		 3165 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3166 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
0f8a249a
BS		 3167 break;
3168 case 0x3: /* V9 wrasi */
6ae20372
BS		 3169 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3170 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
77f193da
BS		 3171 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3172 offsetof(CPUSPARCState, asi));
0f8a249a
BS		 3173 break;
3174 case 0x6: /* V9 wrfprs */
6ae20372
BS		 3175 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3176 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
77f193da
BS		 3177 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3178 offsetof(CPUSPARCState, fprs));
6ae20372 3179 save_state(dc, cpu_cond);
3299908c 3180 gen_op_next_insn();
57fec1fe 3181 tcg_gen_exit_tb(0);
3299908c 3182 dc->is_br = 1;
0f8a249a
BS		 3183 break;
3184 case 0xf: /* V9 sir, nop if user */
3475187d 3185#if !defined(CONFIG_USER_ONLY)
0f8a249a 3186 if (supervisor(dc))
1a2fb1c0 3187 ; // XXX
3475187d 3188#endif
0f8a249a
BS		 3189 break;
3190 case 0x13: /* Graphics Status */
6ae20372 3191 if (gen_trap_ifnofpu(dc, cpu_cond))
725cb90b 3192 goto jmp_insn;
ece43b8d
BS		 3193 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3194 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da 3195 offsetof(CPUSPARCState, gsr));
0f8a249a
BS		 3196 break;
3197 case 0x17: /* Tick compare */
83469015 3198#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3199 if (!supervisor(dc))
3200 goto illegal_insn;
83469015 3201#endif
ccd4a219
BS		 3202 {
3203 TCGv r_tickptr;
3204
ece43b8d 3205 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3206 cpu_src2);
ece43b8d 3207 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da
BS		 3208 offsetof(CPUSPARCState,
3209 tick_cmpr));
ccd4a219
BS		 3210 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3211 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3212 offsetof(CPUState, tick));
3213 tcg_gen_helper_0_2(helper_tick_set_limit,
ece43b8d 3214 r_tickptr, cpu_tmp0);
2ea815ca 3215 tcg_temp_free(r_tickptr);
ccd4a219 3216 }
0f8a249a
BS		 3217 break;
3218 case 0x18: /* System tick */
83469015 3219#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3220 if (!supervisor(dc))
3221 goto illegal_insn;
83469015 3222#endif
ccd4a219
BS		 3223 {
3224 TCGv r_tickptr;
3225
6ae20372
BS		 3226 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3227 cpu_src2);
ccd4a219
BS		 3228 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3229 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3230 offsetof(CPUState, stick));
3231 tcg_gen_helper_0_2(helper_tick_set_count,
6ae20372 3232 r_tickptr, cpu_dst);
2ea815ca 3233 tcg_temp_free(r_tickptr);
ccd4a219 3234 }
0f8a249a
BS		 3235 break;
3236 case 0x19: /* System tick compare */
83469015 3237#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3238 if (!supervisor(dc))
3239 goto illegal_insn;
3475187d 3240#endif
ccd4a219
BS		 3241 {
3242 TCGv r_tickptr;
3243
ece43b8d 3244 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3245 cpu_src2);
ece43b8d 3246 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da
BS		 3247 offsetof(CPUSPARCState,
3248 stick_cmpr));
ccd4a219
BS		 3249 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3250 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3251 offsetof(CPUState, stick));
3252 tcg_gen_helper_0_2(helper_tick_set_limit,
ece43b8d 3253 r_tickptr, cpu_tmp0);
2ea815ca 3254 tcg_temp_free(r_tickptr);
ccd4a219 3255 }
0f8a249a 3256 break;
83469015 3257
0f8a249a 3258 case 0x10: /* Performance Control */
77f193da
BS		 3259 case 0x11: /* Performance Instrumentation
3260 Counter */
0f8a249a
BS		 3261 case 0x12: /* Dispatch Control */
3262 case 0x14: /* Softint set */
3263 case 0x15: /* Softint clear */
3264 case 0x16: /* Softint write */
83469015 3265#endif
3475187d 3266 default:
cf495bcf
FB		 3267 goto illegal_insn;
3268 }
3269 }
3270 break;
e8af50a3 3271#if !defined(CONFIG_USER_ONLY)
af7bf89b 3272 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3273 {
0f8a249a
BS		 3274 if (!supervisor(dc))
3275 goto priv_insn;
3475187d 3276#ifdef TARGET_SPARC64
0f8a249a
BS		 3277 switch (rd) {
3278 case 0:
72a9747b 3279 tcg_gen_helper_0_0(helper_saved);
0f8a249a
BS		 3280 break;
3281 case 1:
72a9747b 3282 tcg_gen_helper_0_0(helper_restored);
0f8a249a 3283 break;
e9ebed4d
BS		 3284 case 2: /* UA2005 allclean */
3285 case 3: /* UA2005 otherw */
3286 case 4: /* UA2005 normalw */
3287 case 5: /* UA2005 invalw */
3288 // XXX
0f8a249a 3289 default:
3475187d
FB		 3290 goto illegal_insn;
3291 }
3292#else
6ae20372
BS		 3293 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3294 tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3295 save_state(dc, cpu_cond);
9e61bde5 3296 gen_op_next_insn();
57fec1fe 3297 tcg_gen_exit_tb(0);
0f8a249a 3298 dc->is_br = 1;
3475187d 3299#endif
e8af50a3
FB		 3300 }
3301 break;
af7bf89b 3302 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3303 {
0f8a249a
BS		 3304 if (!supervisor(dc))
3305 goto priv_insn;
ece43b8d 3306 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3307#ifdef TARGET_SPARC64
0f8a249a
BS		 3308 switch (rd) {
3309 case 0: // tpc
375ee38b
BS		 3310 {
3311 TCGv r_tsptr;
3312
3313 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3314 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3315 offsetof(CPUState, tsptr));
ece43b8d 3316 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3317 offsetof(trap_state, tpc));
2ea815ca 3318 tcg_temp_free(r_tsptr);
375ee38b 3319 }
0f8a249a
BS		 3320 break;
3321 case 1: // tnpc
375ee38b
BS		 3322 {
3323 TCGv r_tsptr;
3324
3325 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3326 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3327 offsetof(CPUState, tsptr));
ece43b8d 3328 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3329 offsetof(trap_state, tnpc));
2ea815ca 3330 tcg_temp_free(r_tsptr);
375ee38b 3331 }
0f8a249a
BS		 3332 break;
3333 case 2: // tstate
375ee38b
BS		 3334 {
3335 TCGv r_tsptr;
3336
3337 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3338 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3339 offsetof(CPUState, tsptr));
ece43b8d 3340 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3341 offsetof(trap_state,
3342 tstate));
2ea815ca 3343 tcg_temp_free(r_tsptr);
375ee38b 3344 }
0f8a249a
BS		 3345 break;
3346 case 3: // tt
375ee38b
BS		 3347 {
3348 TCGv r_tsptr;
3349
3350 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3351 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3352 offsetof(CPUState, tsptr));
ece43b8d 3353 tcg_gen_st_i32(cpu_tmp0, r_tsptr,
375ee38b 3354 offsetof(trap_state, tt));
2ea815ca 3355 tcg_temp_free(r_tsptr);
375ee38b 3356 }
0f8a249a
BS		 3357 break;
3358 case 4: // tick
ccd4a219
BS		 3359 {
3360 TCGv r_tickptr;
3361
3362 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3363 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3364 offsetof(CPUState, tick));
3365 tcg_gen_helper_0_2(helper_tick_set_count,
ece43b8d 3366 r_tickptr, cpu_tmp0);
2ea815ca 3367 tcg_temp_free(r_tickptr);
ccd4a219 3368 }
0f8a249a
BS		 3369 break;
3370 case 5: // tba
ece43b8d 3371 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da 3372 offsetof(CPUSPARCState, tbr));
0f8a249a
BS		 3373 break;
3374 case 6: // pstate
6ae20372 3375 save_state(dc, cpu_cond);
ece43b8d 3376 tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
ded3ab80 3377 gen_op_next_insn();
57fec1fe 3378 tcg_gen_exit_tb(0);
ded3ab80 3379 dc->is_br = 1;
0f8a249a
BS		 3380 break;
3381 case 7: // tl
ece43b8d 3382 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3383 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3384 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3385 break;
3386 case 8: // pil
ece43b8d 3387 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3388 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3389 offsetof(CPUSPARCState,
3390 psrpil));
0f8a249a
BS		 3391 break;
3392 case 9: // cwp
ece43b8d 3393 tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
0f8a249a
BS		 3394 break;
3395 case 10: // cansave
ece43b8d 3396 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3397 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3398 offsetof(CPUSPARCState,
3399 cansave));
0f8a249a
BS		 3400 break;
3401 case 11: // canrestore
ece43b8d 3402 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3403 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3404 offsetof(CPUSPARCState,
3405 canrestore));
0f8a249a
BS		 3406 break;
3407 case 12: // cleanwin
ece43b8d 3408 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3409 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3410 offsetof(CPUSPARCState,
3411 cleanwin));
0f8a249a
BS		 3412 break;
3413 case 13: // otherwin
ece43b8d 3414 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3415 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3416 offsetof(CPUSPARCState,
3417 otherwin));
0f8a249a
BS		 3418 break;
3419 case 14: // wstate
ece43b8d 3420 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3421 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3422 offsetof(CPUSPARCState,
3423 wstate));
0f8a249a 3424 break;
e9ebed4d 3425 case 16: // UA2005 gl
ece43b8d 3426 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3427 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3428 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3429 break;
3430 case 26: // UA2005 strand status
3431 if (!hypervisor(dc))
3432 goto priv_insn;
ece43b8d 3433 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3434 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3435 offsetof(CPUSPARCState, ssr));
e9ebed4d 3436 break;
0f8a249a
BS		 3437 default:
3438 goto illegal_insn;
3439 }
3475187d 3440#else
ece43b8d 3441 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3442 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3443 offsetof(CPUSPARCState, wim));
3475187d 3444#endif
e8af50a3
FB		 3445 }
3446 break;
e9ebed4d 3447 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3448 {
e9ebed4d 3449#ifndef TARGET_SPARC64
0f8a249a
BS		 3450 if (!supervisor(dc))
3451 goto priv_insn;
ece43b8d
BS		 3452 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3453 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da 3454 offsetof(CPUSPARCState, tbr));
e9ebed4d
BS		 3455#else
3456 if (!hypervisor(dc))
3457 goto priv_insn;
ece43b8d 3458 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3459 switch (rd) {
3460 case 0: // hpstate
3461 // XXX gen_op_wrhpstate();
6ae20372 3462 save_state(dc, cpu_cond);
e9ebed4d 3463 gen_op_next_insn();
57fec1fe 3464 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3465 dc->is_br = 1;
3466 break;
3467 case 1: // htstate
3468 // XXX gen_op_wrhtstate();
3469 break;
3470 case 3: // hintp
ece43b8d 3471 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3472 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3473 offsetof(CPUSPARCState, hintp));
e9ebed4d
BS		 3474 break;
3475 case 5: // htba
ece43b8d 3476 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
77f193da
BS		 3477 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3478 offsetof(CPUSPARCState, htba));
e9ebed4d
BS		 3479 break;
3480 case 31: // hstick_cmpr
ccd4a219
BS		 3481 {
3482 TCGv r_tickptr;
3483
ece43b8d 3484 tcg_gen_st_tl(cpu_tmp0, cpu_env,
77f193da
BS		 3485 offsetof(CPUSPARCState,
3486 hstick_cmpr));
ccd4a219
BS		 3487 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3488 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3489 offsetof(CPUState, hstick));
3490 tcg_gen_helper_0_2(helper_tick_set_limit,
ece43b8d 3491 r_tickptr, cpu_tmp0);
2ea815ca 3492 tcg_temp_free(r_tickptr);
ccd4a219 3493 }
e9ebed4d
BS		 3494 break;
3495 case 6: // hver readonly
3496 default:
3497 goto illegal_insn;
3498 }
3499#endif
e8af50a3
FB		 3500 }
3501 break;
3502#endif
3475187d 3503#ifdef TARGET_SPARC64
0f8a249a
BS		 3504 case 0x2c: /* V9 movcc */
3505 {
3506 int cc = GET_FIELD_SP(insn, 11, 12);
3507 int cond = GET_FIELD_SP(insn, 14, 17);
748b9d8e 3508 TCGv r_cond;
00f219bf
BS		 3509 int l1;
3510
748b9d8e 3511 r_cond = tcg_temp_new(TCG_TYPE_TL);
0f8a249a
BS		 3512 if (insn & (1 << 18)) {
3513 if (cc == 0)
748b9d8e 3514 gen_cond(r_cond, 0, cond);
0f8a249a 3515 else if (cc == 2)
748b9d8e 3516 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 3517 else
3518 goto illegal_insn;
3519 } else {
748b9d8e 3520 gen_fcond(r_cond, cc, cond);
0f8a249a 3521 }
00f219bf
BS		 3522
3523 l1 = gen_new_label();
3524
cb63669a 3525 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
00f219bf 3526 if (IS_IMM) { /* immediate */
2ea815ca
BS		 3527 TCGv r_const;
3528
00f219bf 3529 rs2 = GET_FIELD_SPs(insn, 0, 10);
2ea815ca
BS		 3530 r_const = tcg_const_tl((int)rs2);
3531 gen_movl_TN_reg(rd, r_const);
3532 tcg_temp_free(r_const);
00f219bf
BS		 3533 } else {
3534 rs2 = GET_FIELD_SP(insn, 0, 4);
9c6c6662
BS		 3535 gen_movl_reg_TN(rs2, cpu_tmp0);
3536 gen_movl_TN_reg(rd, cpu_tmp0);
00f219bf 3537 }
00f219bf 3538 gen_set_label(l1);
2ea815ca 3539 tcg_temp_free(r_cond);
0f8a249a
BS		 3540 break;
3541 }
3542 case 0x2d: /* V9 sdivx */
6ae20372
BS		 3543 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3544 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3545 break;
3546 case 0x2e: /* V9 popc */
3547 {
a49d9390 3548 cpu_src2 = get_src2(insn, cpu_src2);
6ae20372
BS		 3549 tcg_gen_helper_1_1(helper_popc, cpu_dst,
3550 cpu_src2);
3551 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 3552 }
3553 case 0x2f: /* V9 movr */
3554 {
3555 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 3556 int l1;
3557
9322a4bf 3558 cpu_src1 = get_src1(insn, cpu_src1);
00f219bf
BS		 3559
3560 l1 = gen_new_label();
3561
cb63669a
PB		 3562 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3563 cpu_src1, 0, l1);
0f8a249a 3564 if (IS_IMM) { /* immediate */
2ea815ca
BS		 3565 TCGv r_const;
3566
0f8a249a 3567 rs2 = GET_FIELD_SPs(insn, 0, 9);
2ea815ca
BS		 3568 r_const = tcg_const_tl((int)rs2);
3569 gen_movl_TN_reg(rd, r_const);
3570 tcg_temp_free(r_const);
00f219bf 3571 } else {
0f8a249a 3572 rs2 = GET_FIELD_SP(insn, 0, 4);
9c6c6662
BS		 3573 gen_movl_reg_TN(rs2, cpu_tmp0);
3574 gen_movl_TN_reg(rd, cpu_tmp0);
0f8a249a 3575 }
00f219bf 3576 gen_set_label(l1);
0f8a249a
BS		 3577 break;
3578 }
3579#endif
3580 default:
3581 goto illegal_insn;
3582 }
3583 }
3299908c
BS		 3584 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3585#ifdef TARGET_SPARC64
3586 int opf = GET_FIELD_SP(insn, 5, 13);
3587 rs1 = GET_FIELD(insn, 13, 17);
3588 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 3589 if (gen_trap_ifnofpu(dc, cpu_cond))
e9ebed4d 3590 goto jmp_insn;
3299908c
BS		 3591
3592 switch (opf) {
e9ebed4d
BS		 3593 case 0x000: /* VIS I edge8cc */
3594 case 0x001: /* VIS II edge8n */
3595 case 0x002: /* VIS I edge8lcc */
3596 case 0x003: /* VIS II edge8ln */
3597 case 0x004: /* VIS I edge16cc */
3598 case 0x005: /* VIS II edge16n */
3599 case 0x006: /* VIS I edge16lcc */
3600 case 0x007: /* VIS II edge16ln */
3601 case 0x008: /* VIS I edge32cc */
3602 case 0x009: /* VIS II edge32n */
3603 case 0x00a: /* VIS I edge32lcc */
3604 case 0x00b: /* VIS II edge32ln */
3605 // XXX
3606 goto illegal_insn;
3607 case 0x010: /* VIS I array8 */
64a88d5d 3608 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 3609 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3610 gen_movl_reg_TN(rs2, cpu_src2);
3611 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3612 cpu_src2);
3613 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 3614 break;
3615 case 0x012: /* VIS I array16 */
64a88d5d 3616 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 3617 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3618 gen_movl_reg_TN(rs2, cpu_src2);
3619 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3620 cpu_src2);
3621 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3622 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d
BS		 3623 break;
3624 case 0x014: /* VIS I array32 */
64a88d5d 3625 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 3626 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3627 gen_movl_reg_TN(rs2, cpu_src2);
3628 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3629 cpu_src2);
3630 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3631 gen_movl_TN_reg(rd, cpu_dst);
e9ebed4d 3632 break;
3299908c 3633 case 0x018: /* VIS I alignaddr */
64a88d5d 3634 CHECK_FPU_FEATURE(dc, VIS1);
9322a4bf 3635 cpu_src1 = get_src1(insn, cpu_src1);
6ae20372
BS		 3636 gen_movl_reg_TN(rs2, cpu_src2);
3637 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3638 cpu_src2);
3639 gen_movl_TN_reg(rd, cpu_dst);
3299908c 3640 break;
e9ebed4d 3641 case 0x019: /* VIS II bmask */
3299908c 3642 case 0x01a: /* VIS I alignaddrl */
3299908c 3643 // XXX
e9ebed4d
BS		 3644 goto illegal_insn;
3645 case 0x020: /* VIS I fcmple16 */
64a88d5d 3646 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3647 gen_op_load_fpr_DT0(DFPREG(rs1));
3648 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3649 tcg_gen_helper_0_0(helper_fcmple16);
2382dc6b 3650 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3651 break;
3652 case 0x022: /* VIS I fcmpne16 */
64a88d5d 3653 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3654 gen_op_load_fpr_DT0(DFPREG(rs1));
3655 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3656 tcg_gen_helper_0_0(helper_fcmpne16);
2382dc6b 3657 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3658 break;
e9ebed4d 3659 case 0x024: /* VIS I fcmple32 */
64a88d5d 3660 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3661 gen_op_load_fpr_DT0(DFPREG(rs1));
3662 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3663 tcg_gen_helper_0_0(helper_fcmple32);
2382dc6b 3664 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3665 break;
3666 case 0x026: /* VIS I fcmpne32 */
64a88d5d 3667 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3668 gen_op_load_fpr_DT0(DFPREG(rs1));
3669 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3670 tcg_gen_helper_0_0(helper_fcmpne32);
2382dc6b 3671 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3672 break;
3673 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 3674 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3675 gen_op_load_fpr_DT0(DFPREG(rs1));
3676 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3677 tcg_gen_helper_0_0(helper_fcmpgt16);
2382dc6b 3678 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3679 break;
3680 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 3681 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3682 gen_op_load_fpr_DT0(DFPREG(rs1));
3683 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3684 tcg_gen_helper_0_0(helper_fcmpeq16);
2382dc6b 3685 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3686 break;
3687 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 3688 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3689 gen_op_load_fpr_DT0(DFPREG(rs1));
3690 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3691 tcg_gen_helper_0_0(helper_fcmpgt32);
2382dc6b 3692 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3693 break;
3694 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 3695 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3696 gen_op_load_fpr_DT0(DFPREG(rs1));
3697 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3698 tcg_gen_helper_0_0(helper_fcmpeq32);
2382dc6b 3699 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3700 break;
3701 case 0x031: /* VIS I fmul8x16 */
64a88d5d 3702 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3703 gen_op_load_fpr_DT0(DFPREG(rs1));
3704 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3705 tcg_gen_helper_0_0(helper_fmul8x16);
2382dc6b 3706 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3707 break;
3708 case 0x033: /* VIS I fmul8x16au */
64a88d5d 3709 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3710 gen_op_load_fpr_DT0(DFPREG(rs1));
3711 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3712 tcg_gen_helper_0_0(helper_fmul8x16au);
2382dc6b 3713 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3714 break;
3715 case 0x035: /* VIS I fmul8x16al */
64a88d5d 3716 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3717 gen_op_load_fpr_DT0(DFPREG(rs1));
3718 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3719 tcg_gen_helper_0_0(helper_fmul8x16al);
2382dc6b 3720 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3721 break;
3722 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 3723 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3724 gen_op_load_fpr_DT0(DFPREG(rs1));
3725 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3726 tcg_gen_helper_0_0(helper_fmul8sux16);
2382dc6b 3727 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3728 break;
3729 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 3730 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3731 gen_op_load_fpr_DT0(DFPREG(rs1));
3732 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3733 tcg_gen_helper_0_0(helper_fmul8ulx16);
2382dc6b 3734 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3735 break;
3736 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 3737 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3738 gen_op_load_fpr_DT0(DFPREG(rs1));
3739 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3740 tcg_gen_helper_0_0(helper_fmuld8sux16);
2382dc6b 3741 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3742 break;
3743 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 3744 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3745 gen_op_load_fpr_DT0(DFPREG(rs1));
3746 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3747 tcg_gen_helper_0_0(helper_fmuld8ulx16);
2382dc6b 3748 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3749 break;
3750 case 0x03a: /* VIS I fpack32 */
3751 case 0x03b: /* VIS I fpack16 */
3752 case 0x03d: /* VIS I fpackfix */
3753 case 0x03e: /* VIS I pdist */
3754 // XXX
3755 goto illegal_insn;
3299908c 3756 case 0x048: /* VIS I faligndata */
64a88d5d 3757 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3758 gen_op_load_fpr_DT0(DFPREG(rs1));
3759 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3760 tcg_gen_helper_0_0(helper_faligndata);
2382dc6b 3761 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3762 break;
e9ebed4d 3763 case 0x04b: /* VIS I fpmerge */
64a88d5d 3764 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3765 gen_op_load_fpr_DT0(DFPREG(rs1));
3766 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3767 tcg_gen_helper_0_0(helper_fpmerge);
2382dc6b 3768 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3769 break;
3770 case 0x04c: /* VIS II bshuffle */
3771 // XXX
3772 goto illegal_insn;
3773 case 0x04d: /* VIS I fexpand */
64a88d5d 3774 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3775 gen_op_load_fpr_DT0(DFPREG(rs1));
3776 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3777 tcg_gen_helper_0_0(helper_fexpand);
2382dc6b 3778 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3779 break;
3780 case 0x050: /* VIS I fpadd16 */
64a88d5d 3781 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3782 gen_op_load_fpr_DT0(DFPREG(rs1));
3783 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3784 tcg_gen_helper_0_0(helper_fpadd16);
2382dc6b 3785 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3786 break;
3787 case 0x051: /* VIS I fpadd16s */
64a88d5d 3788 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3789 gen_op_load_fpr_FT0(rs1);
3790 gen_op_load_fpr_FT1(rs2);
44e7757c 3791 tcg_gen_helper_0_0(helper_fpadd16s);
e9ebed4d
BS		 3792 gen_op_store_FT0_fpr(rd);
3793 break;
3794 case 0x052: /* VIS I fpadd32 */
64a88d5d 3795 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3796 gen_op_load_fpr_DT0(DFPREG(rs1));
3797 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3798 tcg_gen_helper_0_0(helper_fpadd32);
2382dc6b 3799 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3800 break;
3801 case 0x053: /* VIS I fpadd32s */
64a88d5d 3802 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3803 gen_op_load_fpr_FT0(rs1);
3804 gen_op_load_fpr_FT1(rs2);
44e7757c 3805 tcg_gen_helper_0_0(helper_fpadd32s);
e9ebed4d
BS		 3806 gen_op_store_FT0_fpr(rd);
3807 break;
3808 case 0x054: /* VIS I fpsub16 */
64a88d5d 3809 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3810 gen_op_load_fpr_DT0(DFPREG(rs1));
3811 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3812 tcg_gen_helper_0_0(helper_fpsub16);
2382dc6b 3813 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3814 break;
3815 case 0x055: /* VIS I fpsub16s */
64a88d5d 3816 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3817 gen_op_load_fpr_FT0(rs1);
3818 gen_op_load_fpr_FT1(rs2);
44e7757c 3819 tcg_gen_helper_0_0(helper_fpsub16s);
e9ebed4d
BS		 3820 gen_op_store_FT0_fpr(rd);
3821 break;
3822 case 0x056: /* VIS I fpsub32 */
64a88d5d 3823 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3824 gen_op_load_fpr_DT0(DFPREG(rs1));
3825 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3826 tcg_gen_helper_0_0(helper_fpadd32);
2382dc6b 3827 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3828 break;
3829 case 0x057: /* VIS I fpsub32s */
64a88d5d 3830 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3831 gen_op_load_fpr_FT0(rs1);
3832 gen_op_load_fpr_FT1(rs2);
44e7757c 3833 tcg_gen_helper_0_0(helper_fpsub32s);
e9ebed4d
BS		 3834 gen_op_store_FT0_fpr(rd);
3835 break;
3299908c 3836 case 0x060: /* VIS I fzero */
64a88d5d 3837 CHECK_FPU_FEATURE(dc, VIS1);
44e7757c 3838 tcg_gen_helper_0_0(helper_movl_DT0_0);
2382dc6b 3839 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3840 break;
3841 case 0x061: /* VIS I fzeros */
64a88d5d 3842 CHECK_FPU_FEATURE(dc, VIS1);
44e7757c 3843 tcg_gen_helper_0_0(helper_movl_FT0_0);
3299908c
BS		 3844 gen_op_store_FT0_fpr(rd);
3845 break;
e9ebed4d 3846 case 0x062: /* VIS I fnor */
64a88d5d 3847 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3848 gen_op_load_fpr_DT0(DFPREG(rs1));
3849 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3850 tcg_gen_helper_0_0(helper_fnor);
2382dc6b 3851 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3852 break;
3853 case 0x063: /* VIS I fnors */
64a88d5d 3854 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3855 gen_op_load_fpr_FT0(rs1);
3856 gen_op_load_fpr_FT1(rs2);
44e7757c 3857 tcg_gen_helper_0_0(helper_fnors);
e9ebed4d
BS		 3858 gen_op_store_FT0_fpr(rd);
3859 break;
3860 case 0x064: /* VIS I fandnot2 */
64a88d5d 3861 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3862 gen_op_load_fpr_DT1(DFPREG(rs1));
3863 gen_op_load_fpr_DT0(DFPREG(rs2));
44e7757c 3864 tcg_gen_helper_0_0(helper_fandnot);
2382dc6b 3865 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3866 break;
3867 case 0x065: /* VIS I fandnot2s */
64a88d5d 3868 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3869 gen_op_load_fpr_FT1(rs1);
3870 gen_op_load_fpr_FT0(rs2);
44e7757c 3871 tcg_gen_helper_0_0(helper_fandnots);
e9ebed4d
BS		 3872 gen_op_store_FT0_fpr(rd);
3873 break;
3874 case 0x066: /* VIS I fnot2 */
64a88d5d 3875 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b 3876 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3877 tcg_gen_helper_0_0(helper_fnot);
2382dc6b 3878 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3879 break;
3880 case 0x067: /* VIS I fnot2s */
64a88d5d 3881 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d 3882 gen_op_load_fpr_FT1(rs2);
44e7757c 3883 tcg_gen_helper_0_0(helper_fnot);
e9ebed4d
BS		 3884 gen_op_store_FT0_fpr(rd);
3885 break;
3886 case 0x068: /* VIS I fandnot1 */
64a88d5d 3887 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3888 gen_op_load_fpr_DT0(DFPREG(rs1));
3889 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3890 tcg_gen_helper_0_0(helper_fandnot);
2382dc6b 3891 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3892 break;
3893 case 0x069: /* VIS I fandnot1s */
64a88d5d 3894 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3895 gen_op_load_fpr_FT0(rs1);
3896 gen_op_load_fpr_FT1(rs2);
44e7757c 3897 tcg_gen_helper_0_0(helper_fandnots);
e9ebed4d
BS		 3898 gen_op_store_FT0_fpr(rd);
3899 break;
3900 case 0x06a: /* VIS I fnot1 */
64a88d5d 3901 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b 3902 gen_op_load_fpr_DT1(DFPREG(rs1));
44e7757c 3903 tcg_gen_helper_0_0(helper_fnot);
2382dc6b 3904 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3905 break;
3906 case 0x06b: /* VIS I fnot1s */
64a88d5d 3907 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d 3908 gen_op_load_fpr_FT1(rs1);
44e7757c 3909 tcg_gen_helper_0_0(helper_fnot);
e9ebed4d
BS		 3910 gen_op_store_FT0_fpr(rd);
3911 break;
3912 case 0x06c: /* VIS I fxor */
64a88d5d 3913 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3914 gen_op_load_fpr_DT0(DFPREG(rs1));
3915 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3916 tcg_gen_helper_0_0(helper_fxor);
2382dc6b 3917 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3918 break;
3919 case 0x06d: /* VIS I fxors */
64a88d5d 3920 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3921 gen_op_load_fpr_FT0(rs1);
3922 gen_op_load_fpr_FT1(rs2);
44e7757c 3923 tcg_gen_helper_0_0(helper_fxors);
e9ebed4d
BS		 3924 gen_op_store_FT0_fpr(rd);
3925 break;
3926 case 0x06e: /* VIS I fnand */
64a88d5d 3927 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3928 gen_op_load_fpr_DT0(DFPREG(rs1));
3929 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3930 tcg_gen_helper_0_0(helper_fnand);
2382dc6b 3931 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3932 break;
3933 case 0x06f: /* VIS I fnands */
64a88d5d 3934 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3935 gen_op_load_fpr_FT0(rs1);
3936 gen_op_load_fpr_FT1(rs2);
44e7757c 3937 tcg_gen_helper_0_0(helper_fnands);
e9ebed4d
BS		 3938 gen_op_store_FT0_fpr(rd);
3939 break;
3940 case 0x070: /* VIS I fand */
64a88d5d 3941 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3942 gen_op_load_fpr_DT0(DFPREG(rs1));
3943 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3944 tcg_gen_helper_0_0(helper_fand);
2382dc6b 3945 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3946 break;
3947 case 0x071: /* VIS I fands */
64a88d5d 3948 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3949 gen_op_load_fpr_FT0(rs1);
3950 gen_op_load_fpr_FT1(rs2);
44e7757c 3951 tcg_gen_helper_0_0(helper_fands);
e9ebed4d
BS		 3952 gen_op_store_FT0_fpr(rd);
3953 break;
3954 case 0x072: /* VIS I fxnor */
64a88d5d 3955 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3956 gen_op_load_fpr_DT0(DFPREG(rs1));
3957 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 3958 tcg_gen_helper_0_0(helper_fxnor);
2382dc6b 3959 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3960 break;
3961 case 0x073: /* VIS I fxnors */
64a88d5d 3962 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3963 gen_op_load_fpr_FT0(rs1);
3964 gen_op_load_fpr_FT1(rs2);
44e7757c 3965 tcg_gen_helper_0_0(helper_fxnors);
e9ebed4d
BS		 3966 gen_op_store_FT0_fpr(rd);
3967 break;
3299908c 3968 case 0x074: /* VIS I fsrc1 */
64a88d5d 3969 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3970 gen_op_load_fpr_DT0(DFPREG(rs1));
3971 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3972 break;
3973 case 0x075: /* VIS I fsrc1s */
64a88d5d 3974 CHECK_FPU_FEATURE(dc, VIS1);
3299908c
BS		 3975 gen_op_load_fpr_FT0(rs1);
3976 gen_op_store_FT0_fpr(rd);
3977 break;
e9ebed4d 3978 case 0x076: /* VIS I fornot2 */
64a88d5d 3979 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3980 gen_op_load_fpr_DT1(DFPREG(rs1));
3981 gen_op_load_fpr_DT0(DFPREG(rs2));
44e7757c 3982 tcg_gen_helper_0_0(helper_fornot);
2382dc6b 3983 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3984 break;
3985 case 0x077: /* VIS I fornot2s */
64a88d5d 3986 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 3987 gen_op_load_fpr_FT1(rs1);
3988 gen_op_load_fpr_FT0(rs2);
44e7757c 3989 tcg_gen_helper_0_0(helper_fornots);
e9ebed4d
BS		 3990 gen_op_store_FT0_fpr(rd);
3991 break;
3299908c 3992 case 0x078: /* VIS I fsrc2 */
64a88d5d 3993 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 3994 gen_op_load_fpr_DT0(DFPREG(rs2));
3995 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3996 break;
3997 case 0x079: /* VIS I fsrc2s */
64a88d5d 3998 CHECK_FPU_FEATURE(dc, VIS1);
3299908c
BS		 3999 gen_op_load_fpr_FT0(rs2);
4000 gen_op_store_FT0_fpr(rd);
4001 break;
e9ebed4d 4002 case 0x07a: /* VIS I fornot1 */
64a88d5d 4003 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 4004 gen_op_load_fpr_DT0(DFPREG(rs1));
4005 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 4006 tcg_gen_helper_0_0(helper_fornot);
2382dc6b 4007 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 4008 break;
4009 case 0x07b: /* VIS I fornot1s */
64a88d5d 4010 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 4011 gen_op_load_fpr_FT0(rs1);
4012 gen_op_load_fpr_FT1(rs2);
44e7757c 4013 tcg_gen_helper_0_0(helper_fornots);
e9ebed4d
BS		 4014 gen_op_store_FT0_fpr(rd);
4015 break;
4016 case 0x07c: /* VIS I for */
64a88d5d 4017 CHECK_FPU_FEATURE(dc, VIS1);
2382dc6b
BS		 4018 gen_op_load_fpr_DT0(DFPREG(rs1));
4019 gen_op_load_fpr_DT1(DFPREG(rs2));
44e7757c 4020 tcg_gen_helper_0_0(helper_for);
2382dc6b 4021 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 4022 break;
4023 case 0x07d: /* VIS I fors */
64a88d5d 4024 CHECK_FPU_FEATURE(dc, VIS1);
e9ebed4d
BS		 4025 gen_op_load_fpr_FT0(rs1);
4026 gen_op_load_fpr_FT1(rs2);
44e7757c 4027 tcg_gen_helper_0_0(helper_fors);
e9ebed4d
BS		 4028 gen_op_store_FT0_fpr(rd);
4029 break;
3299908c 4030 case 0x07e: /* VIS I fone */
64a88d5d 4031 CHECK_FPU_FEATURE(dc, VIS1);
44e7757c 4032 tcg_gen_helper_0_0(helper_movl_DT0_1);
2382dc6b 4033 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 4034 break;
4035 case 0x07f: /* VIS I fones */
64a88d5d 4036 CHECK_FPU_FEATURE(dc, VIS1);
44e7757c 4037 tcg_gen_helper_0_0(helper_movl_FT0_1);
3299908c
BS		 4038 gen_op_store_FT0_fpr(rd);
4039 break;
e9ebed4d
BS		 4040 case 0x080: /* VIS I shutdown */
4041 case 0x081: /* VIS II siam */
4042 // XXX
4043 goto illegal_insn;
3299908c
BS		 4044 default:
4045 goto illegal_insn;
4046 }
4047#else
0f8a249a 4048 goto ncp_insn;
3299908c
BS		 4049#endif
4050 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4051#ifdef TARGET_SPARC64
0f8a249a 4052 goto illegal_insn;
fcc72045 4053#else
0f8a249a 4054 goto ncp_insn;
fcc72045 4055#endif
3475187d 4056#ifdef TARGET_SPARC64
0f8a249a 4057 } else if (xop == 0x39) { /* V9 return */
2ea815ca
BS		 4058 TCGv r_const;
4059
6ae20372 4060 save_state(dc, cpu_cond);
9322a4bf 4061 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 4062 if (IS_IMM) { /* immediate */
4063 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 4064 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a 4065 } else { /* register */
3475187d 4066 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4067 if (rs2) {
6ae20372
BS		 4068 gen_movl_reg_TN(rs2, cpu_src2);
4069 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 4070 } else
4071 tcg_gen_mov_tl(cpu_dst, cpu_src1);
3475187d 4072 }
72a9747b 4073 tcg_gen_helper_0_0(helper_restore);
6ae20372 4074 gen_mov_pc_npc(dc, cpu_cond);
2ea815ca
BS		 4075 r_const = tcg_const_i32(3);
4076 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4077 tcg_temp_free(r_const);
6ae20372 4078 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 4079 dc->npc = DYNAMIC_PC;
4080 goto jmp_insn;
3475187d 4081#endif
0f8a249a 4082 } else {
9322a4bf 4083 cpu_src1 = get_src1(insn, cpu_src1);
0f8a249a
BS		 4084 if (IS_IMM) { /* immediate */
4085 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 4086 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
0f8a249a 4087 } else { /* register */
e80cfcfc 4088 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4089 if (rs2) {
6ae20372
BS		 4090 gen_movl_reg_TN(rs2, cpu_src2);
4091 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
6f551262
BS		 4092 } else
4093 tcg_gen_mov_tl(cpu_dst, cpu_src1);
cf495bcf 4094 }
0f8a249a
BS		 4095 switch (xop) {
4096 case 0x38: /* jmpl */
4097 {
2ea815ca
BS		 4098 TCGv r_const;
4099
4100 r_const = tcg_const_tl(dc->pc);
4101 gen_movl_TN_reg(rd, r_const);
4102 tcg_temp_free(r_const);
6ae20372 4103 gen_mov_pc_npc(dc, cpu_cond);
2ea815ca 4104 r_const = tcg_const_i32(3);
77f193da 4105 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
2ea815ca
BS		 4106 r_const);
4107 tcg_temp_free(r_const);
6ae20372 4108 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a
BS		 4109 dc->npc = DYNAMIC_PC;
4110 }
4111 goto jmp_insn;
3475187d 4112#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4113 case 0x39: /* rett, V9 return */
4114 {
2ea815ca
BS		 4115 TCGv r_const;
4116
0f8a249a
BS		 4117 if (!supervisor(dc))
4118 goto priv_insn;
6ae20372 4119 gen_mov_pc_npc(dc, cpu_cond);
2ea815ca 4120 r_const = tcg_const_i32(3);
77f193da 4121 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
2ea815ca
BS		 4122 r_const);
4123 tcg_temp_free(r_const);
6ae20372 4124 tcg_gen_mov_tl(cpu_npc, cpu_dst);
0f8a249a 4125 dc->npc = DYNAMIC_PC;
1a2fb1c0 4126 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 4127 }
4128 goto jmp_insn;
4129#endif
4130 case 0x3b: /* flush */
64a88d5d
BS		 4131 if (!((dc)->features & CPU_FEATURE_FLUSH))
4132 goto unimp_flush;
6ae20372 4133 tcg_gen_helper_0_1(helper_flush, cpu_dst);
0f8a249a
BS		 4134 break;
4135 case 0x3c: /* save */
6ae20372 4136 save_state(dc, cpu_cond);
72a9747b 4137 tcg_gen_helper_0_0(helper_save);
6ae20372 4138 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a
BS		 4139 break;
4140 case 0x3d: /* restore */
6ae20372 4141 save_state(dc, cpu_cond);
72a9747b 4142 tcg_gen_helper_0_0(helper_restore);
6ae20372 4143 gen_movl_TN_reg(rd, cpu_dst);
0f8a249a 4144 break;
3475187d 4145#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4146 case 0x3e: /* V9 done/retry */
4147 {
4148 switch (rd) {
4149 case 0:
4150 if (!supervisor(dc))
4151 goto priv_insn;
4152 dc->npc = DYNAMIC_PC;
4153 dc->pc = DYNAMIC_PC;
1a2fb1c0 4154 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 4155 goto jmp_insn;
4156 case 1:
4157 if (!supervisor(dc))
4158 goto priv_insn;
4159 dc->npc = DYNAMIC_PC;
4160 dc->pc = DYNAMIC_PC;
1a2fb1c0 4161 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 4162 goto jmp_insn;
4163 default:
4164 goto illegal_insn;
4165 }
4166 }
4167 break;
4168#endif
4169 default:
4170 goto illegal_insn;
4171 }
cf495bcf 4172 }
0f8a249a
BS		 4173 break;
4174 }
4175 break;
4176 case 3: /* load/store instructions */
4177 {
4178 unsigned int xop = GET_FIELD(insn, 7, 12);
9322a4bf 4179
9322a4bf 4180 cpu_src1 = get_src1(insn, cpu_src1);
81ad8ba2
BS		 4181 if (xop == 0x3c || xop == 0x3e)
4182 {
4183 rs2 = GET_FIELD(insn, 27, 31);
6ae20372 4184 gen_movl_reg_TN(rs2, cpu_src2);
81ad8ba2
BS		 4185 }
4186 else if (IS_IMM) { /* immediate */
0f8a249a 4187 rs2 = GET_FIELDs(insn, 19, 31);
6ae20372 4188 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
0f8a249a
BS		 4189 } else { /* register */
4190 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4191 if (rs2 != 0) {
6ae20372
BS		 4192 gen_movl_reg_TN(rs2, cpu_src2);
4193 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
6f551262
BS		 4194 } else
4195 tcg_gen_mov_tl(cpu_addr, cpu_src1);
0f8a249a 4196 }
2f2ecb83
BS		 4197 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4198 (xop > 0x17 && xop <= 0x1d ) ||
4199 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 4200 switch (xop) {
1a2fb1c0 4201 case 0x0: /* load unsigned word */
6ae20372
BS		 4202 ABI32_MASK(cpu_addr);
4203 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4204 break;
4205 case 0x1: /* load unsigned byte */
6ae20372
BS		 4206 ABI32_MASK(cpu_addr);
4207 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4208 break;
4209 case 0x2: /* load unsigned halfword */
6ae20372
BS		 4210 ABI32_MASK(cpu_addr);
4211 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4212 break;
4213 case 0x3: /* load double word */
0f8a249a 4214 if (rd & 1)
d4218d99 4215 goto illegal_insn;
1a2fb1c0 4216 else {
2ea815ca
BS		 4217 TCGv r_const;
4218
c2bc0e38 4219 save_state(dc, cpu_cond);
2ea815ca 4220 r_const = tcg_const_i32(7);
d987963a 4221 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
2ea815ca
BS		 4222 r_const); // XXX remove
4223 tcg_temp_free(r_const);
6ae20372
BS		 4224 ABI32_MASK(cpu_addr);
4225 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
32b6c812
BS		 4226 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4227 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4228 gen_movl_TN_reg(rd + 1, cpu_tmp0);
8911f501 4229 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
6ae20372
BS		 4230 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4231 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
1a2fb1c0 4232 }
0f8a249a
BS		 4233 break;
4234 case 0x9: /* load signed byte */
6ae20372
BS		 4235 ABI32_MASK(cpu_addr);
4236 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4237 break;
4238 case 0xa: /* load signed halfword */
6ae20372
BS		 4239 ABI32_MASK(cpu_addr);
4240 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4241 break;
4242 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4243 {
4244 TCGv r_const;
4245
4246 ABI32_MASK(cpu_addr);
4247 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4248 r_const = tcg_const_tl(0xff);
4249 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4250 tcg_temp_free(r_const);
4251 }
0f8a249a 4252 break;
77f193da
BS		 4253 case 0x0f: /* swap register with memory. Also
4254 atomically */
64a88d5d 4255 CHECK_IU_FEATURE(dc, SWAP);
6ae20372
BS		 4256 gen_movl_reg_TN(rd, cpu_val);
4257 ABI32_MASK(cpu_addr);
4258 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4259 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4260 tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
0f8a249a 4261 break;
3475187d 4262#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4263 case 0x10: /* load word alternate */
3475187d 4264#ifndef TARGET_SPARC64
0f8a249a
BS		 4265 if (IS_IMM)
4266 goto illegal_insn;
4267 if (!supervisor(dc))
4268 goto priv_insn;
6ea4a6c8 4269#endif
c2bc0e38 4270 save_state(dc, cpu_cond);
6ae20372 4271 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a
BS		 4272 break;
4273 case 0x11: /* load unsigned byte alternate */
3475187d 4274#ifndef TARGET_SPARC64
0f8a249a
BS		 4275 if (IS_IMM)
4276 goto illegal_insn;
4277 if (!supervisor(dc))
4278 goto priv_insn;
4279#endif
c2bc0e38 4280 save_state(dc, cpu_cond);
6ae20372 4281 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a
BS		 4282 break;
4283 case 0x12: /* load unsigned halfword alternate */
3475187d 4284#ifndef TARGET_SPARC64
0f8a249a
BS		 4285 if (IS_IMM)
4286 goto illegal_insn;
4287 if (!supervisor(dc))
4288 goto priv_insn;
3475187d 4289#endif
c2bc0e38 4290 save_state(dc, cpu_cond);
6ae20372 4291 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a
BS		 4292 break;
4293 case 0x13: /* load double word alternate */
3475187d 4294#ifndef TARGET_SPARC64
0f8a249a
BS		 4295 if (IS_IMM)
4296 goto illegal_insn;
4297 if (!supervisor(dc))
4298 goto priv_insn;
3475187d 4299#endif
0f8a249a 4300 if (rd & 1)
d4218d99 4301 goto illegal_insn;
c2bc0e38 4302 save_state(dc, cpu_cond);
6ae20372 4303 gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
32b6c812 4304 gen_movl_TN_reg(rd + 1, cpu_tmp0);
0f8a249a
BS		 4305 break;
4306 case 0x19: /* load signed byte alternate */
3475187d 4307#ifndef TARGET_SPARC64
0f8a249a
BS		 4308 if (IS_IMM)
4309 goto illegal_insn;
4310 if (!supervisor(dc))
4311 goto priv_insn;
4312#endif
c2bc0e38 4313 save_state(dc, cpu_cond);
6ae20372 4314 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a
BS		 4315 break;
4316 case 0x1a: /* load signed halfword alternate */
3475187d 4317#ifndef TARGET_SPARC64
0f8a249a
BS		 4318 if (IS_IMM)
4319 goto illegal_insn;
4320 if (!supervisor(dc))
4321 goto priv_insn;
3475187d 4322#endif
c2bc0e38 4323 save_state(dc, cpu_cond);
6ae20372 4324 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4325 break;
4326 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4327#ifndef TARGET_SPARC64
0f8a249a
BS		 4328 if (IS_IMM)
4329 goto illegal_insn;
4330 if (!supervisor(dc))
4331 goto priv_insn;
4332#endif
c2bc0e38 4333 save_state(dc, cpu_cond);
6ae20372 4334 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4335 break;
77f193da
BS		 4336 case 0x1f: /* swap reg with alt. memory. Also
4337 atomically */
64a88d5d 4338 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4339#ifndef TARGET_SPARC64
0f8a249a
BS		 4340 if (IS_IMM)
4341 goto illegal_insn;
4342 if (!supervisor(dc))
4343 goto priv_insn;
6ea4a6c8 4344#endif
c2bc0e38 4345 save_state(dc, cpu_cond);
6ae20372
BS		 4346 gen_movl_reg_TN(rd, cpu_val);
4347 gen_swap_asi(cpu_val, cpu_addr, insn);
0f8a249a 4348 break;
3475187d
FB		 4349
4350#ifndef TARGET_SPARC64
0f8a249a
BS		 4351 case 0x30: /* ldc */
4352 case 0x31: /* ldcsr */
4353 case 0x33: /* lddc */
4354 goto ncp_insn;
3475187d
FB		 4355#endif
4356#endif
4357#ifdef TARGET_SPARC64
0f8a249a 4358 case 0x08: /* V9 ldsw */
6ae20372
BS		 4359 ABI32_MASK(cpu_addr);
4360 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4361 break;
4362 case 0x0b: /* V9 ldx */
6ae20372
BS		 4363 ABI32_MASK(cpu_addr);
4364 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4365 break;
4366 case 0x18: /* V9 ldswa */
c2bc0e38 4367 save_state(dc, cpu_cond);
6ae20372 4368 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4369 break;
4370 case 0x1b: /* V9 ldxa */
c2bc0e38 4371 save_state(dc, cpu_cond);
6ae20372 4372 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4373 break;
4374 case 0x2d: /* V9 prefetch, no effect */
4375 goto skip_move;
4376 case 0x30: /* V9 ldfa */
c2bc0e38 4377 save_state(dc, cpu_cond);
6ae20372 4378 gen_ldf_asi(cpu_addr, insn, 4, rd);
81ad8ba2 4379 goto skip_move;
0f8a249a 4380 case 0x33: /* V9 lddfa */
c2bc0e38 4381 save_state(dc, cpu_cond);
6ae20372 4382 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
81ad8ba2 4383 goto skip_move;
0f8a249a
BS		 4384 case 0x3d: /* V9 prefetcha, no effect */
4385 goto skip_move;
4386 case 0x32: /* V9 ldqfa */
64a88d5d 4387 CHECK_FPU_FEATURE(dc, FLOAT128);
c2bc0e38 4388 save_state(dc, cpu_cond);
6ae20372 4389 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
1f587329 4390 goto skip_move;
0f8a249a
BS		 4391#endif
4392 default:
4393 goto illegal_insn;
4394 }
6ae20372 4395 gen_movl_TN_reg(rd, cpu_val);
3475187d 4396#ifdef TARGET_SPARC64
0f8a249a 4397 skip_move: ;
3475187d 4398#endif
0f8a249a 4399 } else if (xop >= 0x20 && xop < 0x24) {
6ae20372 4400 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4401 goto jmp_insn;
c2bc0e38 4402 save_state(dc, cpu_cond);
0f8a249a
BS		 4403 switch (xop) {
4404 case 0x20: /* load fpreg */
c2bc0e38 4405 ABI32_MASK(cpu_addr);
6ae20372 4406 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
ce8536e2
BS		 4407 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4408 offsetof(CPUState, fpr[rd]));
0f8a249a
BS		 4409 break;
4410 case 0x21: /* load fsr */
c2bc0e38 4411 ABI32_MASK(cpu_addr);
6ae20372 4412 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
ce8536e2
BS		 4413 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4414 offsetof(CPUState, ft0));
7e8c2b6c 4415 tcg_gen_helper_0_0(helper_ldfsr);
0f8a249a
BS		 4416 break;
4417 case 0x22: /* load quad fpreg */
2ea815ca
BS		 4418 {
4419 TCGv r_const;
4420
4421 CHECK_FPU_FEATURE(dc, FLOAT128);
4422 r_const = tcg_const_i32(dc->mem_idx);
4423 tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4424 tcg_temp_free(r_const);
4425 gen_op_store_QT0_fpr(QFPREG(rd));
4426 }
1f587329 4427 break;
0f8a249a 4428 case 0x23: /* load double fpreg */
2ea815ca
BS		 4429 {
4430 TCGv r_const;
4431
4432 r_const = tcg_const_i32(dc->mem_idx);
4433 tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4434 tcg_temp_free(r_const);
4435 gen_op_store_DT0_fpr(DFPREG(rd));
4436 }
0f8a249a
BS		 4437 break;
4438 default:
4439 goto illegal_insn;
4440 }
4441 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4442 xop == 0xe || xop == 0x1e) {
6ae20372 4443 gen_movl_reg_TN(rd, cpu_val);
0f8a249a 4444 switch (xop) {
1a2fb1c0 4445 case 0x4: /* store word */
6ae20372
BS		 4446 ABI32_MASK(cpu_addr);
4447 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4448 break;
1a2fb1c0 4449 case 0x5: /* store byte */
6ae20372
BS		 4450 ABI32_MASK(cpu_addr);
4451 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4452 break;
1a2fb1c0 4453 case 0x6: /* store halfword */
6ae20372
BS		 4454 ABI32_MASK(cpu_addr);
4455 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4456 break;
1a2fb1c0 4457 case 0x7: /* store double word */
0f8a249a 4458 if (rd & 1)
d4218d99 4459 goto illegal_insn;
1a2fb1c0 4460 else {
2ea815ca 4461 TCGv r_low, r_const;
1a2fb1c0 4462
c2bc0e38
BS		 4463 save_state(dc, cpu_cond);
4464 ABI32_MASK(cpu_addr);
2ea815ca 4465 r_const = tcg_const_i32(7);
c2bc0e38 4466 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
2ea815ca
BS		 4467 r_const); // XXX remove
4468 tcg_temp_free(r_const);
8d96d209 4469 r_low = tcg_temp_new(TCG_TYPE_TL);
1a2fb1c0 4470 gen_movl_reg_TN(rd + 1, r_low);
6ae20372 4471 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
1a2fb1c0 4472 r_low);
2ea815ca 4473 tcg_temp_free(r_low);
6ae20372 4474 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
7fa76c0b 4475 }
0f8a249a 4476 break;
3475187d 4477#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 4478 case 0x14: /* store word alternate */
3475187d 4479#ifndef TARGET_SPARC64
0f8a249a
BS		 4480 if (IS_IMM)
4481 goto illegal_insn;
4482 if (!supervisor(dc))
4483 goto priv_insn;
6ea4a6c8 4484#endif
c2bc0e38 4485 save_state(dc, cpu_cond);
6ae20372 4486 gen_st_asi(cpu_val, cpu_addr, insn, 4);
d39c0b99 4487 break;
1a2fb1c0 4488 case 0x15: /* store byte alternate */
3475187d 4489#ifndef TARGET_SPARC64
0f8a249a
BS		 4490 if (IS_IMM)
4491 goto illegal_insn;
4492 if (!supervisor(dc))
4493 goto priv_insn;
3475187d 4494#endif
c2bc0e38 4495 save_state(dc, cpu_cond);
6ae20372 4496 gen_st_asi(cpu_val, cpu_addr, insn, 1);
d39c0b99 4497 break;
1a2fb1c0 4498 case 0x16: /* store halfword alternate */
3475187d 4499#ifndef TARGET_SPARC64
0f8a249a
BS		 4500 if (IS_IMM)
4501 goto illegal_insn;
4502 if (!supervisor(dc))
4503 goto priv_insn;
6ea4a6c8 4504#endif
c2bc0e38 4505 save_state(dc, cpu_cond);
6ae20372 4506 gen_st_asi(cpu_val, cpu_addr, insn, 2);
d39c0b99 4507 break;
1a2fb1c0 4508 case 0x17: /* store double word alternate */
3475187d 4509#ifndef TARGET_SPARC64
0f8a249a
BS		 4510 if (IS_IMM)
4511 goto illegal_insn;
4512 if (!supervisor(dc))
4513 goto priv_insn;
3475187d 4514#endif
0f8a249a 4515 if (rd & 1)
d4218d99 4516 goto illegal_insn;
1a2fb1c0 4517 else {
c2bc0e38 4518 save_state(dc, cpu_cond);
6ae20372 4519 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4520 }
d39c0b99 4521 break;
e80cfcfc 4522#endif
3475187d 4523#ifdef TARGET_SPARC64
0f8a249a 4524 case 0x0e: /* V9 stx */
6ae20372
BS		 4525 ABI32_MASK(cpu_addr);
4526 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4527 break;
4528 case 0x1e: /* V9 stxa */
c2bc0e38 4529 save_state(dc, cpu_cond);
6ae20372 4530 gen_st_asi(cpu_val, cpu_addr, insn, 8);
0f8a249a 4531 break;
3475187d 4532#endif
0f8a249a
BS		 4533 default:
4534 goto illegal_insn;
4535 }
4536 } else if (xop > 0x23 && xop < 0x28) {
6ae20372 4537 if (gen_trap_ifnofpu(dc, cpu_cond))
a80dde08 4538 goto jmp_insn;
c2bc0e38 4539 save_state(dc, cpu_cond);
0f8a249a 4540 switch (xop) {
ce8536e2 4541 case 0x24: /* store fpreg */
c2bc0e38 4542 ABI32_MASK(cpu_addr);
ce8536e2
BS		 4543 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4544 offsetof(CPUState, fpr[rd]));
6ae20372 4545 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4546 break;
4547 case 0x25: /* stfsr, V9 stxfsr */
c2bc0e38 4548 ABI32_MASK(cpu_addr);
bb5529bb 4549 tcg_gen_helper_0_0(helper_stfsr);
ce8536e2
BS		 4550 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4551 offsetof(CPUState, ft0));
6ae20372 4552 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
0f8a249a 4553 break;
1f587329
BS		 4554 case 0x26:
4555#ifdef TARGET_SPARC64
1f587329 4556 /* V9 stqf, store quad fpreg */
2ea815ca
BS		 4557 {
4558 TCGv r_const;
4559
4560 CHECK_FPU_FEATURE(dc, FLOAT128);
4561 gen_op_load_fpr_QT0(QFPREG(rd));
4562 r_const = tcg_const_i32(dc->mem_idx);
4563 tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4564 tcg_temp_free(r_const);
4565 }
1f587329 4566 break;
1f587329
BS		 4567#else /* !TARGET_SPARC64 */
4568 /* stdfq, store floating point queue */
4569#if defined(CONFIG_USER_ONLY)
4570 goto illegal_insn;
4571#else
0f8a249a
BS		 4572 if (!supervisor(dc))
4573 goto priv_insn;
6ae20372 4574 if (gen_trap_ifnofpu(dc, cpu_cond))
0f8a249a
BS		 4575 goto jmp_insn;
4576 goto nfq_insn;
1f587329 4577#endif
0f8a249a 4578#endif
7fa76c0b 4579 case 0x27: /* store double fpreg */
2ea815ca
BS		 4580 {
4581 TCGv r_const;
4582
4583 gen_op_load_fpr_DT0(DFPREG(rd));
4584 r_const = tcg_const_i32(dc->mem_idx);
4585 tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4586 tcg_temp_free(r_const);
4587 }
0f8a249a
BS		 4588 break;
4589 default:
4590 goto illegal_insn;
4591 }
4592 } else if (xop > 0x33 && xop < 0x3f) {
c2bc0e38 4593 save_state(dc, cpu_cond);
0f8a249a 4594 switch (xop) {
a4d17f19 4595#ifdef TARGET_SPARC64
0f8a249a 4596 case 0x34: /* V9 stfa */
3391c818 4597 gen_op_load_fpr_FT0(rd);
6ae20372 4598 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 4599 break;
1f587329 4600 case 0x36: /* V9 stqfa */
2ea815ca
BS		 4601 {
4602 TCGv r_const;
4603
4604 CHECK_FPU_FEATURE(dc, FLOAT128);
4605 r_const = tcg_const_i32(7);
4606 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4607 r_const);
4608 tcg_temp_free(r_const);
4609 gen_op_load_fpr_QT0(QFPREG(rd));
4610 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4611 }
1f587329 4612 break;
0f8a249a 4613 case 0x37: /* V9 stdfa */
3391c818 4614 gen_op_load_fpr_DT0(DFPREG(rd));
6ae20372 4615 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a
BS		 4616 break;
4617 case 0x3c: /* V9 casa */
6ae20372
BS		 4618 gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4619 gen_movl_TN_reg(rd, cpu_val);
0f8a249a
BS		 4620 break;
4621 case 0x3e: /* V9 casxa */
6ae20372
BS		 4622 gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4623 gen_movl_TN_reg(rd, cpu_val);
0f8a249a 4624 break;
a4d17f19 4625#else
0f8a249a
BS		 4626 case 0x34: /* stc */
4627 case 0x35: /* stcsr */
4628 case 0x36: /* stdcq */
4629 case 0x37: /* stdc */
4630 goto ncp_insn;
4631#endif
4632 default:
4633 goto illegal_insn;
4634 }
e8af50a3 4635 }
0f8a249a
BS		 4636 else
4637 goto illegal_insn;
4638 }
4639 break;
cf495bcf
FB		 4640 }
4641 /* default case for non jump instructions */
72cbca10 4642 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 4643 dc->pc = DYNAMIC_PC;
4644 gen_op_next_insn();
72cbca10
FB		 4645 } else if (dc->npc == JUMP_PC) {
4646 /* we can do a static jump */
6ae20372 4647 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 4648 dc->is_br = 1;
4649 } else {
0f8a249a
BS		 4650 dc->pc = dc->npc;
4651 dc->npc = dc->npc + 4;
cf495bcf 4652 }
e80cfcfc 4653 jmp_insn:
cf495bcf
FB		 4654 return;
4655 illegal_insn:
2ea815ca
BS		 4656 {
4657 TCGv r_const;
4658
4659 save_state(dc, cpu_cond);
4660 r_const = tcg_const_i32(TT_ILL_INSN);
4661 tcg_gen_helper_0_1(raise_exception, r_const);
4662 tcg_temp_free(r_const);
4663 dc->is_br = 1;
4664 }
e8af50a3 4665 return;
64a88d5d 4666 unimp_flush:
2ea815ca
BS		 4667 {
4668 TCGv r_const;
4669
4670 save_state(dc, cpu_cond);
4671 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4672 tcg_gen_helper_0_1(raise_exception, r_const);
4673 tcg_temp_free(r_const);
4674 dc->is_br = 1;
4675 }
64a88d5d 4676 return;
e80cfcfc 4677#if !defined(CONFIG_USER_ONLY)
e8af50a3 4678 priv_insn:
2ea815ca
BS		 4679 {
4680 TCGv r_const;
4681
4682 save_state(dc, cpu_cond);
4683 r_const = tcg_const_i32(TT_PRIV_INSN);
4684 tcg_gen_helper_0_1(raise_exception, r_const);
4685 tcg_temp_free(r_const);
4686 dc->is_br = 1;
4687 }
e80cfcfc 4688 return;
64a88d5d 4689#endif
e80cfcfc 4690 nfpu_insn:
6ae20372 4691 save_state(dc, cpu_cond);
e80cfcfc
FB		 4692 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4693 dc->is_br = 1;
fcc72045 4694 return;
64a88d5d 4695#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 4696 nfq_insn:
6ae20372 4697 save_state(dc, cpu_cond);
9143e598
BS		 4698 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4699 dc->is_br = 1;
4700 return;
4701#endif
fcc72045
BS		 4702#ifndef TARGET_SPARC64
4703 ncp_insn:
2ea815ca
BS		 4704 {
4705 TCGv r_const;
4706
4707 save_state(dc, cpu_cond);
4708 r_const = tcg_const_i32(TT_NCP_INSN);
4709 tcg_gen_helper_0_1(raise_exception, r_const);
4710 tcg_temp_free(r_const);
4711 dc->is_br = 1;
4712 }
fcc72045
BS		 4713 return;
4714#endif
7a3f1944
FB		 4715}
4716
cf495bcf 4717static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 4718 int spc, CPUSPARCState *env)
7a3f1944 4719{
72cbca10 4720 target_ulong pc_start, last_pc;
cf495bcf
FB		 4721 uint16_t *gen_opc_end;
4722 DisasContext dc1, *dc = &dc1;
e8af50a3 4723 int j, lj = -1;
2e70f6ef
PB		 4724 int num_insns;
4725 int max_insns;
cf495bcf
FB		 4726
4727 memset(dc, 0, sizeof(DisasContext));
cf495bcf 4728 dc->tb = tb;
72cbca10 4729 pc_start = tb->pc;
cf495bcf 4730 dc->pc = pc_start;
e80cfcfc 4731 last_pc = dc->pc;
72cbca10 4732 dc->npc = (target_ulong) tb->cs_base;
6f27aba6 4733 dc->mem_idx = cpu_mmu_index(env);
64a88d5d
BS		 4734 dc->features = env->features;
4735 if ((dc->features & CPU_FEATURE_FLOAT)) {
4736 dc->fpu_enabled = cpu_fpu_enabled(env);
4737#if defined(CONFIG_USER_ONLY)
4738 dc->features |= CPU_FEATURE_FLOAT128;
4739#endif
4740 } else
4741 dc->fpu_enabled = 0;
cf495bcf 4742 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 4743
1a2fb1c0 4744 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
8911f501
BS		 4745 cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4746 cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
d987963a
BS		 4747
4748 cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4749
4750 // loads and stores
3f0436fe 4751 cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
d987963a 4752 cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
1a2fb1c0 4753
2e70f6ef
PB		 4754 num_insns = 0;
4755 max_insns = tb->cflags & CF_COUNT_MASK;
4756 if (max_insns == 0)
4757 max_insns = CF_COUNT_MASK;
4758 gen_icount_start();
cf495bcf 4759 do {
e8af50a3
FB		 4760 if (env->nb_breakpoints > 0) {
4761 for(j = 0; j < env->nb_breakpoints; j++) {
4762 if (env->breakpoints[j] == dc->pc) {
0f8a249a 4763 if (dc->pc != pc_start)
6ae20372 4764 save_state(dc, cpu_cond);
1a2fb1c0 4765 tcg_gen_helper_0_0(helper_debug);
57fec1fe 4766 tcg_gen_exit_tb(0);
0f8a249a 4767 dc->is_br = 1;
e80cfcfc 4768 goto exit_gen_loop;
e8af50a3
FB		 4769 }
4770 }
4771 }
4772 if (spc) {
4773 if (loglevel > 0)
4774 fprintf(logfile, "Search PC...\n");
4775 j = gen_opc_ptr - gen_opc_buf;
4776 if (lj < j) {
4777 lj++;
4778 while (lj < j)
4779 gen_opc_instr_start[lj++] = 0;
4780 gen_opc_pc[lj] = dc->pc;
4781 gen_opc_npc[lj] = dc->npc;
4782 gen_opc_instr_start[lj] = 1;
2e70f6ef 4783 gen_opc_icount[lj] = num_insns;
e8af50a3
FB		 4784 }
4785 }
2e70f6ef
PB		 4786 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4787 gen_io_start();
0f8a249a
BS		 4788 last_pc = dc->pc;
4789 disas_sparc_insn(dc);
2e70f6ef 4790 num_insns++;
0f8a249a
BS		 4791
4792 if (dc->is_br)
4793 break;
4794 /* if the next PC is different, we abort now */
4795 if (dc->pc != (last_pc + 4))
4796 break;
d39c0b99
FB		 4797 /* if we reach a page boundary, we stop generation so that the
4798 PC of a TT_TFAULT exception is always in the right page */
4799 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4800 break;
e80cfcfc
FB		 4801 /* if single step mode, we generate only one instruction and
4802 generate an exception */
4803 if (env->singlestep_enabled) {
2f5680ee 4804 tcg_gen_movi_tl(cpu_pc, dc->pc);
57fec1fe 4805 tcg_gen_exit_tb(0);
e80cfcfc
FB		 4806 break;
4807 }
cf495bcf 4808 } while ((gen_opc_ptr < gen_opc_end) &&
2e70f6ef
PB		 4809 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4810 num_insns < max_insns);
e80cfcfc
FB		 4811
4812 exit_gen_loop:
d987963a 4813 tcg_temp_free(cpu_addr);
3f0436fe 4814 tcg_temp_free(cpu_val);
d987963a 4815 tcg_temp_free(cpu_dst);
2ea815ca
BS		 4816 tcg_temp_free(cpu_tmp64);
4817 tcg_temp_free(cpu_tmp32);
4818 tcg_temp_free(cpu_tmp0);
2e70f6ef
PB		 4819 if (tb->cflags & CF_LAST_IO)
4820 gen_io_end();
72cbca10 4821 if (!dc->is_br) {
5fafdf24 4822 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 4823 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4824 /* static PC and NPC: we can use direct chaining */
2f5680ee 4825 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10
FB		 4826 } else {
4827 if (dc->pc != DYNAMIC_PC)
2f5680ee 4828 tcg_gen_movi_tl(cpu_pc, dc->pc);
6ae20372 4829 save_npc(dc, cpu_cond);
57fec1fe 4830 tcg_gen_exit_tb(0);
72cbca10
FB		 4831 }
4832 }
2e70f6ef 4833 gen_icount_end(tb, num_insns);
cf495bcf 4834 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 4835 if (spc) {
4836 j = gen_opc_ptr - gen_opc_buf;
4837 lj++;
4838 while (lj <= j)
4839 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 4840#if 0
4841 if (loglevel > 0) {
4842 page_dump(logfile);
4843 }
4844#endif
c3278b7b
FB		 4845 gen_opc_jump_pc[0] = dc->jump_pc[0];
4846 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 4847 } else {
e80cfcfc 4848 tb->size = last_pc + 4 - pc_start;
2e70f6ef 4849 tb->icount = num_insns;
e8af50a3 4850 }
7a3f1944 4851#ifdef DEBUG_DISAS
e19e89a5 4852 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 4853 fprintf(logfile, "--------------\n");
4854 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4855 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4856 fprintf(logfile, "\n");
cf495bcf 4857 }
7a3f1944 4858#endif
cf495bcf 4859 return 0;
7a3f1944
FB		 4860}
4861
cf495bcf 4862int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4863{
e8af50a3 4864 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 4865}
4866
cf495bcf 4867int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4868{
e8af50a3 4869 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 4870}
4871
c48fcb47 4872void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 4873{
f5069b26 4874 unsigned int i;
c48fcb47 4875 static int inited;
f5069b26
BS		 4876 static const char * const gregnames[8] = {
4877 NULL, // g0 not used
4878 "g1",
4879 "g2",
4880 "g3",
4881 "g4",
4882 "g5",
4883 "g6",
4884 "g7",
4885 };
aaed909a 4886
1a2fb1c0
BS		 4887 /* init various static tables */
4888 if (!inited) {
4889 inited = 1;
4890
1a2fb1c0 4891 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
db4a4ea4
BS		 4892 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4893 offsetof(CPUState, regwptr),
4894 "regwptr");
1a2fb1c0 4895#ifdef TARGET_SPARC64
dc99a3f2
BS		 4896 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4897 TCG_AREG0, offsetof(CPUState, xcc),
4898 "xcc");
1a2fb1c0 4899#endif
7c60cc4b 4900 cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
77f193da
BS		 4901 TCG_AREG0, offsetof(CPUState, cond),
4902 "cond");
dc99a3f2
BS		 4903 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4904 TCG_AREG0, offsetof(CPUState, cc_src),
4905 "cc_src");
d9bdab86
BS		 4906 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4907 offsetof(CPUState, cc_src2),
4908 "cc_src2");
dc99a3f2
BS		 4909 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4910 TCG_AREG0, offsetof(CPUState, cc_dst),
4911 "cc_dst");
4912 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4913 TCG_AREG0, offsetof(CPUState, psr),
4914 "psr");
87e92502
BS		 4915 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4916 TCG_AREG0, offsetof(CPUState, fsr),
4917 "fsr");
48d5c82b
BS		 4918 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4919 TCG_AREG0, offsetof(CPUState, pc),
4920 "pc");
4921 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4922 TCG_AREG0, offsetof(CPUState, npc),
4923 "npc");
f5069b26
BS		 4924 for (i = 1; i < 8; i++)
4925 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4926 offsetof(CPUState, gregs[i]),
4927 gregnames[i]);
c9e03d8f
BS		 4928 /* register helpers */
4929
4930#undef DEF_HELPER
4931#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4932#include "helper.h"
1a2fb1c0 4933 }
658138bc 4934}
d2856f1a
AJ		 4935
4936void gen_pc_load(CPUState *env, TranslationBlock *tb,
4937 unsigned long searched_pc, int pc_pos, void *puc)
4938{
4939 target_ulong npc;
4940 env->pc = gen_opc_pc[pc_pos];
4941 npc = gen_opc_npc[pc_pos];
4942 if (npc == 1) {
4943 /* dynamic NPC: already stored */
4944 } else if (npc == 2) {
4945 target_ulong t2 = (target_ulong)(unsigned long)puc;
4946 /* jump PC: use T2 and the jump targets of the translation */
4947 if (t2)
4948 env->npc = gen_opc_jump_pc[0];
4949 else
4950 env->npc = gen_opc_jump_pc[1];
4951 } else {
4952 env->npc = npc;
4953 }
4954}
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