]> git.proxmox.com Git - mirror_qemu.git/blame - target-sparc/translate.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
fixed WP semantics
[mirror_qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
bd497938 5 Copyright (C) 2003 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
bd497938 25 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 26 FPU-Instructions
7a3f1944 27 Privileged instructions
bd497938 28 Coprocessor-Instructions
7a3f1944
FB		 29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
bd497938 31*/
7a3f1944
FB		 32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
45typedef struct DisasContext {
cf495bcf
FB		 46 uint8_t *pc; /* NULL means dynamic value */
47 uint8_t *npc; /* NULL means dynamic value */
48 int is_br;
49 struct TranslationBlock *tb;
7a3f1944
FB		 50} DisasContext;
51
52static uint16_t *gen_opc_ptr;
53static uint32_t *gen_opparam_ptr;
54extern FILE *logfile;
55extern int loglevel;
56
57enum {
58#define DEF(s,n,copy_size) INDEX_op_ ## s,
59#include "opc.h"
60#undef DEF
cf495bcf 61 NB_OPS
7a3f1944
FB		 62};
63
64#include "gen-op.h"
65
66#define GET_FIELD(X, FROM, TO) \
67 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
68
69#define IS_IMM (insn & (1<<13))
70
cf495bcf 71static void disas_sparc_insn(DisasContext * dc);
7a3f1944 72
7a3f1944 73static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 74 {
75 gen_op_movl_g0_T0,
76 gen_op_movl_g1_T0,
77 gen_op_movl_g2_T0,
78 gen_op_movl_g3_T0,
79 gen_op_movl_g4_T0,
80 gen_op_movl_g5_T0,
81 gen_op_movl_g6_T0,
82 gen_op_movl_g7_T0,
83 gen_op_movl_o0_T0,
84 gen_op_movl_o1_T0,
85 gen_op_movl_o2_T0,
86 gen_op_movl_o3_T0,
87 gen_op_movl_o4_T0,
88 gen_op_movl_o5_T0,
89 gen_op_movl_o6_T0,
90 gen_op_movl_o7_T0,
91 gen_op_movl_l0_T0,
92 gen_op_movl_l1_T0,
93 gen_op_movl_l2_T0,
94 gen_op_movl_l3_T0,
95 gen_op_movl_l4_T0,
96 gen_op_movl_l5_T0,
97 gen_op_movl_l6_T0,
98 gen_op_movl_l7_T0,
99 gen_op_movl_i0_T0,
100 gen_op_movl_i1_T0,
101 gen_op_movl_i2_T0,
102 gen_op_movl_i3_T0,
103 gen_op_movl_i4_T0,
104 gen_op_movl_i5_T0,
105 gen_op_movl_i6_T0,
106 gen_op_movl_i7_T0,
107 },
108 {
109 gen_op_movl_g0_T1,
110 gen_op_movl_g1_T1,
111 gen_op_movl_g2_T1,
112 gen_op_movl_g3_T1,
113 gen_op_movl_g4_T1,
114 gen_op_movl_g5_T1,
115 gen_op_movl_g6_T1,
116 gen_op_movl_g7_T1,
117 gen_op_movl_o0_T1,
118 gen_op_movl_o1_T1,
119 gen_op_movl_o2_T1,
120 gen_op_movl_o3_T1,
121 gen_op_movl_o4_T1,
122 gen_op_movl_o5_T1,
123 gen_op_movl_o6_T1,
124 gen_op_movl_o7_T1,
125 gen_op_movl_l0_T1,
126 gen_op_movl_l1_T1,
127 gen_op_movl_l2_T1,
128 gen_op_movl_l3_T1,
129 gen_op_movl_l4_T1,
130 gen_op_movl_l5_T1,
131 gen_op_movl_l6_T1,
132 gen_op_movl_l7_T1,
133 gen_op_movl_i0_T1,
134 gen_op_movl_i1_T1,
135 gen_op_movl_i2_T1,
136 gen_op_movl_i3_T1,
137 gen_op_movl_i4_T1,
138 gen_op_movl_i5_T1,
139 gen_op_movl_i6_T1,
140 gen_op_movl_i7_T1,
141 }
7a3f1944
FB		 142};
143
144static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 145 {
146 gen_op_movl_T0_g0,
147 gen_op_movl_T0_g1,
148 gen_op_movl_T0_g2,
149 gen_op_movl_T0_g3,
150 gen_op_movl_T0_g4,
151 gen_op_movl_T0_g5,
152 gen_op_movl_T0_g6,
153 gen_op_movl_T0_g7,
154 gen_op_movl_T0_o0,
155 gen_op_movl_T0_o1,
156 gen_op_movl_T0_o2,
157 gen_op_movl_T0_o3,
158 gen_op_movl_T0_o4,
159 gen_op_movl_T0_o5,
160 gen_op_movl_T0_o6,
161 gen_op_movl_T0_o7,
162 gen_op_movl_T0_l0,
163 gen_op_movl_T0_l1,
164 gen_op_movl_T0_l2,
165 gen_op_movl_T0_l3,
166 gen_op_movl_T0_l4,
167 gen_op_movl_T0_l5,
168 gen_op_movl_T0_l6,
169 gen_op_movl_T0_l7,
170 gen_op_movl_T0_i0,
171 gen_op_movl_T0_i1,
172 gen_op_movl_T0_i2,
173 gen_op_movl_T0_i3,
174 gen_op_movl_T0_i4,
175 gen_op_movl_T0_i5,
176 gen_op_movl_T0_i6,
177 gen_op_movl_T0_i7,
178 },
179 {
180 gen_op_movl_T1_g0,
181 gen_op_movl_T1_g1,
182 gen_op_movl_T1_g2,
183 gen_op_movl_T1_g3,
184 gen_op_movl_T1_g4,
185 gen_op_movl_T1_g5,
186 gen_op_movl_T1_g6,
187 gen_op_movl_T1_g7,
188 gen_op_movl_T1_o0,
189 gen_op_movl_T1_o1,
190 gen_op_movl_T1_o2,
191 gen_op_movl_T1_o3,
192 gen_op_movl_T1_o4,
193 gen_op_movl_T1_o5,
194 gen_op_movl_T1_o6,
195 gen_op_movl_T1_o7,
196 gen_op_movl_T1_l0,
197 gen_op_movl_T1_l1,
198 gen_op_movl_T1_l2,
199 gen_op_movl_T1_l3,
200 gen_op_movl_T1_l4,
201 gen_op_movl_T1_l5,
202 gen_op_movl_T1_l6,
203 gen_op_movl_T1_l7,
204 gen_op_movl_T1_i0,
205 gen_op_movl_T1_i1,
206 gen_op_movl_T1_i2,
207 gen_op_movl_T1_i3,
208 gen_op_movl_T1_i4,
209 gen_op_movl_T1_i5,
210 gen_op_movl_T1_i6,
211 gen_op_movl_T1_i7,
212 },
213 {
214 gen_op_movl_T2_g0,
215 gen_op_movl_T2_g1,
216 gen_op_movl_T2_g2,
217 gen_op_movl_T2_g3,
218 gen_op_movl_T2_g4,
219 gen_op_movl_T2_g5,
220 gen_op_movl_T2_g6,
221 gen_op_movl_T2_g7,
222 gen_op_movl_T2_o0,
223 gen_op_movl_T2_o1,
224 gen_op_movl_T2_o2,
225 gen_op_movl_T2_o3,
226 gen_op_movl_T2_o4,
227 gen_op_movl_T2_o5,
228 gen_op_movl_T2_o6,
229 gen_op_movl_T2_o7,
230 gen_op_movl_T2_l0,
231 gen_op_movl_T2_l1,
232 gen_op_movl_T2_l2,
233 gen_op_movl_T2_l3,
234 gen_op_movl_T2_l4,
235 gen_op_movl_T2_l5,
236 gen_op_movl_T2_l6,
237 gen_op_movl_T2_l7,
238 gen_op_movl_T2_i0,
239 gen_op_movl_T2_i1,
240 gen_op_movl_T2_i2,
241 gen_op_movl_T2_i3,
242 gen_op_movl_T2_i4,
243 gen_op_movl_T2_i5,
244 gen_op_movl_T2_i6,
245 gen_op_movl_T2_i7,
246 }
7a3f1944
FB		 247};
248
249static GenOpFunc1 *gen_op_movl_TN_im[3] = {
cf495bcf
FB		 250 gen_op_movl_T0_im,
251 gen_op_movl_T1_im,
252 gen_op_movl_T2_im
7a3f1944
FB		 253};
254
cf495bcf 255static inline void gen_movl_imm_TN(int reg, int imm)
7a3f1944 256{
cf495bcf 257 gen_op_movl_TN_im[reg] (imm);
7a3f1944
FB		 258}
259
cf495bcf 260static inline void gen_movl_imm_T1(int val)
7a3f1944 261{
cf495bcf 262 gen_movl_imm_TN(1, val);
7a3f1944
FB		 263}
264
cf495bcf 265static inline void gen_movl_imm_T0(int val)
7a3f1944 266{
cf495bcf 267 gen_movl_imm_TN(0, val);
7a3f1944
FB		 268}
269
cf495bcf 270static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 271{
cf495bcf
FB		 272 if (reg)
273 gen_op_movl_reg_TN[t][reg] ();
274 else
275 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 276}
277
cf495bcf 278static inline void gen_movl_reg_T0(int reg)
7a3f1944 279{
cf495bcf 280 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 281}
282
cf495bcf 283static inline void gen_movl_reg_T1(int reg)
7a3f1944 284{
cf495bcf 285 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 286}
287
cf495bcf 288static inline void gen_movl_reg_T2(int reg)
7a3f1944 289{
cf495bcf 290 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 291}
292
cf495bcf 293static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 294{
cf495bcf
FB		 295 if (reg)
296 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 297}
298
cf495bcf 299static inline void gen_movl_T0_reg(int reg)
7a3f1944 300{
cf495bcf 301 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 302}
303
cf495bcf 304static inline void gen_movl_T1_reg(int reg)
7a3f1944 305{
cf495bcf 306 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 307}
308
cf495bcf 309static void gen_cond(int cond)
7a3f1944 310{
7a3f1944 311 switch (cond) {
cf495bcf
FB		 312 case 0x0:
313 gen_op_movl_T2_0();
314 break;
315 case 0x1:
316 gen_op_eval_be();
317 break;
318 case 0x2:
319 gen_op_eval_ble();
320 break;
321 case 0x3:
322 gen_op_eval_bl();
323 break;
324 case 0x4:
325 gen_op_eval_bleu();
326 break;
327 case 0x5:
328 gen_op_eval_bcs();
329 break;
330 case 0x6:
331 gen_op_eval_bneg();
332 break;
333 case 0x7:
334 gen_op_eval_bvs();
335 break;
336 case 0x8:
337 gen_op_movl_T2_1();
338 break;
339 case 0x9:
340 gen_op_eval_bne();
341 break;
342 case 0xa:
343 gen_op_eval_bg();
344 break;
345 case 0xb:
346 gen_op_eval_bge();
347 break;
348 case 0xc:
349 gen_op_eval_bgu();
350 break;
351 case 0xd:
352 gen_op_eval_bcc();
353 break;
354 case 0xe:
355 gen_op_eval_bpos();
356 break;
357 default:
358 case 0xf:
359 gen_op_eval_bvc();
360 break;
7a3f1944 361 }
7a3f1944
FB		 362}
363
cf495bcf
FB		 364
365static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn)
7a3f1944 366{
cf495bcf
FB		 367 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
368 target += (uint32_t) dc->pc;
369 if (cond == 0x0) {
370 /* unconditional not taken */
371 if (a) {
372 dc->pc = dc->npc + 4;
373 dc->npc = dc->pc + 4;
374 } else {
375 dc->pc = dc->npc;
376 dc->npc = dc->pc + 4;
377 }
378 } else if (cond == 0x8) {
379 /* unconditional taken */
380 if (a) {
381 dc->pc = (uint8_t *) target;
382 dc->npc = dc->pc + 4;
383 } else {
384 dc->pc = dc->npc;
385 dc->npc = (uint8_t *) target;
386 }
387 } else {
388 gen_cond(cond);
389 if (a) {
390 gen_op_generic_branch_a((uint32_t) target,
391 (uint32_t) (dc->npc));
392 dc->is_br = 1;
393 dc->pc = NULL;
394 dc->npc = NULL;
395 } else {
396 dc->pc = dc->npc;
397 gen_op_generic_branch((uint32_t) target,
398 (uint32_t) (dc->npc + 4));
399 dc->npc = NULL;
400 }
401 }
7a3f1944
FB		 402}
403
cf495bcf 404#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
7a3f1944 405
cf495bcf 406static int sign_extend(int x, int len)
7a3f1944 407{
cf495bcf
FB		 408 len = 32 - len;
409 return (x << len) >> len;
7a3f1944
FB		 410}
411
cf495bcf 412static inline void save_state(DisasContext * dc)
7a3f1944 413{
cf495bcf
FB		 414 gen_op_jmp_im((uint32_t)dc->pc);
415 if (dc->npc != NULL)
416 gen_op_movl_npc_im((long) dc->npc);
417}
7a3f1944 418
cf495bcf
FB		 419static void disas_sparc_insn(DisasContext * dc)
420{
421 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 422
cf495bcf
FB		 423 insn = ldl_code(dc->pc);
424 opc = GET_FIELD(insn, 0, 1);
7a3f1944 425
cf495bcf
FB		 426 rd = GET_FIELD(insn, 2, 6);
427 switch (opc) {
428 case 0: /* branches/sethi */
429 {
430 unsigned int xop = GET_FIELD(insn, 7, 9);
431 int target;
432 target = GET_FIELD(insn, 10, 31);
433 switch (xop) {
434 case 0x0:
435 case 0x1: /* UNIMPL */
436 goto illegal_insn;
437 case 0x2: /* BN+x */
7a3f1944 438 {
cf495bcf
FB		 439 target <<= 2;
440 target = sign_extend(target, 22);
441 do_branch(dc, target, insn);
442 goto jmp_insn;
7a3f1944 443 }
cf495bcf
FB		 444 case 0x3: /* FBN+x */
445 break;
446 case 0x4: /* SETHI */
447 gen_movl_imm_T0(target << 10);
448 gen_movl_T0_reg(rd);
449 break;
450 case 0x5: /*CBN+x */
451 break;
452 }
453 break;
454 }
455 case 1:
456 /*CALL*/ {
457 unsigned int target = GET_FIELDs(insn, 2, 31) << 2;
458
459 gen_op_movl_T0_im((long) (dc->pc));
460 gen_movl_T0_reg(15);
461 target = (long) dc->pc + target;
462 dc->pc = dc->npc;
463 dc->npc = (uint8_t *) target;
464 }
465 goto jmp_insn;
466 case 2: /* FPU & Logical Operations */
467 {
468 unsigned int xop = GET_FIELD(insn, 7, 12);
469 if (xop == 0x3a) { /* generate trap */
470 int cond;
471 rs1 = GET_FIELD(insn, 13, 17);
472 gen_movl_reg_T0(rs1);
473 if (IS_IMM) {
474 gen_movl_imm_T1(GET_FIELD(insn, 25, 31));
475 } else {
476 rs2 = GET_FIELD(insn, 27, 31);
477 gen_movl_reg_T1(rs2);
478 }
479 gen_op_add_T1_T0();
480 save_state(dc);
481 cond = GET_FIELD(insn, 3, 6);
482 if (cond == 0x8) {
483 gen_op_trap_T0();
484 dc->is_br = 1;
485 goto jmp_insn;
486 } else {
487 gen_op_trapcc_T0();
488 }
489 } else if (xop == 0x28) {
490 rs1 = GET_FIELD(insn, 13, 17);
491 switch(rs1) {
492 case 0: /* rdy */
493 gen_op_rdy();
494 gen_movl_T0_reg(rd);
495 break;
496 default:
497 goto illegal_insn;
498 }
499 } else if (xop == 0x34 || xop == 0x35) { /* FPU Operations */
500 goto illegal_insn;
501 } else {
502 rs1 = GET_FIELD(insn, 13, 17);
503 gen_movl_reg_T0(rs1);
504 if (IS_IMM) { /* immediate */
505 rs2 = GET_FIELDs(insn, 19, 31);
506 gen_movl_imm_T1(rs2);
507 } else { /* register */
508 rs2 = GET_FIELD(insn, 27, 31);
509 gen_movl_reg_T1(rs2);
510 }
511 if (xop < 0x20) {
512 switch (xop & ~0x10) {
513 case 0x0:
514 if (xop & 0x10)
515 gen_op_add_T1_T0_cc();
516 else
517 gen_op_add_T1_T0();
518 break;
519 case 0x1:
520 gen_op_and_T1_T0();
521 if (xop & 0x10)
522 gen_op_logic_T0_cc();
523 break;
524 case 0x2:
525 gen_op_or_T1_T0();
526 if (xop & 0x10)
527 gen_op_logic_T0_cc();
528 break;
529 case 0x3:
530 gen_op_xor_T1_T0();
531 if (xop & 0x10)
532 gen_op_logic_T0_cc();
533 break;
534 case 0x4:
535 if (xop & 0x10)
536 gen_op_sub_T1_T0_cc();
537 else
538 gen_op_sub_T1_T0();
539 break;
540 case 0x5:
541 gen_op_andn_T1_T0();
542 if (xop & 0x10)
543 gen_op_logic_T0_cc();
544 break;
545 case 0x6:
546 gen_op_orn_T1_T0();
547 if (xop & 0x10)
548 gen_op_logic_T0_cc();
549 break;
550 case 0x7:
551 gen_op_xnor_T1_T0();
552 if (xop & 0x10)
553 gen_op_logic_T0_cc();
554 break;
555 case 0x8:
556 gen_op_addx_T1_T0();
557 if (xop & 0x10)
558 gen_op_set_flags();
559 break;
560 case 0xa:
561 gen_op_umul_T1_T0();
562 if (xop & 0x10)
563 gen_op_logic_T0_cc();
564 break;
565 case 0xb:
566 gen_op_smul_T1_T0();
567 if (xop & 0x10)
568 gen_op_logic_T0_cc();
569 break;
570 case 0xc:
571 gen_op_subx_T1_T0();
572 if (xop & 0x10)
573 gen_op_set_flags();
574 break;
575 case 0xe:
576 gen_op_udiv_T1_T0();
577 if (xop & 0x10)
578 gen_op_div_cc();
579 break;
580 case 0xf:
581 gen_op_sdiv_T1_T0();
582 if (xop & 0x10)
583 gen_op_div_cc();
584 break;
585 default:
586 goto illegal_insn;
587 }
588 gen_movl_T0_reg(rd);
589 } else {
590 switch (xop) {
591 case 0x24: /* mulscc */
592 gen_op_mulscc_T1_T0();
593 gen_movl_T0_reg(rd);
594 break;
595 case 0x25: /* SLL */
596 gen_op_sll();
597 gen_movl_T0_reg(rd);
598 break;
599 case 0x26:
600 gen_op_srl();
601 gen_movl_T0_reg(rd);
602 break;
603 case 0x27:
604 gen_op_sra();
605 gen_movl_T0_reg(rd);
606 break;
607 case 0x30:
608 {
609 gen_op_xor_T1_T0();
610 switch(rd) {
611 case 0:
612 gen_op_wry();
613 break;
614 default:
615 goto illegal_insn;
616 }
617 }
618 break;
619 case 0x38: /* jmpl */
620 {
621 gen_op_add_T1_T0();
622 gen_op_movl_npc_T0();
623 if (rd != 0) {
624 gen_op_movl_T0_im((long) (dc->pc));
625 gen_movl_T0_reg(rd);
626 }
627 dc->pc = dc->npc;
628 dc->npc = NULL;
629 }
630 goto jmp_insn;
631 case 0x3b: /* flush */
632 /* nothing to do */
633 break;
634 case 0x3c: /* save */
635 save_state(dc);
636 gen_op_add_T1_T0();
637 gen_op_save();
638 gen_movl_T0_reg(rd);
639 break;
640 case 0x3d: /* restore */
641 save_state(dc);
642 gen_op_add_T1_T0();
643 gen_op_restore();
644 gen_movl_T0_reg(rd);
645 break;
646 default:
647 goto illegal_insn;
648 }
649 }
650 }
651 break;
652 }
653 case 3: /* load/store instructions */
654 {
655 unsigned int xop = GET_FIELD(insn, 7, 12);
656 rs1 = GET_FIELD(insn, 13, 17);
657 gen_movl_reg_T0(rs1);
658 if (IS_IMM) { /* immediate */
659 rs2 = GET_FIELDs(insn, 19, 31);
660 gen_movl_imm_T1(rs2);
661 } else { /* register */
662 rs2 = GET_FIELD(insn, 27, 31);
663 gen_movl_reg_T1(rs2);
664 }
665 gen_op_add_T1_T0();
666 if (xop < 4 || xop > 7) {
667 switch (xop) {
668 case 0x0: /* load word */
669 gen_op_ld();
670 break;
671 case 0x1: /* load unsigned byte */
672 gen_op_ldub();
673 break;
674 case 0x2: /* load unsigned halfword */
675 gen_op_lduh();
676 break;
677 case 0x3: /* load double word */
678 gen_op_ldd();
679 gen_movl_T0_reg(rd + 1);
680 break;
681 case 0x9: /* load signed byte */
682 gen_op_ldsb();
683 break;
684 case 0xa: /* load signed halfword */
685 gen_op_ldsh();
686 break;
687 case 0xd: /* ldstub -- XXX: should be atomically */
688 gen_op_ldstub();
689 break;
690 case 0x0f: /* swap register with memory. Also atomically */
691 gen_op_swap();
692 break;
7a3f1944 693 }
cf495bcf
FB		 694 gen_movl_T1_reg(rd);
695 } else if (xop < 8) {
696 gen_movl_reg_T1(rd);
697 switch (xop) {
698 case 0x4:
699 gen_op_st();
700 break;
701 case 0x5:
702 gen_op_stb();
703 break;
704 case 0x6:
705 gen_op_sth();
706 break;
707 case 0x7:
708 gen_movl_reg_T2(rd + 1);
709 gen_op_std();
710 break;
7a3f1944 711 }
cf495bcf 712 }
7a3f1944 713 }
cf495bcf
FB		 714 }
715 /* default case for non jump instructions */
716 if (dc->npc != NULL) {
717 dc->pc = dc->npc;
718 dc->npc = dc->npc + 4;
719 } else {
720 dc->pc = NULL;
721 gen_op_next_insn();
722 }
723 jmp_insn:;
724 return;
725 illegal_insn:
726 gen_op_jmp_im((uint32_t)dc->pc);
727 if (dc->npc != NULL)
728 gen_op_movl_npc_im((long) dc->npc);
729 gen_op_exception(TT_ILL_INSN);
730 dc->is_br = 1;
7a3f1944
FB		 731}
732
cf495bcf
FB		 733static inline int gen_intermediate_code_internal(TranslationBlock * tb,
734 int spc)
7a3f1944 735{
cf495bcf
FB		 736 uint8_t *pc_start, *last_pc;
737 uint16_t *gen_opc_end;
738 DisasContext dc1, *dc = &dc1;
739
740 memset(dc, 0, sizeof(DisasContext));
741 if (spc) {
742 printf("SearchPC not yet supported\n");
743 exit(0);
744 }
745 dc->tb = tb;
746 pc_start = (uint8_t *) tb->pc;
747 dc->pc = pc_start;
748 dc->npc = (uint8_t *) tb->cs_base;
749
750 gen_opc_ptr = gen_opc_buf;
751 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
752 gen_opparam_ptr = gen_opparam_buf;
753
754 do {
755 last_pc = dc->pc;
756 disas_sparc_insn(dc);
757 if (dc->is_br)
758 break;
759 /* if the next PC is different, we abort now */
760 if (dc->pc != (last_pc + 4))
761 break;
762 } while ((gen_opc_ptr < gen_opc_end) &&
763 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
764 if (dc->pc != NULL)
765 gen_op_jmp_im((long) dc->pc);
766 if (dc->npc != NULL)
767 gen_op_movl_npc_im((long) dc->npc);
768 gen_op_movl_T0_0();
769 gen_op_exit_tb();
770
771 *gen_opc_ptr = INDEX_op_end;
7a3f1944 772#ifdef DEBUG_DISAS
cf495bcf
FB		 773 if (loglevel) {
774 fprintf(logfile, "--------------\n");
775 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
776 disas(logfile, pc_start, last_pc + 4 - pc_start, 0, 0);
777 fprintf(logfile, "\n");
778 fprintf(logfile, "OP:\n");
779 dump_ops(gen_opc_buf, gen_opparam_buf);
780 fprintf(logfile, "\n");
781 }
7a3f1944
FB		 782#endif
783
cf495bcf 784 return 0;
7a3f1944
FB		 785}
786
cf495bcf 787int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 788{
cf495bcf 789 return gen_intermediate_code_internal(tb, 0);
7a3f1944
FB		 790}
791
cf495bcf 792int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 793{
cf495bcf 794 return gen_intermediate_code_internal(tb, 1);
7a3f1944
FB		 795}
796
cf495bcf 797CPUSPARCState *cpu_sparc_init(void)
7a3f1944 798{
cf495bcf
FB		 799 CPUSPARCState *env;
800
801 cpu_exec_init();
802
803 if (!(env = malloc(sizeof(CPUSPARCState))))
804 return (NULL);
805 memset(env, 0, sizeof(*env));
806 env->cwp = 0;
807 env->wim = 1;
808 env->regwptr = env->regbase + (env->cwp * 16);
809 env->user_mode_only = 1;
810 return (env);
7a3f1944
FB		 811}
812
813#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
814
cf495bcf 815void cpu_sparc_dump_state(CPUSPARCState * env, FILE * f, int flags)
7a3f1944 816{
cf495bcf
FB		 817 int i, x;
818
819 fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc);
820 fprintf(f, "General Registers:\n");
821 for (i = 0; i < 4; i++)
822 fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
823 fprintf(f, "\n");
824 for (; i < 8; i++)
825 fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
826 fprintf(f, "\nCurrent Register Window:\n");
827 for (x = 0; x < 3; x++) {
828 for (i = 0; i < 4; i++)
829 fprintf(f, "%%%c%d: 0x%08x\t",
830 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
831 env->regwptr[i + x * 8]);
832 fprintf(f, "\n");
833 for (; i < 8; i++)
834 fprintf(f, "%%%c%d: 0x%08x\t",
835 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
836 env->regwptr[i + x * 8]);
837 fprintf(f, "\n");
838 }
839 fprintf(f, "psr: 0x%08x -> %c%c%c%c wim: 0x%08x\n", env->psr | env->cwp,
840 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
841 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
842 env->wim);
7a3f1944 843}
edfcbd99
FB		 844
845target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
846{
847 return addr;
848}
QEMU mirror