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tcg: Remove gen_intermediate_code_pc
[mirror_qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
7a3f1944
FB		 21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
76cad711 28#include "disas/disas.h"
2ef6175a 29#include "exec/helper-proto.h"
57fec1fe 30#include "tcg-op.h"
f08b6170 31#include "exec/cpu_ldst.h"
7a3f1944 32
2ef6175a 33#include "exec/helper-gen.h"
a7812ae4 34
a7e30d84
LV		 35#include "trace-tcg.h"
36
37
7a3f1944
FB		 38#define DEBUG_DISAS
39
72cbca10
FB		 40#define DYNAMIC_PC 1 /* dynamic pc value */
41#define JUMP_PC 2 /* dynamic pc value which takes only two values
42 according to jump_pc[T2] */
43
1a2fb1c0 44/* global register indexes */
a7812ae4 45static TCGv_ptr cpu_env, cpu_regwptr;
25517f99
PB		 46static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
47static TCGv_i32 cpu_cc_op;
a7812ae4
PB		 48static TCGv_i32 cpu_psr;
49static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
255e1fcb
BS		 50static TCGv cpu_y;
51#ifndef CONFIG_USER_ONLY
52static TCGv cpu_tbr;
53#endif
5793f2a4 54static TCGv cpu_cond;
dc99a3f2 55#ifdef TARGET_SPARC64
a7812ae4
PB		 56static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
57static TCGv cpu_gsr;
255e1fcb 58static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4
PB		 59static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
60static TCGv_i32 cpu_softint;
255e1fcb
BS		 61#else
62static TCGv cpu_wim;
dc99a3f2 63#endif
714547bb 64/* Floating point registers */
30038fd8 65static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 66
022c62cb 67#include "exec/gen-icount.h"
2e70f6ef 68
7a3f1944 69typedef struct DisasContext {
0f8a249a
BS		 70 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
71 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 72 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 73 int is_br;
e8af50a3 74 int mem_idx;
a80dde08 75 int fpu_enabled;
2cade6a3 76 int address_mask_32bit;
060718c1 77 int singlestep;
8393617c 78 uint32_t cc_op; /* current CC operation */
cf495bcf 79 struct TranslationBlock *tb;
5578ceab 80 sparc_def_t *def;
30038fd8 81 TCGv_i32 t32[3];
88023616 82 TCGv ttl[5];
30038fd8 83 int n_t32;
88023616 84 int n_ttl;
7a3f1944
FB		 85} DisasContext;
86
416fcaea
RH		 87typedef struct {
88 TCGCond cond;
89 bool is_bool;
90 bool g1, g2;
91 TCGv c1, c2;
92} DisasCompare;
93
3475187d 94// This function uses non-native bit order
dc1a6971
BS		 95#define GET_FIELD(X, FROM, TO) \
96 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 97
3475187d 98// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 99#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 100 GET_FIELD(X, 31 - (TO), 31 - (FROM))
101
102#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 103#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 104
105#ifdef TARGET_SPARC64
0387d928 106#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 107#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 108#else
c185970a 109#define DFPREG(r) (r & 0x1e)
1f587329 110#define QFPREG(r) (r & 0x1c)
3475187d
FB		 111#endif
112
b158a785
BS		 113#define UA2005_HTRAP_MASK 0xff
114#define V8_TRAP_MASK 0x7f
115
3475187d
FB		 116static int sign_extend(int x, int len)
117{
118 len = 32 - len;
119 return (x << len) >> len;
120}
121
7a3f1944
FB		 122#define IS_IMM (insn & (1<<13))
123
2ae23e17
RH		 124static inline TCGv_i32 get_temp_i32(DisasContext *dc)
125{
126 TCGv_i32 t;
127 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
128 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
129 return t;
130}
131
132static inline TCGv get_temp_tl(DisasContext *dc)
133{
134 TCGv t;
135 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
136 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
137 return t;
138}
139
141ae5c1
RH		 140static inline void gen_update_fprs_dirty(int rd)
141{
142#if defined(TARGET_SPARC64)
143 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
144#endif
145}
146
ff07ec83 147/* floating point registers moves */
208ae657
RH		 148static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
149{
30038fd8
RH		 150#if TCG_TARGET_REG_BITS == 32
151 if (src & 1) {
152 return TCGV_LOW(cpu_fpr[src / 2]);
153 } else {
154 return TCGV_HIGH(cpu_fpr[src / 2]);
155 }
156#else
157 if (src & 1) {
158 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
159 } else {
2ae23e17 160 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 161 TCGv_i64 t = tcg_temp_new_i64();
162
163 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 164 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 165 tcg_temp_free_i64(t);
166
30038fd8
RH		 167 return ret;
168 }
169#endif
208ae657
RH		 170}
171
172static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
173{
30038fd8
RH		 174#if TCG_TARGET_REG_BITS == 32
175 if (dst & 1) {
176 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
177 } else {
178 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
179 }
180#else
181 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
182 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
183 (dst & 1 ? 0 : 32), 32);
184#endif
141ae5c1 185 gen_update_fprs_dirty(dst);
208ae657
RH		 186}
187
ba5f5179 188static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 189{
ba5f5179 190 return get_temp_i32(dc);
208ae657
RH		 191}
192
96eda024
RH		 193static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
194{
96eda024 195 src = DFPREG(src);
30038fd8 196 return cpu_fpr[src / 2];
96eda024
RH		 197}
198
199static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
200{
201 dst = DFPREG(dst);
30038fd8 202 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 203 gen_update_fprs_dirty(dst);
204}
205
3886b8a3 206static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 207{
3886b8a3 208 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 209}
210
ff07ec83
BS		 211static void gen_op_load_fpr_QT0(unsigned int src)
212{
30038fd8
RH		 213 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
214 offsetof(CPU_QuadU, ll.upper));
215 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
216 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 217}
218
219static void gen_op_load_fpr_QT1(unsigned int src)
220{
30038fd8
RH		 221 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
222 offsetof(CPU_QuadU, ll.upper));
223 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
224 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 225}
226
227static void gen_op_store_QT0_fpr(unsigned int dst)
228{
30038fd8
RH		 229 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
230 offsetof(CPU_QuadU, ll.upper));
231 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
232 offsetof(CPU_QuadU, ll.lower));
ff07ec83 233}
1f587329 234
ac11f776 235#ifdef TARGET_SPARC64
30038fd8 236static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 237{
238 rd = QFPREG(rd);
239 rs = QFPREG(rs);
240
30038fd8
RH		 241 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
242 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 243 gen_update_fprs_dirty(rd);
244}
245#endif
246
81ad8ba2
BS		 247/* moves */
248#ifdef CONFIG_USER_ONLY
3475187d 249#define supervisor(dc) 0
81ad8ba2 250#ifdef TARGET_SPARC64
e9ebed4d 251#define hypervisor(dc) 0
81ad8ba2 252#endif
3475187d 253#else
2aae2b8e 254#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 255#ifdef TARGET_SPARC64
2aae2b8e 256#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 257#else
3475187d 258#endif
81ad8ba2
BS		 259#endif
260
2cade6a3
BS		 261#ifdef TARGET_SPARC64
262#ifndef TARGET_ABI32
263#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 264#else
2cade6a3
BS		 265#define AM_CHECK(dc) (1)
266#endif
1a2fb1c0 267#endif
3391c818 268
2cade6a3
BS		 269static inline void gen_address_mask(DisasContext *dc, TCGv addr)
270{
271#ifdef TARGET_SPARC64
272 if (AM_CHECK(dc))
273 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
274#endif
275}
276
88023616
RH		 277static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
278{
279 if (reg == 0 || reg >= 8) {
280 TCGv t = get_temp_tl(dc);
281 if (reg == 0) {
282 tcg_gen_movi_tl(t, 0);
283 } else {
284 tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
285 }
286 return t;
287 } else {
288 return cpu_gregs[reg];
289 }
290}
291
292static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
293{
294 if (reg > 0) {
295 if (reg < 8) {
296 tcg_gen_mov_tl(cpu_gregs[reg], v);
297 } else {
298 tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
299 }
300 }
301}
302
303static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
304{
305 if (reg == 0 || reg >= 8) {
306 return get_temp_tl(dc);
307 } else {
308 return cpu_gregs[reg];
309 }
310}
311
5fafdf24 312static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 313 target_ulong pc, target_ulong npc)
314{
315 TranslationBlock *tb;
316
317 tb = s->tb;
318 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
060718c1
RH		 319 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
320 !s->singlestep) {
6e256c93 321 /* jump to same page: we can use a direct jump */
57fec1fe 322 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 323 tcg_gen_movi_tl(cpu_pc, pc);
324 tcg_gen_movi_tl(cpu_npc, npc);
8cfd0495 325 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
6e256c93
FB		 326 } else {
327 /* jump to another page: currently not optimized */
2f5680ee
BS		 328 tcg_gen_movi_tl(cpu_pc, pc);
329 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 330 tcg_gen_exit_tb(0);
6e256c93
FB		 331 }
332}
333
19f329ad 334// XXX suboptimal
a7812ae4 335static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 336{
8911f501 337 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 338 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 339 tcg_gen_andi_tl(reg, reg, 0x1);
340}
341
a7812ae4 342static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 343{
8911f501 344 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 345 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 346 tcg_gen_andi_tl(reg, reg, 0x1);
347}
348
a7812ae4 349static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 350{
8911f501 351 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 352 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 353 tcg_gen_andi_tl(reg, reg, 0x1);
354}
355
a7812ae4 356static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 357{
8911f501 358 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 359 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 360 tcg_gen_andi_tl(reg, reg, 0x1);
361}
362
4af984a7 363static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 364{
4af984a7 365 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 366 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 367 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 368 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 369}
370
70c48285 371static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 372{
70c48285
RH		 373 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
374
375 /* Carry is computed from a previous add: (dst < src) */
376#if TARGET_LONG_BITS == 64
377 cc_src1_32 = tcg_temp_new_i32();
378 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 379 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
380 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 381#else
382 cc_src1_32 = cpu_cc_dst;
383 cc_src2_32 = cpu_cc_src;
384#endif
385
386 carry_32 = tcg_temp_new_i32();
387 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
388
389#if TARGET_LONG_BITS == 64
390 tcg_temp_free_i32(cc_src1_32);
391 tcg_temp_free_i32(cc_src2_32);
392#endif
393
394 return carry_32;
41d72852
BS		 395}
396
70c48285 397static TCGv_i32 gen_sub32_carry32(void)
41d72852 398{
70c48285
RH		 399 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
400
401 /* Carry is computed from a previous borrow: (src1 < src2) */
402#if TARGET_LONG_BITS == 64
403 cc_src1_32 = tcg_temp_new_i32();
404 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 405 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
406 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 407#else
408 cc_src1_32 = cpu_cc_src;
409 cc_src2_32 = cpu_cc_src2;
410#endif
411
412 carry_32 = tcg_temp_new_i32();
413 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
414
415#if TARGET_LONG_BITS == 64
416 tcg_temp_free_i32(cc_src1_32);
417 tcg_temp_free_i32(cc_src2_32);
418#endif
419
420 return carry_32;
421}
422
423static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
424 TCGv src2, int update_cc)
425{
426 TCGv_i32 carry_32;
427 TCGv carry;
428
429 switch (dc->cc_op) {
430 case CC_OP_DIV:
431 case CC_OP_LOGIC:
432 /* Carry is known to be zero. Fall back to plain ADD. */
433 if (update_cc) {
434 gen_op_add_cc(dst, src1, src2);
435 } else {
436 tcg_gen_add_tl(dst, src1, src2);
437 }
438 return;
439
440 case CC_OP_ADD:
441 case CC_OP_TADD:
442 case CC_OP_TADDTV:
15fe216f
RH		 443 if (TARGET_LONG_BITS == 32) {
444 /* We can re-use the host's hardware carry generation by using
445 an ADD2 opcode. We discard the low part of the output.
446 Ideally we'd combine this operation with the add that
447 generated the carry in the first place. */
448 carry = tcg_temp_new();
449 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
450 tcg_temp_free(carry);
70c48285
RH		 451 goto add_done;
452 }
70c48285
RH		 453 carry_32 = gen_add32_carry32();
454 break;
455
456 case CC_OP_SUB:
457 case CC_OP_TSUB:
458 case CC_OP_TSUBTV:
459 carry_32 = gen_sub32_carry32();
460 break;
461
462 default:
463 /* We need external help to produce the carry. */
464 carry_32 = tcg_temp_new_i32();
2ffd9176 465 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 466 break;
467 }
468
469#if TARGET_LONG_BITS == 64
470 carry = tcg_temp_new();
471 tcg_gen_extu_i32_i64(carry, carry_32);
472#else
473 carry = carry_32;
474#endif
475
476 tcg_gen_add_tl(dst, src1, src2);
477 tcg_gen_add_tl(dst, dst, carry);
478
479 tcg_temp_free_i32(carry_32);
480#if TARGET_LONG_BITS == 64
481 tcg_temp_free(carry);
482#endif
483
70c48285 484 add_done:
70c48285
RH		 485 if (update_cc) {
486 tcg_gen_mov_tl(cpu_cc_src, src1);
487 tcg_gen_mov_tl(cpu_cc_src2, src2);
488 tcg_gen_mov_tl(cpu_cc_dst, dst);
489 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
490 dc->cc_op = CC_OP_ADDX;
491 }
dc99a3f2
BS		 492}
493
41d72852 494static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 495{
4af984a7 496 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 497 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 498 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 499 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 500}
501
70c48285
RH		 502static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
503 TCGv src2, int update_cc)
41d72852 504{
70c48285
RH		 505 TCGv_i32 carry_32;
506 TCGv carry;
41d72852 507
70c48285
RH		 508 switch (dc->cc_op) {
509 case CC_OP_DIV:
510 case CC_OP_LOGIC:
511 /* Carry is known to be zero. Fall back to plain SUB. */
512 if (update_cc) {
513 gen_op_sub_cc(dst, src1, src2);
514 } else {
515 tcg_gen_sub_tl(dst, src1, src2);
516 }
517 return;
518
519 case CC_OP_ADD:
520 case CC_OP_TADD:
521 case CC_OP_TADDTV:
522 carry_32 = gen_add32_carry32();
523 break;
524
525 case CC_OP_SUB:
526 case CC_OP_TSUB:
527 case CC_OP_TSUBTV:
15fe216f
RH		 528 if (TARGET_LONG_BITS == 32) {
529 /* We can re-use the host's hardware carry generation by using
530 a SUB2 opcode. We discard the low part of the output.
531 Ideally we'd combine this operation with the add that
532 generated the carry in the first place. */
533 carry = tcg_temp_new();
534 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
535 tcg_temp_free(carry);
70c48285
RH		 536 goto sub_done;
537 }
70c48285
RH		 538 carry_32 = gen_sub32_carry32();
539 break;
540
541 default:
542 /* We need external help to produce the carry. */
543 carry_32 = tcg_temp_new_i32();
2ffd9176 544 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 545 break;
546 }
547
548#if TARGET_LONG_BITS == 64
549 carry = tcg_temp_new();
550 tcg_gen_extu_i32_i64(carry, carry_32);
551#else
552 carry = carry_32;
553#endif
554
555 tcg_gen_sub_tl(dst, src1, src2);
556 tcg_gen_sub_tl(dst, dst, carry);
557
558 tcg_temp_free_i32(carry_32);
559#if TARGET_LONG_BITS == 64
560 tcg_temp_free(carry);
561#endif
562
70c48285 563 sub_done:
70c48285
RH		 564 if (update_cc) {
565 tcg_gen_mov_tl(cpu_cc_src, src1);
566 tcg_gen_mov_tl(cpu_cc_src2, src2);
567 tcg_gen_mov_tl(cpu_cc_dst, dst);
568 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
569 dc->cc_op = CC_OP_SUBX;
570 }
dc99a3f2
BS		 571}
572
4af984a7 573static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 574{
de9e9d9f 575 TCGv r_temp, zero, t0;
d9bdab86 576
a7812ae4 577 r_temp = tcg_temp_new();
de9e9d9f 578 t0 = tcg_temp_new();
d9bdab86
BS		 579
580 /* old op:
581 if (!(env->y & 1))
582 T1 = 0;
583 */
6cb675b0 584 zero = tcg_const_tl(0);
72ccba79 585 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 586 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 587 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 588 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
589 zero, cpu_cc_src2);
590 tcg_temp_free(zero);
d9bdab86
BS		 591
592 // b2 = T0 & 1;
593 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 594 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
595 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 596 tcg_gen_shri_tl(t0, cpu_y, 1);
597 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
598 tcg_gen_or_tl(t0, t0, r_temp);
599 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 600
601 // b1 = N ^ V;
de9e9d9f 602 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 603 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 604 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 605 tcg_temp_free(r_temp);
d9bdab86
BS		 606
607 // T0 = (b1 << 31) | (T0 >> 1);
608 // src1 = T0;
de9e9d9f 609 tcg_gen_shli_tl(t0, t0, 31);
6f551262 610 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 611 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
612 tcg_temp_free(t0);
d9bdab86 613
5c6a0628 614 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 615
5c6a0628 616 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 617}
618
fb170183 619static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 620{
528692a8 621#if TARGET_LONG_BITS == 32
fb170183 622 if (sign_ext) {
528692a8 623 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 624 } else {
528692a8 625 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 626 }
528692a8
RH		 627#else
628 TCGv t0 = tcg_temp_new_i64();
629 TCGv t1 = tcg_temp_new_i64();
fb170183 630
528692a8
RH		 631 if (sign_ext) {
632 tcg_gen_ext32s_i64(t0, src1);
633 tcg_gen_ext32s_i64(t1, src2);
634 } else {
635 tcg_gen_ext32u_i64(t0, src1);
636 tcg_gen_ext32u_i64(t1, src2);
637 }
fb170183 638
528692a8
RH		 639 tcg_gen_mul_i64(dst, t0, t1);
640 tcg_temp_free(t0);
641 tcg_temp_free(t1);
fb170183 642
528692a8
RH		 643 tcg_gen_shri_i64(cpu_y, dst, 32);
644#endif
8879d139
BS		 645}
646
fb170183 647static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 648{
fb170183
IK		 649 /* zero-extend truncated operands before multiplication */
650 gen_op_multiply(dst, src1, src2, 0);
651}
8879d139 652
fb170183
IK		 653static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
654{
655 /* sign-extend truncated operands before multiplication */
656 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 657}
658
19f329ad
BS		 659// 1
660static inline void gen_op_eval_ba(TCGv dst)
661{
662 tcg_gen_movi_tl(dst, 1);
663}
664
665// Z
a7812ae4 666static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 667{
668 gen_mov_reg_Z(dst, src);
669}
670
671// Z | (N ^ V)
a7812ae4 672static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 673{
de9e9d9f
RH		 674 TCGv t0 = tcg_temp_new();
675 gen_mov_reg_N(t0, src);
19f329ad 676 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 677 tcg_gen_xor_tl(dst, dst, t0);
678 gen_mov_reg_Z(t0, src);
679 tcg_gen_or_tl(dst, dst, t0);
680 tcg_temp_free(t0);
19f329ad
BS		 681}
682
683// N ^ V
a7812ae4 684static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 685{
de9e9d9f
RH		 686 TCGv t0 = tcg_temp_new();
687 gen_mov_reg_V(t0, src);
19f329ad 688 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 689 tcg_gen_xor_tl(dst, dst, t0);
690 tcg_temp_free(t0);
19f329ad
BS		 691}
692
693// C | Z
a7812ae4 694static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 695{
de9e9d9f
RH		 696 TCGv t0 = tcg_temp_new();
697 gen_mov_reg_Z(t0, src);
19f329ad 698 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 699 tcg_gen_or_tl(dst, dst, t0);
700 tcg_temp_free(t0);
19f329ad
BS		 701}
702
703// C
a7812ae4 704static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 705{
706 gen_mov_reg_C(dst, src);
707}
708
709// V
a7812ae4 710static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 711{
712 gen_mov_reg_V(dst, src);
713}
714
715// 0
716static inline void gen_op_eval_bn(TCGv dst)
717{
718 tcg_gen_movi_tl(dst, 0);
719}
720
721// N
a7812ae4 722static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 723{
724 gen_mov_reg_N(dst, src);
725}
726
727// !Z
a7812ae4 728static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 729{
730 gen_mov_reg_Z(dst, src);
731 tcg_gen_xori_tl(dst, dst, 0x1);
732}
733
734// !(Z | (N ^ V))
a7812ae4 735static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 736{
de9e9d9f 737 gen_op_eval_ble(dst, src);
19f329ad
BS		 738 tcg_gen_xori_tl(dst, dst, 0x1);
739}
740
741// !(N ^ V)
a7812ae4 742static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 743{
de9e9d9f 744 gen_op_eval_bl(dst, src);
19f329ad
BS		 745 tcg_gen_xori_tl(dst, dst, 0x1);
746}
747
748// !(C | Z)
a7812ae4 749static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 750{
de9e9d9f 751 gen_op_eval_bleu(dst, src);
19f329ad
BS		 752 tcg_gen_xori_tl(dst, dst, 0x1);
753}
754
755// !C
a7812ae4 756static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 757{
758 gen_mov_reg_C(dst, src);
759 tcg_gen_xori_tl(dst, dst, 0x1);
760}
761
762// !N
a7812ae4 763static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 764{
765 gen_mov_reg_N(dst, src);
766 tcg_gen_xori_tl(dst, dst, 0x1);
767}
768
769// !V
a7812ae4 770static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 771{
772 gen_mov_reg_V(dst, src);
773 tcg_gen_xori_tl(dst, dst, 0x1);
774}
775
776/*
777 FPSR bit field FCC1 | FCC0:
778 0 =
779 1 <
780 2 >
781 3 unordered
782*/
783static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
784 unsigned int fcc_offset)
785{
ba6a9d8c 786 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 787 tcg_gen_andi_tl(reg, reg, 0x1);
788}
789
790static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
791 unsigned int fcc_offset)
792{
ba6a9d8c 793 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 794 tcg_gen_andi_tl(reg, reg, 0x1);
795}
796
797// !0: FCC0 | FCC1
798static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
799 unsigned int fcc_offset)
800{
de9e9d9f 801 TCGv t0 = tcg_temp_new();
19f329ad 802 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 803 gen_mov_reg_FCC1(t0, src, fcc_offset);
804 tcg_gen_or_tl(dst, dst, t0);
805 tcg_temp_free(t0);
19f329ad
BS		 806}
807
808// 1 or 2: FCC0 ^ FCC1
809static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
810 unsigned int fcc_offset)
811{
de9e9d9f 812 TCGv t0 = tcg_temp_new();
19f329ad 813 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 814 gen_mov_reg_FCC1(t0, src, fcc_offset);
815 tcg_gen_xor_tl(dst, dst, t0);
816 tcg_temp_free(t0);
19f329ad
BS		 817}
818
819// 1 or 3: FCC0
820static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
821 unsigned int fcc_offset)
822{
823 gen_mov_reg_FCC0(dst, src, fcc_offset);
824}
825
826// 1: FCC0 & !FCC1
827static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
828 unsigned int fcc_offset)
829{
de9e9d9f 830 TCGv t0 = tcg_temp_new();
19f329ad 831 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 832 gen_mov_reg_FCC1(t0, src, fcc_offset);
833 tcg_gen_andc_tl(dst, dst, t0);
834 tcg_temp_free(t0);
19f329ad
BS		 835}
836
837// 2 or 3: FCC1
838static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
839 unsigned int fcc_offset)
840{
841 gen_mov_reg_FCC1(dst, src, fcc_offset);
842}
843
844// 2: !FCC0 & FCC1
845static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
846 unsigned int fcc_offset)
847{
de9e9d9f 848 TCGv t0 = tcg_temp_new();
19f329ad 849 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 850 gen_mov_reg_FCC1(t0, src, fcc_offset);
851 tcg_gen_andc_tl(dst, t0, dst);
852 tcg_temp_free(t0);
19f329ad
BS		 853}
854
855// 3: FCC0 & FCC1
856static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
857 unsigned int fcc_offset)
858{
de9e9d9f 859 TCGv t0 = tcg_temp_new();
19f329ad 860 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 861 gen_mov_reg_FCC1(t0, src, fcc_offset);
862 tcg_gen_and_tl(dst, dst, t0);
863 tcg_temp_free(t0);
19f329ad
BS		 864}
865
866// 0: !(FCC0 | FCC1)
867static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
868 unsigned int fcc_offset)
869{
de9e9d9f 870 TCGv t0 = tcg_temp_new();
19f329ad 871 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 872 gen_mov_reg_FCC1(t0, src, fcc_offset);
873 tcg_gen_or_tl(dst, dst, t0);
19f329ad 874 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 875 tcg_temp_free(t0);
19f329ad
BS		 876}
877
878// 0 or 3: !(FCC0 ^ FCC1)
879static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
880 unsigned int fcc_offset)
881{
de9e9d9f 882 TCGv t0 = tcg_temp_new();
19f329ad 883 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 884 gen_mov_reg_FCC1(t0, src, fcc_offset);
885 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 886 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 887 tcg_temp_free(t0);
19f329ad
BS		 888}
889
890// 0 or 2: !FCC0
891static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
892 unsigned int fcc_offset)
893{
894 gen_mov_reg_FCC0(dst, src, fcc_offset);
895 tcg_gen_xori_tl(dst, dst, 0x1);
896}
897
898// !1: !(FCC0 & !FCC1)
899static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
900 unsigned int fcc_offset)
901{
de9e9d9f 902 TCGv t0 = tcg_temp_new();
19f329ad 903 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 904 gen_mov_reg_FCC1(t0, src, fcc_offset);
905 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 906 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 907 tcg_temp_free(t0);
19f329ad
BS		 908}
909
910// 0 or 1: !FCC1
911static inline void gen_op_eval_fble(TCGv dst, TCGv src,
912 unsigned int fcc_offset)
913{
914 gen_mov_reg_FCC1(dst, src, fcc_offset);
915 tcg_gen_xori_tl(dst, dst, 0x1);
916}
917
918// !2: !(!FCC0 & FCC1)
919static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
920 unsigned int fcc_offset)
921{
de9e9d9f 922 TCGv t0 = tcg_temp_new();
19f329ad 923 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 924 gen_mov_reg_FCC1(t0, src, fcc_offset);
925 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 926 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 927 tcg_temp_free(t0);
19f329ad
BS		 928}
929
930// !3: !(FCC0 & FCC1)
931static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
932 unsigned int fcc_offset)
933{
de9e9d9f 934 TCGv t0 = tcg_temp_new();
19f329ad 935 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 936 gen_mov_reg_FCC1(t0, src, fcc_offset);
937 tcg_gen_and_tl(dst, dst, t0);
19f329ad 938 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 939 tcg_temp_free(t0);
19f329ad
BS		 940}
941
46525e1f 942static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 943 target_ulong pc2, TCGv r_cond)
83469015 944{
42a268c2 945 TCGLabel *l1 = gen_new_label();
83469015 946
cb63669a 947 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 948
6e256c93 949 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 950
951 gen_set_label(l1);
6e256c93 952 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 953}
954
bfa31b76 955static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 956{
42a268c2 957 TCGLabel *l1 = gen_new_label();
bfa31b76 958 target_ulong npc = dc->npc;
83469015 959
bfa31b76 960 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 961
bfa31b76 962 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 963
964 gen_set_label(l1);
bfa31b76
RH		 965 gen_goto_tb(dc, 1, npc + 4, npc + 8);
966
967 dc->is_br = 1;
83469015
FB		 968}
969
2bf2e019
RH		 970static void gen_branch_n(DisasContext *dc, target_ulong pc1)
971{
972 target_ulong npc = dc->npc;
973
974 if (likely(npc != DYNAMIC_PC)) {
975 dc->pc = npc;
976 dc->jump_pc[0] = pc1;
977 dc->jump_pc[1] = npc + 4;
978 dc->npc = JUMP_PC;
979 } else {
980 TCGv t, z;
981
982 tcg_gen_mov_tl(cpu_pc, cpu_npc);
983
984 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
985 t = tcg_const_tl(pc1);
986 z = tcg_const_tl(0);
987 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
988 tcg_temp_free(t);
989 tcg_temp_free(z);
990
991 dc->pc = DYNAMIC_PC;
992 }
993}
994
2e655fe7 995static inline void gen_generic_branch(DisasContext *dc)
83469015 996{
61316742
RH		 997 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
998 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
999 TCGv zero = tcg_const_tl(0);
19f329ad 1000
61316742 1001 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1002
61316742
RH		 1003 tcg_temp_free(npc0);
1004 tcg_temp_free(npc1);
1005 tcg_temp_free(zero);
83469015
FB		 1006}
1007
4af984a7
BS		 1008/* call this function before using the condition register as it may
1009 have been set for a jump */
dee8913c 1010static inline void flush_cond(DisasContext *dc)
83469015
FB		 1011{
1012 if (dc->npc == JUMP_PC) {
2e655fe7 1013 gen_generic_branch(dc);
83469015
FB		 1014 dc->npc = DYNAMIC_PC;
1015 }
1016}
1017
934da7ee 1018static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1019{
1020 if (dc->npc == JUMP_PC) {
2e655fe7 1021 gen_generic_branch(dc);
72cbca10
FB		 1022 dc->npc = DYNAMIC_PC;
1023 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1024 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1025 }
1026}
1027
20132b96 1028static inline void update_psr(DisasContext *dc)
72cbca10 1029{
cfa90513
BS		 1030 if (dc->cc_op != CC_OP_FLAGS) {
1031 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1032 gen_helper_compute_psr(cpu_env);
cfa90513 1033 }
20132b96
RH		 1034}
1035
1036static inline void save_state(DisasContext *dc)
1037{
1038 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1039 save_npc(dc);
72cbca10
FB		 1040}
1041
13a6dd00 1042static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1043{
1044 if (dc->npc == JUMP_PC) {
2e655fe7 1045 gen_generic_branch(dc);
48d5c82b 1046 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1047 dc->pc = DYNAMIC_PC;
1048 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1049 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1050 dc->pc = DYNAMIC_PC;
1051 } else {
1052 dc->pc = dc->npc;
1053 }
1054}
1055
38bc628b
BS		 1056static inline void gen_op_next_insn(void)
1057{
48d5c82b
BS		 1058 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1059 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1060}
1061
416fcaea
RH		 1062static void free_compare(DisasCompare *cmp)
1063{
1064 if (!cmp->g1) {
1065 tcg_temp_free(cmp->c1);
1066 }
1067 if (!cmp->g2) {
1068 tcg_temp_free(cmp->c2);
1069 }
1070}
1071
2a484ecf 1072static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1073 DisasContext *dc)
19f329ad 1074{
2a484ecf 1075 static int subcc_cond[16] = {
96b5a3d3 1076 TCG_COND_NEVER,
2a484ecf
RH		 1077 TCG_COND_EQ,
1078 TCG_COND_LE,
1079 TCG_COND_LT,
1080 TCG_COND_LEU,
1081 TCG_COND_LTU,
1082 -1, /* neg */
1083 -1, /* overflow */
96b5a3d3 1084 TCG_COND_ALWAYS,
2a484ecf
RH		 1085 TCG_COND_NE,
1086 TCG_COND_GT,
1087 TCG_COND_GE,
1088 TCG_COND_GTU,
1089 TCG_COND_GEU,
1090 -1, /* pos */
1091 -1, /* no overflow */
1092 };
1093
96b5a3d3
RH		 1094 static int logic_cond[16] = {
1095 TCG_COND_NEVER,
1096 TCG_COND_EQ, /* eq: Z */
1097 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1098 TCG_COND_LT, /* lt: N ^ V -> N */
1099 TCG_COND_EQ, /* leu: C | Z -> Z */
1100 TCG_COND_NEVER, /* ltu: C -> 0 */
1101 TCG_COND_LT, /* neg: N */
1102 TCG_COND_NEVER, /* vs: V -> 0 */
1103 TCG_COND_ALWAYS,
1104 TCG_COND_NE, /* ne: !Z */
1105 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1106 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1107 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1108 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1109 TCG_COND_GE, /* pos: !N */
1110 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1111 };
1112
a7812ae4 1113 TCGv_i32 r_src;
416fcaea
RH		 1114 TCGv r_dst;
1115
3475187d 1116#ifdef TARGET_SPARC64
2a484ecf 1117 if (xcc) {
dc99a3f2 1118 r_src = cpu_xcc;
2a484ecf 1119 } else {
dc99a3f2 1120 r_src = cpu_psr;
2a484ecf 1121 }
3475187d 1122#else
dc99a3f2 1123 r_src = cpu_psr;
3475187d 1124#endif
2a484ecf 1125
8393617c 1126 switch (dc->cc_op) {
96b5a3d3
RH		 1127 case CC_OP_LOGIC:
1128 cmp->cond = logic_cond[cond];
1129 do_compare_dst_0:
1130 cmp->is_bool = false;
1131 cmp->g2 = false;
1132 cmp->c2 = tcg_const_tl(0);
1133#ifdef TARGET_SPARC64
1134 if (!xcc) {
1135 cmp->g1 = false;
1136 cmp->c1 = tcg_temp_new();
1137 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1138 break;
1139 }
1140#endif
1141 cmp->g1 = true;
1142 cmp->c1 = cpu_cc_dst;
1143 break;
1144
2a484ecf
RH		 1145 case CC_OP_SUB:
1146 switch (cond) {
1147 case 6: /* neg */
1148 case 14: /* pos */
1149 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1150 goto do_compare_dst_0;
2a484ecf 1151
2a484ecf
RH		 1152 case 7: /* overflow */
1153 case 15: /* !overflow */
1154 goto do_dynamic;
1155
1156 default:
1157 cmp->cond = subcc_cond[cond];
1158 cmp->is_bool = false;
1159#ifdef TARGET_SPARC64
1160 if (!xcc) {
1161 /* Note that sign-extension works for unsigned compares as
1162 long as both operands are sign-extended. */
1163 cmp->g1 = cmp->g2 = false;
1164 cmp->c1 = tcg_temp_new();
1165 cmp->c2 = tcg_temp_new();
1166 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1167 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1168 break;
2a484ecf
RH		 1169 }
1170#endif
1171 cmp->g1 = cmp->g2 = true;
1172 cmp->c1 = cpu_cc_src;
1173 cmp->c2 = cpu_cc_src2;
1174 break;
1175 }
8393617c 1176 break;
2a484ecf 1177
8393617c 1178 default:
2a484ecf 1179 do_dynamic:
2ffd9176 1180 gen_helper_compute_psr(cpu_env);
8393617c 1181 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1182 /* FALLTHRU */
1183
1184 case CC_OP_FLAGS:
1185 /* We're going to generate a boolean result. */
1186 cmp->cond = TCG_COND_NE;
1187 cmp->is_bool = true;
1188 cmp->g1 = cmp->g2 = false;
1189 cmp->c1 = r_dst = tcg_temp_new();
1190 cmp->c2 = tcg_const_tl(0);
1191
1192 switch (cond) {
1193 case 0x0:
1194 gen_op_eval_bn(r_dst);
1195 break;
1196 case 0x1:
1197 gen_op_eval_be(r_dst, r_src);
1198 break;
1199 case 0x2:
1200 gen_op_eval_ble(r_dst, r_src);
1201 break;
1202 case 0x3:
1203 gen_op_eval_bl(r_dst, r_src);
1204 break;
1205 case 0x4:
1206 gen_op_eval_bleu(r_dst, r_src);
1207 break;
1208 case 0x5:
1209 gen_op_eval_bcs(r_dst, r_src);
1210 break;
1211 case 0x6:
1212 gen_op_eval_bneg(r_dst, r_src);
1213 break;
1214 case 0x7:
1215 gen_op_eval_bvs(r_dst, r_src);
1216 break;
1217 case 0x8:
1218 gen_op_eval_ba(r_dst);
1219 break;
1220 case 0x9:
1221 gen_op_eval_bne(r_dst, r_src);
1222 break;
1223 case 0xa:
1224 gen_op_eval_bg(r_dst, r_src);
1225 break;
1226 case 0xb:
1227 gen_op_eval_bge(r_dst, r_src);
1228 break;
1229 case 0xc:
1230 gen_op_eval_bgu(r_dst, r_src);
1231 break;
1232 case 0xd:
1233 gen_op_eval_bcc(r_dst, r_src);
1234 break;
1235 case 0xe:
1236 gen_op_eval_bpos(r_dst, r_src);
1237 break;
1238 case 0xf:
1239 gen_op_eval_bvc(r_dst, r_src);
1240 break;
1241 }
19f329ad
BS		 1242 break;
1243 }
1244}
7a3f1944 1245
416fcaea 1246static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1247{
19f329ad 1248 unsigned int offset;
416fcaea
RH		 1249 TCGv r_dst;
1250
1251 /* For now we still generate a straight boolean result. */
1252 cmp->cond = TCG_COND_NE;
1253 cmp->is_bool = true;
1254 cmp->g1 = cmp->g2 = false;
1255 cmp->c1 = r_dst = tcg_temp_new();
1256 cmp->c2 = tcg_const_tl(0);
19f329ad 1257
19f329ad
BS		 1258 switch (cc) {
1259 default:
1260 case 0x0:
1261 offset = 0;
1262 break;
1263 case 0x1:
1264 offset = 32 - 10;
1265 break;
1266 case 0x2:
1267 offset = 34 - 10;
1268 break;
1269 case 0x3:
1270 offset = 36 - 10;
1271 break;
1272 }
1273
1274 switch (cond) {
1275 case 0x0:
1276 gen_op_eval_bn(r_dst);
1277 break;
1278 case 0x1:
87e92502 1279 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1280 break;
1281 case 0x2:
87e92502 1282 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1283 break;
1284 case 0x3:
87e92502 1285 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1286 break;
1287 case 0x4:
87e92502 1288 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1289 break;
1290 case 0x5:
87e92502 1291 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1292 break;
1293 case 0x6:
87e92502 1294 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1295 break;
1296 case 0x7:
87e92502 1297 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1298 break;
1299 case 0x8:
1300 gen_op_eval_ba(r_dst);
1301 break;
1302 case 0x9:
87e92502 1303 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1304 break;
1305 case 0xa:
87e92502 1306 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1307 break;
1308 case 0xb:
87e92502 1309 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1310 break;
1311 case 0xc:
87e92502 1312 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1313 break;
1314 case 0xd:
87e92502 1315 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1316 break;
1317 case 0xe:
87e92502 1318 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1319 break;
1320 case 0xf:
87e92502 1321 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1322 break;
1323 }
e8af50a3 1324}
00f219bf 1325
416fcaea
RH		 1326static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1327 DisasContext *dc)
1328{
1329 DisasCompare cmp;
1330 gen_compare(&cmp, cc, cond, dc);
1331
1332 /* The interface is to return a boolean in r_dst. */
1333 if (cmp.is_bool) {
1334 tcg_gen_mov_tl(r_dst, cmp.c1);
1335 } else {
1336 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1337 }
1338
1339 free_compare(&cmp);
1340}
1341
1342static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1343{
1344 DisasCompare cmp;
1345 gen_fcompare(&cmp, cc, cond);
1346
1347 /* The interface is to return a boolean in r_dst. */
1348 if (cmp.is_bool) {
1349 tcg_gen_mov_tl(r_dst, cmp.c1);
1350 } else {
1351 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1352 }
1353
1354 free_compare(&cmp);
1355}
1356
19f329ad 1357#ifdef TARGET_SPARC64
00f219bf
BS		 1358// Inverted logic
1359static const int gen_tcg_cond_reg[8] = {
1360 -1,
1361 TCG_COND_NE,
1362 TCG_COND_GT,
1363 TCG_COND_GE,
1364 -1,
1365 TCG_COND_EQ,
1366 TCG_COND_LE,
1367 TCG_COND_LT,
1368};
19f329ad 1369
416fcaea
RH		 1370static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1371{
1372 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1373 cmp->is_bool = false;
1374 cmp->g1 = true;
1375 cmp->g2 = false;
1376 cmp->c1 = r_src;
1377 cmp->c2 = tcg_const_tl(0);
1378}
1379
4af984a7 1380static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1381{
416fcaea
RH		 1382 DisasCompare cmp;
1383 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1384
416fcaea
RH		 1385 /* The interface is to return a boolean in r_dst. */
1386 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1387
1388 free_compare(&cmp);
19f329ad 1389}
3475187d 1390#endif
cf495bcf 1391
d4a288ef 1392static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1393{
cf495bcf 1394 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1395 target_ulong target = dc->pc + offset;
5fafdf24 1396
22036a49
AT		 1397#ifdef TARGET_SPARC64
1398 if (unlikely(AM_CHECK(dc))) {
1399 target &= 0xffffffffULL;
1400 }
1401#endif
cf495bcf 1402 if (cond == 0x0) {
0f8a249a
BS		 1403 /* unconditional not taken */
1404 if (a) {
1405 dc->pc = dc->npc + 4;
1406 dc->npc = dc->pc + 4;
1407 } else {
1408 dc->pc = dc->npc;
1409 dc->npc = dc->pc + 4;
1410 }
cf495bcf 1411 } else if (cond == 0x8) {
0f8a249a
BS		 1412 /* unconditional taken */
1413 if (a) {
1414 dc->pc = target;
1415 dc->npc = dc->pc + 4;
1416 } else {
1417 dc->pc = dc->npc;
1418 dc->npc = target;
c27e2752 1419 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1420 }
cf495bcf 1421 } else {
dee8913c 1422 flush_cond(dc);
d4a288ef 1423 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1424 if (a) {
bfa31b76 1425 gen_branch_a(dc, target);
0f8a249a 1426 } else {
2bf2e019 1427 gen_branch_n(dc, target);
0f8a249a 1428 }
cf495bcf 1429 }
7a3f1944
FB		 1430}
1431
d4a288ef 1432static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1433{
1434 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1435 target_ulong target = dc->pc + offset;
1436
22036a49
AT		 1437#ifdef TARGET_SPARC64
1438 if (unlikely(AM_CHECK(dc))) {
1439 target &= 0xffffffffULL;
1440 }
1441#endif
e8af50a3 1442 if (cond == 0x0) {
0f8a249a
BS		 1443 /* unconditional not taken */
1444 if (a) {
1445 dc->pc = dc->npc + 4;
1446 dc->npc = dc->pc + 4;
1447 } else {
1448 dc->pc = dc->npc;
1449 dc->npc = dc->pc + 4;
1450 }
e8af50a3 1451 } else if (cond == 0x8) {
0f8a249a
BS		 1452 /* unconditional taken */
1453 if (a) {
1454 dc->pc = target;
1455 dc->npc = dc->pc + 4;
1456 } else {
1457 dc->pc = dc->npc;
1458 dc->npc = target;
c27e2752 1459 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1460 }
e8af50a3 1461 } else {
dee8913c 1462 flush_cond(dc);
d4a288ef 1463 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1464 if (a) {
bfa31b76 1465 gen_branch_a(dc, target);
0f8a249a 1466 } else {
2bf2e019 1467 gen_branch_n(dc, target);
0f8a249a 1468 }
e8af50a3
FB		 1469 }
1470}
1471
3475187d 1472#ifdef TARGET_SPARC64
4af984a7 1473static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1474 TCGv r_reg)
7a3f1944 1475{
3475187d
FB		 1476 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1477 target_ulong target = dc->pc + offset;
1478
22036a49
AT		 1479 if (unlikely(AM_CHECK(dc))) {
1480 target &= 0xffffffffULL;
1481 }
dee8913c 1482 flush_cond(dc);
d4a288ef 1483 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1484 if (a) {
bfa31b76 1485 gen_branch_a(dc, target);
3475187d 1486 } else {
2bf2e019 1487 gen_branch_n(dc, target);
3475187d 1488 }
7a3f1944
FB		 1489}
1490
a7812ae4 1491static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1492{
714547bb
BS		 1493 switch (fccno) {
1494 case 0:
2e2f4ade 1495 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1496 break;
1497 case 1:
2e2f4ade 1498 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1499 break;
1500 case 2:
2e2f4ade 1501 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1502 break;
1503 case 3:
2e2f4ade 1504 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1505 break;
1506 }
7e8c2b6c
BS		 1507}
1508
03fb8cfc 1509static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1510{
a7812ae4
PB		 1511 switch (fccno) {
1512 case 0:
03fb8cfc 1513 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1514 break;
1515 case 1:
03fb8cfc 1516 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1517 break;
1518 case 2:
03fb8cfc 1519 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1520 break;
1521 case 3:
03fb8cfc 1522 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1523 break;
1524 }
7e8c2b6c
BS		 1525}
1526
7e8c2b6c
BS		 1527static inline void gen_op_fcmpq(int fccno)
1528{
a7812ae4
PB		 1529 switch (fccno) {
1530 case 0:
2e2f4ade 1531 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1532 break;
1533 case 1:
2e2f4ade 1534 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1535 break;
1536 case 2:
2e2f4ade 1537 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1538 break;
1539 case 3:
2e2f4ade 1540 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1541 break;
1542 }
7e8c2b6c 1543}
7e8c2b6c 1544
a7812ae4 1545static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1546{
714547bb
BS		 1547 switch (fccno) {
1548 case 0:
2e2f4ade 1549 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1550 break;
1551 case 1:
2e2f4ade 1552 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1553 break;
1554 case 2:
2e2f4ade 1555 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1556 break;
1557 case 3:
2e2f4ade 1558 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1559 break;
1560 }
7e8c2b6c
BS		 1561}
1562
03fb8cfc 1563static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1564{
a7812ae4
PB		 1565 switch (fccno) {
1566 case 0:
03fb8cfc 1567 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1568 break;
1569 case 1:
03fb8cfc 1570 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1571 break;
1572 case 2:
03fb8cfc 1573 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1574 break;
1575 case 3:
03fb8cfc 1576 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1577 break;
1578 }
7e8c2b6c
BS		 1579}
1580
7e8c2b6c
BS		 1581static inline void gen_op_fcmpeq(int fccno)
1582{
a7812ae4
PB		 1583 switch (fccno) {
1584 case 0:
2e2f4ade 1585 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1586 break;
1587 case 1:
2e2f4ade 1588 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1589 break;
1590 case 2:
2e2f4ade 1591 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1592 break;
1593 case 3:
2e2f4ade 1594 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1595 break;
1596 }
7e8c2b6c 1597}
7e8c2b6c
BS		 1598
1599#else
1600
714547bb 1601static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1602{
2e2f4ade 1603 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1604}
1605
03fb8cfc 1606static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1607{
03fb8cfc 1608 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1609}
1610
7e8c2b6c
BS		 1611static inline void gen_op_fcmpq(int fccno)
1612{
2e2f4ade 1613 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1614}
7e8c2b6c 1615
714547bb 1616static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1617{
2e2f4ade 1618 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1619}
1620
03fb8cfc 1621static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1622{
03fb8cfc 1623 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1624}
1625
7e8c2b6c
BS		 1626static inline void gen_op_fcmpeq(int fccno)
1627{
2e2f4ade 1628 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1629}
1630#endif
1631
134d77a1
BS		 1632static inline void gen_op_fpexception_im(int fsr_flags)
1633{
a7812ae4 1634 TCGv_i32 r_const;
2ea815ca 1635
47ad35f1 1636 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1637 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca 1638 r_const = tcg_const_i32(TT_FP_EXCP);
bc265319 1639 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1640 tcg_temp_free_i32(r_const);
134d77a1
BS		 1641}
1642
5b12f1e8 1643static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1644{
1645#if !defined(CONFIG_USER_ONLY)
1646 if (!dc->fpu_enabled) {
a7812ae4 1647 TCGv_i32 r_const;
2ea815ca 1648
66442b07 1649 save_state(dc);
2ea815ca 1650 r_const = tcg_const_i32(TT_NFPU_INSN);
bc265319 1651 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1652 tcg_temp_free_i32(r_const);
a80dde08
FB		 1653 dc->is_br = 1;
1654 return 1;
1655 }
1656#endif
1657 return 0;
1658}
1659
7e8c2b6c
BS		 1660static inline void gen_op_clear_ieee_excp_and_FTT(void)
1661{
47ad35f1 1662 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1663}
1664
61f17f6e
RH		 1665static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1666 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1667{
1668 TCGv_i32 dst, src;
1669
61f17f6e 1670 src = gen_load_fpr_F(dc, rs);
ba5f5179 1671 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1672
1673 gen(dst, cpu_env, src);
1674
61f17f6e
RH		 1675 gen_store_fpr_F(dc, rd, dst);
1676}
1677
1678static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1679 void (*gen)(TCGv_i32, TCGv_i32))
1680{
1681 TCGv_i32 dst, src;
1682
1683 src = gen_load_fpr_F(dc, rs);
ba5f5179 1684 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1685
1686 gen(dst, src);
1687
1688 gen_store_fpr_F(dc, rd, dst);
1689}
1690
1691static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1692 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1693{
1694 TCGv_i32 dst, src1, src2;
1695
61f17f6e
RH		 1696 src1 = gen_load_fpr_F(dc, rs1);
1697 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1698 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1699
1700 gen(dst, cpu_env, src1, src2);
1701
61f17f6e
RH		 1702 gen_store_fpr_F(dc, rd, dst);
1703}
1704
1705#ifdef TARGET_SPARC64
1706static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1707 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1708{
1709 TCGv_i32 dst, src1, src2;
1710
1711 src1 = gen_load_fpr_F(dc, rs1);
1712 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1713 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1714
1715 gen(dst, src1, src2);
1716
1717 gen_store_fpr_F(dc, rd, dst);
1718}
1719#endif
1720
1721static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1722 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1723{
1724 TCGv_i64 dst, src;
1725
61f17f6e 1726 src = gen_load_fpr_D(dc, rs);
3886b8a3 1727 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1728
1729 gen(dst, cpu_env, src);
1730
61f17f6e
RH		 1731 gen_store_fpr_D(dc, rd, dst);
1732}
1733
1734#ifdef TARGET_SPARC64
1735static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1736 void (*gen)(TCGv_i64, TCGv_i64))
1737{
1738 TCGv_i64 dst, src;
1739
1740 src = gen_load_fpr_D(dc, rs);
3886b8a3 1741 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1742
1743 gen(dst, src);
1744
1745 gen_store_fpr_D(dc, rd, dst);
1746}
1747#endif
1748
1749static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1750 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1751{
1752 TCGv_i64 dst, src1, src2;
1753
61f17f6e
RH		 1754 src1 = gen_load_fpr_D(dc, rs1);
1755 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1756 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1757
1758 gen(dst, cpu_env, src1, src2);
1759
61f17f6e
RH		 1760 gen_store_fpr_D(dc, rd, dst);
1761}
1762
1763#ifdef TARGET_SPARC64
1764static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1765 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1766{
1767 TCGv_i64 dst, src1, src2;
1768
1769 src1 = gen_load_fpr_D(dc, rs1);
1770 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1771 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1772
1773 gen(dst, src1, src2);
1774
1775 gen_store_fpr_D(dc, rd, dst);
1776}
f888300b 1777
2dedf314
RH		 1778static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1779 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1780{
1781 TCGv_i64 dst, src1, src2;
1782
1783 src1 = gen_load_fpr_D(dc, rs1);
1784 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1785 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1786
1787 gen(dst, cpu_gsr, src1, src2);
1788
1789 gen_store_fpr_D(dc, rd, dst);
1790}
1791
f888300b
RH		 1792static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1793 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1794{
1795 TCGv_i64 dst, src0, src1, src2;
1796
1797 src1 = gen_load_fpr_D(dc, rs1);
1798 src2 = gen_load_fpr_D(dc, rs2);
1799 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1800 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1801
1802 gen(dst, src0, src1, src2);
1803
1804 gen_store_fpr_D(dc, rd, dst);
1805}
61f17f6e
RH		 1806#endif
1807
1808static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1809 void (*gen)(TCGv_ptr))
1810{
61f17f6e
RH		 1811 gen_op_load_fpr_QT1(QFPREG(rs));
1812
1813 gen(cpu_env);
1814
61f17f6e
RH		 1815 gen_op_store_QT0_fpr(QFPREG(rd));
1816 gen_update_fprs_dirty(QFPREG(rd));
1817}
1818
1819#ifdef TARGET_SPARC64
1820static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1821 void (*gen)(TCGv_ptr))
1822{
1823 gen_op_load_fpr_QT1(QFPREG(rs));
1824
1825 gen(cpu_env);
1826
1827 gen_op_store_QT0_fpr(QFPREG(rd));
1828 gen_update_fprs_dirty(QFPREG(rd));
1829}
1830#endif
1831
1832static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1833 void (*gen)(TCGv_ptr))
1834{
61f17f6e
RH		 1835 gen_op_load_fpr_QT0(QFPREG(rs1));
1836 gen_op_load_fpr_QT1(QFPREG(rs2));
1837
1838 gen(cpu_env);
1839
61f17f6e
RH		 1840 gen_op_store_QT0_fpr(QFPREG(rd));
1841 gen_update_fprs_dirty(QFPREG(rd));
1842}
1843
1844static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1845 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1846{
1847 TCGv_i64 dst;
1848 TCGv_i32 src1, src2;
1849
61f17f6e
RH		 1850 src1 = gen_load_fpr_F(dc, rs1);
1851 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1852 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1853
1854 gen(dst, cpu_env, src1, src2);
1855
61f17f6e
RH		 1856 gen_store_fpr_D(dc, rd, dst);
1857}
1858
1859static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1860 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1861{
1862 TCGv_i64 src1, src2;
1863
61f17f6e
RH		 1864 src1 = gen_load_fpr_D(dc, rs1);
1865 src2 = gen_load_fpr_D(dc, rs2);
1866
1867 gen(cpu_env, src1, src2);
1868
61f17f6e
RH		 1869 gen_op_store_QT0_fpr(QFPREG(rd));
1870 gen_update_fprs_dirty(QFPREG(rd));
1871}
1872
1873#ifdef TARGET_SPARC64
1874static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1875 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1876{
1877 TCGv_i64 dst;
1878 TCGv_i32 src;
1879
61f17f6e 1880 src = gen_load_fpr_F(dc, rs);
3886b8a3 1881 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1882
1883 gen(dst, cpu_env, src);
1884
61f17f6e
RH		 1885 gen_store_fpr_D(dc, rd, dst);
1886}
1887#endif
1888
1889static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1890 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1891{
1892 TCGv_i64 dst;
1893 TCGv_i32 src;
1894
1895 src = gen_load_fpr_F(dc, rs);
3886b8a3 1896 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1897
1898 gen(dst, cpu_env, src);
1899
1900 gen_store_fpr_D(dc, rd, dst);
1901}
1902
1903static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1904 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1905{
1906 TCGv_i32 dst;
1907 TCGv_i64 src;
1908
61f17f6e 1909 src = gen_load_fpr_D(dc, rs);
ba5f5179 1910 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1911
1912 gen(dst, cpu_env, src);
1913
61f17f6e
RH		 1914 gen_store_fpr_F(dc, rd, dst);
1915}
1916
1917static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1918 void (*gen)(TCGv_i32, TCGv_ptr))
1919{
1920 TCGv_i32 dst;
1921
61f17f6e 1922 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1923 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1924
1925 gen(dst, cpu_env);
1926
61f17f6e
RH		 1927 gen_store_fpr_F(dc, rd, dst);
1928}
1929
1930static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1931 void (*gen)(TCGv_i64, TCGv_ptr))
1932{
1933 TCGv_i64 dst;
1934
61f17f6e 1935 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1936 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1937
1938 gen(dst, cpu_env);
1939
61f17f6e
RH		 1940 gen_store_fpr_D(dc, rd, dst);
1941}
1942
1943static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1944 void (*gen)(TCGv_ptr, TCGv_i32))
1945{
1946 TCGv_i32 src;
1947
1948 src = gen_load_fpr_F(dc, rs);
1949
1950 gen(cpu_env, src);
1951
1952 gen_op_store_QT0_fpr(QFPREG(rd));
1953 gen_update_fprs_dirty(QFPREG(rd));
1954}
1955
1956static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1957 void (*gen)(TCGv_ptr, TCGv_i64))
1958{
1959 TCGv_i64 src;
1960
1961 src = gen_load_fpr_D(dc, rs);
1962
1963 gen(cpu_env, src);
1964
1965 gen_op_store_QT0_fpr(QFPREG(rd));
1966 gen_update_fprs_dirty(QFPREG(rd));
1967}
1968
1a2fb1c0
BS		 1969/* asi moves */
1970#ifdef TARGET_SPARC64
a7812ae4 1971static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0 1972{
95f9397c 1973 int asi;
a7812ae4 1974 TCGv_i32 r_asi;
1a2fb1c0 1975
1a2fb1c0 1976 if (IS_IMM) {
a7812ae4 1977 r_asi = tcg_temp_new_i32();
255e1fcb 1978 tcg_gen_mov_i32(r_asi, cpu_asi);
1a2fb1c0
BS		 1979 } else {
1980 asi = GET_FIELD(insn, 19, 26);
0425bee5 1981 r_asi = tcg_const_i32(asi);
1a2fb1c0 1982 }
0425bee5
BS		 1983 return r_asi;
1984}
1985
77f193da
BS		 1986static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1987 int sign)
0425bee5 1988{
a7812ae4 1989 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 1990
4af984a7 1991 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1992 r_size = tcg_const_i32(size);
1993 r_sign = tcg_const_i32(sign);
fe8d8f0f 1994 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4
PB		 1995 tcg_temp_free_i32(r_sign);
1996 tcg_temp_free_i32(r_size);
1997 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1998}
1999
4af984a7 2000static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2001{
a7812ae4 2002 TCGv_i32 r_asi, r_size;
1a2fb1c0 2003
4af984a7 2004 r_asi = gen_get_asi(insn, addr);
2ea815ca 2005 r_size = tcg_const_i32(size);
fe8d8f0f 2006 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2007 tcg_temp_free_i32(r_size);
2008 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2009}
2010
4af984a7 2011static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2012{
a7812ae4 2013 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2014
4af984a7 2015 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2016 r_size = tcg_const_i32(size);
2017 r_rd = tcg_const_i32(rd);
fe8d8f0f 2018 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2019 tcg_temp_free_i32(r_rd);
2020 tcg_temp_free_i32(r_size);
2021 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2022}
2023
4af984a7 2024static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2025{
a7812ae4 2026 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2027
31741a27 2028 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2029 r_size = tcg_const_i32(size);
2030 r_rd = tcg_const_i32(rd);
fe8d8f0f 2031 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2032 tcg_temp_free_i32(r_rd);
2033 tcg_temp_free_i32(r_size);
2034 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2035}
2036
06828032 2037static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2038{
a7812ae4 2039 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2040 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2041
4af984a7 2042 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2043 r_size = tcg_const_i32(4);
2044 r_sign = tcg_const_i32(0);
1ec789ab 2045 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4 2046 tcg_temp_free_i32(r_sign);
06828032 2047 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2048 tcg_temp_free_i32(r_size);
2049 tcg_temp_free_i32(r_asi);
1ec789ab
RH		 2050 tcg_gen_trunc_i64_tl(dst, t64);
2051 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2052}
2053
c7785e16
RH		 2054static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2055 int insn, int rd)
1a2fb1c0 2056{
a7812ae4 2057 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2058
4af984a7 2059 r_asi = gen_get_asi(insn, addr);
db166940 2060 r_rd = tcg_const_i32(rd);
fe8d8f0f 2061 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
a7812ae4
PB		 2062 tcg_temp_free_i32(r_rd);
2063 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2064}
2065
c7785e16
RH		 2066static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2067 int insn, int rd)
0425bee5 2068{
a7812ae4 2069 TCGv_i32 r_asi, r_size;
c7785e16 2070 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2071 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2072
1ec789ab 2073 tcg_gen_concat_tl_i64(t64, lo, hi);
4af984a7 2074 r_asi = gen_get_asi(insn, addr);
2ea815ca 2075 r_size = tcg_const_i32(8);
1ec789ab 2076 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
a7812ae4
PB		 2077 tcg_temp_free_i32(r_size);
2078 tcg_temp_free_i32(r_asi);
1ec789ab 2079 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2080}
2081
81634eea 2082static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
c7785e16 2083 TCGv val2, int insn, int rd)
1a2fb1c0 2084{
81634eea
RH		 2085 TCGv val1 = gen_load_gpr(dc, rd);
2086 TCGv dst = gen_dest_gpr(dc, rd);
c7785e16 2087 TCGv_i32 r_asi = gen_get_asi(insn, addr);
1a2fb1c0 2088
81634eea 2089 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2090 tcg_temp_free_i32(r_asi);
81634eea 2091 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2092}
2093
2094#elif !defined(CONFIG_USER_ONLY)
2095
77f193da
BS		 2096static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2097 int sign)
1a2fb1c0 2098{
a7812ae4 2099 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2100 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2101
2ea815ca
BS		 2102 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2103 r_size = tcg_const_i32(size);
2104 r_sign = tcg_const_i32(sign);
1ec789ab
RH		 2105 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2106 tcg_temp_free_i32(r_sign);
2107 tcg_temp_free_i32(r_size);
2108 tcg_temp_free_i32(r_asi);
2109 tcg_gen_trunc_i64_tl(dst, t64);
2110 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2111}
2112
4af984a7 2113static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2114{
a7812ae4 2115 TCGv_i32 r_asi, r_size;
1ec789ab 2116 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2117
1ec789ab 2118 tcg_gen_extu_tl_i64(t64, src);
2ea815ca
BS		 2119 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2120 r_size = tcg_const_i32(size);
1ec789ab
RH		 2121 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2122 tcg_temp_free_i32(r_size);
2123 tcg_temp_free_i32(r_asi);
2124 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2125}
2126
06828032 2127static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2128{
a7812ae4 2129 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2130 TCGv_i64 r_val, t64;
1a2fb1c0 2131
2ea815ca
BS		 2132 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2133 r_size = tcg_const_i32(4);
2134 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2135 t64 = tcg_temp_new_i64();
2136 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2ea815ca 2137 tcg_temp_free(r_sign);
a7812ae4 2138 r_val = tcg_temp_new_i64();
06828032 2139 tcg_gen_extu_tl_i64(r_val, src);
fe8d8f0f 2140 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4 2141 tcg_temp_free_i64(r_val);
1ec789ab
RH		 2142 tcg_temp_free_i32(r_size);
2143 tcg_temp_free_i32(r_asi);
2144 tcg_gen_trunc_i64_tl(dst, t64);
2145 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2146}
2147
c7785e16
RH		 2148static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2149 int insn, int rd)
1a2fb1c0 2150{
a7812ae4 2151 TCGv_i32 r_asi, r_size, r_sign;
c7785e16 2152 TCGv t;
1ec789ab 2153 TCGv_i64 t64;
1a2fb1c0 2154
2ea815ca
BS		 2155 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2156 r_size = tcg_const_i32(8);
2157 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2158 t64 = tcg_temp_new_i64();
2159 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2160 tcg_temp_free_i32(r_sign);
2161 tcg_temp_free_i32(r_size);
2162 tcg_temp_free_i32(r_asi);
c7785e16
RH		 2163
2164 t = gen_dest_gpr(dc, rd + 1);
1ec789ab 2165 tcg_gen_trunc_i64_tl(t, t64);
c7785e16
RH		 2166 gen_store_gpr(dc, rd + 1, t);
2167
1ec789ab
RH		 2168 tcg_gen_shri_i64(t64, t64, 32);
2169 tcg_gen_trunc_i64_tl(hi, t64);
2170 tcg_temp_free_i64(t64);
c7785e16 2171 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2172}
2173
c7785e16
RH		 2174static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2175 int insn, int rd)
0425bee5 2176{
a7812ae4 2177 TCGv_i32 r_asi, r_size;
c7785e16 2178 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2179 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2180
1ec789ab 2181 tcg_gen_concat_tl_i64(t64, lo, hi);
2ea815ca
BS		 2182 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2183 r_size = tcg_const_i32(8);
1ec789ab
RH		 2184 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2185 tcg_temp_free_i32(r_size);
2186 tcg_temp_free_i32(r_asi);
2187 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2188}
2189#endif
2190
2191#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
16c358e9
SH		 2192static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
2193 TCGv val2, int insn, int rd)
2194{
2195 TCGv val1 = gen_load_gpr(dc, rd);
2196 TCGv dst = gen_dest_gpr(dc, rd);
2197#ifdef TARGET_SPARC64
2198 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2199#else
2200 TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2201#endif
2202
2203 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2204 tcg_temp_free_i32(r_asi);
2205 gen_store_gpr(dc, rd, dst);
2206}
2207
4af984a7 2208static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2209{
a7812ae4
PB		 2210 TCGv_i64 r_val;
2211 TCGv_i32 r_asi, r_size;
1a2fb1c0 2212
4af984a7 2213 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 2214
2ea815ca
BS		 2215 r_val = tcg_const_i64(0xffULL);
2216 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2217 r_size = tcg_const_i32(1);
fe8d8f0f 2218 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4
PB		 2219 tcg_temp_free_i32(r_size);
2220 tcg_temp_free_i32(r_asi);
2221 tcg_temp_free_i64(r_val);
1a2fb1c0
BS		 2222}
2223#endif
2224
9d1d4e34 2225static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2226{
9d1d4e34
RH		 2227 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2228 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2229}
2230
9d1d4e34 2231static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2232{
a49d9390 2233 if (IS_IMM) { /* immediate */
42a8aa83 2234 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2235 TCGv t = get_temp_tl(dc);
2236 tcg_gen_movi_tl(t, simm);
2237 return t;
2238 } else { /* register */
42a8aa83 2239 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2240 return gen_load_gpr(dc, rs2);
a49d9390 2241 }
a49d9390
BS		 2242}
2243
8194f35a 2244#ifdef TARGET_SPARC64
7e480893
RH		 2245static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2246{
2247 TCGv_i32 c32, zero, dst, s1, s2;
2248
2249 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2250 or fold the comparison down to 32 bits and use movcond_i32. Choose
2251 the later. */
2252 c32 = tcg_temp_new_i32();
2253 if (cmp->is_bool) {
ecc7b3aa 2254 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2255 } else {
2256 TCGv_i64 c64 = tcg_temp_new_i64();
2257 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2258 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2259 tcg_temp_free_i64(c64);
2260 }
2261
2262 s1 = gen_load_fpr_F(dc, rs);
2263 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2264 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2265 zero = tcg_const_i32(0);
2266
2267 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2268
2269 tcg_temp_free_i32(c32);
2270 tcg_temp_free_i32(zero);
2271 gen_store_fpr_F(dc, rd, dst);
2272}
2273
2274static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2275{
3886b8a3 2276 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2277 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2278 gen_load_fpr_D(dc, rs),
2279 gen_load_fpr_D(dc, rd));
2280 gen_store_fpr_D(dc, rd, dst);
2281}
2282
2283static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2284{
2285 int qd = QFPREG(rd);
2286 int qs = QFPREG(rs);
2287
2288 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2289 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2290 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2291 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2292
2293 gen_update_fprs_dirty(qd);
2294}
2295
a2035e83 2296#ifndef CONFIG_USER_ONLY
8194f35a
IK		 2297static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2298{
b551ec04 2299 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2300
2301 /* load env->tl into r_tl */
b551ec04 2302 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2303
2304 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2305 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2306
2307 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2308 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2309 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2310
2311 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2312 {
2313 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2314 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2315 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2316 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2317 }
8194f35a 2318
b551ec04 2319 tcg_temp_free_i32(r_tl);
8194f35a 2320}
a2035e83 2321#endif
6c073553
RH		 2322
2323static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2324 int width, bool cc, bool left)
2325{
2326 TCGv lo1, lo2, t1, t2;
2327 uint64_t amask, tabl, tabr;
2328 int shift, imask, omask;
2329
2330 if (cc) {
2331 tcg_gen_mov_tl(cpu_cc_src, s1);
2332 tcg_gen_mov_tl(cpu_cc_src2, s2);
2333 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2334 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2335 dc->cc_op = CC_OP_SUB;
2336 }
2337
2338 /* Theory of operation: there are two tables, left and right (not to
2339 be confused with the left and right versions of the opcode). These
2340 are indexed by the low 3 bits of the inputs. To make things "easy",
2341 these tables are loaded into two constants, TABL and TABR below.
2342 The operation index = (input & imask) << shift calculates the index
2343 into the constant, while val = (table >> index) & omask calculates
2344 the value we're looking for. */
2345 switch (width) {
2346 case 8:
2347 imask = 0x7;
2348 shift = 3;
2349 omask = 0xff;
2350 if (left) {
2351 tabl = 0x80c0e0f0f8fcfeffULL;
2352 tabr = 0xff7f3f1f0f070301ULL;
2353 } else {
2354 tabl = 0x0103070f1f3f7fffULL;
2355 tabr = 0xfffefcf8f0e0c080ULL;
2356 }
2357 break;
2358 case 16:
2359 imask = 0x6;
2360 shift = 1;
2361 omask = 0xf;
2362 if (left) {
2363 tabl = 0x8cef;
2364 tabr = 0xf731;
2365 } else {
2366 tabl = 0x137f;
2367 tabr = 0xfec8;
2368 }
2369 break;
2370 case 32:
2371 imask = 0x4;
2372 shift = 0;
2373 omask = 0x3;
2374 if (left) {
2375 tabl = (2 << 2) | 3;
2376 tabr = (3 << 2) | 1;
2377 } else {
2378 tabl = (1 << 2) | 3;
2379 tabr = (3 << 2) | 2;
2380 }
2381 break;
2382 default:
2383 abort();
2384 }
2385
2386 lo1 = tcg_temp_new();
2387 lo2 = tcg_temp_new();
2388 tcg_gen_andi_tl(lo1, s1, imask);
2389 tcg_gen_andi_tl(lo2, s2, imask);
2390 tcg_gen_shli_tl(lo1, lo1, shift);
2391 tcg_gen_shli_tl(lo2, lo2, shift);
2392
2393 t1 = tcg_const_tl(tabl);
2394 t2 = tcg_const_tl(tabr);
2395 tcg_gen_shr_tl(lo1, t1, lo1);
2396 tcg_gen_shr_tl(lo2, t2, lo2);
2397 tcg_gen_andi_tl(dst, lo1, omask);
2398 tcg_gen_andi_tl(lo2, lo2, omask);
2399
2400 amask = -8;
2401 if (AM_CHECK(dc)) {
2402 amask &= 0xffffffffULL;
2403 }
2404 tcg_gen_andi_tl(s1, s1, amask);
2405 tcg_gen_andi_tl(s2, s2, amask);
2406
2407 /* We want to compute
2408 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2409 We've already done dst = lo1, so this reduces to
2410 dst &= (s1 == s2 ? -1 : lo2)
2411 Which we perform by
2412 lo2 |= -(s1 == s2)
2413 dst &= lo2
2414 */
2415 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2416 tcg_gen_neg_tl(t1, t1);
2417 tcg_gen_or_tl(lo2, lo2, t1);
2418 tcg_gen_and_tl(dst, dst, lo2);
2419
2420 tcg_temp_free(lo1);
2421 tcg_temp_free(lo2);
2422 tcg_temp_free(t1);
2423 tcg_temp_free(t2);
2424}
add545ab
RH		 2425
2426static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2427{
2428 TCGv tmp = tcg_temp_new();
2429
2430 tcg_gen_add_tl(tmp, s1, s2);
2431 tcg_gen_andi_tl(dst, tmp, -8);
2432 if (left) {
2433 tcg_gen_neg_tl(tmp, tmp);
2434 }
2435 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2436
2437 tcg_temp_free(tmp);
2438}
50c796f9
RH		 2439
2440static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2441{
2442 TCGv t1, t2, shift;
2443
2444 t1 = tcg_temp_new();
2445 t2 = tcg_temp_new();
2446 shift = tcg_temp_new();
2447
2448 tcg_gen_andi_tl(shift, gsr, 7);
2449 tcg_gen_shli_tl(shift, shift, 3);
2450 tcg_gen_shl_tl(t1, s1, shift);
2451
2452 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2453 shift of (up to 63) followed by a constant shift of 1. */
2454 tcg_gen_xori_tl(shift, shift, 63);
2455 tcg_gen_shr_tl(t2, s2, shift);
2456 tcg_gen_shri_tl(t2, t2, 1);
2457
2458 tcg_gen_or_tl(dst, t1, t2);
2459
2460 tcg_temp_free(t1);
2461 tcg_temp_free(t2);
2462 tcg_temp_free(shift);
2463}
8194f35a
IK		 2464#endif
2465
64a88d5d 2466#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2467 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2468 goto illegal_insn;
2469#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2470 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2471 goto nfpu_insn;
2472
0bee699e 2473/* before an instruction, dc->pc must be static */
0184e266 2474static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2475{
0184e266 2476 unsigned int opc, rs1, rs2, rd;
a4273524 2477 TCGv cpu_src1, cpu_src2;
208ae657 2478 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2479 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2480 target_long simm;
7a3f1944 2481
cf495bcf 2482 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2483 rd = GET_FIELD(insn, 2, 6);
6ae20372 2484
cf495bcf 2485 switch (opc) {
0f8a249a
BS		 2486 case 0: /* branches/sethi */
2487 {
2488 unsigned int xop = GET_FIELD(insn, 7, 9);
2489 int32_t target;
2490 switch (xop) {
3475187d 2491#ifdef TARGET_SPARC64
0f8a249a
BS		 2492 case 0x1: /* V9 BPcc */
2493 {
2494 int cc;
2495
2496 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2497 target = sign_extend(target, 19);
0f8a249a
BS		 2498 target <<= 2;
2499 cc = GET_FIELD_SP(insn, 20, 21);
2500 if (cc == 0)
d4a288ef 2501 do_branch(dc, target, insn, 0);
0f8a249a 2502 else if (cc == 2)
d4a288ef 2503 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2504 else
2505 goto illegal_insn;
2506 goto jmp_insn;
2507 }
2508 case 0x3: /* V9 BPr */
2509 {
2510 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2511 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2512 target = sign_extend(target, 16);
2513 target <<= 2;
9d1d4e34 2514 cpu_src1 = get_src1(dc, insn);
d4a288ef 2515 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2516 goto jmp_insn;
2517 }
2518 case 0x5: /* V9 FBPcc */
2519 {
2520 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2521 if (gen_trap_ifnofpu(dc)) {
a80dde08 2522 goto jmp_insn;
5b12f1e8 2523 }
0f8a249a
BS		 2524 target = GET_FIELD_SP(insn, 0, 18);
2525 target = sign_extend(target, 19);
2526 target <<= 2;
d4a288ef 2527 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2528 goto jmp_insn;
2529 }
a4d17f19 2530#else
0f8a249a
BS		 2531 case 0x7: /* CBN+x */
2532 {
2533 goto ncp_insn;
2534 }
2535#endif
2536 case 0x2: /* BN+x */
2537 {
2538 target = GET_FIELD(insn, 10, 31);
2539 target = sign_extend(target, 22);
2540 target <<= 2;
d4a288ef 2541 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2542 goto jmp_insn;
2543 }
2544 case 0x6: /* FBN+x */
2545 {
5b12f1e8 2546 if (gen_trap_ifnofpu(dc)) {
a80dde08 2547 goto jmp_insn;
5b12f1e8 2548 }
0f8a249a
BS		 2549 target = GET_FIELD(insn, 10, 31);
2550 target = sign_extend(target, 22);
2551 target <<= 2;
d4a288ef 2552 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2553 goto jmp_insn;
2554 }
2555 case 0x4: /* SETHI */
97ea2859
RH		 2556 /* Special-case %g0 because that's the canonical nop. */
2557 if (rd) {
0f8a249a 2558 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2559 TCGv t = gen_dest_gpr(dc, rd);
2560 tcg_gen_movi_tl(t, value << 10);
2561 gen_store_gpr(dc, rd, t);
0f8a249a 2562 }
0f8a249a
BS		 2563 break;
2564 case 0x0: /* UNIMPL */
2565 default:
3475187d 2566 goto illegal_insn;
0f8a249a
BS		 2567 }
2568 break;
2569 }
2570 break;
dc1a6971
BS		 2571 case 1: /*CALL*/
2572 {
0f8a249a 2573 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2574 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2575
97ea2859
RH		 2576 tcg_gen_movi_tl(o7, dc->pc);
2577 gen_store_gpr(dc, 15, o7);
0f8a249a 2578 target += dc->pc;
13a6dd00 2579 gen_mov_pc_npc(dc);
22036a49
AT		 2580#ifdef TARGET_SPARC64
2581 if (unlikely(AM_CHECK(dc))) {
2582 target &= 0xffffffffULL;
2583 }
2584#endif
0f8a249a
BS		 2585 dc->npc = target;
2586 }
2587 goto jmp_insn;
2588 case 2: /* FPU & Logical Operations */
2589 {
2590 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2591 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2592 TCGv cpu_tmp0;
5793f2a4 2593
0f8a249a 2594 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2595 int cond = GET_FIELD(insn, 3, 6);
2596 TCGv_i32 trap;
42a268c2
RH		 2597 TCGLabel *l1 = NULL;
2598 int mask;
3475187d 2599
bd49ed41
RH		 2600 if (cond == 0) {
2601 /* Trap never. */
2602 break;
cf495bcf 2603 }
b04d9890 2604
bd49ed41 2605 save_state(dc);
b04d9890 2606
bd49ed41
RH		 2607 if (cond != 8) {
2608 /* Conditional trap. */
3a49e759 2609 DisasCompare cmp;
3475187d 2610#ifdef TARGET_SPARC64
0f8a249a
BS		 2611 /* V9 icc/xcc */
2612 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2613 if (cc == 0) {
2614 gen_compare(&cmp, 0, cond, dc);
2615 } else if (cc == 2) {
2616 gen_compare(&cmp, 1, cond, dc);
2617 } else {
0f8a249a 2618 goto illegal_insn;
3a49e759 2619 }
3475187d 2620#else
3a49e759 2621 gen_compare(&cmp, 0, cond, dc);
3475187d 2622#endif
b158a785 2623 l1 = gen_new_label();
3a49e759
RH		 2624 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2625 cmp.c1, cmp.c2, l1);
2626 free_compare(&cmp);
bd49ed41 2627 }
b158a785 2628
bd49ed41
RH		 2629 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2630 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2631
2632 /* Don't use the normal temporaries, as they may well have
2633 gone out of scope with the branch above. While we're
2634 doing that we might as well pre-truncate to 32-bit. */
2635 trap = tcg_temp_new_i32();
2636
2637 rs1 = GET_FIELD_SP(insn, 14, 18);
2638 if (IS_IMM) {
2639 rs2 = GET_FIELD_SP(insn, 0, 6);
2640 if (rs1 == 0) {
2641 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2642 /* Signal that the trap value is fully constant. */
2643 mask = 0;
2644 } else {
97ea2859 2645 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2646 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2647 tcg_gen_addi_i32(trap, trap, rs2);
2648 }
2649 } else {
97ea2859 2650 TCGv t1, t2;
bd49ed41 2651 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2652 t1 = gen_load_gpr(dc, rs1);
2653 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2654 tcg_gen_add_tl(t1, t1, t2);
2655 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2656 }
2657 if (mask != 0) {
2658 tcg_gen_andi_i32(trap, trap, mask);
2659 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2660 }
2661
2662 gen_helper_raise_exception(cpu_env, trap);
2663 tcg_temp_free_i32(trap);
b158a785 2664
fe1755cb
RH		 2665 if (cond == 8) {
2666 /* An unconditional trap ends the TB. */
2667 dc->is_br = 1;
2668 goto jmp_insn;
2669 } else {
2670 /* A conditional trap falls through to the next insn. */
b158a785 2671 gen_set_label(l1);
fe1755cb 2672 break;
cf495bcf
FB		 2673 }
2674 } else if (xop == 0x28) {
2675 rs1 = GET_FIELD(insn, 13, 17);
2676 switch(rs1) {
2677 case 0: /* rdy */
65fe7b09
BS		 2678#ifndef TARGET_SPARC64
2679 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2680 manual, rdy on the microSPARC
2681 II */
2682 case 0x0f: /* stbar in the SPARCv8 manual,
2683 rdy on the microSPARC II */
2684 case 0x10 ... 0x1f: /* implementation-dependent in the
2685 SPARCv8 manual, rdy on the
2686 microSPARC II */
4a2ba232
FC		 2687 /* Read Asr17 */
2688 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2689 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2690 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2691 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2692 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2693 break;
2694 }
65fe7b09 2695#endif
97ea2859 2696 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2697 break;
3475187d 2698#ifdef TARGET_SPARC64
0f8a249a 2699 case 0x2: /* V9 rdccr */
20132b96 2700 update_psr(dc);
063c3675 2701 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2702 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2703 break;
0f8a249a 2704 case 0x3: /* V9 rdasi */
255e1fcb 2705 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
97ea2859 2706 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2707 break;
0f8a249a 2708 case 0x4: /* V9 rdtick */
ccd4a219 2709 {
a7812ae4 2710 TCGv_ptr r_tickptr;
ccd4a219 2711
a7812ae4 2712 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2713 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2714 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 2715 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2716 tcg_temp_free_ptr(r_tickptr);
97ea2859 2717 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2718 }
3475187d 2719 break;
0f8a249a 2720 case 0x5: /* V9 rdpc */
2ea815ca 2721 {
97ea2859 2722 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2723 if (unlikely(AM_CHECK(dc))) {
97ea2859 2724 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2725 } else {
97ea2859 2726 tcg_gen_movi_tl(t, dc->pc);
22036a49 2727 }
97ea2859 2728 gen_store_gpr(dc, rd, t);
2ea815ca 2729 }
0f8a249a
BS		 2730 break;
2731 case 0x6: /* V9 rdfprs */
255e1fcb 2732 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2733 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2734 break;
65fe7b09
BS		 2735 case 0xf: /* V9 membar */
2736 break; /* no effect */
0f8a249a 2737 case 0x13: /* Graphics Status */
5b12f1e8 2738 if (gen_trap_ifnofpu(dc)) {
725cb90b 2739 goto jmp_insn;
5b12f1e8 2740 }
97ea2859 2741 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2742 break;
9d926598
BS		 2743 case 0x16: /* Softint */
2744 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
97ea2859 2745 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2746 break;
0f8a249a 2747 case 0x17: /* Tick compare */
97ea2859 2748 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2749 break;
0f8a249a 2750 case 0x18: /* System tick */
ccd4a219 2751 {
a7812ae4 2752 TCGv_ptr r_tickptr;
ccd4a219 2753
a7812ae4 2754 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2755 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2756 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 2757 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2758 tcg_temp_free_ptr(r_tickptr);
97ea2859 2759 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2760 }
83469015 2761 break;
0f8a249a 2762 case 0x19: /* System tick compare */
97ea2859 2763 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2764 break;
0f8a249a
BS		 2765 case 0x10: /* Performance Control */
2766 case 0x11: /* Performance Instrumentation Counter */
2767 case 0x12: /* Dispatch Control */
2768 case 0x14: /* Softint set, WO */
2769 case 0x15: /* Softint clear, WO */
3475187d
FB		 2770#endif
2771 default:
cf495bcf
FB		 2772 goto illegal_insn;
2773 }
e8af50a3 2774#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2775 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2776#ifndef TARGET_SPARC64
20132b96 2777 if (!supervisor(dc)) {
0f8a249a 2778 goto priv_insn;
20132b96
RH		 2779 }
2780 update_psr(dc);
063c3675 2781 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2782#else
fb79ceb9 2783 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2784 if (!hypervisor(dc))
2785 goto priv_insn;
2786 rs1 = GET_FIELD(insn, 13, 17);
2787 switch (rs1) {
2788 case 0: // hpstate
2789 // gen_op_rdhpstate();
2790 break;
2791 case 1: // htstate
2792 // gen_op_rdhtstate();
2793 break;
2794 case 3: // hintp
255e1fcb 2795 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2796 break;
2797 case 5: // htba
255e1fcb 2798 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2799 break;
2800 case 6: // hver
255e1fcb 2801 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2802 break;
2803 case 31: // hstick_cmpr
255e1fcb 2804 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2805 break;
2806 default:
2807 goto illegal_insn;
2808 }
2809#endif
97ea2859 2810 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2811 break;
3475187d 2812 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2813 if (!supervisor(dc)) {
0f8a249a 2814 goto priv_insn;
de9e9d9f
RH		 2815 }
2816 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2817#ifdef TARGET_SPARC64
2818 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2819 switch (rs1) {
2820 case 0: // tpc
375ee38b 2821 {
a7812ae4 2822 TCGv_ptr r_tsptr;
375ee38b 2823
a7812ae4 2824 r_tsptr = tcg_temp_new_ptr();
8194f35a 2825 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2826 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2827 offsetof(trap_state, tpc));
a7812ae4 2828 tcg_temp_free_ptr(r_tsptr);
375ee38b 2829 }
0f8a249a
BS		 2830 break;
2831 case 1: // tnpc
375ee38b 2832 {
a7812ae4 2833 TCGv_ptr r_tsptr;
375ee38b 2834
a7812ae4 2835 r_tsptr = tcg_temp_new_ptr();
8194f35a 2836 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2837 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2838 offsetof(trap_state, tnpc));
a7812ae4 2839 tcg_temp_free_ptr(r_tsptr);
375ee38b 2840 }
0f8a249a
BS		 2841 break;
2842 case 2: // tstate
375ee38b 2843 {
a7812ae4 2844 TCGv_ptr r_tsptr;
375ee38b 2845
a7812ae4 2846 r_tsptr = tcg_temp_new_ptr();
8194f35a 2847 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2848 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2849 offsetof(trap_state, tstate));
a7812ae4 2850 tcg_temp_free_ptr(r_tsptr);
375ee38b 2851 }
0f8a249a
BS		 2852 break;
2853 case 3: // tt
375ee38b 2854 {
45778f99 2855 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2856
8194f35a 2857 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2858 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2859 offsetof(trap_state, tt));
a7812ae4 2860 tcg_temp_free_ptr(r_tsptr);
375ee38b 2861 }
0f8a249a
BS		 2862 break;
2863 case 4: // tick
ccd4a219 2864 {
a7812ae4 2865 TCGv_ptr r_tickptr;
ccd4a219 2866
a7812ae4 2867 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2868 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2869 offsetof(CPUSPARCState, tick));
a7812ae4 2870 gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
a7812ae4 2871 tcg_temp_free_ptr(r_tickptr);
ccd4a219 2872 }
0f8a249a
BS		 2873 break;
2874 case 5: // tba
255e1fcb 2875 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2876 break;
2877 case 6: // pstate
45778f99
RH		 2878 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2879 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2880 break;
2881 case 7: // tl
45778f99
RH		 2882 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2883 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 2884 break;
2885 case 8: // pil
45778f99
RH		 2886 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2887 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 2888 break;
2889 case 9: // cwp
063c3675 2890 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2891 break;
2892 case 10: // cansave
45778f99
RH		 2893 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2894 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 2895 break;
2896 case 11: // canrestore
45778f99
RH		 2897 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2898 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 2899 break;
2900 case 12: // cleanwin
45778f99
RH		 2901 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2902 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 2903 break;
2904 case 13: // otherwin
45778f99
RH		 2905 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2906 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 2907 break;
2908 case 14: // wstate
45778f99
RH		 2909 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2910 offsetof(CPUSPARCState, wstate));
0f8a249a 2911 break;
e9ebed4d 2912 case 16: // UA2005 gl
fb79ceb9 2913 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 2914 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2915 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 2916 break;
2917 case 26: // UA2005 strand status
fb79ceb9 2918 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2919 if (!hypervisor(dc))
2920 goto priv_insn;
527067d8 2921 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2922 break;
0f8a249a 2923 case 31: // ver
255e1fcb 2924 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2925 break;
2926 case 15: // fq
2927 default:
2928 goto illegal_insn;
2929 }
3475187d 2930#else
255e1fcb 2931 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2932#endif
97ea2859 2933 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 2934 break;
3475187d
FB		 2935 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2936#ifdef TARGET_SPARC64
66442b07 2937 save_state(dc);
063c3675 2938 gen_helper_flushw(cpu_env);
3475187d 2939#else
0f8a249a
BS		 2940 if (!supervisor(dc))
2941 goto priv_insn;
97ea2859 2942 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 2943#endif
e8af50a3
FB		 2944 break;
2945#endif
0f8a249a 2946 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 2947 if (gen_trap_ifnofpu(dc)) {
a80dde08 2948 goto jmp_insn;
5b12f1e8 2949 }
0f8a249a 2950 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2951 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2952 rs2 = GET_FIELD(insn, 27, 31);
2953 xop = GET_FIELD(insn, 18, 26);
66442b07 2954 save_state(dc);
0f8a249a 2955 switch (xop) {
dc1a6971 2956 case 0x1: /* fmovs */
208ae657
RH		 2957 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2958 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2959 break;
2960 case 0x5: /* fnegs */
61f17f6e 2961 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2962 break;
2963 case 0x9: /* fabss */
61f17f6e 2964 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2965 break;
2966 case 0x29: /* fsqrts */
2967 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2968 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2969 break;
2970 case 0x2a: /* fsqrtd */
2971 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2972 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2973 break;
2974 case 0x2b: /* fsqrtq */
2975 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2976 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2977 break;
2978 case 0x41: /* fadds */
61f17f6e 2979 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2980 break;
2981 case 0x42: /* faddd */
61f17f6e 2982 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2983 break;
2984 case 0x43: /* faddq */
2985 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2986 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2987 break;
2988 case 0x45: /* fsubs */
61f17f6e 2989 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2990 break;
2991 case 0x46: /* fsubd */
61f17f6e 2992 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 2993 break;
2994 case 0x47: /* fsubq */
2995 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2996 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 2997 break;
2998 case 0x49: /* fmuls */
2999 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3000 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3001 break;
3002 case 0x4a: /* fmuld */
3003 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3004 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3005 break;
3006 case 0x4b: /* fmulq */
3007 CHECK_FPU_FEATURE(dc, FLOAT128);
3008 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3009 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3010 break;
3011 case 0x4d: /* fdivs */
61f17f6e 3012 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3013 break;
3014 case 0x4e: /* fdivd */
61f17f6e 3015 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3016 break;
3017 case 0x4f: /* fdivq */
3018 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3019 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3020 break;
3021 case 0x69: /* fsmuld */
3022 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3023 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3024 break;
3025 case 0x6e: /* fdmulq */
3026 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3027 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3028 break;
3029 case 0xc4: /* fitos */
61f17f6e 3030 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3031 break;
3032 case 0xc6: /* fdtos */
61f17f6e 3033 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3034 break;
3035 case 0xc7: /* fqtos */
3036 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3037 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3038 break;
3039 case 0xc8: /* fitod */
61f17f6e 3040 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3041 break;
3042 case 0xc9: /* fstod */
61f17f6e 3043 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3044 break;
3045 case 0xcb: /* fqtod */
3046 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3047 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3048 break;
3049 case 0xcc: /* fitoq */
3050 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3051 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3052 break;
3053 case 0xcd: /* fstoq */
3054 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3055 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3056 break;
3057 case 0xce: /* fdtoq */
3058 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3059 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3060 break;
3061 case 0xd1: /* fstoi */
61f17f6e 3062 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3063 break;
3064 case 0xd2: /* fdtoi */
61f17f6e 3065 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3066 break;
3067 case 0xd3: /* fqtoi */
3068 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3069 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3070 break;
3475187d 3071#ifdef TARGET_SPARC64
dc1a6971 3072 case 0x2: /* V9 fmovd */
96eda024
RH		 3073 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3074 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3075 break;
3076 case 0x3: /* V9 fmovq */
3077 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3078 gen_move_Q(rd, rs2);
dc1a6971
BS		 3079 break;
3080 case 0x6: /* V9 fnegd */
61f17f6e 3081 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3082 break;
3083 case 0x7: /* V9 fnegq */
3084 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3085 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3086 break;
3087 case 0xa: /* V9 fabsd */
61f17f6e 3088 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3089 break;
3090 case 0xb: /* V9 fabsq */
3091 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3092 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3093 break;
3094 case 0x81: /* V9 fstox */
61f17f6e 3095 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3096 break;
3097 case 0x82: /* V9 fdtox */
61f17f6e 3098 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3099 break;
3100 case 0x83: /* V9 fqtox */
3101 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3102 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3103 break;
3104 case 0x84: /* V9 fxtos */
61f17f6e 3105 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3106 break;
3107 case 0x88: /* V9 fxtod */
61f17f6e 3108 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3109 break;
3110 case 0x8c: /* V9 fxtoq */
3111 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3112 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3113 break;
0f8a249a 3114#endif
dc1a6971
BS		 3115 default:
3116 goto illegal_insn;
0f8a249a
BS		 3117 }
3118 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3119#ifdef TARGET_SPARC64
0f8a249a 3120 int cond;
3475187d 3121#endif
5b12f1e8 3122 if (gen_trap_ifnofpu(dc)) {
a80dde08 3123 goto jmp_insn;
5b12f1e8 3124 }
0f8a249a 3125 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3126 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3127 rs2 = GET_FIELD(insn, 27, 31);
3128 xop = GET_FIELD(insn, 18, 26);
66442b07 3129 save_state(dc);
dcf24905 3130
690995a6
RH		 3131#ifdef TARGET_SPARC64
3132#define FMOVR(sz) \
3133 do { \
3134 DisasCompare cmp; \
e7c8afb9 3135 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3136 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3137 gen_compare_reg(&cmp, cond, cpu_src1); \
3138 gen_fmov##sz(dc, &cmp, rd, rs2); \
3139 free_compare(&cmp); \
3140 } while (0)
3141
3142 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3143 FMOVR(s);
0f8a249a
BS		 3144 break;
3145 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3146 FMOVR(d);
0f8a249a
BS		 3147 break;
3148 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3149 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3150 FMOVR(q);
1f587329 3151 break;
0f8a249a 3152 }
690995a6 3153#undef FMOVR
0f8a249a
BS		 3154#endif
3155 switch (xop) {
3475187d 3156#ifdef TARGET_SPARC64
7e480893
RH		 3157#define FMOVCC(fcc, sz) \
3158 do { \
3159 DisasCompare cmp; \
714547bb 3160 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3161 gen_fcompare(&cmp, fcc, cond); \
3162 gen_fmov##sz(dc, &cmp, rd, rs2); \
3163 free_compare(&cmp); \
3164 } while (0)
3165
0f8a249a 3166 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3167 FMOVCC(0, s);
0f8a249a
BS		 3168 break;
3169 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3170 FMOVCC(0, d);
0f8a249a
BS		 3171 break;
3172 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3173 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3174 FMOVCC(0, q);
1f587329 3175 break;
0f8a249a 3176 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3177 FMOVCC(1, s);
0f8a249a
BS		 3178 break;
3179 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3180 FMOVCC(1, d);
0f8a249a
BS		 3181 break;
3182 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3183 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3184 FMOVCC(1, q);
1f587329 3185 break;
0f8a249a 3186 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3187 FMOVCC(2, s);
0f8a249a
BS		 3188 break;
3189 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3190 FMOVCC(2, d);
0f8a249a
BS		 3191 break;
3192 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3193 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3194 FMOVCC(2, q);
1f587329 3195 break;
0f8a249a 3196 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3197 FMOVCC(3, s);
0f8a249a
BS		 3198 break;
3199 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3200 FMOVCC(3, d);
0f8a249a
BS		 3201 break;
3202 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3203 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3204 FMOVCC(3, q);
1f587329 3205 break;
7e480893
RH		 3206#undef FMOVCC
3207#define FMOVCC(xcc, sz) \
3208 do { \
3209 DisasCompare cmp; \
714547bb 3210 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3211 gen_compare(&cmp, xcc, cond, dc); \
3212 gen_fmov##sz(dc, &cmp, rd, rs2); \
3213 free_compare(&cmp); \
3214 } while (0)
19f329ad 3215
0f8a249a 3216 case 0x101: /* V9 fmovscc %icc */
7e480893 3217 FMOVCC(0, s);
0f8a249a
BS		 3218 break;
3219 case 0x102: /* V9 fmovdcc %icc */
7e480893 3220 FMOVCC(0, d);
b7d69dc2 3221 break;
0f8a249a 3222 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3223 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3224 FMOVCC(0, q);
1f587329 3225 break;
0f8a249a 3226 case 0x181: /* V9 fmovscc %xcc */
7e480893 3227 FMOVCC(1, s);
0f8a249a
BS		 3228 break;
3229 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3230 FMOVCC(1, d);
0f8a249a
BS		 3231 break;
3232 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3233 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3234 FMOVCC(1, q);
1f587329 3235 break;
7e480893 3236#undef FMOVCC
1f587329
BS		 3237#endif
3238 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3239 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3240 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3241 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3242 break;
1f587329 3243 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3244 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3245 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3246 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3247 break;
1f587329 3248 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3249 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3250 gen_op_load_fpr_QT0(QFPREG(rs1));
3251 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3252 gen_op_fcmpq(rd & 3);
1f587329 3253 break;
0f8a249a 3254 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3255 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3256 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3257 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3258 break;
3259 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3260 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3261 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3262 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3263 break;
1f587329 3264 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3265 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3266 gen_op_load_fpr_QT0(QFPREG(rs1));
3267 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3268 gen_op_fcmpeq(rd & 3);
1f587329 3269 break;
0f8a249a
BS		 3270 default:
3271 goto illegal_insn;
3272 }
0f8a249a 3273 } else if (xop == 0x2) {
97ea2859 3274 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3275 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3276 if (rs1 == 0) {
97ea2859 3277 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3278 if (IS_IMM) { /* immediate */
67526b20 3279 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3280 tcg_gen_movi_tl(dst, simm);
3281 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3282 } else { /* register */
3283 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3284 if (rs2 == 0) {
3285 tcg_gen_movi_tl(dst, 0);
3286 gen_store_gpr(dc, rd, dst);
3287 } else {
3288 cpu_src2 = gen_load_gpr(dc, rs2);
3289 gen_store_gpr(dc, rd, cpu_src2);
3290 }
0f8a249a 3291 }
0f8a249a 3292 } else {
9d1d4e34 3293 cpu_src1 = get_src1(dc, insn);
0f8a249a 3294 if (IS_IMM) { /* immediate */
67526b20 3295 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3296 tcg_gen_ori_tl(dst, cpu_src1, simm);
3297 gen_store_gpr(dc, rd, dst);
0f8a249a 3298 } else { /* register */
0f8a249a 3299 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3300 if (rs2 == 0) {
3301 /* mov shortcut: or x, %g0, y -> mov x, y */
3302 gen_store_gpr(dc, rd, cpu_src1);
3303 } else {
3304 cpu_src2 = gen_load_gpr(dc, rs2);
3305 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3306 gen_store_gpr(dc, rd, dst);
3307 }
0f8a249a 3308 }
0f8a249a 3309 }
83469015 3310#ifdef TARGET_SPARC64
0f8a249a 3311 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3312 cpu_src1 = get_src1(dc, insn);
0f8a249a 3313 if (IS_IMM) { /* immediate */
67526b20 3314 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3315 if (insn & (1 << 12)) {
67526b20 3316 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3317 } else {
67526b20 3318 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3319 }
0f8a249a 3320 } else { /* register */
83469015 3321 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3322 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3323 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3324 if (insn & (1 << 12)) {
6ae20372 3325 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3326 } else {
6ae20372 3327 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3328 }
01b1fa6d 3329 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3330 }
97ea2859 3331 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3332 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3333 cpu_src1 = get_src1(dc, insn);
0f8a249a 3334 if (IS_IMM) { /* immediate */
67526b20 3335 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3336 if (insn & (1 << 12)) {
67526b20 3337 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3338 } else {
6ae20372 3339 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3340 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3341 }
0f8a249a 3342 } else { /* register */
83469015 3343 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3344 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3345 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3346 if (insn & (1 << 12)) {
6ae20372
BS		 3347 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3348 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3349 } else {
6ae20372
BS		 3350 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3351 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3352 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3353 }
83469015 3354 }
97ea2859 3355 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3356 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3357 cpu_src1 = get_src1(dc, insn);
0f8a249a 3358 if (IS_IMM) { /* immediate */
67526b20 3359 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3360 if (insn & (1 << 12)) {
67526b20 3361 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3362 } else {
97ea2859 3363 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3364 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3365 }
0f8a249a 3366 } else { /* register */
83469015 3367 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3368 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3369 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3370 if (insn & (1 << 12)) {
6ae20372
BS		 3371 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3372 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3373 } else {
6ae20372 3374 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3375 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3376 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3377 }
83469015 3378 }
97ea2859 3379 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3380#endif
fcc72045 3381 } else if (xop < 0x36) {
cf495bcf 3382 if (xop < 0x20) {
9d1d4e34
RH		 3383 cpu_src1 = get_src1(dc, insn);
3384 cpu_src2 = get_src2(dc, insn);
cf495bcf 3385 switch (xop & ~0x10) {
b89e94af 3386 case 0x0: /* add */
97ea2859
RH		 3387 if (xop & 0x10) {
3388 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3389 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3390 dc->cc_op = CC_OP_ADD;
41d72852 3391 } else {
97ea2859 3392 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3393 }
cf495bcf 3394 break;
b89e94af 3395 case 0x1: /* and */
97ea2859 3396 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3397 if (xop & 0x10) {
38482a77
BS		 3398 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3399 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3400 dc->cc_op = CC_OP_LOGIC;
41d72852 3401 }
cf495bcf 3402 break;
b89e94af 3403 case 0x2: /* or */
97ea2859 3404 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3405 if (xop & 0x10) {
38482a77
BS		 3406 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3407 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3408 dc->cc_op = CC_OP_LOGIC;
8393617c 3409 }
0f8a249a 3410 break;
b89e94af 3411 case 0x3: /* xor */
97ea2859 3412 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3413 if (xop & 0x10) {
38482a77
BS		 3414 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3415 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3416 dc->cc_op = CC_OP_LOGIC;
8393617c 3417 }
cf495bcf 3418 break;
b89e94af 3419 case 0x4: /* sub */
97ea2859
RH		 3420 if (xop & 0x10) {
3421 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3422 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3423 dc->cc_op = CC_OP_SUB;
41d72852 3424 } else {
97ea2859 3425 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3426 }
cf495bcf 3427 break;
b89e94af 3428 case 0x5: /* andn */
97ea2859 3429 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3430 if (xop & 0x10) {
38482a77
BS		 3431 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3432 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3433 dc->cc_op = CC_OP_LOGIC;
8393617c 3434 }
cf495bcf 3435 break;
b89e94af 3436 case 0x6: /* orn */
97ea2859 3437 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3438 if (xop & 0x10) {
38482a77
BS		 3439 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3440 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3441 dc->cc_op = CC_OP_LOGIC;
8393617c 3442 }
cf495bcf 3443 break;
b89e94af 3444 case 0x7: /* xorn */
97ea2859 3445 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3446 if (xop & 0x10) {
38482a77
BS		 3447 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3448 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3449 dc->cc_op = CC_OP_LOGIC;
8393617c 3450 }
cf495bcf 3451 break;
b89e94af 3452 case 0x8: /* addx, V9 addc */
70c48285
RH		 3453 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3454 (xop & 0x10));
cf495bcf 3455 break;
ded3ab80 3456#ifdef TARGET_SPARC64
0f8a249a 3457 case 0x9: /* V9 mulx */
97ea2859 3458 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3459 break;
3460#endif
b89e94af 3461 case 0xa: /* umul */
64a88d5d 3462 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3463 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3464 if (xop & 0x10) {
38482a77
BS		 3465 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3466 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3467 dc->cc_op = CC_OP_LOGIC;
8393617c 3468 }
cf495bcf 3469 break;
b89e94af 3470 case 0xb: /* smul */
64a88d5d 3471 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3472 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3473 if (xop & 0x10) {
38482a77
BS		 3474 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3475 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3476 dc->cc_op = CC_OP_LOGIC;
8393617c 3477 }
cf495bcf 3478 break;
b89e94af 3479 case 0xc: /* subx, V9 subc */
70c48285
RH		 3480 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3481 (xop & 0x10));
cf495bcf 3482 break;
ded3ab80 3483#ifdef TARGET_SPARC64
0f8a249a 3484 case 0xd: /* V9 udivx */
c28ae41e 3485 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3486 break;
3487#endif
b89e94af 3488 case 0xe: /* udiv */
64a88d5d 3489 CHECK_IU_FEATURE(dc, DIV);
8393617c 3490 if (xop & 0x10) {
7a5e4488
BS		 3491 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3492 cpu_src2);
6c78ea32 3493 dc->cc_op = CC_OP_DIV;
0fcec41e 3494 } else {
7a5e4488
BS		 3495 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3496 cpu_src2);
8393617c 3497 }
cf495bcf 3498 break;
b89e94af 3499 case 0xf: /* sdiv */
64a88d5d 3500 CHECK_IU_FEATURE(dc, DIV);
8393617c 3501 if (xop & 0x10) {
7a5e4488
BS		 3502 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3503 cpu_src2);
6c78ea32 3504 dc->cc_op = CC_OP_DIV;
0fcec41e 3505 } else {
7a5e4488
BS		 3506 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3507 cpu_src2);
8393617c 3508 }
cf495bcf
FB		 3509 break;
3510 default:
3511 goto illegal_insn;
3512 }
97ea2859 3513 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3514 } else {
9d1d4e34
RH		 3515 cpu_src1 = get_src1(dc, insn);
3516 cpu_src2 = get_src2(dc, insn);
cf495bcf 3517 switch (xop) {
0f8a249a 3518 case 0x20: /* taddcc */
a2ea4aa9 3519 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3520 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3521 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3522 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3523 break;
3524 case 0x21: /* tsubcc */
a2ea4aa9 3525 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3526 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3527 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3528 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3529 break;
3530 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3531 gen_helper_taddcctv(cpu_dst, cpu_env,
3532 cpu_src1, cpu_src2);
97ea2859 3533 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3534 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3535 break;
3536 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3537 gen_helper_tsubcctv(cpu_dst, cpu_env,
3538 cpu_src1, cpu_src2);
97ea2859 3539 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3540 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3541 break;
cf495bcf 3542 case 0x24: /* mulscc */
20132b96 3543 update_psr(dc);
6ae20372 3544 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3545 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3546 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3547 dc->cc_op = CC_OP_ADD;
cf495bcf 3548 break;
83469015 3549#ifndef TARGET_SPARC64
0f8a249a 3550 case 0x25: /* sll */
e35298cd 3551 if (IS_IMM) { /* immediate */
67526b20
BS		 3552 simm = GET_FIELDs(insn, 20, 31);
3553 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3554 } else { /* register */
de9e9d9f 3555 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3556 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3557 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3558 }
97ea2859 3559 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3560 break;
83469015 3561 case 0x26: /* srl */
e35298cd 3562 if (IS_IMM) { /* immediate */
67526b20
BS		 3563 simm = GET_FIELDs(insn, 20, 31);
3564 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3565 } else { /* register */
de9e9d9f 3566 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3567 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3568 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3569 }
97ea2859 3570 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3571 break;
83469015 3572 case 0x27: /* sra */
e35298cd 3573 if (IS_IMM) { /* immediate */
67526b20
BS		 3574 simm = GET_FIELDs(insn, 20, 31);
3575 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3576 } else { /* register */
de9e9d9f 3577 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3578 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3579 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3580 }
97ea2859 3581 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3582 break;
83469015 3583#endif
cf495bcf
FB		 3584 case 0x30:
3585 {
de9e9d9f 3586 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3587 switch(rd) {
3475187d 3588 case 0: /* wry */
5068cbd9
BS		 3589 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3590 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3591 break;
65fe7b09
BS		 3592#ifndef TARGET_SPARC64
3593 case 0x01 ... 0x0f: /* undefined in the
3594 SPARCv8 manual, nop
3595 on the microSPARC
3596 II */
3597 case 0x10 ... 0x1f: /* implementation-dependent
3598 in the SPARCv8
3599 manual, nop on the
3600 microSPARC II */
d1c36ba7
RH		 3601 if ((rd == 0x13) && (dc->def->features &
3602 CPU_FEATURE_POWERDOWN)) {
3603 /* LEON3 power-down */
1cf892ca 3604 save_state(dc);
d1c36ba7
RH		 3605 gen_helper_power_down(cpu_env);
3606 }
65fe7b09
BS		 3607 break;
3608#else
0f8a249a 3609 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3610 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3611 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3612 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3613 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3614 break;
3615 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3616 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3617 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
3618 tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
0f8a249a
BS		 3619 break;
3620 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3621 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3622 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3623 save_state(dc);
3299908c 3624 gen_op_next_insn();
57fec1fe 3625 tcg_gen_exit_tb(0);
3299908c 3626 dc->is_br = 1;
0f8a249a
BS		 3627 break;
3628 case 0xf: /* V9 sir, nop if user */
3475187d 3629#if !defined(CONFIG_USER_ONLY)
6ad6135d 3630 if (supervisor(dc)) {
1a2fb1c0 3631 ; // XXX
6ad6135d 3632 }
3475187d 3633#endif
0f8a249a
BS		 3634 break;
3635 case 0x13: /* Graphics Status */
5b12f1e8 3636 if (gen_trap_ifnofpu(dc)) {
725cb90b 3637 goto jmp_insn;
5b12f1e8 3638 }
255e1fcb 3639 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3640 break;
9d926598
BS		 3641 case 0x14: /* Softint set */
3642 if (!supervisor(dc))
3643 goto illegal_insn;
aeff993c
RH		 3644 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3645 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3646 break;
3647 case 0x15: /* Softint clear */
3648 if (!supervisor(dc))
3649 goto illegal_insn;
aeff993c
RH		 3650 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3651 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3652 break;
3653 case 0x16: /* Softint write */
3654 if (!supervisor(dc))
3655 goto illegal_insn;
aeff993c
RH		 3656 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3657 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3658 break;
0f8a249a 3659 case 0x17: /* Tick compare */
83469015 3660#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3661 if (!supervisor(dc))
3662 goto illegal_insn;
83469015 3663#endif
ccd4a219 3664 {
a7812ae4 3665 TCGv_ptr r_tickptr;
ccd4a219 3666
255e1fcb 3667 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3668 cpu_src2);
a7812ae4 3669 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3670 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3671 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3672 gen_helper_tick_set_limit(r_tickptr,
3673 cpu_tick_cmpr);
3674 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3675 }
0f8a249a
BS		 3676 break;
3677 case 0x18: /* System tick */
83469015 3678#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3679 if (!supervisor(dc))
3680 goto illegal_insn;
83469015 3681#endif
ccd4a219 3682 {
a7812ae4 3683 TCGv_ptr r_tickptr;
ccd4a219 3684
7b04bd5c 3685 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3686 cpu_src2);
a7812ae4 3687 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3688 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3689 offsetof(CPUSPARCState, stick));
a7812ae4 3690 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3691 cpu_tmp0);
a7812ae4 3692 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3693 }
0f8a249a
BS		 3694 break;
3695 case 0x19: /* System tick compare */
83469015 3696#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3697 if (!supervisor(dc))
3698 goto illegal_insn;
3475187d 3699#endif
ccd4a219 3700 {
a7812ae4 3701 TCGv_ptr r_tickptr;
ccd4a219 3702
255e1fcb 3703 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3704 cpu_src2);
a7812ae4 3705 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3706 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3707 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3708 gen_helper_tick_set_limit(r_tickptr,
3709 cpu_stick_cmpr);
3710 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3711 }
0f8a249a 3712 break;
83469015 3713
0f8a249a 3714 case 0x10: /* Performance Control */
77f193da
BS		 3715 case 0x11: /* Performance Instrumentation
3716 Counter */
0f8a249a 3717 case 0x12: /* Dispatch Control */
83469015 3718#endif
3475187d 3719 default:
cf495bcf
FB		 3720 goto illegal_insn;
3721 }
3722 }
3723 break;
e8af50a3 3724#if !defined(CONFIG_USER_ONLY)
af7bf89b 3725 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3726 {
0f8a249a
BS		 3727 if (!supervisor(dc))
3728 goto priv_insn;
3475187d 3729#ifdef TARGET_SPARC64
0f8a249a
BS		 3730 switch (rd) {
3731 case 0:
063c3675 3732 gen_helper_saved(cpu_env);
0f8a249a
BS		 3733 break;
3734 case 1:
063c3675 3735 gen_helper_restored(cpu_env);
0f8a249a 3736 break;
e9ebed4d
BS		 3737 case 2: /* UA2005 allclean */
3738 case 3: /* UA2005 otherw */
3739 case 4: /* UA2005 normalw */
3740 case 5: /* UA2005 invalw */
3741 // XXX
0f8a249a 3742 default:
3475187d
FB		 3743 goto illegal_insn;
3744 }
3745#else
de9e9d9f 3746 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3747 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3748 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3749 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3750 dc->cc_op = CC_OP_FLAGS;
66442b07 3751 save_state(dc);
9e61bde5 3752 gen_op_next_insn();
57fec1fe 3753 tcg_gen_exit_tb(0);
0f8a249a 3754 dc->is_br = 1;
3475187d 3755#endif
e8af50a3
FB		 3756 }
3757 break;
af7bf89b 3758 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3759 {
0f8a249a
BS		 3760 if (!supervisor(dc))
3761 goto priv_insn;
de9e9d9f 3762 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3763 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3764#ifdef TARGET_SPARC64
0f8a249a
BS		 3765 switch (rd) {
3766 case 0: // tpc
375ee38b 3767 {
a7812ae4 3768 TCGv_ptr r_tsptr;
375ee38b 3769
a7812ae4 3770 r_tsptr = tcg_temp_new_ptr();
8194f35a 3771 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3772 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3773 offsetof(trap_state, tpc));
a7812ae4 3774 tcg_temp_free_ptr(r_tsptr);
375ee38b 3775 }
0f8a249a
BS		 3776 break;
3777 case 1: // tnpc
375ee38b 3778 {
a7812ae4 3779 TCGv_ptr r_tsptr;
375ee38b 3780
a7812ae4 3781 r_tsptr = tcg_temp_new_ptr();
8194f35a 3782 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3783 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3784 offsetof(trap_state, tnpc));
a7812ae4 3785 tcg_temp_free_ptr(r_tsptr);
375ee38b 3786 }
0f8a249a
BS		 3787 break;
3788 case 2: // tstate
375ee38b 3789 {
a7812ae4 3790 TCGv_ptr r_tsptr;
375ee38b 3791
a7812ae4 3792 r_tsptr = tcg_temp_new_ptr();
8194f35a 3793 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3794 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3795 offsetof(trap_state,
3796 tstate));
a7812ae4 3797 tcg_temp_free_ptr(r_tsptr);
375ee38b 3798 }
0f8a249a
BS		 3799 break;
3800 case 3: // tt
375ee38b 3801 {
a7812ae4 3802 TCGv_ptr r_tsptr;
375ee38b 3803
a7812ae4 3804 r_tsptr = tcg_temp_new_ptr();
8194f35a 3805 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3806 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3807 offsetof(trap_state, tt));
a7812ae4 3808 tcg_temp_free_ptr(r_tsptr);
375ee38b 3809 }
0f8a249a
BS		 3810 break;
3811 case 4: // tick
ccd4a219 3812 {
a7812ae4 3813 TCGv_ptr r_tickptr;
ccd4a219 3814
a7812ae4 3815 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3816 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3817 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3818 gen_helper_tick_set_count(r_tickptr,
3819 cpu_tmp0);
3820 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3821 }
0f8a249a
BS		 3822 break;
3823 case 5: // tba
255e1fcb 3824 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3825 break;
3826 case 6: // pstate
6234ac09
RH		 3827 save_state(dc);
3828 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3829 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3830 break;
3831 case 7: // tl
6234ac09 3832 save_state(dc);
7b9e066b 3833 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3834 offsetof(CPUSPARCState, tl));
3835 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3836 break;
3837 case 8: // pil
063c3675 3838 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3839 break;
3840 case 9: // cwp
063c3675 3841 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3842 break;
3843 case 10: // cansave
7b9e066b
RH		 3844 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3845 offsetof(CPUSPARCState,
3846 cansave));
0f8a249a
BS		 3847 break;
3848 case 11: // canrestore
7b9e066b
RH		 3849 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3850 offsetof(CPUSPARCState,
3851 canrestore));
0f8a249a
BS		 3852 break;
3853 case 12: // cleanwin
7b9e066b
RH		 3854 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3855 offsetof(CPUSPARCState,
3856 cleanwin));
0f8a249a
BS		 3857 break;
3858 case 13: // otherwin
7b9e066b
RH		 3859 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3860 offsetof(CPUSPARCState,
3861 otherwin));
0f8a249a
BS		 3862 break;
3863 case 14: // wstate
7b9e066b
RH		 3864 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3865 offsetof(CPUSPARCState,
3866 wstate));
0f8a249a 3867 break;
e9ebed4d 3868 case 16: // UA2005 gl
fb79ceb9 3869 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 3870 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3871 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3872 break;
3873 case 26: // UA2005 strand status
fb79ceb9 3874 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3875 if (!hypervisor(dc))
3876 goto priv_insn;
527067d8 3877 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3878 break;
0f8a249a
BS		 3879 default:
3880 goto illegal_insn;
3881 }
3475187d 3882#else
7b9e066b
RH		 3883 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3884 if (dc->def->nwindows != 32) {
3885 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 3886 (1 << dc->def->nwindows) - 1);
7b9e066b 3887 }
3475187d 3888#endif
e8af50a3
FB		 3889 }
3890 break;
e9ebed4d 3891 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3892 {
e9ebed4d 3893#ifndef TARGET_SPARC64
0f8a249a
BS		 3894 if (!supervisor(dc))
3895 goto priv_insn;
255e1fcb 3896 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3897#else
fb79ceb9 3898 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3899 if (!hypervisor(dc))
3900 goto priv_insn;
de9e9d9f 3901 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3902 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3903 switch (rd) {
3904 case 0: // hpstate
3905 // XXX gen_op_wrhpstate();
66442b07 3906 save_state(dc);
e9ebed4d 3907 gen_op_next_insn();
57fec1fe 3908 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3909 dc->is_br = 1;
3910 break;
3911 case 1: // htstate
3912 // XXX gen_op_wrhtstate();
3913 break;
3914 case 3: // hintp
255e1fcb 3915 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3916 break;
3917 case 5: // htba
255e1fcb 3918 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3919 break;
3920 case 31: // hstick_cmpr
ccd4a219 3921 {
a7812ae4 3922 TCGv_ptr r_tickptr;
ccd4a219 3923
255e1fcb 3924 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3925 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3926 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3927 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 3928 gen_helper_tick_set_limit(r_tickptr,
3929 cpu_hstick_cmpr);
3930 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3931 }
e9ebed4d
BS		 3932 break;
3933 case 6: // hver readonly
3934 default:
3935 goto illegal_insn;
3936 }
3937#endif
e8af50a3
FB		 3938 }
3939 break;
3940#endif
3475187d 3941#ifdef TARGET_SPARC64
0f8a249a
BS		 3942 case 0x2c: /* V9 movcc */
3943 {
3944 int cc = GET_FIELD_SP(insn, 11, 12);
3945 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 3946 DisasCompare cmp;
97ea2859 3947 TCGv dst;
00f219bf 3948
0f8a249a 3949 if (insn & (1 << 18)) {
f52879b4
RH		 3950 if (cc == 0) {
3951 gen_compare(&cmp, 0, cond, dc);
3952 } else if (cc == 2) {
3953 gen_compare(&cmp, 1, cond, dc);
3954 } else {
0f8a249a 3955 goto illegal_insn;
f52879b4 3956 }
0f8a249a 3957 } else {
f52879b4 3958 gen_fcompare(&cmp, cc, cond);
0f8a249a 3959 }
00f219bf 3960
f52879b4
RH		 3961 /* The get_src2 above loaded the normal 13-bit
3962 immediate field, not the 11-bit field we have
3963 in movcc. But it did handle the reg case. */
3964 if (IS_IMM) {
67526b20 3965 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 3966 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 3967 }
f52879b4 3968
97ea2859
RH		 3969 dst = gen_load_gpr(dc, rd);
3970 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 3971 cmp.c1, cmp.c2,
97ea2859 3972 cpu_src2, dst);
f52879b4 3973 free_compare(&cmp);
97ea2859 3974 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3975 break;
3976 }
3977 case 0x2d: /* V9 sdivx */
c28ae41e 3978 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 3979 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 3980 break;
3981 case 0x2e: /* V9 popc */
97ea2859
RH		 3982 gen_helper_popc(cpu_dst, cpu_src2);
3983 gen_store_gpr(dc, rd, cpu_dst);
3984 break;
0f8a249a
BS		 3985 case 0x2f: /* V9 movr */
3986 {
3987 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 3988 DisasCompare cmp;
97ea2859 3989 TCGv dst;
00f219bf 3990
c33f80f5 3991 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 3992
c33f80f5
RH		 3993 /* The get_src2 above loaded the normal 13-bit
3994 immediate field, not the 10-bit field we have
3995 in movr. But it did handle the reg case. */
3996 if (IS_IMM) {
67526b20 3997 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 3998 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 3999 }
c33f80f5 4000
97ea2859
RH		 4001 dst = gen_load_gpr(dc, rd);
4002 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4003 cmp.c1, cmp.c2,
97ea2859 4004 cpu_src2, dst);
c33f80f5 4005 free_compare(&cmp);
97ea2859 4006 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4007 break;
4008 }
4009#endif
4010 default:
4011 goto illegal_insn;
4012 }
4013 }
3299908c
BS		 4014 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4015#ifdef TARGET_SPARC64
4016 int opf = GET_FIELD_SP(insn, 5, 13);
4017 rs1 = GET_FIELD(insn, 13, 17);
4018 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4019 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4020 goto jmp_insn;
5b12f1e8 4021 }
3299908c
BS		 4022
4023 switch (opf) {
e9ebed4d 4024 case 0x000: /* VIS I edge8cc */
6c073553 4025 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4026 cpu_src1 = gen_load_gpr(dc, rs1);
4027 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4028 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4029 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4030 break;
e9ebed4d 4031 case 0x001: /* VIS II edge8n */
6c073553 4032 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4033 cpu_src1 = gen_load_gpr(dc, rs1);
4034 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4035 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4036 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4037 break;
e9ebed4d 4038 case 0x002: /* VIS I edge8lcc */
6c073553 4039 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4040 cpu_src1 = gen_load_gpr(dc, rs1);
4041 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4042 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4043 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4044 break;
e9ebed4d 4045 case 0x003: /* VIS II edge8ln */
6c073553 4046 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4047 cpu_src1 = gen_load_gpr(dc, rs1);
4048 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4049 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4050 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4051 break;
e9ebed4d 4052 case 0x004: /* VIS I edge16cc */
6c073553 4053 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4054 cpu_src1 = gen_load_gpr(dc, rs1);
4055 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4056 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4057 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4058 break;
e9ebed4d 4059 case 0x005: /* VIS II edge16n */
6c073553 4060 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4061 cpu_src1 = gen_load_gpr(dc, rs1);
4062 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4063 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4064 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4065 break;
e9ebed4d 4066 case 0x006: /* VIS I edge16lcc */
6c073553 4067 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4068 cpu_src1 = gen_load_gpr(dc, rs1);
4069 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4070 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4071 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4072 break;
e9ebed4d 4073 case 0x007: /* VIS II edge16ln */
6c073553 4074 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4075 cpu_src1 = gen_load_gpr(dc, rs1);
4076 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4077 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4078 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4079 break;
e9ebed4d 4080 case 0x008: /* VIS I edge32cc */
6c073553 4081 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4082 cpu_src1 = gen_load_gpr(dc, rs1);
4083 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4084 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4085 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4086 break;
e9ebed4d 4087 case 0x009: /* VIS II edge32n */
6c073553 4088 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4089 cpu_src1 = gen_load_gpr(dc, rs1);
4090 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4091 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4092 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4093 break;
e9ebed4d 4094 case 0x00a: /* VIS I edge32lcc */
6c073553 4095 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4096 cpu_src1 = gen_load_gpr(dc, rs1);
4097 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4098 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4099 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4100 break;
e9ebed4d 4101 case 0x00b: /* VIS II edge32ln */
6c073553 4102 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4103 cpu_src1 = gen_load_gpr(dc, rs1);
4104 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4105 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4106 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4107 break;
e9ebed4d 4108 case 0x010: /* VIS I array8 */
64a88d5d 4109 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4110 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4111 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4112 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4113 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4114 break;
4115 case 0x012: /* VIS I array16 */
64a88d5d 4116 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4117 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4118 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4119 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4120 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4121 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4122 break;
4123 case 0x014: /* VIS I array32 */
64a88d5d 4124 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4125 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4126 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4127 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4128 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4129 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4130 break;
3299908c 4131 case 0x018: /* VIS I alignaddr */
64a88d5d 4132 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4133 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4134 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4135 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4136 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4137 break;
4138 case 0x01a: /* VIS I alignaddrl */
add545ab 4139 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4140 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4141 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4142 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4143 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4144 break;
4145 case 0x019: /* VIS II bmask */
793a137a 4146 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4147 cpu_src1 = gen_load_gpr(dc, rs1);
4148 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4149 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4150 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4151 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4152 break;
e9ebed4d 4153 case 0x020: /* VIS I fcmple16 */
64a88d5d 4154 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4155 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4156 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4157 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4158 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4159 break;
4160 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4161 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4162 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4163 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4164 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4165 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4166 break;
e9ebed4d 4167 case 0x024: /* VIS I fcmple32 */
64a88d5d 4168 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4169 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4170 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4171 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4172 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4173 break;
4174 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4175 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4176 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4177 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4178 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4179 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4180 break;
4181 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4182 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4183 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4184 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4185 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4186 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4187 break;
4188 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4189 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4190 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4191 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4192 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4193 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4194 break;
4195 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4196 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4197 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4198 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4199 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4200 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4201 break;
4202 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4203 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4204 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4205 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4206 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4207 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4208 break;
4209 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4210 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4211 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4212 break;
4213 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4214 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4215 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4216 break;
4217 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4218 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4219 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4220 break;
4221 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4222 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4223 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4224 break;
4225 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4226 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4227 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4228 break;
4229 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4230 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4231 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4232 break;
4233 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4234 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4235 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4236 break;
4237 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4238 CHECK_FPU_FEATURE(dc, VIS1);
4239 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4240 break;
e9ebed4d 4241 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4242 CHECK_FPU_FEATURE(dc, VIS1);
4243 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4244 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4245 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4246 gen_store_fpr_F(dc, rd, cpu_dst_32);
4247 break;
e9ebed4d 4248 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4249 CHECK_FPU_FEATURE(dc, VIS1);
4250 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4251 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4252 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4253 gen_store_fpr_F(dc, rd, cpu_dst_32);
4254 break;
f888300b
RH		 4255 case 0x03e: /* VIS I pdist */
4256 CHECK_FPU_FEATURE(dc, VIS1);
4257 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4258 break;
3299908c 4259 case 0x048: /* VIS I faligndata */
64a88d5d 4260 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4261 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4262 break;
e9ebed4d 4263 case 0x04b: /* VIS I fpmerge */
64a88d5d 4264 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4265 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4266 break;
4267 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4268 CHECK_FPU_FEATURE(dc, VIS2);
4269 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4270 break;
e9ebed4d 4271 case 0x04d: /* VIS I fexpand */
64a88d5d 4272 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4273 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4274 break;
4275 case 0x050: /* VIS I fpadd16 */
64a88d5d 4276 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4277 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4278 break;
4279 case 0x051: /* VIS I fpadd16s */
64a88d5d 4280 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4281 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4282 break;
4283 case 0x052: /* VIS I fpadd32 */
64a88d5d 4284 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4285 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4286 break;
4287 case 0x053: /* VIS I fpadd32s */
64a88d5d 4288 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4289 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4290 break;
4291 case 0x054: /* VIS I fpsub16 */
64a88d5d 4292 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4293 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4294 break;
4295 case 0x055: /* VIS I fpsub16s */
64a88d5d 4296 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4297 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4298 break;
4299 case 0x056: /* VIS I fpsub32 */
64a88d5d 4300 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4301 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4302 break;
4303 case 0x057: /* VIS I fpsub32s */
64a88d5d 4304 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4305 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4306 break;
3299908c 4307 case 0x060: /* VIS I fzero */
64a88d5d 4308 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4309 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4310 tcg_gen_movi_i64(cpu_dst_64, 0);
4311 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4312 break;
4313 case 0x061: /* VIS I fzeros */
64a88d5d 4314 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4315 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4316 tcg_gen_movi_i32(cpu_dst_32, 0);
4317 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4318 break;
e9ebed4d 4319 case 0x062: /* VIS I fnor */
64a88d5d 4320 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4321 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4322 break;
4323 case 0x063: /* VIS I fnors */
64a88d5d 4324 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4325 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4326 break;
4327 case 0x064: /* VIS I fandnot2 */
64a88d5d 4328 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4329 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4330 break;
4331 case 0x065: /* VIS I fandnot2s */
64a88d5d 4332 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4333 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4334 break;
4335 case 0x066: /* VIS I fnot2 */
64a88d5d 4336 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4337 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4338 break;
4339 case 0x067: /* VIS I fnot2s */
64a88d5d 4340 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4341 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4342 break;
4343 case 0x068: /* VIS I fandnot1 */
64a88d5d 4344 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4345 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4346 break;
4347 case 0x069: /* VIS I fandnot1s */
64a88d5d 4348 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4349 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4350 break;
4351 case 0x06a: /* VIS I fnot1 */
64a88d5d 4352 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4353 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4354 break;
4355 case 0x06b: /* VIS I fnot1s */
64a88d5d 4356 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4357 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4358 break;
4359 case 0x06c: /* VIS I fxor */
64a88d5d 4360 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4361 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4362 break;
4363 case 0x06d: /* VIS I fxors */
64a88d5d 4364 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4365 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4366 break;
4367 case 0x06e: /* VIS I fnand */
64a88d5d 4368 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4369 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4370 break;
4371 case 0x06f: /* VIS I fnands */
64a88d5d 4372 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4373 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4374 break;
4375 case 0x070: /* VIS I fand */
64a88d5d 4376 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4377 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4378 break;
4379 case 0x071: /* VIS I fands */
64a88d5d 4380 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4381 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4382 break;
4383 case 0x072: /* VIS I fxnor */
64a88d5d 4384 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4385 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4386 break;
4387 case 0x073: /* VIS I fxnors */
64a88d5d 4388 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4389 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4390 break;
3299908c 4391 case 0x074: /* VIS I fsrc1 */
64a88d5d 4392 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4393 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4394 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4395 break;
4396 case 0x075: /* VIS I fsrc1s */
64a88d5d 4397 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4398 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4399 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4400 break;
e9ebed4d 4401 case 0x076: /* VIS I fornot2 */
64a88d5d 4402 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4403 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4404 break;
4405 case 0x077: /* VIS I fornot2s */
64a88d5d 4406 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4407 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4408 break;
3299908c 4409 case 0x078: /* VIS I fsrc2 */
64a88d5d 4410 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4411 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4412 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4413 break;
4414 case 0x079: /* VIS I fsrc2s */
64a88d5d 4415 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4416 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4417 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4418 break;
e9ebed4d 4419 case 0x07a: /* VIS I fornot1 */
64a88d5d 4420 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4421 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4422 break;
4423 case 0x07b: /* VIS I fornot1s */
64a88d5d 4424 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4425 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4426 break;
4427 case 0x07c: /* VIS I for */
64a88d5d 4428 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4429 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4430 break;
4431 case 0x07d: /* VIS I fors */
64a88d5d 4432 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4433 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4434 break;
3299908c 4435 case 0x07e: /* VIS I fone */
64a88d5d 4436 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4437 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4438 tcg_gen_movi_i64(cpu_dst_64, -1);
4439 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4440 break;
4441 case 0x07f: /* VIS I fones */
64a88d5d 4442 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4443 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4444 tcg_gen_movi_i32(cpu_dst_32, -1);
4445 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4446 break;
e9ebed4d
BS		 4447 case 0x080: /* VIS I shutdown */
4448 case 0x081: /* VIS II siam */
4449 // XXX
4450 goto illegal_insn;
3299908c
BS		 4451 default:
4452 goto illegal_insn;
4453 }
4454#else
0f8a249a 4455 goto ncp_insn;
3299908c
BS		 4456#endif
4457 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4458#ifdef TARGET_SPARC64
0f8a249a 4459 goto illegal_insn;
fcc72045 4460#else
0f8a249a 4461 goto ncp_insn;
fcc72045 4462#endif
3475187d 4463#ifdef TARGET_SPARC64
0f8a249a 4464 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4465 TCGv_i32 r_const;
2ea815ca 4466
66442b07 4467 save_state(dc);
9d1d4e34 4468 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4469 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4470 if (IS_IMM) { /* immediate */
67526b20 4471 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4472 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4473 } else { /* register */
3475187d 4474 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4475 if (rs2) {
97ea2859 4476 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4477 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4478 } else {
7b04bd5c 4479 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4480 }
3475187d 4481 }
063c3675 4482 gen_helper_restore(cpu_env);
13a6dd00 4483 gen_mov_pc_npc(dc);
2ea815ca 4484 r_const = tcg_const_i32(3);
7b04bd5c 4485 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4486 tcg_temp_free_i32(r_const);
7b04bd5c 4487 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4488 dc->npc = DYNAMIC_PC;
4489 goto jmp_insn;
3475187d 4490#endif
0f8a249a 4491 } else {
9d1d4e34 4492 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4493 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4494 if (IS_IMM) { /* immediate */
67526b20 4495 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4496 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4497 } else { /* register */
e80cfcfc 4498 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4499 if (rs2) {
97ea2859 4500 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4501 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4502 } else {
7b04bd5c 4503 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4504 }
cf495bcf 4505 }
0f8a249a
BS		 4506 switch (xop) {
4507 case 0x38: /* jmpl */
4508 {
97ea2859 4509 TCGv t;
a7812ae4 4510 TCGv_i32 r_const;
2ea815ca 4511
97ea2859
RH		 4512 t = gen_dest_gpr(dc, rd);
4513 tcg_gen_movi_tl(t, dc->pc);
4514 gen_store_gpr(dc, rd, t);
13a6dd00 4515 gen_mov_pc_npc(dc);
2ea815ca 4516 r_const = tcg_const_i32(3);
7b04bd5c 4517 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4518 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4519 gen_address_mask(dc, cpu_tmp0);
4520 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4521 dc->npc = DYNAMIC_PC;
4522 }
4523 goto jmp_insn;
3475187d 4524#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4525 case 0x39: /* rett, V9 return */
4526 {
a7812ae4 4527 TCGv_i32 r_const;
2ea815ca 4528
0f8a249a
BS		 4529 if (!supervisor(dc))
4530 goto priv_insn;
13a6dd00 4531 gen_mov_pc_npc(dc);
2ea815ca 4532 r_const = tcg_const_i32(3);
7b04bd5c 4533 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4534 tcg_temp_free_i32(r_const);
7b04bd5c 4535 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4536 dc->npc = DYNAMIC_PC;
063c3675 4537 gen_helper_rett(cpu_env);
0f8a249a
BS		 4538 }
4539 goto jmp_insn;
4540#endif
4541 case 0x3b: /* flush */
5578ceab 4542 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4543 goto unimp_flush;
dcfd14b3 4544 /* nop */
0f8a249a
BS		 4545 break;
4546 case 0x3c: /* save */
66442b07 4547 save_state(dc);
063c3675 4548 gen_helper_save(cpu_env);
7b04bd5c 4549 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4550 break;
4551 case 0x3d: /* restore */
66442b07 4552 save_state(dc);
063c3675 4553 gen_helper_restore(cpu_env);
7b04bd5c 4554 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4555 break;
3475187d 4556#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4557 case 0x3e: /* V9 done/retry */
4558 {
4559 switch (rd) {
4560 case 0:
4561 if (!supervisor(dc))
4562 goto priv_insn;
4563 dc->npc = DYNAMIC_PC;
4564 dc->pc = DYNAMIC_PC;
063c3675 4565 gen_helper_done(cpu_env);
0f8a249a
BS		 4566 goto jmp_insn;
4567 case 1:
4568 if (!supervisor(dc))
4569 goto priv_insn;
4570 dc->npc = DYNAMIC_PC;
4571 dc->pc = DYNAMIC_PC;
063c3675 4572 gen_helper_retry(cpu_env);
0f8a249a
BS		 4573 goto jmp_insn;
4574 default:
4575 goto illegal_insn;
4576 }
4577 }
4578 break;
4579#endif
4580 default:
4581 goto illegal_insn;
4582 }
cf495bcf 4583 }
0f8a249a
BS		 4584 break;
4585 }
4586 break;
4587 case 3: /* load/store instructions */
4588 {
4589 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4590 /* ??? gen_address_mask prevents us from using a source
4591 register directly. Always generate a temporary. */
4592 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4593
5e6ed439
RH		 4594 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4595 if (xop == 0x3c || xop == 0x3e) {
4596 /* V9 casa/casxa : no offset */
71817e48 4597 } else if (IS_IMM) { /* immediate */
67526b20 4598 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4599 if (simm != 0) {
4600 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4601 }
0f8a249a
BS		 4602 } else { /* register */
4603 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4604 if (rs2 != 0) {
5e6ed439 4605 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4606 }
0f8a249a 4607 }
2f2ecb83
BS		 4608 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4609 (xop > 0x17 && xop <= 0x1d ) ||
4610 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4611 TCGv cpu_val = gen_dest_gpr(dc, rd);
4612
0f8a249a 4613 switch (xop) {
b89e94af 4614 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4615 gen_address_mask(dc, cpu_addr);
6ae20372 4616 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4617 break;
b89e94af 4618 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4619 gen_address_mask(dc, cpu_addr);
6ae20372 4620 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4621 break;
b89e94af 4622 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4623 gen_address_mask(dc, cpu_addr);
6ae20372 4624 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4625 break;
b89e94af 4626 case 0x3: /* ldd, load double word */
0f8a249a 4627 if (rd & 1)
d4218d99 4628 goto illegal_insn;
1a2fb1c0 4629 else {
a7812ae4 4630 TCGv_i32 r_const;
abcc7191 4631 TCGv_i64 t64;
2ea815ca 4632
66442b07 4633 save_state(dc);
2ea815ca 4634 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4635 /* XXX remove alignment check */
4636 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4637 tcg_temp_free_i32(r_const);
2cade6a3 4638 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4639 t64 = tcg_temp_new_i64();
4640 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4641 tcg_gen_trunc_i64_tl(cpu_val, t64);
4642 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4643 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4644 tcg_gen_shri_i64(t64, t64, 32);
4645 tcg_gen_trunc_i64_tl(cpu_val, t64);
4646 tcg_temp_free_i64(t64);
de9e9d9f 4647 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4648 }
0f8a249a 4649 break;
b89e94af 4650 case 0x9: /* ldsb, load signed byte */
2cade6a3 4651 gen_address_mask(dc, cpu_addr);
6ae20372 4652 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4653 break;
b89e94af 4654 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4655 gen_address_mask(dc, cpu_addr);
6ae20372 4656 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4657 break;
4658 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4659 {
4660 TCGv r_const;
4661
2cade6a3 4662 gen_address_mask(dc, cpu_addr);
2ea815ca
BS		 4663 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4664 r_const = tcg_const_tl(0xff);
4665 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4666 tcg_temp_free(r_const);
4667 }
0f8a249a 4668 break;
de9e9d9f
RH		 4669 case 0x0f:
4670 /* swap, swap register with memory. Also atomically */
4671 {
4672 TCGv t0 = get_temp_tl(dc);
4673 CHECK_IU_FEATURE(dc, SWAP);
4674 cpu_src1 = gen_load_gpr(dc, rd);
4675 gen_address_mask(dc, cpu_addr);
4676 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4677 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4678 tcg_gen_mov_tl(cpu_val, t0);
4679 }
0f8a249a 4680 break;
3475187d 4681#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4682 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4683#ifndef TARGET_SPARC64
0f8a249a
BS		 4684 if (IS_IMM)
4685 goto illegal_insn;
4686 if (!supervisor(dc))
4687 goto priv_insn;
6ea4a6c8 4688#endif
66442b07 4689 save_state(dc);
6ae20372 4690 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4691 break;
b89e94af 4692 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4693#ifndef TARGET_SPARC64
0f8a249a
BS		 4694 if (IS_IMM)
4695 goto illegal_insn;
4696 if (!supervisor(dc))
4697 goto priv_insn;
4698#endif
66442b07 4699 save_state(dc);
6ae20372 4700 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4701 break;
b89e94af 4702 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4703#ifndef TARGET_SPARC64
0f8a249a
BS		 4704 if (IS_IMM)
4705 goto illegal_insn;
4706 if (!supervisor(dc))
4707 goto priv_insn;
3475187d 4708#endif
66442b07 4709 save_state(dc);
6ae20372 4710 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4711 break;
b89e94af 4712 case 0x13: /* ldda, load double word alternate */
3475187d 4713#ifndef TARGET_SPARC64
0f8a249a
BS		 4714 if (IS_IMM)
4715 goto illegal_insn;
4716 if (!supervisor(dc))
4717 goto priv_insn;
3475187d 4718#endif
0f8a249a 4719 if (rd & 1)
d4218d99 4720 goto illegal_insn;
66442b07 4721 save_state(dc);
c7785e16 4722 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4723 goto skip_move;
b89e94af 4724 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4725#ifndef TARGET_SPARC64
0f8a249a
BS		 4726 if (IS_IMM)
4727 goto illegal_insn;
4728 if (!supervisor(dc))
4729 goto priv_insn;
4730#endif
66442b07 4731 save_state(dc);
6ae20372 4732 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4733 break;
b89e94af 4734 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4735#ifndef TARGET_SPARC64
0f8a249a
BS		 4736 if (IS_IMM)
4737 goto illegal_insn;
4738 if (!supervisor(dc))
4739 goto priv_insn;
3475187d 4740#endif
66442b07 4741 save_state(dc);
6ae20372 4742 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4743 break;
4744 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4745#ifndef TARGET_SPARC64
0f8a249a
BS		 4746 if (IS_IMM)
4747 goto illegal_insn;
4748 if (!supervisor(dc))
4749 goto priv_insn;
4750#endif
66442b07 4751 save_state(dc);
6ae20372 4752 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4753 break;
b89e94af 4754 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4755 atomically */
64a88d5d 4756 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4757#ifndef TARGET_SPARC64
0f8a249a
BS		 4758 if (IS_IMM)
4759 goto illegal_insn;
4760 if (!supervisor(dc))
4761 goto priv_insn;
6ea4a6c8 4762#endif
66442b07 4763 save_state(dc);
06828032
RH		 4764 cpu_src1 = gen_load_gpr(dc, rd);
4765 gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4766 break;
3475187d
FB		 4767
4768#ifndef TARGET_SPARC64
0f8a249a
BS		 4769 case 0x30: /* ldc */
4770 case 0x31: /* ldcsr */
4771 case 0x33: /* lddc */
4772 goto ncp_insn;
3475187d
FB		 4773#endif
4774#endif
4775#ifdef TARGET_SPARC64
0f8a249a 4776 case 0x08: /* V9 ldsw */
2cade6a3 4777 gen_address_mask(dc, cpu_addr);
6ae20372 4778 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4779 break;
4780 case 0x0b: /* V9 ldx */
2cade6a3 4781 gen_address_mask(dc, cpu_addr);
6ae20372 4782 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4783 break;
4784 case 0x18: /* V9 ldswa */
66442b07 4785 save_state(dc);
6ae20372 4786 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4787 break;
4788 case 0x1b: /* V9 ldxa */
66442b07 4789 save_state(dc);
6ae20372 4790 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4791 break;
4792 case 0x2d: /* V9 prefetch, no effect */
4793 goto skip_move;
4794 case 0x30: /* V9 ldfa */
5b12f1e8 4795 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4796 goto jmp_insn;
4797 }
66442b07 4798 save_state(dc);
6ae20372 4799 gen_ldf_asi(cpu_addr, insn, 4, rd);
638737ad 4800 gen_update_fprs_dirty(rd);
81ad8ba2 4801 goto skip_move;
0f8a249a 4802 case 0x33: /* V9 lddfa */
5b12f1e8 4803 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4804 goto jmp_insn;
4805 }
66442b07 4806 save_state(dc);
6ae20372 4807 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
638737ad 4808 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4809 goto skip_move;
0f8a249a
BS		 4810 case 0x3d: /* V9 prefetcha, no effect */
4811 goto skip_move;
4812 case 0x32: /* V9 ldqfa */
64a88d5d 4813 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4814 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4815 goto jmp_insn;
4816 }
66442b07 4817 save_state(dc);
6ae20372 4818 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
638737ad 4819 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4820 goto skip_move;
0f8a249a
BS		 4821#endif
4822 default:
4823 goto illegal_insn;
4824 }
97ea2859 4825 gen_store_gpr(dc, rd, cpu_val);
db166940 4826#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4827 skip_move: ;
3475187d 4828#endif
0f8a249a 4829 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4830 TCGv t0;
4831
5b12f1e8 4832 if (gen_trap_ifnofpu(dc)) {
a80dde08 4833 goto jmp_insn;
5b12f1e8 4834 }
66442b07 4835 save_state(dc);
0f8a249a 4836 switch (xop) {
b89e94af 4837 case 0x20: /* ldf, load fpreg */
2cade6a3 4838 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4839 t0 = get_temp_tl(dc);
4840 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4841 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4842 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4843 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4844 break;
3a3b925d
BS		 4845 case 0x21: /* ldfsr, V9 ldxfsr */
4846#ifdef TARGET_SPARC64
2cade6a3 4847 gen_address_mask(dc, cpu_addr);
3a3b925d 4848 if (rd == 1) {
abcc7191
RH		 4849 TCGv_i64 t64 = tcg_temp_new_i64();
4850 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4851 gen_helper_ldxfsr(cpu_env, t64);
4852 tcg_temp_free_i64(t64);
f8641947 4853 break;
fe987e23 4854 }
f8641947 4855#endif
de9e9d9f
RH		 4856 cpu_dst_32 = get_temp_i32(dc);
4857 t0 = get_temp_tl(dc);
4858 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4859 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4860 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4861 break;
b89e94af 4862 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4863 {
a7812ae4 4864 TCGv_i32 r_const;
2ea815ca
BS		 4865
4866 CHECK_FPU_FEATURE(dc, FLOAT128);
4867 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4868 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4869 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4870 tcg_temp_free_i32(r_const);
2ea815ca 4871 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4872 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4873 }
1f587329 4874 break;
b89e94af 4875 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4876 gen_address_mask(dc, cpu_addr);
3886b8a3 4877 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4878 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4879 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4880 break;
4881 default:
4882 goto illegal_insn;
4883 }
dc1a6971 4884 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4885 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4886 TCGv cpu_val = gen_load_gpr(dc, rd);
4887
0f8a249a 4888 switch (xop) {
b89e94af 4889 case 0x4: /* st, store word */
2cade6a3 4890 gen_address_mask(dc, cpu_addr);
6ae20372 4891 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4892 break;
b89e94af 4893 case 0x5: /* stb, store byte */
2cade6a3 4894 gen_address_mask(dc, cpu_addr);
6ae20372 4895 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4896 break;
b89e94af 4897 case 0x6: /* sth, store halfword */
2cade6a3 4898 gen_address_mask(dc, cpu_addr);
6ae20372 4899 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4900 break;
b89e94af 4901 case 0x7: /* std, store double word */
0f8a249a 4902 if (rd & 1)
d4218d99 4903 goto illegal_insn;
1a2fb1c0 4904 else {
a7812ae4 4905 TCGv_i32 r_const;
abcc7191 4906 TCGv_i64 t64;
81634eea 4907 TCGv lo;
1a2fb1c0 4908
66442b07 4909 save_state(dc);
2cade6a3 4910 gen_address_mask(dc, cpu_addr);
2ea815ca 4911 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4912 /* XXX remove alignment check */
4913 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4914 tcg_temp_free_i32(r_const);
81634eea 4915 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 4916
4917 t64 = tcg_temp_new_i64();
4918 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4919 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4920 tcg_temp_free_i64(t64);
7fa76c0b 4921 }
0f8a249a 4922 break;
3475187d 4923#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4924 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4925#ifndef TARGET_SPARC64
0f8a249a
BS		 4926 if (IS_IMM)
4927 goto illegal_insn;
4928 if (!supervisor(dc))
4929 goto priv_insn;
6ea4a6c8 4930#endif
66442b07 4931 save_state(dc);
6ae20372 4932 gen_st_asi(cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4933 dc->npc = DYNAMIC_PC;
d39c0b99 4934 break;
b89e94af 4935 case 0x15: /* stba, store byte alternate */
3475187d 4936#ifndef TARGET_SPARC64
0f8a249a
BS		 4937 if (IS_IMM)
4938 goto illegal_insn;
4939 if (!supervisor(dc))
4940 goto priv_insn;
3475187d 4941#endif
66442b07 4942 save_state(dc);
6ae20372 4943 gen_st_asi(cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4944 dc->npc = DYNAMIC_PC;
d39c0b99 4945 break;
b89e94af 4946 case 0x16: /* stha, store halfword alternate */
3475187d 4947#ifndef TARGET_SPARC64
0f8a249a
BS		 4948 if (IS_IMM)
4949 goto illegal_insn;
4950 if (!supervisor(dc))
4951 goto priv_insn;
6ea4a6c8 4952#endif
66442b07 4953 save_state(dc);
6ae20372 4954 gen_st_asi(cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4955 dc->npc = DYNAMIC_PC;
d39c0b99 4956 break;
b89e94af 4957 case 0x17: /* stda, store double word alternate */
3475187d 4958#ifndef TARGET_SPARC64
0f8a249a
BS		 4959 if (IS_IMM)
4960 goto illegal_insn;
4961 if (!supervisor(dc))
4962 goto priv_insn;
3475187d 4963#endif
0f8a249a 4964 if (rd & 1)
d4218d99 4965 goto illegal_insn;
1a2fb1c0 4966 else {
66442b07 4967 save_state(dc);
c7785e16 4968 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4969 }
d39c0b99 4970 break;
e80cfcfc 4971#endif
3475187d 4972#ifdef TARGET_SPARC64
0f8a249a 4973 case 0x0e: /* V9 stx */
2cade6a3 4974 gen_address_mask(dc, cpu_addr);
6ae20372 4975 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4976 break;
4977 case 0x1e: /* V9 stxa */
66442b07 4978 save_state(dc);
6ae20372 4979 gen_st_asi(cpu_val, cpu_addr, insn, 8);
9fd1ae3a 4980 dc->npc = DYNAMIC_PC;
0f8a249a 4981 break;
3475187d 4982#endif
0f8a249a
BS		 4983 default:
4984 goto illegal_insn;
4985 }
4986 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 4987 if (gen_trap_ifnofpu(dc)) {
a80dde08 4988 goto jmp_insn;
5b12f1e8 4989 }
66442b07 4990 save_state(dc);
0f8a249a 4991 switch (xop) {
b89e94af 4992 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 4993 {
4994 TCGv t = get_temp_tl(dc);
4995 gen_address_mask(dc, cpu_addr);
4996 cpu_src1_32 = gen_load_fpr_F(dc, rd);
4997 tcg_gen_ext_i32_tl(t, cpu_src1_32);
4998 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
4999 }
0f8a249a
BS		 5000 break;
5001 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5002 {
5003 TCGv t = get_temp_tl(dc);
5004
5005 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5006#ifdef TARGET_SPARC64
f8641947
RH		 5007 gen_address_mask(dc, cpu_addr);
5008 if (rd == 1) {
5009 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5010 break;
5011 }
3a3b925d 5012#endif
f8641947
RH		 5013 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5014 }
0f8a249a 5015 break;
1f587329
BS		 5016 case 0x26:
5017#ifdef TARGET_SPARC64
1f587329 5018 /* V9 stqf, store quad fpreg */
2ea815ca 5019 {
a7812ae4 5020 TCGv_i32 r_const;
2ea815ca
BS		 5021
5022 CHECK_FPU_FEATURE(dc, FLOAT128);
5023 gen_op_load_fpr_QT0(QFPREG(rd));
5024 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5025 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5026 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5027 tcg_temp_free_i32(r_const);
2ea815ca 5028 }
1f587329 5029 break;
1f587329
BS		 5030#else /* !TARGET_SPARC64 */
5031 /* stdfq, store floating point queue */
5032#if defined(CONFIG_USER_ONLY)
5033 goto illegal_insn;
5034#else
0f8a249a
BS		 5035 if (!supervisor(dc))
5036 goto priv_insn;
5b12f1e8 5037 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5038 goto jmp_insn;
5b12f1e8 5039 }
0f8a249a 5040 goto nfq_insn;
1f587329 5041#endif
0f8a249a 5042#endif
b89e94af 5043 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5044 gen_address_mask(dc, cpu_addr);
5045 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5046 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5047 break;
5048 default:
5049 goto illegal_insn;
5050 }
5051 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5052 save_state(dc);
0f8a249a 5053 switch (xop) {
a4d17f19 5054#ifdef TARGET_SPARC64
0f8a249a 5055 case 0x34: /* V9 stfa */
5b12f1e8 5056 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5057 goto jmp_insn;
5058 }
6ae20372 5059 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 5060 break;
1f587329 5061 case 0x36: /* V9 stqfa */
2ea815ca 5062 {
a7812ae4 5063 TCGv_i32 r_const;
2ea815ca
BS		 5064
5065 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5066 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5067 goto jmp_insn;
5068 }
2ea815ca 5069 r_const = tcg_const_i32(7);
fe8d8f0f 5070 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5071 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5072 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5073 }
1f587329 5074 break;
0f8a249a 5075 case 0x37: /* V9 stdfa */
5b12f1e8 5076 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5077 goto jmp_insn;
5078 }
6ae20372 5079 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5080 break;
0f8a249a 5081 case 0x3e: /* V9 casxa */
a4273524
RH		 5082 rs2 = GET_FIELD(insn, 27, 31);
5083 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5084 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5085 break;
a4d17f19 5086#else
0f8a249a
BS		 5087 case 0x34: /* stc */
5088 case 0x35: /* stcsr */
5089 case 0x36: /* stdcq */
5090 case 0x37: /* stdc */
5091 goto ncp_insn;
16c358e9
SH		 5092#endif
5093#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5094 case 0x3c: /* V9 or LEON3 casa */
5095#ifndef TARGET_SPARC64
5096 CHECK_IU_FEATURE(dc, CASA);
5097 if (IS_IMM) {
5098 goto illegal_insn;
5099 }
5100 if (!supervisor(dc)) {
5101 goto priv_insn;
5102 }
5103#endif
5104 rs2 = GET_FIELD(insn, 27, 31);
5105 cpu_src2 = gen_load_gpr(dc, rs2);
5106 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5107 break;
0f8a249a
BS		 5108#endif
5109 default:
5110 goto illegal_insn;
5111 }
a4273524 5112 } else {
0f8a249a 5113 goto illegal_insn;
a4273524 5114 }
0f8a249a
BS		 5115 }
5116 break;
cf495bcf
FB		 5117 }
5118 /* default case for non jump instructions */
72cbca10 5119 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5120 dc->pc = DYNAMIC_PC;
5121 gen_op_next_insn();
72cbca10
FB		 5122 } else if (dc->npc == JUMP_PC) {
5123 /* we can do a static jump */
6ae20372 5124 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5125 dc->is_br = 1;
5126 } else {
0f8a249a
BS		 5127 dc->pc = dc->npc;
5128 dc->npc = dc->npc + 4;
cf495bcf 5129 }
e80cfcfc 5130 jmp_insn:
42a8aa83 5131 goto egress;
cf495bcf 5132 illegal_insn:
2ea815ca 5133 {
a7812ae4 5134 TCGv_i32 r_const;
2ea815ca 5135
66442b07 5136 save_state(dc);
2ea815ca 5137 r_const = tcg_const_i32(TT_ILL_INSN);
bc265319 5138 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5139 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5140 dc->is_br = 1;
5141 }
42a8aa83 5142 goto egress;
64a88d5d 5143 unimp_flush:
2ea815ca 5144 {
a7812ae4 5145 TCGv_i32 r_const;
2ea815ca 5146
66442b07 5147 save_state(dc);
2ea815ca 5148 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
bc265319 5149 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5150 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5151 dc->is_br = 1;
5152 }
42a8aa83 5153 goto egress;
e80cfcfc 5154#if !defined(CONFIG_USER_ONLY)
e8af50a3 5155 priv_insn:
2ea815ca 5156 {
a7812ae4 5157 TCGv_i32 r_const;
2ea815ca 5158
66442b07 5159 save_state(dc);
2ea815ca 5160 r_const = tcg_const_i32(TT_PRIV_INSN);
bc265319 5161 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5162 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5163 dc->is_br = 1;
5164 }
42a8aa83 5165 goto egress;
64a88d5d 5166#endif
e80cfcfc 5167 nfpu_insn:
66442b07 5168 save_state(dc);
e80cfcfc
FB		 5169 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5170 dc->is_br = 1;
42a8aa83 5171 goto egress;
64a88d5d 5172#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5173 nfq_insn:
66442b07 5174 save_state(dc);
9143e598
BS		 5175 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5176 dc->is_br = 1;
42a8aa83 5177 goto egress;
9143e598 5178#endif
fcc72045
BS		 5179#ifndef TARGET_SPARC64
5180 ncp_insn:
2ea815ca
BS		 5181 {
5182 TCGv r_const;
5183
66442b07 5184 save_state(dc);
2ea815ca 5185 r_const = tcg_const_i32(TT_NCP_INSN);
bc265319 5186 gen_helper_raise_exception(cpu_env, r_const);
2ea815ca
BS		 5187 tcg_temp_free(r_const);
5188 dc->is_br = 1;
5189 }
42a8aa83 5190 goto egress;
fcc72045 5191#endif
42a8aa83 5192 egress:
30038fd8
RH		 5193 if (dc->n_t32 != 0) {
5194 int i;
5195 for (i = dc->n_t32 - 1; i >= 0; --i) {
5196 tcg_temp_free_i32(dc->t32[i]);
5197 }
5198 dc->n_t32 = 0;
5199 }
88023616
RH		 5200 if (dc->n_ttl != 0) {
5201 int i;
5202 for (i = dc->n_ttl - 1; i >= 0; --i) {
5203 tcg_temp_free(dc->ttl[i]);
5204 }
5205 dc->n_ttl = 0;
5206 }
7a3f1944
FB		 5207}
5208
4e5e1215 5209void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5210{
4e5e1215 5211 SPARCCPU *cpu = sparc_env_get_cpu(env);
ed2803da 5212 CPUState *cs = CPU(cpu);
72cbca10 5213 target_ulong pc_start, last_pc;
cf495bcf 5214 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5215 int num_insns;
5216 int max_insns;
0184e266 5217 unsigned int insn;
cf495bcf
FB		 5218
5219 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5220 dc->tb = tb;
72cbca10 5221 pc_start = tb->pc;
cf495bcf 5222 dc->pc = pc_start;
e80cfcfc 5223 last_pc = dc->pc;
72cbca10 5224 dc->npc = (target_ulong) tb->cs_base;
8393617c 5225 dc->cc_op = CC_OP_DYNAMIC;
97ed5ccd 5226 dc->mem_idx = cpu_mmu_index(env, false);
5578ceab 5227 dc->def = env->def;
f838e2c5
BS		 5228 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5229 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5230 dc->singlestep = (cs->singlestep_enabled || singlestep);
cf495bcf 5231
2e70f6ef
PB		 5232 num_insns = 0;
5233 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5234 if (max_insns == 0) {
2e70f6ef 5235 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5236 }
5237 if (max_insns > TCG_MAX_INSNS) {
5238 max_insns = TCG_MAX_INSNS;
5239 }
5240
cd42d5b2 5241 gen_tb_start(tb);
cf495bcf 5242 do {
a3d5ad76
RH		 5243 if (dc->npc & JUMP_PC) {
5244 assert(dc->jump_pc[1] == dc->pc + 4);
5245 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5246 } else {
5247 tcg_gen_insn_start(dc->pc, dc->npc);
5248 }
959082fc 5249 num_insns++;
667b8e29 5250
b933066a
RH		 5251 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5252 if (dc->pc != pc_start) {
5253 save_state(dc);
5254 }
5255 gen_helper_debug(cpu_env);
5256 tcg_gen_exit_tb(0);
5257 dc->is_br = 1;
5258 goto exit_gen_loop;
5259 }
5260
959082fc 5261 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5262 gen_io_start();
667b8e29
RH		 5263 }
5264
0f8a249a 5265 last_pc = dc->pc;
0184e266 5266 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5267
0184e266 5268 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5269
5270 if (dc->is_br)
5271 break;
5272 /* if the next PC is different, we abort now */
5273 if (dc->pc != (last_pc + 4))
5274 break;
d39c0b99
FB		 5275 /* if we reach a page boundary, we stop generation so that the
5276 PC of a TT_TFAULT exception is always in the right page */
5277 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5278 break;
e80cfcfc
FB		 5279 /* if single step mode, we generate only one instruction and
5280 generate an exception */
060718c1 5281 if (dc->singlestep) {
e80cfcfc
FB		 5282 break;
5283 }
fe700adb 5284 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5285 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5286 num_insns < max_insns);
e80cfcfc
FB		 5287
5288 exit_gen_loop:
b09b2fd3 5289 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5290 gen_io_end();
b09b2fd3 5291 }
72cbca10 5292 if (!dc->is_br) {
5fafdf24 5293 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5294 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5295 /* static PC and NPC: we can use direct chaining */
2f5680ee 5296 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5297 } else {
b09b2fd3 5298 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5299 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5300 }
934da7ee 5301 save_npc(dc);
57fec1fe 5302 tcg_gen_exit_tb(0);
72cbca10
FB		 5303 }
5304 }
806f352d 5305 gen_tb_end(tb, num_insns);
0a7df5da 5306
4e5e1215
RH		 5307 tb->size = last_pc + 4 - pc_start;
5308 tb->icount = num_insns;
5309
7a3f1944 5310#ifdef DEBUG_DISAS
8fec2b8c 5311 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 5312 qemu_log("--------------\n");
5313 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5314 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5315 qemu_log("\n");
cf495bcf 5316 }
7a3f1944 5317#endif
7a3f1944
FB		 5318}
5319
c48fcb47 5320void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5321{
f5069b26 5322 unsigned int i;
c48fcb47 5323 static int inited;
f5069b26
BS		 5324 static const char * const gregnames[8] = {
5325 NULL, // g0 not used
5326 "g1",
5327 "g2",
5328 "g3",
5329 "g4",
5330 "g5",
5331 "g6",
5332 "g7",
5333 };
30038fd8
RH		 5334 static const char * const fregnames[32] = {
5335 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5336 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5337 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5338 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5339 };
aaed909a 5340
1a2fb1c0
BS		 5341 /* init various static tables */
5342 if (!inited) {
5343 inited = 1;
5344
a7812ae4
PB		 5345 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5346 cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
c5f9864e 5347 offsetof(CPUSPARCState, regwptr),
a7812ae4 5348 "regwptr");
1a2fb1c0 5349#ifdef TARGET_SPARC64
c5f9864e 5350 cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc),
a7812ae4 5351 "xcc");
c5f9864e 5352 cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi),
a7812ae4 5353 "asi");
c5f9864e 5354 cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs),
a7812ae4 5355 "fprs");
c5f9864e 5356 cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr),
255e1fcb 5357 "gsr");
a7812ae4 5358 cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5359 offsetof(CPUSPARCState, tick_cmpr),
255e1fcb 5360 "tick_cmpr");
a7812ae4 5361 cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5362 offsetof(CPUSPARCState, stick_cmpr),
255e1fcb 5363 "stick_cmpr");
a7812ae4 5364 cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5365 offsetof(CPUSPARCState, hstick_cmpr),
255e1fcb 5366 "hstick_cmpr");
c5f9864e 5367 cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp),
255e1fcb 5368 "hintp");
c5f9864e 5369 cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba),
a7812ae4 5370 "htba");
c5f9864e 5371 cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver),
a7812ae4
PB		 5372 "hver");
5373 cpu_ssr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5374 offsetof(CPUSPARCState, ssr), "ssr");
a7812ae4 5375 cpu_ver = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5376 offsetof(CPUSPARCState, version), "ver");
a7812ae4 5377 cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
c5f9864e 5378 offsetof(CPUSPARCState, softint),
a7812ae4 5379 "softint");
255e1fcb 5380#else
c5f9864e 5381 cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim),
255e1fcb 5382 "wim");
1a2fb1c0 5383#endif
c5f9864e 5384 cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond),
77f193da 5385 "cond");
c5f9864e 5386 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src),
dc99a3f2 5387 "cc_src");
a7812ae4 5388 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5389 offsetof(CPUSPARCState, cc_src2),
d9bdab86 5390 "cc_src2");
c5f9864e 5391 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst),
dc99a3f2 5392 "cc_dst");
c5f9864e 5393 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op),
8393617c 5394 "cc_op");
c5f9864e 5395 cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr),
a7812ae4 5396 "psr");
c5f9864e 5397 cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr),
87e92502 5398 "fsr");
c5f9864e 5399 cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc),
48d5c82b 5400 "pc");
c5f9864e 5401 cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc),
a7812ae4 5402 "npc");
c5f9864e 5403 cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
255e1fcb 5404#ifndef CONFIG_USER_ONLY
c5f9864e 5405 cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr),
255e1fcb
BS		 5406 "tbr");
5407#endif
30038fd8 5408 for (i = 1; i < 8; i++) {
a7812ae4 5409 cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5410 offsetof(CPUSPARCState, gregs[i]),
f5069b26 5411 gregnames[i]);
30038fd8
RH		 5412 }
5413 for (i = 0; i < TARGET_DPREGS; i++) {
5414 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
c5f9864e 5415 offsetof(CPUSPARCState, fpr[i]),
45c7b743 5416 fregnames[i]);
30038fd8 5417 }
1a2fb1c0 5418 }
658138bc 5419}
d2856f1a 5420
bad729e2
RH		 5421void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5422 target_ulong *data)
d2856f1a 5423{
bad729e2
RH		 5424 target_ulong pc = data[0];
5425 target_ulong npc = data[1];
5426
5427 env->pc = pc;
6c42444f 5428 if (npc == DYNAMIC_PC) {
d2856f1a 5429 /* dynamic NPC: already stored */
6c42444f 5430 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5431 /* jump PC: use 'cond' and the jump targets of the translation */
5432 if (env->cond) {
6c42444f 5433 env->npc = npc & ~3;
d7da2a10 5434 } else {
6c42444f 5435 env->npc = pc + 4;
d7da2a10 5436 }
d2856f1a
AJ		 5437 } else {
5438 env->npc = npc;
5439 }
5440}
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