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target-sparc: Remove gen_opc_jump_pc
[mirror_qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
7a3f1944
FB		 21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
76cad711 28#include "disas/disas.h"
2ef6175a 29#include "exec/helper-proto.h"
57fec1fe 30#include "tcg-op.h"
f08b6170 31#include "exec/cpu_ldst.h"
7a3f1944 32
2ef6175a 33#include "exec/helper-gen.h"
a7812ae4 34
a7e30d84
LV		 35#include "trace-tcg.h"
36
37
7a3f1944
FB		 38#define DEBUG_DISAS
39
72cbca10
FB		 40#define DYNAMIC_PC 1 /* dynamic pc value */
41#define JUMP_PC 2 /* dynamic pc value which takes only two values
42 according to jump_pc[T2] */
43
1a2fb1c0 44/* global register indexes */
a7812ae4 45static TCGv_ptr cpu_env, cpu_regwptr;
25517f99
PB		 46static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
47static TCGv_i32 cpu_cc_op;
a7812ae4
PB		 48static TCGv_i32 cpu_psr;
49static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
255e1fcb
BS		 50static TCGv cpu_y;
51#ifndef CONFIG_USER_ONLY
52static TCGv cpu_tbr;
53#endif
5793f2a4 54static TCGv cpu_cond;
dc99a3f2 55#ifdef TARGET_SPARC64
a7812ae4
PB		 56static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
57static TCGv cpu_gsr;
255e1fcb 58static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4
PB		 59static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
60static TCGv_i32 cpu_softint;
255e1fcb
BS		 61#else
62static TCGv cpu_wim;
dc99a3f2 63#endif
714547bb 64/* Floating point registers */
30038fd8 65static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 66
1a7ff922 67static target_ulong gen_opc_npc[OPC_BUF_SIZE];
1a7ff922 68
022c62cb 69#include "exec/gen-icount.h"
2e70f6ef 70
7a3f1944 71typedef struct DisasContext {
0f8a249a
BS		 72 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
73 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 74 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 75 int is_br;
e8af50a3 76 int mem_idx;
a80dde08 77 int fpu_enabled;
2cade6a3 78 int address_mask_32bit;
060718c1 79 int singlestep;
8393617c 80 uint32_t cc_op; /* current CC operation */
cf495bcf 81 struct TranslationBlock *tb;
5578ceab 82 sparc_def_t *def;
30038fd8 83 TCGv_i32 t32[3];
88023616 84 TCGv ttl[5];
30038fd8 85 int n_t32;
88023616 86 int n_ttl;
7a3f1944
FB		 87} DisasContext;
88
416fcaea
RH		 89typedef struct {
90 TCGCond cond;
91 bool is_bool;
92 bool g1, g2;
93 TCGv c1, c2;
94} DisasCompare;
95
3475187d 96// This function uses non-native bit order
dc1a6971
BS		 97#define GET_FIELD(X, FROM, TO) \
98 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 99
3475187d 100// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 101#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 102 GET_FIELD(X, 31 - (TO), 31 - (FROM))
103
104#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 105#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 106
107#ifdef TARGET_SPARC64
0387d928 108#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 109#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 110#else
c185970a 111#define DFPREG(r) (r & 0x1e)
1f587329 112#define QFPREG(r) (r & 0x1c)
3475187d
FB		 113#endif
114
b158a785
BS		 115#define UA2005_HTRAP_MASK 0xff
116#define V8_TRAP_MASK 0x7f
117
3475187d
FB		 118static int sign_extend(int x, int len)
119{
120 len = 32 - len;
121 return (x << len) >> len;
122}
123
7a3f1944
FB		 124#define IS_IMM (insn & (1<<13))
125
2ae23e17
RH		 126static inline TCGv_i32 get_temp_i32(DisasContext *dc)
127{
128 TCGv_i32 t;
129 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
130 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
131 return t;
132}
133
134static inline TCGv get_temp_tl(DisasContext *dc)
135{
136 TCGv t;
137 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
138 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
139 return t;
140}
141
141ae5c1
RH		 142static inline void gen_update_fprs_dirty(int rd)
143{
144#if defined(TARGET_SPARC64)
145 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
146#endif
147}
148
ff07ec83 149/* floating point registers moves */
208ae657
RH		 150static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
151{
30038fd8
RH		 152#if TCG_TARGET_REG_BITS == 32
153 if (src & 1) {
154 return TCGV_LOW(cpu_fpr[src / 2]);
155 } else {
156 return TCGV_HIGH(cpu_fpr[src / 2]);
157 }
158#else
159 if (src & 1) {
160 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
161 } else {
2ae23e17 162 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 163 TCGv_i64 t = tcg_temp_new_i64();
164
165 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 166 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 167 tcg_temp_free_i64(t);
168
30038fd8
RH		 169 return ret;
170 }
171#endif
208ae657
RH		 172}
173
174static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
175{
30038fd8
RH		 176#if TCG_TARGET_REG_BITS == 32
177 if (dst & 1) {
178 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
179 } else {
180 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
181 }
182#else
183 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
184 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
185 (dst & 1 ? 0 : 32), 32);
186#endif
141ae5c1 187 gen_update_fprs_dirty(dst);
208ae657
RH		 188}
189
ba5f5179 190static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 191{
ba5f5179 192 return get_temp_i32(dc);
208ae657
RH		 193}
194
96eda024
RH		 195static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
196{
96eda024 197 src = DFPREG(src);
30038fd8 198 return cpu_fpr[src / 2];
96eda024
RH		 199}
200
201static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
202{
203 dst = DFPREG(dst);
30038fd8 204 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 205 gen_update_fprs_dirty(dst);
206}
207
3886b8a3 208static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 209{
3886b8a3 210 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 211}
212
ff07ec83
BS		 213static void gen_op_load_fpr_QT0(unsigned int src)
214{
30038fd8
RH		 215 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
216 offsetof(CPU_QuadU, ll.upper));
217 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
218 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 219}
220
221static void gen_op_load_fpr_QT1(unsigned int src)
222{
30038fd8
RH		 223 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
224 offsetof(CPU_QuadU, ll.upper));
225 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
226 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 227}
228
229static void gen_op_store_QT0_fpr(unsigned int dst)
230{
30038fd8
RH		 231 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
232 offsetof(CPU_QuadU, ll.upper));
233 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
234 offsetof(CPU_QuadU, ll.lower));
ff07ec83 235}
1f587329 236
ac11f776 237#ifdef TARGET_SPARC64
30038fd8 238static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 239{
240 rd = QFPREG(rd);
241 rs = QFPREG(rs);
242
30038fd8
RH		 243 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
244 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 245 gen_update_fprs_dirty(rd);
246}
247#endif
248
81ad8ba2
BS		 249/* moves */
250#ifdef CONFIG_USER_ONLY
3475187d 251#define supervisor(dc) 0
81ad8ba2 252#ifdef TARGET_SPARC64
e9ebed4d 253#define hypervisor(dc) 0
81ad8ba2 254#endif
3475187d 255#else
2aae2b8e 256#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 257#ifdef TARGET_SPARC64
2aae2b8e 258#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 259#else
3475187d 260#endif
81ad8ba2
BS		 261#endif
262
2cade6a3
BS		 263#ifdef TARGET_SPARC64
264#ifndef TARGET_ABI32
265#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 266#else
2cade6a3
BS		 267#define AM_CHECK(dc) (1)
268#endif
1a2fb1c0 269#endif
3391c818 270
2cade6a3
BS		 271static inline void gen_address_mask(DisasContext *dc, TCGv addr)
272{
273#ifdef TARGET_SPARC64
274 if (AM_CHECK(dc))
275 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
276#endif
277}
278
88023616
RH		 279static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
280{
281 if (reg == 0 || reg >= 8) {
282 TCGv t = get_temp_tl(dc);
283 if (reg == 0) {
284 tcg_gen_movi_tl(t, 0);
285 } else {
286 tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
287 }
288 return t;
289 } else {
290 return cpu_gregs[reg];
291 }
292}
293
294static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
295{
296 if (reg > 0) {
297 if (reg < 8) {
298 tcg_gen_mov_tl(cpu_gregs[reg], v);
299 } else {
300 tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
301 }
302 }
303}
304
305static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
306{
307 if (reg == 0 || reg >= 8) {
308 return get_temp_tl(dc);
309 } else {
310 return cpu_gregs[reg];
311 }
312}
313
5fafdf24 314static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 315 target_ulong pc, target_ulong npc)
316{
317 TranslationBlock *tb;
318
319 tb = s->tb;
320 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
060718c1
RH		 321 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
322 !s->singlestep) {
6e256c93 323 /* jump to same page: we can use a direct jump */
57fec1fe 324 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 325 tcg_gen_movi_tl(cpu_pc, pc);
326 tcg_gen_movi_tl(cpu_npc, npc);
8cfd0495 327 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
6e256c93
FB		 328 } else {
329 /* jump to another page: currently not optimized */
2f5680ee
BS		 330 tcg_gen_movi_tl(cpu_pc, pc);
331 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 332 tcg_gen_exit_tb(0);
6e256c93
FB		 333 }
334}
335
19f329ad 336// XXX suboptimal
a7812ae4 337static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 338{
8911f501 339 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 340 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 341 tcg_gen_andi_tl(reg, reg, 0x1);
342}
343
a7812ae4 344static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 345{
8911f501 346 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 347 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 348 tcg_gen_andi_tl(reg, reg, 0x1);
349}
350
a7812ae4 351static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 352{
8911f501 353 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 354 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 355 tcg_gen_andi_tl(reg, reg, 0x1);
356}
357
a7812ae4 358static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 359{
8911f501 360 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 361 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 362 tcg_gen_andi_tl(reg, reg, 0x1);
363}
364
4af984a7 365static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 366{
4af984a7 367 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 368 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 369 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 370 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 371}
372
70c48285 373static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 374{
70c48285
RH		 375 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
376
377 /* Carry is computed from a previous add: (dst < src) */
378#if TARGET_LONG_BITS == 64
379 cc_src1_32 = tcg_temp_new_i32();
380 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 381 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
382 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 383#else
384 cc_src1_32 = cpu_cc_dst;
385 cc_src2_32 = cpu_cc_src;
386#endif
387
388 carry_32 = tcg_temp_new_i32();
389 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
390
391#if TARGET_LONG_BITS == 64
392 tcg_temp_free_i32(cc_src1_32);
393 tcg_temp_free_i32(cc_src2_32);
394#endif
395
396 return carry_32;
41d72852
BS		 397}
398
70c48285 399static TCGv_i32 gen_sub32_carry32(void)
41d72852 400{
70c48285
RH		 401 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
402
403 /* Carry is computed from a previous borrow: (src1 < src2) */
404#if TARGET_LONG_BITS == 64
405 cc_src1_32 = tcg_temp_new_i32();
406 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 407 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
408 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 409#else
410 cc_src1_32 = cpu_cc_src;
411 cc_src2_32 = cpu_cc_src2;
412#endif
413
414 carry_32 = tcg_temp_new_i32();
415 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
416
417#if TARGET_LONG_BITS == 64
418 tcg_temp_free_i32(cc_src1_32);
419 tcg_temp_free_i32(cc_src2_32);
420#endif
421
422 return carry_32;
423}
424
425static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
426 TCGv src2, int update_cc)
427{
428 TCGv_i32 carry_32;
429 TCGv carry;
430
431 switch (dc->cc_op) {
432 case CC_OP_DIV:
433 case CC_OP_LOGIC:
434 /* Carry is known to be zero. Fall back to plain ADD. */
435 if (update_cc) {
436 gen_op_add_cc(dst, src1, src2);
437 } else {
438 tcg_gen_add_tl(dst, src1, src2);
439 }
440 return;
441
442 case CC_OP_ADD:
443 case CC_OP_TADD:
444 case CC_OP_TADDTV:
15fe216f
RH		 445 if (TARGET_LONG_BITS == 32) {
446 /* We can re-use the host's hardware carry generation by using
447 an ADD2 opcode. We discard the low part of the output.
448 Ideally we'd combine this operation with the add that
449 generated the carry in the first place. */
450 carry = tcg_temp_new();
451 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
452 tcg_temp_free(carry);
70c48285
RH		 453 goto add_done;
454 }
70c48285
RH		 455 carry_32 = gen_add32_carry32();
456 break;
457
458 case CC_OP_SUB:
459 case CC_OP_TSUB:
460 case CC_OP_TSUBTV:
461 carry_32 = gen_sub32_carry32();
462 break;
463
464 default:
465 /* We need external help to produce the carry. */
466 carry_32 = tcg_temp_new_i32();
2ffd9176 467 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 468 break;
469 }
470
471#if TARGET_LONG_BITS == 64
472 carry = tcg_temp_new();
473 tcg_gen_extu_i32_i64(carry, carry_32);
474#else
475 carry = carry_32;
476#endif
477
478 tcg_gen_add_tl(dst, src1, src2);
479 tcg_gen_add_tl(dst, dst, carry);
480
481 tcg_temp_free_i32(carry_32);
482#if TARGET_LONG_BITS == 64
483 tcg_temp_free(carry);
484#endif
485
70c48285 486 add_done:
70c48285
RH		 487 if (update_cc) {
488 tcg_gen_mov_tl(cpu_cc_src, src1);
489 tcg_gen_mov_tl(cpu_cc_src2, src2);
490 tcg_gen_mov_tl(cpu_cc_dst, dst);
491 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
492 dc->cc_op = CC_OP_ADDX;
493 }
dc99a3f2
BS		 494}
495
41d72852 496static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 497{
4af984a7 498 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 499 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 500 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 501 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 502}
503
70c48285
RH		 504static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
505 TCGv src2, int update_cc)
41d72852 506{
70c48285
RH		 507 TCGv_i32 carry_32;
508 TCGv carry;
41d72852 509
70c48285
RH		 510 switch (dc->cc_op) {
511 case CC_OP_DIV:
512 case CC_OP_LOGIC:
513 /* Carry is known to be zero. Fall back to plain SUB. */
514 if (update_cc) {
515 gen_op_sub_cc(dst, src1, src2);
516 } else {
517 tcg_gen_sub_tl(dst, src1, src2);
518 }
519 return;
520
521 case CC_OP_ADD:
522 case CC_OP_TADD:
523 case CC_OP_TADDTV:
524 carry_32 = gen_add32_carry32();
525 break;
526
527 case CC_OP_SUB:
528 case CC_OP_TSUB:
529 case CC_OP_TSUBTV:
15fe216f
RH		 530 if (TARGET_LONG_BITS == 32) {
531 /* We can re-use the host's hardware carry generation by using
532 a SUB2 opcode. We discard the low part of the output.
533 Ideally we'd combine this operation with the add that
534 generated the carry in the first place. */
535 carry = tcg_temp_new();
536 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
537 tcg_temp_free(carry);
70c48285
RH		 538 goto sub_done;
539 }
70c48285
RH		 540 carry_32 = gen_sub32_carry32();
541 break;
542
543 default:
544 /* We need external help to produce the carry. */
545 carry_32 = tcg_temp_new_i32();
2ffd9176 546 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 547 break;
548 }
549
550#if TARGET_LONG_BITS == 64
551 carry = tcg_temp_new();
552 tcg_gen_extu_i32_i64(carry, carry_32);
553#else
554 carry = carry_32;
555#endif
556
557 tcg_gen_sub_tl(dst, src1, src2);
558 tcg_gen_sub_tl(dst, dst, carry);
559
560 tcg_temp_free_i32(carry_32);
561#if TARGET_LONG_BITS == 64
562 tcg_temp_free(carry);
563#endif
564
70c48285 565 sub_done:
70c48285
RH		 566 if (update_cc) {
567 tcg_gen_mov_tl(cpu_cc_src, src1);
568 tcg_gen_mov_tl(cpu_cc_src2, src2);
569 tcg_gen_mov_tl(cpu_cc_dst, dst);
570 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
571 dc->cc_op = CC_OP_SUBX;
572 }
dc99a3f2
BS		 573}
574
4af984a7 575static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 576{
de9e9d9f 577 TCGv r_temp, zero, t0;
d9bdab86 578
a7812ae4 579 r_temp = tcg_temp_new();
de9e9d9f 580 t0 = tcg_temp_new();
d9bdab86
BS		 581
582 /* old op:
583 if (!(env->y & 1))
584 T1 = 0;
585 */
6cb675b0 586 zero = tcg_const_tl(0);
72ccba79 587 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 588 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 589 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 590 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
591 zero, cpu_cc_src2);
592 tcg_temp_free(zero);
d9bdab86
BS		 593
594 // b2 = T0 & 1;
595 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 596 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
597 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 598 tcg_gen_shri_tl(t0, cpu_y, 1);
599 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
600 tcg_gen_or_tl(t0, t0, r_temp);
601 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 602
603 // b1 = N ^ V;
de9e9d9f 604 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 605 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 606 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 607 tcg_temp_free(r_temp);
d9bdab86
BS		 608
609 // T0 = (b1 << 31) | (T0 >> 1);
610 // src1 = T0;
de9e9d9f 611 tcg_gen_shli_tl(t0, t0, 31);
6f551262 612 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 613 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
614 tcg_temp_free(t0);
d9bdab86 615
5c6a0628 616 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 617
5c6a0628 618 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 619}
620
fb170183 621static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 622{
528692a8 623#if TARGET_LONG_BITS == 32
fb170183 624 if (sign_ext) {
528692a8 625 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 626 } else {
528692a8 627 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 628 }
528692a8
RH		 629#else
630 TCGv t0 = tcg_temp_new_i64();
631 TCGv t1 = tcg_temp_new_i64();
fb170183 632
528692a8
RH		 633 if (sign_ext) {
634 tcg_gen_ext32s_i64(t0, src1);
635 tcg_gen_ext32s_i64(t1, src2);
636 } else {
637 tcg_gen_ext32u_i64(t0, src1);
638 tcg_gen_ext32u_i64(t1, src2);
639 }
fb170183 640
528692a8
RH		 641 tcg_gen_mul_i64(dst, t0, t1);
642 tcg_temp_free(t0);
643 tcg_temp_free(t1);
fb170183 644
528692a8
RH		 645 tcg_gen_shri_i64(cpu_y, dst, 32);
646#endif
8879d139
BS		 647}
648
fb170183 649static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 650{
fb170183
IK		 651 /* zero-extend truncated operands before multiplication */
652 gen_op_multiply(dst, src1, src2, 0);
653}
8879d139 654
fb170183
IK		 655static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
656{
657 /* sign-extend truncated operands before multiplication */
658 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 659}
660
19f329ad
BS		 661// 1
662static inline void gen_op_eval_ba(TCGv dst)
663{
664 tcg_gen_movi_tl(dst, 1);
665}
666
667// Z
a7812ae4 668static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 669{
670 gen_mov_reg_Z(dst, src);
671}
672
673// Z | (N ^ V)
a7812ae4 674static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 675{
de9e9d9f
RH		 676 TCGv t0 = tcg_temp_new();
677 gen_mov_reg_N(t0, src);
19f329ad 678 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 679 tcg_gen_xor_tl(dst, dst, t0);
680 gen_mov_reg_Z(t0, src);
681 tcg_gen_or_tl(dst, dst, t0);
682 tcg_temp_free(t0);
19f329ad
BS		 683}
684
685// N ^ V
a7812ae4 686static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 687{
de9e9d9f
RH		 688 TCGv t0 = tcg_temp_new();
689 gen_mov_reg_V(t0, src);
19f329ad 690 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 691 tcg_gen_xor_tl(dst, dst, t0);
692 tcg_temp_free(t0);
19f329ad
BS		 693}
694
695// C | Z
a7812ae4 696static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 697{
de9e9d9f
RH		 698 TCGv t0 = tcg_temp_new();
699 gen_mov_reg_Z(t0, src);
19f329ad 700 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 701 tcg_gen_or_tl(dst, dst, t0);
702 tcg_temp_free(t0);
19f329ad
BS		 703}
704
705// C
a7812ae4 706static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 707{
708 gen_mov_reg_C(dst, src);
709}
710
711// V
a7812ae4 712static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 713{
714 gen_mov_reg_V(dst, src);
715}
716
717// 0
718static inline void gen_op_eval_bn(TCGv dst)
719{
720 tcg_gen_movi_tl(dst, 0);
721}
722
723// N
a7812ae4 724static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 725{
726 gen_mov_reg_N(dst, src);
727}
728
729// !Z
a7812ae4 730static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 731{
732 gen_mov_reg_Z(dst, src);
733 tcg_gen_xori_tl(dst, dst, 0x1);
734}
735
736// !(Z | (N ^ V))
a7812ae4 737static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 738{
de9e9d9f 739 gen_op_eval_ble(dst, src);
19f329ad
BS		 740 tcg_gen_xori_tl(dst, dst, 0x1);
741}
742
743// !(N ^ V)
a7812ae4 744static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 745{
de9e9d9f 746 gen_op_eval_bl(dst, src);
19f329ad
BS		 747 tcg_gen_xori_tl(dst, dst, 0x1);
748}
749
750// !(C | Z)
a7812ae4 751static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 752{
de9e9d9f 753 gen_op_eval_bleu(dst, src);
19f329ad
BS		 754 tcg_gen_xori_tl(dst, dst, 0x1);
755}
756
757// !C
a7812ae4 758static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 759{
760 gen_mov_reg_C(dst, src);
761 tcg_gen_xori_tl(dst, dst, 0x1);
762}
763
764// !N
a7812ae4 765static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 766{
767 gen_mov_reg_N(dst, src);
768 tcg_gen_xori_tl(dst, dst, 0x1);
769}
770
771// !V
a7812ae4 772static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 773{
774 gen_mov_reg_V(dst, src);
775 tcg_gen_xori_tl(dst, dst, 0x1);
776}
777
778/*
779 FPSR bit field FCC1 | FCC0:
780 0 =
781 1 <
782 2 >
783 3 unordered
784*/
785static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
786 unsigned int fcc_offset)
787{
ba6a9d8c 788 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 789 tcg_gen_andi_tl(reg, reg, 0x1);
790}
791
792static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
793 unsigned int fcc_offset)
794{
ba6a9d8c 795 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 796 tcg_gen_andi_tl(reg, reg, 0x1);
797}
798
799// !0: FCC0 | FCC1
800static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
801 unsigned int fcc_offset)
802{
de9e9d9f 803 TCGv t0 = tcg_temp_new();
19f329ad 804 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 805 gen_mov_reg_FCC1(t0, src, fcc_offset);
806 tcg_gen_or_tl(dst, dst, t0);
807 tcg_temp_free(t0);
19f329ad
BS		 808}
809
810// 1 or 2: FCC0 ^ FCC1
811static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
812 unsigned int fcc_offset)
813{
de9e9d9f 814 TCGv t0 = tcg_temp_new();
19f329ad 815 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 816 gen_mov_reg_FCC1(t0, src, fcc_offset);
817 tcg_gen_xor_tl(dst, dst, t0);
818 tcg_temp_free(t0);
19f329ad
BS		 819}
820
821// 1 or 3: FCC0
822static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
823 unsigned int fcc_offset)
824{
825 gen_mov_reg_FCC0(dst, src, fcc_offset);
826}
827
828// 1: FCC0 & !FCC1
829static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
830 unsigned int fcc_offset)
831{
de9e9d9f 832 TCGv t0 = tcg_temp_new();
19f329ad 833 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 834 gen_mov_reg_FCC1(t0, src, fcc_offset);
835 tcg_gen_andc_tl(dst, dst, t0);
836 tcg_temp_free(t0);
19f329ad
BS		 837}
838
839// 2 or 3: FCC1
840static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
841 unsigned int fcc_offset)
842{
843 gen_mov_reg_FCC1(dst, src, fcc_offset);
844}
845
846// 2: !FCC0 & FCC1
847static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
848 unsigned int fcc_offset)
849{
de9e9d9f 850 TCGv t0 = tcg_temp_new();
19f329ad 851 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 852 gen_mov_reg_FCC1(t0, src, fcc_offset);
853 tcg_gen_andc_tl(dst, t0, dst);
854 tcg_temp_free(t0);
19f329ad
BS		 855}
856
857// 3: FCC0 & FCC1
858static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
859 unsigned int fcc_offset)
860{
de9e9d9f 861 TCGv t0 = tcg_temp_new();
19f329ad 862 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 863 gen_mov_reg_FCC1(t0, src, fcc_offset);
864 tcg_gen_and_tl(dst, dst, t0);
865 tcg_temp_free(t0);
19f329ad
BS		 866}
867
868// 0: !(FCC0 | FCC1)
869static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
870 unsigned int fcc_offset)
871{
de9e9d9f 872 TCGv t0 = tcg_temp_new();
19f329ad 873 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 874 gen_mov_reg_FCC1(t0, src, fcc_offset);
875 tcg_gen_or_tl(dst, dst, t0);
19f329ad 876 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 877 tcg_temp_free(t0);
19f329ad
BS		 878}
879
880// 0 or 3: !(FCC0 ^ FCC1)
881static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
882 unsigned int fcc_offset)
883{
de9e9d9f 884 TCGv t0 = tcg_temp_new();
19f329ad 885 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 886 gen_mov_reg_FCC1(t0, src, fcc_offset);
887 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 888 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 889 tcg_temp_free(t0);
19f329ad
BS		 890}
891
892// 0 or 2: !FCC0
893static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
894 unsigned int fcc_offset)
895{
896 gen_mov_reg_FCC0(dst, src, fcc_offset);
897 tcg_gen_xori_tl(dst, dst, 0x1);
898}
899
900// !1: !(FCC0 & !FCC1)
901static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
902 unsigned int fcc_offset)
903{
de9e9d9f 904 TCGv t0 = tcg_temp_new();
19f329ad 905 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 906 gen_mov_reg_FCC1(t0, src, fcc_offset);
907 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 908 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 909 tcg_temp_free(t0);
19f329ad
BS		 910}
911
912// 0 or 1: !FCC1
913static inline void gen_op_eval_fble(TCGv dst, TCGv src,
914 unsigned int fcc_offset)
915{
916 gen_mov_reg_FCC1(dst, src, fcc_offset);
917 tcg_gen_xori_tl(dst, dst, 0x1);
918}
919
920// !2: !(!FCC0 & FCC1)
921static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
922 unsigned int fcc_offset)
923{
de9e9d9f 924 TCGv t0 = tcg_temp_new();
19f329ad 925 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 926 gen_mov_reg_FCC1(t0, src, fcc_offset);
927 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 928 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 929 tcg_temp_free(t0);
19f329ad
BS		 930}
931
932// !3: !(FCC0 & FCC1)
933static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
934 unsigned int fcc_offset)
935{
de9e9d9f 936 TCGv t0 = tcg_temp_new();
19f329ad 937 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 938 gen_mov_reg_FCC1(t0, src, fcc_offset);
939 tcg_gen_and_tl(dst, dst, t0);
19f329ad 940 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 941 tcg_temp_free(t0);
19f329ad
BS		 942}
943
46525e1f 944static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 945 target_ulong pc2, TCGv r_cond)
83469015 946{
42a268c2 947 TCGLabel *l1 = gen_new_label();
83469015 948
cb63669a 949 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 950
6e256c93 951 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 952
953 gen_set_label(l1);
6e256c93 954 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 955}
956
bfa31b76 957static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 958{
42a268c2 959 TCGLabel *l1 = gen_new_label();
bfa31b76 960 target_ulong npc = dc->npc;
83469015 961
bfa31b76 962 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 963
bfa31b76 964 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 965
966 gen_set_label(l1);
bfa31b76
RH		 967 gen_goto_tb(dc, 1, npc + 4, npc + 8);
968
969 dc->is_br = 1;
83469015
FB		 970}
971
2bf2e019
RH		 972static void gen_branch_n(DisasContext *dc, target_ulong pc1)
973{
974 target_ulong npc = dc->npc;
975
976 if (likely(npc != DYNAMIC_PC)) {
977 dc->pc = npc;
978 dc->jump_pc[0] = pc1;
979 dc->jump_pc[1] = npc + 4;
980 dc->npc = JUMP_PC;
981 } else {
982 TCGv t, z;
983
984 tcg_gen_mov_tl(cpu_pc, cpu_npc);
985
986 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
987 t = tcg_const_tl(pc1);
988 z = tcg_const_tl(0);
989 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
990 tcg_temp_free(t);
991 tcg_temp_free(z);
992
993 dc->pc = DYNAMIC_PC;
994 }
995}
996
2e655fe7 997static inline void gen_generic_branch(DisasContext *dc)
83469015 998{
61316742
RH		 999 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1000 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1001 TCGv zero = tcg_const_tl(0);
19f329ad 1002
61316742 1003 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1004
61316742
RH		 1005 tcg_temp_free(npc0);
1006 tcg_temp_free(npc1);
1007 tcg_temp_free(zero);
83469015
FB		 1008}
1009
4af984a7
BS		 1010/* call this function before using the condition register as it may
1011 have been set for a jump */
dee8913c 1012static inline void flush_cond(DisasContext *dc)
83469015
FB		 1013{
1014 if (dc->npc == JUMP_PC) {
2e655fe7 1015 gen_generic_branch(dc);
83469015
FB		 1016 dc->npc = DYNAMIC_PC;
1017 }
1018}
1019
934da7ee 1020static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1021{
1022 if (dc->npc == JUMP_PC) {
2e655fe7 1023 gen_generic_branch(dc);
72cbca10
FB		 1024 dc->npc = DYNAMIC_PC;
1025 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1026 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1027 }
1028}
1029
20132b96 1030static inline void update_psr(DisasContext *dc)
72cbca10 1031{
cfa90513
BS		 1032 if (dc->cc_op != CC_OP_FLAGS) {
1033 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1034 gen_helper_compute_psr(cpu_env);
cfa90513 1035 }
20132b96
RH		 1036}
1037
1038static inline void save_state(DisasContext *dc)
1039{
1040 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1041 save_npc(dc);
72cbca10
FB		 1042}
1043
13a6dd00 1044static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1045{
1046 if (dc->npc == JUMP_PC) {
2e655fe7 1047 gen_generic_branch(dc);
48d5c82b 1048 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1049 dc->pc = DYNAMIC_PC;
1050 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1051 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1052 dc->pc = DYNAMIC_PC;
1053 } else {
1054 dc->pc = dc->npc;
1055 }
1056}
1057
38bc628b
BS		 1058static inline void gen_op_next_insn(void)
1059{
48d5c82b
BS		 1060 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1061 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1062}
1063
416fcaea
RH		 1064static void free_compare(DisasCompare *cmp)
1065{
1066 if (!cmp->g1) {
1067 tcg_temp_free(cmp->c1);
1068 }
1069 if (!cmp->g2) {
1070 tcg_temp_free(cmp->c2);
1071 }
1072}
1073
2a484ecf 1074static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1075 DisasContext *dc)
19f329ad 1076{
2a484ecf 1077 static int subcc_cond[16] = {
96b5a3d3 1078 TCG_COND_NEVER,
2a484ecf
RH		 1079 TCG_COND_EQ,
1080 TCG_COND_LE,
1081 TCG_COND_LT,
1082 TCG_COND_LEU,
1083 TCG_COND_LTU,
1084 -1, /* neg */
1085 -1, /* overflow */
96b5a3d3 1086 TCG_COND_ALWAYS,
2a484ecf
RH		 1087 TCG_COND_NE,
1088 TCG_COND_GT,
1089 TCG_COND_GE,
1090 TCG_COND_GTU,
1091 TCG_COND_GEU,
1092 -1, /* pos */
1093 -1, /* no overflow */
1094 };
1095
96b5a3d3
RH		 1096 static int logic_cond[16] = {
1097 TCG_COND_NEVER,
1098 TCG_COND_EQ, /* eq: Z */
1099 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1100 TCG_COND_LT, /* lt: N ^ V -> N */
1101 TCG_COND_EQ, /* leu: C | Z -> Z */
1102 TCG_COND_NEVER, /* ltu: C -> 0 */
1103 TCG_COND_LT, /* neg: N */
1104 TCG_COND_NEVER, /* vs: V -> 0 */
1105 TCG_COND_ALWAYS,
1106 TCG_COND_NE, /* ne: !Z */
1107 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1108 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1109 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1110 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1111 TCG_COND_GE, /* pos: !N */
1112 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1113 };
1114
a7812ae4 1115 TCGv_i32 r_src;
416fcaea
RH		 1116 TCGv r_dst;
1117
3475187d 1118#ifdef TARGET_SPARC64
2a484ecf 1119 if (xcc) {
dc99a3f2 1120 r_src = cpu_xcc;
2a484ecf 1121 } else {
dc99a3f2 1122 r_src = cpu_psr;
2a484ecf 1123 }
3475187d 1124#else
dc99a3f2 1125 r_src = cpu_psr;
3475187d 1126#endif
2a484ecf 1127
8393617c 1128 switch (dc->cc_op) {
96b5a3d3
RH		 1129 case CC_OP_LOGIC:
1130 cmp->cond = logic_cond[cond];
1131 do_compare_dst_0:
1132 cmp->is_bool = false;
1133 cmp->g2 = false;
1134 cmp->c2 = tcg_const_tl(0);
1135#ifdef TARGET_SPARC64
1136 if (!xcc) {
1137 cmp->g1 = false;
1138 cmp->c1 = tcg_temp_new();
1139 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1140 break;
1141 }
1142#endif
1143 cmp->g1 = true;
1144 cmp->c1 = cpu_cc_dst;
1145 break;
1146
2a484ecf
RH		 1147 case CC_OP_SUB:
1148 switch (cond) {
1149 case 6: /* neg */
1150 case 14: /* pos */
1151 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1152 goto do_compare_dst_0;
2a484ecf 1153
2a484ecf
RH		 1154 case 7: /* overflow */
1155 case 15: /* !overflow */
1156 goto do_dynamic;
1157
1158 default:
1159 cmp->cond = subcc_cond[cond];
1160 cmp->is_bool = false;
1161#ifdef TARGET_SPARC64
1162 if (!xcc) {
1163 /* Note that sign-extension works for unsigned compares as
1164 long as both operands are sign-extended. */
1165 cmp->g1 = cmp->g2 = false;
1166 cmp->c1 = tcg_temp_new();
1167 cmp->c2 = tcg_temp_new();
1168 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1169 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1170 break;
2a484ecf
RH		 1171 }
1172#endif
1173 cmp->g1 = cmp->g2 = true;
1174 cmp->c1 = cpu_cc_src;
1175 cmp->c2 = cpu_cc_src2;
1176 break;
1177 }
8393617c 1178 break;
2a484ecf 1179
8393617c 1180 default:
2a484ecf 1181 do_dynamic:
2ffd9176 1182 gen_helper_compute_psr(cpu_env);
8393617c 1183 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1184 /* FALLTHRU */
1185
1186 case CC_OP_FLAGS:
1187 /* We're going to generate a boolean result. */
1188 cmp->cond = TCG_COND_NE;
1189 cmp->is_bool = true;
1190 cmp->g1 = cmp->g2 = false;
1191 cmp->c1 = r_dst = tcg_temp_new();
1192 cmp->c2 = tcg_const_tl(0);
1193
1194 switch (cond) {
1195 case 0x0:
1196 gen_op_eval_bn(r_dst);
1197 break;
1198 case 0x1:
1199 gen_op_eval_be(r_dst, r_src);
1200 break;
1201 case 0x2:
1202 gen_op_eval_ble(r_dst, r_src);
1203 break;
1204 case 0x3:
1205 gen_op_eval_bl(r_dst, r_src);
1206 break;
1207 case 0x4:
1208 gen_op_eval_bleu(r_dst, r_src);
1209 break;
1210 case 0x5:
1211 gen_op_eval_bcs(r_dst, r_src);
1212 break;
1213 case 0x6:
1214 gen_op_eval_bneg(r_dst, r_src);
1215 break;
1216 case 0x7:
1217 gen_op_eval_bvs(r_dst, r_src);
1218 break;
1219 case 0x8:
1220 gen_op_eval_ba(r_dst);
1221 break;
1222 case 0x9:
1223 gen_op_eval_bne(r_dst, r_src);
1224 break;
1225 case 0xa:
1226 gen_op_eval_bg(r_dst, r_src);
1227 break;
1228 case 0xb:
1229 gen_op_eval_bge(r_dst, r_src);
1230 break;
1231 case 0xc:
1232 gen_op_eval_bgu(r_dst, r_src);
1233 break;
1234 case 0xd:
1235 gen_op_eval_bcc(r_dst, r_src);
1236 break;
1237 case 0xe:
1238 gen_op_eval_bpos(r_dst, r_src);
1239 break;
1240 case 0xf:
1241 gen_op_eval_bvc(r_dst, r_src);
1242 break;
1243 }
19f329ad
BS		 1244 break;
1245 }
1246}
7a3f1944 1247
416fcaea 1248static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1249{
19f329ad 1250 unsigned int offset;
416fcaea
RH		 1251 TCGv r_dst;
1252
1253 /* For now we still generate a straight boolean result. */
1254 cmp->cond = TCG_COND_NE;
1255 cmp->is_bool = true;
1256 cmp->g1 = cmp->g2 = false;
1257 cmp->c1 = r_dst = tcg_temp_new();
1258 cmp->c2 = tcg_const_tl(0);
19f329ad 1259
19f329ad
BS		 1260 switch (cc) {
1261 default:
1262 case 0x0:
1263 offset = 0;
1264 break;
1265 case 0x1:
1266 offset = 32 - 10;
1267 break;
1268 case 0x2:
1269 offset = 34 - 10;
1270 break;
1271 case 0x3:
1272 offset = 36 - 10;
1273 break;
1274 }
1275
1276 switch (cond) {
1277 case 0x0:
1278 gen_op_eval_bn(r_dst);
1279 break;
1280 case 0x1:
87e92502 1281 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1282 break;
1283 case 0x2:
87e92502 1284 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1285 break;
1286 case 0x3:
87e92502 1287 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1288 break;
1289 case 0x4:
87e92502 1290 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1291 break;
1292 case 0x5:
87e92502 1293 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1294 break;
1295 case 0x6:
87e92502 1296 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1297 break;
1298 case 0x7:
87e92502 1299 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1300 break;
1301 case 0x8:
1302 gen_op_eval_ba(r_dst);
1303 break;
1304 case 0x9:
87e92502 1305 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1306 break;
1307 case 0xa:
87e92502 1308 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1309 break;
1310 case 0xb:
87e92502 1311 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1312 break;
1313 case 0xc:
87e92502 1314 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1315 break;
1316 case 0xd:
87e92502 1317 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1318 break;
1319 case 0xe:
87e92502 1320 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1321 break;
1322 case 0xf:
87e92502 1323 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1324 break;
1325 }
e8af50a3 1326}
00f219bf 1327
416fcaea
RH		 1328static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1329 DisasContext *dc)
1330{
1331 DisasCompare cmp;
1332 gen_compare(&cmp, cc, cond, dc);
1333
1334 /* The interface is to return a boolean in r_dst. */
1335 if (cmp.is_bool) {
1336 tcg_gen_mov_tl(r_dst, cmp.c1);
1337 } else {
1338 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1339 }
1340
1341 free_compare(&cmp);
1342}
1343
1344static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1345{
1346 DisasCompare cmp;
1347 gen_fcompare(&cmp, cc, cond);
1348
1349 /* The interface is to return a boolean in r_dst. */
1350 if (cmp.is_bool) {
1351 tcg_gen_mov_tl(r_dst, cmp.c1);
1352 } else {
1353 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1354 }
1355
1356 free_compare(&cmp);
1357}
1358
19f329ad 1359#ifdef TARGET_SPARC64
00f219bf
BS		 1360// Inverted logic
1361static const int gen_tcg_cond_reg[8] = {
1362 -1,
1363 TCG_COND_NE,
1364 TCG_COND_GT,
1365 TCG_COND_GE,
1366 -1,
1367 TCG_COND_EQ,
1368 TCG_COND_LE,
1369 TCG_COND_LT,
1370};
19f329ad 1371
416fcaea
RH		 1372static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1373{
1374 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1375 cmp->is_bool = false;
1376 cmp->g1 = true;
1377 cmp->g2 = false;
1378 cmp->c1 = r_src;
1379 cmp->c2 = tcg_const_tl(0);
1380}
1381
4af984a7 1382static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1383{
416fcaea
RH		 1384 DisasCompare cmp;
1385 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1386
416fcaea
RH		 1387 /* The interface is to return a boolean in r_dst. */
1388 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1389
1390 free_compare(&cmp);
19f329ad 1391}
3475187d 1392#endif
cf495bcf 1393
d4a288ef 1394static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1395{
cf495bcf 1396 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1397 target_ulong target = dc->pc + offset;
5fafdf24 1398
22036a49
AT		 1399#ifdef TARGET_SPARC64
1400 if (unlikely(AM_CHECK(dc))) {
1401 target &= 0xffffffffULL;
1402 }
1403#endif
cf495bcf 1404 if (cond == 0x0) {
0f8a249a
BS		 1405 /* unconditional not taken */
1406 if (a) {
1407 dc->pc = dc->npc + 4;
1408 dc->npc = dc->pc + 4;
1409 } else {
1410 dc->pc = dc->npc;
1411 dc->npc = dc->pc + 4;
1412 }
cf495bcf 1413 } else if (cond == 0x8) {
0f8a249a
BS		 1414 /* unconditional taken */
1415 if (a) {
1416 dc->pc = target;
1417 dc->npc = dc->pc + 4;
1418 } else {
1419 dc->pc = dc->npc;
1420 dc->npc = target;
c27e2752 1421 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1422 }
cf495bcf 1423 } else {
dee8913c 1424 flush_cond(dc);
d4a288ef 1425 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1426 if (a) {
bfa31b76 1427 gen_branch_a(dc, target);
0f8a249a 1428 } else {
2bf2e019 1429 gen_branch_n(dc, target);
0f8a249a 1430 }
cf495bcf 1431 }
7a3f1944
FB		 1432}
1433
d4a288ef 1434static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1435{
1436 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1437 target_ulong target = dc->pc + offset;
1438
22036a49
AT		 1439#ifdef TARGET_SPARC64
1440 if (unlikely(AM_CHECK(dc))) {
1441 target &= 0xffffffffULL;
1442 }
1443#endif
e8af50a3 1444 if (cond == 0x0) {
0f8a249a
BS		 1445 /* unconditional not taken */
1446 if (a) {
1447 dc->pc = dc->npc + 4;
1448 dc->npc = dc->pc + 4;
1449 } else {
1450 dc->pc = dc->npc;
1451 dc->npc = dc->pc + 4;
1452 }
e8af50a3 1453 } else if (cond == 0x8) {
0f8a249a
BS		 1454 /* unconditional taken */
1455 if (a) {
1456 dc->pc = target;
1457 dc->npc = dc->pc + 4;
1458 } else {
1459 dc->pc = dc->npc;
1460 dc->npc = target;
c27e2752 1461 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1462 }
e8af50a3 1463 } else {
dee8913c 1464 flush_cond(dc);
d4a288ef 1465 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1466 if (a) {
bfa31b76 1467 gen_branch_a(dc, target);
0f8a249a 1468 } else {
2bf2e019 1469 gen_branch_n(dc, target);
0f8a249a 1470 }
e8af50a3
FB		 1471 }
1472}
1473
3475187d 1474#ifdef TARGET_SPARC64
4af984a7 1475static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1476 TCGv r_reg)
7a3f1944 1477{
3475187d
FB		 1478 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1479 target_ulong target = dc->pc + offset;
1480
22036a49
AT		 1481 if (unlikely(AM_CHECK(dc))) {
1482 target &= 0xffffffffULL;
1483 }
dee8913c 1484 flush_cond(dc);
d4a288ef 1485 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1486 if (a) {
bfa31b76 1487 gen_branch_a(dc, target);
3475187d 1488 } else {
2bf2e019 1489 gen_branch_n(dc, target);
3475187d 1490 }
7a3f1944
FB		 1491}
1492
a7812ae4 1493static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1494{
714547bb
BS		 1495 switch (fccno) {
1496 case 0:
2e2f4ade 1497 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1498 break;
1499 case 1:
2e2f4ade 1500 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1501 break;
1502 case 2:
2e2f4ade 1503 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1504 break;
1505 case 3:
2e2f4ade 1506 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1507 break;
1508 }
7e8c2b6c
BS		 1509}
1510
03fb8cfc 1511static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1512{
a7812ae4
PB		 1513 switch (fccno) {
1514 case 0:
03fb8cfc 1515 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1516 break;
1517 case 1:
03fb8cfc 1518 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1519 break;
1520 case 2:
03fb8cfc 1521 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1522 break;
1523 case 3:
03fb8cfc 1524 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1525 break;
1526 }
7e8c2b6c
BS		 1527}
1528
7e8c2b6c
BS		 1529static inline void gen_op_fcmpq(int fccno)
1530{
a7812ae4
PB		 1531 switch (fccno) {
1532 case 0:
2e2f4ade 1533 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1534 break;
1535 case 1:
2e2f4ade 1536 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1537 break;
1538 case 2:
2e2f4ade 1539 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1540 break;
1541 case 3:
2e2f4ade 1542 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1543 break;
1544 }
7e8c2b6c 1545}
7e8c2b6c 1546
a7812ae4 1547static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1548{
714547bb
BS		 1549 switch (fccno) {
1550 case 0:
2e2f4ade 1551 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1552 break;
1553 case 1:
2e2f4ade 1554 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1555 break;
1556 case 2:
2e2f4ade 1557 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1558 break;
1559 case 3:
2e2f4ade 1560 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1561 break;
1562 }
7e8c2b6c
BS		 1563}
1564
03fb8cfc 1565static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1566{
a7812ae4
PB		 1567 switch (fccno) {
1568 case 0:
03fb8cfc 1569 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1570 break;
1571 case 1:
03fb8cfc 1572 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1573 break;
1574 case 2:
03fb8cfc 1575 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1576 break;
1577 case 3:
03fb8cfc 1578 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1579 break;
1580 }
7e8c2b6c
BS		 1581}
1582
7e8c2b6c
BS		 1583static inline void gen_op_fcmpeq(int fccno)
1584{
a7812ae4
PB		 1585 switch (fccno) {
1586 case 0:
2e2f4ade 1587 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1588 break;
1589 case 1:
2e2f4ade 1590 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1591 break;
1592 case 2:
2e2f4ade 1593 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1594 break;
1595 case 3:
2e2f4ade 1596 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1597 break;
1598 }
7e8c2b6c 1599}
7e8c2b6c
BS		 1600
1601#else
1602
714547bb 1603static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1604{
2e2f4ade 1605 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1606}
1607
03fb8cfc 1608static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1609{
03fb8cfc 1610 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1611}
1612
7e8c2b6c
BS		 1613static inline void gen_op_fcmpq(int fccno)
1614{
2e2f4ade 1615 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1616}
7e8c2b6c 1617
714547bb 1618static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1619{
2e2f4ade 1620 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1621}
1622
03fb8cfc 1623static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1624{
03fb8cfc 1625 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1626}
1627
7e8c2b6c
BS		 1628static inline void gen_op_fcmpeq(int fccno)
1629{
2e2f4ade 1630 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1631}
1632#endif
1633
134d77a1
BS		 1634static inline void gen_op_fpexception_im(int fsr_flags)
1635{
a7812ae4 1636 TCGv_i32 r_const;
2ea815ca 1637
47ad35f1 1638 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1639 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca 1640 r_const = tcg_const_i32(TT_FP_EXCP);
bc265319 1641 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1642 tcg_temp_free_i32(r_const);
134d77a1
BS		 1643}
1644
5b12f1e8 1645static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1646{
1647#if !defined(CONFIG_USER_ONLY)
1648 if (!dc->fpu_enabled) {
a7812ae4 1649 TCGv_i32 r_const;
2ea815ca 1650
66442b07 1651 save_state(dc);
2ea815ca 1652 r_const = tcg_const_i32(TT_NFPU_INSN);
bc265319 1653 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1654 tcg_temp_free_i32(r_const);
a80dde08
FB		 1655 dc->is_br = 1;
1656 return 1;
1657 }
1658#endif
1659 return 0;
1660}
1661
7e8c2b6c
BS		 1662static inline void gen_op_clear_ieee_excp_and_FTT(void)
1663{
47ad35f1 1664 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1665}
1666
61f17f6e
RH		 1667static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1668 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1669{
1670 TCGv_i32 dst, src;
1671
61f17f6e 1672 src = gen_load_fpr_F(dc, rs);
ba5f5179 1673 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1674
1675 gen(dst, cpu_env, src);
1676
61f17f6e
RH		 1677 gen_store_fpr_F(dc, rd, dst);
1678}
1679
1680static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1681 void (*gen)(TCGv_i32, TCGv_i32))
1682{
1683 TCGv_i32 dst, src;
1684
1685 src = gen_load_fpr_F(dc, rs);
ba5f5179 1686 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1687
1688 gen(dst, src);
1689
1690 gen_store_fpr_F(dc, rd, dst);
1691}
1692
1693static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1694 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1695{
1696 TCGv_i32 dst, src1, src2;
1697
61f17f6e
RH		 1698 src1 = gen_load_fpr_F(dc, rs1);
1699 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1700 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1701
1702 gen(dst, cpu_env, src1, src2);
1703
61f17f6e
RH		 1704 gen_store_fpr_F(dc, rd, dst);
1705}
1706
1707#ifdef TARGET_SPARC64
1708static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1709 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1710{
1711 TCGv_i32 dst, src1, src2;
1712
1713 src1 = gen_load_fpr_F(dc, rs1);
1714 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1715 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1716
1717 gen(dst, src1, src2);
1718
1719 gen_store_fpr_F(dc, rd, dst);
1720}
1721#endif
1722
1723static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1724 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1725{
1726 TCGv_i64 dst, src;
1727
61f17f6e 1728 src = gen_load_fpr_D(dc, rs);
3886b8a3 1729 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1730
1731 gen(dst, cpu_env, src);
1732
61f17f6e
RH		 1733 gen_store_fpr_D(dc, rd, dst);
1734}
1735
1736#ifdef TARGET_SPARC64
1737static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1738 void (*gen)(TCGv_i64, TCGv_i64))
1739{
1740 TCGv_i64 dst, src;
1741
1742 src = gen_load_fpr_D(dc, rs);
3886b8a3 1743 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1744
1745 gen(dst, src);
1746
1747 gen_store_fpr_D(dc, rd, dst);
1748}
1749#endif
1750
1751static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1752 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1753{
1754 TCGv_i64 dst, src1, src2;
1755
61f17f6e
RH		 1756 src1 = gen_load_fpr_D(dc, rs1);
1757 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1758 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1759
1760 gen(dst, cpu_env, src1, src2);
1761
61f17f6e
RH		 1762 gen_store_fpr_D(dc, rd, dst);
1763}
1764
1765#ifdef TARGET_SPARC64
1766static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1767 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1768{
1769 TCGv_i64 dst, src1, src2;
1770
1771 src1 = gen_load_fpr_D(dc, rs1);
1772 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1773 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1774
1775 gen(dst, src1, src2);
1776
1777 gen_store_fpr_D(dc, rd, dst);
1778}
f888300b 1779
2dedf314
RH		 1780static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1781 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1782{
1783 TCGv_i64 dst, src1, src2;
1784
1785 src1 = gen_load_fpr_D(dc, rs1);
1786 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1787 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1788
1789 gen(dst, cpu_gsr, src1, src2);
1790
1791 gen_store_fpr_D(dc, rd, dst);
1792}
1793
f888300b
RH		 1794static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1795 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1796{
1797 TCGv_i64 dst, src0, src1, src2;
1798
1799 src1 = gen_load_fpr_D(dc, rs1);
1800 src2 = gen_load_fpr_D(dc, rs2);
1801 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1802 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1803
1804 gen(dst, src0, src1, src2);
1805
1806 gen_store_fpr_D(dc, rd, dst);
1807}
61f17f6e
RH		 1808#endif
1809
1810static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1811 void (*gen)(TCGv_ptr))
1812{
61f17f6e
RH		 1813 gen_op_load_fpr_QT1(QFPREG(rs));
1814
1815 gen(cpu_env);
1816
61f17f6e
RH		 1817 gen_op_store_QT0_fpr(QFPREG(rd));
1818 gen_update_fprs_dirty(QFPREG(rd));
1819}
1820
1821#ifdef TARGET_SPARC64
1822static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1823 void (*gen)(TCGv_ptr))
1824{
1825 gen_op_load_fpr_QT1(QFPREG(rs));
1826
1827 gen(cpu_env);
1828
1829 gen_op_store_QT0_fpr(QFPREG(rd));
1830 gen_update_fprs_dirty(QFPREG(rd));
1831}
1832#endif
1833
1834static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1835 void (*gen)(TCGv_ptr))
1836{
61f17f6e
RH		 1837 gen_op_load_fpr_QT0(QFPREG(rs1));
1838 gen_op_load_fpr_QT1(QFPREG(rs2));
1839
1840 gen(cpu_env);
1841
61f17f6e
RH		 1842 gen_op_store_QT0_fpr(QFPREG(rd));
1843 gen_update_fprs_dirty(QFPREG(rd));
1844}
1845
1846static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1847 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1848{
1849 TCGv_i64 dst;
1850 TCGv_i32 src1, src2;
1851
61f17f6e
RH		 1852 src1 = gen_load_fpr_F(dc, rs1);
1853 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1854 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1855
1856 gen(dst, cpu_env, src1, src2);
1857
61f17f6e
RH		 1858 gen_store_fpr_D(dc, rd, dst);
1859}
1860
1861static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1862 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1863{
1864 TCGv_i64 src1, src2;
1865
61f17f6e
RH		 1866 src1 = gen_load_fpr_D(dc, rs1);
1867 src2 = gen_load_fpr_D(dc, rs2);
1868
1869 gen(cpu_env, src1, src2);
1870
61f17f6e
RH		 1871 gen_op_store_QT0_fpr(QFPREG(rd));
1872 gen_update_fprs_dirty(QFPREG(rd));
1873}
1874
1875#ifdef TARGET_SPARC64
1876static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1877 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1878{
1879 TCGv_i64 dst;
1880 TCGv_i32 src;
1881
61f17f6e 1882 src = gen_load_fpr_F(dc, rs);
3886b8a3 1883 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1884
1885 gen(dst, cpu_env, src);
1886
61f17f6e
RH		 1887 gen_store_fpr_D(dc, rd, dst);
1888}
1889#endif
1890
1891static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1892 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1893{
1894 TCGv_i64 dst;
1895 TCGv_i32 src;
1896
1897 src = gen_load_fpr_F(dc, rs);
3886b8a3 1898 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1899
1900 gen(dst, cpu_env, src);
1901
1902 gen_store_fpr_D(dc, rd, dst);
1903}
1904
1905static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1906 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1907{
1908 TCGv_i32 dst;
1909 TCGv_i64 src;
1910
61f17f6e 1911 src = gen_load_fpr_D(dc, rs);
ba5f5179 1912 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1913
1914 gen(dst, cpu_env, src);
1915
61f17f6e
RH		 1916 gen_store_fpr_F(dc, rd, dst);
1917}
1918
1919static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1920 void (*gen)(TCGv_i32, TCGv_ptr))
1921{
1922 TCGv_i32 dst;
1923
61f17f6e 1924 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1925 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1926
1927 gen(dst, cpu_env);
1928
61f17f6e
RH		 1929 gen_store_fpr_F(dc, rd, dst);
1930}
1931
1932static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1933 void (*gen)(TCGv_i64, TCGv_ptr))
1934{
1935 TCGv_i64 dst;
1936
61f17f6e 1937 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1938 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1939
1940 gen(dst, cpu_env);
1941
61f17f6e
RH		 1942 gen_store_fpr_D(dc, rd, dst);
1943}
1944
1945static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1946 void (*gen)(TCGv_ptr, TCGv_i32))
1947{
1948 TCGv_i32 src;
1949
1950 src = gen_load_fpr_F(dc, rs);
1951
1952 gen(cpu_env, src);
1953
1954 gen_op_store_QT0_fpr(QFPREG(rd));
1955 gen_update_fprs_dirty(QFPREG(rd));
1956}
1957
1958static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1959 void (*gen)(TCGv_ptr, TCGv_i64))
1960{
1961 TCGv_i64 src;
1962
1963 src = gen_load_fpr_D(dc, rs);
1964
1965 gen(cpu_env, src);
1966
1967 gen_op_store_QT0_fpr(QFPREG(rd));
1968 gen_update_fprs_dirty(QFPREG(rd));
1969}
1970
1a2fb1c0
BS		 1971/* asi moves */
1972#ifdef TARGET_SPARC64
a7812ae4 1973static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0 1974{
95f9397c 1975 int asi;
a7812ae4 1976 TCGv_i32 r_asi;
1a2fb1c0 1977
1a2fb1c0 1978 if (IS_IMM) {
a7812ae4 1979 r_asi = tcg_temp_new_i32();
255e1fcb 1980 tcg_gen_mov_i32(r_asi, cpu_asi);
1a2fb1c0
BS		 1981 } else {
1982 asi = GET_FIELD(insn, 19, 26);
0425bee5 1983 r_asi = tcg_const_i32(asi);
1a2fb1c0 1984 }
0425bee5
BS		 1985 return r_asi;
1986}
1987
77f193da
BS		 1988static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1989 int sign)
0425bee5 1990{
a7812ae4 1991 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 1992
4af984a7 1993 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1994 r_size = tcg_const_i32(size);
1995 r_sign = tcg_const_i32(sign);
fe8d8f0f 1996 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4
PB		 1997 tcg_temp_free_i32(r_sign);
1998 tcg_temp_free_i32(r_size);
1999 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2000}
2001
4af984a7 2002static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2003{
a7812ae4 2004 TCGv_i32 r_asi, r_size;
1a2fb1c0 2005
4af984a7 2006 r_asi = gen_get_asi(insn, addr);
2ea815ca 2007 r_size = tcg_const_i32(size);
fe8d8f0f 2008 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2009 tcg_temp_free_i32(r_size);
2010 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2011}
2012
4af984a7 2013static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2014{
a7812ae4 2015 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2016
4af984a7 2017 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2018 r_size = tcg_const_i32(size);
2019 r_rd = tcg_const_i32(rd);
fe8d8f0f 2020 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2021 tcg_temp_free_i32(r_rd);
2022 tcg_temp_free_i32(r_size);
2023 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2024}
2025
4af984a7 2026static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2027{
a7812ae4 2028 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2029
31741a27 2030 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2031 r_size = tcg_const_i32(size);
2032 r_rd = tcg_const_i32(rd);
fe8d8f0f 2033 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2034 tcg_temp_free_i32(r_rd);
2035 tcg_temp_free_i32(r_size);
2036 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2037}
2038
06828032 2039static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2040{
a7812ae4 2041 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2042 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2043
4af984a7 2044 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2045 r_size = tcg_const_i32(4);
2046 r_sign = tcg_const_i32(0);
1ec789ab 2047 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4 2048 tcg_temp_free_i32(r_sign);
06828032 2049 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2050 tcg_temp_free_i32(r_size);
2051 tcg_temp_free_i32(r_asi);
1ec789ab
RH		 2052 tcg_gen_trunc_i64_tl(dst, t64);
2053 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2054}
2055
c7785e16
RH		 2056static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2057 int insn, int rd)
1a2fb1c0 2058{
a7812ae4 2059 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2060
4af984a7 2061 r_asi = gen_get_asi(insn, addr);
db166940 2062 r_rd = tcg_const_i32(rd);
fe8d8f0f 2063 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
a7812ae4
PB		 2064 tcg_temp_free_i32(r_rd);
2065 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2066}
2067
c7785e16
RH		 2068static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2069 int insn, int rd)
0425bee5 2070{
a7812ae4 2071 TCGv_i32 r_asi, r_size;
c7785e16 2072 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2073 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2074
1ec789ab 2075 tcg_gen_concat_tl_i64(t64, lo, hi);
4af984a7 2076 r_asi = gen_get_asi(insn, addr);
2ea815ca 2077 r_size = tcg_const_i32(8);
1ec789ab 2078 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
a7812ae4
PB		 2079 tcg_temp_free_i32(r_size);
2080 tcg_temp_free_i32(r_asi);
1ec789ab 2081 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2082}
2083
81634eea 2084static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
c7785e16 2085 TCGv val2, int insn, int rd)
1a2fb1c0 2086{
81634eea
RH		 2087 TCGv val1 = gen_load_gpr(dc, rd);
2088 TCGv dst = gen_dest_gpr(dc, rd);
c7785e16 2089 TCGv_i32 r_asi = gen_get_asi(insn, addr);
1a2fb1c0 2090
81634eea 2091 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2092 tcg_temp_free_i32(r_asi);
81634eea 2093 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2094}
2095
2096#elif !defined(CONFIG_USER_ONLY)
2097
77f193da
BS		 2098static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2099 int sign)
1a2fb1c0 2100{
a7812ae4 2101 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2102 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2103
2ea815ca
BS		 2104 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2105 r_size = tcg_const_i32(size);
2106 r_sign = tcg_const_i32(sign);
1ec789ab
RH		 2107 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2108 tcg_temp_free_i32(r_sign);
2109 tcg_temp_free_i32(r_size);
2110 tcg_temp_free_i32(r_asi);
2111 tcg_gen_trunc_i64_tl(dst, t64);
2112 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2113}
2114
4af984a7 2115static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2116{
a7812ae4 2117 TCGv_i32 r_asi, r_size;
1ec789ab 2118 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2119
1ec789ab 2120 tcg_gen_extu_tl_i64(t64, src);
2ea815ca
BS		 2121 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2122 r_size = tcg_const_i32(size);
1ec789ab
RH		 2123 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2124 tcg_temp_free_i32(r_size);
2125 tcg_temp_free_i32(r_asi);
2126 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2127}
2128
06828032 2129static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2130{
a7812ae4 2131 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2132 TCGv_i64 r_val, t64;
1a2fb1c0 2133
2ea815ca
BS		 2134 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2135 r_size = tcg_const_i32(4);
2136 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2137 t64 = tcg_temp_new_i64();
2138 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2ea815ca 2139 tcg_temp_free(r_sign);
a7812ae4 2140 r_val = tcg_temp_new_i64();
06828032 2141 tcg_gen_extu_tl_i64(r_val, src);
fe8d8f0f 2142 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4 2143 tcg_temp_free_i64(r_val);
1ec789ab
RH		 2144 tcg_temp_free_i32(r_size);
2145 tcg_temp_free_i32(r_asi);
2146 tcg_gen_trunc_i64_tl(dst, t64);
2147 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2148}
2149
c7785e16
RH		 2150static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2151 int insn, int rd)
1a2fb1c0 2152{
a7812ae4 2153 TCGv_i32 r_asi, r_size, r_sign;
c7785e16 2154 TCGv t;
1ec789ab 2155 TCGv_i64 t64;
1a2fb1c0 2156
2ea815ca
BS		 2157 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2158 r_size = tcg_const_i32(8);
2159 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2160 t64 = tcg_temp_new_i64();
2161 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2162 tcg_temp_free_i32(r_sign);
2163 tcg_temp_free_i32(r_size);
2164 tcg_temp_free_i32(r_asi);
c7785e16
RH		 2165
2166 t = gen_dest_gpr(dc, rd + 1);
1ec789ab 2167 tcg_gen_trunc_i64_tl(t, t64);
c7785e16
RH		 2168 gen_store_gpr(dc, rd + 1, t);
2169
1ec789ab
RH		 2170 tcg_gen_shri_i64(t64, t64, 32);
2171 tcg_gen_trunc_i64_tl(hi, t64);
2172 tcg_temp_free_i64(t64);
c7785e16 2173 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2174}
2175
c7785e16
RH		 2176static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2177 int insn, int rd)
0425bee5 2178{
a7812ae4 2179 TCGv_i32 r_asi, r_size;
c7785e16 2180 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2181 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2182
1ec789ab 2183 tcg_gen_concat_tl_i64(t64, lo, hi);
2ea815ca
BS		 2184 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2185 r_size = tcg_const_i32(8);
1ec789ab
RH		 2186 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2187 tcg_temp_free_i32(r_size);
2188 tcg_temp_free_i32(r_asi);
2189 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2190}
2191#endif
2192
2193#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
16c358e9
SH		 2194static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
2195 TCGv val2, int insn, int rd)
2196{
2197 TCGv val1 = gen_load_gpr(dc, rd);
2198 TCGv dst = gen_dest_gpr(dc, rd);
2199#ifdef TARGET_SPARC64
2200 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2201#else
2202 TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2203#endif
2204
2205 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2206 tcg_temp_free_i32(r_asi);
2207 gen_store_gpr(dc, rd, dst);
2208}
2209
4af984a7 2210static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2211{
a7812ae4
PB		 2212 TCGv_i64 r_val;
2213 TCGv_i32 r_asi, r_size;
1a2fb1c0 2214
4af984a7 2215 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 2216
2ea815ca
BS		 2217 r_val = tcg_const_i64(0xffULL);
2218 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2219 r_size = tcg_const_i32(1);
fe8d8f0f 2220 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4
PB		 2221 tcg_temp_free_i32(r_size);
2222 tcg_temp_free_i32(r_asi);
2223 tcg_temp_free_i64(r_val);
1a2fb1c0
BS		 2224}
2225#endif
2226
9d1d4e34 2227static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2228{
9d1d4e34
RH		 2229 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2230 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2231}
2232
9d1d4e34 2233static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2234{
a49d9390 2235 if (IS_IMM) { /* immediate */
42a8aa83 2236 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2237 TCGv t = get_temp_tl(dc);
2238 tcg_gen_movi_tl(t, simm);
2239 return t;
2240 } else { /* register */
42a8aa83 2241 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2242 return gen_load_gpr(dc, rs2);
a49d9390 2243 }
a49d9390
BS		 2244}
2245
8194f35a 2246#ifdef TARGET_SPARC64
7e480893
RH		 2247static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2248{
2249 TCGv_i32 c32, zero, dst, s1, s2;
2250
2251 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2252 or fold the comparison down to 32 bits and use movcond_i32. Choose
2253 the later. */
2254 c32 = tcg_temp_new_i32();
2255 if (cmp->is_bool) {
ecc7b3aa 2256 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2257 } else {
2258 TCGv_i64 c64 = tcg_temp_new_i64();
2259 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2260 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2261 tcg_temp_free_i64(c64);
2262 }
2263
2264 s1 = gen_load_fpr_F(dc, rs);
2265 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2266 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2267 zero = tcg_const_i32(0);
2268
2269 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2270
2271 tcg_temp_free_i32(c32);
2272 tcg_temp_free_i32(zero);
2273 gen_store_fpr_F(dc, rd, dst);
2274}
2275
2276static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2277{
3886b8a3 2278 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2279 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2280 gen_load_fpr_D(dc, rs),
2281 gen_load_fpr_D(dc, rd));
2282 gen_store_fpr_D(dc, rd, dst);
2283}
2284
2285static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2286{
2287 int qd = QFPREG(rd);
2288 int qs = QFPREG(rs);
2289
2290 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2291 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2292 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2293 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2294
2295 gen_update_fprs_dirty(qd);
2296}
2297
a2035e83 2298#ifndef CONFIG_USER_ONLY
8194f35a
IK		 2299static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2300{
b551ec04 2301 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2302
2303 /* load env->tl into r_tl */
b551ec04 2304 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2305
2306 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2307 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2308
2309 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2310 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2311 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2312
2313 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2314 {
2315 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2316 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2317 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2318 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2319 }
8194f35a 2320
b551ec04 2321 tcg_temp_free_i32(r_tl);
8194f35a 2322}
a2035e83 2323#endif
6c073553
RH		 2324
2325static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2326 int width, bool cc, bool left)
2327{
2328 TCGv lo1, lo2, t1, t2;
2329 uint64_t amask, tabl, tabr;
2330 int shift, imask, omask;
2331
2332 if (cc) {
2333 tcg_gen_mov_tl(cpu_cc_src, s1);
2334 tcg_gen_mov_tl(cpu_cc_src2, s2);
2335 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2336 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2337 dc->cc_op = CC_OP_SUB;
2338 }
2339
2340 /* Theory of operation: there are two tables, left and right (not to
2341 be confused with the left and right versions of the opcode). These
2342 are indexed by the low 3 bits of the inputs. To make things "easy",
2343 these tables are loaded into two constants, TABL and TABR below.
2344 The operation index = (input & imask) << shift calculates the index
2345 into the constant, while val = (table >> index) & omask calculates
2346 the value we're looking for. */
2347 switch (width) {
2348 case 8:
2349 imask = 0x7;
2350 shift = 3;
2351 omask = 0xff;
2352 if (left) {
2353 tabl = 0x80c0e0f0f8fcfeffULL;
2354 tabr = 0xff7f3f1f0f070301ULL;
2355 } else {
2356 tabl = 0x0103070f1f3f7fffULL;
2357 tabr = 0xfffefcf8f0e0c080ULL;
2358 }
2359 break;
2360 case 16:
2361 imask = 0x6;
2362 shift = 1;
2363 omask = 0xf;
2364 if (left) {
2365 tabl = 0x8cef;
2366 tabr = 0xf731;
2367 } else {
2368 tabl = 0x137f;
2369 tabr = 0xfec8;
2370 }
2371 break;
2372 case 32:
2373 imask = 0x4;
2374 shift = 0;
2375 omask = 0x3;
2376 if (left) {
2377 tabl = (2 << 2) | 3;
2378 tabr = (3 << 2) | 1;
2379 } else {
2380 tabl = (1 << 2) | 3;
2381 tabr = (3 << 2) | 2;
2382 }
2383 break;
2384 default:
2385 abort();
2386 }
2387
2388 lo1 = tcg_temp_new();
2389 lo2 = tcg_temp_new();
2390 tcg_gen_andi_tl(lo1, s1, imask);
2391 tcg_gen_andi_tl(lo2, s2, imask);
2392 tcg_gen_shli_tl(lo1, lo1, shift);
2393 tcg_gen_shli_tl(lo2, lo2, shift);
2394
2395 t1 = tcg_const_tl(tabl);
2396 t2 = tcg_const_tl(tabr);
2397 tcg_gen_shr_tl(lo1, t1, lo1);
2398 tcg_gen_shr_tl(lo2, t2, lo2);
2399 tcg_gen_andi_tl(dst, lo1, omask);
2400 tcg_gen_andi_tl(lo2, lo2, omask);
2401
2402 amask = -8;
2403 if (AM_CHECK(dc)) {
2404 amask &= 0xffffffffULL;
2405 }
2406 tcg_gen_andi_tl(s1, s1, amask);
2407 tcg_gen_andi_tl(s2, s2, amask);
2408
2409 /* We want to compute
2410 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2411 We've already done dst = lo1, so this reduces to
2412 dst &= (s1 == s2 ? -1 : lo2)
2413 Which we perform by
2414 lo2 |= -(s1 == s2)
2415 dst &= lo2
2416 */
2417 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2418 tcg_gen_neg_tl(t1, t1);
2419 tcg_gen_or_tl(lo2, lo2, t1);
2420 tcg_gen_and_tl(dst, dst, lo2);
2421
2422 tcg_temp_free(lo1);
2423 tcg_temp_free(lo2);
2424 tcg_temp_free(t1);
2425 tcg_temp_free(t2);
2426}
add545ab
RH		 2427
2428static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2429{
2430 TCGv tmp = tcg_temp_new();
2431
2432 tcg_gen_add_tl(tmp, s1, s2);
2433 tcg_gen_andi_tl(dst, tmp, -8);
2434 if (left) {
2435 tcg_gen_neg_tl(tmp, tmp);
2436 }
2437 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2438
2439 tcg_temp_free(tmp);
2440}
50c796f9
RH		 2441
2442static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2443{
2444 TCGv t1, t2, shift;
2445
2446 t1 = tcg_temp_new();
2447 t2 = tcg_temp_new();
2448 shift = tcg_temp_new();
2449
2450 tcg_gen_andi_tl(shift, gsr, 7);
2451 tcg_gen_shli_tl(shift, shift, 3);
2452 tcg_gen_shl_tl(t1, s1, shift);
2453
2454 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2455 shift of (up to 63) followed by a constant shift of 1. */
2456 tcg_gen_xori_tl(shift, shift, 63);
2457 tcg_gen_shr_tl(t2, s2, shift);
2458 tcg_gen_shri_tl(t2, t2, 1);
2459
2460 tcg_gen_or_tl(dst, t1, t2);
2461
2462 tcg_temp_free(t1);
2463 tcg_temp_free(t2);
2464 tcg_temp_free(shift);
2465}
8194f35a
IK		 2466#endif
2467
64a88d5d 2468#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2469 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2470 goto illegal_insn;
2471#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2472 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2473 goto nfpu_insn;
2474
0bee699e 2475/* before an instruction, dc->pc must be static */
0184e266 2476static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2477{
0184e266 2478 unsigned int opc, rs1, rs2, rd;
a4273524 2479 TCGv cpu_src1, cpu_src2;
208ae657 2480 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2481 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2482 target_long simm;
7a3f1944 2483
cf495bcf 2484 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2485 rd = GET_FIELD(insn, 2, 6);
6ae20372 2486
cf495bcf 2487 switch (opc) {
0f8a249a
BS		 2488 case 0: /* branches/sethi */
2489 {
2490 unsigned int xop = GET_FIELD(insn, 7, 9);
2491 int32_t target;
2492 switch (xop) {
3475187d 2493#ifdef TARGET_SPARC64
0f8a249a
BS		 2494 case 0x1: /* V9 BPcc */
2495 {
2496 int cc;
2497
2498 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2499 target = sign_extend(target, 19);
0f8a249a
BS		 2500 target <<= 2;
2501 cc = GET_FIELD_SP(insn, 20, 21);
2502 if (cc == 0)
d4a288ef 2503 do_branch(dc, target, insn, 0);
0f8a249a 2504 else if (cc == 2)
d4a288ef 2505 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2506 else
2507 goto illegal_insn;
2508 goto jmp_insn;
2509 }
2510 case 0x3: /* V9 BPr */
2511 {
2512 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2513 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2514 target = sign_extend(target, 16);
2515 target <<= 2;
9d1d4e34 2516 cpu_src1 = get_src1(dc, insn);
d4a288ef 2517 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2518 goto jmp_insn;
2519 }
2520 case 0x5: /* V9 FBPcc */
2521 {
2522 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2523 if (gen_trap_ifnofpu(dc)) {
a80dde08 2524 goto jmp_insn;
5b12f1e8 2525 }
0f8a249a
BS		 2526 target = GET_FIELD_SP(insn, 0, 18);
2527 target = sign_extend(target, 19);
2528 target <<= 2;
d4a288ef 2529 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2530 goto jmp_insn;
2531 }
a4d17f19 2532#else
0f8a249a
BS		 2533 case 0x7: /* CBN+x */
2534 {
2535 goto ncp_insn;
2536 }
2537#endif
2538 case 0x2: /* BN+x */
2539 {
2540 target = GET_FIELD(insn, 10, 31);
2541 target = sign_extend(target, 22);
2542 target <<= 2;
d4a288ef 2543 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2544 goto jmp_insn;
2545 }
2546 case 0x6: /* FBN+x */
2547 {
5b12f1e8 2548 if (gen_trap_ifnofpu(dc)) {
a80dde08 2549 goto jmp_insn;
5b12f1e8 2550 }
0f8a249a
BS		 2551 target = GET_FIELD(insn, 10, 31);
2552 target = sign_extend(target, 22);
2553 target <<= 2;
d4a288ef 2554 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2555 goto jmp_insn;
2556 }
2557 case 0x4: /* SETHI */
97ea2859
RH		 2558 /* Special-case %g0 because that's the canonical nop. */
2559 if (rd) {
0f8a249a 2560 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2561 TCGv t = gen_dest_gpr(dc, rd);
2562 tcg_gen_movi_tl(t, value << 10);
2563 gen_store_gpr(dc, rd, t);
0f8a249a 2564 }
0f8a249a
BS		 2565 break;
2566 case 0x0: /* UNIMPL */
2567 default:
3475187d 2568 goto illegal_insn;
0f8a249a
BS		 2569 }
2570 break;
2571 }
2572 break;
dc1a6971
BS		 2573 case 1: /*CALL*/
2574 {
0f8a249a 2575 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2576 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2577
97ea2859
RH		 2578 tcg_gen_movi_tl(o7, dc->pc);
2579 gen_store_gpr(dc, 15, o7);
0f8a249a 2580 target += dc->pc;
13a6dd00 2581 gen_mov_pc_npc(dc);
22036a49
AT		 2582#ifdef TARGET_SPARC64
2583 if (unlikely(AM_CHECK(dc))) {
2584 target &= 0xffffffffULL;
2585 }
2586#endif
0f8a249a
BS		 2587 dc->npc = target;
2588 }
2589 goto jmp_insn;
2590 case 2: /* FPU & Logical Operations */
2591 {
2592 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2593 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2594 TCGv cpu_tmp0;
5793f2a4 2595
0f8a249a 2596 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2597 int cond = GET_FIELD(insn, 3, 6);
2598 TCGv_i32 trap;
42a268c2
RH		 2599 TCGLabel *l1 = NULL;
2600 int mask;
3475187d 2601
bd49ed41
RH		 2602 if (cond == 0) {
2603 /* Trap never. */
2604 break;
cf495bcf 2605 }
b04d9890 2606
bd49ed41 2607 save_state(dc);
b04d9890 2608
bd49ed41
RH		 2609 if (cond != 8) {
2610 /* Conditional trap. */
3a49e759 2611 DisasCompare cmp;
3475187d 2612#ifdef TARGET_SPARC64
0f8a249a
BS		 2613 /* V9 icc/xcc */
2614 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2615 if (cc == 0) {
2616 gen_compare(&cmp, 0, cond, dc);
2617 } else if (cc == 2) {
2618 gen_compare(&cmp, 1, cond, dc);
2619 } else {
0f8a249a 2620 goto illegal_insn;
3a49e759 2621 }
3475187d 2622#else
3a49e759 2623 gen_compare(&cmp, 0, cond, dc);
3475187d 2624#endif
b158a785 2625 l1 = gen_new_label();
3a49e759
RH		 2626 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2627 cmp.c1, cmp.c2, l1);
2628 free_compare(&cmp);
bd49ed41 2629 }
b158a785 2630
bd49ed41
RH		 2631 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2632 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2633
2634 /* Don't use the normal temporaries, as they may well have
2635 gone out of scope with the branch above. While we're
2636 doing that we might as well pre-truncate to 32-bit. */
2637 trap = tcg_temp_new_i32();
2638
2639 rs1 = GET_FIELD_SP(insn, 14, 18);
2640 if (IS_IMM) {
2641 rs2 = GET_FIELD_SP(insn, 0, 6);
2642 if (rs1 == 0) {
2643 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2644 /* Signal that the trap value is fully constant. */
2645 mask = 0;
2646 } else {
97ea2859 2647 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2648 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2649 tcg_gen_addi_i32(trap, trap, rs2);
2650 }
2651 } else {
97ea2859 2652 TCGv t1, t2;
bd49ed41 2653 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2654 t1 = gen_load_gpr(dc, rs1);
2655 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2656 tcg_gen_add_tl(t1, t1, t2);
2657 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2658 }
2659 if (mask != 0) {
2660 tcg_gen_andi_i32(trap, trap, mask);
2661 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2662 }
2663
2664 gen_helper_raise_exception(cpu_env, trap);
2665 tcg_temp_free_i32(trap);
b158a785 2666
fe1755cb
RH		 2667 if (cond == 8) {
2668 /* An unconditional trap ends the TB. */
2669 dc->is_br = 1;
2670 goto jmp_insn;
2671 } else {
2672 /* A conditional trap falls through to the next insn. */
b158a785 2673 gen_set_label(l1);
fe1755cb 2674 break;
cf495bcf
FB		 2675 }
2676 } else if (xop == 0x28) {
2677 rs1 = GET_FIELD(insn, 13, 17);
2678 switch(rs1) {
2679 case 0: /* rdy */
65fe7b09
BS		 2680#ifndef TARGET_SPARC64
2681 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2682 manual, rdy on the microSPARC
2683 II */
2684 case 0x0f: /* stbar in the SPARCv8 manual,
2685 rdy on the microSPARC II */
2686 case 0x10 ... 0x1f: /* implementation-dependent in the
2687 SPARCv8 manual, rdy on the
2688 microSPARC II */
4a2ba232
FC		 2689 /* Read Asr17 */
2690 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2691 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2692 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2693 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2694 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2695 break;
2696 }
65fe7b09 2697#endif
97ea2859 2698 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2699 break;
3475187d 2700#ifdef TARGET_SPARC64
0f8a249a 2701 case 0x2: /* V9 rdccr */
20132b96 2702 update_psr(dc);
063c3675 2703 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2704 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2705 break;
0f8a249a 2706 case 0x3: /* V9 rdasi */
255e1fcb 2707 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
97ea2859 2708 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2709 break;
0f8a249a 2710 case 0x4: /* V9 rdtick */
ccd4a219 2711 {
a7812ae4 2712 TCGv_ptr r_tickptr;
ccd4a219 2713
a7812ae4 2714 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2715 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2716 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 2717 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2718 tcg_temp_free_ptr(r_tickptr);
97ea2859 2719 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2720 }
3475187d 2721 break;
0f8a249a 2722 case 0x5: /* V9 rdpc */
2ea815ca 2723 {
97ea2859 2724 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2725 if (unlikely(AM_CHECK(dc))) {
97ea2859 2726 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2727 } else {
97ea2859 2728 tcg_gen_movi_tl(t, dc->pc);
22036a49 2729 }
97ea2859 2730 gen_store_gpr(dc, rd, t);
2ea815ca 2731 }
0f8a249a
BS		 2732 break;
2733 case 0x6: /* V9 rdfprs */
255e1fcb 2734 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2735 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2736 break;
65fe7b09
BS		 2737 case 0xf: /* V9 membar */
2738 break; /* no effect */
0f8a249a 2739 case 0x13: /* Graphics Status */
5b12f1e8 2740 if (gen_trap_ifnofpu(dc)) {
725cb90b 2741 goto jmp_insn;
5b12f1e8 2742 }
97ea2859 2743 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2744 break;
9d926598
BS		 2745 case 0x16: /* Softint */
2746 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
97ea2859 2747 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2748 break;
0f8a249a 2749 case 0x17: /* Tick compare */
97ea2859 2750 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2751 break;
0f8a249a 2752 case 0x18: /* System tick */
ccd4a219 2753 {
a7812ae4 2754 TCGv_ptr r_tickptr;
ccd4a219 2755
a7812ae4 2756 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2757 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2758 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 2759 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2760 tcg_temp_free_ptr(r_tickptr);
97ea2859 2761 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2762 }
83469015 2763 break;
0f8a249a 2764 case 0x19: /* System tick compare */
97ea2859 2765 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2766 break;
0f8a249a
BS		 2767 case 0x10: /* Performance Control */
2768 case 0x11: /* Performance Instrumentation Counter */
2769 case 0x12: /* Dispatch Control */
2770 case 0x14: /* Softint set, WO */
2771 case 0x15: /* Softint clear, WO */
3475187d
FB		 2772#endif
2773 default:
cf495bcf
FB		 2774 goto illegal_insn;
2775 }
e8af50a3 2776#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2777 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2778#ifndef TARGET_SPARC64
20132b96 2779 if (!supervisor(dc)) {
0f8a249a 2780 goto priv_insn;
20132b96
RH		 2781 }
2782 update_psr(dc);
063c3675 2783 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2784#else
fb79ceb9 2785 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2786 if (!hypervisor(dc))
2787 goto priv_insn;
2788 rs1 = GET_FIELD(insn, 13, 17);
2789 switch (rs1) {
2790 case 0: // hpstate
2791 // gen_op_rdhpstate();
2792 break;
2793 case 1: // htstate
2794 // gen_op_rdhtstate();
2795 break;
2796 case 3: // hintp
255e1fcb 2797 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2798 break;
2799 case 5: // htba
255e1fcb 2800 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2801 break;
2802 case 6: // hver
255e1fcb 2803 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2804 break;
2805 case 31: // hstick_cmpr
255e1fcb 2806 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2807 break;
2808 default:
2809 goto illegal_insn;
2810 }
2811#endif
97ea2859 2812 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2813 break;
3475187d 2814 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2815 if (!supervisor(dc)) {
0f8a249a 2816 goto priv_insn;
de9e9d9f
RH		 2817 }
2818 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2819#ifdef TARGET_SPARC64
2820 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2821 switch (rs1) {
2822 case 0: // tpc
375ee38b 2823 {
a7812ae4 2824 TCGv_ptr r_tsptr;
375ee38b 2825
a7812ae4 2826 r_tsptr = tcg_temp_new_ptr();
8194f35a 2827 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2828 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2829 offsetof(trap_state, tpc));
a7812ae4 2830 tcg_temp_free_ptr(r_tsptr);
375ee38b 2831 }
0f8a249a
BS		 2832 break;
2833 case 1: // tnpc
375ee38b 2834 {
a7812ae4 2835 TCGv_ptr r_tsptr;
375ee38b 2836
a7812ae4 2837 r_tsptr = tcg_temp_new_ptr();
8194f35a 2838 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2839 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2840 offsetof(trap_state, tnpc));
a7812ae4 2841 tcg_temp_free_ptr(r_tsptr);
375ee38b 2842 }
0f8a249a
BS		 2843 break;
2844 case 2: // tstate
375ee38b 2845 {
a7812ae4 2846 TCGv_ptr r_tsptr;
375ee38b 2847
a7812ae4 2848 r_tsptr = tcg_temp_new_ptr();
8194f35a 2849 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2850 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2851 offsetof(trap_state, tstate));
a7812ae4 2852 tcg_temp_free_ptr(r_tsptr);
375ee38b 2853 }
0f8a249a
BS		 2854 break;
2855 case 3: // tt
375ee38b 2856 {
45778f99 2857 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2858
8194f35a 2859 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2860 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2861 offsetof(trap_state, tt));
a7812ae4 2862 tcg_temp_free_ptr(r_tsptr);
375ee38b 2863 }
0f8a249a
BS		 2864 break;
2865 case 4: // tick
ccd4a219 2866 {
a7812ae4 2867 TCGv_ptr r_tickptr;
ccd4a219 2868
a7812ae4 2869 r_tickptr = tcg_temp_new_ptr();
ccd4a219 2870 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2871 offsetof(CPUSPARCState, tick));
a7812ae4 2872 gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
a7812ae4 2873 tcg_temp_free_ptr(r_tickptr);
ccd4a219 2874 }
0f8a249a
BS		 2875 break;
2876 case 5: // tba
255e1fcb 2877 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2878 break;
2879 case 6: // pstate
45778f99
RH		 2880 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2881 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2882 break;
2883 case 7: // tl
45778f99
RH		 2884 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2885 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 2886 break;
2887 case 8: // pil
45778f99
RH		 2888 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2889 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 2890 break;
2891 case 9: // cwp
063c3675 2892 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2893 break;
2894 case 10: // cansave
45778f99
RH		 2895 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2896 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 2897 break;
2898 case 11: // canrestore
45778f99
RH		 2899 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2900 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 2901 break;
2902 case 12: // cleanwin
45778f99
RH		 2903 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2904 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 2905 break;
2906 case 13: // otherwin
45778f99
RH		 2907 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2908 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 2909 break;
2910 case 14: // wstate
45778f99
RH		 2911 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2912 offsetof(CPUSPARCState, wstate));
0f8a249a 2913 break;
e9ebed4d 2914 case 16: // UA2005 gl
fb79ceb9 2915 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 2916 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2917 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 2918 break;
2919 case 26: // UA2005 strand status
fb79ceb9 2920 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2921 if (!hypervisor(dc))
2922 goto priv_insn;
527067d8 2923 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2924 break;
0f8a249a 2925 case 31: // ver
255e1fcb 2926 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2927 break;
2928 case 15: // fq
2929 default:
2930 goto illegal_insn;
2931 }
3475187d 2932#else
255e1fcb 2933 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2934#endif
97ea2859 2935 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 2936 break;
3475187d
FB		 2937 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2938#ifdef TARGET_SPARC64
66442b07 2939 save_state(dc);
063c3675 2940 gen_helper_flushw(cpu_env);
3475187d 2941#else
0f8a249a
BS		 2942 if (!supervisor(dc))
2943 goto priv_insn;
97ea2859 2944 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 2945#endif
e8af50a3
FB		 2946 break;
2947#endif
0f8a249a 2948 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 2949 if (gen_trap_ifnofpu(dc)) {
a80dde08 2950 goto jmp_insn;
5b12f1e8 2951 }
0f8a249a 2952 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2953 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2954 rs2 = GET_FIELD(insn, 27, 31);
2955 xop = GET_FIELD(insn, 18, 26);
66442b07 2956 save_state(dc);
0f8a249a 2957 switch (xop) {
dc1a6971 2958 case 0x1: /* fmovs */
208ae657
RH		 2959 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2960 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2961 break;
2962 case 0x5: /* fnegs */
61f17f6e 2963 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2964 break;
2965 case 0x9: /* fabss */
61f17f6e 2966 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2967 break;
2968 case 0x29: /* fsqrts */
2969 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2970 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2971 break;
2972 case 0x2a: /* fsqrtd */
2973 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2974 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2975 break;
2976 case 0x2b: /* fsqrtq */
2977 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2978 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2979 break;
2980 case 0x41: /* fadds */
61f17f6e 2981 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2982 break;
2983 case 0x42: /* faddd */
61f17f6e 2984 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2985 break;
2986 case 0x43: /* faddq */
2987 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2988 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2989 break;
2990 case 0x45: /* fsubs */
61f17f6e 2991 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2992 break;
2993 case 0x46: /* fsubd */
61f17f6e 2994 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 2995 break;
2996 case 0x47: /* fsubq */
2997 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2998 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 2999 break;
3000 case 0x49: /* fmuls */
3001 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3002 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3003 break;
3004 case 0x4a: /* fmuld */
3005 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3006 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3007 break;
3008 case 0x4b: /* fmulq */
3009 CHECK_FPU_FEATURE(dc, FLOAT128);
3010 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3011 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3012 break;
3013 case 0x4d: /* fdivs */
61f17f6e 3014 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3015 break;
3016 case 0x4e: /* fdivd */
61f17f6e 3017 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3018 break;
3019 case 0x4f: /* fdivq */
3020 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3021 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3022 break;
3023 case 0x69: /* fsmuld */
3024 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3025 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3026 break;
3027 case 0x6e: /* fdmulq */
3028 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3029 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3030 break;
3031 case 0xc4: /* fitos */
61f17f6e 3032 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3033 break;
3034 case 0xc6: /* fdtos */
61f17f6e 3035 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3036 break;
3037 case 0xc7: /* fqtos */
3038 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3039 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3040 break;
3041 case 0xc8: /* fitod */
61f17f6e 3042 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3043 break;
3044 case 0xc9: /* fstod */
61f17f6e 3045 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3046 break;
3047 case 0xcb: /* fqtod */
3048 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3049 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3050 break;
3051 case 0xcc: /* fitoq */
3052 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3053 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3054 break;
3055 case 0xcd: /* fstoq */
3056 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3057 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3058 break;
3059 case 0xce: /* fdtoq */
3060 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3061 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3062 break;
3063 case 0xd1: /* fstoi */
61f17f6e 3064 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3065 break;
3066 case 0xd2: /* fdtoi */
61f17f6e 3067 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3068 break;
3069 case 0xd3: /* fqtoi */
3070 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3071 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3072 break;
3475187d 3073#ifdef TARGET_SPARC64
dc1a6971 3074 case 0x2: /* V9 fmovd */
96eda024
RH		 3075 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3076 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3077 break;
3078 case 0x3: /* V9 fmovq */
3079 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3080 gen_move_Q(rd, rs2);
dc1a6971
BS		 3081 break;
3082 case 0x6: /* V9 fnegd */
61f17f6e 3083 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3084 break;
3085 case 0x7: /* V9 fnegq */
3086 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3087 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3088 break;
3089 case 0xa: /* V9 fabsd */
61f17f6e 3090 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3091 break;
3092 case 0xb: /* V9 fabsq */
3093 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3094 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3095 break;
3096 case 0x81: /* V9 fstox */
61f17f6e 3097 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3098 break;
3099 case 0x82: /* V9 fdtox */
61f17f6e 3100 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3101 break;
3102 case 0x83: /* V9 fqtox */
3103 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3104 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3105 break;
3106 case 0x84: /* V9 fxtos */
61f17f6e 3107 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3108 break;
3109 case 0x88: /* V9 fxtod */
61f17f6e 3110 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3111 break;
3112 case 0x8c: /* V9 fxtoq */
3113 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3114 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3115 break;
0f8a249a 3116#endif
dc1a6971
BS		 3117 default:
3118 goto illegal_insn;
0f8a249a
BS		 3119 }
3120 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3121#ifdef TARGET_SPARC64
0f8a249a 3122 int cond;
3475187d 3123#endif
5b12f1e8 3124 if (gen_trap_ifnofpu(dc)) {
a80dde08 3125 goto jmp_insn;
5b12f1e8 3126 }
0f8a249a 3127 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3128 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3129 rs2 = GET_FIELD(insn, 27, 31);
3130 xop = GET_FIELD(insn, 18, 26);
66442b07 3131 save_state(dc);
dcf24905 3132
690995a6
RH		 3133#ifdef TARGET_SPARC64
3134#define FMOVR(sz) \
3135 do { \
3136 DisasCompare cmp; \
e7c8afb9 3137 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3138 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3139 gen_compare_reg(&cmp, cond, cpu_src1); \
3140 gen_fmov##sz(dc, &cmp, rd, rs2); \
3141 free_compare(&cmp); \
3142 } while (0)
3143
3144 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3145 FMOVR(s);
0f8a249a
BS		 3146 break;
3147 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3148 FMOVR(d);
0f8a249a
BS		 3149 break;
3150 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3151 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3152 FMOVR(q);
1f587329 3153 break;
0f8a249a 3154 }
690995a6 3155#undef FMOVR
0f8a249a
BS		 3156#endif
3157 switch (xop) {
3475187d 3158#ifdef TARGET_SPARC64
7e480893
RH		 3159#define FMOVCC(fcc, sz) \
3160 do { \
3161 DisasCompare cmp; \
714547bb 3162 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3163 gen_fcompare(&cmp, fcc, cond); \
3164 gen_fmov##sz(dc, &cmp, rd, rs2); \
3165 free_compare(&cmp); \
3166 } while (0)
3167
0f8a249a 3168 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3169 FMOVCC(0, s);
0f8a249a
BS		 3170 break;
3171 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3172 FMOVCC(0, d);
0f8a249a
BS		 3173 break;
3174 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3175 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3176 FMOVCC(0, q);
1f587329 3177 break;
0f8a249a 3178 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3179 FMOVCC(1, s);
0f8a249a
BS		 3180 break;
3181 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3182 FMOVCC(1, d);
0f8a249a
BS		 3183 break;
3184 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3185 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3186 FMOVCC(1, q);
1f587329 3187 break;
0f8a249a 3188 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3189 FMOVCC(2, s);
0f8a249a
BS		 3190 break;
3191 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3192 FMOVCC(2, d);
0f8a249a
BS		 3193 break;
3194 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3195 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3196 FMOVCC(2, q);
1f587329 3197 break;
0f8a249a 3198 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3199 FMOVCC(3, s);
0f8a249a
BS		 3200 break;
3201 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3202 FMOVCC(3, d);
0f8a249a
BS		 3203 break;
3204 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3205 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3206 FMOVCC(3, q);
1f587329 3207 break;
7e480893
RH		 3208#undef FMOVCC
3209#define FMOVCC(xcc, sz) \
3210 do { \
3211 DisasCompare cmp; \
714547bb 3212 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3213 gen_compare(&cmp, xcc, cond, dc); \
3214 gen_fmov##sz(dc, &cmp, rd, rs2); \
3215 free_compare(&cmp); \
3216 } while (0)
19f329ad 3217
0f8a249a 3218 case 0x101: /* V9 fmovscc %icc */
7e480893 3219 FMOVCC(0, s);
0f8a249a
BS		 3220 break;
3221 case 0x102: /* V9 fmovdcc %icc */
7e480893 3222 FMOVCC(0, d);
b7d69dc2 3223 break;
0f8a249a 3224 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3225 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3226 FMOVCC(0, q);
1f587329 3227 break;
0f8a249a 3228 case 0x181: /* V9 fmovscc %xcc */
7e480893 3229 FMOVCC(1, s);
0f8a249a
BS		 3230 break;
3231 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3232 FMOVCC(1, d);
0f8a249a
BS		 3233 break;
3234 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3235 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3236 FMOVCC(1, q);
1f587329 3237 break;
7e480893 3238#undef FMOVCC
1f587329
BS		 3239#endif
3240 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3241 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3242 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3243 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3244 break;
1f587329 3245 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3246 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3247 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3248 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3249 break;
1f587329 3250 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3251 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3252 gen_op_load_fpr_QT0(QFPREG(rs1));
3253 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3254 gen_op_fcmpq(rd & 3);
1f587329 3255 break;
0f8a249a 3256 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3257 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3258 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3259 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3260 break;
3261 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3262 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3263 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3264 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3265 break;
1f587329 3266 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3267 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3268 gen_op_load_fpr_QT0(QFPREG(rs1));
3269 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3270 gen_op_fcmpeq(rd & 3);
1f587329 3271 break;
0f8a249a
BS		 3272 default:
3273 goto illegal_insn;
3274 }
0f8a249a 3275 } else if (xop == 0x2) {
97ea2859 3276 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3277 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3278 if (rs1 == 0) {
97ea2859 3279 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3280 if (IS_IMM) { /* immediate */
67526b20 3281 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3282 tcg_gen_movi_tl(dst, simm);
3283 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3284 } else { /* register */
3285 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3286 if (rs2 == 0) {
3287 tcg_gen_movi_tl(dst, 0);
3288 gen_store_gpr(dc, rd, dst);
3289 } else {
3290 cpu_src2 = gen_load_gpr(dc, rs2);
3291 gen_store_gpr(dc, rd, cpu_src2);
3292 }
0f8a249a 3293 }
0f8a249a 3294 } else {
9d1d4e34 3295 cpu_src1 = get_src1(dc, insn);
0f8a249a 3296 if (IS_IMM) { /* immediate */
67526b20 3297 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3298 tcg_gen_ori_tl(dst, cpu_src1, simm);
3299 gen_store_gpr(dc, rd, dst);
0f8a249a 3300 } else { /* register */
0f8a249a 3301 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3302 if (rs2 == 0) {
3303 /* mov shortcut: or x, %g0, y -> mov x, y */
3304 gen_store_gpr(dc, rd, cpu_src1);
3305 } else {
3306 cpu_src2 = gen_load_gpr(dc, rs2);
3307 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3308 gen_store_gpr(dc, rd, dst);
3309 }
0f8a249a 3310 }
0f8a249a 3311 }
83469015 3312#ifdef TARGET_SPARC64
0f8a249a 3313 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3314 cpu_src1 = get_src1(dc, insn);
0f8a249a 3315 if (IS_IMM) { /* immediate */
67526b20 3316 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3317 if (insn & (1 << 12)) {
67526b20 3318 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3319 } else {
67526b20 3320 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3321 }
0f8a249a 3322 } else { /* register */
83469015 3323 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3324 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3325 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3326 if (insn & (1 << 12)) {
6ae20372 3327 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3328 } else {
6ae20372 3329 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3330 }
01b1fa6d 3331 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3332 }
97ea2859 3333 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3334 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3335 cpu_src1 = get_src1(dc, insn);
0f8a249a 3336 if (IS_IMM) { /* immediate */
67526b20 3337 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3338 if (insn & (1 << 12)) {
67526b20 3339 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3340 } else {
6ae20372 3341 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3342 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3343 }
0f8a249a 3344 } else { /* register */
83469015 3345 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3346 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3347 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3348 if (insn & (1 << 12)) {
6ae20372
BS		 3349 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3350 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3351 } else {
6ae20372
BS		 3352 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3353 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3354 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3355 }
83469015 3356 }
97ea2859 3357 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3358 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3359 cpu_src1 = get_src1(dc, insn);
0f8a249a 3360 if (IS_IMM) { /* immediate */
67526b20 3361 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3362 if (insn & (1 << 12)) {
67526b20 3363 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3364 } else {
97ea2859 3365 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3366 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3367 }
0f8a249a 3368 } else { /* register */
83469015 3369 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3370 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3371 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3372 if (insn & (1 << 12)) {
6ae20372
BS		 3373 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3374 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3375 } else {
6ae20372 3376 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3377 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3378 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3379 }
83469015 3380 }
97ea2859 3381 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3382#endif
fcc72045 3383 } else if (xop < 0x36) {
cf495bcf 3384 if (xop < 0x20) {
9d1d4e34
RH		 3385 cpu_src1 = get_src1(dc, insn);
3386 cpu_src2 = get_src2(dc, insn);
cf495bcf 3387 switch (xop & ~0x10) {
b89e94af 3388 case 0x0: /* add */
97ea2859
RH		 3389 if (xop & 0x10) {
3390 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3391 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3392 dc->cc_op = CC_OP_ADD;
41d72852 3393 } else {
97ea2859 3394 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3395 }
cf495bcf 3396 break;
b89e94af 3397 case 0x1: /* and */
97ea2859 3398 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3399 if (xop & 0x10) {
38482a77
BS		 3400 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3401 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3402 dc->cc_op = CC_OP_LOGIC;
41d72852 3403 }
cf495bcf 3404 break;
b89e94af 3405 case 0x2: /* or */
97ea2859 3406 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3407 if (xop & 0x10) {
38482a77
BS		 3408 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3409 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3410 dc->cc_op = CC_OP_LOGIC;
8393617c 3411 }
0f8a249a 3412 break;
b89e94af 3413 case 0x3: /* xor */
97ea2859 3414 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3415 if (xop & 0x10) {
38482a77
BS		 3416 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3417 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3418 dc->cc_op = CC_OP_LOGIC;
8393617c 3419 }
cf495bcf 3420 break;
b89e94af 3421 case 0x4: /* sub */
97ea2859
RH		 3422 if (xop & 0x10) {
3423 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3424 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3425 dc->cc_op = CC_OP_SUB;
41d72852 3426 } else {
97ea2859 3427 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3428 }
cf495bcf 3429 break;
b89e94af 3430 case 0x5: /* andn */
97ea2859 3431 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3432 if (xop & 0x10) {
38482a77
BS		 3433 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3434 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3435 dc->cc_op = CC_OP_LOGIC;
8393617c 3436 }
cf495bcf 3437 break;
b89e94af 3438 case 0x6: /* orn */
97ea2859 3439 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3440 if (xop & 0x10) {
38482a77
BS		 3441 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3442 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3443 dc->cc_op = CC_OP_LOGIC;
8393617c 3444 }
cf495bcf 3445 break;
b89e94af 3446 case 0x7: /* xorn */
97ea2859 3447 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3448 if (xop & 0x10) {
38482a77
BS		 3449 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3450 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3451 dc->cc_op = CC_OP_LOGIC;
8393617c 3452 }
cf495bcf 3453 break;
b89e94af 3454 case 0x8: /* addx, V9 addc */
70c48285
RH		 3455 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3456 (xop & 0x10));
cf495bcf 3457 break;
ded3ab80 3458#ifdef TARGET_SPARC64
0f8a249a 3459 case 0x9: /* V9 mulx */
97ea2859 3460 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3461 break;
3462#endif
b89e94af 3463 case 0xa: /* umul */
64a88d5d 3464 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3465 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3466 if (xop & 0x10) {
38482a77
BS		 3467 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3468 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3469 dc->cc_op = CC_OP_LOGIC;
8393617c 3470 }
cf495bcf 3471 break;
b89e94af 3472 case 0xb: /* smul */
64a88d5d 3473 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3474 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3475 if (xop & 0x10) {
38482a77
BS		 3476 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3477 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3478 dc->cc_op = CC_OP_LOGIC;
8393617c 3479 }
cf495bcf 3480 break;
b89e94af 3481 case 0xc: /* subx, V9 subc */
70c48285
RH		 3482 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3483 (xop & 0x10));
cf495bcf 3484 break;
ded3ab80 3485#ifdef TARGET_SPARC64
0f8a249a 3486 case 0xd: /* V9 udivx */
c28ae41e 3487 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3488 break;
3489#endif
b89e94af 3490 case 0xe: /* udiv */
64a88d5d 3491 CHECK_IU_FEATURE(dc, DIV);
8393617c 3492 if (xop & 0x10) {
7a5e4488
BS		 3493 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3494 cpu_src2);
6c78ea32 3495 dc->cc_op = CC_OP_DIV;
0fcec41e 3496 } else {
7a5e4488
BS		 3497 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3498 cpu_src2);
8393617c 3499 }
cf495bcf 3500 break;
b89e94af 3501 case 0xf: /* sdiv */
64a88d5d 3502 CHECK_IU_FEATURE(dc, DIV);
8393617c 3503 if (xop & 0x10) {
7a5e4488
BS		 3504 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3505 cpu_src2);
6c78ea32 3506 dc->cc_op = CC_OP_DIV;
0fcec41e 3507 } else {
7a5e4488
BS		 3508 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3509 cpu_src2);
8393617c 3510 }
cf495bcf
FB		 3511 break;
3512 default:
3513 goto illegal_insn;
3514 }
97ea2859 3515 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3516 } else {
9d1d4e34
RH		 3517 cpu_src1 = get_src1(dc, insn);
3518 cpu_src2 = get_src2(dc, insn);
cf495bcf 3519 switch (xop) {
0f8a249a 3520 case 0x20: /* taddcc */
a2ea4aa9 3521 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3522 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3523 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3524 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3525 break;
3526 case 0x21: /* tsubcc */
a2ea4aa9 3527 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3528 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3529 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3530 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3531 break;
3532 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3533 gen_helper_taddcctv(cpu_dst, cpu_env,
3534 cpu_src1, cpu_src2);
97ea2859 3535 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3536 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3537 break;
3538 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3539 gen_helper_tsubcctv(cpu_dst, cpu_env,
3540 cpu_src1, cpu_src2);
97ea2859 3541 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3542 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3543 break;
cf495bcf 3544 case 0x24: /* mulscc */
20132b96 3545 update_psr(dc);
6ae20372 3546 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3547 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3548 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3549 dc->cc_op = CC_OP_ADD;
cf495bcf 3550 break;
83469015 3551#ifndef TARGET_SPARC64
0f8a249a 3552 case 0x25: /* sll */
e35298cd 3553 if (IS_IMM) { /* immediate */
67526b20
BS		 3554 simm = GET_FIELDs(insn, 20, 31);
3555 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3556 } else { /* register */
de9e9d9f 3557 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3558 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3559 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3560 }
97ea2859 3561 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3562 break;
83469015 3563 case 0x26: /* srl */
e35298cd 3564 if (IS_IMM) { /* immediate */
67526b20
BS		 3565 simm = GET_FIELDs(insn, 20, 31);
3566 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3567 } else { /* register */
de9e9d9f 3568 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3569 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3570 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3571 }
97ea2859 3572 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3573 break;
83469015 3574 case 0x27: /* sra */
e35298cd 3575 if (IS_IMM) { /* immediate */
67526b20
BS		 3576 simm = GET_FIELDs(insn, 20, 31);
3577 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3578 } else { /* register */
de9e9d9f 3579 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3580 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3581 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3582 }
97ea2859 3583 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3584 break;
83469015 3585#endif
cf495bcf
FB		 3586 case 0x30:
3587 {
de9e9d9f 3588 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3589 switch(rd) {
3475187d 3590 case 0: /* wry */
5068cbd9
BS		 3591 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3592 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3593 break;
65fe7b09
BS		 3594#ifndef TARGET_SPARC64
3595 case 0x01 ... 0x0f: /* undefined in the
3596 SPARCv8 manual, nop
3597 on the microSPARC
3598 II */
3599 case 0x10 ... 0x1f: /* implementation-dependent
3600 in the SPARCv8
3601 manual, nop on the
3602 microSPARC II */
d1c36ba7
RH		 3603 if ((rd == 0x13) && (dc->def->features &
3604 CPU_FEATURE_POWERDOWN)) {
3605 /* LEON3 power-down */
1cf892ca 3606 save_state(dc);
d1c36ba7
RH		 3607 gen_helper_power_down(cpu_env);
3608 }
65fe7b09
BS		 3609 break;
3610#else
0f8a249a 3611 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3612 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3613 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3614 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3615 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3616 break;
3617 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3618 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3619 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
3620 tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
0f8a249a
BS		 3621 break;
3622 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3623 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3624 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3625 save_state(dc);
3299908c 3626 gen_op_next_insn();
57fec1fe 3627 tcg_gen_exit_tb(0);
3299908c 3628 dc->is_br = 1;
0f8a249a
BS		 3629 break;
3630 case 0xf: /* V9 sir, nop if user */
3475187d 3631#if !defined(CONFIG_USER_ONLY)
6ad6135d 3632 if (supervisor(dc)) {
1a2fb1c0 3633 ; // XXX
6ad6135d 3634 }
3475187d 3635#endif
0f8a249a
BS		 3636 break;
3637 case 0x13: /* Graphics Status */
5b12f1e8 3638 if (gen_trap_ifnofpu(dc)) {
725cb90b 3639 goto jmp_insn;
5b12f1e8 3640 }
255e1fcb 3641 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3642 break;
9d926598
BS		 3643 case 0x14: /* Softint set */
3644 if (!supervisor(dc))
3645 goto illegal_insn;
aeff993c
RH		 3646 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3647 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3648 break;
3649 case 0x15: /* Softint clear */
3650 if (!supervisor(dc))
3651 goto illegal_insn;
aeff993c
RH		 3652 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3653 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3654 break;
3655 case 0x16: /* Softint write */
3656 if (!supervisor(dc))
3657 goto illegal_insn;
aeff993c
RH		 3658 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3659 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3660 break;
0f8a249a 3661 case 0x17: /* Tick compare */
83469015 3662#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3663 if (!supervisor(dc))
3664 goto illegal_insn;
83469015 3665#endif
ccd4a219 3666 {
a7812ae4 3667 TCGv_ptr r_tickptr;
ccd4a219 3668
255e1fcb 3669 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3670 cpu_src2);
a7812ae4 3671 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3672 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3673 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3674 gen_helper_tick_set_limit(r_tickptr,
3675 cpu_tick_cmpr);
3676 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3677 }
0f8a249a
BS		 3678 break;
3679 case 0x18: /* System tick */
83469015 3680#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3681 if (!supervisor(dc))
3682 goto illegal_insn;
83469015 3683#endif
ccd4a219 3684 {
a7812ae4 3685 TCGv_ptr r_tickptr;
ccd4a219 3686
7b04bd5c 3687 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3688 cpu_src2);
a7812ae4 3689 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3690 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3691 offsetof(CPUSPARCState, stick));
a7812ae4 3692 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3693 cpu_tmp0);
a7812ae4 3694 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3695 }
0f8a249a
BS		 3696 break;
3697 case 0x19: /* System tick compare */
83469015 3698#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3699 if (!supervisor(dc))
3700 goto illegal_insn;
3475187d 3701#endif
ccd4a219 3702 {
a7812ae4 3703 TCGv_ptr r_tickptr;
ccd4a219 3704
255e1fcb 3705 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3706 cpu_src2);
a7812ae4 3707 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3708 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3709 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3710 gen_helper_tick_set_limit(r_tickptr,
3711 cpu_stick_cmpr);
3712 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3713 }
0f8a249a 3714 break;
83469015 3715
0f8a249a 3716 case 0x10: /* Performance Control */
77f193da
BS		 3717 case 0x11: /* Performance Instrumentation
3718 Counter */
0f8a249a 3719 case 0x12: /* Dispatch Control */
83469015 3720#endif
3475187d 3721 default:
cf495bcf
FB		 3722 goto illegal_insn;
3723 }
3724 }
3725 break;
e8af50a3 3726#if !defined(CONFIG_USER_ONLY)
af7bf89b 3727 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3728 {
0f8a249a
BS		 3729 if (!supervisor(dc))
3730 goto priv_insn;
3475187d 3731#ifdef TARGET_SPARC64
0f8a249a
BS		 3732 switch (rd) {
3733 case 0:
063c3675 3734 gen_helper_saved(cpu_env);
0f8a249a
BS		 3735 break;
3736 case 1:
063c3675 3737 gen_helper_restored(cpu_env);
0f8a249a 3738 break;
e9ebed4d
BS		 3739 case 2: /* UA2005 allclean */
3740 case 3: /* UA2005 otherw */
3741 case 4: /* UA2005 normalw */
3742 case 5: /* UA2005 invalw */
3743 // XXX
0f8a249a 3744 default:
3475187d
FB		 3745 goto illegal_insn;
3746 }
3747#else
de9e9d9f 3748 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3749 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3750 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3751 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3752 dc->cc_op = CC_OP_FLAGS;
66442b07 3753 save_state(dc);
9e61bde5 3754 gen_op_next_insn();
57fec1fe 3755 tcg_gen_exit_tb(0);
0f8a249a 3756 dc->is_br = 1;
3475187d 3757#endif
e8af50a3
FB		 3758 }
3759 break;
af7bf89b 3760 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3761 {
0f8a249a
BS		 3762 if (!supervisor(dc))
3763 goto priv_insn;
de9e9d9f 3764 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3765 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3766#ifdef TARGET_SPARC64
0f8a249a
BS		 3767 switch (rd) {
3768 case 0: // tpc
375ee38b 3769 {
a7812ae4 3770 TCGv_ptr r_tsptr;
375ee38b 3771
a7812ae4 3772 r_tsptr = tcg_temp_new_ptr();
8194f35a 3773 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3774 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3775 offsetof(trap_state, tpc));
a7812ae4 3776 tcg_temp_free_ptr(r_tsptr);
375ee38b 3777 }
0f8a249a
BS		 3778 break;
3779 case 1: // tnpc
375ee38b 3780 {
a7812ae4 3781 TCGv_ptr r_tsptr;
375ee38b 3782
a7812ae4 3783 r_tsptr = tcg_temp_new_ptr();
8194f35a 3784 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3785 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3786 offsetof(trap_state, tnpc));
a7812ae4 3787 tcg_temp_free_ptr(r_tsptr);
375ee38b 3788 }
0f8a249a
BS		 3789 break;
3790 case 2: // tstate
375ee38b 3791 {
a7812ae4 3792 TCGv_ptr r_tsptr;
375ee38b 3793
a7812ae4 3794 r_tsptr = tcg_temp_new_ptr();
8194f35a 3795 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3796 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3797 offsetof(trap_state,
3798 tstate));
a7812ae4 3799 tcg_temp_free_ptr(r_tsptr);
375ee38b 3800 }
0f8a249a
BS		 3801 break;
3802 case 3: // tt
375ee38b 3803 {
a7812ae4 3804 TCGv_ptr r_tsptr;
375ee38b 3805
a7812ae4 3806 r_tsptr = tcg_temp_new_ptr();
8194f35a 3807 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3808 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3809 offsetof(trap_state, tt));
a7812ae4 3810 tcg_temp_free_ptr(r_tsptr);
375ee38b 3811 }
0f8a249a
BS		 3812 break;
3813 case 4: // tick
ccd4a219 3814 {
a7812ae4 3815 TCGv_ptr r_tickptr;
ccd4a219 3816
a7812ae4 3817 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3818 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3819 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3820 gen_helper_tick_set_count(r_tickptr,
3821 cpu_tmp0);
3822 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3823 }
0f8a249a
BS		 3824 break;
3825 case 5: // tba
255e1fcb 3826 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3827 break;
3828 case 6: // pstate
6234ac09
RH		 3829 save_state(dc);
3830 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3831 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3832 break;
3833 case 7: // tl
6234ac09 3834 save_state(dc);
7b9e066b 3835 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3836 offsetof(CPUSPARCState, tl));
3837 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3838 break;
3839 case 8: // pil
063c3675 3840 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3841 break;
3842 case 9: // cwp
063c3675 3843 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3844 break;
3845 case 10: // cansave
7b9e066b
RH		 3846 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3847 offsetof(CPUSPARCState,
3848 cansave));
0f8a249a
BS		 3849 break;
3850 case 11: // canrestore
7b9e066b
RH		 3851 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3852 offsetof(CPUSPARCState,
3853 canrestore));
0f8a249a
BS		 3854 break;
3855 case 12: // cleanwin
7b9e066b
RH		 3856 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3857 offsetof(CPUSPARCState,
3858 cleanwin));
0f8a249a
BS		 3859 break;
3860 case 13: // otherwin
7b9e066b
RH		 3861 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3862 offsetof(CPUSPARCState,
3863 otherwin));
0f8a249a
BS		 3864 break;
3865 case 14: // wstate
7b9e066b
RH		 3866 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3867 offsetof(CPUSPARCState,
3868 wstate));
0f8a249a 3869 break;
e9ebed4d 3870 case 16: // UA2005 gl
fb79ceb9 3871 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 3872 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3873 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3874 break;
3875 case 26: // UA2005 strand status
fb79ceb9 3876 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3877 if (!hypervisor(dc))
3878 goto priv_insn;
527067d8 3879 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3880 break;
0f8a249a
BS		 3881 default:
3882 goto illegal_insn;
3883 }
3475187d 3884#else
7b9e066b
RH		 3885 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3886 if (dc->def->nwindows != 32) {
3887 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 3888 (1 << dc->def->nwindows) - 1);
7b9e066b 3889 }
3475187d 3890#endif
e8af50a3
FB		 3891 }
3892 break;
e9ebed4d 3893 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3894 {
e9ebed4d 3895#ifndef TARGET_SPARC64
0f8a249a
BS		 3896 if (!supervisor(dc))
3897 goto priv_insn;
255e1fcb 3898 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3899#else
fb79ceb9 3900 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3901 if (!hypervisor(dc))
3902 goto priv_insn;
de9e9d9f 3903 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3904 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3905 switch (rd) {
3906 case 0: // hpstate
3907 // XXX gen_op_wrhpstate();
66442b07 3908 save_state(dc);
e9ebed4d 3909 gen_op_next_insn();
57fec1fe 3910 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3911 dc->is_br = 1;
3912 break;
3913 case 1: // htstate
3914 // XXX gen_op_wrhtstate();
3915 break;
3916 case 3: // hintp
255e1fcb 3917 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3918 break;
3919 case 5: // htba
255e1fcb 3920 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3921 break;
3922 case 31: // hstick_cmpr
ccd4a219 3923 {
a7812ae4 3924 TCGv_ptr r_tickptr;
ccd4a219 3925
255e1fcb 3926 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3927 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3928 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3929 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 3930 gen_helper_tick_set_limit(r_tickptr,
3931 cpu_hstick_cmpr);
3932 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3933 }
e9ebed4d
BS		 3934 break;
3935 case 6: // hver readonly
3936 default:
3937 goto illegal_insn;
3938 }
3939#endif
e8af50a3
FB		 3940 }
3941 break;
3942#endif
3475187d 3943#ifdef TARGET_SPARC64
0f8a249a
BS		 3944 case 0x2c: /* V9 movcc */
3945 {
3946 int cc = GET_FIELD_SP(insn, 11, 12);
3947 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 3948 DisasCompare cmp;
97ea2859 3949 TCGv dst;
00f219bf 3950
0f8a249a 3951 if (insn & (1 << 18)) {
f52879b4
RH		 3952 if (cc == 0) {
3953 gen_compare(&cmp, 0, cond, dc);
3954 } else if (cc == 2) {
3955 gen_compare(&cmp, 1, cond, dc);
3956 } else {
0f8a249a 3957 goto illegal_insn;
f52879b4 3958 }
0f8a249a 3959 } else {
f52879b4 3960 gen_fcompare(&cmp, cc, cond);
0f8a249a 3961 }
00f219bf 3962
f52879b4
RH		 3963 /* The get_src2 above loaded the normal 13-bit
3964 immediate field, not the 11-bit field we have
3965 in movcc. But it did handle the reg case. */
3966 if (IS_IMM) {
67526b20 3967 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 3968 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 3969 }
f52879b4 3970
97ea2859
RH		 3971 dst = gen_load_gpr(dc, rd);
3972 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 3973 cmp.c1, cmp.c2,
97ea2859 3974 cpu_src2, dst);
f52879b4 3975 free_compare(&cmp);
97ea2859 3976 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3977 break;
3978 }
3979 case 0x2d: /* V9 sdivx */
c28ae41e 3980 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 3981 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 3982 break;
3983 case 0x2e: /* V9 popc */
97ea2859
RH		 3984 gen_helper_popc(cpu_dst, cpu_src2);
3985 gen_store_gpr(dc, rd, cpu_dst);
3986 break;
0f8a249a
BS		 3987 case 0x2f: /* V9 movr */
3988 {
3989 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 3990 DisasCompare cmp;
97ea2859 3991 TCGv dst;
00f219bf 3992
c33f80f5 3993 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 3994
c33f80f5
RH		 3995 /* The get_src2 above loaded the normal 13-bit
3996 immediate field, not the 10-bit field we have
3997 in movr. But it did handle the reg case. */
3998 if (IS_IMM) {
67526b20 3999 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4000 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4001 }
c33f80f5 4002
97ea2859
RH		 4003 dst = gen_load_gpr(dc, rd);
4004 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4005 cmp.c1, cmp.c2,
97ea2859 4006 cpu_src2, dst);
c33f80f5 4007 free_compare(&cmp);
97ea2859 4008 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4009 break;
4010 }
4011#endif
4012 default:
4013 goto illegal_insn;
4014 }
4015 }
3299908c
BS		 4016 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4017#ifdef TARGET_SPARC64
4018 int opf = GET_FIELD_SP(insn, 5, 13);
4019 rs1 = GET_FIELD(insn, 13, 17);
4020 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4021 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4022 goto jmp_insn;
5b12f1e8 4023 }
3299908c
BS		 4024
4025 switch (opf) {
e9ebed4d 4026 case 0x000: /* VIS I edge8cc */
6c073553 4027 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4028 cpu_src1 = gen_load_gpr(dc, rs1);
4029 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4030 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4031 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4032 break;
e9ebed4d 4033 case 0x001: /* VIS II edge8n */
6c073553 4034 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4035 cpu_src1 = gen_load_gpr(dc, rs1);
4036 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4037 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4038 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4039 break;
e9ebed4d 4040 case 0x002: /* VIS I edge8lcc */
6c073553 4041 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4042 cpu_src1 = gen_load_gpr(dc, rs1);
4043 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4044 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4045 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4046 break;
e9ebed4d 4047 case 0x003: /* VIS II edge8ln */
6c073553 4048 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4049 cpu_src1 = gen_load_gpr(dc, rs1);
4050 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4051 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4052 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4053 break;
e9ebed4d 4054 case 0x004: /* VIS I edge16cc */
6c073553 4055 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4056 cpu_src1 = gen_load_gpr(dc, rs1);
4057 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4058 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4059 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4060 break;
e9ebed4d 4061 case 0x005: /* VIS II edge16n */
6c073553 4062 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4063 cpu_src1 = gen_load_gpr(dc, rs1);
4064 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4065 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4066 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4067 break;
e9ebed4d 4068 case 0x006: /* VIS I edge16lcc */
6c073553 4069 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4070 cpu_src1 = gen_load_gpr(dc, rs1);
4071 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4072 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4073 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4074 break;
e9ebed4d 4075 case 0x007: /* VIS II edge16ln */
6c073553 4076 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4077 cpu_src1 = gen_load_gpr(dc, rs1);
4078 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4079 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4080 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4081 break;
e9ebed4d 4082 case 0x008: /* VIS I edge32cc */
6c073553 4083 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4084 cpu_src1 = gen_load_gpr(dc, rs1);
4085 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4086 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4087 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4088 break;
e9ebed4d 4089 case 0x009: /* VIS II edge32n */
6c073553 4090 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4091 cpu_src1 = gen_load_gpr(dc, rs1);
4092 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4093 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4094 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4095 break;
e9ebed4d 4096 case 0x00a: /* VIS I edge32lcc */
6c073553 4097 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4098 cpu_src1 = gen_load_gpr(dc, rs1);
4099 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4100 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4101 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4102 break;
e9ebed4d 4103 case 0x00b: /* VIS II edge32ln */
6c073553 4104 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4105 cpu_src1 = gen_load_gpr(dc, rs1);
4106 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4107 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4108 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4109 break;
e9ebed4d 4110 case 0x010: /* VIS I array8 */
64a88d5d 4111 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4112 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4113 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4114 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4115 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4116 break;
4117 case 0x012: /* VIS I array16 */
64a88d5d 4118 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4119 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4120 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4121 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4122 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4123 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4124 break;
4125 case 0x014: /* VIS I array32 */
64a88d5d 4126 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4127 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4128 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4129 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4130 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4131 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4132 break;
3299908c 4133 case 0x018: /* VIS I alignaddr */
64a88d5d 4134 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4135 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4136 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4137 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4138 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4139 break;
4140 case 0x01a: /* VIS I alignaddrl */
add545ab 4141 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4142 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4143 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4144 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4145 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4146 break;
4147 case 0x019: /* VIS II bmask */
793a137a 4148 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4149 cpu_src1 = gen_load_gpr(dc, rs1);
4150 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4151 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4152 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4153 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4154 break;
e9ebed4d 4155 case 0x020: /* VIS I fcmple16 */
64a88d5d 4156 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4157 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4158 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4159 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4160 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4161 break;
4162 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4163 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4164 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4165 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4166 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4167 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4168 break;
e9ebed4d 4169 case 0x024: /* VIS I fcmple32 */
64a88d5d 4170 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4171 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4172 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4173 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4174 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4175 break;
4176 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4177 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4178 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4179 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4180 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4181 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4182 break;
4183 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4184 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4185 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4186 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4187 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4188 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4189 break;
4190 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4191 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4192 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4193 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4194 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4195 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4196 break;
4197 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4198 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4199 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4200 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4201 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4202 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4203 break;
4204 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4205 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4206 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4207 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4208 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4209 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4210 break;
4211 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4212 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4213 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4214 break;
4215 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4216 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4217 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4218 break;
4219 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4220 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4221 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4222 break;
4223 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4224 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4225 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4226 break;
4227 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4228 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4229 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4230 break;
4231 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4232 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4233 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4234 break;
4235 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4236 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4237 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4238 break;
4239 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4240 CHECK_FPU_FEATURE(dc, VIS1);
4241 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4242 break;
e9ebed4d 4243 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4244 CHECK_FPU_FEATURE(dc, VIS1);
4245 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4246 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4247 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4248 gen_store_fpr_F(dc, rd, cpu_dst_32);
4249 break;
e9ebed4d 4250 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4251 CHECK_FPU_FEATURE(dc, VIS1);
4252 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4253 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4254 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4255 gen_store_fpr_F(dc, rd, cpu_dst_32);
4256 break;
f888300b
RH		 4257 case 0x03e: /* VIS I pdist */
4258 CHECK_FPU_FEATURE(dc, VIS1);
4259 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4260 break;
3299908c 4261 case 0x048: /* VIS I faligndata */
64a88d5d 4262 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4263 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4264 break;
e9ebed4d 4265 case 0x04b: /* VIS I fpmerge */
64a88d5d 4266 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4267 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4268 break;
4269 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4270 CHECK_FPU_FEATURE(dc, VIS2);
4271 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4272 break;
e9ebed4d 4273 case 0x04d: /* VIS I fexpand */
64a88d5d 4274 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4275 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4276 break;
4277 case 0x050: /* VIS I fpadd16 */
64a88d5d 4278 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4279 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4280 break;
4281 case 0x051: /* VIS I fpadd16s */
64a88d5d 4282 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4283 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4284 break;
4285 case 0x052: /* VIS I fpadd32 */
64a88d5d 4286 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4287 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4288 break;
4289 case 0x053: /* VIS I fpadd32s */
64a88d5d 4290 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4291 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4292 break;
4293 case 0x054: /* VIS I fpsub16 */
64a88d5d 4294 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4295 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4296 break;
4297 case 0x055: /* VIS I fpsub16s */
64a88d5d 4298 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4299 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4300 break;
4301 case 0x056: /* VIS I fpsub32 */
64a88d5d 4302 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4303 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4304 break;
4305 case 0x057: /* VIS I fpsub32s */
64a88d5d 4306 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4307 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4308 break;
3299908c 4309 case 0x060: /* VIS I fzero */
64a88d5d 4310 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4311 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4312 tcg_gen_movi_i64(cpu_dst_64, 0);
4313 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4314 break;
4315 case 0x061: /* VIS I fzeros */
64a88d5d 4316 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4317 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4318 tcg_gen_movi_i32(cpu_dst_32, 0);
4319 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4320 break;
e9ebed4d 4321 case 0x062: /* VIS I fnor */
64a88d5d 4322 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4323 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4324 break;
4325 case 0x063: /* VIS I fnors */
64a88d5d 4326 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4327 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4328 break;
4329 case 0x064: /* VIS I fandnot2 */
64a88d5d 4330 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4331 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4332 break;
4333 case 0x065: /* VIS I fandnot2s */
64a88d5d 4334 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4335 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4336 break;
4337 case 0x066: /* VIS I fnot2 */
64a88d5d 4338 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4339 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4340 break;
4341 case 0x067: /* VIS I fnot2s */
64a88d5d 4342 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4343 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4344 break;
4345 case 0x068: /* VIS I fandnot1 */
64a88d5d 4346 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4347 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4348 break;
4349 case 0x069: /* VIS I fandnot1s */
64a88d5d 4350 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4351 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4352 break;
4353 case 0x06a: /* VIS I fnot1 */
64a88d5d 4354 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4355 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4356 break;
4357 case 0x06b: /* VIS I fnot1s */
64a88d5d 4358 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4359 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4360 break;
4361 case 0x06c: /* VIS I fxor */
64a88d5d 4362 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4363 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4364 break;
4365 case 0x06d: /* VIS I fxors */
64a88d5d 4366 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4367 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4368 break;
4369 case 0x06e: /* VIS I fnand */
64a88d5d 4370 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4371 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4372 break;
4373 case 0x06f: /* VIS I fnands */
64a88d5d 4374 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4375 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4376 break;
4377 case 0x070: /* VIS I fand */
64a88d5d 4378 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4379 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4380 break;
4381 case 0x071: /* VIS I fands */
64a88d5d 4382 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4383 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4384 break;
4385 case 0x072: /* VIS I fxnor */
64a88d5d 4386 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4387 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4388 break;
4389 case 0x073: /* VIS I fxnors */
64a88d5d 4390 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4391 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4392 break;
3299908c 4393 case 0x074: /* VIS I fsrc1 */
64a88d5d 4394 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4395 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4396 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4397 break;
4398 case 0x075: /* VIS I fsrc1s */
64a88d5d 4399 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4400 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4401 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4402 break;
e9ebed4d 4403 case 0x076: /* VIS I fornot2 */
64a88d5d 4404 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4405 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4406 break;
4407 case 0x077: /* VIS I fornot2s */
64a88d5d 4408 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4409 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4410 break;
3299908c 4411 case 0x078: /* VIS I fsrc2 */
64a88d5d 4412 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4413 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4414 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4415 break;
4416 case 0x079: /* VIS I fsrc2s */
64a88d5d 4417 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4418 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4419 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4420 break;
e9ebed4d 4421 case 0x07a: /* VIS I fornot1 */
64a88d5d 4422 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4423 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4424 break;
4425 case 0x07b: /* VIS I fornot1s */
64a88d5d 4426 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4427 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4428 break;
4429 case 0x07c: /* VIS I for */
64a88d5d 4430 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4431 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4432 break;
4433 case 0x07d: /* VIS I fors */
64a88d5d 4434 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4435 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4436 break;
3299908c 4437 case 0x07e: /* VIS I fone */
64a88d5d 4438 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4439 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4440 tcg_gen_movi_i64(cpu_dst_64, -1);
4441 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4442 break;
4443 case 0x07f: /* VIS I fones */
64a88d5d 4444 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4445 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4446 tcg_gen_movi_i32(cpu_dst_32, -1);
4447 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4448 break;
e9ebed4d
BS		 4449 case 0x080: /* VIS I shutdown */
4450 case 0x081: /* VIS II siam */
4451 // XXX
4452 goto illegal_insn;
3299908c
BS		 4453 default:
4454 goto illegal_insn;
4455 }
4456#else
0f8a249a 4457 goto ncp_insn;
3299908c
BS		 4458#endif
4459 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4460#ifdef TARGET_SPARC64
0f8a249a 4461 goto illegal_insn;
fcc72045 4462#else
0f8a249a 4463 goto ncp_insn;
fcc72045 4464#endif
3475187d 4465#ifdef TARGET_SPARC64
0f8a249a 4466 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4467 TCGv_i32 r_const;
2ea815ca 4468
66442b07 4469 save_state(dc);
9d1d4e34 4470 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4471 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4472 if (IS_IMM) { /* immediate */
67526b20 4473 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4474 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4475 } else { /* register */
3475187d 4476 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4477 if (rs2) {
97ea2859 4478 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4479 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4480 } else {
7b04bd5c 4481 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4482 }
3475187d 4483 }
063c3675 4484 gen_helper_restore(cpu_env);
13a6dd00 4485 gen_mov_pc_npc(dc);
2ea815ca 4486 r_const = tcg_const_i32(3);
7b04bd5c 4487 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4488 tcg_temp_free_i32(r_const);
7b04bd5c 4489 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4490 dc->npc = DYNAMIC_PC;
4491 goto jmp_insn;
3475187d 4492#endif
0f8a249a 4493 } else {
9d1d4e34 4494 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4495 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4496 if (IS_IMM) { /* immediate */
67526b20 4497 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4498 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4499 } else { /* register */
e80cfcfc 4500 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4501 if (rs2) {
97ea2859 4502 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4503 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4504 } else {
7b04bd5c 4505 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4506 }
cf495bcf 4507 }
0f8a249a
BS		 4508 switch (xop) {
4509 case 0x38: /* jmpl */
4510 {
97ea2859 4511 TCGv t;
a7812ae4 4512 TCGv_i32 r_const;
2ea815ca 4513
97ea2859
RH		 4514 t = gen_dest_gpr(dc, rd);
4515 tcg_gen_movi_tl(t, dc->pc);
4516 gen_store_gpr(dc, rd, t);
13a6dd00 4517 gen_mov_pc_npc(dc);
2ea815ca 4518 r_const = tcg_const_i32(3);
7b04bd5c 4519 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4520 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4521 gen_address_mask(dc, cpu_tmp0);
4522 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4523 dc->npc = DYNAMIC_PC;
4524 }
4525 goto jmp_insn;
3475187d 4526#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4527 case 0x39: /* rett, V9 return */
4528 {
a7812ae4 4529 TCGv_i32 r_const;
2ea815ca 4530
0f8a249a
BS		 4531 if (!supervisor(dc))
4532 goto priv_insn;
13a6dd00 4533 gen_mov_pc_npc(dc);
2ea815ca 4534 r_const = tcg_const_i32(3);
7b04bd5c 4535 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4536 tcg_temp_free_i32(r_const);
7b04bd5c 4537 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4538 dc->npc = DYNAMIC_PC;
063c3675 4539 gen_helper_rett(cpu_env);
0f8a249a
BS		 4540 }
4541 goto jmp_insn;
4542#endif
4543 case 0x3b: /* flush */
5578ceab 4544 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4545 goto unimp_flush;
dcfd14b3 4546 /* nop */
0f8a249a
BS		 4547 break;
4548 case 0x3c: /* save */
66442b07 4549 save_state(dc);
063c3675 4550 gen_helper_save(cpu_env);
7b04bd5c 4551 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4552 break;
4553 case 0x3d: /* restore */
66442b07 4554 save_state(dc);
063c3675 4555 gen_helper_restore(cpu_env);
7b04bd5c 4556 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4557 break;
3475187d 4558#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4559 case 0x3e: /* V9 done/retry */
4560 {
4561 switch (rd) {
4562 case 0:
4563 if (!supervisor(dc))
4564 goto priv_insn;
4565 dc->npc = DYNAMIC_PC;
4566 dc->pc = DYNAMIC_PC;
063c3675 4567 gen_helper_done(cpu_env);
0f8a249a
BS		 4568 goto jmp_insn;
4569 case 1:
4570 if (!supervisor(dc))
4571 goto priv_insn;
4572 dc->npc = DYNAMIC_PC;
4573 dc->pc = DYNAMIC_PC;
063c3675 4574 gen_helper_retry(cpu_env);
0f8a249a
BS		 4575 goto jmp_insn;
4576 default:
4577 goto illegal_insn;
4578 }
4579 }
4580 break;
4581#endif
4582 default:
4583 goto illegal_insn;
4584 }
cf495bcf 4585 }
0f8a249a
BS		 4586 break;
4587 }
4588 break;
4589 case 3: /* load/store instructions */
4590 {
4591 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4592 /* ??? gen_address_mask prevents us from using a source
4593 register directly. Always generate a temporary. */
4594 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4595
5e6ed439
RH		 4596 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4597 if (xop == 0x3c || xop == 0x3e) {
4598 /* V9 casa/casxa : no offset */
71817e48 4599 } else if (IS_IMM) { /* immediate */
67526b20 4600 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4601 if (simm != 0) {
4602 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4603 }
0f8a249a
BS		 4604 } else { /* register */
4605 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4606 if (rs2 != 0) {
5e6ed439 4607 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4608 }
0f8a249a 4609 }
2f2ecb83
BS		 4610 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4611 (xop > 0x17 && xop <= 0x1d ) ||
4612 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4613 TCGv cpu_val = gen_dest_gpr(dc, rd);
4614
0f8a249a 4615 switch (xop) {
b89e94af 4616 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4617 gen_address_mask(dc, cpu_addr);
6ae20372 4618 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4619 break;
b89e94af 4620 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4621 gen_address_mask(dc, cpu_addr);
6ae20372 4622 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4623 break;
b89e94af 4624 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4625 gen_address_mask(dc, cpu_addr);
6ae20372 4626 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4627 break;
b89e94af 4628 case 0x3: /* ldd, load double word */
0f8a249a 4629 if (rd & 1)
d4218d99 4630 goto illegal_insn;
1a2fb1c0 4631 else {
a7812ae4 4632 TCGv_i32 r_const;
abcc7191 4633 TCGv_i64 t64;
2ea815ca 4634
66442b07 4635 save_state(dc);
2ea815ca 4636 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4637 /* XXX remove alignment check */
4638 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4639 tcg_temp_free_i32(r_const);
2cade6a3 4640 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4641 t64 = tcg_temp_new_i64();
4642 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4643 tcg_gen_trunc_i64_tl(cpu_val, t64);
4644 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4645 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4646 tcg_gen_shri_i64(t64, t64, 32);
4647 tcg_gen_trunc_i64_tl(cpu_val, t64);
4648 tcg_temp_free_i64(t64);
de9e9d9f 4649 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4650 }
0f8a249a 4651 break;
b89e94af 4652 case 0x9: /* ldsb, load signed byte */
2cade6a3 4653 gen_address_mask(dc, cpu_addr);
6ae20372 4654 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4655 break;
b89e94af 4656 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4657 gen_address_mask(dc, cpu_addr);
6ae20372 4658 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4659 break;
4660 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4661 {
4662 TCGv r_const;
4663
2cade6a3 4664 gen_address_mask(dc, cpu_addr);
2ea815ca
BS		 4665 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4666 r_const = tcg_const_tl(0xff);
4667 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4668 tcg_temp_free(r_const);
4669 }
0f8a249a 4670 break;
de9e9d9f
RH		 4671 case 0x0f:
4672 /* swap, swap register with memory. Also atomically */
4673 {
4674 TCGv t0 = get_temp_tl(dc);
4675 CHECK_IU_FEATURE(dc, SWAP);
4676 cpu_src1 = gen_load_gpr(dc, rd);
4677 gen_address_mask(dc, cpu_addr);
4678 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4679 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4680 tcg_gen_mov_tl(cpu_val, t0);
4681 }
0f8a249a 4682 break;
3475187d 4683#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4684 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4685#ifndef TARGET_SPARC64
0f8a249a
BS		 4686 if (IS_IMM)
4687 goto illegal_insn;
4688 if (!supervisor(dc))
4689 goto priv_insn;
6ea4a6c8 4690#endif
66442b07 4691 save_state(dc);
6ae20372 4692 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4693 break;
b89e94af 4694 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4695#ifndef TARGET_SPARC64
0f8a249a
BS		 4696 if (IS_IMM)
4697 goto illegal_insn;
4698 if (!supervisor(dc))
4699 goto priv_insn;
4700#endif
66442b07 4701 save_state(dc);
6ae20372 4702 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4703 break;
b89e94af 4704 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4705#ifndef TARGET_SPARC64
0f8a249a
BS		 4706 if (IS_IMM)
4707 goto illegal_insn;
4708 if (!supervisor(dc))
4709 goto priv_insn;
3475187d 4710#endif
66442b07 4711 save_state(dc);
6ae20372 4712 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4713 break;
b89e94af 4714 case 0x13: /* ldda, load double word alternate */
3475187d 4715#ifndef TARGET_SPARC64
0f8a249a
BS		 4716 if (IS_IMM)
4717 goto illegal_insn;
4718 if (!supervisor(dc))
4719 goto priv_insn;
3475187d 4720#endif
0f8a249a 4721 if (rd & 1)
d4218d99 4722 goto illegal_insn;
66442b07 4723 save_state(dc);
c7785e16 4724 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4725 goto skip_move;
b89e94af 4726 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4727#ifndef TARGET_SPARC64
0f8a249a
BS		 4728 if (IS_IMM)
4729 goto illegal_insn;
4730 if (!supervisor(dc))
4731 goto priv_insn;
4732#endif
66442b07 4733 save_state(dc);
6ae20372 4734 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4735 break;
b89e94af 4736 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4737#ifndef TARGET_SPARC64
0f8a249a
BS		 4738 if (IS_IMM)
4739 goto illegal_insn;
4740 if (!supervisor(dc))
4741 goto priv_insn;
3475187d 4742#endif
66442b07 4743 save_state(dc);
6ae20372 4744 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4745 break;
4746 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4747#ifndef TARGET_SPARC64
0f8a249a
BS		 4748 if (IS_IMM)
4749 goto illegal_insn;
4750 if (!supervisor(dc))
4751 goto priv_insn;
4752#endif
66442b07 4753 save_state(dc);
6ae20372 4754 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4755 break;
b89e94af 4756 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4757 atomically */
64a88d5d 4758 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4759#ifndef TARGET_SPARC64
0f8a249a
BS		 4760 if (IS_IMM)
4761 goto illegal_insn;
4762 if (!supervisor(dc))
4763 goto priv_insn;
6ea4a6c8 4764#endif
66442b07 4765 save_state(dc);
06828032
RH		 4766 cpu_src1 = gen_load_gpr(dc, rd);
4767 gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4768 break;
3475187d
FB		 4769
4770#ifndef TARGET_SPARC64
0f8a249a
BS		 4771 case 0x30: /* ldc */
4772 case 0x31: /* ldcsr */
4773 case 0x33: /* lddc */
4774 goto ncp_insn;
3475187d
FB		 4775#endif
4776#endif
4777#ifdef TARGET_SPARC64
0f8a249a 4778 case 0x08: /* V9 ldsw */
2cade6a3 4779 gen_address_mask(dc, cpu_addr);
6ae20372 4780 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4781 break;
4782 case 0x0b: /* V9 ldx */
2cade6a3 4783 gen_address_mask(dc, cpu_addr);
6ae20372 4784 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4785 break;
4786 case 0x18: /* V9 ldswa */
66442b07 4787 save_state(dc);
6ae20372 4788 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4789 break;
4790 case 0x1b: /* V9 ldxa */
66442b07 4791 save_state(dc);
6ae20372 4792 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4793 break;
4794 case 0x2d: /* V9 prefetch, no effect */
4795 goto skip_move;
4796 case 0x30: /* V9 ldfa */
5b12f1e8 4797 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4798 goto jmp_insn;
4799 }
66442b07 4800 save_state(dc);
6ae20372 4801 gen_ldf_asi(cpu_addr, insn, 4, rd);
638737ad 4802 gen_update_fprs_dirty(rd);
81ad8ba2 4803 goto skip_move;
0f8a249a 4804 case 0x33: /* V9 lddfa */
5b12f1e8 4805 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4806 goto jmp_insn;
4807 }
66442b07 4808 save_state(dc);
6ae20372 4809 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
638737ad 4810 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4811 goto skip_move;
0f8a249a
BS		 4812 case 0x3d: /* V9 prefetcha, no effect */
4813 goto skip_move;
4814 case 0x32: /* V9 ldqfa */
64a88d5d 4815 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4816 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4817 goto jmp_insn;
4818 }
66442b07 4819 save_state(dc);
6ae20372 4820 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
638737ad 4821 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4822 goto skip_move;
0f8a249a
BS		 4823#endif
4824 default:
4825 goto illegal_insn;
4826 }
97ea2859 4827 gen_store_gpr(dc, rd, cpu_val);
db166940 4828#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4829 skip_move: ;
3475187d 4830#endif
0f8a249a 4831 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4832 TCGv t0;
4833
5b12f1e8 4834 if (gen_trap_ifnofpu(dc)) {
a80dde08 4835 goto jmp_insn;
5b12f1e8 4836 }
66442b07 4837 save_state(dc);
0f8a249a 4838 switch (xop) {
b89e94af 4839 case 0x20: /* ldf, load fpreg */
2cade6a3 4840 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4841 t0 = get_temp_tl(dc);
4842 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4843 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4844 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4845 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4846 break;
3a3b925d
BS		 4847 case 0x21: /* ldfsr, V9 ldxfsr */
4848#ifdef TARGET_SPARC64
2cade6a3 4849 gen_address_mask(dc, cpu_addr);
3a3b925d 4850 if (rd == 1) {
abcc7191
RH		 4851 TCGv_i64 t64 = tcg_temp_new_i64();
4852 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4853 gen_helper_ldxfsr(cpu_env, t64);
4854 tcg_temp_free_i64(t64);
f8641947 4855 break;
fe987e23 4856 }
f8641947 4857#endif
de9e9d9f
RH		 4858 cpu_dst_32 = get_temp_i32(dc);
4859 t0 = get_temp_tl(dc);
4860 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4861 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4862 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4863 break;
b89e94af 4864 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4865 {
a7812ae4 4866 TCGv_i32 r_const;
2ea815ca
BS		 4867
4868 CHECK_FPU_FEATURE(dc, FLOAT128);
4869 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4870 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4871 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4872 tcg_temp_free_i32(r_const);
2ea815ca 4873 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4874 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4875 }
1f587329 4876 break;
b89e94af 4877 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4878 gen_address_mask(dc, cpu_addr);
3886b8a3 4879 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4880 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4881 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4882 break;
4883 default:
4884 goto illegal_insn;
4885 }
dc1a6971 4886 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4887 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4888 TCGv cpu_val = gen_load_gpr(dc, rd);
4889
0f8a249a 4890 switch (xop) {
b89e94af 4891 case 0x4: /* st, store word */
2cade6a3 4892 gen_address_mask(dc, cpu_addr);
6ae20372 4893 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4894 break;
b89e94af 4895 case 0x5: /* stb, store byte */
2cade6a3 4896 gen_address_mask(dc, cpu_addr);
6ae20372 4897 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4898 break;
b89e94af 4899 case 0x6: /* sth, store halfword */
2cade6a3 4900 gen_address_mask(dc, cpu_addr);
6ae20372 4901 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4902 break;
b89e94af 4903 case 0x7: /* std, store double word */
0f8a249a 4904 if (rd & 1)
d4218d99 4905 goto illegal_insn;
1a2fb1c0 4906 else {
a7812ae4 4907 TCGv_i32 r_const;
abcc7191 4908 TCGv_i64 t64;
81634eea 4909 TCGv lo;
1a2fb1c0 4910
66442b07 4911 save_state(dc);
2cade6a3 4912 gen_address_mask(dc, cpu_addr);
2ea815ca 4913 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4914 /* XXX remove alignment check */
4915 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4916 tcg_temp_free_i32(r_const);
81634eea 4917 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 4918
4919 t64 = tcg_temp_new_i64();
4920 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4921 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4922 tcg_temp_free_i64(t64);
7fa76c0b 4923 }
0f8a249a 4924 break;
3475187d 4925#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4926 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4927#ifndef TARGET_SPARC64
0f8a249a
BS		 4928 if (IS_IMM)
4929 goto illegal_insn;
4930 if (!supervisor(dc))
4931 goto priv_insn;
6ea4a6c8 4932#endif
66442b07 4933 save_state(dc);
6ae20372 4934 gen_st_asi(cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4935 dc->npc = DYNAMIC_PC;
d39c0b99 4936 break;
b89e94af 4937 case 0x15: /* stba, store byte alternate */
3475187d 4938#ifndef TARGET_SPARC64
0f8a249a
BS		 4939 if (IS_IMM)
4940 goto illegal_insn;
4941 if (!supervisor(dc))
4942 goto priv_insn;
3475187d 4943#endif
66442b07 4944 save_state(dc);
6ae20372 4945 gen_st_asi(cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4946 dc->npc = DYNAMIC_PC;
d39c0b99 4947 break;
b89e94af 4948 case 0x16: /* stha, store halfword alternate */
3475187d 4949#ifndef TARGET_SPARC64
0f8a249a
BS		 4950 if (IS_IMM)
4951 goto illegal_insn;
4952 if (!supervisor(dc))
4953 goto priv_insn;
6ea4a6c8 4954#endif
66442b07 4955 save_state(dc);
6ae20372 4956 gen_st_asi(cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4957 dc->npc = DYNAMIC_PC;
d39c0b99 4958 break;
b89e94af 4959 case 0x17: /* stda, store double word alternate */
3475187d 4960#ifndef TARGET_SPARC64
0f8a249a
BS		 4961 if (IS_IMM)
4962 goto illegal_insn;
4963 if (!supervisor(dc))
4964 goto priv_insn;
3475187d 4965#endif
0f8a249a 4966 if (rd & 1)
d4218d99 4967 goto illegal_insn;
1a2fb1c0 4968 else {
66442b07 4969 save_state(dc);
c7785e16 4970 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4971 }
d39c0b99 4972 break;
e80cfcfc 4973#endif
3475187d 4974#ifdef TARGET_SPARC64
0f8a249a 4975 case 0x0e: /* V9 stx */
2cade6a3 4976 gen_address_mask(dc, cpu_addr);
6ae20372 4977 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4978 break;
4979 case 0x1e: /* V9 stxa */
66442b07 4980 save_state(dc);
6ae20372 4981 gen_st_asi(cpu_val, cpu_addr, insn, 8);
9fd1ae3a 4982 dc->npc = DYNAMIC_PC;
0f8a249a 4983 break;
3475187d 4984#endif
0f8a249a
BS		 4985 default:
4986 goto illegal_insn;
4987 }
4988 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 4989 if (gen_trap_ifnofpu(dc)) {
a80dde08 4990 goto jmp_insn;
5b12f1e8 4991 }
66442b07 4992 save_state(dc);
0f8a249a 4993 switch (xop) {
b89e94af 4994 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 4995 {
4996 TCGv t = get_temp_tl(dc);
4997 gen_address_mask(dc, cpu_addr);
4998 cpu_src1_32 = gen_load_fpr_F(dc, rd);
4999 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5000 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5001 }
0f8a249a
BS		 5002 break;
5003 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5004 {
5005 TCGv t = get_temp_tl(dc);
5006
5007 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5008#ifdef TARGET_SPARC64
f8641947
RH		 5009 gen_address_mask(dc, cpu_addr);
5010 if (rd == 1) {
5011 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5012 break;
5013 }
3a3b925d 5014#endif
f8641947
RH		 5015 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5016 }
0f8a249a 5017 break;
1f587329
BS		 5018 case 0x26:
5019#ifdef TARGET_SPARC64
1f587329 5020 /* V9 stqf, store quad fpreg */
2ea815ca 5021 {
a7812ae4 5022 TCGv_i32 r_const;
2ea815ca
BS		 5023
5024 CHECK_FPU_FEATURE(dc, FLOAT128);
5025 gen_op_load_fpr_QT0(QFPREG(rd));
5026 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5027 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5028 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5029 tcg_temp_free_i32(r_const);
2ea815ca 5030 }
1f587329 5031 break;
1f587329
BS		 5032#else /* !TARGET_SPARC64 */
5033 /* stdfq, store floating point queue */
5034#if defined(CONFIG_USER_ONLY)
5035 goto illegal_insn;
5036#else
0f8a249a
BS		 5037 if (!supervisor(dc))
5038 goto priv_insn;
5b12f1e8 5039 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5040 goto jmp_insn;
5b12f1e8 5041 }
0f8a249a 5042 goto nfq_insn;
1f587329 5043#endif
0f8a249a 5044#endif
b89e94af 5045 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5046 gen_address_mask(dc, cpu_addr);
5047 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5048 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5049 break;
5050 default:
5051 goto illegal_insn;
5052 }
5053 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5054 save_state(dc);
0f8a249a 5055 switch (xop) {
a4d17f19 5056#ifdef TARGET_SPARC64
0f8a249a 5057 case 0x34: /* V9 stfa */
5b12f1e8 5058 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5059 goto jmp_insn;
5060 }
6ae20372 5061 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 5062 break;
1f587329 5063 case 0x36: /* V9 stqfa */
2ea815ca 5064 {
a7812ae4 5065 TCGv_i32 r_const;
2ea815ca
BS		 5066
5067 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5068 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5069 goto jmp_insn;
5070 }
2ea815ca 5071 r_const = tcg_const_i32(7);
fe8d8f0f 5072 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5073 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5074 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5075 }
1f587329 5076 break;
0f8a249a 5077 case 0x37: /* V9 stdfa */
5b12f1e8 5078 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5079 goto jmp_insn;
5080 }
6ae20372 5081 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5082 break;
0f8a249a 5083 case 0x3e: /* V9 casxa */
a4273524
RH		 5084 rs2 = GET_FIELD(insn, 27, 31);
5085 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5086 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5087 break;
a4d17f19 5088#else
0f8a249a
BS		 5089 case 0x34: /* stc */
5090 case 0x35: /* stcsr */
5091 case 0x36: /* stdcq */
5092 case 0x37: /* stdc */
5093 goto ncp_insn;
16c358e9
SH		 5094#endif
5095#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5096 case 0x3c: /* V9 or LEON3 casa */
5097#ifndef TARGET_SPARC64
5098 CHECK_IU_FEATURE(dc, CASA);
5099 if (IS_IMM) {
5100 goto illegal_insn;
5101 }
5102 if (!supervisor(dc)) {
5103 goto priv_insn;
5104 }
5105#endif
5106 rs2 = GET_FIELD(insn, 27, 31);
5107 cpu_src2 = gen_load_gpr(dc, rs2);
5108 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5109 break;
0f8a249a
BS		 5110#endif
5111 default:
5112 goto illegal_insn;
5113 }
a4273524 5114 } else {
0f8a249a 5115 goto illegal_insn;
a4273524 5116 }
0f8a249a
BS		 5117 }
5118 break;
cf495bcf
FB		 5119 }
5120 /* default case for non jump instructions */
72cbca10 5121 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5122 dc->pc = DYNAMIC_PC;
5123 gen_op_next_insn();
72cbca10
FB		 5124 } else if (dc->npc == JUMP_PC) {
5125 /* we can do a static jump */
6ae20372 5126 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5127 dc->is_br = 1;
5128 } else {
0f8a249a
BS		 5129 dc->pc = dc->npc;
5130 dc->npc = dc->npc + 4;
cf495bcf 5131 }
e80cfcfc 5132 jmp_insn:
42a8aa83 5133 goto egress;
cf495bcf 5134 illegal_insn:
2ea815ca 5135 {
a7812ae4 5136 TCGv_i32 r_const;
2ea815ca 5137
66442b07 5138 save_state(dc);
2ea815ca 5139 r_const = tcg_const_i32(TT_ILL_INSN);
bc265319 5140 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5141 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5142 dc->is_br = 1;
5143 }
42a8aa83 5144 goto egress;
64a88d5d 5145 unimp_flush:
2ea815ca 5146 {
a7812ae4 5147 TCGv_i32 r_const;
2ea815ca 5148
66442b07 5149 save_state(dc);
2ea815ca 5150 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
bc265319 5151 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5152 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5153 dc->is_br = 1;
5154 }
42a8aa83 5155 goto egress;
e80cfcfc 5156#if !defined(CONFIG_USER_ONLY)
e8af50a3 5157 priv_insn:
2ea815ca 5158 {
a7812ae4 5159 TCGv_i32 r_const;
2ea815ca 5160
66442b07 5161 save_state(dc);
2ea815ca 5162 r_const = tcg_const_i32(TT_PRIV_INSN);
bc265319 5163 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5164 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5165 dc->is_br = 1;
5166 }
42a8aa83 5167 goto egress;
64a88d5d 5168#endif
e80cfcfc 5169 nfpu_insn:
66442b07 5170 save_state(dc);
e80cfcfc
FB		 5171 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5172 dc->is_br = 1;
42a8aa83 5173 goto egress;
64a88d5d 5174#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5175 nfq_insn:
66442b07 5176 save_state(dc);
9143e598
BS		 5177 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5178 dc->is_br = 1;
42a8aa83 5179 goto egress;
9143e598 5180#endif
fcc72045
BS		 5181#ifndef TARGET_SPARC64
5182 ncp_insn:
2ea815ca
BS		 5183 {
5184 TCGv r_const;
5185
66442b07 5186 save_state(dc);
2ea815ca 5187 r_const = tcg_const_i32(TT_NCP_INSN);
bc265319 5188 gen_helper_raise_exception(cpu_env, r_const);
2ea815ca
BS		 5189 tcg_temp_free(r_const);
5190 dc->is_br = 1;
5191 }
42a8aa83 5192 goto egress;
fcc72045 5193#endif
42a8aa83 5194 egress:
30038fd8
RH		 5195 if (dc->n_t32 != 0) {
5196 int i;
5197 for (i = dc->n_t32 - 1; i >= 0; --i) {
5198 tcg_temp_free_i32(dc->t32[i]);
5199 }
5200 dc->n_t32 = 0;
5201 }
88023616
RH		 5202 if (dc->n_ttl != 0) {
5203 int i;
5204 for (i = dc->n_ttl - 1; i >= 0; --i) {
5205 tcg_temp_free(dc->ttl[i]);
5206 }
5207 dc->n_ttl = 0;
5208 }
7a3f1944
FB		 5209}
5210
68a47155
AF		 5211static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
5212 TranslationBlock *tb,
5213 bool spc)
7a3f1944 5214{
ed2803da 5215 CPUState *cs = CPU(cpu);
68a47155 5216 CPUSPARCState *env = &cpu->env;
72cbca10 5217 target_ulong pc_start, last_pc;
cf495bcf 5218 DisasContext dc1, *dc = &dc1;
e8af50a3 5219 int j, lj = -1;
2e70f6ef
PB		 5220 int num_insns;
5221 int max_insns;
0184e266 5222 unsigned int insn;
cf495bcf
FB		 5223
5224 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5225 dc->tb = tb;
72cbca10 5226 pc_start = tb->pc;
cf495bcf 5227 dc->pc = pc_start;
e80cfcfc 5228 last_pc = dc->pc;
72cbca10 5229 dc->npc = (target_ulong) tb->cs_base;
8393617c 5230 dc->cc_op = CC_OP_DYNAMIC;
97ed5ccd 5231 dc->mem_idx = cpu_mmu_index(env, false);
5578ceab 5232 dc->def = env->def;
f838e2c5
BS		 5233 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5234 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5235 dc->singlestep = (cs->singlestep_enabled || singlestep);
cf495bcf 5236
2e70f6ef
PB		 5237 num_insns = 0;
5238 max_insns = tb->cflags & CF_COUNT_MASK;
5239 if (max_insns == 0)
5240 max_insns = CF_COUNT_MASK;
cd42d5b2 5241 gen_tb_start(tb);
cf495bcf 5242 do {
e8af50a3 5243 if (spc) {
93fcfe39 5244 qemu_log("Search PC...\n");
fe700adb 5245 j = tcg_op_buf_count();
e8af50a3
FB		 5246 if (lj < j) {
5247 lj++;
5248 while (lj < j)
ab1103de 5249 tcg_ctx.gen_opc_instr_start[lj++] = 0;
25983cad 5250 tcg_ctx.gen_opc_pc[lj] = dc->pc;
e8af50a3 5251 gen_opc_npc[lj] = dc->npc;
6c42444f
RH		 5252 if (dc->npc & JUMP_PC) {
5253 assert(dc->jump_pc[1] == dc->pc + 4);
5254 gen_opc_npc[lj] = dc->jump_pc[0] | JUMP_PC;
5255 }
ab1103de 5256 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 5257 tcg_ctx.gen_opc_icount[lj] = num_insns;
e8af50a3
FB		 5258 }
5259 }
667b8e29 5260 tcg_gen_insn_start(dc->pc);
959082fc 5261 num_insns++;
667b8e29 5262
b933066a
RH		 5263 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5264 if (dc->pc != pc_start) {
5265 save_state(dc);
5266 }
5267 gen_helper_debug(cpu_env);
5268 tcg_gen_exit_tb(0);
5269 dc->is_br = 1;
5270 goto exit_gen_loop;
5271 }
5272
959082fc 5273 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5274 gen_io_start();
667b8e29
RH		 5275 }
5276
0f8a249a 5277 last_pc = dc->pc;
0184e266 5278 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5279
0184e266 5280 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5281
5282 if (dc->is_br)
5283 break;
5284 /* if the next PC is different, we abort now */
5285 if (dc->pc != (last_pc + 4))
5286 break;
d39c0b99
FB		 5287 /* if we reach a page boundary, we stop generation so that the
5288 PC of a TT_TFAULT exception is always in the right page */
5289 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5290 break;
e80cfcfc
FB		 5291 /* if single step mode, we generate only one instruction and
5292 generate an exception */
060718c1 5293 if (dc->singlestep) {
e80cfcfc
FB		 5294 break;
5295 }
fe700adb 5296 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5297 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5298 num_insns < max_insns);
e80cfcfc
FB		 5299
5300 exit_gen_loop:
b09b2fd3 5301 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5302 gen_io_end();
b09b2fd3 5303 }
72cbca10 5304 if (!dc->is_br) {
5fafdf24 5305 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5306 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5307 /* static PC and NPC: we can use direct chaining */
2f5680ee 5308 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5309 } else {
b09b2fd3 5310 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5311 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5312 }
934da7ee 5313 save_npc(dc);
57fec1fe 5314 tcg_gen_exit_tb(0);
72cbca10
FB		 5315 }
5316 }
806f352d 5317 gen_tb_end(tb, num_insns);
0a7df5da 5318
e8af50a3 5319 if (spc) {
fe700adb 5320 j = tcg_op_buf_count();
e8af50a3
FB		 5321 lj++;
5322 while (lj <= j)
ab1103de 5323 tcg_ctx.gen_opc_instr_start[lj++] = 0;
e8af50a3 5324#if 0
93fcfe39 5325 log_page_dump();
e8af50a3
FB		 5326#endif
5327 } else {
e80cfcfc 5328 tb->size = last_pc + 4 - pc_start;
2e70f6ef 5329 tb->icount = num_insns;
e8af50a3 5330 }
7a3f1944 5331#ifdef DEBUG_DISAS
8fec2b8c 5332 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 5333 qemu_log("--------------\n");
5334 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5335 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5336 qemu_log("\n");
cf495bcf 5337 }
7a3f1944 5338#endif
7a3f1944
FB		 5339}
5340
2cfc5f17 5341void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5342{
68a47155 5343 gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, false);
7a3f1944
FB		 5344}
5345
2cfc5f17 5346void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5347{
68a47155 5348 gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, true);
7a3f1944
FB		 5349}
5350
c48fcb47 5351void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5352{
f5069b26 5353 unsigned int i;
c48fcb47 5354 static int inited;
f5069b26
BS		 5355 static const char * const gregnames[8] = {
5356 NULL, // g0 not used
5357 "g1",
5358 "g2",
5359 "g3",
5360 "g4",
5361 "g5",
5362 "g6",
5363 "g7",
5364 };
30038fd8
RH		 5365 static const char * const fregnames[32] = {
5366 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5367 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5368 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5369 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5370 };
aaed909a 5371
1a2fb1c0
BS		 5372 /* init various static tables */
5373 if (!inited) {
5374 inited = 1;
5375
a7812ae4
PB		 5376 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5377 cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
c5f9864e 5378 offsetof(CPUSPARCState, regwptr),
a7812ae4 5379 "regwptr");
1a2fb1c0 5380#ifdef TARGET_SPARC64
c5f9864e 5381 cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc),
a7812ae4 5382 "xcc");
c5f9864e 5383 cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi),
a7812ae4 5384 "asi");
c5f9864e 5385 cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs),
a7812ae4 5386 "fprs");
c5f9864e 5387 cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr),
255e1fcb 5388 "gsr");
a7812ae4 5389 cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5390 offsetof(CPUSPARCState, tick_cmpr),
255e1fcb 5391 "tick_cmpr");
a7812ae4 5392 cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5393 offsetof(CPUSPARCState, stick_cmpr),
255e1fcb 5394 "stick_cmpr");
a7812ae4 5395 cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5396 offsetof(CPUSPARCState, hstick_cmpr),
255e1fcb 5397 "hstick_cmpr");
c5f9864e 5398 cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp),
255e1fcb 5399 "hintp");
c5f9864e 5400 cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba),
a7812ae4 5401 "htba");
c5f9864e 5402 cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver),
a7812ae4
PB		 5403 "hver");
5404 cpu_ssr = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5405 offsetof(CPUSPARCState, ssr), "ssr");
a7812ae4 5406 cpu_ver = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5407 offsetof(CPUSPARCState, version), "ver");
a7812ae4 5408 cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
c5f9864e 5409 offsetof(CPUSPARCState, softint),
a7812ae4 5410 "softint");
255e1fcb 5411#else
c5f9864e 5412 cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim),
255e1fcb 5413 "wim");
1a2fb1c0 5414#endif
c5f9864e 5415 cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond),
77f193da 5416 "cond");
c5f9864e 5417 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src),
dc99a3f2 5418 "cc_src");
a7812ae4 5419 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5420 offsetof(CPUSPARCState, cc_src2),
d9bdab86 5421 "cc_src2");
c5f9864e 5422 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst),
dc99a3f2 5423 "cc_dst");
c5f9864e 5424 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op),
8393617c 5425 "cc_op");
c5f9864e 5426 cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr),
a7812ae4 5427 "psr");
c5f9864e 5428 cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr),
87e92502 5429 "fsr");
c5f9864e 5430 cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc),
48d5c82b 5431 "pc");
c5f9864e 5432 cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc),
a7812ae4 5433 "npc");
c5f9864e 5434 cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
255e1fcb 5435#ifndef CONFIG_USER_ONLY
c5f9864e 5436 cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr),
255e1fcb
BS		 5437 "tbr");
5438#endif
30038fd8 5439 for (i = 1; i < 8; i++) {
a7812ae4 5440 cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
c5f9864e 5441 offsetof(CPUSPARCState, gregs[i]),
f5069b26 5442 gregnames[i]);
30038fd8
RH		 5443 }
5444 for (i = 0; i < TARGET_DPREGS; i++) {
5445 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
c5f9864e 5446 offsetof(CPUSPARCState, fpr[i]),
45c7b743 5447 fregnames[i]);
30038fd8 5448 }
1a2fb1c0 5449 }
658138bc 5450}
d2856f1a 5451
c5f9864e 5452void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos)
d2856f1a 5453{
6c42444f
RH		 5454 target_ulong pc, npc;
5455 env->pc = pc = tcg_ctx.gen_opc_pc[pc_pos];
d2856f1a 5456 npc = gen_opc_npc[pc_pos];
6c42444f 5457 if (npc == DYNAMIC_PC) {
d2856f1a 5458 /* dynamic NPC: already stored */
6c42444f 5459 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5460 /* jump PC: use 'cond' and the jump targets of the translation */
5461 if (env->cond) {
6c42444f 5462 env->npc = npc & ~3;
d7da2a10 5463 } else {
6c42444f 5464 env->npc = pc + 4;
d7da2a10 5465 }
d2856f1a
AJ		 5466 } else {
5467 env->npc = npc;
5468 }
5469}
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