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Convert mulscc to TCG, add cc_src2
[mirror_qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
bd497938 28*/
7a3f1944
FB		 29
30#include <stdarg.h>
31#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <inttypes.h>
35
36#include "cpu.h"
37#include "exec-all.h"
38#include "disas.h"
1a2fb1c0 39#include "helper.h"
57fec1fe 40#include "tcg-op.h"
7a3f1944
FB		 41
42#define DEBUG_DISAS
43
72cbca10
FB		 44#define DYNAMIC_PC 1 /* dynamic pc value */
45#define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
47
1a2fb1c0 48/* global register indexes */
d9bdab86 49static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
87e92502 50static TCGv cpu_psr, cpu_fsr, cpu_gregs[8];
dc99a3f2
BS		 51#ifdef TARGET_SPARC64
52static TCGv cpu_xcc;
53#endif
1a2fb1c0
BS		 54/* local register indexes (only used inside old micro ops) */
55static TCGv cpu_tmp0;
56
7a3f1944 57typedef struct DisasContext {
0f8a249a
BS		 58 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
59 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 60 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 61 int is_br;
e8af50a3 62 int mem_idx;
a80dde08 63 int fpu_enabled;
cf495bcf 64 struct TranslationBlock *tb;
7a3f1944
FB		 65} DisasContext;
66
aaed909a
FB		 67typedef struct sparc_def_t sparc_def_t;
68
62724a37
BS		 69struct sparc_def_t {
70 const unsigned char *name;
71 target_ulong iu_version;
72 uint32_t fpu_version;
73 uint32_t mmu_version;
6d5f237a 74 uint32_t mmu_bm;
3deaeab7
BS		 75 uint32_t mmu_ctpr_mask;
76 uint32_t mmu_cxr_mask;
77 uint32_t mmu_sfsr_mask;
78 uint32_t mmu_trcr_mask;
62724a37
BS		 79};
80
aaed909a
FB		 81static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
82
7a3f1944
FB		 83extern FILE *logfile;
84extern int loglevel;
85
3475187d 86// This function uses non-native bit order
7a3f1944
FB		 87#define GET_FIELD(X, FROM, TO) \
88 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
89
3475187d
FB		 90// This function uses the order in the manuals, i.e. bit 0 is 2^0
91#define GET_FIELD_SP(X, FROM, TO) \
92 GET_FIELD(X, 31 - (TO), 31 - (FROM))
93
94#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 95#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 96
97#ifdef TARGET_SPARC64
19f329ad 98#define FFPREG(r) (r)
0387d928 99#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 100#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 101#else
19f329ad 102#define FFPREG(r) (r)
c185970a 103#define DFPREG(r) (r & 0x1e)
1f587329 104#define QFPREG(r) (r & 0x1c)
3475187d
FB		 105#endif
106
107static int sign_extend(int x, int len)
108{
109 len = 32 - len;
110 return (x << len) >> len;
111}
112
7a3f1944
FB		 113#define IS_IMM (insn & (1<<13))
114
cf495bcf 115static void disas_sparc_insn(DisasContext * dc);
7a3f1944 116
3475187d
FB		 117#ifdef TARGET_SPARC64
118#define GEN32(func, NAME) \
a68156d0 119static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 120NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
121NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
122NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
123NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
124NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
125NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
126NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
127NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
128NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
129NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
130NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
131NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
132}; \
133static inline void func(int n) \
134{ \
135 NAME ## _table[n](); \
136}
137#else
e8af50a3 138#define GEN32(func, NAME) \
a68156d0 139static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 140NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
141NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
142NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
143NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
144NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
145NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
146NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
147NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
148}; \
149static inline void func(int n) \
150{ \
151 NAME ## _table[n](); \
152}
3475187d 153#endif
e8af50a3
FB		 154
155/* floating point registers moves */
156GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
157GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 158GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
159GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 160
161GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
162GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 163GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
164GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 165
1f587329
BS		 166#if defined(CONFIG_USER_ONLY)
167GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
168GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
169GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
170GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
171#endif
172
81ad8ba2
BS		 173/* moves */
174#ifdef CONFIG_USER_ONLY
3475187d 175#define supervisor(dc) 0
81ad8ba2 176#ifdef TARGET_SPARC64
e9ebed4d 177#define hypervisor(dc) 0
81ad8ba2 178#endif
3475187d 179#define gen_op_ldst(name) gen_op_##name##_raw()
3475187d 180#else
6f27aba6 181#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 182#ifdef TARGET_SPARC64
183#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6
BS		 184#define OP_LD_TABLE(width) \
185 static GenOpFunc * const gen_op_##width[] = { \
186 &gen_op_##width##_user, \
187 &gen_op_##width##_kernel, \
188 &gen_op_##width##_hypv, \
189 };
190#else
0f8a249a 191#define OP_LD_TABLE(width) \
a68156d0 192 static GenOpFunc * const gen_op_##width[] = { \
0f8a249a
BS		 193 &gen_op_##width##_user, \
194 &gen_op_##width##_kernel, \
81ad8ba2 195 };
3475187d 196#endif
6f27aba6
BS		 197#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
198#endif
e8af50a3 199
81ad8ba2 200#ifndef CONFIG_USER_ONLY
b25deda7
BS		 201#ifdef __i386__
202OP_LD_TABLE(std);
203#endif /* __i386__ */
e8af50a3
FB		 204OP_LD_TABLE(stf);
205OP_LD_TABLE(stdf);
206OP_LD_TABLE(ldf);
207OP_LD_TABLE(lddf);
81ad8ba2
BS		 208#endif
209
1a2fb1c0
BS		 210#ifdef TARGET_ABI32
211#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
212#else
213#define ABI32_MASK(addr)
214#endif
3391c818 215
1a2fb1c0 216static inline void gen_movl_simm_T1(int32_t val)
81ad8ba2 217{
1a2fb1c0 218 tcg_gen_movi_tl(cpu_T[1], val);
81ad8ba2
BS		 219}
220
1a2fb1c0 221static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 222{
1a2fb1c0
BS		 223 if (reg == 0)
224 tcg_gen_movi_tl(tn, 0);
225 else if (reg < 8)
f5069b26 226 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
1a2fb1c0 227 else {
1a2fb1c0 228 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 229 }
230}
231
1a2fb1c0 232static inline void gen_movl_reg_T0(int reg)
81ad8ba2 233{
1a2fb1c0 234 gen_movl_reg_TN(reg, cpu_T[0]);
81ad8ba2
BS		 235}
236
1a2fb1c0 237static inline void gen_movl_reg_T1(int reg)
81ad8ba2 238{
1a2fb1c0 239 gen_movl_reg_TN(reg, cpu_T[1]);
81ad8ba2
BS		 240}
241
b25deda7
BS		 242#ifdef __i386__
243static inline void gen_movl_reg_T2(int reg)
244{
245 gen_movl_reg_TN(reg, cpu_T[2]);
246}
247
248#endif /* __i386__ */
1a2fb1c0 249static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 250{
1a2fb1c0
BS		 251 if (reg == 0)
252 return;
253 else if (reg < 8)
f5069b26 254 tcg_gen_mov_tl(cpu_gregs[reg], tn);
1a2fb1c0 255 else {
1a2fb1c0 256 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 257 }
258}
259
1a2fb1c0 260static inline void gen_movl_T0_reg(int reg)
3475187d 261{
1a2fb1c0 262 gen_movl_TN_reg(reg, cpu_T[0]);
3475187d
FB		 263}
264
1a2fb1c0 265static inline void gen_movl_T1_reg(int reg)
3475187d 266{
1a2fb1c0 267 gen_movl_TN_reg(reg, cpu_T[1]);
3475187d
FB		 268}
269
1a2fb1c0 270static inline void gen_op_movl_T0_env(size_t offset)
7a3f1944 271{
1a2fb1c0 272 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 273}
274
1a2fb1c0 275static inline void gen_op_movl_env_T0(size_t offset)
7a3f1944 276{
1a2fb1c0 277 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 278}
279
1a2fb1c0 280static inline void gen_op_movtl_T0_env(size_t offset)
7a3f1944 281{
1a2fb1c0 282 tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 283}
284
1a2fb1c0 285static inline void gen_op_movtl_env_T0(size_t offset)
7a3f1944 286{
1a2fb1c0 287 tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 288}
289
1a2fb1c0 290static inline void gen_op_add_T1_T0(void)
7a3f1944 291{
1a2fb1c0 292 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 293}
294
1a2fb1c0 295static inline void gen_op_or_T1_T0(void)
7a3f1944 296{
1a2fb1c0 297 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 298}
299
1a2fb1c0 300static inline void gen_op_xor_T1_T0(void)
7a3f1944 301{
1a2fb1c0 302 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 303}
304
3475187d
FB		 305static inline void gen_jmp_im(target_ulong pc)
306{
1a2fb1c0
BS		 307 tcg_gen_movi_tl(cpu_tmp0, pc);
308 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
3475187d
FB		 309}
310
311static inline void gen_movl_npc_im(target_ulong npc)
312{
1a2fb1c0
BS		 313 tcg_gen_movi_tl(cpu_tmp0, npc);
314 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
3475187d
FB		 315}
316
5fafdf24 317static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 318 target_ulong pc, target_ulong npc)
319{
320 TranslationBlock *tb;
321
322 tb = s->tb;
323 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
324 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
325 /* jump to same page: we can use a direct jump */
57fec1fe 326 tcg_gen_goto_tb(tb_num);
6e256c93
FB		 327 gen_jmp_im(pc);
328 gen_movl_npc_im(npc);
57fec1fe 329 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 330 } else {
331 /* jump to another page: currently not optimized */
332 gen_jmp_im(pc);
333 gen_movl_npc_im(npc);
57fec1fe 334 tcg_gen_exit_tb(0);
6e256c93
FB		 335 }
336}
337
19f329ad
BS		 338// XXX suboptimal
339static inline void gen_mov_reg_N(TCGv reg, TCGv src)
340{
341 tcg_gen_shri_i32(reg, src, 23);
342 tcg_gen_andi_tl(reg, reg, 0x1);
343}
344
345static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
346{
347 tcg_gen_shri_i32(reg, src, 22);
348 tcg_gen_andi_tl(reg, reg, 0x1);
349}
350
351static inline void gen_mov_reg_V(TCGv reg, TCGv src)
352{
353 tcg_gen_shri_i32(reg, src, 21);
354 tcg_gen_andi_tl(reg, reg, 0x1);
355}
356
357static inline void gen_mov_reg_C(TCGv reg, TCGv src)
358{
359 tcg_gen_shri_i32(reg, src, 20);
360 tcg_gen_andi_tl(reg, reg, 0x1);
361}
362
dc99a3f2
BS		 363static inline void gen_op_exception(int exception)
364{
0425bee5
BS		 365 tcg_gen_movi_i32(cpu_tmp0, exception);
366 tcg_gen_helper_0_1(raise_exception, cpu_tmp0);
dc99a3f2
BS		 367}
368
369static inline void gen_cc_clear(void)
370{
371 tcg_gen_movi_i32(cpu_psr, 0);
372#ifdef TARGET_SPARC64
373 tcg_gen_movi_i32(cpu_xcc, 0);
374#endif
375}
376
377/* old op:
378 if (!T0)
379 env->psr |= PSR_ZERO;
380 if ((int32_t) T0 < 0)
381 env->psr |= PSR_NEG;
382*/
383static inline void gen_cc_NZ(TCGv dst)
384{
385 int l1, l2;
dc99a3f2
BS		 386
387 l1 = gen_new_label();
388 l2 = gen_new_label();
0425bee5 389 tcg_gen_brcond_i32(TCG_COND_NE, dst, tcg_const_i32(0), l1);
dc99a3f2
BS		 390 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
391 gen_set_label(l1);
0425bee5 392 tcg_gen_brcond_i32(TCG_COND_GE, dst, tcg_const_i32(0), l2);
dc99a3f2
BS		 393 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
394 gen_set_label(l2);
395#ifdef TARGET_SPARC64
396 {
397 int l3, l4;
398
399 l3 = gen_new_label();
400 l4 = gen_new_label();
0425bee5 401 tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3);
dc99a3f2
BS		 402 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
403 gen_set_label(l3);
0425bee5 404 tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4);
dc99a3f2
BS		 405 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
406 gen_set_label(l4);
407 }
408#endif
409}
410
411/* old op:
412 if (T0 < src1)
413 env->psr |= PSR_CARRY;
414*/
415static inline void gen_cc_C_add(TCGv dst, TCGv src1)
416{
417 int l1;
418
419 l1 = gen_new_label();
420 tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
421 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
422 gen_set_label(l1);
423#ifdef TARGET_SPARC64
424 {
425 int l2;
426
427 l2 = gen_new_label();
428 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
429 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
430 gen_set_label(l2);
431 }
432#endif
433}
434
435/* old op:
436 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
437 env->psr |= PSR_OVF;
438*/
439static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
440{
0425bee5 441 TCGv r_temp;
dc99a3f2
BS		 442 int l1;
443
444 l1 = gen_new_label();
445
446 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 447 tcg_gen_xor_tl(r_temp, src1, src2);
448 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 449 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
450 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
451 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
452 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
dc99a3f2
BS		 453 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
454 gen_set_label(l1);
455#ifdef TARGET_SPARC64
456 {
457 int l2;
458
459 l2 = gen_new_label();
dc99a3f2
BS		 460 tcg_gen_xor_tl(r_temp, src1, src2);
461 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 462 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
463 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
464 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
465 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
dc99a3f2
BS		 466 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
467 gen_set_label(l2);
468 }
469#endif
0425bee5 470 tcg_gen_discard_tl(r_temp);
dc99a3f2
BS		 471}
472
473static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
474{
0425bee5 475 TCGv r_temp;
dc99a3f2
BS		 476 int l1;
477
478 l1 = gen_new_label();
479
480 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 481 tcg_gen_xor_tl(r_temp, src1, src2);
482 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 483 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
484 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
485 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
486 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
dc99a3f2
BS		 487 gen_op_exception(TT_TOVF);
488 gen_set_label(l1);
489#ifdef TARGET_SPARC64
490 {
491 int l2;
492
493 l2 = gen_new_label();
dc99a3f2
BS		 494 tcg_gen_xor_tl(r_temp, src1, src2);
495 tcg_gen_xori_tl(r_temp, r_temp, -1);
0425bee5
BS		 496 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
497 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
498 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
499 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
dc99a3f2
BS		 500 gen_op_exception(TT_TOVF);
501 gen_set_label(l2);
502 }
503#endif
0425bee5 504 tcg_gen_discard_tl(r_temp);
dc99a3f2
BS		 505}
506
507static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
508{
509 int l1;
dc99a3f2
BS		 510
511 l1 = gen_new_label();
0425bee5
BS		 512 tcg_gen_or_tl(cpu_tmp0, src1, src2);
513 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
514 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
dc99a3f2
BS		 515 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
516 gen_set_label(l1);
517}
518
519static inline void gen_tag_tv(TCGv src1, TCGv src2)
520{
521 int l1;
dc99a3f2
BS		 522
523 l1 = gen_new_label();
0425bee5
BS		 524 tcg_gen_or_tl(cpu_tmp0, src1, src2);
525 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
526 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
dc99a3f2
BS		 527 gen_op_exception(TT_TOVF);
528 gen_set_label(l1);
529}
530
531static inline void gen_op_add_T1_T0_cc(void)
532{
533 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
534 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
535 gen_cc_clear();
536 gen_cc_NZ(cpu_T[0]);
537 gen_cc_C_add(cpu_T[0], cpu_cc_src);
538 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
539}
540
541static inline void gen_op_addx_T1_T0_cc(void)
542{
543 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
544 gen_mov_reg_C(cpu_tmp0, cpu_psr);
545 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
546 gen_cc_clear();
547 gen_cc_C_add(cpu_T[0], cpu_cc_src);
548 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
549 gen_cc_C_add(cpu_T[0], cpu_cc_src);
550 gen_cc_NZ(cpu_T[0]);
551 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
552}
553
554static inline void gen_op_tadd_T1_T0_cc(void)
555{
556 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
557 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
558 gen_cc_clear();
559 gen_cc_NZ(cpu_T[0]);
560 gen_cc_C_add(cpu_T[0], cpu_cc_src);
561 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
562 gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
563}
564
565static inline void gen_op_tadd_T1_T0_ccTV(void)
566{
567 gen_tag_tv(cpu_T[0], cpu_T[1]);
568 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
569 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
570 gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
571 gen_cc_clear();
572 gen_cc_NZ(cpu_T[0]);
573 gen_cc_C_add(cpu_T[0], cpu_cc_src);
574}
575
576/* old op:
577 if (src1 < T1)
578 env->psr |= PSR_CARRY;
579*/
580static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
581{
582 int l1;
583
584 l1 = gen_new_label();
585 tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
586 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
587 gen_set_label(l1);
588#ifdef TARGET_SPARC64
589 {
590 int l2;
591
592 l2 = gen_new_label();
593 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
594 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
595 gen_set_label(l2);
596 }
597#endif
598}
599
600/* old op:
601 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
602 env->psr |= PSR_OVF;
603*/
604static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
605{
0425bee5 606 TCGv r_temp;
dc99a3f2
BS		 607 int l1;
608
609 l1 = gen_new_label();
610
611 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 612 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 613 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
614 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
615 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
616 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
dc99a3f2
BS		 617 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
618 gen_set_label(l1);
619#ifdef TARGET_SPARC64
620 {
621 int l2;
622
623 l2 = gen_new_label();
dc99a3f2 624 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 625 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
626 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
627 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
628 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
dc99a3f2
BS		 629 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
630 gen_set_label(l2);
631 }
632#endif
0425bee5 633 tcg_gen_discard_tl(r_temp);
dc99a3f2
BS		 634}
635
636static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
637{
0425bee5 638 TCGv r_temp;
dc99a3f2
BS		 639 int l1;
640
641 l1 = gen_new_label();
642
643 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2 644 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 645 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
646 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
647 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
648 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_i32(0), l1);
dc99a3f2
BS		 649 gen_op_exception(TT_TOVF);
650 gen_set_label(l1);
651#ifdef TARGET_SPARC64
652 {
653 int l2;
654
655 l2 = gen_new_label();
dc99a3f2 656 tcg_gen_xor_tl(r_temp, src1, src2);
0425bee5
BS		 657 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
658 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
659 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
660 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
dc99a3f2
BS		 661 gen_op_exception(TT_TOVF);
662 gen_set_label(l2);
663 }
664#endif
0425bee5 665 tcg_gen_discard_tl(r_temp);
dc99a3f2
BS		 666}
667
668static inline void gen_op_sub_T1_T0_cc(void)
669{
670 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
671 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
672 gen_cc_clear();
673 gen_cc_NZ(cpu_T[0]);
674 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
675 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
676}
677
678static inline void gen_op_subx_T1_T0_cc(void)
679{
680 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
681 gen_mov_reg_C(cpu_tmp0, cpu_psr);
682 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
683 gen_cc_clear();
684 gen_cc_C_sub(cpu_T[0], cpu_cc_src);
685 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
686 gen_cc_C_sub(cpu_T[0], cpu_cc_src);
687 gen_cc_NZ(cpu_T[0]);
688 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
689}
690
691static inline void gen_op_tsub_T1_T0_cc(void)
692{
693 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
694 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
695 gen_cc_clear();
696 gen_cc_NZ(cpu_T[0]);
697 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
698 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
699 gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
700}
701
702static inline void gen_op_tsub_T1_T0_ccTV(void)
703{
704 gen_tag_tv(cpu_T[0], cpu_T[1]);
705 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
706 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
707 gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
708 gen_cc_clear();
709 gen_cc_NZ(cpu_T[0]);
710 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
711}
712
d9bdab86
BS		 713static inline void gen_op_mulscc_T1_T0(void)
714{
715 TCGv r_temp;
716 int l1, l2;
717
718 l1 = gen_new_label();
719 l2 = gen_new_label();
720 r_temp = tcg_temp_new(TCG_TYPE_TL);
721
722 /* old op:
723 if (!(env->y & 1))
724 T1 = 0;
725 */
726 tcg_gen_ld_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
727 tcg_gen_andi_i32(r_temp, r_temp, 0x1);
728 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
729 tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
730 gen_op_jmp_label(l2);
731 gen_set_label(l1);
732 tcg_gen_movi_tl(cpu_cc_src2, 0);
733 gen_set_label(l2);
734
735 // b2 = T0 & 1;
736 // env->y = (b2 << 31) | (env->y >> 1);
737 tcg_gen_shli_i32(r_temp, cpu_T[0], 31);
738 tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
739 tcg_gen_shri_i32(cpu_tmp0, cpu_tmp0, 1);
740 tcg_gen_or_i32(cpu_tmp0, cpu_tmp0, r_temp);
741 tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
742
743 // b1 = N ^ V;
744 gen_mov_reg_N(cpu_tmp0, cpu_psr);
745 gen_mov_reg_V(r_temp, cpu_psr);
746 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
747
748 // T0 = (b1 << 31) | (T0 >> 1);
749 // src1 = T0;
750 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
751 tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1);
752 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
753
754 /* do addition and update flags */
755 tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2);
756 tcg_gen_discard_tl(r_temp);
757
758 gen_cc_clear();
759 gen_cc_NZ(cpu_T[0]);
760 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2);
761 gen_cc_C_add(cpu_T[0], cpu_cc_src);
762}
763
1a7b60e7
BS		 764#ifdef TARGET_SPARC64
765static inline void gen_trap_ifdivzero_i64(TCGv divisor)
766{
767 int l1;
768
769 l1 = gen_new_label();
770 tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
771 gen_op_exception(TT_DIV_ZERO);
772 gen_set_label(l1);
773}
774
775static inline void gen_op_sdivx_T1_T0(void)
776{
777 int l1, l2;
778
779 l1 = gen_new_label();
780 l2 = gen_new_label();
781 gen_trap_ifdivzero_i64(cpu_T[1]);
782 tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1);
783 tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1);
784 tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
785 gen_op_jmp_label(l2);
786 gen_set_label(l1);
787 tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
788 gen_set_label(l2);
789}
790#endif
791
dc99a3f2
BS		 792static inline void gen_op_div_cc(void)
793{
794 int l1;
dc99a3f2
BS		 795
796 gen_cc_clear();
797 gen_cc_NZ(cpu_T[0]);
798 l1 = gen_new_label();
0425bee5 799 tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], tcg_const_i32(0), l1);
dc99a3f2
BS		 800 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
801 gen_set_label(l1);
802}
803
804static inline void gen_op_logic_T0_cc(void)
805{
806 gen_cc_clear();
807 gen_cc_NZ(cpu_T[0]);
808}
809
19f329ad
BS		 810// 1
811static inline void gen_op_eval_ba(TCGv dst)
812{
813 tcg_gen_movi_tl(dst, 1);
814}
815
816// Z
817static inline void gen_op_eval_be(TCGv dst, TCGv src)
818{
819 gen_mov_reg_Z(dst, src);
820}
821
822// Z | (N ^ V)
823static inline void gen_op_eval_ble(TCGv dst, TCGv src)
824{
0425bee5 825 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 826 gen_mov_reg_V(dst, src);
0425bee5
BS		 827 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
828 gen_mov_reg_Z(cpu_tmp0, src);
829 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 830}
831
832// N ^ V
833static inline void gen_op_eval_bl(TCGv dst, TCGv src)
834{
0425bee5 835 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 836 gen_mov_reg_N(dst, src);
0425bee5 837 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 838}
839
840// C | Z
841static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
842{
0425bee5 843 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 844 gen_mov_reg_C(dst, src);
0425bee5 845 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 846}
847
848// C
849static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
850{
851 gen_mov_reg_C(dst, src);
852}
853
854// V
855static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
856{
857 gen_mov_reg_V(dst, src);
858}
859
860// 0
861static inline void gen_op_eval_bn(TCGv dst)
862{
863 tcg_gen_movi_tl(dst, 0);
864}
865
866// N
867static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
868{
869 gen_mov_reg_N(dst, src);
870}
871
872// !Z
873static inline void gen_op_eval_bne(TCGv dst, TCGv src)
874{
875 gen_mov_reg_Z(dst, src);
876 tcg_gen_xori_tl(dst, dst, 0x1);
877}
878
879// !(Z | (N ^ V))
880static inline void gen_op_eval_bg(TCGv dst, TCGv src)
881{
0425bee5 882 gen_mov_reg_N(cpu_tmp0, src);
19f329ad 883 gen_mov_reg_V(dst, src);
0425bee5
BS		 884 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
885 gen_mov_reg_Z(cpu_tmp0, src);
886 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 887 tcg_gen_xori_tl(dst, dst, 0x1);
888}
889
890// !(N ^ V)
891static inline void gen_op_eval_bge(TCGv dst, TCGv src)
892{
0425bee5 893 gen_mov_reg_V(cpu_tmp0, src);
19f329ad 894 gen_mov_reg_N(dst, src);
0425bee5 895 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 896 tcg_gen_xori_tl(dst, dst, 0x1);
897}
898
899// !(C | Z)
900static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
901{
0425bee5 902 gen_mov_reg_Z(cpu_tmp0, src);
19f329ad 903 gen_mov_reg_C(dst, src);
0425bee5 904 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 905 tcg_gen_xori_tl(dst, dst, 0x1);
906}
907
908// !C
909static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
910{
911 gen_mov_reg_C(dst, src);
912 tcg_gen_xori_tl(dst, dst, 0x1);
913}
914
915// !N
916static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
917{
918 gen_mov_reg_N(dst, src);
919 tcg_gen_xori_tl(dst, dst, 0x1);
920}
921
922// !V
923static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
924{
925 gen_mov_reg_V(dst, src);
926 tcg_gen_xori_tl(dst, dst, 0x1);
927}
928
929/*
930 FPSR bit field FCC1 | FCC0:
931 0 =
932 1 <
933 2 >
934 3 unordered
935*/
936static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
937 unsigned int fcc_offset)
938{
939 tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
940 tcg_gen_andi_tl(reg, reg, 0x1);
941}
942
943static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
944 unsigned int fcc_offset)
945{
946 tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
947 tcg_gen_andi_tl(reg, reg, 0x1);
948}
949
950// !0: FCC0 | FCC1
951static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
952 unsigned int fcc_offset)
953{
19f329ad 954 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 955 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
956 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 957}
958
959// 1 or 2: FCC0 ^ FCC1
960static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
961 unsigned int fcc_offset)
962{
19f329ad 963 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 964 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
965 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 966}
967
968// 1 or 3: FCC0
969static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
970 unsigned int fcc_offset)
971{
972 gen_mov_reg_FCC0(dst, src, fcc_offset);
973}
974
975// 1: FCC0 & !FCC1
976static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
977 unsigned int fcc_offset)
978{
19f329ad 979 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 980 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
981 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
982 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 983}
984
985// 2 or 3: FCC1
986static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
987 unsigned int fcc_offset)
988{
989 gen_mov_reg_FCC1(dst, src, fcc_offset);
990}
991
992// 2: !FCC0 & FCC1
993static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
994 unsigned int fcc_offset)
995{
19f329ad
BS		 996 gen_mov_reg_FCC0(dst, src, fcc_offset);
997 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 998 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
999 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1000}
1001
1002// 3: FCC0 & FCC1
1003static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1004 unsigned int fcc_offset)
1005{
19f329ad 1006 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1007 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1008 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1009}
1010
1011// 0: !(FCC0 | FCC1)
1012static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1013 unsigned int fcc_offset)
1014{
19f329ad 1015 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1016 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1017 tcg_gen_or_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1018 tcg_gen_xori_tl(dst, dst, 0x1);
1019}
1020
1021// 0 or 3: !(FCC0 ^ FCC1)
1022static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1023 unsigned int fcc_offset)
1024{
19f329ad 1025 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1026 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1027 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1028 tcg_gen_xori_tl(dst, dst, 0x1);
1029}
1030
1031// 0 or 2: !FCC0
1032static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1033 unsigned int fcc_offset)
1034{
1035 gen_mov_reg_FCC0(dst, src, fcc_offset);
1036 tcg_gen_xori_tl(dst, dst, 0x1);
1037}
1038
1039// !1: !(FCC0 & !FCC1)
1040static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1041 unsigned int fcc_offset)
1042{
19f329ad 1043 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1044 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1045 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1046 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1047 tcg_gen_xori_tl(dst, dst, 0x1);
1048}
1049
1050// 0 or 1: !FCC1
1051static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1052 unsigned int fcc_offset)
1053{
1054 gen_mov_reg_FCC1(dst, src, fcc_offset);
1055 tcg_gen_xori_tl(dst, dst, 0x1);
1056}
1057
1058// !2: !(!FCC0 & FCC1)
1059static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1060 unsigned int fcc_offset)
1061{
19f329ad
BS		 1062 gen_mov_reg_FCC0(dst, src, fcc_offset);
1063 tcg_gen_xori_tl(dst, dst, 0x1);
0425bee5
BS		 1064 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1065 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1066 tcg_gen_xori_tl(dst, dst, 0x1);
1067}
1068
1069// !3: !(FCC0 & FCC1)
1070static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1071 unsigned int fcc_offset)
1072{
19f329ad 1073 gen_mov_reg_FCC0(dst, src, fcc_offset);
0425bee5
BS		 1074 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1075 tcg_gen_and_tl(dst, dst, cpu_tmp0);
19f329ad
BS		 1076 tcg_gen_xori_tl(dst, dst, 0x1);
1077}
1078
46525e1f 1079static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 1080 target_ulong pc2, TCGv r_cond)
83469015
FB		 1081{
1082 int l1;
1083
1084 l1 = gen_new_label();
1085
0425bee5 1086 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1087
6e256c93 1088 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1089
1090 gen_set_label(l1);
6e256c93 1091 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1092}
1093
46525e1f 1094static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 1095 target_ulong pc2, TCGv r_cond)
83469015
FB		 1096{
1097 int l1;
1098
1099 l1 = gen_new_label();
1100
0425bee5 1101 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015 1102
6e256c93 1103 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 1104
1105 gen_set_label(l1);
6e256c93 1106 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 1107}
1108
46525e1f
BS		 1109static inline void gen_branch(DisasContext *dc, target_ulong pc,
1110 target_ulong npc)
83469015 1111{
6e256c93 1112 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 1113}
1114
19f329ad
BS		 1115static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1116 TCGv r_cond)
83469015
FB		 1117{
1118 int l1, l2;
1119
1120 l1 = gen_new_label();
1121 l2 = gen_new_label();
19f329ad 1122
0425bee5 1123 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
83469015
FB		 1124
1125 gen_movl_npc_im(npc1);
1126 gen_op_jmp_label(l2);
1127
1128 gen_set_label(l1);
1129 gen_movl_npc_im(npc2);
1130 gen_set_label(l2);
1131}
1132
1133/* call this function before using T2 as it may have been set for a jump */
1134static inline void flush_T2(DisasContext * dc)
1135{
1136 if (dc->npc == JUMP_PC) {
19f329ad 1137 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
83469015
FB		 1138 dc->npc = DYNAMIC_PC;
1139 }
1140}
1141
72cbca10
FB		 1142static inline void save_npc(DisasContext * dc)
1143{
1144 if (dc->npc == JUMP_PC) {
19f329ad 1145 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
72cbca10
FB		 1146 dc->npc = DYNAMIC_PC;
1147 } else if (dc->npc != DYNAMIC_PC) {
3475187d 1148 gen_movl_npc_im(dc->npc);
72cbca10
FB		 1149 }
1150}
1151
1152static inline void save_state(DisasContext * dc)
1153{
3475187d 1154 gen_jmp_im(dc->pc);
72cbca10
FB		 1155 save_npc(dc);
1156}
1157
0bee699e
FB		 1158static inline void gen_mov_pc_npc(DisasContext * dc)
1159{
1160 if (dc->npc == JUMP_PC) {
19f329ad 1161 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
38bc628b
BS		 1162 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1163 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 1164 dc->pc = DYNAMIC_PC;
1165 } else if (dc->npc == DYNAMIC_PC) {
38bc628b
BS		 1166 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1167 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 1168 dc->pc = DYNAMIC_PC;
1169 } else {
1170 dc->pc = dc->npc;
1171 }
1172}
1173
38bc628b
BS		 1174static inline void gen_op_next_insn(void)
1175{
1176 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1177 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1178 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
1179 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1180}
1181
19f329ad
BS		 1182static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1183{
1184 TCGv r_src;
3475187d 1185
3475187d 1186#ifdef TARGET_SPARC64
19f329ad 1187 if (cc)
dc99a3f2 1188 r_src = cpu_xcc;
19f329ad 1189 else
dc99a3f2 1190 r_src = cpu_psr;
3475187d 1191#else
dc99a3f2 1192 r_src = cpu_psr;
3475187d 1193#endif
19f329ad
BS		 1194 switch (cond) {
1195 case 0x0:
1196 gen_op_eval_bn(r_dst);
1197 break;
1198 case 0x1:
1199 gen_op_eval_be(r_dst, r_src);
1200 break;
1201 case 0x2:
1202 gen_op_eval_ble(r_dst, r_src);
1203 break;
1204 case 0x3:
1205 gen_op_eval_bl(r_dst, r_src);
1206 break;
1207 case 0x4:
1208 gen_op_eval_bleu(r_dst, r_src);
1209 break;
1210 case 0x5:
1211 gen_op_eval_bcs(r_dst, r_src);
1212 break;
1213 case 0x6:
1214 gen_op_eval_bneg(r_dst, r_src);
1215 break;
1216 case 0x7:
1217 gen_op_eval_bvs(r_dst, r_src);
1218 break;
1219 case 0x8:
1220 gen_op_eval_ba(r_dst);
1221 break;
1222 case 0x9:
1223 gen_op_eval_bne(r_dst, r_src);
1224 break;
1225 case 0xa:
1226 gen_op_eval_bg(r_dst, r_src);
1227 break;
1228 case 0xb:
1229 gen_op_eval_bge(r_dst, r_src);
1230 break;
1231 case 0xc:
1232 gen_op_eval_bgu(r_dst, r_src);
1233 break;
1234 case 0xd:
1235 gen_op_eval_bcc(r_dst, r_src);
1236 break;
1237 case 0xe:
1238 gen_op_eval_bpos(r_dst, r_src);
1239 break;
1240 case 0xf:
1241 gen_op_eval_bvc(r_dst, r_src);
1242 break;
1243 }
1244}
7a3f1944 1245
19f329ad 1246static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
e8af50a3 1247{
19f329ad
BS		 1248 unsigned int offset;
1249
19f329ad
BS		 1250 switch (cc) {
1251 default:
1252 case 0x0:
1253 offset = 0;
1254 break;
1255 case 0x1:
1256 offset = 32 - 10;
1257 break;
1258 case 0x2:
1259 offset = 34 - 10;
1260 break;
1261 case 0x3:
1262 offset = 36 - 10;
1263 break;
1264 }
1265
1266 switch (cond) {
1267 case 0x0:
1268 gen_op_eval_bn(r_dst);
1269 break;
1270 case 0x1:
87e92502 1271 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1272 break;
1273 case 0x2:
87e92502 1274 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1275 break;
1276 case 0x3:
87e92502 1277 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1278 break;
1279 case 0x4:
87e92502 1280 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1281 break;
1282 case 0x5:
87e92502 1283 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1284 break;
1285 case 0x6:
87e92502 1286 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1287 break;
1288 case 0x7:
87e92502 1289 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1290 break;
1291 case 0x8:
1292 gen_op_eval_ba(r_dst);
1293 break;
1294 case 0x9:
87e92502 1295 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1296 break;
1297 case 0xa:
87e92502 1298 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1299 break;
1300 case 0xb:
87e92502 1301 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1302 break;
1303 case 0xc:
87e92502 1304 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1305 break;
1306 case 0xd:
87e92502 1307 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1308 break;
1309 case 0xe:
87e92502 1310 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1311 break;
1312 case 0xf:
87e92502 1313 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1314 break;
1315 }
e8af50a3 1316}
00f219bf 1317
19f329ad 1318#ifdef TARGET_SPARC64
00f219bf
BS		 1319// Inverted logic
1320static const int gen_tcg_cond_reg[8] = {
1321 -1,
1322 TCG_COND_NE,
1323 TCG_COND_GT,
1324 TCG_COND_GE,
1325 -1,
1326 TCG_COND_EQ,
1327 TCG_COND_LE,
1328 TCG_COND_LT,
1329};
19f329ad
BS		 1330
1331static inline void gen_cond_reg(TCGv r_dst, int cond)
1332{
19f329ad
BS		 1333 int l1;
1334
1335 l1 = gen_new_label();
0425bee5
BS		 1336 tcg_gen_movi_tl(r_dst, 0);
1337 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1);
19f329ad
BS		 1338 tcg_gen_movi_tl(r_dst, 1);
1339 gen_set_label(l1);
1340}
3475187d 1341#endif
cf495bcf 1342
0bee699e 1343/* XXX: potentially incorrect if dynamic npc */
3475187d 1344static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1345{
cf495bcf 1346 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1347 target_ulong target = dc->pc + offset;
5fafdf24 1348
cf495bcf 1349 if (cond == 0x0) {
0f8a249a
BS		 1350 /* unconditional not taken */
1351 if (a) {
1352 dc->pc = dc->npc + 4;
1353 dc->npc = dc->pc + 4;
1354 } else {
1355 dc->pc = dc->npc;
1356 dc->npc = dc->pc + 4;
1357 }
cf495bcf 1358 } else if (cond == 0x8) {
0f8a249a
BS		 1359 /* unconditional taken */
1360 if (a) {
1361 dc->pc = target;
1362 dc->npc = dc->pc + 4;
1363 } else {
1364 dc->pc = dc->npc;
1365 dc->npc = target;
1366 }
cf495bcf 1367 } else {
72cbca10 1368 flush_T2(dc);
19f329ad 1369 gen_cond(cpu_T[2], cc, cond);
0f8a249a 1370 if (a) {
19f329ad 1371 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
cf495bcf 1372 dc->is_br = 1;
0f8a249a 1373 } else {
cf495bcf 1374 dc->pc = dc->npc;
72cbca10
FB		 1375 dc->jump_pc[0] = target;
1376 dc->jump_pc[1] = dc->npc + 4;
1377 dc->npc = JUMP_PC;
0f8a249a 1378 }
cf495bcf 1379 }
7a3f1944
FB		 1380}
1381
0bee699e 1382/* XXX: potentially incorrect if dynamic npc */
3475187d 1383static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1384{
1385 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1386 target_ulong target = dc->pc + offset;
1387
e8af50a3 1388 if (cond == 0x0) {
0f8a249a
BS		 1389 /* unconditional not taken */
1390 if (a) {
1391 dc->pc = dc->npc + 4;
1392 dc->npc = dc->pc + 4;
1393 } else {
1394 dc->pc = dc->npc;
1395 dc->npc = dc->pc + 4;
1396 }
e8af50a3 1397 } else if (cond == 0x8) {
0f8a249a
BS		 1398 /* unconditional taken */
1399 if (a) {
1400 dc->pc = target;
1401 dc->npc = dc->pc + 4;
1402 } else {
1403 dc->pc = dc->npc;
1404 dc->npc = target;
1405 }
e8af50a3
FB		 1406 } else {
1407 flush_T2(dc);
19f329ad 1408 gen_fcond(cpu_T[2], cc, cond);
0f8a249a 1409 if (a) {
19f329ad 1410 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
e8af50a3 1411 dc->is_br = 1;
0f8a249a 1412 } else {
e8af50a3
FB		 1413 dc->pc = dc->npc;
1414 dc->jump_pc[0] = target;
1415 dc->jump_pc[1] = dc->npc + 4;
1416 dc->npc = JUMP_PC;
0f8a249a 1417 }
e8af50a3
FB		 1418 }
1419}
1420
3475187d
FB		 1421#ifdef TARGET_SPARC64
1422/* XXX: potentially incorrect if dynamic npc */
1423static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 1424{
3475187d
FB		 1425 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1426 target_ulong target = dc->pc + offset;
1427
1428 flush_T2(dc);
19f329ad 1429 gen_cond_reg(cpu_T[2], cond);
3475187d 1430 if (a) {
19f329ad 1431 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
0f8a249a 1432 dc->is_br = 1;
3475187d 1433 } else {
0f8a249a
BS		 1434 dc->pc = dc->npc;
1435 dc->jump_pc[0] = target;
1436 dc->jump_pc[1] = dc->npc + 4;
1437 dc->npc = JUMP_PC;
3475187d 1438 }
7a3f1944
FB		 1439}
1440
3475187d 1441static GenOpFunc * const gen_fcmps[4] = {
7e8c2b6c
BS		 1442 helper_fcmps,
1443 helper_fcmps_fcc1,
1444 helper_fcmps_fcc2,
1445 helper_fcmps_fcc3,
3475187d
FB		 1446};
1447
1448static GenOpFunc * const gen_fcmpd[4] = {
7e8c2b6c
BS		 1449 helper_fcmpd,
1450 helper_fcmpd_fcc1,
1451 helper_fcmpd_fcc2,
1452 helper_fcmpd_fcc3,
3475187d 1453};
417454b0 1454
1f587329
BS		 1455#if defined(CONFIG_USER_ONLY)
1456static GenOpFunc * const gen_fcmpq[4] = {
7e8c2b6c
BS		 1457 helper_fcmpq,
1458 helper_fcmpq_fcc1,
1459 helper_fcmpq_fcc2,
1460 helper_fcmpq_fcc3,
1f587329
BS		 1461};
1462#endif
1463
417454b0 1464static GenOpFunc * const gen_fcmpes[4] = {
7e8c2b6c
BS		 1465 helper_fcmpes,
1466 helper_fcmpes_fcc1,
1467 helper_fcmpes_fcc2,
1468 helper_fcmpes_fcc3,
417454b0
BS		 1469};
1470
1471static GenOpFunc * const gen_fcmped[4] = {
7e8c2b6c
BS		 1472 helper_fcmped,
1473 helper_fcmped_fcc1,
1474 helper_fcmped_fcc2,
1475 helper_fcmped_fcc3,
417454b0
BS		 1476};
1477
1f587329
BS		 1478#if defined(CONFIG_USER_ONLY)
1479static GenOpFunc * const gen_fcmpeq[4] = {
7e8c2b6c
BS		 1480 helper_fcmpeq,
1481 helper_fcmpeq_fcc1,
1482 helper_fcmpeq_fcc2,
1483 helper_fcmpeq_fcc3,
1f587329
BS		 1484};
1485#endif
7e8c2b6c
BS		 1486
1487static inline void gen_op_fcmps(int fccno)
1488{
1489 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1490}
1491
1492static inline void gen_op_fcmpd(int fccno)
1493{
1494 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1495}
1496
1497#if defined(CONFIG_USER_ONLY)
1498static inline void gen_op_fcmpq(int fccno)
1499{
1500 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1501}
1502#endif
1503
1504static inline void gen_op_fcmpes(int fccno)
1505{
1506 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1507}
1508
1509static inline void gen_op_fcmped(int fccno)
1510{
1511 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1512}
1513
1514#if defined(CONFIG_USER_ONLY)
1515static inline void gen_op_fcmpeq(int fccno)
1516{
1517 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1518}
1519#endif
1520
1521#else
1522
1523static inline void gen_op_fcmps(int fccno)
1524{
1525 tcg_gen_helper_0_0(helper_fcmps);
1526}
1527
1528static inline void gen_op_fcmpd(int fccno)
1529{
1530 tcg_gen_helper_0_0(helper_fcmpd);
1531}
1532
1533#if defined(CONFIG_USER_ONLY)
1534static inline void gen_op_fcmpq(int fccno)
1535{
1536 tcg_gen_helper_0_0(helper_fcmpq);
1537}
1538#endif
1539
1540static inline void gen_op_fcmpes(int fccno)
1541{
1542 tcg_gen_helper_0_0(helper_fcmpes);
1543}
1544
1545static inline void gen_op_fcmped(int fccno)
1546{
1547 tcg_gen_helper_0_0(helper_fcmped);
1548}
1549
1550#if defined(CONFIG_USER_ONLY)
1551static inline void gen_op_fcmpeq(int fccno)
1552{
1553 tcg_gen_helper_0_0(helper_fcmpeq);
1554}
1555#endif
1556
3475187d
FB		 1557#endif
1558
134d77a1
BS		 1559static inline void gen_op_fpexception_im(int fsr_flags)
1560{
87e92502
BS		 1561 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1562 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
134d77a1
BS		 1563 gen_op_exception(TT_FP_EXCP);
1564}
1565
a80dde08
FB		 1566static int gen_trap_ifnofpu(DisasContext * dc)
1567{
1568#if !defined(CONFIG_USER_ONLY)
1569 if (!dc->fpu_enabled) {
1570 save_state(dc);
1571 gen_op_exception(TT_NFPU_INSN);
1572 dc->is_br = 1;
1573 return 1;
1574 }
1575#endif
1576 return 0;
1577}
1578
7e8c2b6c
BS		 1579static inline void gen_op_clear_ieee_excp_and_FTT(void)
1580{
87e92502 1581 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
7e8c2b6c
BS		 1582}
1583
1584static inline void gen_clear_float_exceptions(void)
1585{
1586 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1587}
1588
1a2fb1c0
BS		 1589/* asi moves */
1590#ifdef TARGET_SPARC64
0425bee5 1591static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0
BS		 1592{
1593 int asi, offset;
0425bee5 1594 TCGv r_asi;
1a2fb1c0 1595
1a2fb1c0 1596 if (IS_IMM) {
0425bee5 1597 r_asi = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1598 offset = GET_FIELD(insn, 25, 31);
0425bee5
BS		 1599 tcg_gen_addi_tl(r_addr, r_addr, offset);
1600 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1a2fb1c0
BS		 1601 } else {
1602 asi = GET_FIELD(insn, 19, 26);
0425bee5 1603 r_asi = tcg_const_i32(asi);
1a2fb1c0 1604 }
0425bee5
BS		 1605 return r_asi;
1606}
1607
1608static inline void gen_ld_asi(int insn, int size, int sign)
1609{
1610 TCGv r_asi;
1611
1612 r_asi = gen_get_asi(insn, cpu_T[0]);
1613 tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi,
1614 tcg_const_i32(size), tcg_const_i32(sign));
1615 tcg_gen_discard_i32(r_asi);
1a2fb1c0
BS		 1616}
1617
1618static inline void gen_st_asi(int insn, int size)
1619{
0425bee5 1620 TCGv r_asi;
1a2fb1c0 1621
0425bee5
BS		 1622 r_asi = gen_get_asi(insn, cpu_T[0]);
1623 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi,
1624 tcg_const_i32(size));
1625 tcg_gen_discard_i32(r_asi);
1a2fb1c0
BS		 1626}
1627
1628static inline void gen_ldf_asi(int insn, int size, int rd)
1629{
0425bee5 1630 TCGv r_asi;
1a2fb1c0 1631
0425bee5
BS		 1632 r_asi = gen_get_asi(insn, cpu_T[0]);
1633 tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
1634 tcg_const_i32(rd));
1635 tcg_gen_discard_i32(r_asi);
1a2fb1c0
BS		 1636}
1637
1638static inline void gen_stf_asi(int insn, int size, int rd)
1639{
0425bee5 1640 TCGv r_asi;
1a2fb1c0 1641
0425bee5
BS		 1642 r_asi = gen_get_asi(insn, cpu_T[0]);
1643 tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
1644 tcg_const_i32(rd));
1645 tcg_gen_discard_i32(r_asi);
1a2fb1c0
BS		 1646}
1647
1648static inline void gen_swap_asi(int insn)
1649{
0425bee5 1650 TCGv r_temp, r_asi;
1a2fb1c0 1651
1a2fb1c0 1652 r_temp = tcg_temp_new(TCG_TYPE_I32);
0425bee5
BS		 1653 r_asi = gen_get_asi(insn, cpu_T[0]);
1654 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi,
1655 tcg_const_i32(4), tcg_const_i32(0));
1656 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
1657 tcg_const_i32(4));
1a2fb1c0 1658 tcg_gen_mov_i32(cpu_T[1], r_temp);
0425bee5
BS		 1659 tcg_gen_discard_i32(r_asi);
1660 tcg_gen_discard_i32(r_temp);
1a2fb1c0
BS		 1661}
1662
1663static inline void gen_ldda_asi(int insn)
1664{
0425bee5 1665 TCGv r_dword, r_asi;
1a2fb1c0 1666
1a2fb1c0 1667 r_dword = tcg_temp_new(TCG_TYPE_I64);
0425bee5
BS		 1668 r_asi = gen_get_asi(insn, cpu_T[0]);
1669 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], r_asi,
1670 tcg_const_i32(8), tcg_const_i32(0));
1a2fb1c0
BS		 1671 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1672 tcg_gen_shri_i64(r_dword, r_dword, 32);
1673 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
0425bee5
BS		 1674 tcg_gen_discard_i32(r_asi);
1675 tcg_gen_discard_i64(r_dword);
1676}
1677
1678static inline void gen_stda_asi(int insn, int rd)
1679{
1680 TCGv r_dword, r_temp, r_asi;
1681
1682 r_dword = tcg_temp_new(TCG_TYPE_I64);
1683 r_temp = tcg_temp_new(TCG_TYPE_I32);
1684 gen_movl_reg_TN(rd + 1, r_temp);
1685 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
1686 r_temp);
1687 r_asi = gen_get_asi(insn, cpu_T[0]);
1688 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi,
1689 tcg_const_i32(8));
1690 tcg_gen_discard_i32(r_asi);
1691 tcg_gen_discard_i32(r_temp);
1692 tcg_gen_discard_i64(r_dword);
1a2fb1c0
BS		 1693}
1694
1695static inline void gen_cas_asi(int insn, int rd)
1696{
1a2fb1c0
BS		 1697 TCGv r_val1, r_asi;
1698
1699 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1700 gen_movl_reg_TN(rd, r_val1);
0425bee5 1701 r_asi = gen_get_asi(insn, cpu_T[0]);
1a2fb1c0
BS		 1702 tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1703 r_asi);
0425bee5
BS		 1704 tcg_gen_discard_i32(r_asi);
1705 tcg_gen_discard_i32(r_val1);
1a2fb1c0
BS		 1706}
1707
1708static inline void gen_casx_asi(int insn, int rd)
1709{
1a2fb1c0
BS		 1710 TCGv r_val1, r_asi;
1711
1712 r_val1 = tcg_temp_new(TCG_TYPE_I64);
1a2fb1c0 1713 gen_movl_reg_TN(rd, r_val1);
0425bee5 1714 r_asi = gen_get_asi(insn, cpu_T[0]);
1a2fb1c0
BS		 1715 tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1716 r_asi);
0425bee5
BS		 1717 tcg_gen_discard_i32(r_asi);
1718 tcg_gen_discard_i32(r_val1);
1a2fb1c0
BS		 1719}
1720
1721#elif !defined(CONFIG_USER_ONLY)
1722
1723static inline void gen_ld_asi(int insn, int size, int sign)
1724{
1725 int asi;
0425bee5 1726 TCGv r_dword;
1a2fb1c0 1727
1a2fb1c0 1728 r_dword = tcg_temp_new(TCG_TYPE_I64);
1a2fb1c0 1729 asi = GET_FIELD(insn, 19, 26);
0425bee5
BS		 1730 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
1731 tcg_const_i32(size), tcg_const_i32(sign));
1a2fb1c0 1732 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
0425bee5 1733 tcg_gen_discard_i64(r_dword);
1a2fb1c0
BS		 1734}
1735
1736static inline void gen_st_asi(int insn, int size)
1737{
1738 int asi;
0425bee5 1739 TCGv r_dword;
1a2fb1c0
BS		 1740
1741 r_dword = tcg_temp_new(TCG_TYPE_I64);
1742 tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
1a2fb1c0 1743 asi = GET_FIELD(insn, 19, 26);
0425bee5
BS		 1744 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
1745 tcg_const_i32(size));
1746 tcg_gen_discard_i64(r_dword);
1a2fb1c0
BS		 1747}
1748
1749static inline void gen_swap_asi(int insn)
1750{
1751 int asi;
0425bee5 1752 TCGv r_temp;
1a2fb1c0 1753
1a2fb1c0 1754 r_temp = tcg_temp_new(TCG_TYPE_I32);
1a2fb1c0 1755 asi = GET_FIELD(insn, 19, 26);
0425bee5
BS		 1756 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi),
1757 tcg_const_i32(4), tcg_const_i32(0));
1758 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi),
1759 tcg_const_i32(4));
1a2fb1c0 1760 tcg_gen_mov_i32(cpu_T[1], r_temp);
0425bee5 1761 tcg_gen_discard_i32(r_temp);
1a2fb1c0
BS		 1762}
1763
1764static inline void gen_ldda_asi(int insn)
1765{
1766 int asi;
0425bee5 1767 TCGv r_dword;
1a2fb1c0 1768
1a2fb1c0 1769 r_dword = tcg_temp_new(TCG_TYPE_I64);
1a2fb1c0 1770 asi = GET_FIELD(insn, 19, 26);
0425bee5
BS		 1771 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], tcg_const_i32(asi),
1772 tcg_const_i32(8), tcg_const_i32(0));
1a2fb1c0
BS		 1773 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1774 tcg_gen_shri_i64(r_dword, r_dword, 32);
1775 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
0425bee5
BS		 1776 tcg_gen_discard_i64(r_dword);
1777}
1778
1779static inline void gen_stda_asi(int insn, int rd)
1780{
1781 int asi;
1782 TCGv r_dword, r_temp;
1783
1784 r_dword = tcg_temp_new(TCG_TYPE_I64);
1785 r_temp = tcg_temp_new(TCG_TYPE_I32);
1786 gen_movl_reg_TN(rd + 1, r_temp);
1787 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1], r_temp);
1788 asi = GET_FIELD(insn, 19, 26);
1789 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, tcg_const_i32(asi),
1790 tcg_const_i32(8));
1791 tcg_gen_discard_i64(r_dword);
1a2fb1c0
BS		 1792}
1793#endif
1794
1795#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1796static inline void gen_ldstub_asi(int insn)
1797{
1798 int asi;
1a2fb1c0
BS		 1799
1800 gen_ld_asi(insn, 1, 0);
1801
1a2fb1c0 1802 asi = GET_FIELD(insn, 19, 26);
0425bee5
BS		 1803 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xff),
1804 tcg_const_i32(asi), tcg_const_i32(1));
1a2fb1c0
BS		 1805}
1806#endif
1807
0bee699e 1808/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1809static void disas_sparc_insn(DisasContext * dc)
1810{
1811 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1812
0fa85d43 1813 insn = ldl_code(dc->pc);
cf495bcf 1814 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1815
cf495bcf
FB		 1816 rd = GET_FIELD(insn, 2, 6);
1817 switch (opc) {
0f8a249a
BS		 1818 case 0: /* branches/sethi */
1819 {
1820 unsigned int xop = GET_FIELD(insn, 7, 9);
1821 int32_t target;
1822 switch (xop) {
3475187d 1823#ifdef TARGET_SPARC64
0f8a249a
BS		 1824 case 0x1: /* V9 BPcc */
1825 {
1826 int cc;
1827
1828 target = GET_FIELD_SP(insn, 0, 18);
1829 target = sign_extend(target, 18);
1830 target <<= 2;
1831 cc = GET_FIELD_SP(insn, 20, 21);
1832 if (cc == 0)
1833 do_branch(dc, target, insn, 0);
1834 else if (cc == 2)
1835 do_branch(dc, target, insn, 1);
1836 else
1837 goto illegal_insn;
1838 goto jmp_insn;
1839 }
1840 case 0x3: /* V9 BPr */
1841 {
1842 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1843 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1844 target = sign_extend(target, 16);
1845 target <<= 2;
1846 rs1 = GET_FIELD(insn, 13, 17);
1847 gen_movl_reg_T0(rs1);
1848 do_branch_reg(dc, target, insn);
1849 goto jmp_insn;
1850 }
1851 case 0x5: /* V9 FBPcc */
1852 {
1853 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1854 if (gen_trap_ifnofpu(dc))
1855 goto jmp_insn;
0f8a249a
BS		 1856 target = GET_FIELD_SP(insn, 0, 18);
1857 target = sign_extend(target, 19);
1858 target <<= 2;
1859 do_fbranch(dc, target, insn, cc);
1860 goto jmp_insn;
1861 }
a4d17f19 1862#else
0f8a249a
BS		 1863 case 0x7: /* CBN+x */
1864 {
1865 goto ncp_insn;
1866 }
1867#endif
1868 case 0x2: /* BN+x */
1869 {
1870 target = GET_FIELD(insn, 10, 31);
1871 target = sign_extend(target, 22);
1872 target <<= 2;
1873 do_branch(dc, target, insn, 0);
1874 goto jmp_insn;
1875 }
1876 case 0x6: /* FBN+x */
1877 {
a80dde08
FB		 1878 if (gen_trap_ifnofpu(dc))
1879 goto jmp_insn;
0f8a249a
BS		 1880 target = GET_FIELD(insn, 10, 31);
1881 target = sign_extend(target, 22);
1882 target <<= 2;
1883 do_fbranch(dc, target, insn, 0);
1884 goto jmp_insn;
1885 }
1886 case 0x4: /* SETHI */
e80cfcfc
FB		 1887#define OPTIM
1888#if defined(OPTIM)
0f8a249a 1889 if (rd) { // nop
e80cfcfc 1890#endif
0f8a249a 1891 uint32_t value = GET_FIELD(insn, 10, 31);
1a2fb1c0 1892 tcg_gen_movi_tl(cpu_T[0], value << 10);
0f8a249a 1893 gen_movl_T0_reg(rd);
e80cfcfc 1894#if defined(OPTIM)
0f8a249a 1895 }
e80cfcfc 1896#endif
0f8a249a
BS		 1897 break;
1898 case 0x0: /* UNIMPL */
1899 default:
3475187d 1900 goto illegal_insn;
0f8a249a
BS		 1901 }
1902 break;
1903 }
1904 break;
cf495bcf 1905 case 1:
0f8a249a
BS		 1906 /*CALL*/ {
1907 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1908
1a2fb1c0 1909 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 1910 gen_movl_T0_reg(15);
1911 target += dc->pc;
0bee699e 1912 gen_mov_pc_npc(dc);
0f8a249a
BS		 1913 dc->npc = target;
1914 }
1915 goto jmp_insn;
1916 case 2: /* FPU & Logical Operations */
1917 {
1918 unsigned int xop = GET_FIELD(insn, 7, 12);
1919 if (xop == 0x3a) { /* generate trap */
cf495bcf 1920 int cond;
3475187d 1921
cf495bcf
FB		 1922 rs1 = GET_FIELD(insn, 13, 17);
1923 gen_movl_reg_T0(rs1);
0f8a249a
BS		 1924 if (IS_IMM) {
1925 rs2 = GET_FIELD(insn, 25, 31);
1a2fb1c0 1926 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
cf495bcf
FB		 1927 } else {
1928 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 1929#if defined(OPTIM)
0f8a249a 1930 if (rs2 != 0) {
e80cfcfc 1931#endif
0f8a249a
BS		 1932 gen_movl_reg_T1(rs2);
1933 gen_op_add_T1_T0();
e80cfcfc 1934#if defined(OPTIM)
0f8a249a 1935 }
e80cfcfc 1936#endif
cf495bcf 1937 }
cf495bcf
FB		 1938 cond = GET_FIELD(insn, 3, 6);
1939 if (cond == 0x8) {
a80dde08 1940 save_state(dc);
1a2fb1c0 1941 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
af7bf89b 1942 } else if (cond != 0) {
748b9d8e 1943 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
3475187d 1944#ifdef TARGET_SPARC64
0f8a249a
BS		 1945 /* V9 icc/xcc */
1946 int cc = GET_FIELD_SP(insn, 11, 12);
748b9d8e 1947
a80dde08 1948 save_state(dc);
0f8a249a 1949 if (cc == 0)
748b9d8e 1950 gen_cond(r_cond, 0, cond);
0f8a249a 1951 else if (cc == 2)
748b9d8e 1952 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 1953 else
1954 goto illegal_insn;
3475187d 1955#else
a80dde08 1956 save_state(dc);
748b9d8e 1957 gen_cond(r_cond, 0, cond);
3475187d 1958#endif
748b9d8e 1959 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
0425bee5 1960 tcg_gen_discard_tl(r_cond);
cf495bcf 1961 }
a80dde08 1962 gen_op_next_insn();
57fec1fe 1963 tcg_gen_exit_tb(0);
a80dde08
FB		 1964 dc->is_br = 1;
1965 goto jmp_insn;
cf495bcf
FB		 1966 } else if (xop == 0x28) {
1967 rs1 = GET_FIELD(insn, 13, 17);
1968 switch(rs1) {
1969 case 0: /* rdy */
65fe7b09
BS		 1970#ifndef TARGET_SPARC64
1971 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1972 manual, rdy on the microSPARC
1973 II */
1974 case 0x0f: /* stbar in the SPARCv8 manual,
1975 rdy on the microSPARC II */
1976 case 0x10 ... 0x1f: /* implementation-dependent in the
1977 SPARCv8 manual, rdy on the
1978 microSPARC II */
1979#endif
1980 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1981 gen_movl_T0_reg(rd);
1982 break;
3475187d 1983#ifdef TARGET_SPARC64
0f8a249a 1984 case 0x2: /* V9 rdccr */
3475187d
FB		 1985 gen_op_rdccr();
1986 gen_movl_T0_reg(rd);
1987 break;
0f8a249a
BS		 1988 case 0x3: /* V9 rdasi */
1989 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
3475187d
FB		 1990 gen_movl_T0_reg(rd);
1991 break;
0f8a249a 1992 case 0x4: /* V9 rdtick */
ccd4a219
BS		 1993 {
1994 TCGv r_tickptr;
1995
1996 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
1997 tcg_gen_ld_ptr(r_tickptr, cpu_env,
1998 offsetof(CPUState, tick));
1999 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2000 r_tickptr);
2001 gen_movl_T0_reg(rd);
0425bee5 2002 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 2003 }
3475187d 2004 break;
0f8a249a 2005 case 0x5: /* V9 rdpc */
1a2fb1c0 2006 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 2007 gen_movl_T0_reg(rd);
2008 break;
2009 case 0x6: /* V9 rdfprs */
2010 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
3475187d
FB		 2011 gen_movl_T0_reg(rd);
2012 break;
65fe7b09
BS		 2013 case 0xf: /* V9 membar */
2014 break; /* no effect */
0f8a249a 2015 case 0x13: /* Graphics Status */
725cb90b
FB		 2016 if (gen_trap_ifnofpu(dc))
2017 goto jmp_insn;
0f8a249a 2018 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
725cb90b
FB		 2019 gen_movl_T0_reg(rd);
2020 break;
0f8a249a
BS		 2021 case 0x17: /* Tick compare */
2022 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
83469015
FB		 2023 gen_movl_T0_reg(rd);
2024 break;
0f8a249a 2025 case 0x18: /* System tick */
ccd4a219
BS		 2026 {
2027 TCGv r_tickptr;
2028
2029 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2030 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2031 offsetof(CPUState, stick));
2032 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2033 r_tickptr);
2034 gen_movl_T0_reg(rd);
0425bee5 2035 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 2036 }
83469015 2037 break;
0f8a249a
BS		 2038 case 0x19: /* System tick compare */
2039 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
83469015
FB		 2040 gen_movl_T0_reg(rd);
2041 break;
0f8a249a
BS		 2042 case 0x10: /* Performance Control */
2043 case 0x11: /* Performance Instrumentation Counter */
2044 case 0x12: /* Dispatch Control */
2045 case 0x14: /* Softint set, WO */
2046 case 0x15: /* Softint clear, WO */
2047 case 0x16: /* Softint write */
3475187d
FB		 2048#endif
2049 default:
cf495bcf
FB		 2050 goto illegal_insn;
2051 }
e8af50a3 2052#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2053 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2054#ifndef TARGET_SPARC64
0f8a249a
BS		 2055 if (!supervisor(dc))
2056 goto priv_insn;
1a2fb1c0 2057 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
e9ebed4d
BS		 2058#else
2059 if (!hypervisor(dc))
2060 goto priv_insn;
2061 rs1 = GET_FIELD(insn, 13, 17);
2062 switch (rs1) {
2063 case 0: // hpstate
2064 // gen_op_rdhpstate();
2065 break;
2066 case 1: // htstate
2067 // gen_op_rdhtstate();
2068 break;
2069 case 3: // hintp
2070 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
2071 break;
2072 case 5: // htba
2073 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
2074 break;
2075 case 6: // hver
2076 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
2077 break;
2078 case 31: // hstick_cmpr
2079 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2080 break;
2081 default:
2082 goto illegal_insn;
2083 }
2084#endif
e8af50a3
FB		 2085 gen_movl_T0_reg(rd);
2086 break;
3475187d 2087 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 2088 if (!supervisor(dc))
2089 goto priv_insn;
3475187d
FB		 2090#ifdef TARGET_SPARC64
2091 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2092 switch (rs1) {
2093 case 0: // tpc
375ee38b
BS		 2094 {
2095 TCGv r_tsptr;
2096
2097 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2098 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2099 offsetof(CPUState, tsptr));
2100 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2101 offsetof(trap_state, tpc));
0425bee5 2102 tcg_gen_discard_ptr(r_tsptr);
375ee38b 2103 }
0f8a249a
BS		 2104 break;
2105 case 1: // tnpc
375ee38b
BS		 2106 {
2107 TCGv r_tsptr;
2108
2109 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2110 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2111 offsetof(CPUState, tsptr));
2112 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2113 offsetof(trap_state, tnpc));
0425bee5 2114 tcg_gen_discard_ptr(r_tsptr);
375ee38b 2115 }
0f8a249a
BS		 2116 break;
2117 case 2: // tstate
375ee38b
BS		 2118 {
2119 TCGv r_tsptr;
2120
2121 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2122 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2123 offsetof(CPUState, tsptr));
2124 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2125 offsetof(trap_state, tstate));
0425bee5 2126 tcg_gen_discard_ptr(r_tsptr);
375ee38b 2127 }
0f8a249a
BS		 2128 break;
2129 case 3: // tt
375ee38b
BS		 2130 {
2131 TCGv r_tsptr;
2132
2133 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2134 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2135 offsetof(CPUState, tsptr));
2136 tcg_gen_ld_i32(cpu_T[0], r_tsptr,
2137 offsetof(trap_state, tt));
0425bee5 2138 tcg_gen_discard_ptr(r_tsptr);
375ee38b 2139 }
0f8a249a
BS		 2140 break;
2141 case 4: // tick
ccd4a219
BS		 2142 {
2143 TCGv r_tickptr;
2144
2145 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2146 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2147 offsetof(CPUState, tick));
2148 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2149 r_tickptr);
2150 gen_movl_T0_reg(rd);
0425bee5 2151 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 2152 }
0f8a249a
BS		 2153 break;
2154 case 5: // tba
2155 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2156 break;
2157 case 6: // pstate
1a2fb1c0 2158 gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2159 break;
2160 case 7: // tl
2161 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
2162 break;
2163 case 8: // pil
2164 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2165 break;
2166 case 9: // cwp
2167 gen_op_rdcwp();
2168 break;
2169 case 10: // cansave
2170 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
2171 break;
2172 case 11: // canrestore
2173 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
2174 break;
2175 case 12: // cleanwin
2176 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
2177 break;
2178 case 13: // otherwin
2179 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
2180 break;
2181 case 14: // wstate
2182 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
2183 break;
e9ebed4d
BS		 2184 case 16: // UA2005 gl
2185 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
2186 break;
2187 case 26: // UA2005 strand status
2188 if (!hypervisor(dc))
2189 goto priv_insn;
2190 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
2191 break;
0f8a249a
BS		 2192 case 31: // ver
2193 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
2194 break;
2195 case 15: // fq
2196 default:
2197 goto illegal_insn;
2198 }
3475187d 2199#else
0f8a249a 2200 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
3475187d 2201#endif
e8af50a3
FB		 2202 gen_movl_T0_reg(rd);
2203 break;
3475187d
FB		 2204 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2205#ifdef TARGET_SPARC64
0f8a249a 2206 gen_op_flushw();
3475187d 2207#else
0f8a249a
BS		 2208 if (!supervisor(dc))
2209 goto priv_insn;
2210 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 2211 gen_movl_T0_reg(rd);
3475187d 2212#endif
e8af50a3
FB		 2213 break;
2214#endif
0f8a249a 2215 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 2216 if (gen_trap_ifnofpu(dc))
2217 goto jmp_insn;
0f8a249a 2218 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2219 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2220 rs2 = GET_FIELD(insn, 27, 31);
2221 xop = GET_FIELD(insn, 18, 26);
2222 switch (xop) {
2223 case 0x1: /* fmovs */
2224 gen_op_load_fpr_FT0(rs2);
2225 gen_op_store_FT0_fpr(rd);
2226 break;
2227 case 0x5: /* fnegs */
2228 gen_op_load_fpr_FT1(rs2);
2229 gen_op_fnegs();
2230 gen_op_store_FT0_fpr(rd);
2231 break;
2232 case 0x9: /* fabss */
2233 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2234 tcg_gen_helper_0_0(helper_fabss);
0f8a249a
BS		 2235 gen_op_store_FT0_fpr(rd);
2236 break;
2237 case 0x29: /* fsqrts */
2238 gen_op_load_fpr_FT1(rs2);
7e8c2b6c
BS		 2239 gen_clear_float_exceptions();
2240 tcg_gen_helper_0_0(helper_fsqrts);
2241 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2242 gen_op_store_FT0_fpr(rd);
2243 break;
2244 case 0x2a: /* fsqrtd */
2245 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c
BS		 2246 gen_clear_float_exceptions();
2247 tcg_gen_helper_0_0(helper_fsqrtd);
2248 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2249 gen_op_store_DT0_fpr(DFPREG(rd));
2250 break;
2251 case 0x2b: /* fsqrtq */
1f587329
BS		 2252#if defined(CONFIG_USER_ONLY)
2253 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c
BS		 2254 gen_clear_float_exceptions();
2255 tcg_gen_helper_0_0(helper_fsqrtq);
2256 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2257 gen_op_store_QT0_fpr(QFPREG(rd));
2258 break;
2259#else
0f8a249a 2260 goto nfpu_insn;
1f587329 2261#endif
0f8a249a
BS		 2262 case 0x41:
2263 gen_op_load_fpr_FT0(rs1);
2264 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2265 gen_clear_float_exceptions();
0f8a249a 2266 gen_op_fadds();
7e8c2b6c 2267 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2268 gen_op_store_FT0_fpr(rd);
2269 break;
2270 case 0x42:
2271 gen_op_load_fpr_DT0(DFPREG(rs1));
2272 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2273 gen_clear_float_exceptions();
0f8a249a 2274 gen_op_faddd();
7e8c2b6c 2275 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2276 gen_op_store_DT0_fpr(DFPREG(rd));
2277 break;
2278 case 0x43: /* faddq */
1f587329
BS		 2279#if defined(CONFIG_USER_ONLY)
2280 gen_op_load_fpr_QT0(QFPREG(rs1));
2281 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2282 gen_clear_float_exceptions();
1f587329 2283 gen_op_faddq();
7e8c2b6c 2284 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2285 gen_op_store_QT0_fpr(QFPREG(rd));
2286 break;
2287#else
0f8a249a 2288 goto nfpu_insn;
1f587329 2289#endif
0f8a249a
BS		 2290 case 0x45:
2291 gen_op_load_fpr_FT0(rs1);
2292 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2293 gen_clear_float_exceptions();
0f8a249a 2294 gen_op_fsubs();
7e8c2b6c 2295 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2296 gen_op_store_FT0_fpr(rd);
2297 break;
2298 case 0x46:
2299 gen_op_load_fpr_DT0(DFPREG(rs1));
2300 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2301 gen_clear_float_exceptions();
0f8a249a 2302 gen_op_fsubd();
7e8c2b6c 2303 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2304 gen_op_store_DT0_fpr(DFPREG(rd));
2305 break;
2306 case 0x47: /* fsubq */
1f587329
BS		 2307#if defined(CONFIG_USER_ONLY)
2308 gen_op_load_fpr_QT0(QFPREG(rs1));
2309 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2310 gen_clear_float_exceptions();
1f587329 2311 gen_op_fsubq();
7e8c2b6c 2312 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2313 gen_op_store_QT0_fpr(QFPREG(rd));
2314 break;
2315#else
0f8a249a 2316 goto nfpu_insn;
1f587329 2317#endif
0f8a249a
BS		 2318 case 0x49:
2319 gen_op_load_fpr_FT0(rs1);
2320 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2321 gen_clear_float_exceptions();
0f8a249a 2322 gen_op_fmuls();
7e8c2b6c 2323 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2324 gen_op_store_FT0_fpr(rd);
2325 break;
2326 case 0x4a:
2327 gen_op_load_fpr_DT0(DFPREG(rs1));
2328 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2329 gen_clear_float_exceptions();
0f8a249a 2330 gen_op_fmuld();
7e8c2b6c 2331 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2382dc6b 2332 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2333 break;
2334 case 0x4b: /* fmulq */
1f587329
BS		 2335#if defined(CONFIG_USER_ONLY)
2336 gen_op_load_fpr_QT0(QFPREG(rs1));
2337 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2338 gen_clear_float_exceptions();
1f587329 2339 gen_op_fmulq();
7e8c2b6c 2340 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2341 gen_op_store_QT0_fpr(QFPREG(rd));
2342 break;
2343#else
0f8a249a 2344 goto nfpu_insn;
1f587329 2345#endif
0f8a249a
BS		 2346 case 0x4d:
2347 gen_op_load_fpr_FT0(rs1);
2348 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2349 gen_clear_float_exceptions();
0f8a249a 2350 gen_op_fdivs();
7e8c2b6c 2351 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2352 gen_op_store_FT0_fpr(rd);
2353 break;
2354 case 0x4e:
2355 gen_op_load_fpr_DT0(DFPREG(rs1));
2356 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2357 gen_clear_float_exceptions();
0f8a249a 2358 gen_op_fdivd();
7e8c2b6c 2359 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2360 gen_op_store_DT0_fpr(DFPREG(rd));
2361 break;
2362 case 0x4f: /* fdivq */
1f587329
BS		 2363#if defined(CONFIG_USER_ONLY)
2364 gen_op_load_fpr_QT0(QFPREG(rs1));
2365 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2366 gen_clear_float_exceptions();
1f587329 2367 gen_op_fdivq();
7e8c2b6c 2368 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2369 gen_op_store_QT0_fpr(QFPREG(rd));
2370 break;
2371#else
0f8a249a 2372 goto nfpu_insn;
1f587329 2373#endif
0f8a249a
BS		 2374 case 0x69:
2375 gen_op_load_fpr_FT0(rs1);
2376 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2377 gen_clear_float_exceptions();
0f8a249a 2378 gen_op_fsmuld();
7e8c2b6c 2379 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2380 gen_op_store_DT0_fpr(DFPREG(rd));
2381 break;
2382 case 0x6e: /* fdmulq */
1f587329
BS		 2383#if defined(CONFIG_USER_ONLY)
2384 gen_op_load_fpr_DT0(DFPREG(rs1));
2385 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2386 gen_clear_float_exceptions();
1f587329 2387 gen_op_fdmulq();
7e8c2b6c 2388 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2389 gen_op_store_QT0_fpr(QFPREG(rd));
2390 break;
2391#else
0f8a249a 2392 goto nfpu_insn;
1f587329 2393#endif
0f8a249a
BS		 2394 case 0xc4:
2395 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2396 gen_clear_float_exceptions();
0f8a249a 2397 gen_op_fitos();
7e8c2b6c 2398 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2399 gen_op_store_FT0_fpr(rd);
2400 break;
2401 case 0xc6:
2402 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2403 gen_clear_float_exceptions();
0f8a249a 2404 gen_op_fdtos();
7e8c2b6c 2405 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2406 gen_op_store_FT0_fpr(rd);
2407 break;
2408 case 0xc7: /* fqtos */
1f587329
BS		 2409#if defined(CONFIG_USER_ONLY)
2410 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2411 gen_clear_float_exceptions();
1f587329 2412 gen_op_fqtos();
7e8c2b6c 2413 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2414 gen_op_store_FT0_fpr(rd);
2415 break;
2416#else
0f8a249a 2417 goto nfpu_insn;
1f587329 2418#endif
0f8a249a
BS		 2419 case 0xc8:
2420 gen_op_load_fpr_FT1(rs2);
2421 gen_op_fitod();
2422 gen_op_store_DT0_fpr(DFPREG(rd));
2423 break;
2424 case 0xc9:
2425 gen_op_load_fpr_FT1(rs2);
2426 gen_op_fstod();
2427 gen_op_store_DT0_fpr(DFPREG(rd));
2428 break;
2429 case 0xcb: /* fqtod */
1f587329
BS		 2430#if defined(CONFIG_USER_ONLY)
2431 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2432 gen_clear_float_exceptions();
1f587329 2433 gen_op_fqtod();
7e8c2b6c 2434 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2435 gen_op_store_DT0_fpr(DFPREG(rd));
2436 break;
2437#else
0f8a249a 2438 goto nfpu_insn;
1f587329 2439#endif
0f8a249a 2440 case 0xcc: /* fitoq */
1f587329
BS		 2441#if defined(CONFIG_USER_ONLY)
2442 gen_op_load_fpr_FT1(rs2);
2443 gen_op_fitoq();
2444 gen_op_store_QT0_fpr(QFPREG(rd));
2445 break;
2446#else
0f8a249a 2447 goto nfpu_insn;
1f587329 2448#endif
0f8a249a 2449 case 0xcd: /* fstoq */
1f587329
BS		 2450#if defined(CONFIG_USER_ONLY)
2451 gen_op_load_fpr_FT1(rs2);
2452 gen_op_fstoq();
2453 gen_op_store_QT0_fpr(QFPREG(rd));
2454 break;
2455#else
0f8a249a 2456 goto nfpu_insn;
1f587329 2457#endif
0f8a249a 2458 case 0xce: /* fdtoq */
1f587329
BS		 2459#if defined(CONFIG_USER_ONLY)
2460 gen_op_load_fpr_DT1(DFPREG(rs2));
2461 gen_op_fdtoq();
2462 gen_op_store_QT0_fpr(QFPREG(rd));
2463 break;
2464#else
0f8a249a 2465 goto nfpu_insn;
1f587329 2466#endif
0f8a249a
BS		 2467 case 0xd1:
2468 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2469 gen_clear_float_exceptions();
0f8a249a 2470 gen_op_fstoi();
7e8c2b6c 2471 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2472 gen_op_store_FT0_fpr(rd);
2473 break;
2474 case 0xd2:
2382dc6b 2475 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2476 gen_clear_float_exceptions();
0f8a249a 2477 gen_op_fdtoi();
7e8c2b6c 2478 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2479 gen_op_store_FT0_fpr(rd);
2480 break;
2481 case 0xd3: /* fqtoi */
1f587329
BS		 2482#if defined(CONFIG_USER_ONLY)
2483 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2484 gen_clear_float_exceptions();
1f587329 2485 gen_op_fqtoi();
7e8c2b6c 2486 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2487 gen_op_store_FT0_fpr(rd);
2488 break;
2489#else
0f8a249a 2490 goto nfpu_insn;
1f587329 2491#endif
3475187d 2492#ifdef TARGET_SPARC64
0f8a249a
BS		 2493 case 0x2: /* V9 fmovd */
2494 gen_op_load_fpr_DT0(DFPREG(rs2));
2495 gen_op_store_DT0_fpr(DFPREG(rd));
2496 break;
1f587329
BS		 2497 case 0x3: /* V9 fmovq */
2498#if defined(CONFIG_USER_ONLY)
2499 gen_op_load_fpr_QT0(QFPREG(rs2));
2500 gen_op_store_QT0_fpr(QFPREG(rd));
2501 break;
2502#else
2503 goto nfpu_insn;
2504#endif
0f8a249a
BS		 2505 case 0x6: /* V9 fnegd */
2506 gen_op_load_fpr_DT1(DFPREG(rs2));
2507 gen_op_fnegd();
2508 gen_op_store_DT0_fpr(DFPREG(rd));
2509 break;
1f587329
BS		 2510 case 0x7: /* V9 fnegq */
2511#if defined(CONFIG_USER_ONLY)
2512 gen_op_load_fpr_QT1(QFPREG(rs2));
2513 gen_op_fnegq();
2514 gen_op_store_QT0_fpr(QFPREG(rd));
2515 break;
2516#else
2517 goto nfpu_insn;
2518#endif
0f8a249a
BS		 2519 case 0xa: /* V9 fabsd */
2520 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2521 tcg_gen_helper_0_0(helper_fabsd);
0f8a249a
BS		 2522 gen_op_store_DT0_fpr(DFPREG(rd));
2523 break;
1f587329
BS		 2524 case 0xb: /* V9 fabsq */
2525#if defined(CONFIG_USER_ONLY)
2526 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2527 tcg_gen_helper_0_0(helper_fabsq);
1f587329
BS		 2528 gen_op_store_QT0_fpr(QFPREG(rd));
2529 break;
2530#else
2531 goto nfpu_insn;
2532#endif
0f8a249a
BS		 2533 case 0x81: /* V9 fstox */
2534 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2535 gen_clear_float_exceptions();
0f8a249a 2536 gen_op_fstox();
7e8c2b6c 2537 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2538 gen_op_store_DT0_fpr(DFPREG(rd));
2539 break;
2540 case 0x82: /* V9 fdtox */
2541 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2542 gen_clear_float_exceptions();
0f8a249a 2543 gen_op_fdtox();
7e8c2b6c 2544 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2545 gen_op_store_DT0_fpr(DFPREG(rd));
2546 break;
1f587329
BS		 2547 case 0x83: /* V9 fqtox */
2548#if defined(CONFIG_USER_ONLY)
2549 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2550 gen_clear_float_exceptions();
1f587329 2551 gen_op_fqtox();
7e8c2b6c 2552 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2553 gen_op_store_DT0_fpr(DFPREG(rd));
2554 break;
2555#else
2556 goto nfpu_insn;
2557#endif
0f8a249a
BS		 2558 case 0x84: /* V9 fxtos */
2559 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2560 gen_clear_float_exceptions();
0f8a249a 2561 gen_op_fxtos();
7e8c2b6c 2562 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2563 gen_op_store_FT0_fpr(rd);
2564 break;
2565 case 0x88: /* V9 fxtod */
2566 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2567 gen_clear_float_exceptions();
0f8a249a 2568 gen_op_fxtod();
7e8c2b6c 2569 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2570 gen_op_store_DT0_fpr(DFPREG(rd));
2571 break;
0f8a249a 2572 case 0x8c: /* V9 fxtoq */
1f587329
BS		 2573#if defined(CONFIG_USER_ONLY)
2574 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2575 gen_clear_float_exceptions();
1f587329 2576 gen_op_fxtoq();
7e8c2b6c 2577 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2578 gen_op_store_QT0_fpr(QFPREG(rd));
2579 break;
2580#else
0f8a249a 2581 goto nfpu_insn;
1f587329 2582#endif
0f8a249a
BS		 2583#endif
2584 default:
2585 goto illegal_insn;
2586 }
2587 } else if (xop == 0x35) { /* FPU Operations */
3475187d 2588#ifdef TARGET_SPARC64
0f8a249a 2589 int cond;
3475187d 2590#endif
a80dde08
FB		 2591 if (gen_trap_ifnofpu(dc))
2592 goto jmp_insn;
0f8a249a 2593 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 2594 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2595 rs2 = GET_FIELD(insn, 27, 31);
2596 xop = GET_FIELD(insn, 18, 26);
3475187d 2597#ifdef TARGET_SPARC64
0f8a249a 2598 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 2599 int l1;
2600
2601 l1 = gen_new_label();
0f8a249a 2602 cond = GET_FIELD_SP(insn, 14, 17);
0f8a249a
BS		 2603 rs1 = GET_FIELD(insn, 13, 17);
2604 gen_movl_reg_T0(rs1);
0425bee5
BS		 2605 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2606 tcg_const_tl(0), l1);
19f329ad 2607 gen_op_load_fpr_FT0(rs2);
0f8a249a 2608 gen_op_store_FT0_fpr(rd);
dcf24905 2609 gen_set_label(l1);
0f8a249a
BS		 2610 break;
2611 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 2612 int l1;
2613
2614 l1 = gen_new_label();
0f8a249a 2615 cond = GET_FIELD_SP(insn, 14, 17);
0f8a249a
BS		 2616 rs1 = GET_FIELD(insn, 13, 17);
2617 gen_movl_reg_T0(rs1);
0425bee5
BS		 2618 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2619 tcg_const_tl(0), l1);
19f329ad 2620 gen_op_load_fpr_DT0(DFPREG(rs2));
2382dc6b 2621 gen_op_store_DT0_fpr(DFPREG(rd));
dcf24905 2622 gen_set_label(l1);
0f8a249a
BS		 2623 break;
2624 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1f587329 2625#if defined(CONFIG_USER_ONLY)
dcf24905
BS		 2626 int l1;
2627
2628 l1 = gen_new_label();
1f587329 2629 cond = GET_FIELD_SP(insn, 14, 17);
1f587329
BS		 2630 rs1 = GET_FIELD(insn, 13, 17);
2631 gen_movl_reg_T0(rs1);
0425bee5
BS		 2632 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2633 tcg_const_tl(0), l1);
19f329ad 2634 gen_op_load_fpr_QT0(QFPREG(rs2));
1f587329 2635 gen_op_store_QT0_fpr(QFPREG(rd));
dcf24905 2636 gen_set_label(l1);
1f587329
BS		 2637 break;
2638#else
0f8a249a 2639 goto nfpu_insn;
1f587329 2640#endif
0f8a249a
BS		 2641 }
2642#endif
2643 switch (xop) {
3475187d 2644#ifdef TARGET_SPARC64
19f329ad
BS		 2645#define FMOVCC(size_FDQ, fcc) \
2646 { \
0425bee5 2647 TCGv r_cond; \
19f329ad
BS		 2648 int l1; \
2649 \
2650 l1 = gen_new_label(); \
19f329ad 2651 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2652 cond = GET_FIELD_SP(insn, 14, 17); \
2653 gen_fcond(r_cond, fcc, cond); \
0425bee5
BS		 2654 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2655 tcg_const_tl(0), l1); \
19f329ad
BS		 2656 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2657 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2658 gen_set_label(l1); \
0425bee5 2659 tcg_gen_discard_tl(r_cond); \
19f329ad 2660 }
0f8a249a 2661 case 0x001: /* V9 fmovscc %fcc0 */
19f329ad 2662 FMOVCC(F, 0);
0f8a249a
BS		 2663 break;
2664 case 0x002: /* V9 fmovdcc %fcc0 */
19f329ad 2665 FMOVCC(D, 0);
0f8a249a
BS		 2666 break;
2667 case 0x003: /* V9 fmovqcc %fcc0 */
1f587329 2668#if defined(CONFIG_USER_ONLY)
19f329ad 2669 FMOVCC(Q, 0);
1f587329
BS		 2670 break;
2671#else
0f8a249a 2672 goto nfpu_insn;
1f587329 2673#endif
0f8a249a 2674 case 0x041: /* V9 fmovscc %fcc1 */
19f329ad 2675 FMOVCC(F, 1);
0f8a249a
BS		 2676 break;
2677 case 0x042: /* V9 fmovdcc %fcc1 */
19f329ad 2678 FMOVCC(D, 1);
0f8a249a
BS		 2679 break;
2680 case 0x043: /* V9 fmovqcc %fcc1 */
1f587329 2681#if defined(CONFIG_USER_ONLY)
19f329ad 2682 FMOVCC(Q, 1);
1f587329
BS		 2683 break;
2684#else
0f8a249a 2685 goto nfpu_insn;
1f587329 2686#endif
0f8a249a 2687 case 0x081: /* V9 fmovscc %fcc2 */
19f329ad 2688 FMOVCC(F, 2);
0f8a249a
BS		 2689 break;
2690 case 0x082: /* V9 fmovdcc %fcc2 */
19f329ad 2691 FMOVCC(D, 2);
0f8a249a
BS		 2692 break;
2693 case 0x083: /* V9 fmovqcc %fcc2 */
1f587329 2694#if defined(CONFIG_USER_ONLY)
19f329ad 2695 FMOVCC(Q, 2);
1f587329
BS		 2696 break;
2697#else
0f8a249a 2698 goto nfpu_insn;
1f587329 2699#endif
0f8a249a 2700 case 0x0c1: /* V9 fmovscc %fcc3 */
19f329ad 2701 FMOVCC(F, 3);
0f8a249a
BS		 2702 break;
2703 case 0x0c2: /* V9 fmovdcc %fcc3 */
19f329ad 2704 FMOVCC(D, 3);
0f8a249a
BS		 2705 break;
2706 case 0x0c3: /* V9 fmovqcc %fcc3 */
1f587329 2707#if defined(CONFIG_USER_ONLY)
19f329ad 2708 FMOVCC(Q, 3);
1f587329
BS		 2709 break;
2710#else
0f8a249a 2711 goto nfpu_insn;
1f587329 2712#endif
19f329ad
BS		 2713#undef FMOVCC
2714#define FMOVCC(size_FDQ, icc) \
2715 { \
0425bee5 2716 TCGv r_cond; \
19f329ad
BS		 2717 int l1; \
2718 \
2719 l1 = gen_new_label(); \
19f329ad 2720 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2721 cond = GET_FIELD_SP(insn, 14, 17); \
2722 gen_cond(r_cond, icc, cond); \
0425bee5
BS		 2723 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2724 tcg_const_tl(0), l1); \
19f329ad
BS		 2725 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2726 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2727 gen_set_label(l1); \
0425bee5 2728 tcg_gen_discard_tl(r_cond); \
19f329ad
BS		 2729 }
2730
0f8a249a 2731 case 0x101: /* V9 fmovscc %icc */
19f329ad 2732 FMOVCC(F, 0);
0f8a249a
BS		 2733 break;
2734 case 0x102: /* V9 fmovdcc %icc */
19f329ad 2735 FMOVCC(D, 0);
0f8a249a 2736 case 0x103: /* V9 fmovqcc %icc */
1f587329 2737#if defined(CONFIG_USER_ONLY)
19f329ad 2738 FMOVCC(D, 0);
1f587329
BS		 2739 break;
2740#else
0f8a249a 2741 goto nfpu_insn;
1f587329 2742#endif
0f8a249a 2743 case 0x181: /* V9 fmovscc %xcc */
19f329ad 2744 FMOVCC(F, 1);
0f8a249a
BS		 2745 break;
2746 case 0x182: /* V9 fmovdcc %xcc */
19f329ad 2747 FMOVCC(D, 1);
0f8a249a
BS		 2748 break;
2749 case 0x183: /* V9 fmovqcc %xcc */
1f587329 2750#if defined(CONFIG_USER_ONLY)
19f329ad 2751 FMOVCC(Q, 1);
1f587329
BS		 2752 break;
2753#else
0f8a249a
BS		 2754 goto nfpu_insn;
2755#endif
19f329ad 2756#undef FMOVCC
1f587329
BS		 2757#endif
2758 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 2759 gen_op_load_fpr_FT0(rs1);
2760 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2761 gen_op_fcmps(rd & 3);
0f8a249a 2762 break;
1f587329 2763 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 2764 gen_op_load_fpr_DT0(DFPREG(rs1));
2765 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2766 gen_op_fcmpd(rd & 3);
0f8a249a 2767 break;
1f587329
BS		 2768 case 0x53: /* fcmpq, V9 %fcc */
2769#if defined(CONFIG_USER_ONLY)
2770 gen_op_load_fpr_QT0(QFPREG(rs1));
2771 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2772 gen_op_fcmpq(rd & 3);
1f587329
BS		 2773 break;
2774#else /* !defined(CONFIG_USER_ONLY) */
0f8a249a 2775 goto nfpu_insn;
1f587329 2776#endif
0f8a249a
BS		 2777 case 0x55: /* fcmpes, V9 %fcc */
2778 gen_op_load_fpr_FT0(rs1);
2779 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2780 gen_op_fcmpes(rd & 3);
0f8a249a
BS		 2781 break;
2782 case 0x56: /* fcmped, V9 %fcc */
2783 gen_op_load_fpr_DT0(DFPREG(rs1));
2784 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2785 gen_op_fcmped(rd & 3);
0f8a249a 2786 break;
1f587329
BS		 2787 case 0x57: /* fcmpeq, V9 %fcc */
2788#if defined(CONFIG_USER_ONLY)
2789 gen_op_load_fpr_QT0(QFPREG(rs1));
2790 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2791 gen_op_fcmpeq(rd & 3);
1f587329
BS		 2792 break;
2793#else/* !defined(CONFIG_USER_ONLY) */
0f8a249a 2794 goto nfpu_insn;
1f587329 2795#endif
0f8a249a
BS		 2796 default:
2797 goto illegal_insn;
2798 }
e80cfcfc 2799#if defined(OPTIM)
0f8a249a
BS		 2800 } else if (xop == 0x2) {
2801 // clr/mov shortcut
e80cfcfc
FB		 2802
2803 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2804 if (rs1 == 0) {
1a2fb1c0 2805 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a
BS		 2806 if (IS_IMM) { /* immediate */
2807 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2808 tcg_gen_movi_tl(cpu_T[0], (int)rs2);
0f8a249a
BS		 2809 } else { /* register */
2810 rs2 = GET_FIELD(insn, 27, 31);
1a2fb1c0 2811 gen_movl_reg_T0(rs2);
0f8a249a 2812 }
0f8a249a
BS		 2813 } else {
2814 gen_movl_reg_T0(rs1);
2815 if (IS_IMM) { /* immediate */
0f8a249a 2816 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2817 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 2818 } else { /* register */
2819 // or x, %g0, y -> mov T1, x; mov y, T1
2820 rs2 = GET_FIELD(insn, 27, 31);
2821 if (rs2 != 0) {
2822 gen_movl_reg_T1(rs2);
2823 gen_op_or_T1_T0();
2824 }
2825 }
0f8a249a 2826 }
1a2fb1c0 2827 gen_movl_T0_reg(rd);
83469015
FB		 2828#endif
2829#ifdef TARGET_SPARC64
0f8a249a 2830 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015 2831 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2832 gen_movl_reg_T0(rs1);
2833 if (IS_IMM) { /* immediate */
83469015 2834 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2835 if (insn & (1 << 12)) {
2836 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2837 } else {
2838 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2839 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2840 }
0f8a249a 2841 } else { /* register */
83469015
FB		 2842 rs2 = GET_FIELD(insn, 27, 31);
2843 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2844 if (insn & (1 << 12)) {
2845 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2846 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2847 } else {
2848 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2849 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2850 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2851 }
83469015 2852 }
0f8a249a
BS		 2853 gen_movl_T0_reg(rd);
2854 } else if (xop == 0x26) { /* srl, V9 srlx */
83469015 2855 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2856 gen_movl_reg_T0(rs1);
2857 if (IS_IMM) { /* immediate */
83469015 2858 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2859 if (insn & (1 << 12)) {
2860 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2861 } else {
2862 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2863 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2864 }
0f8a249a 2865 } else { /* register */
83469015
FB		 2866 rs2 = GET_FIELD(insn, 27, 31);
2867 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2868 if (insn & (1 << 12)) {
2869 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2870 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2871 } else {
2872 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2873 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2874 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2875 }
83469015 2876 }
0f8a249a
BS		 2877 gen_movl_T0_reg(rd);
2878 } else if (xop == 0x27) { /* sra, V9 srax */
83469015 2879 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2880 gen_movl_reg_T0(rs1);
2881 if (IS_IMM) { /* immediate */
83469015 2882 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2883 if (insn & (1 << 12)) {
2884 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2885 } else {
2886 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2887 tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2888 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2889 }
0f8a249a 2890 } else { /* register */
83469015
FB		 2891 rs2 = GET_FIELD(insn, 27, 31);
2892 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2893 if (insn & (1 << 12)) {
2894 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2895 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2896 } else {
2897 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2898 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2899 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2900 }
83469015 2901 }
0f8a249a 2902 gen_movl_T0_reg(rd);
e80cfcfc 2903#endif
fcc72045 2904 } else if (xop < 0x36) {
e80cfcfc 2905 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2906 gen_movl_reg_T0(rs1);
2907 if (IS_IMM) { /* immediate */
cf495bcf 2908 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 2909 gen_movl_simm_T1(rs2);
0f8a249a 2910 } else { /* register */
cf495bcf
FB		 2911 rs2 = GET_FIELD(insn, 27, 31);
2912 gen_movl_reg_T1(rs2);
2913 }
2914 if (xop < 0x20) {
2915 switch (xop & ~0x10) {
2916 case 0x0:
2917 if (xop & 0x10)
2918 gen_op_add_T1_T0_cc();
2919 else
2920 gen_op_add_T1_T0();
2921 break;
2922 case 0x1:
1a2fb1c0 2923 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2924 if (xop & 0x10)
2925 gen_op_logic_T0_cc();
2926 break;
2927 case 0x2:
1a2fb1c0 2928 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
0f8a249a
BS		 2929 if (xop & 0x10)
2930 gen_op_logic_T0_cc();
2931 break;
cf495bcf 2932 case 0x3:
1a2fb1c0 2933 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2934 if (xop & 0x10)
2935 gen_op_logic_T0_cc();
2936 break;
2937 case 0x4:
2938 if (xop & 0x10)
2939 gen_op_sub_T1_T0_cc();
2940 else
1a2fb1c0 2941 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2942 break;
2943 case 0x5:
56ec06bb
BS		 2944 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2945 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2946 if (xop & 0x10)
2947 gen_op_logic_T0_cc();
2948 break;
2949 case 0x6:
56ec06bb
BS		 2950 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2951 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2952 if (xop & 0x10)
2953 gen_op_logic_T0_cc();
2954 break;
2955 case 0x7:
56ec06bb
BS		 2956 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2957 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2958 if (xop & 0x10)
2959 gen_op_logic_T0_cc();
2960 break;
2961 case 0x8:
cf495bcf 2962 if (xop & 0x10)
af7bf89b 2963 gen_op_addx_T1_T0_cc();
38bc628b 2964 else {
dc99a3f2 2965 gen_mov_reg_C(cpu_tmp0, cpu_psr);
38bc628b
BS		 2966 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2967 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2968 }
cf495bcf 2969 break;
ded3ab80 2970#ifdef TARGET_SPARC64
0f8a249a 2971 case 0x9: /* V9 mulx */
1a2fb1c0 2972 tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
ded3ab80
PB		 2973 break;
2974#endif
cf495bcf
FB		 2975 case 0xa:
2976 gen_op_umul_T1_T0();
2977 if (xop & 0x10)
2978 gen_op_logic_T0_cc();
2979 break;
2980 case 0xb:
2981 gen_op_smul_T1_T0();
2982 if (xop & 0x10)
2983 gen_op_logic_T0_cc();
2984 break;
2985 case 0xc:
cf495bcf 2986 if (xop & 0x10)
af7bf89b 2987 gen_op_subx_T1_T0_cc();
38bc628b 2988 else {
dc99a3f2 2989 gen_mov_reg_C(cpu_tmp0, cpu_psr);
38bc628b
BS		 2990 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2991 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2992 }
cf495bcf 2993 break;
ded3ab80 2994#ifdef TARGET_SPARC64
0f8a249a 2995 case 0xd: /* V9 udivx */
1a7b60e7
BS		 2996 gen_trap_ifdivzero_i64(cpu_T[1]);
2997 tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
ded3ab80
PB		 2998 break;
2999#endif
cf495bcf
FB		 3000 case 0xe:
3001 gen_op_udiv_T1_T0();
3002 if (xop & 0x10)
3003 gen_op_div_cc();
3004 break;
3005 case 0xf:
3006 gen_op_sdiv_T1_T0();
3007 if (xop & 0x10)
3008 gen_op_div_cc();
3009 break;
3010 default:
3011 goto illegal_insn;
3012 }
0f8a249a 3013 gen_movl_T0_reg(rd);
cf495bcf
FB		 3014 } else {
3015 switch (xop) {
0f8a249a
BS		 3016 case 0x20: /* taddcc */
3017 gen_op_tadd_T1_T0_cc();
3018 gen_movl_T0_reg(rd);
3019 break;
3020 case 0x21: /* tsubcc */
3021 gen_op_tsub_T1_T0_cc();
3022 gen_movl_T0_reg(rd);
3023 break;
3024 case 0x22: /* taddcctv */
90251fb9 3025 save_state(dc);
0f8a249a
BS		 3026 gen_op_tadd_T1_T0_ccTV();
3027 gen_movl_T0_reg(rd);
3028 break;
3029 case 0x23: /* tsubcctv */
90251fb9 3030 save_state(dc);
0f8a249a
BS		 3031 gen_op_tsub_T1_T0_ccTV();
3032 gen_movl_T0_reg(rd);
3033 break;
cf495bcf
FB		 3034 case 0x24: /* mulscc */
3035 gen_op_mulscc_T1_T0();
3036 gen_movl_T0_reg(rd);
3037 break;
83469015 3038#ifndef TARGET_SPARC64
0f8a249a 3039 case 0x25: /* sll */
1a2fb1c0
BS		 3040 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3041 tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3042 gen_movl_T0_reg(rd);
3043 break;
83469015 3044 case 0x26: /* srl */
1a2fb1c0
BS		 3045 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3046 tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3047 gen_movl_T0_reg(rd);
3048 break;
83469015 3049 case 0x27: /* sra */
1a2fb1c0
BS		 3050 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3051 tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3052 gen_movl_T0_reg(rd);
3053 break;
83469015 3054#endif
cf495bcf
FB		 3055 case 0x30:
3056 {
cf495bcf 3057 switch(rd) {
3475187d 3058 case 0: /* wry */
0f8a249a
BS		 3059 gen_op_xor_T1_T0();
3060 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 3061 break;
65fe7b09
BS		 3062#ifndef TARGET_SPARC64
3063 case 0x01 ... 0x0f: /* undefined in the
3064 SPARCv8 manual, nop
3065 on the microSPARC
3066 II */
3067 case 0x10 ... 0x1f: /* implementation-dependent
3068 in the SPARCv8
3069 manual, nop on the
3070 microSPARC II */
3071 break;
3072#else
0f8a249a 3073 case 0x2: /* V9 wrccr */
ee0b03fd 3074 gen_op_xor_T1_T0();
3475187d 3075 gen_op_wrccr();
0f8a249a
BS		 3076 break;
3077 case 0x3: /* V9 wrasi */
ee0b03fd 3078 gen_op_xor_T1_T0();
0f8a249a
BS		 3079 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
3080 break;
3081 case 0x6: /* V9 wrfprs */
3082 gen_op_xor_T1_T0();
3083 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 3084 save_state(dc);
3085 gen_op_next_insn();
57fec1fe 3086 tcg_gen_exit_tb(0);
3299908c 3087 dc->is_br = 1;
0f8a249a
BS		 3088 break;
3089 case 0xf: /* V9 sir, nop if user */
3475187d 3090#if !defined(CONFIG_USER_ONLY)
0f8a249a 3091 if (supervisor(dc))
1a2fb1c0 3092 ; // XXX
3475187d 3093#endif
0f8a249a
BS		 3094 break;
3095 case 0x13: /* Graphics Status */
725cb90b
FB		 3096 if (gen_trap_ifnofpu(dc))
3097 goto jmp_insn;
ee0b03fd 3098 gen_op_xor_T1_T0();
0f8a249a
BS		 3099 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
3100 break;
3101 case 0x17: /* Tick compare */
83469015 3102#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3103 if (!supervisor(dc))
3104 goto illegal_insn;
83469015 3105#endif
ccd4a219
BS		 3106 {
3107 TCGv r_tickptr;
3108
3109 gen_op_xor_T1_T0();
3110 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3111 tick_cmpr));
3112 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3113 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3114 offsetof(CPUState, tick));
3115 tcg_gen_helper_0_2(helper_tick_set_limit,
3116 r_tickptr, cpu_T[0]);
0425bee5 3117 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 3118 }
0f8a249a
BS		 3119 break;
3120 case 0x18: /* System tick */
83469015 3121#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3122 if (!supervisor(dc))
3123 goto illegal_insn;
83469015 3124#endif
ccd4a219
BS		 3125 {
3126 TCGv r_tickptr;
3127
3128 gen_op_xor_T1_T0();
3129 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3130 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3131 offsetof(CPUState, stick));
3132 tcg_gen_helper_0_2(helper_tick_set_count,
3133 r_tickptr, cpu_T[0]);
0425bee5 3134 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 3135 }
0f8a249a
BS		 3136 break;
3137 case 0x19: /* System tick compare */
83469015 3138#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3139 if (!supervisor(dc))
3140 goto illegal_insn;
3475187d 3141#endif
ccd4a219
BS		 3142 {
3143 TCGv r_tickptr;
3144
3145 gen_op_xor_T1_T0();
3146 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3147 stick_cmpr));
3148 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3149 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3150 offsetof(CPUState, stick));
3151 tcg_gen_helper_0_2(helper_tick_set_limit,
3152 r_tickptr, cpu_T[0]);
0425bee5 3153 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 3154 }
0f8a249a 3155 break;
83469015 3156
0f8a249a
BS		 3157 case 0x10: /* Performance Control */
3158 case 0x11: /* Performance Instrumentation Counter */
3159 case 0x12: /* Dispatch Control */
3160 case 0x14: /* Softint set */
3161 case 0x15: /* Softint clear */
3162 case 0x16: /* Softint write */
83469015 3163#endif
3475187d 3164 default:
cf495bcf
FB		 3165 goto illegal_insn;
3166 }
3167 }
3168 break;
e8af50a3 3169#if !defined(CONFIG_USER_ONLY)
af7bf89b 3170 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3171 {
0f8a249a
BS		 3172 if (!supervisor(dc))
3173 goto priv_insn;
3475187d 3174#ifdef TARGET_SPARC64
0f8a249a
BS		 3175 switch (rd) {
3176 case 0:
3177 gen_op_saved();
3178 break;
3179 case 1:
3180 gen_op_restored();
3181 break;
e9ebed4d
BS		 3182 case 2: /* UA2005 allclean */
3183 case 3: /* UA2005 otherw */
3184 case 4: /* UA2005 normalw */
3185 case 5: /* UA2005 invalw */
3186 // XXX
0f8a249a 3187 default:
3475187d
FB		 3188 goto illegal_insn;
3189 }
3190#else
e8af50a3 3191 gen_op_xor_T1_T0();
1a2fb1c0 3192 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
9e61bde5
FB		 3193 save_state(dc);
3194 gen_op_next_insn();
57fec1fe 3195 tcg_gen_exit_tb(0);
0f8a249a 3196 dc->is_br = 1;
3475187d 3197#endif
e8af50a3
FB		 3198 }
3199 break;
af7bf89b 3200 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3201 {
0f8a249a
BS		 3202 if (!supervisor(dc))
3203 goto priv_insn;
e8af50a3 3204 gen_op_xor_T1_T0();
3475187d 3205#ifdef TARGET_SPARC64
0f8a249a
BS		 3206 switch (rd) {
3207 case 0: // tpc
375ee38b
BS		 3208 {
3209 TCGv r_tsptr;
3210
3211 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3212 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3213 offsetof(CPUState, tsptr));
3214 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3215 offsetof(trap_state, tpc));
0425bee5 3216 tcg_gen_discard_ptr(r_tsptr);
375ee38b 3217 }
0f8a249a
BS		 3218 break;
3219 case 1: // tnpc
375ee38b
BS		 3220 {
3221 TCGv r_tsptr;
3222
3223 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3224 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3225 offsetof(CPUState, tsptr));
3226 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3227 offsetof(trap_state, tnpc));
0425bee5 3228 tcg_gen_discard_ptr(r_tsptr);
375ee38b 3229 }
0f8a249a
BS		 3230 break;
3231 case 2: // tstate
375ee38b
BS		 3232 {
3233 TCGv r_tsptr;
3234
3235 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3236 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3237 offsetof(CPUState, tsptr));
3238 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3239 offsetof(trap_state, tstate));
0425bee5 3240 tcg_gen_discard_ptr(r_tsptr);
375ee38b 3241 }
0f8a249a
BS		 3242 break;
3243 case 3: // tt
375ee38b
BS		 3244 {
3245 TCGv r_tsptr;
3246
3247 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3248 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3249 offsetof(CPUState, tsptr));
3250 tcg_gen_st_i32(cpu_T[0], r_tsptr,
3251 offsetof(trap_state, tt));
0425bee5 3252 tcg_gen_discard_ptr(r_tsptr);
375ee38b 3253 }
0f8a249a
BS		 3254 break;
3255 case 4: // tick
ccd4a219
BS		 3256 {
3257 TCGv r_tickptr;
3258
3259 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3260 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3261 offsetof(CPUState, tick));
3262 tcg_gen_helper_0_2(helper_tick_set_count,
3263 r_tickptr, cpu_T[0]);
0425bee5 3264 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 3265 }
0f8a249a
BS		 3266 break;
3267 case 5: // tba
3268 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3269 break;
3270 case 6: // pstate
ded3ab80 3271 save_state(dc);
1a2fb1c0 3272 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
ded3ab80 3273 gen_op_next_insn();
57fec1fe 3274 tcg_gen_exit_tb(0);
ded3ab80 3275 dc->is_br = 1;
0f8a249a
BS		 3276 break;
3277 case 7: // tl
3278 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
3279 break;
3280 case 8: // pil
3281 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3282 break;
3283 case 9: // cwp
3284 gen_op_wrcwp();
3285 break;
3286 case 10: // cansave
3287 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
3288 break;
3289 case 11: // canrestore
3290 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
3291 break;
3292 case 12: // cleanwin
3293 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
3294 break;
3295 case 13: // otherwin
3296 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
3297 break;
3298 case 14: // wstate
3299 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
3300 break;
e9ebed4d
BS		 3301 case 16: // UA2005 gl
3302 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
3303 break;
3304 case 26: // UA2005 strand status
3305 if (!hypervisor(dc))
3306 goto priv_insn;
3307 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
3308 break;
0f8a249a
BS		 3309 default:
3310 goto illegal_insn;
3311 }
3475187d 3312#else
1a2fb1c0
BS		 3313 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3314 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3475187d 3315#endif
e8af50a3
FB		 3316 }
3317 break;
e9ebed4d 3318 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3319 {
e9ebed4d 3320#ifndef TARGET_SPARC64
0f8a249a
BS		 3321 if (!supervisor(dc))
3322 goto priv_insn;
e8af50a3 3323 gen_op_xor_T1_T0();
e9ebed4d
BS		 3324 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3325#else
3326 if (!hypervisor(dc))
3327 goto priv_insn;
3328 gen_op_xor_T1_T0();
3329 switch (rd) {
3330 case 0: // hpstate
3331 // XXX gen_op_wrhpstate();
3332 save_state(dc);
3333 gen_op_next_insn();
57fec1fe 3334 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3335 dc->is_br = 1;
3336 break;
3337 case 1: // htstate
3338 // XXX gen_op_wrhtstate();
3339 break;
3340 case 3: // hintp
3341 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
3342 break;
3343 case 5: // htba
3344 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
3345 break;
3346 case 31: // hstick_cmpr
ccd4a219
BS		 3347 {
3348 TCGv r_tickptr;
3349
3350 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3351 hstick_cmpr));
3352 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3353 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3354 offsetof(CPUState, hstick));
3355 tcg_gen_helper_0_2(helper_tick_set_limit,
3356 r_tickptr, cpu_T[0]);
0425bee5 3357 tcg_gen_discard_ptr(r_tickptr);
ccd4a219 3358 }
e9ebed4d
BS		 3359 break;
3360 case 6: // hver readonly
3361 default:
3362 goto illegal_insn;
3363 }
3364#endif
e8af50a3
FB		 3365 }
3366 break;
3367#endif
3475187d 3368#ifdef TARGET_SPARC64
0f8a249a
BS		 3369 case 0x2c: /* V9 movcc */
3370 {
3371 int cc = GET_FIELD_SP(insn, 11, 12);
3372 int cond = GET_FIELD_SP(insn, 14, 17);
748b9d8e 3373 TCGv r_cond;
00f219bf
BS		 3374 int l1;
3375
748b9d8e 3376 r_cond = tcg_temp_new(TCG_TYPE_TL);
0f8a249a
BS		 3377 if (insn & (1 << 18)) {
3378 if (cc == 0)
748b9d8e 3379 gen_cond(r_cond, 0, cond);
0f8a249a 3380 else if (cc == 2)
748b9d8e 3381 gen_cond(r_cond, 1, cond);
0f8a249a
BS		 3382 else
3383 goto illegal_insn;
3384 } else {
748b9d8e 3385 gen_fcond(r_cond, cc, cond);
0f8a249a 3386 }
00f219bf
BS		 3387
3388 l1 = gen_new_label();
3389
748b9d8e
BS		 3390 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3391 tcg_const_tl(0), l1);
00f219bf
BS		 3392 if (IS_IMM) { /* immediate */
3393 rs2 = GET_FIELD_SPs(insn, 0, 10);
3394 gen_movl_simm_T1(rs2);
3395 } else {
3396 rs2 = GET_FIELD_SP(insn, 0, 4);
3397 gen_movl_reg_T1(rs2);
3398 }
3399 gen_movl_T1_reg(rd);
3400 gen_set_label(l1);
0425bee5 3401 tcg_gen_discard_tl(r_cond);
0f8a249a
BS		 3402 break;
3403 }
3404 case 0x2d: /* V9 sdivx */
3475187d 3405 gen_op_sdivx_T1_T0();
0f8a249a
BS		 3406 gen_movl_T0_reg(rd);
3407 break;
3408 case 0x2e: /* V9 popc */
3409 {
3410 if (IS_IMM) { /* immediate */
3411 rs2 = GET_FIELD_SPs(insn, 0, 12);
3412 gen_movl_simm_T1(rs2);
3413 // XXX optimize: popc(constant)
3414 }
3415 else {
3416 rs2 = GET_FIELD_SP(insn, 0, 4);
3417 gen_movl_reg_T1(rs2);
3418 }
1a2fb1c0
BS		 3419 tcg_gen_helper_1_1(helper_popc, cpu_T[0],
3420 cpu_T[1]);
0f8a249a
BS		 3421 gen_movl_T0_reg(rd);
3422 }
3423 case 0x2f: /* V9 movr */
3424 {
3425 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 3426 int l1;
3427
0f8a249a 3428 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3429 gen_movl_reg_T0(rs1);
00f219bf
BS		 3430
3431 l1 = gen_new_label();
3432
0425bee5
BS		 3433 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
3434 tcg_const_tl(0), l1);
0f8a249a
BS		 3435 if (IS_IMM) { /* immediate */
3436 rs2 = GET_FIELD_SPs(insn, 0, 9);
3437 gen_movl_simm_T1(rs2);
00f219bf 3438 } else {
0f8a249a
BS		 3439 rs2 = GET_FIELD_SP(insn, 0, 4);
3440 gen_movl_reg_T1(rs2);
3441 }
00f219bf
BS		 3442 gen_movl_T1_reg(rd);
3443 gen_set_label(l1);
0f8a249a
BS		 3444 break;
3445 }
3446#endif
3447 default:
3448 goto illegal_insn;
3449 }
3450 }
3299908c
BS		 3451 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3452#ifdef TARGET_SPARC64
3453 int opf = GET_FIELD_SP(insn, 5, 13);
3454 rs1 = GET_FIELD(insn, 13, 17);
3455 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 3456 if (gen_trap_ifnofpu(dc))
3457 goto jmp_insn;
3299908c
BS		 3458
3459 switch (opf) {
e9ebed4d
BS		 3460 case 0x000: /* VIS I edge8cc */
3461 case 0x001: /* VIS II edge8n */
3462 case 0x002: /* VIS I edge8lcc */
3463 case 0x003: /* VIS II edge8ln */
3464 case 0x004: /* VIS I edge16cc */
3465 case 0x005: /* VIS II edge16n */
3466 case 0x006: /* VIS I edge16lcc */
3467 case 0x007: /* VIS II edge16ln */
3468 case 0x008: /* VIS I edge32cc */
3469 case 0x009: /* VIS II edge32n */
3470 case 0x00a: /* VIS I edge32lcc */
3471 case 0x00b: /* VIS II edge32ln */
3472 // XXX
3473 goto illegal_insn;
3474 case 0x010: /* VIS I array8 */
3475 gen_movl_reg_T0(rs1);
3476 gen_movl_reg_T1(rs2);
3477 gen_op_array8();
3478 gen_movl_T0_reg(rd);
3479 break;
3480 case 0x012: /* VIS I array16 */
3481 gen_movl_reg_T0(rs1);
3482 gen_movl_reg_T1(rs2);
3483 gen_op_array16();
3484 gen_movl_T0_reg(rd);
3485 break;
3486 case 0x014: /* VIS I array32 */
3487 gen_movl_reg_T0(rs1);
3488 gen_movl_reg_T1(rs2);
3489 gen_op_array32();
3490 gen_movl_T0_reg(rd);
3491 break;
3299908c 3492 case 0x018: /* VIS I alignaddr */
3299908c
BS		 3493 gen_movl_reg_T0(rs1);
3494 gen_movl_reg_T1(rs2);
3495 gen_op_alignaddr();
3496 gen_movl_T0_reg(rd);
3497 break;
e9ebed4d 3498 case 0x019: /* VIS II bmask */
3299908c 3499 case 0x01a: /* VIS I alignaddrl */
3299908c 3500 // XXX
e9ebed4d
BS		 3501 goto illegal_insn;
3502 case 0x020: /* VIS I fcmple16 */
2382dc6b
BS		 3503 gen_op_load_fpr_DT0(DFPREG(rs1));
3504 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3505 gen_op_fcmple16();
2382dc6b 3506 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3507 break;
3508 case 0x022: /* VIS I fcmpne16 */
2382dc6b
BS		 3509 gen_op_load_fpr_DT0(DFPREG(rs1));
3510 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3511 gen_op_fcmpne16();
2382dc6b 3512 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3513 break;
e9ebed4d 3514 case 0x024: /* VIS I fcmple32 */
2382dc6b
BS		 3515 gen_op_load_fpr_DT0(DFPREG(rs1));
3516 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3517 gen_op_fcmple32();
2382dc6b 3518 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3519 break;
3520 case 0x026: /* VIS I fcmpne32 */
2382dc6b
BS		 3521 gen_op_load_fpr_DT0(DFPREG(rs1));
3522 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3523 gen_op_fcmpne32();
2382dc6b 3524 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3525 break;
3526 case 0x028: /* VIS I fcmpgt16 */
2382dc6b
BS		 3527 gen_op_load_fpr_DT0(DFPREG(rs1));
3528 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3529 gen_op_fcmpgt16();
2382dc6b 3530 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3531 break;
3532 case 0x02a: /* VIS I fcmpeq16 */
2382dc6b
BS		 3533 gen_op_load_fpr_DT0(DFPREG(rs1));
3534 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3535 gen_op_fcmpeq16();
2382dc6b 3536 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3537 break;
3538 case 0x02c: /* VIS I fcmpgt32 */
2382dc6b
BS		 3539 gen_op_load_fpr_DT0(DFPREG(rs1));
3540 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3541 gen_op_fcmpgt32();
2382dc6b 3542 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3543 break;
3544 case 0x02e: /* VIS I fcmpeq32 */
2382dc6b
BS		 3545 gen_op_load_fpr_DT0(DFPREG(rs1));
3546 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3547 gen_op_fcmpeq32();
2382dc6b 3548 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3549 break;
3550 case 0x031: /* VIS I fmul8x16 */
2382dc6b
BS		 3551 gen_op_load_fpr_DT0(DFPREG(rs1));
3552 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3553 gen_op_fmul8x16();
2382dc6b 3554 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3555 break;
3556 case 0x033: /* VIS I fmul8x16au */
2382dc6b
BS		 3557 gen_op_load_fpr_DT0(DFPREG(rs1));
3558 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3559 gen_op_fmul8x16au();
2382dc6b 3560 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3561 break;
3562 case 0x035: /* VIS I fmul8x16al */
2382dc6b
BS		 3563 gen_op_load_fpr_DT0(DFPREG(rs1));
3564 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3565 gen_op_fmul8x16al();
2382dc6b 3566 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3567 break;
3568 case 0x036: /* VIS I fmul8sux16 */
2382dc6b
BS		 3569 gen_op_load_fpr_DT0(DFPREG(rs1));
3570 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3571 gen_op_fmul8sux16();
2382dc6b 3572 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3573 break;
3574 case 0x037: /* VIS I fmul8ulx16 */
2382dc6b
BS		 3575 gen_op_load_fpr_DT0(DFPREG(rs1));
3576 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3577 gen_op_fmul8ulx16();
2382dc6b 3578 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3579 break;
3580 case 0x038: /* VIS I fmuld8sux16 */
2382dc6b
BS		 3581 gen_op_load_fpr_DT0(DFPREG(rs1));
3582 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3583 gen_op_fmuld8sux16();
2382dc6b 3584 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3585 break;
3586 case 0x039: /* VIS I fmuld8ulx16 */
2382dc6b
BS		 3587 gen_op_load_fpr_DT0(DFPREG(rs1));
3588 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3589 gen_op_fmuld8ulx16();
2382dc6b 3590 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3591 break;
3592 case 0x03a: /* VIS I fpack32 */
3593 case 0x03b: /* VIS I fpack16 */
3594 case 0x03d: /* VIS I fpackfix */
3595 case 0x03e: /* VIS I pdist */
3596 // XXX
3597 goto illegal_insn;
3299908c 3598 case 0x048: /* VIS I faligndata */
2382dc6b
BS		 3599 gen_op_load_fpr_DT0(DFPREG(rs1));
3600 gen_op_load_fpr_DT1(DFPREG(rs2));
3299908c 3601 gen_op_faligndata();
2382dc6b 3602 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3603 break;
e9ebed4d 3604 case 0x04b: /* VIS I fpmerge */
2382dc6b
BS		 3605 gen_op_load_fpr_DT0(DFPREG(rs1));
3606 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3607 gen_op_fpmerge();
2382dc6b 3608 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3609 break;
3610 case 0x04c: /* VIS II bshuffle */
3611 // XXX
3612 goto illegal_insn;
3613 case 0x04d: /* VIS I fexpand */
2382dc6b
BS		 3614 gen_op_load_fpr_DT0(DFPREG(rs1));
3615 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3616 gen_op_fexpand();
2382dc6b 3617 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3618 break;
3619 case 0x050: /* VIS I fpadd16 */
2382dc6b
BS		 3620 gen_op_load_fpr_DT0(DFPREG(rs1));
3621 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3622 gen_op_fpadd16();
2382dc6b 3623 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3624 break;
3625 case 0x051: /* VIS I fpadd16s */
3626 gen_op_load_fpr_FT0(rs1);
3627 gen_op_load_fpr_FT1(rs2);
3628 gen_op_fpadd16s();
3629 gen_op_store_FT0_fpr(rd);
3630 break;
3631 case 0x052: /* VIS I fpadd32 */
2382dc6b
BS		 3632 gen_op_load_fpr_DT0(DFPREG(rs1));
3633 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3634 gen_op_fpadd32();
2382dc6b 3635 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3636 break;
3637 case 0x053: /* VIS I fpadd32s */
3638 gen_op_load_fpr_FT0(rs1);
3639 gen_op_load_fpr_FT1(rs2);
3640 gen_op_fpadd32s();
3641 gen_op_store_FT0_fpr(rd);
3642 break;
3643 case 0x054: /* VIS I fpsub16 */
2382dc6b
BS		 3644 gen_op_load_fpr_DT0(DFPREG(rs1));
3645 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3646 gen_op_fpsub16();
2382dc6b 3647 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3648 break;
3649 case 0x055: /* VIS I fpsub16s */
3650 gen_op_load_fpr_FT0(rs1);
3651 gen_op_load_fpr_FT1(rs2);
3652 gen_op_fpsub16s();
3653 gen_op_store_FT0_fpr(rd);
3654 break;
3655 case 0x056: /* VIS I fpsub32 */
2382dc6b
BS		 3656 gen_op_load_fpr_DT0(DFPREG(rs1));
3657 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3658 gen_op_fpadd32();
2382dc6b 3659 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3660 break;
3661 case 0x057: /* VIS I fpsub32s */
3662 gen_op_load_fpr_FT0(rs1);
3663 gen_op_load_fpr_FT1(rs2);
3664 gen_op_fpsub32s();
3665 gen_op_store_FT0_fpr(rd);
3666 break;
3299908c 3667 case 0x060: /* VIS I fzero */
3299908c 3668 gen_op_movl_DT0_0();
2382dc6b 3669 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3670 break;
3671 case 0x061: /* VIS I fzeros */
3299908c
BS		 3672 gen_op_movl_FT0_0();
3673 gen_op_store_FT0_fpr(rd);
3674 break;
e9ebed4d 3675 case 0x062: /* VIS I fnor */
2382dc6b
BS		 3676 gen_op_load_fpr_DT0(DFPREG(rs1));
3677 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3678 gen_op_fnor();
2382dc6b 3679 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3680 break;
3681 case 0x063: /* VIS I fnors */
3682 gen_op_load_fpr_FT0(rs1);
3683 gen_op_load_fpr_FT1(rs2);
3684 gen_op_fnors();
3685 gen_op_store_FT0_fpr(rd);
3686 break;
3687 case 0x064: /* VIS I fandnot2 */
2382dc6b
BS		 3688 gen_op_load_fpr_DT1(DFPREG(rs1));
3689 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 3690 gen_op_fandnot();
2382dc6b 3691 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3692 break;
3693 case 0x065: /* VIS I fandnot2s */
3694 gen_op_load_fpr_FT1(rs1);
3695 gen_op_load_fpr_FT0(rs2);
3696 gen_op_fandnots();
3697 gen_op_store_FT0_fpr(rd);
3698 break;
3699 case 0x066: /* VIS I fnot2 */
2382dc6b 3700 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3701 gen_op_fnot();
2382dc6b 3702 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3703 break;
3704 case 0x067: /* VIS I fnot2s */
3705 gen_op_load_fpr_FT1(rs2);
3706 gen_op_fnot();
3707 gen_op_store_FT0_fpr(rd);
3708 break;
3709 case 0x068: /* VIS I fandnot1 */
2382dc6b
BS		 3710 gen_op_load_fpr_DT0(DFPREG(rs1));
3711 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3712 gen_op_fandnot();
2382dc6b 3713 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3714 break;
3715 case 0x069: /* VIS I fandnot1s */
3716 gen_op_load_fpr_FT0(rs1);
3717 gen_op_load_fpr_FT1(rs2);
3718 gen_op_fandnots();
3719 gen_op_store_FT0_fpr(rd);
3720 break;
3721 case 0x06a: /* VIS I fnot1 */
2382dc6b 3722 gen_op_load_fpr_DT1(DFPREG(rs1));
e9ebed4d 3723 gen_op_fnot();
2382dc6b 3724 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3725 break;
3726 case 0x06b: /* VIS I fnot1s */
3727 gen_op_load_fpr_FT1(rs1);
3728 gen_op_fnot();
3729 gen_op_store_FT0_fpr(rd);
3730 break;
3731 case 0x06c: /* VIS I fxor */
2382dc6b
BS		 3732 gen_op_load_fpr_DT0(DFPREG(rs1));
3733 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3734 gen_op_fxor();
2382dc6b 3735 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3736 break;
3737 case 0x06d: /* VIS I fxors */
3738 gen_op_load_fpr_FT0(rs1);
3739 gen_op_load_fpr_FT1(rs2);
3740 gen_op_fxors();
3741 gen_op_store_FT0_fpr(rd);
3742 break;
3743 case 0x06e: /* VIS I fnand */
2382dc6b
BS		 3744 gen_op_load_fpr_DT0(DFPREG(rs1));
3745 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3746 gen_op_fnand();
2382dc6b 3747 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3748 break;
3749 case 0x06f: /* VIS I fnands */
3750 gen_op_load_fpr_FT0(rs1);
3751 gen_op_load_fpr_FT1(rs2);
3752 gen_op_fnands();
3753 gen_op_store_FT0_fpr(rd);
3754 break;
3755 case 0x070: /* VIS I fand */
2382dc6b
BS		 3756 gen_op_load_fpr_DT0(DFPREG(rs1));
3757 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3758 gen_op_fand();
2382dc6b 3759 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3760 break;
3761 case 0x071: /* VIS I fands */
3762 gen_op_load_fpr_FT0(rs1);
3763 gen_op_load_fpr_FT1(rs2);
3764 gen_op_fands();
3765 gen_op_store_FT0_fpr(rd);
3766 break;
3767 case 0x072: /* VIS I fxnor */
2382dc6b
BS		 3768 gen_op_load_fpr_DT0(DFPREG(rs1));
3769 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3770 gen_op_fxnor();
2382dc6b 3771 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3772 break;
3773 case 0x073: /* VIS I fxnors */
3774 gen_op_load_fpr_FT0(rs1);
3775 gen_op_load_fpr_FT1(rs2);
3776 gen_op_fxnors();
3777 gen_op_store_FT0_fpr(rd);
3778 break;
3299908c 3779 case 0x074: /* VIS I fsrc1 */
2382dc6b
BS		 3780 gen_op_load_fpr_DT0(DFPREG(rs1));
3781 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3782 break;
3783 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 3784 gen_op_load_fpr_FT0(rs1);
3785 gen_op_store_FT0_fpr(rd);
3786 break;
e9ebed4d 3787 case 0x076: /* VIS I fornot2 */
2382dc6b
BS		 3788 gen_op_load_fpr_DT1(DFPREG(rs1));
3789 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 3790 gen_op_fornot();
2382dc6b 3791 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3792 break;
3793 case 0x077: /* VIS I fornot2s */
3794 gen_op_load_fpr_FT1(rs1);
3795 gen_op_load_fpr_FT0(rs2);
3796 gen_op_fornots();
3797 gen_op_store_FT0_fpr(rd);
3798 break;
3299908c 3799 case 0x078: /* VIS I fsrc2 */
2382dc6b
BS		 3800 gen_op_load_fpr_DT0(DFPREG(rs2));
3801 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3802 break;
3803 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 3804 gen_op_load_fpr_FT0(rs2);
3805 gen_op_store_FT0_fpr(rd);
3806 break;
e9ebed4d 3807 case 0x07a: /* VIS I fornot1 */
2382dc6b
BS		 3808 gen_op_load_fpr_DT0(DFPREG(rs1));
3809 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3810 gen_op_fornot();
2382dc6b 3811 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3812 break;
3813 case 0x07b: /* VIS I fornot1s */
3814 gen_op_load_fpr_FT0(rs1);
3815 gen_op_load_fpr_FT1(rs2);
3816 gen_op_fornots();
3817 gen_op_store_FT0_fpr(rd);
3818 break;
3819 case 0x07c: /* VIS I for */
2382dc6b
BS		 3820 gen_op_load_fpr_DT0(DFPREG(rs1));
3821 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3822 gen_op_for();
2382dc6b 3823 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3824 break;
3825 case 0x07d: /* VIS I fors */
3826 gen_op_load_fpr_FT0(rs1);
3827 gen_op_load_fpr_FT1(rs2);
3828 gen_op_fors();
3829 gen_op_store_FT0_fpr(rd);
3830 break;
3299908c 3831 case 0x07e: /* VIS I fone */
3299908c 3832 gen_op_movl_DT0_1();
2382dc6b 3833 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3834 break;
3835 case 0x07f: /* VIS I fones */
3299908c
BS		 3836 gen_op_movl_FT0_1();
3837 gen_op_store_FT0_fpr(rd);
3838 break;
e9ebed4d
BS		 3839 case 0x080: /* VIS I shutdown */
3840 case 0x081: /* VIS II siam */
3841 // XXX
3842 goto illegal_insn;
3299908c
BS		 3843 default:
3844 goto illegal_insn;
3845 }
3846#else
0f8a249a 3847 goto ncp_insn;
3299908c
BS		 3848#endif
3849 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 3850#ifdef TARGET_SPARC64
0f8a249a 3851 goto illegal_insn;
fcc72045 3852#else
0f8a249a 3853 goto ncp_insn;
fcc72045 3854#endif
3475187d 3855#ifdef TARGET_SPARC64
0f8a249a 3856 } else if (xop == 0x39) { /* V9 return */
3475187d 3857 rs1 = GET_FIELD(insn, 13, 17);
1ad21e69 3858 save_state(dc);
0f8a249a
BS		 3859 gen_movl_reg_T0(rs1);
3860 if (IS_IMM) { /* immediate */
3861 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3862 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 3863 } else { /* register */
3475187d
FB		 3864 rs2 = GET_FIELD(insn, 27, 31);
3865#if defined(OPTIM)
0f8a249a 3866 if (rs2) {
3475187d 3867#endif
0f8a249a
BS		 3868 gen_movl_reg_T1(rs2);
3869 gen_op_add_T1_T0();
3475187d 3870#if defined(OPTIM)
0f8a249a 3871 }
3475187d
FB		 3872#endif
3873 }
0f8a249a
BS		 3874 gen_op_restore();
3875 gen_mov_pc_npc(dc);
6ea4a6c8 3876 gen_op_check_align_T0_3();
1a2fb1c0 3877 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3878 dc->npc = DYNAMIC_PC;
3879 goto jmp_insn;
3475187d 3880#endif
0f8a249a 3881 } else {
e80cfcfc 3882 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3883 gen_movl_reg_T0(rs1);
3884 if (IS_IMM) { /* immediate */
3885 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3886 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 3887 } else { /* register */
e80cfcfc
FB		 3888 rs2 = GET_FIELD(insn, 27, 31);
3889#if defined(OPTIM)
0f8a249a 3890 if (rs2) {
e80cfcfc 3891#endif
0f8a249a
BS		 3892 gen_movl_reg_T1(rs2);
3893 gen_op_add_T1_T0();
e80cfcfc 3894#if defined(OPTIM)
0f8a249a 3895 }
e8af50a3 3896#endif
cf495bcf 3897 }
0f8a249a
BS		 3898 switch (xop) {
3899 case 0x38: /* jmpl */
3900 {
3901 if (rd != 0) {
1a2fb1c0 3902 tcg_gen_movi_tl(cpu_T[1], dc->pc);
0f8a249a
BS		 3903 gen_movl_T1_reg(rd);
3904 }
0bee699e 3905 gen_mov_pc_npc(dc);
6ea4a6c8 3906 gen_op_check_align_T0_3();
1a2fb1c0 3907 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3908 dc->npc = DYNAMIC_PC;
3909 }
3910 goto jmp_insn;
3475187d 3911#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 3912 case 0x39: /* rett, V9 return */
3913 {
3914 if (!supervisor(dc))
3915 goto priv_insn;
0bee699e 3916 gen_mov_pc_npc(dc);
6ea4a6c8 3917 gen_op_check_align_T0_3();
1a2fb1c0 3918 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a 3919 dc->npc = DYNAMIC_PC;
1a2fb1c0 3920 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 3921 }
3922 goto jmp_insn;
3923#endif
3924 case 0x3b: /* flush */
1a2fb1c0 3925 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
0f8a249a
BS		 3926 break;
3927 case 0x3c: /* save */
3928 save_state(dc);
3929 gen_op_save();
3930 gen_movl_T0_reg(rd);
3931 break;
3932 case 0x3d: /* restore */
3933 save_state(dc);
3934 gen_op_restore();
3935 gen_movl_T0_reg(rd);
3936 break;
3475187d 3937#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 3938 case 0x3e: /* V9 done/retry */
3939 {
3940 switch (rd) {
3941 case 0:
3942 if (!supervisor(dc))
3943 goto priv_insn;
3944 dc->npc = DYNAMIC_PC;
3945 dc->pc = DYNAMIC_PC;
1a2fb1c0 3946 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 3947 goto jmp_insn;
3948 case 1:
3949 if (!supervisor(dc))
3950 goto priv_insn;
3951 dc->npc = DYNAMIC_PC;
3952 dc->pc = DYNAMIC_PC;
1a2fb1c0 3953 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 3954 goto jmp_insn;
3955 default:
3956 goto illegal_insn;
3957 }
3958 }
3959 break;
3960#endif
3961 default:
3962 goto illegal_insn;
3963 }
cf495bcf 3964 }
0f8a249a
BS		 3965 break;
3966 }
3967 break;
3968 case 3: /* load/store instructions */
3969 {
3970 unsigned int xop = GET_FIELD(insn, 7, 12);
3971 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 3972 save_state(dc);
0f8a249a 3973 gen_movl_reg_T0(rs1);
81ad8ba2
BS		 3974 if (xop == 0x3c || xop == 0x3e)
3975 {
3976 rs2 = GET_FIELD(insn, 27, 31);
3977 gen_movl_reg_T1(rs2);
3978 }
3979 else if (IS_IMM) { /* immediate */
0f8a249a 3980 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3981 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 3982 } else { /* register */
3983 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 3984#if defined(OPTIM)
0f8a249a 3985 if (rs2 != 0) {
e80cfcfc 3986#endif
0f8a249a
BS		 3987 gen_movl_reg_T1(rs2);
3988 gen_op_add_T1_T0();
e80cfcfc 3989#if defined(OPTIM)
0f8a249a 3990 }
e80cfcfc 3991#endif
0f8a249a 3992 }
2f2ecb83
BS		 3993 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
3994 (xop > 0x17 && xop <= 0x1d ) ||
3995 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 3996 switch (xop) {
1a2fb1c0 3997 case 0x0: /* load unsigned word */
6ea4a6c8 3998 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3999 ABI32_MASK(cpu_T[0]);
4000 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4001 break;
4002 case 0x1: /* load unsigned byte */
1a2fb1c0
BS		 4003 ABI32_MASK(cpu_T[0]);
4004 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4005 break;
4006 case 0x2: /* load unsigned halfword */
6ea4a6c8 4007 gen_op_check_align_T0_1();
1a2fb1c0
BS		 4008 ABI32_MASK(cpu_T[0]);
4009 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4010 break;
4011 case 0x3: /* load double word */
0f8a249a 4012 if (rd & 1)
d4218d99 4013 goto illegal_insn;
1a2fb1c0
BS		 4014 else {
4015 TCGv r_dword;
4016
4017 r_dword = tcg_temp_new(TCG_TYPE_I64);
4018 gen_op_check_align_T0_7();
4019 ABI32_MASK(cpu_T[0]);
4020 tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
4021 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
4022 gen_movl_T0_reg(rd + 1);
4023 tcg_gen_shri_i64(r_dword, r_dword, 32);
4024 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
0425bee5 4025 tcg_gen_discard_i64(r_dword);
1a2fb1c0 4026 }
0f8a249a
BS		 4027 break;
4028 case 0x9: /* load signed byte */
1a2fb1c0
BS		 4029 ABI32_MASK(cpu_T[0]);
4030 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4031 break;
4032 case 0xa: /* load signed halfword */
6ea4a6c8 4033 gen_op_check_align_T0_1();
1a2fb1c0
BS		 4034 ABI32_MASK(cpu_T[0]);
4035 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4036 break;
4037 case 0xd: /* ldstub -- XXX: should be atomically */
1a2fb1c0
BS		 4038 tcg_gen_movi_i32(cpu_tmp0, 0xff);
4039 ABI32_MASK(cpu_T[0]);
4040 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4041 tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4042 break;
4043 case 0x0f: /* swap register with memory. Also atomically */
6ea4a6c8 4044 gen_op_check_align_T0_3();
0f8a249a 4045 gen_movl_reg_T1(rd);
1a2fb1c0
BS		 4046 ABI32_MASK(cpu_T[0]);
4047 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
4048 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4049 tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
0f8a249a 4050 break;
3475187d 4051#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4052 case 0x10: /* load word alternate */
3475187d 4053#ifndef TARGET_SPARC64
0f8a249a
BS		 4054 if (IS_IMM)
4055 goto illegal_insn;
4056 if (!supervisor(dc))
4057 goto priv_insn;
6ea4a6c8 4058#endif
8f577d3d 4059 gen_op_check_align_T0_3();
81ad8ba2 4060 gen_ld_asi(insn, 4, 0);
0f8a249a
BS		 4061 break;
4062 case 0x11: /* load unsigned byte alternate */
3475187d 4063#ifndef TARGET_SPARC64
0f8a249a
BS		 4064 if (IS_IMM)
4065 goto illegal_insn;
4066 if (!supervisor(dc))
4067 goto priv_insn;
4068#endif
81ad8ba2 4069 gen_ld_asi(insn, 1, 0);
0f8a249a
BS		 4070 break;
4071 case 0x12: /* load unsigned halfword alternate */
3475187d 4072#ifndef TARGET_SPARC64
0f8a249a
BS		 4073 if (IS_IMM)
4074 goto illegal_insn;
4075 if (!supervisor(dc))
4076 goto priv_insn;
3475187d 4077#endif
8f577d3d 4078 gen_op_check_align_T0_1();
81ad8ba2 4079 gen_ld_asi(insn, 2, 0);
0f8a249a
BS		 4080 break;
4081 case 0x13: /* load double word alternate */
3475187d 4082#ifndef TARGET_SPARC64
0f8a249a
BS		 4083 if (IS_IMM)
4084 goto illegal_insn;
4085 if (!supervisor(dc))
4086 goto priv_insn;
3475187d 4087#endif
0f8a249a 4088 if (rd & 1)
d4218d99 4089 goto illegal_insn;
6ea4a6c8 4090 gen_op_check_align_T0_7();
81ad8ba2 4091 gen_ldda_asi(insn);
0f8a249a
BS		 4092 gen_movl_T0_reg(rd + 1);
4093 break;
4094 case 0x19: /* load signed byte alternate */
3475187d 4095#ifndef TARGET_SPARC64
0f8a249a
BS		 4096 if (IS_IMM)
4097 goto illegal_insn;
4098 if (!supervisor(dc))
4099 goto priv_insn;
4100#endif
81ad8ba2 4101 gen_ld_asi(insn, 1, 1);
0f8a249a
BS		 4102 break;
4103 case 0x1a: /* load signed halfword alternate */
3475187d 4104#ifndef TARGET_SPARC64
0f8a249a
BS		 4105 if (IS_IMM)
4106 goto illegal_insn;
4107 if (!supervisor(dc))
4108 goto priv_insn;
3475187d 4109#endif
8f577d3d 4110 gen_op_check_align_T0_1();
81ad8ba2 4111 gen_ld_asi(insn, 2, 1);
0f8a249a
BS		 4112 break;
4113 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4114#ifndef TARGET_SPARC64
0f8a249a
BS		 4115 if (IS_IMM)
4116 goto illegal_insn;
4117 if (!supervisor(dc))
4118 goto priv_insn;
4119#endif
81ad8ba2 4120 gen_ldstub_asi(insn);
0f8a249a
BS		 4121 break;
4122 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 4123#ifndef TARGET_SPARC64
0f8a249a
BS		 4124 if (IS_IMM)
4125 goto illegal_insn;
4126 if (!supervisor(dc))
4127 goto priv_insn;
6ea4a6c8 4128#endif
8f577d3d 4129 gen_op_check_align_T0_3();
81ad8ba2
BS		 4130 gen_movl_reg_T1(rd);
4131 gen_swap_asi(insn);
0f8a249a 4132 break;
3475187d
FB		 4133
4134#ifndef TARGET_SPARC64
0f8a249a
BS		 4135 case 0x30: /* ldc */
4136 case 0x31: /* ldcsr */
4137 case 0x33: /* lddc */
4138 goto ncp_insn;
3475187d
FB		 4139#endif
4140#endif
4141#ifdef TARGET_SPARC64
0f8a249a 4142 case 0x08: /* V9 ldsw */
6ea4a6c8 4143 gen_op_check_align_T0_3();
1a2fb1c0
BS		 4144 ABI32_MASK(cpu_T[0]);
4145 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4146 break;
4147 case 0x0b: /* V9 ldx */
6ea4a6c8 4148 gen_op_check_align_T0_7();
1a2fb1c0
BS		 4149 ABI32_MASK(cpu_T[0]);
4150 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4151 break;
4152 case 0x18: /* V9 ldswa */
6ea4a6c8 4153 gen_op_check_align_T0_3();
81ad8ba2 4154 gen_ld_asi(insn, 4, 1);
0f8a249a
BS		 4155 break;
4156 case 0x1b: /* V9 ldxa */
6ea4a6c8 4157 gen_op_check_align_T0_7();
81ad8ba2 4158 gen_ld_asi(insn, 8, 0);
0f8a249a
BS		 4159 break;
4160 case 0x2d: /* V9 prefetch, no effect */
4161 goto skip_move;
4162 case 0x30: /* V9 ldfa */
6ea4a6c8 4163 gen_op_check_align_T0_3();
2382dc6b 4164 gen_ldf_asi(insn, 4, rd);
81ad8ba2 4165 goto skip_move;
0f8a249a 4166 case 0x33: /* V9 lddfa */
3391c818 4167 gen_op_check_align_T0_3();
2382dc6b 4168 gen_ldf_asi(insn, 8, DFPREG(rd));
81ad8ba2 4169 goto skip_move;
0f8a249a
BS		 4170 case 0x3d: /* V9 prefetcha, no effect */
4171 goto skip_move;
4172 case 0x32: /* V9 ldqfa */
1f587329
BS		 4173#if defined(CONFIG_USER_ONLY)
4174 gen_op_check_align_T0_3();
2382dc6b 4175 gen_ldf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 4176 goto skip_move;
4177#else
0f8a249a 4178 goto nfpu_insn;
1f587329 4179#endif
0f8a249a
BS		 4180#endif
4181 default:
4182 goto illegal_insn;
4183 }
4184 gen_movl_T1_reg(rd);
3475187d 4185#ifdef TARGET_SPARC64
0f8a249a 4186 skip_move: ;
3475187d 4187#endif
0f8a249a 4188 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 4189 if (gen_trap_ifnofpu(dc))
4190 goto jmp_insn;
0f8a249a
BS		 4191 switch (xop) {
4192 case 0x20: /* load fpreg */
6ea4a6c8 4193 gen_op_check_align_T0_3();
0f8a249a
BS		 4194 gen_op_ldst(ldf);
4195 gen_op_store_FT0_fpr(rd);
4196 break;
4197 case 0x21: /* load fsr */
6ea4a6c8 4198 gen_op_check_align_T0_3();
0f8a249a 4199 gen_op_ldst(ldf);
7e8c2b6c 4200 tcg_gen_helper_0_0(helper_ldfsr);
0f8a249a
BS		 4201 break;
4202 case 0x22: /* load quad fpreg */
1f587329
BS		 4203#if defined(CONFIG_USER_ONLY)
4204 gen_op_check_align_T0_7();
4205 gen_op_ldst(ldqf);
4206 gen_op_store_QT0_fpr(QFPREG(rd));
4207 break;
4208#else
0f8a249a 4209 goto nfpu_insn;
1f587329 4210#endif
0f8a249a 4211 case 0x23: /* load double fpreg */
6ea4a6c8 4212 gen_op_check_align_T0_7();
0f8a249a
BS		 4213 gen_op_ldst(lddf);
4214 gen_op_store_DT0_fpr(DFPREG(rd));
4215 break;
4216 default:
4217 goto illegal_insn;
4218 }
4219 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4220 xop == 0xe || xop == 0x1e) {
4221 gen_movl_reg_T1(rd);
4222 switch (xop) {
1a2fb1c0 4223 case 0x4: /* store word */
6ea4a6c8 4224 gen_op_check_align_T0_3();
1a2fb1c0
BS		 4225 ABI32_MASK(cpu_T[0]);
4226 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 4227 break;
1a2fb1c0
BS		 4228 case 0x5: /* store byte */
4229 ABI32_MASK(cpu_T[0]);
4230 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 4231 break;
1a2fb1c0 4232 case 0x6: /* store halfword */
6ea4a6c8 4233 gen_op_check_align_T0_1();
1a2fb1c0
BS		 4234 ABI32_MASK(cpu_T[0]);
4235 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 4236 break;
1a2fb1c0 4237 case 0x7: /* store double word */
0f8a249a 4238 if (rd & 1)
d4218d99 4239 goto illegal_insn;
b25deda7 4240#ifndef __i386__
1a2fb1c0
BS		 4241 else {
4242 TCGv r_dword, r_low;
4243
4244 gen_op_check_align_T0_7();
4245 r_dword = tcg_temp_new(TCG_TYPE_I64);
4246 r_low = tcg_temp_new(TCG_TYPE_I32);
4247 gen_movl_reg_TN(rd + 1, r_low);
4248 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4249 r_low);
4250 tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
0425bee5 4251 tcg_gen_discard_i64(r_dword);
1a2fb1c0 4252 }
b25deda7
BS		 4253#else /* __i386__ */
4254 gen_op_check_align_T0_7();
4255 flush_T2(dc);
4256 gen_movl_reg_T2(rd + 1);
4257 gen_op_ldst(std);
4258#endif /* __i386__ */
0f8a249a 4259 break;
3475187d 4260#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 4261 case 0x14: /* store word alternate */
3475187d 4262#ifndef TARGET_SPARC64
0f8a249a
BS		 4263 if (IS_IMM)
4264 goto illegal_insn;
4265 if (!supervisor(dc))
4266 goto priv_insn;
6ea4a6c8 4267#endif
6ea4a6c8 4268 gen_op_check_align_T0_3();
81ad8ba2 4269 gen_st_asi(insn, 4);
d39c0b99 4270 break;
1a2fb1c0 4271 case 0x15: /* store byte alternate */
3475187d 4272#ifndef TARGET_SPARC64
0f8a249a
BS		 4273 if (IS_IMM)
4274 goto illegal_insn;
4275 if (!supervisor(dc))
4276 goto priv_insn;
3475187d 4277#endif
81ad8ba2 4278 gen_st_asi(insn, 1);
d39c0b99 4279 break;
1a2fb1c0 4280 case 0x16: /* store halfword alternate */
3475187d 4281#ifndef TARGET_SPARC64
0f8a249a
BS		 4282 if (IS_IMM)
4283 goto illegal_insn;
4284 if (!supervisor(dc))
4285 goto priv_insn;
6ea4a6c8 4286#endif
6ea4a6c8 4287 gen_op_check_align_T0_1();
81ad8ba2 4288 gen_st_asi(insn, 2);
d39c0b99 4289 break;
1a2fb1c0 4290 case 0x17: /* store double word alternate */
3475187d 4291#ifndef TARGET_SPARC64
0f8a249a
BS		 4292 if (IS_IMM)
4293 goto illegal_insn;
4294 if (!supervisor(dc))
4295 goto priv_insn;
3475187d 4296#endif
0f8a249a 4297 if (rd & 1)
d4218d99 4298 goto illegal_insn;
1a2fb1c0 4299 else {
1a2fb1c0 4300 gen_op_check_align_T0_7();
0425bee5 4301 gen_stda_asi(insn, rd);
1a2fb1c0 4302 }
d39c0b99 4303 break;
e80cfcfc 4304#endif
3475187d 4305#ifdef TARGET_SPARC64
0f8a249a 4306 case 0x0e: /* V9 stx */
6ea4a6c8 4307 gen_op_check_align_T0_7();
1a2fb1c0
BS		 4308 ABI32_MASK(cpu_T[0]);
4309 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4310 break;
4311 case 0x1e: /* V9 stxa */
6ea4a6c8 4312 gen_op_check_align_T0_7();
81ad8ba2 4313 gen_st_asi(insn, 8);
0f8a249a 4314 break;
3475187d 4315#endif
0f8a249a
BS		 4316 default:
4317 goto illegal_insn;
4318 }
4319 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 4320 if (gen_trap_ifnofpu(dc))
4321 goto jmp_insn;
0f8a249a
BS		 4322 switch (xop) {
4323 case 0x24:
6ea4a6c8 4324 gen_op_check_align_T0_3();
e8af50a3 4325 gen_op_load_fpr_FT0(rd);
0f8a249a
BS		 4326 gen_op_ldst(stf);
4327 break;
4328 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8
BS		 4329#ifdef CONFIG_USER_ONLY
4330 gen_op_check_align_T0_3();
4331#endif
bb5529bb 4332 tcg_gen_helper_0_0(helper_stfsr);
0f8a249a
BS		 4333 gen_op_ldst(stf);
4334 break;
1f587329
BS		 4335 case 0x26:
4336#ifdef TARGET_SPARC64
4337#if defined(CONFIG_USER_ONLY)
4338 /* V9 stqf, store quad fpreg */
4339 gen_op_check_align_T0_7();
4340 gen_op_load_fpr_QT0(QFPREG(rd));
4341 gen_op_ldst(stqf);
4342 break;
4343#else
4344 goto nfpu_insn;
4345#endif
4346#else /* !TARGET_SPARC64 */
4347 /* stdfq, store floating point queue */
4348#if defined(CONFIG_USER_ONLY)
4349 goto illegal_insn;
4350#else
0f8a249a
BS		 4351 if (!supervisor(dc))
4352 goto priv_insn;
4353 if (gen_trap_ifnofpu(dc))
4354 goto jmp_insn;
4355 goto nfq_insn;
1f587329 4356#endif
0f8a249a
BS		 4357#endif
4358 case 0x27:
6ea4a6c8 4359 gen_op_check_align_T0_7();
3475187d 4360 gen_op_load_fpr_DT0(DFPREG(rd));
0f8a249a
BS		 4361 gen_op_ldst(stdf);
4362 break;
4363 default:
4364 goto illegal_insn;
4365 }
4366 } else if (xop > 0x33 && xop < 0x3f) {
4367 switch (xop) {
a4d17f19 4368#ifdef TARGET_SPARC64
0f8a249a 4369 case 0x34: /* V9 stfa */
6ea4a6c8 4370 gen_op_check_align_T0_3();
3391c818 4371 gen_op_load_fpr_FT0(rd);
2382dc6b 4372 gen_stf_asi(insn, 4, rd);
0f8a249a 4373 break;
1f587329
BS		 4374 case 0x36: /* V9 stqfa */
4375#if defined(CONFIG_USER_ONLY)
4376 gen_op_check_align_T0_7();
4377 gen_op_load_fpr_QT0(QFPREG(rd));
2382dc6b 4378 gen_stf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 4379 break;
4380#else
4381 goto nfpu_insn;
4382#endif
0f8a249a 4383 case 0x37: /* V9 stdfa */
3391c818
BS		 4384 gen_op_check_align_T0_3();
4385 gen_op_load_fpr_DT0(DFPREG(rd));
2382dc6b 4386 gen_stf_asi(insn, 8, DFPREG(rd));
0f8a249a
BS		 4387 break;
4388 case 0x3c: /* V9 casa */
6ea4a6c8 4389 gen_op_check_align_T0_3();
1a2fb1c0 4390 gen_cas_asi(insn, rd);
81ad8ba2 4391 gen_movl_T1_reg(rd);
0f8a249a
BS		 4392 break;
4393 case 0x3e: /* V9 casxa */
6ea4a6c8 4394 gen_op_check_align_T0_7();
1a2fb1c0 4395 gen_casx_asi(insn, rd);
81ad8ba2 4396 gen_movl_T1_reg(rd);
0f8a249a 4397 break;
a4d17f19 4398#else
0f8a249a
BS		 4399 case 0x34: /* stc */
4400 case 0x35: /* stcsr */
4401 case 0x36: /* stdcq */
4402 case 0x37: /* stdc */
4403 goto ncp_insn;
4404#endif
4405 default:
4406 goto illegal_insn;
4407 }
e8af50a3 4408 }
0f8a249a
BS		 4409 else
4410 goto illegal_insn;
4411 }
4412 break;
cf495bcf
FB		 4413 }
4414 /* default case for non jump instructions */
72cbca10 4415 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 4416 dc->pc = DYNAMIC_PC;
4417 gen_op_next_insn();
72cbca10
FB		 4418 } else if (dc->npc == JUMP_PC) {
4419 /* we can do a static jump */
19f329ad 4420 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
72cbca10
FB		 4421 dc->is_br = 1;
4422 } else {
0f8a249a
BS		 4423 dc->pc = dc->npc;
4424 dc->npc = dc->npc + 4;
cf495bcf 4425 }
e80cfcfc 4426 jmp_insn:
cf495bcf
FB		 4427 return;
4428 illegal_insn:
72cbca10 4429 save_state(dc);
cf495bcf
FB		 4430 gen_op_exception(TT_ILL_INSN);
4431 dc->is_br = 1;
e8af50a3 4432 return;
e80cfcfc 4433#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 4434 priv_insn:
4435 save_state(dc);
4436 gen_op_exception(TT_PRIV_INSN);
4437 dc->is_br = 1;
e80cfcfc 4438 return;
e80cfcfc
FB		 4439 nfpu_insn:
4440 save_state(dc);
4441 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4442 dc->is_br = 1;
fcc72045 4443 return;
1f587329 4444#ifndef TARGET_SPARC64
9143e598
BS		 4445 nfq_insn:
4446 save_state(dc);
4447 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4448 dc->is_br = 1;
4449 return;
4450#endif
1f587329 4451#endif
fcc72045
BS		 4452#ifndef TARGET_SPARC64
4453 ncp_insn:
4454 save_state(dc);
4455 gen_op_exception(TT_NCP_INSN);
4456 dc->is_br = 1;
4457 return;
4458#endif
7a3f1944
FB		 4459}
4460
1a2fb1c0
BS		 4461static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4462{
4463}
4464
cf495bcf 4465static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 4466 int spc, CPUSPARCState *env)
7a3f1944 4467{
72cbca10 4468 target_ulong pc_start, last_pc;
cf495bcf
FB		 4469 uint16_t *gen_opc_end;
4470 DisasContext dc1, *dc = &dc1;
e8af50a3 4471 int j, lj = -1;
cf495bcf
FB		 4472
4473 memset(dc, 0, sizeof(DisasContext));
cf495bcf 4474 dc->tb = tb;
72cbca10 4475 pc_start = tb->pc;
cf495bcf 4476 dc->pc = pc_start;
e80cfcfc 4477 last_pc = dc->pc;
72cbca10 4478 dc->npc = (target_ulong) tb->cs_base;
6f27aba6
BS		 4479 dc->mem_idx = cpu_mmu_index(env);
4480 dc->fpu_enabled = cpu_fpu_enabled(env);
cf495bcf 4481 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 4482
1a2fb1c0 4483 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
1a2fb1c0 4484
cf495bcf 4485 do {
e8af50a3
FB		 4486 if (env->nb_breakpoints > 0) {
4487 for(j = 0; j < env->nb_breakpoints; j++) {
4488 if (env->breakpoints[j] == dc->pc) {
0f8a249a
BS		 4489 if (dc->pc != pc_start)
4490 save_state(dc);
1a2fb1c0 4491 tcg_gen_helper_0_0(helper_debug);
57fec1fe 4492 tcg_gen_exit_tb(0);
0f8a249a 4493 dc->is_br = 1;
e80cfcfc 4494 goto exit_gen_loop;
e8af50a3
FB		 4495 }
4496 }
4497 }
4498 if (spc) {
4499 if (loglevel > 0)
4500 fprintf(logfile, "Search PC...\n");
4501 j = gen_opc_ptr - gen_opc_buf;
4502 if (lj < j) {
4503 lj++;
4504 while (lj < j)
4505 gen_opc_instr_start[lj++] = 0;
4506 gen_opc_pc[lj] = dc->pc;
4507 gen_opc_npc[lj] = dc->npc;
4508 gen_opc_instr_start[lj] = 1;
4509 }
4510 }
0f8a249a
BS		 4511 last_pc = dc->pc;
4512 disas_sparc_insn(dc);
4513
4514 if (dc->is_br)
4515 break;
4516 /* if the next PC is different, we abort now */
4517 if (dc->pc != (last_pc + 4))
4518 break;
d39c0b99
FB		 4519 /* if we reach a page boundary, we stop generation so that the
4520 PC of a TT_TFAULT exception is always in the right page */
4521 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4522 break;
e80cfcfc
FB		 4523 /* if single step mode, we generate only one instruction and
4524 generate an exception */
4525 if (env->singlestep_enabled) {
3475187d 4526 gen_jmp_im(dc->pc);
57fec1fe 4527 tcg_gen_exit_tb(0);
e80cfcfc
FB		 4528 break;
4529 }
cf495bcf 4530 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 4531 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 4532
4533 exit_gen_loop:
72cbca10 4534 if (!dc->is_br) {
5fafdf24 4535 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 4536 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4537 /* static PC and NPC: we can use direct chaining */
46525e1f 4538 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 4539 } else {
4540 if (dc->pc != DYNAMIC_PC)
3475187d 4541 gen_jmp_im(dc->pc);
72cbca10 4542 save_npc(dc);
57fec1fe 4543 tcg_gen_exit_tb(0);
72cbca10
FB		 4544 }
4545 }
cf495bcf 4546 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 4547 if (spc) {
4548 j = gen_opc_ptr - gen_opc_buf;
4549 lj++;
4550 while (lj <= j)
4551 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 4552#if 0
4553 if (loglevel > 0) {
4554 page_dump(logfile);
4555 }
4556#endif
c3278b7b
FB		 4557 gen_opc_jump_pc[0] = dc->jump_pc[0];
4558 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 4559 } else {
e80cfcfc 4560 tb->size = last_pc + 4 - pc_start;
e8af50a3 4561 }
7a3f1944 4562#ifdef DEBUG_DISAS
e19e89a5 4563 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 4564 fprintf(logfile, "--------------\n");
4565 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4566 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4567 fprintf(logfile, "\n");
cf495bcf 4568 }
7a3f1944 4569#endif
cf495bcf 4570 return 0;
7a3f1944
FB		 4571}
4572
cf495bcf 4573int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4574{
e8af50a3 4575 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 4576}
4577
cf495bcf 4578int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4579{
e8af50a3 4580 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 4581}
4582
e80cfcfc
FB		 4583void cpu_reset(CPUSPARCState *env)
4584{
bb05683b 4585 tlb_flush(env, 1);
cf495bcf
FB		 4586 env->cwp = 0;
4587 env->wim = 1;
4588 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 4589#if defined(CONFIG_USER_ONLY)
cf495bcf 4590 env->user_mode_only = 1;
5ef54116 4591#ifdef TARGET_SPARC64
6ef905f6
BS		 4592 env->cleanwin = NWINDOWS - 2;
4593 env->cansave = NWINDOWS - 2;
4594 env->pstate = PS_RMO | PS_PEF | PS_IE;
4595 env->asi = 0x82; // Primary no-fault
5ef54116 4596#endif
e8af50a3 4597#else
32af58f9 4598 env->psret = 0;
e8af50a3 4599 env->psrs = 1;
0bee699e 4600 env->psrps = 1;
3475187d 4601#ifdef TARGET_SPARC64
83469015 4602 env->pstate = PS_PRIV;
6f27aba6 4603 env->hpstate = HS_PRIV;
83469015 4604 env->pc = 0x1fff0000000ULL;
375ee38b 4605 env->tsptr = &env->ts[env->tl];
3475187d 4606#else
40ce0a9a 4607 env->pc = 0;
32af58f9 4608 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
6d5f237a 4609 env->mmuregs[0] |= env->mmu_bm;
3475187d 4610#endif
83469015 4611 env->npc = env->pc + 4;
e8af50a3 4612#endif
e80cfcfc
FB		 4613}
4614
aaed909a 4615CPUSPARCState *cpu_sparc_init(const char *cpu_model)
e80cfcfc
FB		 4616{
4617 CPUSPARCState *env;
aaed909a 4618 const sparc_def_t *def;
1a2fb1c0 4619 static int inited;
f5069b26
BS		 4620 unsigned int i;
4621 static const char * const gregnames[8] = {
4622 NULL, // g0 not used
4623 "g1",
4624 "g2",
4625 "g3",
4626 "g4",
4627 "g5",
4628 "g6",
4629 "g7",
4630 };
aaed909a
FB		 4631
4632 def = cpu_sparc_find_by_name(cpu_model);
4633 if (!def)
4634 return NULL;
e80cfcfc 4635
c68ea704
FB		 4636 env = qemu_mallocz(sizeof(CPUSPARCState));
4637 if (!env)
0f8a249a 4638 return NULL;
c68ea704 4639 cpu_exec_init(env);
01ba9816 4640 env->cpu_model_str = cpu_model;
aaed909a
FB		 4641 env->version = def->iu_version;
4642 env->fsr = def->fpu_version;
4643#if !defined(TARGET_SPARC64)
4644 env->mmu_bm = def->mmu_bm;
3deaeab7
BS		 4645 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
4646 env->mmu_cxr_mask = def->mmu_cxr_mask;
4647 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
4648 env->mmu_trcr_mask = def->mmu_trcr_mask;
aaed909a
FB		 4649 env->mmuregs[0] |= def->mmu_version;
4650 cpu_sparc_set_id(env, 0);
4651#endif
1a2fb1c0
BS		 4652
4653 /* init various static tables */
4654 if (!inited) {
4655 inited = 1;
4656
4657 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4658 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
db4a4ea4
BS		 4659 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4660 offsetof(CPUState, regwptr),
4661 "regwptr");
1a2fb1c0
BS		 4662 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4663#ifdef TARGET_SPARC64
4664 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4665 TCG_AREG0, offsetof(CPUState, t0), "T0");
4666 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4667 TCG_AREG0, offsetof(CPUState, t1), "T1");
4668 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4669 TCG_AREG0, offsetof(CPUState, t2), "T2");
dc99a3f2
BS		 4670 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4671 TCG_AREG0, offsetof(CPUState, xcc),
4672 "xcc");
1a2fb1c0
BS		 4673#else
4674 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4675 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4676 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4677#endif
dc99a3f2
BS		 4678 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4679 TCG_AREG0, offsetof(CPUState, cc_src),
4680 "cc_src");
d9bdab86
BS		 4681 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4682 offsetof(CPUState, cc_src2),
4683 "cc_src2");
dc99a3f2
BS		 4684 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4685 TCG_AREG0, offsetof(CPUState, cc_dst),
4686 "cc_dst");
4687 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4688 TCG_AREG0, offsetof(CPUState, psr),
4689 "psr");
87e92502
BS		 4690 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4691 TCG_AREG0, offsetof(CPUState, fsr),
4692 "fsr");
f5069b26
BS		 4693 for (i = 1; i < 8; i++)
4694 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4695 offsetof(CPUState, gregs[i]),
4696 gregnames[i]);
1a2fb1c0
BS		 4697 }
4698
aaed909a
FB		 4699 cpu_reset(env);
4700
4701 return env;
4702}
4703
4704void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
4705{
4706#if !defined(TARGET_SPARC64)
4707 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
4708#endif
7a3f1944
FB		 4709}
4710
62724a37
BS		 4711static const sparc_def_t sparc_defs[] = {
4712#ifdef TARGET_SPARC64
7d77bf20
BS		 4713 {
4714 .name = "Fujitsu Sparc64",
4715 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
4716 | (MAXTL << 8) | (NWINDOWS - 1)),
4717 .fpu_version = 0x00000000,
4718 .mmu_version = 0,
4719 },
4720 {
4721 .name = "Fujitsu Sparc64 III",
4722 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
4723 | (MAXTL << 8) | (NWINDOWS - 1)),
4724 .fpu_version = 0x00000000,
4725 .mmu_version = 0,
4726 },
4727 {
4728 .name = "Fujitsu Sparc64 IV",
4729 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
4730 | (MAXTL << 8) | (NWINDOWS - 1)),
4731 .fpu_version = 0x00000000,
4732 .mmu_version = 0,
4733 },
4734 {
4735 .name = "Fujitsu Sparc64 V",
4736 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
4737 | (MAXTL << 8) | (NWINDOWS - 1)),
4738 .fpu_version = 0x00000000,
4739 .mmu_version = 0,
4740 },
4741 {
4742 .name = "TI UltraSparc I",
4743 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4744 | (MAXTL << 8) | (NWINDOWS - 1)),
4745 .fpu_version = 0x00000000,
4746 .mmu_version = 0,
4747 },
62724a37
BS		 4748 {
4749 .name = "TI UltraSparc II",
7d77bf20
BS		 4750 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
4751 | (MAXTL << 8) | (NWINDOWS - 1)),
4752 .fpu_version = 0x00000000,
4753 .mmu_version = 0,
4754 },
4755 {
4756 .name = "TI UltraSparc IIi",
4757 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
4758 | (MAXTL << 8) | (NWINDOWS - 1)),
4759 .fpu_version = 0x00000000,
4760 .mmu_version = 0,
4761 },
4762 {
4763 .name = "TI UltraSparc IIe",
4764 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
4765 | (MAXTL << 8) | (NWINDOWS - 1)),
4766 .fpu_version = 0x00000000,
4767 .mmu_version = 0,
4768 },
4769 {
4770 .name = "Sun UltraSparc III",
4771 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
4772 | (MAXTL << 8) | (NWINDOWS - 1)),
4773 .fpu_version = 0x00000000,
4774 .mmu_version = 0,
4775 },
4776 {
4777 .name = "Sun UltraSparc III Cu",
4778 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
4779 | (MAXTL << 8) | (NWINDOWS - 1)),
4780 .fpu_version = 0x00000000,
4781 .mmu_version = 0,
4782 },
4783 {
4784 .name = "Sun UltraSparc IIIi",
4785 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
4786 | (MAXTL << 8) | (NWINDOWS - 1)),
4787 .fpu_version = 0x00000000,
4788 .mmu_version = 0,
4789 },
4790 {
4791 .name = "Sun UltraSparc IV",
4792 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
4793 | (MAXTL << 8) | (NWINDOWS - 1)),
4794 .fpu_version = 0x00000000,
4795 .mmu_version = 0,
4796 },
4797 {
4798 .name = "Sun UltraSparc IV+",
4799 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
4800 | (MAXTL << 8) | (NWINDOWS - 1)),
4801 .fpu_version = 0x00000000,
4802 .mmu_version = 0,
4803 },
4804 {
4805 .name = "Sun UltraSparc IIIi+",
4806 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
4807 | (MAXTL << 8) | (NWINDOWS - 1)),
4808 .fpu_version = 0x00000000,
4809 .mmu_version = 0,
4810 },
4811 {
4812 .name = "NEC UltraSparc I",
4813 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
62724a37
BS		 4814 | (MAXTL << 8) | (NWINDOWS - 1)),
4815 .fpu_version = 0x00000000,
4816 .mmu_version = 0,
4817 },
4818#else
406f82e8
BS		 4819 {
4820 .name = "Fujitsu MB86900",
4821 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
4822 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4823 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
4824 .mmu_bm = 0x00004000,
3deaeab7
BS		 4825 .mmu_ctpr_mask = 0x007ffff0,
4826 .mmu_cxr_mask = 0x0000003f,
4827 .mmu_sfsr_mask = 0xffffffff,
4828 .mmu_trcr_mask = 0xffffffff,
406f82e8 4829 },
62724a37
BS		 4830 {
4831 .name = "Fujitsu MB86904",
4832 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
4833 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4834 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
6d5f237a 4835 .mmu_bm = 0x00004000,
3deaeab7
BS		 4836 .mmu_ctpr_mask = 0x00ffffc0,
4837 .mmu_cxr_mask = 0x000000ff,
4838 .mmu_sfsr_mask = 0x00016fff,
4839 .mmu_trcr_mask = 0x00ffffff,
62724a37 4840 },
e0353fe2 4841 {
5ef62c5c
BS		 4842 .name = "Fujitsu MB86907",
4843 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
4844 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4845 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
6d5f237a 4846 .mmu_bm = 0x00004000,
3deaeab7
BS		 4847 .mmu_ctpr_mask = 0xffffffc0,
4848 .mmu_cxr_mask = 0x000000ff,
4849 .mmu_sfsr_mask = 0x00016fff,
4850 .mmu_trcr_mask = 0xffffffff,
5ef62c5c 4851 },
406f82e8
BS		 4852 {
4853 .name = "LSI L64811",
4854 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
4855 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
4856 .mmu_version = 0x10 << 24,
4857 .mmu_bm = 0x00004000,
3deaeab7
BS		 4858 .mmu_ctpr_mask = 0x007ffff0,
4859 .mmu_cxr_mask = 0x0000003f,
4860 .mmu_sfsr_mask = 0xffffffff,
4861 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4862 },
4863 {
4864 .name = "Cypress CY7C601",
4865 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
4866 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4867 .mmu_version = 0x10 << 24,
4868 .mmu_bm = 0x00004000,
3deaeab7
BS		 4869 .mmu_ctpr_mask = 0x007ffff0,
4870 .mmu_cxr_mask = 0x0000003f,
4871 .mmu_sfsr_mask = 0xffffffff,
4872 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4873 },
4874 {
4875 .name = "Cypress CY7C611",
4876 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
4877 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4878 .mmu_version = 0x10 << 24,
4879 .mmu_bm = 0x00004000,
3deaeab7
BS		 4880 .mmu_ctpr_mask = 0x007ffff0,
4881 .mmu_cxr_mask = 0x0000003f,
4882 .mmu_sfsr_mask = 0xffffffff,
4883 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4884 },
4885 {
4886 .name = "TI SuperSparc II",
4887 .iu_version = 0x40000000,
4888 .fpu_version = 0 << 17,
4889 .mmu_version = 0x04000000,
4890 .mmu_bm = 0x00002000,
3deaeab7
BS		 4891 .mmu_ctpr_mask = 0xffffffc0,
4892 .mmu_cxr_mask = 0x0000ffff,
4893 .mmu_sfsr_mask = 0xffffffff,
4894 .mmu_trcr_mask = 0xffffffff,
406f82e8 4895 },
5ef62c5c
BS		 4896 {
4897 .name = "TI MicroSparc I",
4898 .iu_version = 0x41000000,
4899 .fpu_version = 4 << 17,
4900 .mmu_version = 0x41000000,
6d5f237a 4901 .mmu_bm = 0x00004000,
3deaeab7
BS		 4902 .mmu_ctpr_mask = 0x007ffff0,
4903 .mmu_cxr_mask = 0x0000003f,
4904 .mmu_sfsr_mask = 0x00016fff,
4905 .mmu_trcr_mask = 0x0000003f,
5ef62c5c
BS		 4906 },
4907 {
406f82e8
BS		 4908 .name = "TI MicroSparc II",
4909 .iu_version = 0x42000000,
4910 .fpu_version = 4 << 17,
4911 .mmu_version = 0x02000000,
4912 .mmu_bm = 0x00004000,
3deaeab7
BS		 4913 .mmu_ctpr_mask = 0x00ffffc0,
4914 .mmu_cxr_mask = 0x000000ff,
a3ffaf30 4915 .mmu_sfsr_mask = 0x00016fff,
3deaeab7 4916 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4917 },
4918 {
4919 .name = "TI MicroSparc IIep",
4920 .iu_version = 0x42000000,
4921 .fpu_version = 4 << 17,
4922 .mmu_version = 0x04000000,
4923 .mmu_bm = 0x00004000,
3deaeab7
BS		 4924 .mmu_ctpr_mask = 0x00ffffc0,
4925 .mmu_cxr_mask = 0x000000ff,
4926 .mmu_sfsr_mask = 0x00016bff,
4927 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4928 },
4929 {
4930 .name = "TI SuperSparc 51",
4931 .iu_version = 0x43000000,
5ef62c5c
BS		 4932 .fpu_version = 0 << 17,
4933 .mmu_version = 0x04000000,
6d5f237a 4934 .mmu_bm = 0x00002000,
3deaeab7
BS		 4935 .mmu_ctpr_mask = 0xffffffc0,
4936 .mmu_cxr_mask = 0x0000ffff,
4937 .mmu_sfsr_mask = 0xffffffff,
4938 .mmu_trcr_mask = 0xffffffff,
5ef62c5c
BS		 4939 },
4940 {
406f82e8
BS		 4941 .name = "TI SuperSparc 61",
4942 .iu_version = 0x44000000,
4943 .fpu_version = 0 << 17,
4944 .mmu_version = 0x04000000,
4945 .mmu_bm = 0x00002000,
3deaeab7
BS		 4946 .mmu_ctpr_mask = 0xffffffc0,
4947 .mmu_cxr_mask = 0x0000ffff,
4948 .mmu_sfsr_mask = 0xffffffff,
4949 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4950 },
4951 {
4952 .name = "Ross RT625",
5ef62c5c
BS		 4953 .iu_version = 0x1e000000,
4954 .fpu_version = 1 << 17,
406f82e8
BS		 4955 .mmu_version = 0x1e000000,
4956 .mmu_bm = 0x00004000,
3deaeab7
BS		 4957 .mmu_ctpr_mask = 0x007ffff0,
4958 .mmu_cxr_mask = 0x0000003f,
4959 .mmu_sfsr_mask = 0xffffffff,
4960 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4961 },
4962 {
4963 .name = "Ross RT620",
4964 .iu_version = 0x1f000000,
4965 .fpu_version = 1 << 17,
4966 .mmu_version = 0x1f000000,
4967 .mmu_bm = 0x00004000,
3deaeab7
BS		 4968 .mmu_ctpr_mask = 0x007ffff0,
4969 .mmu_cxr_mask = 0x0000003f,
4970 .mmu_sfsr_mask = 0xffffffff,
4971 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4972 },
4973 {
4974 .name = "BIT B5010",
4975 .iu_version = 0x20000000,
4976 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
4977 .mmu_version = 0x20000000,
4978 .mmu_bm = 0x00004000,
3deaeab7
BS		 4979 .mmu_ctpr_mask = 0x007ffff0,
4980 .mmu_cxr_mask = 0x0000003f,
4981 .mmu_sfsr_mask = 0xffffffff,
4982 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4983 },
4984 {
4985 .name = "Matsushita MN10501",
4986 .iu_version = 0x50000000,
4987 .fpu_version = 0 << 17,
4988 .mmu_version = 0x50000000,
4989 .mmu_bm = 0x00004000,
3deaeab7
BS		 4990 .mmu_ctpr_mask = 0x007ffff0,
4991 .mmu_cxr_mask = 0x0000003f,
4992 .mmu_sfsr_mask = 0xffffffff,
4993 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4994 },
4995 {
4996 .name = "Weitek W8601",
4997 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
4998 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
4999 .mmu_version = 0x10 << 24,
5000 .mmu_bm = 0x00004000,
3deaeab7
BS		 5001 .mmu_ctpr_mask = 0x007ffff0,
5002 .mmu_cxr_mask = 0x0000003f,
5003 .mmu_sfsr_mask = 0xffffffff,
5004 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5005 },
5006 {
5007 .name = "LEON2",
5008 .iu_version = 0xf2000000,
5009 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5010 .mmu_version = 0xf2000000,
5011 .mmu_bm = 0x00004000,
3deaeab7
BS		 5012 .mmu_ctpr_mask = 0x007ffff0,
5013 .mmu_cxr_mask = 0x0000003f,
5014 .mmu_sfsr_mask = 0xffffffff,
5015 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5016 },
5017 {
5018 .name = "LEON3",
5019 .iu_version = 0xf3000000,
5020 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5021 .mmu_version = 0xf3000000,
6d5f237a 5022 .mmu_bm = 0x00004000,
3deaeab7
BS		 5023 .mmu_ctpr_mask = 0x007ffff0,
5024 .mmu_cxr_mask = 0x0000003f,
5025 .mmu_sfsr_mask = 0xffffffff,
5026 .mmu_trcr_mask = 0xffffffff,
e0353fe2 5027 },
62724a37
BS		 5028#endif
5029};
5030
aaed909a 5031static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
62724a37 5032{
62724a37
BS		 5033 unsigned int i;
5034
62724a37
BS		 5035 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5036 if (strcasecmp(name, sparc_defs[i].name) == 0) {
aaed909a 5037 return &sparc_defs[i];
62724a37
BS		 5038 }
5039 }
aaed909a 5040 return NULL;
62724a37
BS		 5041}
5042
5043void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5044{
5045 unsigned int i;
5046
5047 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5048 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
5049 sparc_defs[i].name,
5050 sparc_defs[i].iu_version,
5051 sparc_defs[i].fpu_version,
5052 sparc_defs[i].mmu_version);
5053 }
5054}
5055
7a3f1944
FB		 5056#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
5057
5fafdf24 5058void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 5059 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5060 int flags)
7a3f1944 5061{
cf495bcf
FB		 5062 int i, x;
5063
af7bf89b 5064 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 5065 cpu_fprintf(f, "General Registers:\n");
cf495bcf 5066 for (i = 0; i < 4; i++)
0f8a249a 5067 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 5068 cpu_fprintf(f, "\n");
cf495bcf 5069 for (; i < 8; i++)
0f8a249a 5070 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 5071 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf 5072 for (x = 0; x < 3; x++) {
0f8a249a
BS		 5073 for (i = 0; i < 4; i++)
5074 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5075 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
5076 env->regwptr[i + x * 8]);
5077 cpu_fprintf(f, "\n");
5078 for (; i < 8; i++)
5079 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5080 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
5081 env->regwptr[i + x * 8]);
5082 cpu_fprintf(f, "\n");
cf495bcf 5083 }
7fe48483 5084 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 5085 for (i = 0; i < 32; i++) {
5086 if ((i & 3) == 0)
7fe48483
FB		 5087 cpu_fprintf(f, "%%f%02d:", i);
5088 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 5089 if ((i & 3) == 3)
7fe48483 5090 cpu_fprintf(f, "\n");
e8af50a3 5091 }
ded3ab80 5092#ifdef TARGET_SPARC64
3299908c 5093 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
0f8a249a 5094 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80 5095 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
0f8a249a
BS		 5096 env->cansave, env->canrestore, env->otherwin, env->wstate,
5097 env->cleanwin, NWINDOWS - 1 - env->cwp);
ded3ab80 5098#else
7fe48483 5099 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
0f8a249a
BS		 5100 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
5101 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
5102 env->psrs?'S':'-', env->psrps?'P':'-',
5103 env->psret?'E':'-', env->wim);
ded3ab80 5104#endif
3475187d 5105 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 5106}
edfcbd99 5107
e80cfcfc 5108#if defined(CONFIG_USER_ONLY)
9b3c35e0 5109target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 5110{
5111 return addr;
5112}
658138bc 5113
e80cfcfc 5114#else
af7bf89b
FB		 5115extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
5116 int *access_index, target_ulong address, int rw,
6ebbf390 5117 int mmu_idx);
0fa85d43 5118
9b3c35e0 5119target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 5120{
af7bf89b 5121 target_phys_addr_t phys_addr;
e80cfcfc
FB		 5122 int prot, access_index;
5123
9e31b9e2
BS		 5124 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
5125 MMU_KERNEL_IDX) != 0)
5126 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
5127 0, MMU_KERNEL_IDX) != 0)
6b1575b7 5128 return -1;
6c36d3fa
BS		 5129 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
5130 return -1;
e80cfcfc
FB		 5131 return phys_addr;
5132}
5133#endif
5134
658138bc
FB		 5135void helper_flush(target_ulong addr)
5136{
5137 addr &= ~7;
5138 tb_invalidate_page_range(addr, addr + 8);
5139}
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