]> git.proxmox.com Git - mirror_qemu.git/blame - target-tilegx/translate.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-tilegx: Handle mask instructions
[mirror_qemu.git] / target-tilegx / translate.c
CommitLineData
8fd29dd7
RH		 1/*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21#include "cpu.h"
22#include "qemu/log.h"
23#include "disas/disas.h"
24#include "tcg-op.h"
25#include "exec/cpu_ldst.h"
26#include "opcode_tilegx.h"
27
28#define FMT64X "%016" PRIx64
29
30static TCGv_ptr cpu_env;
31static TCGv cpu_pc;
32static TCGv cpu_regs[TILEGX_R_COUNT];
33
34static const char * const reg_names[64] = {
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
39 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
40 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
41 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
42 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
43};
44
45/* Modified registers are cached in temporaries until the end of the bundle. */
46typedef struct {
47 unsigned reg;
48 TCGv val;
49} DisasContextTemp;
50
51#define MAX_WRITEBACK 4
52
53/* This is the state at translation time. */
54typedef struct {
55 uint64_t pc; /* Current pc */
56
57 TCGv zero; /* For zero register */
58
59 DisasContextTemp wb[MAX_WRITEBACK];
60 int num_wb;
61 int mmuidx;
62 bool exit_tb;
63
64 struct {
65 TCGCond cond; /* branch condition */
66 TCGv dest; /* branch destination */
67 TCGv val1; /* value to be compared against zero, for cond */
68 } jmp; /* Jump object, only once in each TB block */
69} DisasContext;
70
71#include "exec/gen-icount.h"
72
73/* Differentiate the various pipe encodings. */
74#define TY_X0 0
75#define TY_X1 1
76#define TY_Y0 2
77#define TY_Y1 3
78
79/* Remerge the base opcode and extension fields for switching.
80 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
81 Y2 opcode field is 2 bits. */
82#define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
83
84/* Similar, but for Y2 only. */
85#define OEY2(OP, MODE) (OP + MODE * 4)
86
87/* Similar, but make sure opcode names match up. */
88#define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
89#define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
90#define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
91#define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
92#define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
93#define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
94#define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
95
96
97static void gen_exception(DisasContext *dc, TileExcp num)
98{
99 TCGv_i32 tmp;
100
101 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
102
103 tmp = tcg_const_i32(num);
104 gen_helper_exception(cpu_env, tmp);
105 tcg_temp_free_i32(tmp);
106 dc->exit_tb = true;
107}
108
a9fdfc7e
RH		 109static bool check_gr(DisasContext *dc, uint8_t reg)
110{
111 if (likely(reg < TILEGX_R_COUNT)) {
112 return true;
113 }
114
115 switch (reg) {
116 case TILEGX_R_SN:
117 case TILEGX_R_ZERO:
118 break;
119 case TILEGX_R_IDN0:
120 case TILEGX_R_IDN1:
121 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
122 break;
123 case TILEGX_R_UDN0:
124 case TILEGX_R_UDN1:
125 case TILEGX_R_UDN2:
126 case TILEGX_R_UDN3:
127 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
128 break;
129 default:
130 g_assert_not_reached();
131 }
132 return false;
133}
134
135static TCGv load_zero(DisasContext *dc)
136{
137 if (TCGV_IS_UNUSED_I64(dc->zero)) {
138 dc->zero = tcg_const_i64(0);
139 }
140 return dc->zero;
141}
142
143static TCGv load_gr(DisasContext *dc, unsigned reg)
144{
145 if (check_gr(dc, reg)) {
146 return cpu_regs[reg];
147 }
148 return load_zero(dc);
149}
150
151static TCGv dest_gr(DisasContext *dc, unsigned reg)
152{
153 int n;
154
155 /* Skip the result, mark the exception if necessary, and continue */
156 check_gr(dc, reg);
157
158 n = dc->num_wb++;
159 dc->wb[n].reg = reg;
160 return dc->wb[n].val = tcg_temp_new_i64();
161}
162
89b8c750
RH		 163static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
164 void (*operate)(TCGv, TCGv, TCGv))
165{
166 TCGv t0 = tcg_temp_new();
167
168 tcg_gen_ext32s_tl(tdest, tsrca);
169 tcg_gen_ext32s_tl(t0, tsrcb);
170 operate(tdest, tdest, t0);
171
172 tcg_gen_movi_tl(t0, 0x7fffffff);
173 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
174 tcg_gen_movi_tl(t0, -0x80000000LL);
175 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
176
177 tcg_temp_free(t0);
178}
179
7f41a8d6
RH		 180/* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
181 specified by the bottom 3 bits of TSRCB, and set TDEST to the
182 low 64 bits of the resulting value. */
183static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
184{
185 TCGv t0 = tcg_temp_new();
186
187 tcg_gen_andi_tl(t0, tsrcb, 7);
188 tcg_gen_shli_tl(t0, t0, 3);
189 tcg_gen_shr_tl(tdest, tsrcd, t0);
190
191 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
192 arithmetic on a 6-bit field tells us that 64 - t0 is equal
193 to (t0 ^ 63) + 1. So we can do the shift in two parts,
194 neither of which will be an invalid shift by 64. */
195 tcg_gen_xori_tl(t0, t0, 63);
196 tcg_gen_shl_tl(t0, tsrca, t0);
197 tcg_gen_shli_tl(t0, t0, 1);
198 tcg_gen_or_tl(tdest, tdest, t0);
199
200 tcg_temp_free(t0);
201}
202
203/* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
204 right shift is an immediate. */
205static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
206{
207 TCGv t0 = tcg_temp_new();
208
209 tcg_gen_shri_tl(t0, tsrcb, shr);
210 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
211 tcg_gen_or_tl(tdest, tdest, t0);
212
213 tcg_temp_free(t0);
214}
215
4ff49775
RH		 216typedef enum {
217 LU, LS, HU, HS
218} MulHalf;
219
220static void gen_ext_half(TCGv d, TCGv s, MulHalf h)
221{
222 switch (h) {
223 case LU:
224 tcg_gen_ext32u_tl(d, s);
225 break;
226 case LS:
227 tcg_gen_ext32s_tl(d, s);
228 break;
229 case HU:
230 tcg_gen_shri_tl(d, s, 32);
231 break;
232 case HS:
233 tcg_gen_sari_tl(d, s, 32);
234 break;
235 }
236}
237
238static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb,
239 MulHalf ha, MulHalf hb)
240{
241 TCGv t = tcg_temp_new();
242 gen_ext_half(t, tsrca, ha);
243 gen_ext_half(tdest, tsrcb, hb);
244 tcg_gen_mul_tl(tdest, tdest, t);
245 tcg_temp_free(t);
246}
247
0426335d
RH		 248static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
249 unsigned srcb, TCGMemOp memop, const char *name)
250{
251 if (dest) {
252 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
253 }
254
255 tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
256 dc->mmuidx, memop);
257
258 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
259 reg_names[srca], reg_names[srcb]);
260 return TILEGX_EXCP_NONE;
261}
7f41a8d6 262
01cd675c
RH		 263static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
264 int imm, TCGMemOp memop, const char *name)
265{
266 TCGv tsrca = load_gr(dc, srca);
267 TCGv tsrcb = load_gr(dc, srcb);
268
269 tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
270 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
271
272 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
273 reg_names[srca], reg_names[srcb], imm);
274 return TILEGX_EXCP_NONE;
275}
276
8fd29dd7
RH		 277static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
278 unsigned dest, unsigned srca)
279{
a9fdfc7e 280 TCGv tdest, tsrca;
8fd29dd7 281 const char *mnemonic;
0426335d 282 TCGMemOp memop;
d5dbd6eb 283 TileExcp ret = TILEGX_EXCP_NONE;
8fd29dd7 284
d5dbd6eb 285 /* Eliminate instructions with no output before doing anything else. */
8fd29dd7
RH		 286 switch (opext) {
287 case OE_RR_Y0(NOP):
288 case OE_RR_Y1(NOP):
289 case OE_RR_X0(NOP):
290 case OE_RR_X1(NOP):
291 mnemonic = "nop";
d5dbd6eb 292 goto done0;
8fd29dd7
RH		 293 case OE_RR_Y0(FNOP):
294 case OE_RR_Y1(FNOP):
295 case OE_RR_X0(FNOP):
296 case OE_RR_X1(FNOP):
297 mnemonic = "fnop";
d5dbd6eb
RH		 298 goto done0;
299 case OE_RR_X1(DRAIN):
300 mnemonic = "drain";
301 goto done0;
302 case OE_RR_X1(FLUSHWB):
303 mnemonic = "flushwb";
304 goto done0;
305 case OE_RR_X1(ILL):
306 case OE_RR_Y1(ILL):
307 mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
308 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
309 return TILEGX_EXCP_OPCODE_UNKNOWN;
310 case OE_RR_X1(MF):
311 mnemonic = "mf";
312 goto done0;
313 case OE_RR_X1(NAP):
314 /* ??? This should yield, especially in system mode. */
315 mnemonic = "nap";
316 goto done0;
317 case OE_RR_X1(SWINT0):
318 case OE_RR_X1(SWINT2):
319 case OE_RR_X1(SWINT3):
320 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
321 case OE_RR_X1(SWINT1):
322 ret = TILEGX_EXCP_SYSCALL;
323 mnemonic = "swint1";
324 done0:
8fd29dd7
RH		 325 if (srca || dest) {
326 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
327 }
328 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
d5dbd6eb 329 return ret;
c230a994 330
d5dbd6eb
RH		 331 case OE_RR_X1(DTLBPR):
332 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
333 case OE_RR_X1(FINV):
334 mnemonic = "finv";
335 goto done1;
336 case OE_RR_X1(FLUSH):
337 mnemonic = "flush";
338 goto done1;
339 case OE_RR_X1(ICOH):
340 mnemonic = "icoh";
341 goto done1;
342 case OE_RR_X1(INV):
343 mnemonic = "inv";
344 goto done1;
345 case OE_RR_X1(WH64):
346 mnemonic = "wh64";
347 goto done1;
c230a994
RH		 348 case OE_RR_X1(JRP):
349 case OE_RR_Y1(JRP):
350 mnemonic = "jrp";
351 goto do_jr;
352 case OE_RR_X1(JR):
353 case OE_RR_Y1(JR):
354 mnemonic = "jr";
355 goto do_jr;
356 case OE_RR_X1(JALRP):
357 case OE_RR_Y1(JALRP):
358 mnemonic = "jalrp";
359 goto do_jalr;
360 case OE_RR_X1(JALR):
361 case OE_RR_Y1(JALR):
362 mnemonic = "jalr";
363 do_jalr:
364 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
365 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
366 do_jr:
367 dc->jmp.cond = TCG_COND_ALWAYS;
368 dc->jmp.dest = tcg_temp_new();
369 tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
d5dbd6eb
RH		 370 done1:
371 if (dest) {
372 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
373 }
c230a994 374 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
d5dbd6eb 375 return ret;
8fd29dd7
RH		 376 }
377
a9fdfc7e
RH		 378 tdest = dest_gr(dc, dest);
379 tsrca = load_gr(dc, srca);
380
8fd29dd7
RH		 381 switch (opext) {
382 case OE_RR_X0(CNTLZ):
383 case OE_RR_Y0(CNTLZ):
7f41a8d6
RH		 384 gen_helper_cntlz(tdest, tsrca);
385 mnemonic = "cntlz";
386 break;
8fd29dd7
RH		 387 case OE_RR_X0(CNTTZ):
388 case OE_RR_Y0(CNTTZ):
7f41a8d6
RH		 389 gen_helper_cnttz(tdest, tsrca);
390 mnemonic = "cnttz";
391 break;
8fd29dd7
RH		 392 case OE_RR_X0(FSINGLE_PACK1):
393 case OE_RR_Y0(FSINGLE_PACK1):
8fd29dd7 394 case OE_RR_X1(IRET):
0426335d 395 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 396 case OE_RR_X1(LD1S):
0426335d
RH		 397 memop = MO_SB;
398 mnemonic = "ld1s";
399 goto do_load;
8fd29dd7 400 case OE_RR_X1(LD1U):
0426335d
RH		 401 memop = MO_UB;
402 mnemonic = "ld1u";
403 goto do_load;
8fd29dd7 404 case OE_RR_X1(LD2S):
0426335d
RH		 405 memop = MO_TESW;
406 mnemonic = "ld2s";
407 goto do_load;
8fd29dd7 408 case OE_RR_X1(LD2U):
0426335d
RH		 409 memop = MO_TEUW;
410 mnemonic = "ld2u";
411 goto do_load;
8fd29dd7 412 case OE_RR_X1(LD4S):
0426335d
RH		 413 memop = MO_TESL;
414 mnemonic = "ld4s";
415 goto do_load;
8fd29dd7 416 case OE_RR_X1(LD4U):
0426335d
RH		 417 memop = MO_TEUL;
418 mnemonic = "ld4u";
419 goto do_load;
8fd29dd7 420 case OE_RR_X1(LDNT1S):
0426335d
RH		 421 memop = MO_SB;
422 mnemonic = "ldnt1s";
423 goto do_load;
8fd29dd7 424 case OE_RR_X1(LDNT1U):
0426335d
RH		 425 memop = MO_UB;
426 mnemonic = "ldnt1u";
427 goto do_load;
8fd29dd7 428 case OE_RR_X1(LDNT2S):
0426335d
RH		 429 memop = MO_TESW;
430 mnemonic = "ldnt2s";
431 goto do_load;
8fd29dd7 432 case OE_RR_X1(LDNT2U):
0426335d
RH		 433 memop = MO_TEUW;
434 mnemonic = "ldnt2u";
435 goto do_load;
8fd29dd7 436 case OE_RR_X1(LDNT4S):
0426335d
RH		 437 memop = MO_TESL;
438 mnemonic = "ldnt4s";
439 goto do_load;
8fd29dd7 440 case OE_RR_X1(LDNT4U):
0426335d
RH		 441 memop = MO_TEUL;
442 mnemonic = "ldnt4u";
443 goto do_load;
8fd29dd7 444 case OE_RR_X1(LDNT):
0426335d
RH		 445 memop = MO_TEQ;
446 mnemonic = "ldnt";
447 goto do_load;
8fd29dd7 448 case OE_RR_X1(LD):
0426335d
RH		 449 memop = MO_TEQ;
450 mnemonic = "ld";
451 do_load:
452 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
453 break;
454 case OE_RR_X1(LDNA):
455 tcg_gen_andi_tl(tdest, tsrca, ~7);
456 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
457 mnemonic = "ldna";
458 break;
8fd29dd7
RH		 459 case OE_RR_X1(LNK):
460 case OE_RR_Y1(LNK):
c230a994
RH		 461 if (srca) {
462 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
463 }
464 tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
465 mnemonic = "lnk";
466 break;
8fd29dd7
RH		 467 case OE_RR_X0(PCNT):
468 case OE_RR_Y0(PCNT):
7f41a8d6
RH		 469 gen_helper_pcnt(tdest, tsrca);
470 mnemonic = "pcnt";
471 break;
8fd29dd7
RH		 472 case OE_RR_X0(REVBITS):
473 case OE_RR_Y0(REVBITS):
7f41a8d6
RH		 474 gen_helper_revbits(tdest, tsrca);
475 mnemonic = "revbits";
476 break;
8fd29dd7
RH		 477 case OE_RR_X0(REVBYTES):
478 case OE_RR_Y0(REVBYTES):
a9fdfc7e
RH		 479 tcg_gen_bswap64_tl(tdest, tsrca);
480 mnemonic = "revbytes";
481 break;
8fd29dd7
RH		 482 case OE_RR_X0(TBLIDXB0):
483 case OE_RR_Y0(TBLIDXB0):
484 case OE_RR_X0(TBLIDXB1):
485 case OE_RR_Y0(TBLIDXB1):
486 case OE_RR_X0(TBLIDXB2):
487 case OE_RR_Y0(TBLIDXB2):
488 case OE_RR_X0(TBLIDXB3):
489 case OE_RR_Y0(TBLIDXB3):
8fd29dd7
RH		 490 default:
491 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
492 }
493
494 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
495 reg_names[dest], reg_names[srca]);
d5dbd6eb 496 return ret;
8fd29dd7
RH		 497}
498
499static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
500 unsigned dest, unsigned srca, unsigned srcb)
501{
a9fdfc7e
RH		 502 TCGv tdest = dest_gr(dc, dest);
503 TCGv tsrca = load_gr(dc, srca);
504 TCGv tsrcb = load_gr(dc, srcb);
2369976d 505 TCGv t0;
8fd29dd7
RH		 506 const char *mnemonic;
507
508 switch (opext) {
509 case OE_RRR(ADDXSC, 0, X0):
510 case OE_RRR(ADDXSC, 0, X1):
89b8c750
RH		 511 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
512 mnemonic = "addxsc";
513 break;
8fd29dd7
RH		 514 case OE_RRR(ADDX, 0, X0):
515 case OE_RRR(ADDX, 0, X1):
516 case OE_RRR(ADDX, 0, Y0):
517 case OE_RRR(ADDX, 0, Y1):
89b8c750
RH		 518 tcg_gen_add_tl(tdest, tsrca, tsrcb);
519 tcg_gen_ext32s_tl(tdest, tdest);
520 mnemonic = "addx";
521 break;
8fd29dd7
RH		 522 case OE_RRR(ADD, 0, X0):
523 case OE_RRR(ADD, 0, X1):
524 case OE_RRR(ADD, 0, Y0):
525 case OE_RRR(ADD, 0, Y1):
89b8c750
RH		 526 tcg_gen_add_tl(tdest, tsrca, tsrcb);
527 mnemonic = "add";
528 break;
8fd29dd7
RH		 529 case OE_RRR(AND, 0, X0):
530 case OE_RRR(AND, 0, X1):
531 case OE_RRR(AND, 5, Y0):
532 case OE_RRR(AND, 5, Y1):
a9fdfc7e
RH		 533 tcg_gen_and_tl(tdest, tsrca, tsrcb);
534 mnemonic = "and";
535 break;
8fd29dd7
RH		 536 case OE_RRR(CMOVEQZ, 0, X0):
537 case OE_RRR(CMOVEQZ, 4, Y0):
f090f9f7
RH		 538 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, load_zero(dc),
539 tsrcb, load_gr(dc, dest));
540 mnemonic = "cmoveqz";
541 break;
8fd29dd7
RH		 542 case OE_RRR(CMOVNEZ, 0, X0):
543 case OE_RRR(CMOVNEZ, 4, Y0):
f090f9f7
RH		 544 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, load_zero(dc),
545 tsrcb, load_gr(dc, dest));
546 mnemonic = "cmovnez";
547 break;
8fd29dd7
RH		 548 case OE_RRR(CMPEQ, 0, X0):
549 case OE_RRR(CMPEQ, 0, X1):
550 case OE_RRR(CMPEQ, 3, Y0):
551 case OE_RRR(CMPEQ, 3, Y1):
73c54377
RH		 552 tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
553 mnemonic = "cmpeq";
554 break;
8fd29dd7
RH		 555 case OE_RRR(CMPEXCH4, 0, X1):
556 case OE_RRR(CMPEXCH, 0, X1):
73c54377 557 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 558 case OE_RRR(CMPLES, 0, X0):
559 case OE_RRR(CMPLES, 0, X1):
560 case OE_RRR(CMPLES, 2, Y0):
561 case OE_RRR(CMPLES, 2, Y1):
73c54377
RH		 562 tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
563 mnemonic = "cmples";
564 break;
8fd29dd7
RH		 565 case OE_RRR(CMPLEU, 0, X0):
566 case OE_RRR(CMPLEU, 0, X1):
567 case OE_RRR(CMPLEU, 2, Y0):
568 case OE_RRR(CMPLEU, 2, Y1):
73c54377
RH		 569 tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
570 mnemonic = "cmpleu";
571 break;
8fd29dd7
RH		 572 case OE_RRR(CMPLTS, 0, X0):
573 case OE_RRR(CMPLTS, 0, X1):
574 case OE_RRR(CMPLTS, 2, Y0):
575 case OE_RRR(CMPLTS, 2, Y1):
73c54377
RH		 576 tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
577 mnemonic = "cmplts";
578 break;
8fd29dd7
RH		 579 case OE_RRR(CMPLTU, 0, X0):
580 case OE_RRR(CMPLTU, 0, X1):
581 case OE_RRR(CMPLTU, 2, Y0):
582 case OE_RRR(CMPLTU, 2, Y1):
73c54377
RH		 583 tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
584 mnemonic = "cmpltu";
585 break;
8fd29dd7
RH		 586 case OE_RRR(CMPNE, 0, X0):
587 case OE_RRR(CMPNE, 0, X1):
588 case OE_RRR(CMPNE, 3, Y0):
589 case OE_RRR(CMPNE, 3, Y1):
73c54377
RH		 590 tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
591 mnemonic = "cmpne";
592 break;
8fd29dd7
RH		 593 case OE_RRR(CMULAF, 0, X0):
594 case OE_RRR(CMULA, 0, X0):
595 case OE_RRR(CMULFR, 0, X0):
596 case OE_RRR(CMULF, 0, X0):
597 case OE_RRR(CMULHR, 0, X0):
598 case OE_RRR(CMULH, 0, X0):
599 case OE_RRR(CMUL, 0, X0):
600 case OE_RRR(CRC32_32, 0, X0):
601 case OE_RRR(CRC32_8, 0, X0):
7f41a8d6 602 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 603 case OE_RRR(DBLALIGN2, 0, X0):
604 case OE_RRR(DBLALIGN2, 0, X1):
7f41a8d6
RH		 605 gen_dblaligni(tdest, tsrca, tsrcb, 16);
606 mnemonic = "dblalign2";
607 break;
8fd29dd7
RH		 608 case OE_RRR(DBLALIGN4, 0, X0):
609 case OE_RRR(DBLALIGN4, 0, X1):
7f41a8d6
RH		 610 gen_dblaligni(tdest, tsrca, tsrcb, 32);
611 mnemonic = "dblalign4";
612 break;
8fd29dd7
RH		 613 case OE_RRR(DBLALIGN6, 0, X0):
614 case OE_RRR(DBLALIGN6, 0, X1):
7f41a8d6
RH		 615 gen_dblaligni(tdest, tsrca, tsrcb, 48);
616 mnemonic = "dblalign6";
617 break;
8fd29dd7 618 case OE_RRR(DBLALIGN, 0, X0):
7f41a8d6
RH		 619 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
620 mnemonic = "dblalign";
621 break;
8fd29dd7
RH		 622 case OE_RRR(EXCH4, 0, X1):
623 case OE_RRR(EXCH, 0, X1):
624 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
625 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
626 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
627 case OE_RRR(FDOUBLE_PACK1, 0, X0):
628 case OE_RRR(FDOUBLE_PACK2, 0, X0):
629 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
630 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
631 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
632 case OE_RRR(FETCHADD4, 0, X1):
633 case OE_RRR(FETCHADDGEZ4, 0, X1):
634 case OE_RRR(FETCHADDGEZ, 0, X1):
635 case OE_RRR(FETCHADD, 0, X1):
636 case OE_RRR(FETCHAND4, 0, X1):
637 case OE_RRR(FETCHAND, 0, X1):
638 case OE_RRR(FETCHOR4, 0, X1):
639 case OE_RRR(FETCHOR, 0, X1):
640 case OE_RRR(FSINGLE_ADD1, 0, X0):
641 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
642 case OE_RRR(FSINGLE_MUL1, 0, X0):
643 case OE_RRR(FSINGLE_MUL2, 0, X0):
644 case OE_RRR(FSINGLE_PACK2, 0, X0):
645 case OE_RRR(FSINGLE_SUB1, 0, X0):
661ff743 646 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 647 case OE_RRR(MNZ, 0, X0):
648 case OE_RRR(MNZ, 0, X1):
649 case OE_RRR(MNZ, 4, Y0):
650 case OE_RRR(MNZ, 4, Y1):
661ff743
RH		 651 t0 = load_zero(dc);
652 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
653 mnemonic = "mnz";
654 break;
8fd29dd7
RH		 655 case OE_RRR(MULAX, 0, X0):
656 case OE_RRR(MULAX, 3, Y0):
4ff49775
RH		 657 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
658 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
659 tcg_gen_ext32s_tl(tdest, tdest);
660 mnemonic = "mulax";
661 break;
8fd29dd7
RH		 662 case OE_RRR(MULA_HS_HS, 0, X0):
663 case OE_RRR(MULA_HS_HS, 9, Y0):
4ff49775
RH		 664 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
665 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
666 mnemonic = "mula_hs_hs";
667 break;
8fd29dd7 668 case OE_RRR(MULA_HS_HU, 0, X0):
4ff49775
RH		 669 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
670 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
671 mnemonic = "mula_hs_hu";
672 break;
8fd29dd7 673 case OE_RRR(MULA_HS_LS, 0, X0):
4ff49775
RH		 674 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
675 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
676 mnemonic = "mula_hs_ls";
677 break;
8fd29dd7 678 case OE_RRR(MULA_HS_LU, 0, X0):
4ff49775
RH		 679 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
680 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
681 mnemonic = "mula_hs_lu";
682 break;
8fd29dd7
RH		 683 case OE_RRR(MULA_HU_HU, 0, X0):
684 case OE_RRR(MULA_HU_HU, 9, Y0):
4ff49775
RH		 685 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
686 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
687 mnemonic = "mula_hu_hu";
688 break;
8fd29dd7 689 case OE_RRR(MULA_HU_LS, 0, X0):
4ff49775
RH		 690 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
691 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
692 mnemonic = "mula_hu_ls";
693 break;
8fd29dd7 694 case OE_RRR(MULA_HU_LU, 0, X0):
4ff49775
RH		 695 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
696 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
697 mnemonic = "mula_hu_lu";
698 break;
8fd29dd7
RH		 699 case OE_RRR(MULA_LS_LS, 0, X0):
700 case OE_RRR(MULA_LS_LS, 9, Y0):
4ff49775
RH		 701 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
702 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
703 mnemonic = "mula_ls_ls";
704 break;
8fd29dd7 705 case OE_RRR(MULA_LS_LU, 0, X0):
4ff49775
RH		 706 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
707 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
708 mnemonic = "mula_ls_lu";
709 break;
8fd29dd7
RH		 710 case OE_RRR(MULA_LU_LU, 0, X0):
711 case OE_RRR(MULA_LU_LU, 9, Y0):
4ff49775
RH		 712 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
713 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
714 mnemonic = "mula_lu_lu";
715 break;
8fd29dd7
RH		 716 case OE_RRR(MULX, 0, X0):
717 case OE_RRR(MULX, 3, Y0):
4ff49775
RH		 718 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
719 tcg_gen_ext32s_tl(tdest, tdest);
720 mnemonic = "mulx";
721 break;
8fd29dd7
RH		 722 case OE_RRR(MUL_HS_HS, 0, X0):
723 case OE_RRR(MUL_HS_HS, 8, Y0):
4ff49775
RH		 724 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
725 mnemonic = "mul_hs_hs";
726 break;
8fd29dd7 727 case OE_RRR(MUL_HS_HU, 0, X0):
4ff49775
RH		 728 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
729 mnemonic = "mul_hs_hu";
730 break;
8fd29dd7 731 case OE_RRR(MUL_HS_LS, 0, X0):
4ff49775
RH		 732 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
733 mnemonic = "mul_hs_ls";
734 break;
8fd29dd7 735 case OE_RRR(MUL_HS_LU, 0, X0):
4ff49775
RH		 736 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
737 mnemonic = "mul_hs_lu";
738 break;
8fd29dd7
RH		 739 case OE_RRR(MUL_HU_HU, 0, X0):
740 case OE_RRR(MUL_HU_HU, 8, Y0):
4ff49775
RH		 741 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
742 mnemonic = "mul_hu_hu";
743 break;
8fd29dd7 744 case OE_RRR(MUL_HU_LS, 0, X0):
4ff49775
RH		 745 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
746 mnemonic = "mul_hu_ls";
747 break;
8fd29dd7 748 case OE_RRR(MUL_HU_LU, 0, X0):
4ff49775
RH		 749 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
750 mnemonic = "mul_hu_lu";
751 break;
8fd29dd7
RH		 752 case OE_RRR(MUL_LS_LS, 0, X0):
753 case OE_RRR(MUL_LS_LS, 8, Y0):
4ff49775
RH		 754 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
755 mnemonic = "mul_ls_ls";
756 break;
8fd29dd7 757 case OE_RRR(MUL_LS_LU, 0, X0):
4ff49775
RH		 758 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
759 mnemonic = "mul_ls_lu";
760 break;
8fd29dd7
RH		 761 case OE_RRR(MUL_LU_LU, 0, X0):
762 case OE_RRR(MUL_LU_LU, 8, Y0):
4ff49775
RH		 763 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
764 mnemonic = "mul_lu_lu";
765 break;
8fd29dd7
RH		 766 case OE_RRR(MZ, 0, X0):
767 case OE_RRR(MZ, 0, X1):
768 case OE_RRR(MZ, 4, Y0):
769 case OE_RRR(MZ, 4, Y1):
661ff743
RH		 770 t0 = load_zero(dc);
771 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
772 mnemonic = "mz";
773 break;
8fd29dd7
RH		 774 case OE_RRR(NOR, 0, X0):
775 case OE_RRR(NOR, 0, X1):
776 case OE_RRR(NOR, 5, Y0):
777 case OE_RRR(NOR, 5, Y1):
a9fdfc7e
RH		 778 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
779 mnemonic = "nor";
780 break;
8fd29dd7
RH		 781 case OE_RRR(OR, 0, X0):
782 case OE_RRR(OR, 0, X1):
783 case OE_RRR(OR, 5, Y0):
784 case OE_RRR(OR, 5, Y1):
a9fdfc7e
RH		 785 tcg_gen_or_tl(tdest, tsrca, tsrcb);
786 mnemonic = "or";
787 break;
8fd29dd7
RH		 788 case OE_RRR(ROTL, 0, X0):
789 case OE_RRR(ROTL, 0, X1):
790 case OE_RRR(ROTL, 6, Y0):
791 case OE_RRR(ROTL, 6, Y1):
2369976d
RH		 792 tcg_gen_andi_tl(tdest, tsrcb, 63);
793 tcg_gen_rotl_tl(tdest, tsrca, tdest);
794 mnemonic = "rotl";
795 break;
8fd29dd7
RH		 796 case OE_RRR(SHL1ADDX, 0, X0):
797 case OE_RRR(SHL1ADDX, 0, X1):
798 case OE_RRR(SHL1ADDX, 7, Y0):
799 case OE_RRR(SHL1ADDX, 7, Y1):
89b8c750
RH		 800 tcg_gen_shli_tl(tdest, tsrca, 1);
801 tcg_gen_add_tl(tdest, tdest, tsrcb);
802 tcg_gen_ext32s_tl(tdest, tdest);
803 mnemonic = "shl1addx";
804 break;
8fd29dd7
RH		 805 case OE_RRR(SHL1ADD, 0, X0):
806 case OE_RRR(SHL1ADD, 0, X1):
807 case OE_RRR(SHL1ADD, 1, Y0):
808 case OE_RRR(SHL1ADD, 1, Y1):
89b8c750
RH		 809 tcg_gen_shli_tl(tdest, tsrca, 1);
810 tcg_gen_add_tl(tdest, tdest, tsrcb);
811 mnemonic = "shl1add";
812 break;
8fd29dd7
RH		 813 case OE_RRR(SHL2ADDX, 0, X0):
814 case OE_RRR(SHL2ADDX, 0, X1):
815 case OE_RRR(SHL2ADDX, 7, Y0):
816 case OE_RRR(SHL2ADDX, 7, Y1):
89b8c750
RH		 817 tcg_gen_shli_tl(tdest, tsrca, 2);
818 tcg_gen_add_tl(tdest, tdest, tsrcb);
819 tcg_gen_ext32s_tl(tdest, tdest);
820 mnemonic = "shl2addx";
821 break;
8fd29dd7
RH		 822 case OE_RRR(SHL2ADD, 0, X0):
823 case OE_RRR(SHL2ADD, 0, X1):
824 case OE_RRR(SHL2ADD, 1, Y0):
825 case OE_RRR(SHL2ADD, 1, Y1):
89b8c750
RH		 826 tcg_gen_shli_tl(tdest, tsrca, 2);
827 tcg_gen_add_tl(tdest, tdest, tsrcb);
828 mnemonic = "shl2add";
829 break;
8fd29dd7
RH		 830 case OE_RRR(SHL3ADDX, 0, X0):
831 case OE_RRR(SHL3ADDX, 0, X1):
832 case OE_RRR(SHL3ADDX, 7, Y0):
833 case OE_RRR(SHL3ADDX, 7, Y1):
89b8c750
RH		 834 tcg_gen_shli_tl(tdest, tsrca, 3);
835 tcg_gen_add_tl(tdest, tdest, tsrcb);
836 tcg_gen_ext32s_tl(tdest, tdest);
837 mnemonic = "shl3addx";
838 break;
8fd29dd7
RH		 839 case OE_RRR(SHL3ADD, 0, X0):
840 case OE_RRR(SHL3ADD, 0, X1):
841 case OE_RRR(SHL3ADD, 1, Y0):
842 case OE_RRR(SHL3ADD, 1, Y1):
89b8c750
RH		 843 tcg_gen_shli_tl(tdest, tsrca, 3);
844 tcg_gen_add_tl(tdest, tdest, tsrcb);
845 mnemonic = "shl3add";
846 break;
8fd29dd7
RH		 847 case OE_RRR(SHLX, 0, X0):
848 case OE_RRR(SHLX, 0, X1):
2369976d
RH		 849 tcg_gen_andi_tl(tdest, tsrcb, 31);
850 tcg_gen_shl_tl(tdest, tsrca, tdest);
851 tcg_gen_ext32s_tl(tdest, tdest);
852 mnemonic = "shlx";
853 break;
8fd29dd7
RH		 854 case OE_RRR(SHL, 0, X0):
855 case OE_RRR(SHL, 0, X1):
856 case OE_RRR(SHL, 6, Y0):
857 case OE_RRR(SHL, 6, Y1):
2369976d
RH		 858 tcg_gen_andi_tl(tdest, tsrcb, 63);
859 tcg_gen_shl_tl(tdest, tsrca, tdest);
860 mnemonic = "shl";
861 break;
8fd29dd7
RH		 862 case OE_RRR(SHRS, 0, X0):
863 case OE_RRR(SHRS, 0, X1):
864 case OE_RRR(SHRS, 6, Y0):
865 case OE_RRR(SHRS, 6, Y1):
2369976d
RH		 866 tcg_gen_andi_tl(tdest, tsrcb, 63);
867 tcg_gen_sar_tl(tdest, tsrca, tdest);
868 mnemonic = "shrs";
869 break;
8fd29dd7
RH		 870 case OE_RRR(SHRUX, 0, X0):
871 case OE_RRR(SHRUX, 0, X1):
2369976d
RH		 872 t0 = tcg_temp_new();
873 tcg_gen_andi_tl(t0, tsrcb, 31);
874 tcg_gen_ext32u_tl(tdest, tsrca);
875 tcg_gen_shr_tl(tdest, tdest, t0);
876 tcg_gen_ext32s_tl(tdest, tdest);
877 tcg_temp_free(t0);
878 mnemonic = "shrux";
879 break;
8fd29dd7
RH		 880 case OE_RRR(SHRU, 0, X0):
881 case OE_RRR(SHRU, 0, X1):
882 case OE_RRR(SHRU, 6, Y0):
883 case OE_RRR(SHRU, 6, Y1):
2369976d
RH		 884 tcg_gen_andi_tl(tdest, tsrcb, 63);
885 tcg_gen_shr_tl(tdest, tsrca, tdest);
886 mnemonic = "shru";
887 break;
8fd29dd7 888 case OE_RRR(SHUFFLEBYTES, 0, X0):
7f41a8d6
RH		 889 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
890 mnemonic = "shufflebytes";
891 break;
8fd29dd7
RH		 892 case OE_RRR(SUBXSC, 0, X0):
893 case OE_RRR(SUBXSC, 0, X1):
89b8c750
RH		 894 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
895 mnemonic = "subxsc";
896 break;
8fd29dd7
RH		 897 case OE_RRR(SUBX, 0, X0):
898 case OE_RRR(SUBX, 0, X1):
899 case OE_RRR(SUBX, 0, Y0):
900 case OE_RRR(SUBX, 0, Y1):
89b8c750
RH		 901 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
902 tcg_gen_ext32s_tl(tdest, tdest);
903 mnemonic = "subx";
904 break;
8fd29dd7
RH		 905 case OE_RRR(SUB, 0, X0):
906 case OE_RRR(SUB, 0, X1):
907 case OE_RRR(SUB, 0, Y0):
908 case OE_RRR(SUB, 0, Y1):
89b8c750
RH		 909 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
910 mnemonic = "sub";
911 break;
8fd29dd7
RH		 912 case OE_RRR(V1ADDUC, 0, X0):
913 case OE_RRR(V1ADDUC, 0, X1):
914 case OE_RRR(V1ADD, 0, X0):
915 case OE_RRR(V1ADD, 0, X1):
916 case OE_RRR(V1ADIFFU, 0, X0):
917 case OE_RRR(V1AVGU, 0, X0):
918 case OE_RRR(V1CMPEQ, 0, X0):
919 case OE_RRR(V1CMPEQ, 0, X1):
920 case OE_RRR(V1CMPLES, 0, X0):
921 case OE_RRR(V1CMPLES, 0, X1):
922 case OE_RRR(V1CMPLEU, 0, X0):
923 case OE_RRR(V1CMPLEU, 0, X1):
924 case OE_RRR(V1CMPLTS, 0, X0):
925 case OE_RRR(V1CMPLTS, 0, X1):
926 case OE_RRR(V1CMPLTU, 0, X0):
927 case OE_RRR(V1CMPLTU, 0, X1):
928 case OE_RRR(V1CMPNE, 0, X0):
929 case OE_RRR(V1CMPNE, 0, X1):
930 case OE_RRR(V1DDOTPUA, 0, X0):
931 case OE_RRR(V1DDOTPUSA, 0, X0):
932 case OE_RRR(V1DDOTPUS, 0, X0):
933 case OE_RRR(V1DDOTPU, 0, X0):
934 case OE_RRR(V1DOTPA, 0, X0):
935 case OE_RRR(V1DOTPUA, 0, X0):
936 case OE_RRR(V1DOTPUSA, 0, X0):
937 case OE_RRR(V1DOTPUS, 0, X0):
938 case OE_RRR(V1DOTPU, 0, X0):
939 case OE_RRR(V1DOTP, 0, X0):
940 case OE_RRR(V1INT_H, 0, X0):
941 case OE_RRR(V1INT_H, 0, X1):
942 case OE_RRR(V1INT_L, 0, X0):
943 case OE_RRR(V1INT_L, 0, X1):
944 case OE_RRR(V1MAXU, 0, X0):
945 case OE_RRR(V1MAXU, 0, X1):
946 case OE_RRR(V1MINU, 0, X0):
947 case OE_RRR(V1MINU, 0, X1):
948 case OE_RRR(V1MNZ, 0, X0):
949 case OE_RRR(V1MNZ, 0, X1):
950 case OE_RRR(V1MULTU, 0, X0):
951 case OE_RRR(V1MULUS, 0, X0):
952 case OE_RRR(V1MULU, 0, X0):
953 case OE_RRR(V1MZ, 0, X0):
954 case OE_RRR(V1MZ, 0, X1):
955 case OE_RRR(V1SADAU, 0, X0):
956 case OE_RRR(V1SADU, 0, X0):
957 case OE_RRR(V1SHL, 0, X0):
958 case OE_RRR(V1SHL, 0, X1):
959 case OE_RRR(V1SHRS, 0, X0):
960 case OE_RRR(V1SHRS, 0, X1):
961 case OE_RRR(V1SHRU, 0, X0):
962 case OE_RRR(V1SHRU, 0, X1):
963 case OE_RRR(V1SUBUC, 0, X0):
964 case OE_RRR(V1SUBUC, 0, X1):
965 case OE_RRR(V1SUB, 0, X0):
966 case OE_RRR(V1SUB, 0, X1):
967 case OE_RRR(V2ADDSC, 0, X0):
968 case OE_RRR(V2ADDSC, 0, X1):
969 case OE_RRR(V2ADD, 0, X0):
970 case OE_RRR(V2ADD, 0, X1):
971 case OE_RRR(V2ADIFFS, 0, X0):
972 case OE_RRR(V2AVGS, 0, X0):
973 case OE_RRR(V2CMPEQ, 0, X0):
974 case OE_RRR(V2CMPEQ, 0, X1):
975 case OE_RRR(V2CMPLES, 0, X0):
976 case OE_RRR(V2CMPLES, 0, X1):
977 case OE_RRR(V2CMPLEU, 0, X0):
978 case OE_RRR(V2CMPLEU, 0, X1):
979 case OE_RRR(V2CMPLTS, 0, X0):
980 case OE_RRR(V2CMPLTS, 0, X1):
981 case OE_RRR(V2CMPLTU, 0, X0):
982 case OE_RRR(V2CMPLTU, 0, X1):
983 case OE_RRR(V2CMPNE, 0, X0):
984 case OE_RRR(V2CMPNE, 0, X1):
985 case OE_RRR(V2DOTPA, 0, X0):
986 case OE_RRR(V2DOTP, 0, X0):
987 case OE_RRR(V2INT_H, 0, X0):
988 case OE_RRR(V2INT_H, 0, X1):
989 case OE_RRR(V2INT_L, 0, X0):
990 case OE_RRR(V2INT_L, 0, X1):
991 case OE_RRR(V2MAXS, 0, X0):
992 case OE_RRR(V2MAXS, 0, X1):
993 case OE_RRR(V2MINS, 0, X0):
994 case OE_RRR(V2MINS, 0, X1):
995 case OE_RRR(V2MNZ, 0, X0):
996 case OE_RRR(V2MNZ, 0, X1):
997 case OE_RRR(V2MULFSC, 0, X0):
998 case OE_RRR(V2MULS, 0, X0):
999 case OE_RRR(V2MULTS, 0, X0):
1000 case OE_RRR(V2MZ, 0, X0):
1001 case OE_RRR(V2MZ, 0, X1):
1002 case OE_RRR(V2PACKH, 0, X0):
1003 case OE_RRR(V2PACKH, 0, X1):
1004 case OE_RRR(V2PACKL, 0, X0):
1005 case OE_RRR(V2PACKL, 0, X1):
1006 case OE_RRR(V2PACKUC, 0, X0):
1007 case OE_RRR(V2PACKUC, 0, X1):
1008 case OE_RRR(V2SADAS, 0, X0):
1009 case OE_RRR(V2SADAU, 0, X0):
1010 case OE_RRR(V2SADS, 0, X0):
1011 case OE_RRR(V2SADU, 0, X0):
1012 case OE_RRR(V2SHLSC, 0, X0):
1013 case OE_RRR(V2SHLSC, 0, X1):
1014 case OE_RRR(V2SHL, 0, X0):
1015 case OE_RRR(V2SHL, 0, X1):
1016 case OE_RRR(V2SHRS, 0, X0):
1017 case OE_RRR(V2SHRS, 0, X1):
1018 case OE_RRR(V2SHRU, 0, X0):
1019 case OE_RRR(V2SHRU, 0, X1):
1020 case OE_RRR(V2SUBSC, 0, X0):
1021 case OE_RRR(V2SUBSC, 0, X1):
1022 case OE_RRR(V2SUB, 0, X0):
1023 case OE_RRR(V2SUB, 0, X1):
1024 case OE_RRR(V4ADDSC, 0, X0):
1025 case OE_RRR(V4ADDSC, 0, X1):
1026 case OE_RRR(V4ADD, 0, X0):
1027 case OE_RRR(V4ADD, 0, X1):
1028 case OE_RRR(V4INT_H, 0, X0):
1029 case OE_RRR(V4INT_H, 0, X1):
1030 case OE_RRR(V4INT_L, 0, X0):
1031 case OE_RRR(V4INT_L, 0, X1):
1032 case OE_RRR(V4PACKSC, 0, X0):
1033 case OE_RRR(V4PACKSC, 0, X1):
1034 case OE_RRR(V4SHLSC, 0, X0):
1035 case OE_RRR(V4SHLSC, 0, X1):
1036 case OE_RRR(V4SHL, 0, X0):
1037 case OE_RRR(V4SHL, 0, X1):
1038 case OE_RRR(V4SHRS, 0, X0):
1039 case OE_RRR(V4SHRS, 0, X1):
1040 case OE_RRR(V4SHRU, 0, X0):
1041 case OE_RRR(V4SHRU, 0, X1):
1042 case OE_RRR(V4SUBSC, 0, X0):
1043 case OE_RRR(V4SUBSC, 0, X1):
1044 case OE_RRR(V4SUB, 0, X0):
1045 case OE_RRR(V4SUB, 0, X1):
a9fdfc7e 1046 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 1047 case OE_RRR(XOR, 0, X0):
1048 case OE_RRR(XOR, 0, X1):
1049 case OE_RRR(XOR, 5, Y0):
1050 case OE_RRR(XOR, 5, Y1):
a9fdfc7e
RH		 1051 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1052 mnemonic = "xor";
1053 break;
8fd29dd7
RH		 1054 default:
1055 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1056 }
1057
1058 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
1059 reg_names[dest], reg_names[srca], reg_names[srcb]);
1060 return TILEGX_EXCP_NONE;
1061}
1062
1063static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
1064 unsigned dest, unsigned srca, int imm)
1065{
a9fdfc7e
RH		 1066 TCGv tdest = dest_gr(dc, dest);
1067 TCGv tsrca = load_gr(dc, srca);
8fd29dd7 1068 const char *mnemonic;
01cd675c 1069 TCGMemOp memop;
8fd29dd7
RH		 1070
1071 switch (opext) {
89b8c750
RH		 1072 case OE(ADDI_OPCODE_Y0, 0, Y0):
1073 case OE(ADDI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 1074 case OE_IM(ADDI, X0):
1075 case OE_IM(ADDI, X1):
89b8c750
RH		 1076 tcg_gen_addi_tl(tdest, tsrca, imm);
1077 mnemonic = "addi";
1078 break;
1079 case OE(ADDXI_OPCODE_Y0, 0, Y0):
1080 case OE(ADDXI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 1081 case OE_IM(ADDXI, X0):
1082 case OE_IM(ADDXI, X1):
89b8c750
RH		 1083 tcg_gen_addi_tl(tdest, tsrca, imm);
1084 tcg_gen_ext32s_tl(tdest, tdest);
1085 mnemonic = "addxi";
1086 break;
a9fdfc7e
RH		 1087 case OE(ANDI_OPCODE_Y0, 0, Y0):
1088 case OE(ANDI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 1089 case OE_IM(ANDI, X0):
1090 case OE_IM(ANDI, X1):
a9fdfc7e
RH		 1091 tcg_gen_andi_tl(tdest, tsrca, imm);
1092 mnemonic = "andi";
1093 break;
73c54377
RH		 1094 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
1095 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 1096 case OE_IM(CMPEQI, X0):
1097 case OE_IM(CMPEQI, X1):
73c54377
RH		 1098 tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
1099 mnemonic = "cmpeqi";
1100 break;
1101 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
1102 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 1103 case OE_IM(CMPLTSI, X0):
1104 case OE_IM(CMPLTSI, X1):
73c54377
RH		 1105 tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
1106 mnemonic = "cmpltsi";
1107 break;
8fd29dd7
RH		 1108 case OE_IM(CMPLTUI, X0):
1109 case OE_IM(CMPLTUI, X1):
73c54377
RH		 1110 tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
1111 mnemonic = "cmpltui";
1112 break;
8fd29dd7 1113 case OE_IM(LD1S_ADD, X1):
01cd675c
RH		 1114 memop = MO_SB;
1115 mnemonic = "ld1s_add";
1116 goto do_load_add;
8fd29dd7 1117 case OE_IM(LD1U_ADD, X1):
01cd675c
RH		 1118 memop = MO_UB;
1119 mnemonic = "ld1u_add";
1120 goto do_load_add;
8fd29dd7 1121 case OE_IM(LD2S_ADD, X1):
01cd675c
RH		 1122 memop = MO_TESW;
1123 mnemonic = "ld2s_add";
1124 goto do_load_add;
8fd29dd7 1125 case OE_IM(LD2U_ADD, X1):
01cd675c
RH		 1126 memop = MO_TEUW;
1127 mnemonic = "ld2u_add";
1128 goto do_load_add;
8fd29dd7 1129 case OE_IM(LD4S_ADD, X1):
01cd675c
RH		 1130 memop = MO_TESL;
1131 mnemonic = "ld4s_add";
1132 goto do_load_add;
8fd29dd7 1133 case OE_IM(LD4U_ADD, X1):
01cd675c
RH		 1134 memop = MO_TEUL;
1135 mnemonic = "ld4u_add";
1136 goto do_load_add;
8fd29dd7 1137 case OE_IM(LDNT1S_ADD, X1):
01cd675c
RH		 1138 memop = MO_SB;
1139 mnemonic = "ldnt1s_add";
1140 goto do_load_add;
8fd29dd7 1141 case OE_IM(LDNT1U_ADD, X1):
01cd675c
RH		 1142 memop = MO_UB;
1143 mnemonic = "ldnt1u_add";
1144 goto do_load_add;
8fd29dd7 1145 case OE_IM(LDNT2S_ADD, X1):
01cd675c
RH		 1146 memop = MO_TESW;
1147 mnemonic = "ldnt2s_add";
1148 goto do_load_add;
8fd29dd7 1149 case OE_IM(LDNT2U_ADD, X1):
01cd675c
RH		 1150 memop = MO_TEUW;
1151 mnemonic = "ldnt2u_add";
1152 goto do_load_add;
8fd29dd7 1153 case OE_IM(LDNT4S_ADD, X1):
01cd675c
RH		 1154 memop = MO_TESL;
1155 mnemonic = "ldnt4s_add";
1156 goto do_load_add;
8fd29dd7 1157 case OE_IM(LDNT4U_ADD, X1):
01cd675c
RH		 1158 memop = MO_TEUL;
1159 mnemonic = "ldnt4u_add";
1160 goto do_load_add;
8fd29dd7 1161 case OE_IM(LDNT_ADD, X1):
01cd675c
RH		 1162 memop = MO_TEQ;
1163 mnemonic = "ldnt_add";
1164 goto do_load_add;
8fd29dd7 1165 case OE_IM(LD_ADD, X1):
01cd675c
RH		 1166 memop = MO_TEQ;
1167 mnemonic = "ldnt_add";
1168 do_load_add:
1169 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
1170 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1171 break;
8fd29dd7 1172 case OE_IM(LDNA_ADD, X1):
01cd675c
RH		 1173 tcg_gen_andi_tl(tdest, tsrca, ~7);
1174 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
1175 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1176 mnemonic = "ldna_add";
1177 break;
8fd29dd7
RH		 1178 case OE_IM(MFSPR, X1):
1179 case OE_IM(MTSPR, X1):
a9fdfc7e 1180 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 1181 case OE_IM(ORI, X0):
1182 case OE_IM(ORI, X1):
a9fdfc7e
RH		 1183 tcg_gen_ori_tl(tdest, tsrca, imm);
1184 mnemonic = "ori";
1185 break;
8fd29dd7
RH		 1186 case OE_IM(V1ADDI, X0):
1187 case OE_IM(V1ADDI, X1):
1188 case OE_IM(V1CMPEQI, X0):
1189 case OE_IM(V1CMPEQI, X1):
1190 case OE_IM(V1CMPLTSI, X0):
1191 case OE_IM(V1CMPLTSI, X1):
1192 case OE_IM(V1CMPLTUI, X0):
1193 case OE_IM(V1CMPLTUI, X1):
1194 case OE_IM(V1MAXUI, X0):
1195 case OE_IM(V1MAXUI, X1):
1196 case OE_IM(V1MINUI, X0):
1197 case OE_IM(V1MINUI, X1):
1198 case OE_IM(V2ADDI, X0):
1199 case OE_IM(V2ADDI, X1):
1200 case OE_IM(V2CMPEQI, X0):
1201 case OE_IM(V2CMPEQI, X1):
1202 case OE_IM(V2CMPLTSI, X0):
1203 case OE_IM(V2CMPLTSI, X1):
1204 case OE_IM(V2CMPLTUI, X0):
1205 case OE_IM(V2CMPLTUI, X1):
1206 case OE_IM(V2MAXSI, X0):
1207 case OE_IM(V2MAXSI, X1):
1208 case OE_IM(V2MINSI, X0):
1209 case OE_IM(V2MINSI, X1):
a9fdfc7e 1210 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 1211 case OE_IM(XORI, X0):
1212 case OE_IM(XORI, X1):
a9fdfc7e
RH		 1213 tcg_gen_xori_tl(tdest, tsrca, imm);
1214 mnemonic = "xori";
1215 break;
8fd29dd7
RH		 1216
1217 case OE_SH(ROTLI, X0):
1218 case OE_SH(ROTLI, X1):
1219 case OE_SH(ROTLI, Y0):
1220 case OE_SH(ROTLI, Y1):
2369976d
RH		 1221 tcg_gen_rotli_tl(tdest, tsrca, imm);
1222 mnemonic = "rotli";
1223 break;
8fd29dd7
RH		 1224 case OE_SH(SHLI, X0):
1225 case OE_SH(SHLI, X1):
1226 case OE_SH(SHLI, Y0):
1227 case OE_SH(SHLI, Y1):
2369976d
RH		 1228 tcg_gen_shli_tl(tdest, tsrca, imm);
1229 mnemonic = "shli";
1230 break;
8fd29dd7
RH		 1231 case OE_SH(SHLXI, X0):
1232 case OE_SH(SHLXI, X1):
2369976d
RH		 1233 tcg_gen_shli_tl(tdest, tsrca, imm & 31);
1234 tcg_gen_ext32s_tl(tdest, tdest);
1235 mnemonic = "shlxi";
1236 break;
8fd29dd7
RH		 1237 case OE_SH(SHRSI, X0):
1238 case OE_SH(SHRSI, X1):
1239 case OE_SH(SHRSI, Y0):
1240 case OE_SH(SHRSI, Y1):
2369976d
RH		 1241 tcg_gen_sari_tl(tdest, tsrca, imm);
1242 mnemonic = "shrsi";
1243 break;
8fd29dd7
RH		 1244 case OE_SH(SHRUI, X0):
1245 case OE_SH(SHRUI, X1):
1246 case OE_SH(SHRUI, Y0):
1247 case OE_SH(SHRUI, Y1):
2369976d
RH		 1248 tcg_gen_shri_tl(tdest, tsrca, imm);
1249 mnemonic = "shrui";
1250 break;
8fd29dd7
RH		 1251 case OE_SH(SHRUXI, X0):
1252 case OE_SH(SHRUXI, X1):
2369976d
RH		 1253 if ((imm & 31) == 0) {
1254 tcg_gen_ext32s_tl(tdest, tsrca);
1255 } else {
1256 tcg_gen_ext32u_tl(tdest, tsrca);
1257 tcg_gen_shri_tl(tdest, tdest, imm & 31);
1258 }
1259 mnemonic = "shlxi";
1260 break;
8fd29dd7
RH		 1261 case OE_SH(V1SHLI, X0):
1262 case OE_SH(V1SHLI, X1):
1263 case OE_SH(V1SHRSI, X0):
1264 case OE_SH(V1SHRSI, X1):
1265 case OE_SH(V1SHRUI, X0):
1266 case OE_SH(V1SHRUI, X1):
1267 case OE_SH(V2SHLI, X0):
1268 case OE_SH(V2SHLI, X1):
1269 case OE_SH(V2SHRSI, X0):
1270 case OE_SH(V2SHRSI, X1):
1271 case OE_SH(V2SHRUI, X0):
1272 case OE_SH(V2SHRUI, X1):
89b8c750 1273 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 1274
8fd29dd7
RH		 1275 case OE(ADDLI_OPCODE_X0, 0, X0):
1276 case OE(ADDLI_OPCODE_X1, 0, X1):
89b8c750
RH		 1277 tcg_gen_addi_tl(tdest, tsrca, imm);
1278 mnemonic = "addli";
1279 break;
8fd29dd7
RH		 1280 case OE(ADDXLI_OPCODE_X0, 0, X0):
1281 case OE(ADDXLI_OPCODE_X1, 0, X1):
89b8c750
RH		 1282 tcg_gen_addi_tl(tdest, tsrca, imm);
1283 tcg_gen_ext32s_tl(tdest, tdest);
1284 mnemonic = "addxli";
1285 break;
8fd29dd7
RH		 1286 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
1287 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
89b8c750
RH		 1288 tcg_gen_shli_tl(tdest, tsrca, 16);
1289 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
1290 mnemonic = "shl16insli";
1291 break;
8fd29dd7
RH		 1292
1293 default:
1294 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1295 }
1296
1297 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
1298 reg_names[dest], reg_names[srca], imm);
1299 return TILEGX_EXCP_NONE;
1300}
1301
1302static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
1303 unsigned dest, unsigned srca,
1304 unsigned bfs, unsigned bfe)
1305{
c06b1817
RH		 1306 TCGv tdest = dest_gr(dc, dest);
1307 TCGv tsrca = load_gr(dc, srca);
1308 TCGv tsrcd;
1309 int len;
8fd29dd7
RH		 1310 const char *mnemonic;
1311
c06b1817
RH		 1312 /* The bitfield is either between E and S inclusive,
1313 or up from S and down from E inclusive. */
1314 if (bfs <= bfe) {
1315 len = bfe - bfs + 1;
1316 } else {
1317 len = (64 - bfs) + (bfe + 1);
1318 }
1319
8fd29dd7
RH		 1320 switch (ext) {
1321 case BFEXTU_BF_OPCODE_X0:
c06b1817
RH		 1322 if (bfs == 0 && bfe == 7) {
1323 tcg_gen_ext8u_tl(tdest, tsrca);
1324 } else if (bfs == 0 && bfe == 15) {
1325 tcg_gen_ext16u_tl(tdest, tsrca);
1326 } else if (bfs == 0 && bfe == 31) {
1327 tcg_gen_ext32u_tl(tdest, tsrca);
1328 } else {
1329 int rol = 63 - bfe;
1330 if (bfs <= bfe) {
1331 tcg_gen_shli_tl(tdest, tsrca, rol);
1332 } else {
1333 tcg_gen_rotli_tl(tdest, tsrca, rol);
1334 }
1335 tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
1336 }
1337 mnemonic = "bfextu";
1338 break;
1339
8fd29dd7 1340 case BFEXTS_BF_OPCODE_X0:
c06b1817
RH		 1341 if (bfs == 0 && bfe == 7) {
1342 tcg_gen_ext8s_tl(tdest, tsrca);
1343 } else if (bfs == 0 && bfe == 15) {
1344 tcg_gen_ext16s_tl(tdest, tsrca);
1345 } else if (bfs == 0 && bfe == 31) {
1346 tcg_gen_ext32s_tl(tdest, tsrca);
1347 } else {
1348 int rol = 63 - bfe;
1349 if (bfs <= bfe) {
1350 tcg_gen_shli_tl(tdest, tsrca, rol);
1351 } else {
1352 tcg_gen_rotli_tl(tdest, tsrca, rol);
1353 }
1354 tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
1355 }
1356 mnemonic = "bfexts";
1357 break;
1358
8fd29dd7 1359 case BFINS_BF_OPCODE_X0:
c06b1817
RH		 1360 tsrcd = load_gr(dc, dest);
1361 if (bfs <= bfe) {
1362 tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
1363 } else {
1364 tcg_gen_rotri_tl(tdest, tsrcd, bfs);
1365 tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
1366 tcg_gen_rotli_tl(tdest, tdest, bfs);
1367 }
1368 mnemonic = "bfins";
1369 break;
1370
8fd29dd7 1371 case MM_BF_OPCODE_X0:
c06b1817
RH		 1372 tsrcd = load_gr(dc, dest);
1373 if (bfs == 0) {
1374 tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
1375 } else {
1376 uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
1377 TCGv tmp = tcg_const_tl(mask);
1378
1379 tcg_gen_and_tl(tdest, tsrcd, tmp);
1380 tcg_gen_andc_tl(tmp, tsrca, tmp);
1381 tcg_gen_or_tl(tdest, tdest, tmp);
1382 tcg_temp_free(tmp);
1383 }
1384 mnemonic = "mm";
1385 break;
1386
8fd29dd7
RH		 1387 default:
1388 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1389 }
1390
1391 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
1392 reg_names[dest], reg_names[srca], bfs, bfe);
1393 return TILEGX_EXCP_NONE;
1394}
1395
1396static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
1397 unsigned srca, int off)
1398{
1399 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1400 const char *mnemonic;
1401
e04e98bf
RH		 1402 dc->jmp.dest = tcg_const_tl(tgt);
1403 dc->jmp.val1 = tcg_temp_new();
1404 tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
1405
1406 /* Note that the "predict taken" opcodes have bit 0 clear.
1407 Therefore, fold the two cases together by setting bit 0. */
1408 switch (ext | 1) {
8fd29dd7 1409 case BEQZ_BRANCH_OPCODE_X1:
e04e98bf
RH		 1410 dc->jmp.cond = TCG_COND_EQ;
1411 mnemonic = "beqz";
1412 break;
8fd29dd7 1413 case BNEZ_BRANCH_OPCODE_X1:
e04e98bf
RH		 1414 dc->jmp.cond = TCG_COND_NE;
1415 mnemonic = "bnez";
1416 break;
8fd29dd7 1417 case BGEZ_BRANCH_OPCODE_X1:
e04e98bf
RH		 1418 dc->jmp.cond = TCG_COND_GE;
1419 mnemonic = "bgez";
1420 break;
8fd29dd7 1421 case BGTZ_BRANCH_OPCODE_X1:
e04e98bf
RH		 1422 dc->jmp.cond = TCG_COND_GT;
1423 mnemonic = "bgtz";
1424 break;
8fd29dd7 1425 case BLEZ_BRANCH_OPCODE_X1:
e04e98bf
RH		 1426 dc->jmp.cond = TCG_COND_LE;
1427 mnemonic = "blez";
1428 break;
8fd29dd7 1429 case BLTZ_BRANCH_OPCODE_X1:
e04e98bf
RH		 1430 dc->jmp.cond = TCG_COND_LT;
1431 mnemonic = "bltz";
1432 break;
1433 case BLBC_BRANCH_OPCODE_X1:
1434 dc->jmp.cond = TCG_COND_EQ;
1435 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1436 mnemonic = "blbc";
1437 break;
1438 case BLBS_BRANCH_OPCODE_X1:
1439 dc->jmp.cond = TCG_COND_NE;
1440 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1441 mnemonic = "blbs";
1442 break;
8fd29dd7
RH		 1443 default:
1444 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1445 }
1446
1447 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
e04e98bf
RH		 1448 qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
1449 mnemonic, ext & 1 ? "" : "t",
1450 reg_names[srca], tgt, lookup_symbol(tgt));
8fd29dd7
RH		 1451 }
1452 return TILEGX_EXCP_NONE;
1453}
1454
c230a994 1455static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
8fd29dd7
RH		 1456{
1457 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
c230a994 1458 const char *mnemonic = "j";
8fd29dd7 1459
c230a994
RH		 1460 /* The extension field is 1 bit, therefore we only have JAL and J. */
1461 if (ext == JAL_JUMP_OPCODE_X1) {
1462 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
1463 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1464 mnemonic = "jal";
8fd29dd7 1465 }
c230a994
RH		 1466 dc->jmp.cond = TCG_COND_ALWAYS;
1467 dc->jmp.dest = tcg_const_tl(tgt);
8fd29dd7
RH		 1468
1469 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1470 qemu_log("%s " TARGET_FMT_lx " <%s>",
1471 mnemonic, tgt, lookup_symbol(tgt));
1472 }
1473 return TILEGX_EXCP_NONE;
1474}
1475
1476static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
1477{
1478 unsigned opc = get_Opcode_Y0(bundle);
1479 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
1480 unsigned dest = get_Dest_Y0(bundle);
1481 unsigned srca = get_SrcA_Y0(bundle);
1482 unsigned srcb;
1483 int imm;
1484
1485 switch (opc) {
1486 case RRR_1_OPCODE_Y0:
1487 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1488 ext = get_UnaryOpcodeExtension_Y0(bundle);
1489 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
1490 }
1491 /* fallthru */
1492 case RRR_0_OPCODE_Y0:
1493 case RRR_2_OPCODE_Y0:
1494 case RRR_3_OPCODE_Y0:
1495 case RRR_4_OPCODE_Y0:
1496 case RRR_5_OPCODE_Y0:
1497 case RRR_6_OPCODE_Y0:
1498 case RRR_7_OPCODE_Y0:
1499 case RRR_8_OPCODE_Y0:
1500 case RRR_9_OPCODE_Y0:
1501 srcb = get_SrcB_Y0(bundle);
1502 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
1503
1504 case SHIFT_OPCODE_Y0:
1505 ext = get_ShiftOpcodeExtension_Y0(bundle);
1506 imm = get_ShAmt_Y0(bundle);
1507 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
1508
1509 case ADDI_OPCODE_Y0:
1510 case ADDXI_OPCODE_Y0:
1511 case ANDI_OPCODE_Y0:
1512 case CMPEQI_OPCODE_Y0:
1513 case CMPLTSI_OPCODE_Y0:
1514 imm = (int8_t)get_Imm8_Y0(bundle);
1515 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
1516
1517 default:
1518 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1519 }
1520}
1521
1522static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
1523{
1524 unsigned opc = get_Opcode_Y1(bundle);
1525 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
1526 unsigned dest = get_Dest_Y1(bundle);
1527 unsigned srca = get_SrcA_Y1(bundle);
1528 unsigned srcb;
1529 int imm;
1530
1531 switch (get_Opcode_Y1(bundle)) {
1532 case RRR_1_OPCODE_Y1:
1533 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1534 ext = get_UnaryOpcodeExtension_Y1(bundle);
1535 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
1536 }
1537 /* fallthru */
1538 case RRR_0_OPCODE_Y1:
1539 case RRR_2_OPCODE_Y1:
1540 case RRR_3_OPCODE_Y1:
1541 case RRR_4_OPCODE_Y1:
1542 case RRR_5_OPCODE_Y1:
1543 case RRR_6_OPCODE_Y1:
1544 case RRR_7_OPCODE_Y1:
1545 srcb = get_SrcB_Y1(bundle);
1546 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
1547
1548 case SHIFT_OPCODE_Y1:
1549 ext = get_ShiftOpcodeExtension_Y1(bundle);
1550 imm = get_ShAmt_Y1(bundle);
1551 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
1552
1553 case ADDI_OPCODE_Y1:
1554 case ADDXI_OPCODE_Y1:
1555 case ANDI_OPCODE_Y1:
1556 case CMPEQI_OPCODE_Y1:
1557 case CMPLTSI_OPCODE_Y1:
1558 imm = (int8_t)get_Imm8_Y1(bundle);
1559 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
1560
1561 default:
1562 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1563 }
1564}
1565
1566static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
1567{
1568 unsigned mode = get_Mode(bundle);
1569 unsigned opc = get_Opcode_Y2(bundle);
1570 unsigned srca = get_SrcA_Y2(bundle);
1571 unsigned srcbdest = get_SrcBDest_Y2(bundle);
1572 const char *mnemonic;
0426335d 1573 TCGMemOp memop;
8fd29dd7
RH		 1574
1575 switch (OEY2(opc, mode)) {
1576 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1577 memop = MO_SB;
1578 mnemonic = "ld1s";
1579 goto do_load;
8fd29dd7 1580 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1581 memop = MO_UB;
1582 mnemonic = "ld1u";
1583 goto do_load;
8fd29dd7 1584 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1585 memop = MO_TESW;
1586 mnemonic = "ld2s";
1587 goto do_load;
8fd29dd7 1588 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1589 memop = MO_TEUW;
1590 mnemonic = "ld2u";
1591 goto do_load;
8fd29dd7 1592 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
0426335d
RH		 1593 memop = MO_TESL;
1594 mnemonic = "ld4s";
1595 goto do_load;
8fd29dd7 1596 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
0426335d
RH		 1597 memop = MO_TEUL;
1598 mnemonic = "ld4u";
1599 goto do_load;
8fd29dd7 1600 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
0426335d
RH		 1601 memop = MO_TEQ;
1602 mnemonic = "ld";
1603 do_load:
1604 tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
1605 dc->mmuidx, memop);
1606 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
1607 reg_names[srcbdest], reg_names[srca]);
1608 return TILEGX_EXCP_NONE;
8fd29dd7
RH		 1609
1610 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1611 return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
8fd29dd7 1612 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1613 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
8fd29dd7 1614 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1615 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
8fd29dd7 1616 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1617 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
8fd29dd7
RH		 1618
1619 default:
1620 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1621 }
8fd29dd7
RH		 1622}
1623
1624static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
1625{
1626 unsigned opc = get_Opcode_X0(bundle);
1627 unsigned dest = get_Dest_X0(bundle);
1628 unsigned srca = get_SrcA_X0(bundle);
1629 unsigned ext, srcb, bfs, bfe;
1630 int imm;
1631
1632 switch (opc) {
1633 case RRR_0_OPCODE_X0:
1634 ext = get_RRROpcodeExtension_X0(bundle);
1635 if (ext == UNARY_RRR_0_OPCODE_X0) {
1636 ext = get_UnaryOpcodeExtension_X0(bundle);
1637 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
1638 }
1639 srcb = get_SrcB_X0(bundle);
1640 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
1641
1642 case SHIFT_OPCODE_X0:
1643 ext = get_ShiftOpcodeExtension_X0(bundle);
1644 imm = get_ShAmt_X0(bundle);
1645 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1646
1647 case IMM8_OPCODE_X0:
1648 ext = get_Imm8OpcodeExtension_X0(bundle);
1649 imm = (int8_t)get_Imm8_X0(bundle);
1650 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1651
1652 case BF_OPCODE_X0:
1653 ext = get_BFOpcodeExtension_X0(bundle);
1654 bfs = get_BFStart_X0(bundle);
1655 bfe = get_BFEnd_X0(bundle);
1656 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
1657
1658 case ADDLI_OPCODE_X0:
1659 case SHL16INSLI_OPCODE_X0:
1660 case ADDXLI_OPCODE_X0:
1661 imm = (int16_t)get_Imm16_X0(bundle);
1662 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
1663
1664 default:
1665 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1666 }
1667}
1668
1669static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
1670{
1671 unsigned opc = get_Opcode_X1(bundle);
1672 unsigned dest = get_Dest_X1(bundle);
1673 unsigned srca = get_SrcA_X1(bundle);
1674 unsigned ext, srcb;
1675 int imm;
1676
1677 switch (opc) {
1678 case RRR_0_OPCODE_X1:
1679 ext = get_RRROpcodeExtension_X1(bundle);
0426335d
RH		 1680 srcb = get_SrcB_X1(bundle);
1681 switch (ext) {
1682 case UNARY_RRR_0_OPCODE_X1:
8fd29dd7
RH		 1683 ext = get_UnaryOpcodeExtension_X1(bundle);
1684 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
0426335d
RH		 1685 case ST1_RRR_0_OPCODE_X1:
1686 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
1687 case ST2_RRR_0_OPCODE_X1:
1688 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
1689 case ST4_RRR_0_OPCODE_X1:
1690 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
1691 case STNT1_RRR_0_OPCODE_X1:
1692 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
1693 case STNT2_RRR_0_OPCODE_X1:
1694 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
1695 case STNT4_RRR_0_OPCODE_X1:
1696 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
1697 case STNT_RRR_0_OPCODE_X1:
1698 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
1699 case ST_RRR_0_OPCODE_X1:
1700 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
8fd29dd7 1701 }
8fd29dd7
RH		 1702 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
1703
1704 case SHIFT_OPCODE_X1:
1705 ext = get_ShiftOpcodeExtension_X1(bundle);
1706 imm = get_ShAmt_X1(bundle);
1707 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1708
1709 case IMM8_OPCODE_X1:
1710 ext = get_Imm8OpcodeExtension_X1(bundle);
01cd675c
RH		 1711 imm = (int8_t)get_Dest_Imm8_X1(bundle);
1712 srcb = get_SrcB_X1(bundle);
1713 switch (ext) {
1714 case ST1_ADD_IMM8_OPCODE_X1:
1715 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add");
1716 case ST2_ADD_IMM8_OPCODE_X1:
1717 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add");
1718 case ST4_ADD_IMM8_OPCODE_X1:
1719 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add");
1720 case STNT1_ADD_IMM8_OPCODE_X1:
1721 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add");
1722 case STNT2_ADD_IMM8_OPCODE_X1:
1723 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add");
1724 case STNT4_ADD_IMM8_OPCODE_X1:
1725 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add");
1726 case STNT_ADD_IMM8_OPCODE_X1:
1727 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
1728 case ST_ADD_IMM8_OPCODE_X1:
1729 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
1730 }
8fd29dd7
RH		 1731 imm = (int8_t)get_Imm8_X1(bundle);
1732 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1733
1734 case BRANCH_OPCODE_X1:
1735 ext = get_BrType_X1(bundle);
1736 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
1737 return gen_branch_opcode_x1(dc, ext, srca, imm);
1738
1739 case JUMP_OPCODE_X1:
1740 ext = get_JumpOpcodeExtension_X1(bundle);
1741 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
1742 return gen_jump_opcode_x1(dc, ext, imm);
1743
1744 case ADDLI_OPCODE_X1:
1745 case SHL16INSLI_OPCODE_X1:
1746 case ADDXLI_OPCODE_X1:
1747 imm = (int16_t)get_Imm16_X1(bundle);
1748 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
1749
1750 default:
1751 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1752 }
1753}
1754
1755static void notice_excp(DisasContext *dc, uint64_t bundle,
1756 const char *type, TileExcp excp)
1757{
1758 if (likely(excp == TILEGX_EXCP_NONE)) {
1759 return;
1760 }
1761 gen_exception(dc, excp);
1762 if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
1763 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
1764 }
1765}
1766
1767static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
1768{
1769 int i;
1770
1771 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
1772 DisasContextTemp *wb = &dc->wb[i];
1773 wb->reg = TILEGX_R_NOREG;
1774 TCGV_UNUSED_I64(wb->val);
1775 }
1776 dc->num_wb = 0;
1777
1778 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1779 tcg_gen_debug_insn_start(dc->pc);
1780 }
1781
1782 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
1783 if (get_Mode(bundle)) {
1784 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
1785 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1786 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
1787 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1788 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
1789 } else {
1790 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
1791 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1792 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
1793 }
1794 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
1795
1796 for (i = dc->num_wb - 1; i >= 0; --i) {
1797 DisasContextTemp *wb = &dc->wb[i];
1798 if (wb->reg < TILEGX_R_COUNT) {
1799 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
1800 }
1801 tcg_temp_free_i64(wb->val);
1802 }
1803
1804 if (dc->jmp.cond != TCG_COND_NEVER) {
1805 if (dc->jmp.cond == TCG_COND_ALWAYS) {
1806 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
1807 } else {
1808 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1809 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
1810 dc->jmp.val1, load_zero(dc),
1811 dc->jmp.dest, next);
1812 tcg_temp_free_i64(dc->jmp.val1);
1813 tcg_temp_free_i64(next);
1814 }
1815 tcg_temp_free_i64(dc->jmp.dest);
1816 tcg_gen_exit_tb(0);
1817 dc->exit_tb = true;
1818 }
1819}
1820
1821static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
1822 TranslationBlock *tb,
1823 bool search_pc)
1824{
1825 DisasContext ctx;
1826 DisasContext *dc = &ctx;
1827 CPUState *cs = CPU(cpu);
1828 CPUTLGState *env = &cpu->env;
1829 uint64_t pc_start = tb->pc;
1830 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1831 int j, lj = -1;
1832 int num_insns = 0;
1833 int max_insns = tb->cflags & CF_COUNT_MASK;
1834
1835 dc->pc = pc_start;
1836 dc->mmuidx = 0;
1837 dc->exit_tb = false;
1838 dc->jmp.cond = TCG_COND_NEVER;
1839 TCGV_UNUSED_I64(dc->jmp.dest);
1840 TCGV_UNUSED_I64(dc->jmp.val1);
8fd29dd7
RH		 1841 TCGV_UNUSED_I64(dc->zero);
1842
1843 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1844 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1845 }
1846 if (!max_insns) {
1847 max_insns = CF_COUNT_MASK;
1848 }
1849 if (cs->singlestep_enabled || singlestep) {
1850 max_insns = 1;
1851 }
1852 gen_tb_start(tb);
1853
1854 while (1) {
1855 if (search_pc) {
1856 j = tcg_op_buf_count();
1857 if (lj < j) {
1858 lj++;
1859 while (lj < j) {
1860 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1861 }
1862 }
1863 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1864 tcg_ctx.gen_opc_instr_start[lj] = 1;
1865 tcg_ctx.gen_opc_icount[lj] = num_insns;
1866 }
1867 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
1868
1869 if (dc->exit_tb) {
1870 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
1871 break;
1872 }
1873 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
1874 if (++num_insns >= max_insns
1875 || dc->pc >= next_page_start
1876 || tcg_op_buf_full()) {
1877 /* Ending the TB due to TB size or page boundary. Set PC. */
1878 tcg_gen_movi_tl(cpu_pc, dc->pc);
1879 tcg_gen_exit_tb(0);
1880 break;
1881 }
1882 }
1883
1884 gen_tb_end(tb, num_insns);
1885 if (search_pc) {
1886 j = tcg_op_buf_count();
1887 lj++;
1888 while (lj <= j) {
1889 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1890 }
1891 } else {
1892 tb->size = dc->pc - pc_start;
1893 tb->icount = num_insns;
1894 }
1895
1896 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1897}
1898
1899void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
1900{
1901 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
1902}
1903
1904void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
1905{
1906 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
1907}
1908
1909void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
1910{
1911 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1912}
1913
1914void tilegx_tcg_init(void)
1915{
1916 int i;
1917
1918 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1919 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
1920 for (i = 0; i < TILEGX_R_COUNT; i++) {
1921 cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
1922 offsetof(CPUTLGState, regs[i]),
1923 reg_names[i]);
1924 }
1925}
QEMU mirror